diff --git a/os/hal/ports/NUMICRO/LLD/CLKv1/driver.mk b/os/hal/ports/NUMICRO/LLD/CLKv1/driver.mk deleted file mode 100644 index 08740e9b..00000000 --- a/os/hal/ports/NUMICRO/LLD/CLKv1/driver.mk +++ /dev/null @@ -1,2 +0,0 @@ -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/CLKv1/hal_clks_lld.c -PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/CLKv1 diff --git a/os/hal/ports/NUMICRO/LLD/CLKv1/hal_clks_lld.c b/os/hal/ports/NUMICRO/LLD/CLKv1/hal_clks_lld.c deleted file mode 100644 index 6f2c4acf..00000000 --- a/os/hal/ports/NUMICRO/LLD/CLKv1/hal_clks_lld.c +++ /dev/null @@ -1,511 +0,0 @@ -/* - Copyright (C) 2019 /u/KeepItUnder - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file CLKv1/hal_clks_lld.c - * @brief CLK subsystem low level driver code. - * - * @addtogroup CLKS - * @{ - */ - -#include "hal.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * WDT_ModuleNum - * ADC_ModuleNum - * SPI0_ModuleNum - * SPI1_ModuleNum - * SPI2_ModuleNum - * TMR0_ModuleNum - * TMR1_ModuleNum - * TMR2_ModuleNum - * TMR3_ModuleNum - * UART0_ModuleNum - * UART1_ModuleNum - * PWM01_ModuleNum - * PWM23_ModuleNum - * I2S_ModuleNum - * FDIV_ModuleNum - * WWDT_ModuleNum - * USBD_ModuleNum - * I2C0_ModuleNum - * I2C1_ModuleNum - * PS2_ModuleNum - * PDMA_ModuleNum - * ISP_ModuleNum - * - */ - -bool clks_module_hxt_source[22] = { 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 }; -bool clks_module_hirc_source[22] = { 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 }; -bool clks_module_lirc_source[22] = { 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0 }; -bool clks_module_hclk_source[22] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 }; -bool clks_module_pll_source[22] = { 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 }; -bool clks_module_ext_source[22] = { 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; -bool clks_module_divider[22] = { 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 }; -uint32_t clks_module_enable[22] = { CLK_APBCLK_WDT_EN_Msk, - CLK_APBCLK_ADC_EN_Msk, - CLK_APBCLK_SPI0_EN_Msk, - CLK_APBCLK_SPI1_EN_Msk, - CLK_APBCLK_SPI2_EN_Msk, - CLK_APBCLK_TMR0_EN_Msk, - CLK_APBCLK_TMR1_EN_Msk, - CLK_APBCLK_TMR2_EN_Msk, - CLK_APBCLK_TMR3_EN_Msk, - CLK_APBCLK_UART0_EN_Msk, - CLK_APBCLK_UART1_EN_Msk, - CLK_APBCLK_PWM01_EN_Msk, - CLK_APBCLK_PWM23_EN_Msk, - CLK_APBCLK_I2S_EN_Msk, - CLK_APBCLK_FDIV_EN_Msk, - 0, - CLK_APBCLK_USBD_EN_Msk, - CLK_APBCLK_I2C0_EN_Msk, - CLK_APBCLK_I2C1_EN_Msk, - CLK_APBCLK_PS2_EN_Msk, - CLK_AHBCLK_PDMA_EN_Msk, - CLK_AHBCLK_ISP_EN_Msk }; -uint32_t clks_module_sel1_mask[22] = { CLK_CLKSEL1_WDT_S_Msk, - CLK_CLKSEL1_ADC_S_Msk, - CLK_CLKSEL1_SPI0_S_Msk, - CLK_CLKSEL1_SPI1_S_Msk, - CLK_CLKSEL1_SPI2_S_Msk, - CLK_CLKSEL1_TMR0_S_Msk, - CLK_CLKSEL1_TMR1_S_Msk, - CLK_CLKSEL1_TMR2_S_Msk, - CLK_CLKSEL1_TMR3_S_Msk, - CLK_CLKSEL1_UART_S_Msk, - CLK_CLKSEL1_UART_S_Msk, - CLK_CLKSEL1_PWM01_S_Msk, - CLK_CLKSEL1_PWM23_S_Msk, - 0, 0, 0, 0, 0, 0, 0, 0, 0 }; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level CLK driver initialization. - * - * @notapi - */ - -/** @brief Set Core Clock - * - * @description Set the core system clock some reference speed (Hz). - * This should be between 25MHz and 72MHz for the NUC123SD4AN0. - * - * Use either the HXT (exact) or HIRC (nearest using 22.1184MHz) - * as the clock source. - * - */ -uint32_t clks_lld_set_core_clock(uint32_t clkCore) -{ - uint32_t stableHIRC; - - /* Read HIRC clock source stable flag */ - stableHIRC = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk; - - /* Setup __HIRC */ - CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk; - - clks_lld_wait_for_clock_ready(CLK_CLKSTATUS_OSC22M_STB_Msk); - - /* Use __HIRC as HCLK temporarily */ - CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_Msk; - CLK->CLKDIV &= (~CLK_CLKDIV_HCLK_N_Msk); - - /* Is HXT stable ? */ - if(CLK->CLKSTATUS & CLK_CLKSTATUS_XTL12M_STB_Msk) { - /* Use __HXT as PLL source */ - clkCore = clks_lld_enable_pll(CLK_PLLCON_PLL_SRC_HXT, (clkCore << 1)); - } else { - /* Use __HIRC as PLL source */ - clkCore = clks_lld_enable_pll(CLK_PLLCON_PLL_SRC_HIRC, (clkCore << 1)); - - /* Read HIRC clock source stable flag again (since we're using it now) */ - stableHIRC = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk; - } - - /* Set HCLK clock source to PLL */ - clks_lld_set_HCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(2)); - - /* Disable HIRC if HIRC was disabled before we started */ - if (stableHIRC == 0) { - CLK->PWRCON &= ~CLK_PWRCON_OSC22M_EN_Msk; - } - - /* Return actual HCLK frequency is PLL frequency divide 2 */ - return (clkCore >> 1); -} - - -/** @brief Set system HCLK - * - * @description Setup HCLK source and divider - * - * Always switch to a known stable clock source before changing a - * system clock, to avoid issues related to the original clock's - * speed/settings. - * - */ -void clks_lld_set_HCLK(uint32_t clkSource, uint32_t clkDivider) -{ - uint32_t stableHIRC; - - /* Read HIRC clock source stable flag */ - stableHIRC = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk; - - /* Setup __HIRC */ - CLK->PWRCON |= CLK_CLKSTATUS_OSC22M_STB_Msk; - - clks_lld_wait_for_clock_ready(CLK_CLKSTATUS_OSC22M_STB_Msk); - - /* Use __HIRC as HCLK, temporarily */ - CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | CLK_CLKSEL0_HCLK_S_HIRC; - - /* Set new clock divider */ - CLK->CLKDIV = (CLK->CLKDIV & (~CLK_CLKDIV_HCLK_N_Msk)) | clkDivider; - - /* Switch HCLK to new HCLK source */ - CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | clkSource; - - /* Update System Core Clock */ - SystemCoreClockUpdate(); - - /* Disable HIRC if HIRC was disabled before we started */ - if (stableHIRC == 0) { - CLK->PWRCON &= ~CLK_CLKSTATUS_OSC22M_STB_Msk; - } -} - - -void clks_lld_set_module_clock(uint32_t module, uint32_t clkSource, uint32_t clkDivider) -{ - /* Set clock source */ - CLK->CLKSEL1 = (CLK->CLKSEL1 & (~(clks_module_sel1_mask[module]))) | clkSource; - - /* Set secondary clock source bit for PWM01/PWM23 */ - if (module == PWM01_ModuleNum) { - CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_PWM01_S_Msk)) | (clkSource & CLK_CLKSEL2_PWM01_S_Msk); - } else if (module == PWM23_ModuleNum) { - CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_PWM23_S_Msk)) | (clkSource & CLK_CLKSEL2_PWM23_S_Msk); - } - - /* Set clock divider */ - if (clks_module_divider[module]) { - switch (module) { - case ADC_ModuleNum: - CLK->CLKDIV = (CLK->CLKDIV & ~CLK_CLKDIV_ADC_N_Msk) | clkDivider; - break; - case UART0_ModuleNum: - case UART1_ModuleNum: - CLK->CLKDIV = (CLK->CLKDIV & ~CLK_CLKDIV_UART_N_Msk) | clkDivider; - break; - case USBD_ModuleNum: - CLK->CLKDIV = (CLK->CLKDIV & ~CLK_CLKDIV_USB_N_Msk) | clkDivider; - break; - default: - break; - } - } -} - - -void clks_lld_enable_ck0(uint32_t clkSource, uint32_t clkDivider) -{ - CLK->FRQDIV = (CLK_FRQDIV_DIVIDER_EN_Msk | clkDivider) ; - - clks_lld_enable_module_clock(FDIV_ModuleNum); - - clks_lld_set_module_clock(FDIV_ModuleNum, clkSource, 0); -} - - -/** - * @brief Enable module clock - * - * @description Module clock enables are all in either AHBCLK or APBCLK - * Register masks are stored in a table to save knowing bit width - * - */ -void clks_lld_enable_module_clock(uint32_t clkModule) { - switch (clkModule) { - case PDMA_ModuleNum: - case ISP_ModuleNum: - /* AHB Clocks */ - CLK->AHBCLK |= clks_module_enable[clkModule]; - break; - case WWDT_ModuleNum: - /* No Module Clock */ - break; - default: - /* APB Clocks */ - CLK->APBCLK |= clks_module_enable[clkModule]; - break; - } -} - - -/** - * @brief Disable module clock - * - * @description Module clock enables are all in either AHBCLK or APBCLK - * Register masks are stored in a table to save knowing bit width - * - */ -void clks_lld_disable_module_clock(uint32_t clkModule) { - switch (clkModule) { - case PDMA_ModuleNum: - case ISP_ModuleNum: - /* AHB Clocks */ - CLK->AHBCLK &= ~clks_module_enable[clkModule]; - break; - case WWDT_ModuleNum: - /* No Module Clock */ - break; - default: - /* APB Clocks */ - CLK->APBCLK &= ~clks_module_enable[clkModule]; - break; - } -} - - -uint32_t clks_lld_enable_pll(uint32_t pllSrc, uint32_t pllFreq) -{ - /* Disable PLL first to avoid unstable when setting PLL. */ - CLK->PLLCON = CLK_PLLCON_PD_Msk; - - /* Check and setup correct clock source */ - switch (pllSrc) { - case CLK_PLLCON_PLL_SRC_HXT: - /* Use HXT clock */ - CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk; - - /* Wait for stable HXT */ - clks_lld_wait_for_clock_ready(CLK_CLKSTATUS_XTL12M_STB_Msk); - - - break; - case CLK_PLLCON_PLL_SRC_HIRC: - /* Use HIRC clock */ - CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk; - - /* Wait for stable HIRC */ - clks_lld_wait_for_clock_ready(CLK_CLKSTATUS_OSC22M_STB_Msk); - - break; - } - - /** - * Calculate best PLL variables from requested frequency - * - * See NUC123 Technical Reference Manual 5.4.8 PLL Control Register Description, page 124 - * - * NF 1 - * FOUT = FIN x -- x -- - * NR NO - * - */ - - uint32_t NO = 0; - uint32_t NR = 0; - uint32_t clkCalc = 0; - - /* Set "NO" for requested frequency */ - /* We're using "NO" first to set the PLLCON - so make it "NO" - 1; */ - if (pllFreq >= FREQ_25MHZ && pllFreq <= FREQ_50MHZ) { - /* Low frequency - use full variable headroom */ - pllFreq <<= 2; - NO = 3; - } else if (pllFreq > FREQ_50MHZ && pllFreq <= FREQ_100MHZ) { - /* Medium frequency - use full variable headroom */ - pllFreq <<= 1; - NO = 1; - } else if (pllFreq > FREQ_100MHZ && pllFreq <= FREQ_200MHZ) { - /* High frequency - full variable headroom already used */ - NO = 0; - } else { - /* Frequency out of range - use default PLL settings - * - * See NUC123 Technical Reference Manual PLL COntrol Register Description, page 124 - * The default value: 0xC22E - * FIN = 12 MHz - * NR = (1+2) = 3 - * NF = (46+2) = 48 - * NO = 4 - * FOUT = 12/4 x 48 x 1/3 = 48 MHz - */ - if (pllSrc == CLK_PLLCON_PLL_SRC_HXT) { - CLK->PLLCON = 0xC22E; - } else { - CLK->PLLCON = 0xD66F; - } - - /* Wait for stable PLL clock */ - clks_lld_wait_for_clock_ready(CLK_CLKSTATUS_PLL_STB_Msk); - - return clks_lld_get_pll_clock_freq(); - } - - /* Setup "NR" and clkCalc */ - switch (pllSrc) { - case CLK_PLLCON_PLL_SRC_HXT: - NR = 2; - clkCalc = __HXT; - break; - case CLK_PLLCON_PLL_SRC_HIRC: - NR = 4; - clkCalc = __HIRC; - break; - } - - /** - * Loop to calculate best/lowest NR (between 0 or 2 and 31) and best/lowest NF (between 0 and 511) - * - * Best results are off-by-2 until final equation calculation (to allow use in PLLCON) - * - */ - uint32_t bestNR = 0; - uint32_t bestNF = 0; - uint32_t minLimit = -1; - - while (NR <= 33) { - uint32_t tmpCalc1 = clkCalc / NR; - - if (tmpCalc1 > 1600000 && tmpCalc1 < 16000000) { - uint32_t NF = 2; - - while (NF <= 513) { - uint32_t tmpCalc2 = tmpCalc1 * NF; - - if (tmpCalc2 >= 100000000 && tmpCalc2 <= 200000000) { - uint32_t tmpCalc3; - - if (tmpCalc2 > pllFreq) { - tmpCalc3 = tmpCalc2 - pllFreq; - } else { - tmpCalc3 = pllFreq - tmpCalc2; - } - - if (tmpCalc3 < minLimit) { - minLimit = tmpCalc3; - bestNF = NF; - bestNR = NR; - - /* Stop NF calc loop when minLimit tends back to 0 */ - if(minLimit == 0) - break; - } - } - - NF++; - } - } - - NR++; - } - - /* Enable and apply new PLL setting. */ - CLK->PLLCON = pllSrc | (NO << 14) | ((bestNR - 2) << 9) | (bestNF - 2); - - /* Wait for stable PLL clock */ - clks_lld_wait_for_clock_ready(CLK_CLKSTATUS_PLL_STB_Msk); - - /* Return equation result */ - return (clkCalc / ((NO + 1) * bestNR) * bestNF); -} - - -/** - * @brief Wait for stable clock - * - * @description Always wait around 300ms for clock to be stable - * - */ -uint32_t clks_lld_wait_for_clock_ready(uint32_t clkMask) -{ - int32_t timeout = 2180000; - - while (timeout-- > 0) { - if ((CLK->CLKSTATUS & clkMask) == clkMask) { - return 1; - } - } - - return 0; -} - - -void clks_lld_enable_SysTick(uint32_t clkSrc, uint32_t count) { - - // Disable the counter - clks_lld_disable_SysTick(); - - // Clear current values/flags - SysTick->VAL = 0; - - // Set SysTick Clock Source - switch (clkSrc) { - case CLK_CLKSEL0_STCLK_S_HCLK: - SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk; - break; - default: - CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLK_S_Msk) | clkSrc; - // CLK->CLKSEL0 |= SysTick_CTRL_CLKSOURCE_Msk; - break; - } - - // Set reload value - SysTick->LOAD = count; - - // Enable Interrupt and Counter - SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; -} - - -void clks_lld_disable_SysTick(void) { - /* Disable System Tick counter */ - SysTick->CTRL = 0; -} - -/** @} */ diff --git a/os/hal/ports/NUMICRO/LLD/CLKv1/hal_clks_lld.h b/os/hal/ports/NUMICRO/LLD/CLKv1/hal_clks_lld.h deleted file mode 100644 index 62859d6f..00000000 --- a/os/hal/ports/NUMICRO/LLD/CLKv1/hal_clks_lld.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - Copyright (C) 2019 /u/KeepItUnder - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_clks_lld.h - * @brief Clock/Timer subsystem low level header. - * - * @addtogroup CLKS - * @{ - */ - -#ifndef HAL_CLKS_LLD_H -#define HAL_CLKS_LLD_H - -// #if HAL_USE_CLKS || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define FREQ_25MHZ 25000000 -#define FREQ_50MHZ 50000000 -#define FREQ_72MHZ 72000000 -#define FREQ_100MHZ 100000000 -#define FREQ_200MHZ 200000000 - -/*---------------------------------------------------------------------------------------------------------*/ -/* CLKSEL0 */ -/*---------------------------------------------------------------------------------------------------------*/ -#define CLK_CLKSEL0_HCLK_S_HXT (0x0ul<PLLCON; - - if(PllReg & (CLK_PLLCON_PD_Msk | CLK_PLLCON_OE_Msk)) { - PllClock = 0; /* PLL is in power down mode or fix low */ - } else { - - if (PllReg & CLK_PLLCON_PLL_SRC_HIRC) { - pllFIN = __HIRC; /* Use HXT for PLL clock */ - } else { - pllFIN = __HXT; /* Use HXT for PLL clock */ - } - - if (PllReg & CLK_PLLCON_BP_Msk) { - PllClock = pllFIN; - } else { - switch (((PllReg & CLK_PLLCON_OUT_DV_Msk) >> CLK_PLLCON_OUT_DV_Pos)) { - case 0b00: // OUT_DIV == 00 : NO = 1 - pllNO = 1; - break; - case 0b11: // OUT_DIV == 11 : NO = 4 - pllNO = 4; - break; - default: // OUT_DIV == 01 or 10 : NO = 2 - pllNO = 2; - break; - } - - pllNF = ((PllReg & CLK_PLLCON_FB_DV_Msk) >> CLK_PLLCON_FB_DV_Pos) + 2; - pllNR = ((PllReg & CLK_PLLCON_IN_DV_Msk) >> CLK_PLLCON_IN_DV_Pos) + 2; - - /* shift to avoid overflow condition */ - PllClock = (((pllFIN >> 2) * pllNF) / (pllNR * pllNO) << 2); - } - } - - return PllClock; - } - - uint32_t clks_lld_set_core_clock(uint32_t clkCore); - void clks_lld_set_HCLK(uint32_t clkSource, uint32_t clkDivider); - void clks_lld_set_module_clock(uint32_t module, uint32_t clkSource, uint32_t clkDivider); - void clks_lld_enable_ck0(uint32_t clkSource, uint32_t clkDivider); - void clks_lld_enable_module_clock(uint32_t moduleIdx); - void clks_lld_disable_module_clock(uint32_t moduleIdx); - uint32_t clks_lld_enable_pll(uint32_t pllSrc, uint32_t pllFreq); - uint32_t clks_lld_wait_for_clock_ready(uint32_t clkMask); - void clks_lld_enable_SysTick(uint32_t clkSource, uint32_t count); - void clks_lld_disable_SysTick(void); - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_CLK_LLD_H */ - -/** @} */ diff --git a/os/hal/ports/NUMICRO/LLD/GPIOv1/driver.mk b/os/hal/ports/NUMICRO/LLD/GPIOv1/driver.mk index 138ea830..2c0b04be 100644 --- a/os/hal/ports/NUMICRO/LLD/GPIOv1/driver.mk +++ b/os/hal/ports/NUMICRO/LLD/GPIOv1/driver.mk @@ -1,10 +1,10 @@ -# PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/GPIOv1/gpio.c +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/GPIOv1 -ifeq ($(USE_SMART_BUILD),yes) -ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c -endif -else -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c -endif +# ifeq ($(USE_SMART_BUILD),yes) +# ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) +# PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c +# endif +# else +# PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c +# endif diff --git a/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c b/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c index f4e493ec..e76efedd 100644 --- a/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c +++ b/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c @@ -143,7 +143,7 @@ void _pal_lld_init(const PALConfig *config) { GPIOF->DOUT = config->PFData.DOUT; /* Set DeBounce conditions */ - GPIO_DBNCE->DBNCECON = 0x04u; + GPIO->DBNCECON = 0x04u; /* Enable External Crystal Oscillator pins */ SYS->GPF_MFP |= SYS_GPF_MFP_PF0_XT1_OUT | SYS_GPF_MFP_PF1_XT1_IN; diff --git a/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.h b/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.h index bdff726b..10091cfb 100644 --- a/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.h +++ b/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.h @@ -214,11 +214,11 @@ #define SYS_ALT_MFP1_PB0_GPIO NULL /* UART0 RXD */ -#define SYS_GPB_MFP_PB0_UART0_RXD (0x01ul<LOAD = (NUC123_HCLK / OSAL_ST_FREQUENCY) - 1; + SystemUnlockReg(); + CLK->CLKSEL0 &= ~CLK_CLKSEL0_STCLK_S_Msk; + CLK->CLKSEL0 |= CLK_CLKSEL0_STCLK_S_HCLK_DIV2; + LOCKREG(); + + SysTick->LOAD = ((NUC123_HCLK / 2) / OSAL_ST_FREQUENCY) - 1; SysTick->VAL = 0; SysTick->CTRL = (~SysTick_CTRL_CLKSOURCE_Msk) & (SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk); diff --git a/os/hal/ports/NUMICRO/LLD/TIMv1/hal_st_lld.h b/os/hal/ports/NUMICRO/LLD/TIMv1/hal_st_lld.h index a29efd46..f9191fb4 100644 --- a/os/hal/ports/NUMICRO/LLD/TIMv1/hal_st_lld.h +++ b/os/hal/ports/NUMICRO/LLD/TIMv1/hal_st_lld.h @@ -42,7 +42,6 @@ #define CLK_CLKSEL0_STCLK_S_HXT_DIV2 (0x2ul<PLLCON; + + if (PllReg & (CLK_PLLCON_PD_Msk | CLK_PLLCON_OE_Msk)) { + PllClock = 0; /* PLL is off. */ + } else { + + if (PllReg & 0x00080000ul) { + pllFIN = __HIRC; /* Use HXT for PLL clock */ + } else { + pllFIN = __HXT; /* Use HXT for PLL clock */ + } + + if (PllReg & CLK_PLLCON_BP_Msk) { + PllClock = pllFIN; + } else { + switch (((PllReg & CLK_PLLCON_OUT_DV_Msk) >> CLK_PLLCON_OUT_DV_Pos)) { + case 0: /* OUT_DIV == 00 : NO = 1 */ + pllNO = 1; + break; + case 3: /* OUT_DIV == 11 : NO = 4 */ + pllNO = 4; + break; + default: /* OUT_DIV == 01 or 10 : NO = 2 */ + pllNO = 2; + break; + } + + pllNF = ((PllReg & CLK_PLLCON_FB_DV_Msk) >> CLK_PLLCON_FB_DV_Pos) + 2; + pllNR = ((PllReg & CLK_PLLCON_IN_DV_Msk) >> CLK_PLLCON_IN_DV_Pos) + 2; + + /* Shift right to avoid overflow condition */ + PllClock = (((pllFIN >> 2) * pllNF) / (pllNR * pllNO) << 2); + } + } + + /* Pick Clock Source */ + switch (CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk) { + case 0: // External HF Xtal + clkFreq = __HXT; + break; + case 1: // PLL clock / 2 + clkFreq = PllClock >> 1; + break; + case 3: // Internal 10kHz + clkFreq = __LIRC; + break; + case 2: // PLL clock + clkFreq = PllClock; + break; + case 7: // Internal 22.184MHz + clkFreq = __HIRC; + break; + default: + clkFreq = 0; + break; + } + + SystemCoreClock = clkFreq / ((CLK->CLKDIV & CLK_CLKDIV_HCLK_N_Msk) + 1); + CyclesPerUs = SystemCoreClock / 1000000; +} + +/** + * @brief Get PLL clock frequency + * @param None + * @return PLL frequency + * @details This function get PLL frequency. The frequency unit is Hz. + */ +static inline uint32_t get_pll_clock_freq(void) +{ + uint32_t PllReg; + uint32_t pllFIN, pllNF, pllNR, pllNO; + + PllReg = CLK->PLLCON; + + if (PllReg & (CLK_PLLCON_PD_Msk | CLK_PLLCON_OE_Msk)) { + PllClock = 0; /* PLL is in power down mode or fix low */ + } else { + + if (PllReg & NUC123_PLLSRC_HSI) { + pllFIN = __HIRC; /* Use HXT for PLL clock */ + } else { + pllFIN = __HXT; /* Use HXT for PLL clock */ + } + + if (PllReg & CLK_PLLCON_BP_Msk) { + PllClock = pllFIN; + } else { + switch (((PllReg & CLK_PLLCON_OUT_DV_Msk) >> CLK_PLLCON_OUT_DV_Pos)) { + case 0: // OUT_DIV == 00 : NO = 1 + pllNO = 1; + break; + case 3: // OUT_DIV == 11 : NO = 4 + pllNO = 4; + break; + default: // OUT_DIV == 01 or 10 : NO = 2 + pllNO = 2; + break; + } + + pllNF = ((PllReg & CLK_PLLCON_FB_DV_Msk) >> CLK_PLLCON_FB_DV_Pos) + 2; + pllNR = ((PllReg & CLK_PLLCON_IN_DV_Msk) >> CLK_PLLCON_IN_DV_Pos) + 2; + + /* shift to avoid overflow condition */ + PllClock = (((pllFIN >> 2) * pllNF) / (pllNR * pllNO) << 2); + } + } + + return PllClock; +} + +/** + * @brief Wait for stable clock + * + * @description Always wait around 300ms for clock to be stable + * + */ +static uint32_t wait_for_clock_ready(uint32_t clkMask) +{ + int32_t timeout = 2180000; + + while (timeout-- > 0) { + if ((CLK->CLKSTATUS & clkMask) == clkMask) { + return 1; + } + } + + return 0; +} + +/** @brief Set system HCLK + * + * @description Setup HCLK source and divider + * + * Always switch to a known stable clock source before changing a + * system clock, to avoid issues related to the original clock's + * speed/settings. + * + */ +static void set_HCLK(uint32_t clkSource, uint32_t clkDivider) +{ + uint32_t stableHIRC; + + /* Read HIRC clock source stable flag */ + stableHIRC = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk; + + /* Setup __HIRC */ + CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk; + + wait_for_clock_ready(CLK_CLKSTATUS_OSC22M_STB_Msk); + + /* Use __HIRC as HCLK, temporarily */ + CLK->CLKSEL0 = + (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | NUC123_HCLKSRC_HSI; + + /* Set new clock divider */ + CLK->CLKDIV = (CLK->CLKDIV & (~CLK_CLKDIV_HCLK_N_Msk)) | clkDivider; + + /* Switch HCLK to new HCLK source */ + CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | clkSource; + + /* Update System Core Clock */ + SystemCoreClockUpdate(); + + /* Disable HIRC if HIRC was disabled before we started */ + if (stableHIRC == 0) { + CLK->PWRCON &= ~CLK_PWRCON_OSC22M_EN_Msk; + } +} + +static uint32_t enable_pll(uint32_t pllSrc, uint32_t pllFreq) +{ + /* Disable PLL first to avoid unstable when setting PLL. */ + CLK->PLLCON = CLK_PLLCON_PD_Msk; + + /* Check and setup correct clock source */ + switch (pllSrc) { + case NUC123_PLLSRC_HSE: + /* Use HXT clock */ + CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk; + + /* Wait for stable HXT */ + wait_for_clock_ready(CLK_CLKSTATUS_XTL12M_STB_Msk); + + break; + case NUC123_PLLSRC_HSI: + /* Use HIRC clock */ + CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk; + + /* Wait for stable HIRC */ + wait_for_clock_ready(CLK_CLKSTATUS_OSC22M_STB_Msk); + + break; + } + + /** + * Calculate best PLL variables from requested frequency + * + * See NUC123 Technical Reference Manual 5.4.8 PLL Control Register Description, page 124 + * + * NF 1 + * FOUT = FIN x -- x -- + * NR NO + * + */ + + uint32_t NO = 0; + uint32_t NR = 0; + uint32_t clkCalc = 0; + + /* Set "NO" for requested frequency */ + /* We're using "NO" first to set the PLLCON - so make it "NO" - 1; */ + if (pllFreq >= FREQ_25MHZ && pllFreq <= FREQ_50MHZ) { + /* Low frequency - use full variable headroom */ + pllFreq <<= 2; + NO = 3; + } else if (pllFreq > FREQ_50MHZ && pllFreq <= FREQ_100MHZ) { + /* Medium frequency - use full variable headroom */ + pllFreq <<= 1; + NO = 1; + } else if (pllFreq > FREQ_100MHZ && pllFreq <= FREQ_200MHZ) { + /* High frequency - full variable headroom already used */ + NO = 0; + } else { + /* Frequency out of range - use default PLL settings + * + * See NUC123 Technical Reference Manual PLL COntrol Register Description, page 124 + * The default value: 0xC22E + * FIN = 12 MHz + * NR = (1+2) = 3 + * NF = (46+2) = 48 + * NO = 4 + * FOUT = 12/4 x 48 x 1/3 = 48 MHz + */ + if (pllSrc == NUC123_PLLSRC_HSE) { + CLK->PLLCON = 0xC22E; + } else { + CLK->PLLCON = 0xD66F; + } + + /* Wait for stable PLL clock */ + wait_for_clock_ready(CLK_CLKSTATUS_PLL_STB_Msk); + + return get_pll_clock_freq(); + } + + /* Setup "NR" and clkCalc */ + switch (pllSrc) { + case NUC123_PLLSRC_HSE: + NR = 2; + clkCalc = __HXT; + break; + case NUC123_PLLSRC_HSI: + NR = 4; + clkCalc = __HIRC; + break; + } + + /** + * Loop to calculate best/lowest NR (between 0 or 2 and 31) and best/lowest NF (between 0 and 511) + * + * Best results are off-by-2 until final equation calculation (to allow use in PLLCON) + * + */ + uint32_t bestNR = 0; + uint32_t bestNF = 0; + uint32_t minLimit = -1; + + while (NR <= 33) { + uint32_t tmpCalc1 = clkCalc / NR; + + if (tmpCalc1 > 1600000 && tmpCalc1 < 16000000) { + uint32_t NF = 2; + + while (NF <= 513) { + uint32_t tmpCalc2 = tmpCalc1 * NF; + + if (tmpCalc2 >= 100000000 && tmpCalc2 <= 200000000) { + uint32_t tmpCalc3; + + if (tmpCalc2 > pllFreq) { + tmpCalc3 = tmpCalc2 - pllFreq; + } else { + tmpCalc3 = pllFreq - tmpCalc2; + } + + if (tmpCalc3 < minLimit) { + minLimit = tmpCalc3; + bestNF = NF; + bestNR = NR; + + /* Stop NF calc loop when minLimit tends back to 0 */ + if (minLimit == 0) + break; + } + } + + NF++; + } + } + + NR++; + } + + /* Enable and apply new PLL setting. */ + CLK->PLLCON = pllSrc | (NO << 14) | ((bestNR - 2) << 9) | (bestNF - 2); + + /* Wait for stable PLL clock */ + wait_for_clock_ready(CLK_CLKSTATUS_PLL_STB_Msk); + + /* Return equation result */ + return (clkCalc / ((NO + 1) * bestNR) * bestNF); +} + +/** @brief Set Core Clock + * + * @description Set the core system clock some reference speed (Hz). + * This should be between 25MHz and 72MHz for the NUC123SD4AN0. + * + * Use either the HXT (exact) or HIRC (nearest using 22.1184MHz) + * as the clock source. + * + */ +static uint32_t set_core_clock(uint32_t clkCore) +{ + uint32_t stableHIRC; + + /* Read HIRC clock source stable flag */ + stableHIRC = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk; + + /* Setup __HIRC */ + CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk; + + wait_for_clock_ready(CLK_CLKSTATUS_OSC22M_STB_Msk); + + /* Use __HIRC as HCLK temporarily */ + CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_Msk; + CLK->CLKDIV &= (~CLK_CLKDIV_HCLK_N_Msk); + + /* Is HXT stable ? */ + if (CLK->CLKSTATUS & CLK_CLKSTATUS_XTL12M_STB_Msk) { + /* Use __HXT as PLL source */ + clkCore = enable_pll(NUC123_PLLSRC_HSE, (clkCore)); + } else { + /* Use __HIRC as PLL source */ + clkCore = enable_pll(NUC123_PLLSRC_HSI, (clkCore)); + + /* Read HIRC clock source stable flag again (since we're using it now) */ + stableHIRC = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk; + } + + /* Set HCLK clock source to PLL */ + set_HCLK(NUC123_HCLKSRC_PLL, CLK_CLKDIV_HCLK(1)); + + /* Disable HIRC if HIRC was disabled before we started */ + if (stableHIRC == 0) { + CLK->PWRCON &= ~CLK_PWRCON_OSC22M_EN_Msk; + } + + /* Return actual HCLK frequency is PLL frequency divide 2 */ + return (clkCore >> 1); +} + /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ -#if defined(NUC123_DMA_REQUIRED) || defined(__DOXYGEN__) -#if defined(NUC123_DMA1_CH23_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA1 streams 2 and 3 shared ISR. - * @note It is declared here because this device has a non-standard - * DMA shared IRQ handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(NUC123_DMA1_CH23_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - /* Check on channel 2.*/ - dmaServeInterrupt(NUC123_DMA1_STREAM2); - - /* Check on channel 3.*/ - dmaServeInterrupt(NUC123_DMA1_STREAM3); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* defined(NUC123_DMA1_CH23_HANDLER) */ - -#if defined(NUC123_DMA1_CH4567_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA1 streams 4, 5, 6 and 7 shared ISR. - * - * @isr - */ -OSAL_IRQ_HANDLER(NUC123_DMA1_CH4567_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - /* Check on channel 4.*/ - dmaServeInterrupt(NUC123_DMA1_STREAM4); - - /* Check on channel 5.*/ - dmaServeInterrupt(NUC123_DMA1_STREAM5); - -#if NUC123_DMA1_NUM_CHANNELS > 5 - /* Check on channel 6.*/ - dmaServeInterrupt(NUC123_DMA1_STREAM6); -#endif - -#if NUC123_DMA1_NUM_CHANNELS > 6 - /* Check on channel 7.*/ - dmaServeInterrupt(NUC123_DMA1_STREAM7); -#endif - - OSAL_IRQ_EPILOGUE(); -} -#endif /* defined(NUC123_DMA1_CH4567_HANDLER) */ - -#if defined(NUC123_DMA12_CH23_CH12_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA1 streams 2 and 3, DMA2 streams 1 and 1 shared ISR. - * @note It is declared here because this device has a non-standard - * DMA shared IRQ handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(NUC123_DMA12_CH23_CH12_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - /* Check on channel 2 of DMA1.*/ - dmaServeInterrupt(NUC123_DMA1_STREAM2); - - /* Check on channel 3 of DMA1.*/ - dmaServeInterrupt(NUC123_DMA1_STREAM3); - - /* Check on channel 1 of DMA2.*/ - dmaServeInterrupt(NUC123_DMA2_STREAM1); - - /* Check on channel 2 of DMA2.*/ - dmaServeInterrupt(NUC123_DMA2_STREAM2); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* defined(NUC123_DMA12_CH23_CH12_HANDLER) */ - -#if defined(NUC123_DMA12_CH4567_CH345_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA1 streams 4, 5, 6 and 7, DMA2 streams 3, 4 and 5 shared ISR. - * @note It is declared here because this device has a non-standard - * DMA shared IRQ handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(NUC123_DMA12_CH4567_CH345_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - /* Check on channel 4 of DMA1.*/ - dmaServeInterrupt(NUC123_DMA1_STREAM4); - - /* Check on channel 5 of DMA1.*/ - dmaServeInterrupt(NUC123_DMA1_STREAM5); - - /* Check on channel 6 of DMA1.*/ - dmaServeInterrupt(NUC123_DMA1_STREAM6); - - /* Check on channel 7 of DMA1.*/ - dmaServeInterrupt(NUC123_DMA1_STREAM7); - - /* Check on channel 3 of DMA2.*/ - dmaServeInterrupt(NUC123_DMA2_STREAM3); - - /* Check on channel 4 of DMA2.*/ - dmaServeInterrupt(NUC123_DMA2_STREAM4); - - /* Check on channel 5 of DMA2.*/ - dmaServeInterrupt(NUC123_DMA2_STREAM5); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* defined(NUC123_DMA12_CH4567_CH345_HANDLER) */ -#endif /* defined(NUC123_DMA_REQUIRED) */ - /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -181,76 +444,45 @@ OSAL_IRQ_HANDLER(NUC123_DMA12_CH4567_CH345_HANDLER) { * * @notapi */ -void hal_lld_init(void) { - - /* Reset of all peripherals.*/ -// **NUC123TODO -#if defined(NUC123_DMA_REQUIRED) - //dmaInit(); - //usbInit(); - //uartInit(); - //spiInit(); -#endif - //usbInit(); - +void hal_lld_init(void) +{ + if (!clock_initialized) { + NUC123_clock_init(); + } } -/** - * @brief NUC123 clocks and PLL initialization. - * @note All the involved constants come from the file @p board.h. - * @note This function should be invoked just after the system reset. - * - * @special - */ -void NUC123_clock_init(void) { - SystemUnlockReg(); +void NUC123_clock_init(void) +{ + clock_initialized = TRUE; + UNLOCKREG(); - /* Enable XT1_OUT (PF.0) and XT1_IN (PF.1) */ - SYS->GPF_MFP |= SYS_GPF_MFP_PF0_XT1_OUT | SYS_GPF_MFP_PF1_XT1_IN; + /* Always initialize HSI and go from there, things can change later */ + /* TODO: Technically this could also be the crystal, figure out how to allow + * config in linker? */ + /* Enable HSI */ + CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk; + wait_for_clock_ready(CLK_CLKSTATUS_OSC22M_STB_Msk); - /*---------------------------------------------------------------------------------------------------------*/ - /* Init System Clock */ - /*---------------------------------------------------------------------------------------------------------*/ + set_HCLK(NUC123_HCLKSRC_HSI, CLK_CLKDIV_HCLK(1)); - /* Enable Internal RC 22.1184 MHz clock */ - CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk; - - /* Waiting for Internal RC clock ready */ - clks_lld_wait_for_clock_ready(CLK_CLKSTATUS_OSC22M_STB_Msk); +#if NUC123_HSE_ENABLED - /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */ - clks_lld_set_HCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1)); + SYS->GPF_MFP |= (SYS_GPF_MFP_GPF_MFP0_Msk | SYS_GPF_MFP_GPF_MFP1_Msk); - /* Enable external XTAL 12 MHz clock */ - CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk; + CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk; + wait_for_clock_ready(CLK_CLKSTATUS_XTL12M_STB_Msk); - /* Waiting for external XTAL clock ready */ - clks_lld_wait_for_clock_ready(CLK_CLKSTATUS_XTL12M_STB_Msk); +#endif /* NUC123_HSE_ENABLED */ - /* Set core clock */ - clks_lld_set_core_clock(FREQ_72MHZ); +#if NUC123_LSI_ENABLED + CLK->PWRCON |= CLK_PWRCON_IRC10K_EN_Msk; + wait_for_clock_ready(CLK_CLKSTATUS_IRC10K_STB_Msk); +#endif /* NUC123_LSI_ENABLED */ - SystemCoreClock = NUC123_HCLK; + set_core_clock(NUC123_HCLK); + SystemCoreClock = NUC123_HCLK; - clks_lld_enable_SysTick(CLK_CLKSEL0_STCLK_S_HCLK_DIV2, (NUC123_HCLK / OSAL_ST_FREQUENCY) - 1); - - /* Enable module clock */ - clks_lld_enable_module_clock(USBD_ModuleNum); - - /* Select module clock source */ - clks_lld_set_module_clock(USBD_ModuleNum, 0, CLK_CLKDIV_USB(3)); - - /* TEMPORARY!!! */ - /* Set GPB multi-function pins for UART0 RXD and TXD */ - SYS->GPB_MFP = (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD); - /* Set PC.13 as CLKO function pin */ - //SYS->GPC_MFP = SYS_GPC_MFP_PC13_CLKO; - //SYS->ALT_MFP = SYS_ALT_MFP_PC13_CLKO; - - /* Enable CLKO (PC.13) for monitor HCLK. CLKO = HCLK/8 Hz*/ - // clks_lld_enable_ck0(CLK_CLKSEL2_FRQDIV_S_HCLK, 2, 0); - - LOCKREG(); + LOCKREG(); } /** @} */ diff --git a/os/hal/ports/NUMICRO/NUC123SD4AN0/hal_lld.h b/os/hal/ports/NUMICRO/NUC123SD4AN0/hal_lld.h index c53b9f14..e258c1f7 100644 --- a/os/hal/ports/NUMICRO/NUC123SD4AN0/hal_lld.h +++ b/os/hal/ports/NUMICRO/NUC123SD4AN0/hal_lld.h @@ -1,5 +1,6 @@ /* - Copyright (C) 2019 /u/KeepItUnder + Copyright (C) 2020 Alex Lewontin + Copyright (C) 2019 /u/KeepItUnder Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -19,13 +20,9 @@ * @brief NUC123SD4AN0 HAL subsystem low level driver header. * @pre This module requires the following macros to be defined in the * @p board.h file: - * - NUC123_LSECLK. - * - NUC123_LSEDRV. - * - NUC123_LSE_BYPASS (optionally). * - NUC123_HSECLK. * - NUC123_HSE_BYPASS (optionally). * . - * . * * @addtogroup HAL * @{ @@ -44,20 +41,19 @@ */ #if defined(NUC123SD4AN0) || defined(__DOXYGEN__) #define PLATFORM_NAME "NUC123SD4AN0 NUC123 Cortex M0 USB Micro" - #else #error "NUC123 device unsupported or not specified" #endif + +#define NUC123xxxANx +#undef NUC123xxxAEx + /** @} */ /** * @name Absolute Maximum Ratings * @{ */ -/** - * @brief Maximum system clock frequency. - */ -#define NUC123_SYSCLK_MAX FREQ_72MHZ /** * @brief Maximum HSE clock frequency. @@ -70,39 +66,24 @@ #define NUC123_HSECLK_MIN 4000000 /** - * @brief Maximum LSE clock frequency. + * @brief Minimum PLL frequency. */ -#define NUC123_LSECLK_MAX 10000 +#define NUC123_PLLCLK_MIN 25000000UL /** - * @brief Minimum LSE clock frequency. + * @brief Maximum PLL frequency. */ -#define NUC123_LSECLK_MIN 10000 +#define NUC123_PLLCLK_MAX 144000000UL /** - * @brief Maximum PLLs input clock frequency. + * @brief Minimum HCLK divider value. */ -#define NUC123_PLLIN_MAX 24000000 +#define NUC123_HCLKDIV_MIN 1 /** - * @brief Minimum PLLs input clock frequency. + * @brief Maximum HCLK divider value. */ -#define NUC123_PLLIN_MIN 4000000 - -/** - * @brief Maximum PLL output clock frequency. - */ -#define NUC123_PLLOUT_MAX FREQ_72MHZ - -/** - * @brief Minimum PLL output clock frequency. - */ -#define NUC123_PLLOUT_MIN 4000000 - -/** - * @brief Maximum APB clock frequency. - */ -#define NUC123_PCLK_MAX FREQ_72MHZ +#define NUC123_HCLKDIV_MAX 16 /** @} */ /** @@ -110,126 +91,26 @@ * @{ */ #define NUC123_HSICLK __HIRC /**< High speed internal clock. */ -#define NUC123_HSI_69CLK 691200 /**< ~0.69MHz High speed internal clock. */ -#define NUC123_HSI1_38CLK 1382400 /**< ~1.375MHz High speed internal clock. */ -#define NUC123_HSI2_76CLK 2764800 /**< ~2.75MHz High speed internal clock. */ -#define NUC123_HSI5_5CLK 5529600 /**< ~5.5MHz speed internal clock.*/ -#define NUC123_HSI11CLK 11059200 /**< ~11MHz speed internal clock.*/ #define NUC123_LSICLK __LIRC /**< Low speed internal clock. */ /** @} */ /** - * @name CLKSEL0 register bits definitions + * @name HCLK_S bit definitions * @{ */ - -#define NUC123_HCLKSRC_HSE (0 << 0) /**< HCLK source is HSE */ -#define NUC123_HCLKSRC_PLL_2 (1 << 0) /**< HCLK source is PLL/2 */ -#define NUC123_HCLKSRC_PLL (2 << 0) /**< HCLK source is PLL */ -#define NUC123_HCLKSRC_LSI (3 << 0) /**< HCLK source is LSI */ -#define NUC123_HCLKSRC_HSI (7 << 0) /**< HCLK source is HSI */ - -#define NUC123_SW_HSE (0 << 3) /**< SYSCLK source is HSE. */ -#define NUC123_SW_HSE_2 (1 << 3) /**< SYSCLK source is HSE/2. */ -#define NUC123_SW_HCLK_2 (3 << 3) /**< SYSCLK source is HCLK/2. */ -#define NUC123_SW_HSI_2 (7 << 3) /**< SYSCLK source is HSI. */ +#define NUC123_HCLKSRC_HSE (0 << CLK_CLKSEL0_HCLK_S_Pos) /**< HCLK source is HSE. */ +#define NUC123_HCLKSRC_PLL_2 (1 << CLK_CLKSEL0_HCLK_S_Pos) /**< HCLK source is PLL/2. */ +#define NUC123_HCLKSRC_PLL (2 << CLK_CLKSEL0_HCLK_S_Pos) /**< HCLK source is PLL. */ +#define NUC123_HCLKSRC_LSI (3 << CLK_CLKSEL0_HCLK_S_Pos) /**< HCLK source is LSI. */ +#define NUC123_HCLKSRC_HSI (7 << CLK_CLKSEL0_HCLK_S_Pos) /**< HCLK source is HSI. */ /** @} */ /** - * @name CLKSEL1 register bits definitions + * @name PLL_SRC bit definitions * @{ */ -#define NUC123_WDTSRC_MASK (3 << 0) /**< WDT source mask */ -#define NUC123_WDTSRC_HCLK_2048 (2 << 0) /**< WDT source is HCLK/2048 */ -#define NUC123_WDTSRC_LSI (3 << 0) /**< WDT source is LSI */ - -#define NUC123_ADCSRC_MASK (3 << 2) /**< ADC source mask */ -#define NUC123_ADCSRC_HSE (0 << 2) /**< ADC source is HSE */ -#define NUC123_ADCSRC_PLL (1 << 2) /**< ADC source is PLL */ -#define NUC123_ADCSRC_HCLK (2 << 2) /**< ADC source is HCLK */ -#define NUC123_ADCSRC_HSI (3 << 2) /**< ADC source is HSI */ - -#define NUC123_SPI0SRC_MASK (1 << 4) /**< SPI0 source mask */ -#define NUC123_SPI0SRC_PLL (0 << 4) /**< SPI0 source is PLL */ -#define NUC123_SPI0SRC_HCLK (1 << 4) /**< SPI0 source is HCLK */ -#define NUC123_SPI1SRC_MASK (1 << 5) /**< SPI1 source MASK */ -#define NUC123_SPI1SRC_PLL (0 << 5) /**< SPI1 source is PLL */ -#define NUC123_SPI1SRC_HCLK (1 << 5) /**< SPI1 source is HCLK */ -#define NUC123_SPI2SRC_MASK (1 << 6) /**< SPI2 source mask */ -#define NUC123_SPI2SRC_PLL (0 << 6) /**< SPI2 source is PLL */ -#define NUC123_SPI2SRC_HCLK (1 << 6) /**< SPI2 source is HCLK */ - -#define NUC123_TMR0SRC_MASK (7 << 8) /**< TMR0 source mask */ -#define NUC123_TMR0SRC_HSE (0 << 8) /**< TMR0 source is HSE */ -#define NUC123_TMR0SRC_HCLK (2 << 8) /**< TMR0 source is HCLK */ -#define NUC123_TMR0SRC_TM0 (3 << 8) /**< TMR0 source is TM0 pin */ -#define NUC123_TMR0SRC_LSI (5 << 8) /**< TMR0 source is LSI */ -#define NUC123_TMR0SRC_HSI (7 << 8) /**< TMR0 source is HSI */ - -#define NUC123_TMR1SRC_MASK (7 << 12) /**< TMR1 source mask */ -#define NUC123_TMR1SRC_HSE (0 << 12) /**< TMR1 source is HSE */ -#define NUC123_TMR1SRC_HCLK (2 << 12) /**< TMR1 source is HCLK */ -#define NUC123_TMR1SRC_TM1 (3 << 12) /**< TMR1 source is TM1 pin */ -#define NUC123_TMR1SRC_LSI (5 << 12) /**< TMR1 source is LSI */ -#define NUC123_TMR1SRC_HSI (7 << 12) /**< TMR1 source is HSI */ - -#define NUC123_TMR2SRC_MASK (7 << 16) /**< TMR2 source mask */ -#define NUC123_TMR2SRC_HSE (0 << 16) /**< TMR2 source is HSE */ -#define NUC123_TMR2SRC_HCLK (2 << 16) /**< TMR2 source is HCLK */ -#define NUC123_TMR2SRC_TM2 (3 << 16) /**< TMR2 source is TM2 pin */ -#define NUC123_TMR2SRC_LSI (5 << 16) /**< TMR2 source is LSI */ -#define NUC123_TMR2SRC_HSI (7 << 16) /**< TMR2 source is HSI */ - -#define NUC123_TMR3SRC_MASK (7 << 20) /**< TMR3 source mask */ -#define NUC123_TMR3SRC_HSE (0 << 20) /**< TMR3 source is HSE */ -#define NUC123_TMR3SRC_HCLK (2 << 20) /**< TMR3 source is HCLK */ -#define NUC123_TMR3SRC_LSI (5 << 20) /**< TMR3 source is LSI */ -#define NUC123_TMR3SRC_HSI (7 << 20) /**< TMR3 source is HSI */ - -#define NUC123_USARTSRC_MASK (3 << 24) /**< UART source mask. */ -#define NUC123_USARTSRC_HS3 (0 << 24) /**< UART source is HSE. */ -#define NUC123_USARTSRC_PLL (1 << 24) /**< UART source is PLL. */ -#define NUC123_USARTSRC_HSI (3 << 24) /**< UART source is HSI. */ - -#define NUC123_PWM01SRCA_MASK (3 << 28) /**< PWM0/1 source [1:0] mask */ -#define NUC123_PWM01SRCA_HSE (0 << 28) /**< PWM0/1 source [1:0] is HSE */ -#define NUC123_PWM01SRCA_HCLK (2 << 28) /**< PWM0/1 source [1:0] is HCLK*/ -#define NUC123_PWM01SRCA_HSI (3 << 28) /**< PWM0/1 source [1:0] is HSI */ -#define NUC123_PWM01SRCA_LSI (3 << 28) /**< PWM0/1 source [1:0] is LSI */ - -#define NUC123_PWM23SRCA_MASK (3 << 30) /**< PWM2/3 source [1:0] mask */ -#define NUC123_PWM23SRCA_HSE (0 << 30) /**< PWM2/3 source [1:0] is HSE */ -#define NUC123_PWM23SRCA_HCLK (2 << 30) /**< PWM2/3 source [1:0] is HCLK*/ -#define NUC123_PWM23SRCA_HSI (3 << 30) /**< PWM2/3 source [1:0] is HSI */ -#define NUC123_PWM23SRCA_LSI (3 << 30) /**< PWM2/3 source [1:0] is LSI */ -/** @} */ - -/** - * @name CLKSEL2 register bits definitions - * @{ - */ -#define NUC123_I2SSRC_MASK (3 << 0) /**< I2S clock source mask. */ -#define NUC123_I2SSRC_HSE (0 << 0) /**< I2S clock source is HSE. */ -#define NUC123_I2SSRC_PLL (1 << 0) /**< I2S clock source is PLL. */ -#define NUC123_I2SSRC_HCLK (2 << 0) /**< I2S clock source is HCLK. */ -#define NUC123_I2SSRC_HSI (3 << 0) /**< I2S clock source is HSI. */ - -#define NUC123_FREQDIVSRC_MASK (3 << 2) /**< FRQDIV clock source mask */ -#define NUC123_FREQDIVSRC_HSE (0 << 2) /**< FRQDIV clock source is HSE */ -#define NUC123_FREQDIVSRC_HCLK (2 << 2) /**< FRQDIV clock source is HCLK*/ -#define NUC123_FREQDIVSRC_HSI (3 << 2) /**< FRQDIV clock source is LSI */ - -#define NUC123_PWM01SRCB_MASK (1 << 8) /**< PWM0/1 source [2] mask */ -#define NUC123_PWM01SRCB_HSI (0 << 8) /**< PWM0/1 source [2] is HSI */ -#define NUC123_PWM01SRCB_LSI (1 << 8) /**< PWM0/1 source [2] is LSI */ - -#define NUC123_PWM23SRCB_MASK (1 << 9) /**< PWM2/3 source [2] mask */ -#define NUC123_PWM23SRCB_HSI (0 << 9) /**< PWM2/3 source [2] is HSI */ -#define NUC123_PWM23SRCB_LSI (1 << 9) /**< PWM2/3 source [2] is LSI */ - -#define NUC123_WWDTSRC_MASK (3 << 16) /**< WWDT source mask */ -#define NUC123_WWDTSRC_HCLK_2048 (2 << 16) /**< WWDT source is HCLK/2048 */ -#define NUC123_WWDTSRC_LSI (3 << 16) /**< WWDT source is LSI */ +#define NUC123_PLLSRC_HSE (0 << CLK_PLLCON_PLL_SRC_Pos) /**< PLL source is HSE. */ +#define NUC123_PLLSRC_HSI (1 << CLK_PLLCON_PLL_SRC_Pos) /**< PLL source is HSI. */ /** @} */ /*===========================================================================*/ @@ -237,9 +118,10 @@ /*===========================================================================*/ /** - * @name Configuration options + * @name NUMICRO configuration options * @{ */ + /** * @brief Disables the PWR/RCC initialization in the HAL. */ @@ -258,7 +140,7 @@ * @brief Enables or disables the LSI clock source. */ #if !defined(NUC123_LSI_ENABLED) || defined(__DOXYGEN__) -#define NUC123_LSI_ENABLED TRUE +#define NUC123_LSI_ENABLED FALSE #endif /** @@ -269,118 +151,31 @@ #endif /** - * @brief Enables or disables the LSE clock source. + * @brief Enables or disables PLL */ -#if !defined(NUC123_LSE_ENABLED) || defined(__DOXYGEN__) -#define NUC123_LSE_ENABLED FALSE +#if !defined(NUC123_PLL_ENABLED) || defined(__DOXYGEN__) +#define NUC123_PLL_ENABLED FALSE #endif /** * @brief Main clock source selection. - * @note If the selected clock source is not the PLL then the PLL is not - * initialized and started. - * @note The default value is calculated for a 72MHz system clock from - * a 12MHz crystal using the PLL. */ -#if !defined(NUC123_SW) || defined(__DOXYGEN__) -#define NUC123_SW NUC123_SW_HCLK_2 +#if !defined(NUC123_HCLKSRC) || defined(__DOXYGEN__) +#define NUC123_HCLKSRC NUC123_HCLKSRC_HSI +#endif + +/** + * @brief Main clock divider value. + */ +#if !defined(NUC123_HCLKDIV) || defined(__DOXYGEN__) +#define NUC123_HCLKDIV 1 #endif /** * @brief Clock source for the PLL. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The default value is calculated for a 72MHz system clock from - * a 12MHz crystal using the PLL. */ -#if !defined(NUC123_PLLSRC) || defined(__DOXYGEN__) -#define NUC123_PLLSRC NUC123_PLLSRC_HSE -#endif - -/** - * @brief Crystal PLL pre-divider. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The default value is calculated for a 72MHz system clock from - * a 21MHz crystal using the PLL. - */ -#if !defined(NUC123_PREDIV_VALUE) || defined(__DOXYGEN__) -#define NUC123_PREDIV_VALUE 1 -#endif - -/** - * @brief PLL multiplier value. - * @note The allowed range is 2...16. - * @note The default value is calculated for a 72MHz system clock from - * a 12MHz crystal using the PLL. - */ -#if !defined(NUC123_PLLMUL_VALUE) || defined(__DOXYGEN__) -#define NUC123_PLLMUL_VALUE 6 -#endif - -/** - * @brief AHB prescaler value. - * @note The default value is calculated for a 72MHz system clock from - * a 12MHz crystal using the PLL. - */ -#if !defined(NUC123_HPRE) || defined(__DOXYGEN__) -#define NUC123_HPRE NUC123_HPRE_DIV1 -#endif - -/** - * @brief APB1 prescaler value. - */ -#if !defined(NUC123_PPRE) || defined(__DOXYGEN__) -#define NUC123_PPRE NUC123_PPRE_DIV1 -#endif - -/** - * @brief MCO pin setting. - */ -#if !defined(NUC123_MCOSEL) || defined(__DOXYGEN__) -#define NUC123_MCOSEL NUC123_MCOSEL_NOCLOCK -#endif - -/** - * @brief MCO divider setting. - */ -#if !defined(NUC123_MCOPRE) || defined(__DOXYGEN__) -#define NUC123_MCOPRE NUC123_MCOPRE_DIV1 -#endif - -/** - * @brief MCO PLL divider setting. - */ -#if !defined(NUC123_PLLNODIV) || defined(__DOXYGEN__) -#define NUC123_PLLNODIV NUC123_PLLNODIV_DIV2 -#endif - -/** - * @brief USB Clock source. - */ -#if !defined(NUC123_USBSW) || defined(__DOXYGEN__) -#define NUC123_USBSW NUC123_USBSW_HSI48 -#endif - -/** - * @brief CEC clock source. - */ -#if !defined(NUC123_CECSW) || defined(__DOXYGEN__) -#define NUC123_CECSW NUC123_CECSW_HSI -#endif - -/** - * @brief I2C1 clock source. - */ -#if !defined(NUC123_I2C1SW) || defined(__DOXYGEN__) -#define NUC123_I2C1SW NUC123_I2C1SW_HSI -#endif - -/** - * @brief USART1 clock source. - */ -#if !defined(NUC123_USART1SW) || defined(__DOXYGEN__) -#define NUC123_USART1SW NUC123_USART1SW_PCLK +#if !defined(NUC123_PLLCLK) || defined(__DOXYGEN__) +#define NUC123_PLLCLK 72000000UL #endif /** @} */ @@ -396,335 +191,84 @@ #endif /* - * HSI related checks. - */ -#if NUC123_HSI_ENABLED - -/*#if NUC123_SW == NUC123_SW_HSE -#error "HSI not enabled, required by NUC123_SW" -#endif - -#if NUC123_CECSW == NUC123_CECSW_HSI -#error "HSI not enabled, required by NUC123_CECSW" -#endif - -#if NUC123_I2C1SW == NUC123_I2C1SW_HSI -#error "HSI not enabled, required by NUC123_I2C1SW" -#endif - -#if NUC123_USART1SW == NUC123_USART1SW_HSI -#error "HSI not enabled, required by NUC123_USART1SW" -#endif - -#if (NUC123_SW == NUC123_SW_PLL) && \ - (NUC123_PLLSRC == NUC123_PLLSRC_HSI_DIV2) || \ - (NUC123_PLLSRC == NUC123_PLLSRC_HSI) -#error "HSI not enabled, required by NUC123_SW and NUC123_PLLSRC" -#endif - -#if (NUC123_MCOSEL == NUC123_MCOSEL_HSI) || \ - ((NUC123_MCOSEL == NUC123_MCOSEL_PLLDIV2) && \ - ((NUC123_PLLSRC == NUC123_PLLSRC_HSI_DIV2) || \ - (NUC123_PLLSRC == NUC123_PLLSRC_HSI))) -#error "HSI not enabled, required by NUC123_MCOSEL" -#endif -*/ -#endif /* !NUC123_HSI_ENABLED */ - -/* - * HSE related checks. + * HSE checks. */ #if NUC123_HSE_ENABLED -#if NUC123_HSECLK == 0 +#if !defined(NUC123_HSECLK) #error "HSE frequency not defined" #elif (NUC123_HSECLK < NUC123_HSECLK_MIN) || (NUC123_HSECLK > NUC123_HSECLK_MAX) #error "NUC123_HSECLK outside acceptable range (NUC123_HSECLK_MIN...NUC123_HSECLK_MAX)" #endif - -#else /* !NUC123_HSE_ENABLED */ - -#if (NUC123_SW == NUC123_SW_HSE) || (NUC123_SW == NUC123_SW_HSE_2) -#error "HSE not enabled, required by NUC123_SW" -#endif - -#if (NUC123_SW == NUC123_SW_HCL) && (NUC123_PLLSRC == NUC123_PLLSRC_HSE) -#error "HSE not enabled, required by NUC123_SW and NUC123_PLLSRC" -#endif - -#if (NUC123_MCOSEL == NUC123_MCOSEL_HSE) || \ - ((NUC123_MCOSEL == NUC123_MCOSEL_PLLDIV2) && \ - (NUC123_PLLSRC == NUC123_PLLSRC_HSE)) -#error "HSE not enabled, required by NUC123_MCOSEL" -#endif - -#endif /* !NUC123_HSE_ENABLED */ - -/* - * LSI related checks. - */ -#if NUC123_LSI_ENABLED -#else /* !NUC123_LSI_ENABLED */ - -#if NUC123_RTCSEL == NUC123_RTCSEL_LSI -#error "LSI not enabled, required by NUC123_RTCSEL" -#endif - -#endif /* !NUC123_LSI_ENABLED */ - -/* - * LSE related checks. - */ -#if NUC123_LSE_ENABLED - -#if (NUC123_LSECLK == 0) -#error "LSE frequency not defined" -#endif - -#if (NUC123_LSECLK < NUC123_LSECLK_MIN) || (NUC123_LSECLK > NUC123_LSECLK_MAX) -#error "NUC123_LSECLK outside acceptable range (NUC123_LSECLK_MIN...NUC123_LSECLK_MAX)" -#endif - -#if !defined(NUC123_LSEDRV) -#error "NUC123_LSEDRV not defined" -#endif - -#if (NUC123_LSEDRV >> 3) > 3 -#error "NUC123_LSEDRV outside acceptable range ((0<<3)...(3<<3))" -#endif - -#else /* !NUC123_LSE_ENABLED */ - -#endif /* !NUC123_LSE_ENABLED */ - -/* PLL activation conditions.*/ -#if (NUC123_SW == NUC123_SW_PLL) || \ - (NUC123_USBSW == NUC123_USBSW_PCLK) || \ - (NUC123_MCOSEL == NUC123_MCOSEL_PLLDIV2) || \ - defined(__DOXYGEN__) -/** - * @brief PLL activation flag. - */ -#define NUC123_ACTIVATE_PLL TRUE -#else -#define NUC123_ACTIVATE_PLL FALSE -#endif - -/* HSE, HSI prescaler setting check.*/ -#if ((NUC123_PREDIV_VALUE >= 1) || (NUC123_PREDIV_VALUE <= 16)) -#define NUC123_PREDIV ((NUC123_PREDIV_VALUE - 1) << 0) -#else -#error "invalid NUC123_PREDIV value specified" -#endif - -/** - * @brief PLLMUL field. - */ -#if ((NUC123_PLLMUL_VALUE >= 2) && (NUC123_PLLMUL_VALUE <= 16)) || \ - defined(__DOXYGEN__) -#define NUC123_PLLMUL ((NUC123_PLLMUL_VALUE - 2) << 18) -#else -#error "invalid NUC123_PLLMUL_VALUE value specified" -#endif - -/** - * @brief PLL input clock frequency. - */ -#if (NUC123_PLLSRC == NUC123_PLLSRC_HSE) || defined(__DOXYGEN__) -#define NUC123_PLLCLKIN (NUC123_HSECLK / NUC123_PREDIV_VALUE) -#elif NUC123_PLLSRC == NUC123_PLLSRC_HSI_DIV2 -#define NUC123_PLLCLKIN (NUC123_HSICLK / 2) -#elif NUC123_PLLSRC == NUC123_PLLSRC_HSI -#define NUC123_PLLCLKIN (NUC123_HSICLK / NUC123_PREDIV_VALUE) -#else -#error "invalid NUC123_PLLSRC value specified" -#endif - -/* PLL input frequency range check.*/ -#if (NUC123_PLLCLKIN < NUC123_PLLIN_MIN) || (NUC123_PLLCLKIN > NUC123_PLLIN_MAX) -#error "NUC123_PLLCLKIN outside acceptable range (NUC123_PLLIN_MIN...NUC123_PLLIN_MAX)" -#endif - -/** - * @brief PLL output clock frequency. - */ -#define NUC123_PLLCLKOUT (NUC123_PLLCLKIN * NUC123_PLLMUL_VALUE) - -/* PLL output frequency range check. -#if (NUC123_PLLCLKOUT < NUC123_PLLOUT_MIN) || (NUC123_PLLCLKOUT > NUC123_PLLOUT_MAX) -#error "NUC123_PLLCLKOUT outside acceptable range (NUC123_PLLOUT_MIN...NUC123_PLLOUT_MAX)" -#endif -*/ -/** - * @brief System clock source. - */ -#if (NUC123_SW == NUC123_SW_HSE) || defined(__DOXYGEN__) -#define NUC123_SYSCLK NUC123_HSECLK -#elif (NUC123_SW == NUC123_SW_HSE_2) -#define NUC123_SYSCLK NUC123_HSECLK >> 1 -#elif (NUC123_SW == NUC123_SW_HCLK_2) -#define NUC123_SYSCLK FREQ_72MHZ >> 1 -#elif (NUC123_SW == NUC123_SW_HSI_2) -#define NUC123_SYSCLK NUC123_HSI11CLK -#else -#error "invalid NUC123_SW value specified" -#endif - -/* Check on the system clock.*/ -#if NUC123_SYSCLK > NUC123_SYSCLK_MAX -#error "NUC123_SYSCLK above maximum rated frequency (NUC123_SYSCLK_MAX)" -#endif - -/** - * @brief AHB frequency. - * -#if (NUC123_HPRE == NUC123_HPRE_DIV1) || defined(__DOXYGEN__) -#define NUC123_HCLK (NUC123_SYSCLK / 1) -#elif NUC123_HPRE == NUC123_HPRE_DIV2 -#define NUC123_HCLK (NUC123_SYSCLK / 2) -#elif NUC123_HPRE == NUC123_HPRE_DIV4 -#define NUC123_HCLK (NUC123_SYSCLK / 4) -#elif NUC123_HPRE == NUC123_HPRE_DIV8 -#define NUC123_HCLK (NUC123_SYSCLK / 8) -#elif NUC123_HPRE == NUC123_HPRE_DIV16 -#define NUC123_HCLK (NUC123_SYSCLK / 16) -#elif NUC123_HPRE == NUC123_HPRE_DIV64 -#define NUC123_HCLK (NUC123_SYSCLK / 64) -#elif NUC123_HPRE == NUC123_HPRE_DIV128 -#define NUC123_HCLK (NUC123_SYSCLK / 128) -#elif NUC123_HPRE == NUC123_HPRE_DIV256 -#define NUC123_HCLK (NUC123_SYSCLK / 256) -#elif NUC123_HPRE == NUC123_HPRE_DIV512 -#define NUC123_HCLK (NUC123_SYSCLK / 512) -#else -#error "invalid NUC123_HPRE value specified" -#endif -*/ -#define NUC123_HCLK (NUC123_SYSCLK / 1) - -/* AHB frequency check.*/ -#if NUC123_HCLK > NUC123_SYSCLK_MAX -#error "NUC123_HCLK exceeding maximum frequency (NUC123_SYSCLK_MAX)" -#endif - -/** - * @brief APB frequency. - */ -#if (NUC123_PPRE == NUC123_PPRE_DIV1) || defined(__DOXYGEN__) -#define NUC123_PCLK (NUC123_HCLK / 1) -#elif NUC123_PPRE == NUC123_PPRE_DIV2 -#define NUC123_PCLK (NUC123_HCLK / 2) -#elif NUC123_PPRE == NUC123_PPRE_DIV4 -#define NUC123_PCLK (NUC123_HCLK / 4) -#elif NUC123_PPRE == NUC123_PPRE_DIV8 -#define NUC123_PCLK (NUC123_HCLK / 8) -#elif NUC123_PPRE == NUC123_PPRE_DIV16 -#define NUC123_PCLK (NUC123_HCLK / 16) -#else -#error "invalid NUC123_PPRE value specified" -#endif - -/* APB frequency check.*/ -#if NUC123_PCLK > NUC123_PCLK_MAX -#error "NUC123_PCLK exceeding maximum frequency (NUC123_PCLK_MAX)" -#endif - -/* NUC123_PLLNODIV check.*/ -#if (NUC123_PLLNODIV != NUC123_PLLNODIV_DIV2) && \ - (NUC123_PLLNODIV != NUC123_PLLNODIV_DIV1) -#error "invalid NUC123_PLLNODIV value specified" -#endif - - -/** - * @brief CEC frequency. - */ -#if (NUC123_CECSW == NUC123_CECSW_HSI) || defined(__DOXYGEN__) -#define NUC123_CECCLK NUC123_HSICLK -#elif NUC123_CECSW == NUC123_CECSW_LSE -#define NUC123_CECCLK NUC123_LSECLK -#elif NUC123_CECSW == NUC123_CECSW_OFF -#define NUC123_CECCLK 0 -#else -#error "invalid source selected for CEC clock" -#endif - -/** - * @brief I2C1 frequency. - */ -#if (NUC123_I2C1SW == NUC123_I2C1SW_HSI) || defined(__DOXYGEN__) -#define NUC123_I2C1CLK NUC123_HSICLK -#elif NUC123_I2C1SW == NUC123_I2C1SW_SYSCLK -#define NUC123_I2C1CLK NUC123_SYSCLK -#else -#error "invalid source selected for I2C1 clock" -#endif - -/** - * @brief USART1 frequency. - */ -#if (NUC123_USART1SW == NUC123_USART1SW_PCLK) || defined(__DOXYGEN__) -#define NUC123_USART1CLK NUC123_PCLK -#elif NUC123_USART1SW == NUC123_USART1SW_SYSCLK -#define NUC123_USART1CLK NUC123_SYSCLK -#elif NUC123_USART1SW == NUC123_USART1SW_LSE -#define NUC123_USART1CLK NUC123_LSECLK -#elif NUC123_USART1SW == NUC123_USART1SW_HSI -#define NUC123_USART1CLK NUC123_HSICLK -#else -#error "invalid source selected for USART1 clock" -#endif - -// /** -// * @brief USART2 frequency. -// */ -// #define NUC123_USART2CLK NUC123_PCLK - -// /** -// * @brief USART3 frequency. -// */ -// #define NUC123_USART3CLK NUC123_PCLK - -// /** -// * @brief USART4 frequency. -// */ -// #define NUC123_UART4CLK NUC123_PCLK - -// /** -// * @brief USART5 frequency. -// */ -// #define NUC123_UART5CLK NUC123_PCLK - -// /** -// * @brief USART6 frequency. -// */ -// #define NUC123_USART6CLK NUC123_PCLK - -/** - * @brief Timers clock. - */ -#if (NUC123_PPRE == NUC123_PPRE_DIV1) || defined(__DOXYGEN__) -#define NUC123_TIMCLK1 (NUC123_PCLK * 1) -#define NUC123_TIMCLK2 (NUC123_PCLK * 1) -#else -#define NUC123_TIMCLK1 (NUC123_PCLK * 2) -#define NUC123_TIMCLK2 (NUC123_PCLK * 2) -#endif - -/** - * @brief Flash settings. - */ -#if (NUC123_HCLK <= 24000000) || defined(__DOXYGEN__) -#define NUC123_FLASHBITS 0x00000010 -#else -#define NUC123_FLASHBITS 0x00000011 #endif /* - * For compatibility with driver assuming a specific PPRE clock. + * PLL checks */ -#define NUC123_PCLK1 NUC123_PCLK -#define NUC123_PCLK2 NUC123_PCLK + +#if NUC123_PLL_ENABLED + +#if !defined(NUC123_PLLCLK) +#error "PLL frequency not defined" +#endif + +#if (NUC123_PLLCLK < NUC123_PLLCLK_MIN) || \ + (NUC123_PLLCLK > NUC123_PLLCLK_MAX) +#error \ + "NUC123_PLLCLK outside acceptable range (NUC123_PLLCLK_MIN...NUC123_PLLCLK_MAX)" +#endif +#endif /* NUC123_PLL_ENABLED */ + +/* + * HCLK checks. + */ + +#if (NUC123_HCLKDIV < NUC123_HCLKDIV_MIN || \ + NUC123_HCLKDIV > NUC123_HCLKDIV_MAX) +#error \ + "NUC123_HCLKDIV outside acceptable range (NUC123_HCLKDIV_MIN...NUC123_HCLDIV_MAX)" +#endif + +#if NUC123_HCLKSRC == NUC123_HCLKSRC_HSE + +#if !NUC123_HSE_ENABLED +#error "Cannot use HSE as a HCLK source if it is disabled." +#endif + +#define NUC123_HCLK (NUC123_HSECLK / NUC123_HCLKDIV) + +#elif NUC123_HCLKSRC == NUC123_HCLKSRC_PLL_2 + +#if !NUC123_PLL_ENABLED +#error "Cannot use PLL as a HCLK source if it is disabled." +#endif + +#define NUC123_HCLK (NUC123_PLLCLK / 2) + +#elif NUC123_HCLKSRC == NUC123_HCLKSRC_PLL + +#if !NUC123_PLL_ENABLED +#error "Cannot use PLL as a HCLK source if it is disabled." +#endif + +#define NUC123_HCLK (NUC123_PLLCLK / NUC123_HCLKDIV) + +#elif NUC123_HCLKSRC == NUC123_HCLKSRC_LSI + +#if !NUC123_LSI_ENABLED +#error "Cannot use LSI as a HCLK source if it is disabled." +#endif + +#define NUC123_HCLK (NUC123_LSICLK / NUC123_HCLKDIV) + +#elif NUC123_HCLKSRC == NUC123_HCLKSRC_HSI +#if !NUC123_HSI_ENABLED +#error "Cannot use HSI as a HCLK source if it is disabled." +#endif + +#define NUC123_HCLK (NUC123_HSICLK / NUC123_HCLKDIV) + +#endif /*===========================================================================*/ /* Driver data structures and types. */ @@ -733,17 +277,18 @@ /*===========================================================================*/ /* Driver macros. */ /*===========================================================================*/ +/* Alias for compatibility */ +#define SystemUnlockReg() UNLOCKREG() /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ -/* Various helpers.*/ -#include "nvic.h" +/* Various helpers */ +#include "NUC123.h" #include "nuc123_isr.h" -//#include "nuc123_dma.h" -#include "hal_clks_lld.h" -#include "hal_pwm_lld.h" +#include "nuc123_registry.h" +#include "nvic.h" #ifdef __cplusplus extern "C" { @@ -754,6 +299,6 @@ extern "C" { } #endif -#endif /* HAL_LLD_H */ +#endif /* _HAL_LLD_H_ */ /** @} */ diff --git a/os/hal/ports/NUMICRO/NUC123SD4AN0/nuc123_registry.h b/os/hal/ports/NUMICRO/NUC123SD4AN0/nuc123_registry.h index 13c8691e..552950b5 100644 --- a/os/hal/ports/NUMICRO/NUC123SD4AN0/nuc123_registry.h +++ b/os/hal/ports/NUMICRO/NUC123SD4AN0/nuc123_registry.h @@ -253,8 +253,12 @@ #define NUC123_HAS_CRC TRUE #define NUC123_CRC_PROGRAMMABLE FALSE +/* +This currently correspond to the header guards, and gets tripped on double inclusion. +This does not seem correct. #else #error "NUC123SD4AN0 device not specified" +*/ /** @} */ diff --git a/os/hal/ports/NUMICRO/NUC123SD4AN0/platform.mk b/os/hal/ports/NUMICRO/NUC123SD4AN0/platform.mk index ee94b4e0..48241805 100644 --- a/os/hal/ports/NUMICRO/NUC123SD4AN0/platform.mk +++ b/os/hal/ports/NUMICRO/NUC123SD4AN0/platform.mk @@ -1,7 +1,5 @@ -# Required platform files. PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ - $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/NUC123SD4AN0/hal_lld.c \ - $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/NUC123SD4AN0/system_NUC123SD4AN0.c + $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/NUC123SD4AN0/hal_lld.c # Required include directories. PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ @@ -15,7 +13,10 @@ HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define")) endif # Drivers compatible with the platform. -include $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/CLKv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/GPIOv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/TIMv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/USBv1/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC) +ALLINC += $(PLATFORMINC) \ No newline at end of file