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[STM32 NAND] Deleted ugly hack with EXTI interrupt instead of NAND one

This commit is contained in:
barthess 2016-08-16 18:00:59 +03:00
parent eff62993d3
commit e1601e0a7d
9 changed files with 71 additions and 167 deletions
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18
os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h
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@ -587,19 +587,14 @@
PIN_OSPEED_100M(GPIOD_MEM_D0) | \
PIN_OSPEED_100M(GPIOD_MEM_D1))
#if STM32_NAND_USE_EXT_INT
#define NAND_RB_NWAIT_PUPDR(pin) (PIN_PUPDR_PULLUP(pin))
#else
#define NAND_RB_NWAIT_PUPDR(pin) (PIN_PUPDR_FLOATING(pin))
#endif
#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_MEM_D2) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_D3) | \
PIN_PUPDR_FLOATING(GPIOD_PIN2) | \
PIN_PUPDR_FLOATING(GPIOD_PIN3) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_OE) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_WE) | \
NAND_RB_NWAIT_PUPDR(GPIOD_NAND_RB_NWAIT) | \
PIN_PUPDR_PULLUP(GPIOD_NAND_CE1) | \
PIN_PUPDR_FLOATING(GPIOD_NAND_RB_NWAIT) |\
PIN_PUPDR_PULLUP(GPIOD_NAND_CE1) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_D13) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_D14) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_D15) | \
@ -893,21 +888,16 @@
PIN_OSPEED_100M(GPIOG_PIN14) | \
PIN_OSPEED_100M(GPIOG_PIN15))
#if STM32_NAND_USE_EXT_INT
#define NAND_RB1_PUPDR(pin) (PIN_PUPDR_FLOATING(pin))
#else
#define NAND_RB1_PUPDR(pin) (PIN_PUPDR_PULLUP(pin))
#endif
#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_MEM_A10) | \
PIN_PUPDR_FLOATING(GPIOG_MEM_A11) | \
PIN_PUPDR_FLOATING(GPIOG_MEM_A12) | \
PIN_PUPDR_FLOATING(GPIOG_MEM_A13) | \
PIN_PUPDR_FLOATING(GPIOG_MEM_A14) | \
PIN_PUPDR_FLOATING(GPIOG_MEM_A15) | \
NAND_RB1_PUPDR(GPIOG_NAND_RB1) | \
PIN_PUPDR_PULLUP(GPIOG_NAND_RB1) | \
PIN_PUPDR_FLOATING(GPIOG_NAND_RB2) | \
PIN_PUPDR_FLOATING(GPIOG_PIN8) | \
PIN_PUPDR_PULLUP(GPIOG_NAND_CE2) | \
PIN_PUPDR_PULLUP(GPIOG_NAND_CE2) | \
PIN_PUPDR_FLOATING(GPIOG_PIN10) | \
PIN_PUPDR_FLOATING(GPIOG_PIN11) | \
PIN_PUPDR_FLOATING(GPIOG_SRAM_CS1) | \

6
os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
View File

@ -125,7 +125,7 @@ void fsmc_start(FSMCDriver *fsmcp) {
rccResetFSMC();
#endif
rccEnableFSMC(FALSE);
#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND)
#if HAL_USE_NAND
nvicEnableVector(STM32_FSMC_NUMBER, STM32_FSMC_FSMC1_IRQ_PRIORITY);
#endif
}
@ -153,7 +153,7 @@ void fsmc_stop(FSMCDriver *fsmcp) {
/* Disables the peripheral.*/
#if STM32_FSMC_USE_FSMC1
if (&FSMCD1 == fsmcp) {
#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND)
#if HAL_USE_NAND
nvicDisableVector(STM32_FSMC_NUMBER);
#endif
rccDisableFSMC(FALSE);
@ -164,7 +164,6 @@ void fsmc_stop(FSMCDriver *fsmcp) {
}
}
#if !STM32_NAND_USE_EXT_INT
/**
* @brief FSMC shared interrupt handler.
*
@ -185,7 +184,6 @@ CH_IRQ_HANDLER(STM32_FSMC_HANDLER) {
#endif
CH_IRQ_EPILOGUE();
}
#endif /* !STM32_NAND_USE_EXT_INT */
#endif /* HAL_USE_FSMC */

9
os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
View File

@ -247,15 +247,6 @@ typedef struct {
#define STM32_FSMC_USE_FSMC1 FALSE
#endif
/**
* @brief Internal FSMC interrupt enable switch
* @details MCUs in 100-pin package has no dedicated interrupt pin for FSMC.
* You have to use EXTI module instead to workaround this issue.
*/
#if !defined(STM32_NAND_USE_EXT_INT) || defined(__DOXYGEN__)
#define STM32_NAND_USE_EXT_INT FALSE
#endif
/** @} */
/*===========================================================================*/

14
os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c
View File

@ -117,13 +117,10 @@ static uint32_t calc_eccps(NANDDriver *nandp) {
* @notapi
*/
static void nand_ready_isr_enable(NANDDriver *nandp) {
#if STM32_NAND_USE_EXT_INT
nandp->config->ext_nand_isr_enable();
#else
nandp->nand->SR &= ~(FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS |
FSMC_SR_ILEN | FSMC_SR_IFEN);
FSMC_SR_ILEN | FSMC_SR_IFEN);
nandp->nand->SR |= FSMC_SR_IREN;
#endif
}
/**
@ -134,11 +131,8 @@ static void nand_ready_isr_enable(NANDDriver *nandp) {
* @notapi
*/
static void nand_ready_isr_disable(NANDDriver *nandp) {
#if STM32_NAND_USE_EXT_INT
nandp->config->ext_nand_isr_disable();
#else
nandp->nand->SR &= ~FSMC_SR_IREN;
#endif
}
/**
@ -152,10 +146,8 @@ static void nand_isr_handler (NANDDriver *nandp) {
osalSysLockFromISR();
#if !STM32_NAND_USE_EXT_INT
osalDbgCheck(nandp->nand->SR & FSMC_SR_IRS); /* spurious interrupt happened */
nandp->nand->SR &= ~FSMC_SR_IRS;
#endif
switch (nandp->state){
case NAND_READ:

21
os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h
View File

@ -120,10 +120,6 @@
#error "FSMC not present in the selected device"
#endif
#if STM32_NAND_USE_EXT_INT && !HAL_USE_EXT
#error "External interrupt controller must be enabled to use this feature"
#endif
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#endif
@ -142,13 +138,6 @@ typedef struct NANDDriver NANDDriver;
*/
typedef void (*nandisrhandler_t)(NANDDriver *nandp);
#if STM32_NAND_USE_EXT_INT
/**
* @brief Type of function switching external interrupts on and off.
*/
typedef void (*nandisrswitch_t)(void);
#endif /* STM32_NAND_USE_EXT_INT */
/**
* @brief Driver configuration structure.
* @note It could be empty on some architectures.
@ -188,16 +177,6 @@ typedef struct {
* from STMicroelectronics.
*/
uint32_t pmem;
#if STM32_NAND_USE_EXT_INT
/**
* @brief Function enabling interrupts from EXTI
*/
nandisrswitch_t ext_nand_isr_enable;
/**
* @brief Function disabling interrupts from EXTI
*/
nandisrswitch_t ext_nand_isr_disable;
#endif /* STM32_NAND_USE_EXT_INT */
} NANDConfig;
/**

1
testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_spi.c
View File

@ -53,6 +53,7 @@ static const SPIConfig spicfg = {
GPIOA,
GPIOA_SPI1_NSS,
0, //SPI_CR1_BR_1 | SPI_CR1_BR_0
0
};
static uint32_t ints;

2
testhal/STM32/STM32F4xx/FSMC_NAND/halconf.h
View File

@ -62,7 +62,7 @@
* @brief Enables the EXT subsystem.
*/
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
#define HAL_USE_EXT TRUE
#define HAL_USE_EXT FALSE
#endif
/**

166
testhal/STM32/STM32F4xx/FSMC_NAND/main.c
View File

@ -56,8 +56,6 @@
******************************************************************************
*/
#define USE_BAD_MAP TRUE
#define USE_KILL_BLOCK_TEST FALSE
#define FSMCNAND_TIME_SET ((uint32_t) 2) //(8nS)
@ -74,7 +72,7 @@
#define NAND_COL_WRITE_CYCLES 2
#define NAND_TEST_START_BLOCK 1200
#define NAND_TEST_END_BLOCK 1220
#define NAND_TEST_END_BLOCK 1300
#if USE_KILL_BLOCK_TEST
#define NAND_TEST_KILL_BLOCK 8000
@ -88,6 +86,8 @@
#error "You should enable at least one NAND interface"
#endif
#define BAD_MAP_LEN (NAND_BLOCKS_COUNT / (sizeof(bitmap_word_t) * 8))
/*
******************************************************************************
* EXTERNS
@ -99,11 +99,6 @@
* PROTOTYPES
******************************************************************************
*/
#if STM32_NAND_USE_EXT_INT
static void ready_isr_enable(void);
static void ready_isr_disable(void);
static void nand_ready_cb(EXTDriver *extp, expchannel_t channel);
#endif
/*
******************************************************************************
@ -126,14 +121,14 @@ static time_measurement_t tmu_read_data;
static time_measurement_t tmu_read_spare;
static time_measurement_t tmu_driver_start;
#if USE_BAD_MAP
#define BAD_MAP_LEN (NAND_BLOCKS_COUNT / (sizeof(bitmap_word_t) * 8))
/*
*
*/
static bitmap_word_t badblock_map_array[BAD_MAP_LEN];
static bitmap_t badblock_map = {
badblock_map_array,
BAD_MAP_LEN
};
#endif
/*
*
@ -147,47 +142,11 @@ static const NANDConfig nandcfg = {
NAND_COL_WRITE_CYCLES,
/* stm32 specific fields */
((FSMCNAND_TIME_HIZ << 24) | (FSMCNAND_TIME_HOLD << 16) | \
(FSMCNAND_TIME_WAIT << 8) | FSMCNAND_TIME_SET),
#if STM32_NAND_USE_EXT_INT
ready_isr_enable,
ready_isr_disable
#endif
(FSMCNAND_TIME_WAIT << 8) | FSMCNAND_TIME_SET)
};
/**
*
*/
#if STM32_NAND_USE_EXT_INT
static const EXTConfig extcfg = {
{
{EXT_CH_MODE_DISABLED, NULL}, //0
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL}, //4
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_RISING_EDGE | EXT_MODE_GPIOD, nand_ready_cb},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL}, //8
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL}, //12
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL}, //16
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL}, //20
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
}
};
#endif /* STM32_NAND_USE_EXT_INT */
static volatile uint32_t BackgroundThdCnt = 0;
static thread_reference_t background_thd_ptr = NULL;
#if USE_KILL_BLOCK_TEST
static uint32_t KillCycle = 0;
@ -202,25 +161,10 @@ static uint32_t KillCycle = 0;
*/
static void nand_wp_assert(void) {palClearPad(GPIOB, GPIOB_NAND_WP);}
static void nand_wp_release(void) {palSetPad(GPIOB, GPIOB_NAND_WP);}
static void red_led_on(void) {palSetPad(GPIOI, GPIOI_LED_R);}
//static void red_led_on(void) {palSetPad(GPIOI, GPIOI_LED_R);}
static void red_led_off(void) {palClearPad(GPIOI, GPIOI_LED_R);}
#if STM32_NAND_USE_EXT_INT
static void nand_ready_cb(EXTDriver *extp, expchannel_t channel){
(void)extp;
(void)channel;
NAND.isr_handler(&NAND);
}
static void ready_isr_enable(void) {
extChannelEnable(&EXTD1, GPIOD_NAND_RB_NWAIT);
}
static void ready_isr_disable(void) {
extChannelDisable(&EXTD1, GPIOD_NAND_RB_NWAIT);
}
#endif /* STM32_NAND_USE_EXT_INT */
static void red_led_toggle(void) {palTogglePad(GPIOI, GPIOI_LED_R);}
static void green_led_toggle(void) {palTogglePad(GPIOI, GPIOI_LED_G);}
/**
*
@ -467,8 +411,6 @@ static void general_test (NANDDriver *nandp, size_t first,
uint8_t op_status;
uint32_t recc, wecc;
red_led_on();
/* initialize time measurement units */
chTMObjectInit(&tmu_erase);
chTMObjectInit(&tmu_write_data);
@ -478,6 +420,7 @@ static void general_test (NANDDriver *nandp, size_t first,
/* perform basic checks */
for (block=first; block<last; block++){
red_led_toggle();
if (!nandIsBad(nandp, block)){
if (!is_erased(nandp, block)){
op_status = nandErase(nandp, block);
@ -488,6 +431,7 @@ static void general_test (NANDDriver *nandp, size_t first,
/* write block with pattern, read it back and compare */
for (block=first; block<last; block++){
red_led_toggle();
if (!nandIsBad(nandp, block)){
for (page=0; page<nandp->config->pages_per_block; page++){
pattern_fill();
@ -538,17 +482,10 @@ static void general_test (NANDDriver *nandp, size_t first,
red_led_off();
}
/*
******************************************************************************
* EXPORTED FUNCTIONS
******************************************************************************
*
*/
/*
* Application entry point.
*/
int main(void) {
static void nand_test(bool use_badblock_map) {
/* performance counters */
int32_t adc_ints = 0;
@ -560,40 +497,26 @@ int main(void) {
uint32_t background_cnt = 0;
systime_t T = 0;
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
#if STM32_NAND_USE_EXT_INT
extStart(&EXTD1, &extcfg);
#endif
chTMObjectInit(&tmu_driver_start);
chTMStartMeasurementX(&tmu_driver_start);
#if USE_BAD_MAP
nandStart(&NAND, &nandcfg, &badblock_map);
#else
nandStart(&NAND, &nandcfg, NULL);
#endif
if (use_badblock_map) {
nandStart(&NAND, &nandcfg, &badblock_map);
}
else {
nandStart(&NAND, &nandcfg, NULL);
}
chTMStopMeasurementX(&tmu_driver_start);
chThdSleepMilliseconds(4000);
chThdCreateStatic(BackgroundThreadWA,
sizeof(BackgroundThreadWA),
NORMALPRIO - 20,
BackgroundThread,
NULL);
nand_wp_release();
BackgroundThdCnt = 0;
if (NULL != background_thd_ptr) {
background_thd_ptr = chThdCreateStatic(BackgroundThreadWA,
sizeof(BackgroundThreadWA), NORMALPRIO - 10, BackgroundThread, NULL);
}
/*
* run NAND test in parallel with DMA load and background thread
* run NAND test in parallel with DMA loads and background thread
*/
dma_storm_adc_start();
dma_storm_uart_start();
@ -601,9 +524,9 @@ int main(void) {
T = chVTGetSystemTimeX();
general_test(&NAND, NAND_TEST_START_BLOCK, NAND_TEST_END_BLOCK, 1);
T = chVTGetSystemTimeX() - T;
adc_ints = dma_storm_adc_stop();
adc_ints = dma_storm_adc_stop();
uart_ints = dma_storm_uart_stop();
spi_ints = dma_storm_spi_stop();
spi_ints = dma_storm_spi_stop();
chSysLock();
background_cnt = BackgroundThdCnt;
BackgroundThdCnt = 0;
@ -632,6 +555,35 @@ int main(void) {
* perform ECC calculation test
*/
ecc_test(&NAND, NAND_TEST_END_BLOCK);
}
/*
******************************************************************************
* EXPORTED FUNCTIONS
******************************************************************************
*/
/*
* Application entry point.
*/
int main(void) {
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
nand_wp_release();
nand_test(true);
nand_test(false);
#if USE_KILL_BLOCK_TEST
kill_block(&NAND, NAND_TEST_KILL_BLOCK);
@ -642,7 +594,9 @@ int main(void) {
/*
* Normal main() thread activity, in this demo it does nothing.
*/
red_led_off();
while (true) {
green_led_toggle();
chThdSleepMilliseconds(500);
}
}

1
testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h
View File

@ -26,7 +26,6 @@
*/
#define STM32_NAND_USE_FSMC_NAND1 TRUE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0
#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")