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Added New MCU Serial for WB.

This commit is contained in:
wb-joy 2022-03-22 13:15:39 +08:00
parent e41721b202
commit e16ee1dab8
11 changed files with 6674 additions and 0 deletions
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4335
os/common/ext/CMSIS/WB32/WB32FQ95xx/wb32fq95xx.h Normal file
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os/common/startup/ARMCMx/compilers/GCC/ld/WB32FQ95xC.ld Normal file
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/*
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* WB32FQ95xC memory setup.
*/
MEMORY
{
flash0 (rx) : org = 0x08000000, len = 256k
flash1 (rx) : org = 0x00000000, len = 0
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 36k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld

19
os/common/startup/ARMCMx/compilers/GCC/mk/startup_wb32fq95xx.mk Normal file
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# List of the ChibiOS generic WB32FQ95xx startup and CMSIS files.
STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \
$(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/WB32FQ95xx \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
$(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/WB32/WB32FQ95xx
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLXASMSRC += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

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os/common/startup/ARMCMx/devices/WB32FQ95xx/cmparams.h Normal file
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/*
ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio.
(C) 2015 RedoX https://github.com/RedoXyde
(C) 2021 Westberry Technology (ChangZhou) Corp., Ltd
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file WB32FQ95xx/cmparams.h
* @brief ARM Cortex-M3 parameters for the Westberry WB32FQ95xx
*
* @defgroup ARMCMx_WB32FQ95xx Westberry WB32FQ95xx Specific Parameters
* @ingroup ARMCMx_SPECIFIC
* @details This file contains the Cortex-M3 specific parameters for the
* Westberry WB32FQ95xx platform.
* @{
*/
#ifndef _CMPARAMS_H_
#define _CMPARAMS_H_
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL 3
/**
* @brief Systick unit presence.
*/
#define CORTEX_HAS_ST TRUE
/**
* @brief Floating Point unit presence.
*/
#define CORTEX_HAS_FPU FALSE
/**
* @brief Number of bits in priority masks.
*/
#define CORTEX_PRIORITY_BITS 4
/**
* @brief Number of interrupt vectors.
* @note This number does not include the 16 system vectors and must be
* rounded to a multiple of 8.
*/
#define CORTEX_NUM_VECTORS 40
/* The following code is not processed when the file is included from an
asm module.*/
#if !defined(_FROM_ASM_)
#if !defined (WB32FQ95xx)
#include "board.h"
#endif
/* Including the device CMSIS header. Note, we are not using the definitions
from this header because we need this file to be usable also from
assembler source files. We verify that the info matches instead.*/
#include "WB32fq95xx.h"
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
#endif
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
#error "CMSIS __NVIC_PRIO_BITS mismatch"
#endif
#endif /* !defined(_FROM_ASM_) */
#endif /* _CMPARAMS_H_ */
/** @} */

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os/hal/ports/WB32/WB32FQ95xx/hal_lld.c Normal file
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/*
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file WB32FQ95xx/hal_lld.c
* @brief WB32FQ95xx HAL subsystem low level driver source.
*
* @addtogroup HAL
* @{
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/**
* @brief System Clock Frequency (Core Clock)
*/
uint32_t SystemCoreClock = WB32_MAINCLK;
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
void SystemCoreClockUpdate(void);
SystemCoreClockUpdate();
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
* @param None
* @return None
*/
void SystemCoreClockUpdate(void) {
uint32_t ahbprediv, pllprediv, pllmul, mainclk;
switch (RCC->MAINCLKSRC) {
case 0x00: /* MHSI used as main clock */
mainclk = 8000000;
break;
case 0x01: /* FHSI used as main clock */
mainclk = 48000000;
break;
case 0x03: /* HSE used as main clock */
mainclk = WB32_HSECLK;
break;
case 0x02: /* PLL used as main clock */
pllprediv =
(((RCC->PLLPRE & (RCC_PLLPRE_RATIO_Msk | RCC_PLLPRE_DIVEN)) + 1) >> 1) + 1;
pllmul = (0x03 - ((ANCTL->PLLCR >> 6) & 0x03)) * 4 + 12;
if (RCC->PLLSRC == RCC_PLLSRC_HSE) {
mainclk = WB32_HSECLK * pllmul / pllprediv;
}
else {
mainclk = 8000000 * pllmul / pllprediv;
}
break;
default:
mainclk = 8000000;
break;
}
ahbprediv =
(((RCC->AHBPRE & (RCC_AHBPRE_RATIO_Msk | RCC_AHBPRE_DIVEN)) + 1) >> 1) + 1;
SystemCoreClock = mainclk / ahbprediv;
}
#if defined(WB32FQ95xx)
/**
* @brief Configures the main clock frequency, AHBCLK, APB1CLK and APB2CLK prescalers.
* @note This function should be used only after reset.
* @param None
* @return None
*/
static void SetSysClock(void) {
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* Unlocks write to ANCTL registers */
PWR->ANAKEY1 = 0x03;
PWR->ANAKEY2 = 0x0C;
/* APB1CLK = MAINCLK / WB32_PPRE1*/
RCC->APB1PRE = RCC_APB1PRE_SRCEN;
#if WB32_PPRE1 == 1
RCC->APB1PRE |= 0x00;
#else
RCC->APB1PRE |= (WB32_PPRE1 - 2);
RCC->APB1PRE |= 0x01;
#endif /* WB32_PPRE1 == 1 */
#if WB32_HSE_ENABLED == TRUE
/* Configure PD0 and PD1 to analog mode */
RCC->APB1ENR = RCC_APB1ENR_BMX1EN | RCC_APB1ENR_GPIODEN;
GPIOD->CFGMSK = 0xFFFC;
GPIOD->MODER = 0x0F;
/* Enable HSE */
ANCTL->HSECR1 = ANCTL_HSECR1_PADOEN;
ANCTL->HSECR0 = ANCTL_HSECR0_HSEON;
/* Wait till HSE is ready and if Time out is reached exit */
do {
HSEStatus = ANCTL->HSESR & ANCTL_HSESR_HSERDY;
StartUpCounter++;
} while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if (HSEStatus == 0) {
/* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error */
while (1)
;
}
#endif /* WB32_HSE_ENABLED == TRUE */
/* Configure Flash prefetch, Cache and wait state */
#if WB32_MAINCLK <= 32000000
CACHE->CR = CACHE_CR_LATENCY_0WS;
#elif WB32_MAINCLK <= 48000000
CACHE->CR = CACHE_CR_CHEEN | CACHE_CR_PREFEN_ON | CACHE_CR_LATENCY_1WS;
#elif WB32_MAINCLK <= 72000000
CACHE->CR = CACHE_CR_CHEEN | CACHE_CR_PREFEN_ON | CACHE_CR_LATENCY_2WS;
#else
CACHE->CR = CACHE_CR_CHEEN | CACHE_CR_PREFEN_ON | CACHE_CR_LATENCY_3WS;
#endif
/* AHBCLK = WB32_HPRE */
#if WB32_HPRE == 1
RCC->AHBPRE = 0x00;
#else
RCC->AHBPRE = (WB32_HPRE - 2);
RCC->AHBPRE |= 0x01;
#endif /* WB32_HPRE == 1 */
/* APB2CLK = MAINCLK / WB32_PPRE2 */
RCC->APB2PRE = RCC_APB2PRE_SRCEN;
#if WB32_PPRE2 == 1
RCC->APB2PRE |= 0x00;
#else
RCC->APB2PRE |= (WB32_PPRE2 - 2);
RCC->APB2PRE |= 0x01;
#endif /* WB32_PPRE2 == 1 */
#if WB32_PLL_ENABLED == TRUE
/* PLL configuration:
PLLCLK = WB32_HSECLK / WB32_PLLDIV_VALUE * WB32_PLLMUL_VALUE*/
RCC->PLLSRC = WB32_PLLSRC;
RCC->PLLPRE = RCC_PLLPRE_SRCEN;
#if WB32_PLLDIV_VALUE == 1
RCC->PLLPRE |= 0x00;
#else
RCC->PLLPRE |= (WB32_PLLDIV_VALUE - 2);
RCC->PLLPRE |= 0x01;
#endif /* WB32_PLLDIV_VALUE == 1 */
#if WB32_PLLMUL_VALUE == 12
ANCTL->PLLCR = (0x3U << 6);
#elif WB32_PLLMUL_VALUE == 16
ANCTL->PLLCR = (0x2U << 6);
#elif WB32_PLLMUL_VALUE == 20
ANCTL->PLLCR = (0x1U << 6);
#elif WB32_PLLMUL_VALUE == 24
ANCTL->PLLCR = (0x0U << 6);
#endif
/* Enable PLL */
ANCTL->PLLENR = ANCTL_PLLENR_PLLON;
/* Wait till PLL is ready */
while (ANCTL->PLLSR != 0x03) {
}
#endif /* WB32_PLL_ENABLED == TRUE */
/* Select WB32_MAINCLKSRC as system clock source */
RCC->MAINCLKSRC = WB32_MAINCLKSRC;
RCC->MAINCLKUEN = RCC_MAINCLKUEN_ENA;
/* Locks write to ANCTL registers */
PWR->ANAKEY1 = 0x00;
PWR->ANAKEY2 = 0x00;
}
/**
* @brief Clocks initialization.
* @note None
* @param None
* @return None
*/
void wb32_clock_init(void) {
#if WB32_NO_INIT == FALSE
/* Unlocks write to ANCTL registers */
PWR->ANAKEY1 = 0x03;
PWR->ANAKEY2 = 0x0C;
/* Turn off POR */
ANCTL->PORCR = 0x7BE;
/* Locks write to ANCTL registers */
PWR->ANAKEY1 = 0x00;
PWR->ANAKEY2 = 0x00;
SetSysClock();
rccEnableAPB1(RCC_APB1ENR_BMX1EN);
rccEnableAPB2(RCC_APB2ENR_BMX2EN);
SCB->VTOR = FLASH_BASE; /* Vector Table Relocation in Internal FLASH. */
#endif /* WB32_NO_INIT == FALSE */
}
#if HAL_USE_USB || defined(__DOXYGEN__)
/**
* @brief wb32 usb initialization.
* @param[in] usbp pointer to the @p USBDriver object
* @return None
*/
void wb32_usb_init(USBDriver *usbp) {
/* Clock activation.*/
#if WB32_USB_USE_USB1
if (&USBD1 == usbp) {
RCC->AHBENR1 |= RCC_AHBENR1_CRCSFMEN;
/* Enable USB peripheral clock */
RCC->AHBENR1 |= RCC_AHBENR1_USBEN;
/* Configure USB FIFO clock source */
RCC->USBFIFOCLKSRC = RCC_USBFIFOCLKSRC_USBCLK;
/* Enable USB FIFO clock */
RCC->USBFIFOCLKENR = RCC_USBFIFOCLKENR_CLKEN;
/* Configure and enable USB PHY */
SFM->USBPCON = 0x02;
/* Configure and enable USBCLK */
#if (WB32_USBPRE == WB32_USBPRE_DIV1P5)
RCC->USBCLKENR = RCC_USBCLKENR_CLKEN;
RCC->USBPRE = RCC_USBPRE_SRCEN;
RCC->USBPRE |= RCC_USBPRE_RATIO_1_5;
RCC->USBPRE |= RCC_USBPRE_DIVEN;
#elif (WB32_USBPRE == WB32_USBPRE_DIV1)
RCC->USBCLKENR = RCC_USBCLKENR_CLKEN;
RCC->USBPRE = RCC_USBPRE_SRCEN;
RCC->USBPRE |= 0x00;
#elif (WB32_USBPRE == WB32_USBPRE_DIV2)
RCC->USBCLKENR = RCC_USBCLKENR_CLKEN;
RCC->USBPRE = RCC_USBPRE_SRCEN;
RCC->USBPRE |= RCC_USBPRE_RATIO_2;
RCC->USBPRE |= RCC_USBPRE_DIVEN;
#elif (WB32_USBPRE == WB32_USBPRE_DIV3)
RCC->USBCLKENR = RCC_USBCLKENR_CLKEN;
RCC->USBPRE = RCC_USBPRE_SRCEN;
RCC->USBPRE |= RCC_USBPRE_RATIO_3;
RCC->USBPRE |= RCC_USBPRE_DIVEN;
#else
#error "invalid WB32_USBPRE value specified"
#endif
}
#endif
}
/**
* @brief wb32 usb deinitialization.
* @param[in] usbp pointer to the @p USBDriver object
* @return None
*/
void wb32_usb_deinit(USBDriver *usbp) {
#if WB32_USB_USE_USB1
if (&USBD1 == usbp) {
/* Disable USBCLK */
RCC->USBPRE &= RCC_USBPRE_SRCEN;
RCC->USBPRE = 0x00;
RCC->USBCLKENR = 0x00;
/* Disable USB FIFO clock */
RCC->USBFIFOCLKENR = 0x0000;
/* Disable USB peripheral clock */
RCC->AHBENR1 &= ~RCC_AHBENR1_USBEN;
}
#endif
}
/**
* @brief wb32 usb connect.
* @param[in] usbp pointer to the @p USBDriver object
* @return None
*/
void wb32_usb_connect(USBDriver *usbp) {
/* Enable BMX1, GPIOA clock */
RCC->APB1ENR |= RCC_APB1ENR_BMX1EN | RCC_APB1ENR_GPIOAEN;
GPIOA->CFGMSK = (~(GPIO_CFGMSK_CFGMSK11 | GPIO_CFGMSK_CFGMSK12));
/* Configure the drive current of PA11 and PA12 */
GPIOA->CURRENT = (0x3 << 22) | (0x3 << 24);
/* Configure PA11 and PA12 as Alternate function mode */
GPIOA->MODER = (0x2 << 22) | (0x2 << 24);
GPIOA->OTYPER = 0x00;
GPIOA->OSPEEDR = 0x00;
GPIOA->PUPDR = 0x00;
GPIOA->AFRH = (3 << 12) | (3 << 16);
USB->POWER = USB_POWER_SUSEN;
USB->INTRUSBE = USB_INTRUSBE_RSTIE | USB_INTRUSBE_RSUIE | USB_INTRUSBE_SUSIE;
}
/**
* @brief wb32 usb disconnect.
* @param[in] usbp pointer to the @p USBDriver object
* @return None
*/
void wb32_usb_disconnect(USBDriver *usbp) {
/* Enable BMX1, GPIOA clock */
RCC->APB1ENR |= RCC_APB1ENR_BMX1EN | RCC_APB1ENR_GPIOAEN;
GPIOA->CFGMSK = (~(GPIO_CFGMSK_CFGMSK11 | GPIO_CFGMSK_CFGMSK12));
/* Configure PA11 and PA12 as input mode */
GPIOA->MODER = 0x00;
GPIOA->OSPEEDR = 0x00;
GPIOA->PUPDR = 0x00;
/* Configure PA12(D+) as open-drain output mode and output low level */
GPIOA->CFGMSK = (~GPIO_CFGMSK_CFGMSK12);
GPIOA->MODER = (0x1 << 24);
GPIOA->OTYPER = (0x1 << 12);
GPIOA->AFRH = 0x00;
GPIOA->BSRR = (0x1000 << 16);
}
#endif
#else
#error "not defined wb32_clock_init"
#endif
/** @} */

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/*
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file WB32FQ95xx/hal_lld.h
* @brief WB32FQ95xx HAL subsystem low level driver header.
* @pre This module requires the following macros to be defined in the
* @p board.h file:
* - WB32_LSECLK.
* - WB32_LSE_BYPASS (optionally).
* - WB32_HSECLK.
* - WB32_HSE_BYPASS (optionally).
* .
*
* @addtogroup HAL
* @{
*/
#ifndef HAL_LLD_H
#define HAL_LLD_H
#include "wb32_registry.h"
#include "wb32_tim.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name Platform identification
* @{
*/
#define PLATFORM_NAME "WB32FQ95xx"
/**
* @brief Sub-family identifier.
*/
#if !defined(WB32FQ95xx) || defined(__DOXYGEN__)
#define WB32FQ95xx TRUE
#endif
/** @} */
/**
* @name Absolute Maximum Ratings
* @{
*/
/**
* @brief Maximum HSE clock frequency.
*/
#define WB32_HSECLK_MAX 16000000
/**
* @brief Minimum HSE clock frequency.
*/
#define WB32_HSECLK_MIN 4000000
/**
* @brief Maximum LSE clock frequency.
*/
#define WB32_LSECLK_MAX 1000000
/**
* @brief Minimum LSE clock frequency.
*/
#define WB32_LSECLK_MIN 32768
/**
* @brief Maximum PLLs input clock frequency.
*/
#define WB32_PLLIN_MAX 16000000
/**
* @brief Minimum PLLs input clock frequency.
*/
#define WB32_PLLIN_MIN 2000000
/**
* @brief Maximum PLL output clock frequency.
*/
#define WB32_PLLOUT_MAX 96000000
/**
* @brief Minimum PLL output clock frequency.
*/
#define WB32_PLLOUT_MIN 48000000
/**
* @brief Maximum APB1 clock frequency.
*/
#define WB32_PCLK1_MAX 96000000
/**
* @brief Maximum APB2 clock frequency.
*/
#define WB32_PCLK2_MAX 96000000
/** @} */
/**
* @name RCC_MAINCLKSRC register bits definitions
* @{
*/
#define WB32_MAINCLKSRC_MHSI (0)
#define WB32_MAINCLKSRC_FHSI (1)
#define WB32_MAINCLKSRC_PLL (2)
#define WB32_MAINCLKSRC_HSE (3)
/** @} */
/**
* @name RCC_PLLSRC register bits definitions
* @{
*/
#define WB32_PLLSRC_MHSI (0x0U)
#define WB32_PLLSRC_HSE (0x1U)
/** @} */
/**
* @name RCC_USBPRE register bits definitions
* @{
*/
#define WB32_USBPRE_MASK (0x3U << 1)
#define WB32_USBPRE_DIV1 (0x0U)
#define WB32_USBPRE_DIV1P5 (0x5U)
#define WB32_USBPRE_DIV2 (0x1U)
#define WB32_USBPRE_DIV3 (0x3U)
/** @} */
/*===========================================================================*/
/* Platform capabilities. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief Disables the PWR/RCC initialization in the HAL.
*/
#if !defined(WB32_NO_INIT) || defined(__DOXYGEN__)
#define WB32_NO_INIT FALSE
#endif
/**
* @brief Enables or disables the MHSI clock source.
*/
#if !defined(WB32_MHSI_ENABLED) || defined(__DOXYGEN__)
#define WB32_MHSI_ENABLED TRUE
#endif
/**
* @brief Enables or disables the FHSI clock source.
*/
#if !defined(WB32_FHSI_ENABLED) || defined(__DOXYGEN__)
#define WB32_FHSI_ENABLED FALSE
#endif
/**
* @brief Enables or disables the LSI clock source.
*/
#if !defined(WB32_LSI_ENABLED) || defined(__DOXYGEN__)
#define WB32_LSI_ENABLED FALSE
#endif
/**
* @brief Enables or disables the HSE clock source.
*/
#if !defined(WB32_HSE_ENABLED) || defined(__DOXYGEN__)
#define WB32_HSE_ENABLED FALSE
#endif
/**
* @brief Enables or disables the LSE clock source.
*/
#if !defined(WB32_LSE_ENABLED) || defined(__DOXYGEN__)
#define WB32_LSE_ENABLED FALSE
#endif
/**
* @brief Enables or disables the PLL clock source.
*/
#if !defined(WB32_PLL_ENABLED) || defined(__DOXYGEN__)
#define WB32_PLL_ENABLED FALSE
#endif
/**
* @brief Main clock source selection.
* @note If the selected clock source is not the PLL then the PLL is not
* initialized and started.
* @note The default value is calculated for a 96MHz system clock from
* a 8MHz crystal using the PLL.
*/
#if !defined(WB32_MAINCLKSRC) || defined(__DOXYGEN__)
#define WB32_MAINCLKSRC WB32_MAINCLKSRC_PLL
#endif
/**
* @brief Clock source for the PLL.
* @note This setting has only effect if the PLL is selected as the
* system clock source.
*/
#if !defined(WB32_PLLSRC) || defined(__DOXYGEN__)
#define WB32_PLLSRC WB32_PLLSRC_HSE
#endif
/**
* @brief Crystal PLL pre-divider.
* @note This setting has only effect if the PLL is selected as the
* system clock source.
*/
#if !defined(WB32_PLLDIV_VALUE) || defined(__DOXYGEN__)
#define WB32_PLLDIV_VALUE 1
#endif
/**
* @brief PLL multiplier value.
* @note The allowed value is 12, 16, 20, 24.
*/
#if !defined(WB32_PLLMUL_VALUE) || defined(__DOXYGEN__)
#define WB32_PLLMUL_VALUE 12
#endif
/**
* @brief AHB prescaler value.
* @note The default value is calculated for a 96MHz system clock from
* a 8MHz crystal using the PLL.
*/
#if !defined(WB32_HPRE) || defined(__DOXYGEN__)
#define WB32_HPRE 1
#endif
/**
* @brief APB1 prescaler value.
*/
#if !defined(WB32_PPRE1) || defined(__DOXYGEN__)
#define WB32_PPRE1 1
#endif
/**
* @brief APB2 prescaler value.
*/
#if !defined(WB32_PPRE2) || defined(__DOXYGEN__)
#define WB32_PPRE2 1
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*
* Configuration-related checks.
*/
#if !defined(WB32FQ95xx_MCUCONF)
#error "Using a wrong mcuconf.h file, WB32FQ95xx_MCUCONF not defined"
#endif
/*
* MHSI related checks.
*/
#if WB32_MHSI_ENABLED
#else /* !WB32_MHSI_ENABLED */
#if (WB32_MAINCLKSRC == WB32_MAINCLKSRC_MHSI)
#error "MHSI not enabled, required by WB32_MAINCLKSRC"
#endif
#if (WB32_MAINCLKSRC == WB32_MAINCLKSRC_PLL) && \
(WB32_PLLSRC == WB32_PLLSRC_MHSI)
#error "MHSI not enabled, required by WB32_MAINCLKSRC and WB32_PLLSRC"
#endif
#endif
/*
* FHSI related checks.
*/
#if WB32_FHSI_ENABLED
#else /* !WB32_FHSI_ENABLED */
#if (WB32_MAINCLKSRC == WB32_MAINCLKSRC_FHSI)
#error "FHSI not enabled, required by WB32_MAINCLKSRC"
#endif
#endif /* !WB32_FHSI_ENABLED */
/*
* HSE related checks.
*/
#if WB32_HSE_ENABLED
#if WB32_HSECLK == 0
#error "HSE frequency not defined"
#elif (WB32_HSECLK < WB32_HSECLK_MIN) || (WB32_HSECLK > WB32_HSECLK_MAX)
#error "WB32_HSECLK outside acceptable range (WB32_HSECLK_MIN...WB32_HSECLK_MAX)"
#endif
#else /* !WB32_HSE_ENABLED */
#if (WB32_MAINCLKSRC == WB32_MAINCLKSRC_HSE)
#error "HSE not enabled, required by WB32_MAINCLKSRC"
#endif
#if ((WB32_MAINCLKSRC == WB32_MAINCLKSRC_PLL) && (WB32_PLLSRC == WB32_PLLSRC_HSE))
#error "HSE not enabled, required by WB32_MAINCLKSRC and WB32_PLLSRC"
#endif
#endif /* !WB32_HSE_ENABLED */
/*
* LSI related checks.
*/
#if WB32_LSI_ENABLED
#else /* !WB32_LSI_ENABLED */
#endif /* !WB32_LSI_ENABLED */
/*
* LSE related checks.
*/
#if WB32_LSE_ENABLED
#if (WB32_LSECLK == 0)
#error "LSE frequency not defined"
#endif
#if (WB32_LSECLK < WB32_LSECLK_MIN) || (WB32_LSECLK > WB32_LSECLK_MAX)
#error "WB32_LSECLK outside acceptable range (WB32_LSECLK_MIN...WB32_LSECLK_MAX)"
#endif
#else /* !WB32_LSE_ENABLED */
#endif /* !WB32_LSE_ENABLED */
/**
* @brief PLLDIV field.
*/
#if ((WB32_PLLDIV_VALUE >= 1) && (WB32_PLLDIV_VALUE <= 16)) || \
defined(__DOXYGEN__)
#define WB32_PLLDIV WB32_PLLDIV_VALUE
#else
#error "invalid WB32_PLLDIV_VALUE value specified"
#endif
/**
* @brief PLLMUL field.
*/
#if (WB32_PLLMUL_VALUE == 12) || (WB32_PLLMUL_VALUE == 16) || \
(WB32_PLLMUL_VALUE == 20) || (WB32_PLLMUL_VALUE == 24) || \
defined(__DOXYGEN__)
#define WB32_PLLMUL WB32_PLLMUL_VALUE
#else
#error "invalid WB32_PLLMUL_VALUE value specified"
#endif
/**
* @brief PLL input clock frequency.
*/
#if (WB32_PLLSRC == WB32_PLLSRC_HSE) || defined(__DOXYGEN__)
#define WB32_PLLCLKIN (WB32_HSECLK / WB32_PLLDIV_VALUE)
#elif (WB32_PLLSRC == WB32_PLLSRC_MHSI)
#define WB32_PLLCLKIN (8000000 / WB32_PLLDIV_VALUE)
#else
#error "invalid WB32_PLLSRC value specified"
#endif
/* PLL input frequency range check.*/
#if (WB32_PLLCLKIN < WB32_PLLIN_MIN) || (WB32_PLLCLKIN > WB32_PLLIN_MAX)
#error "WB32_PLLCLKIN outside acceptable range (WB32_PLLIN_MIN...WB32_PLLIN_MAX)"
#endif
/**
* @brief PLL output clock frequency.
*/
#define WB32_PLLCLKOUT (WB32_PLLCLKIN * WB32_PLLMUL_VALUE)
/* PLL output frequency range check.*/
#if (WB32_PLLCLKOUT < WB32_PLLOUT_MIN) || (WB32_PLLCLKOUT > WB32_PLLOUT_MAX)
#error "WB32_PLLCLKOUT outside acceptable range (WB32_PLLOUT_MIN...WB32_PLLOUT_MAX)"
#endif
/**
* @brief System clock source.
*/
#if (WB32_MAINCLKSRC == WB32_MAINCLKSRC_PLL) || defined(__DOXYGEN__)
#define WB32_MAINCLK WB32_PLLCLKOUT
#elif (WB32_MAINCLKSRC == WB32_MAINCLKSRC_MHSI)
#define WB32_MAINCLK 8000000
#elif (WB32_MAINCLKSRC == WB32_MAINCLKSRC_FHSI)
#define WB32_MAINCLK 48000000
#elif (WB32_MAINCLKSRC == WB32_MAINCLKSRC_HSE)
#define WB32_MAINCLK WB32_HSECLK
#else
#error "invalid WB32_MAINCLKSRC value specified"
#endif
/**
* @brief AHB frequency.
*/
#if ((WB32_HPRE >= 1) && (WB32_HPRE <= 64)) || \
defined(__DOXYGEN__)
#define WB32_HCLK (WB32_MAINCLK / WB32_HPRE)
#else
#error "invalid WB32_HPRE value specified"
#endif
/**
* @brief APB1 frequency.
*/
#if ((WB32_PPRE1 >= 1) && (WB32_PPRE1 <= 64)) || \
defined(__DOXYGEN__)
#define WB32_PCLK1 (WB32_MAINCLK / WB32_PPRE1)
#else
#error "invalid WB32_PPRE1 value specified"
#endif
/* APB1 frequency check.*/
#if WB32_PCLK1 > WB32_PCLK1_MAX
#error "WB32_PCLK1 exceeding maximum frequency (WB32_PCLK1_MAX)"
#endif
/**
* @brief APB2 frequency.
*/
#if ((WB32_PPRE2 >= 1) && (WB32_PPRE2 <= 64)) || \
defined(__DOXYGEN__)
#define WB32_PCLK2 (WB32_MAINCLK / WB32_PPRE2)
#else
#error "invalid WB32_PPRE2 value specified"
#endif
/* APB2 frequency check.*/
#if WB32_PCLK2 > WB32_PCLK2_MAX
#error "WB32_PCLK2 exceeding maximum frequency (WB32_PCLK2_MAX)"
#endif
/**
* @brief USB frequency.
*/
#if (WB32_USBPRE == WB32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
#define WB32_USBCLK ((WB32_MAINCLK * 2) / 3)
#elif (WB32_USBPRE == WB32_USBPRE_DIV1)
#define WB32_USBCLK WB32_MAINCLK
#elif (WB32_USBPRE == WB32_USBPRE_DIV2)
#define WB32_USBCLK (WB32_MAINCLK / 2)
#elif (WB32_USBPRE == WB32_USBPRE_DIV3)
#define WB32_USBCLK (WB32_MAINCLK / 3)
#else
#error "invalid WB32_USBPRE value specified"
#endif
/**
* @brief Timers 1, 2, 3, 4 clock.
*/
#define WB32_TIMCLK1 WB32_PCLK1
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
/* Various helpers.*/
#include "nvic.h"
#include "wb32_isr.h"
#include "wb32_rcc.h"
#ifdef __cplusplus
extern "C" {
#endif
void hal_lld_init(void);
void wb32_clock_init(void);
#ifdef __cplusplus
}
#endif
#endif /* HAL_LLD_H */
/** @} */

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# Required platform files.
PLATFORMSRC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
$(CHIBIOS_CONTRIB)/os/hal/ports/WB32/WB32FQ95xx/hal_lld.c \
$(CHIBIOS_CONTRIB)/os/hal/ports/WB32/WB32FQ95xx/wb32_isr.c
# Required include directories.
PLATFORMINC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
$(CHIBIOS_CONTRIB)/os/hal/ports/WB32/WB32FQ95xx
ifeq ($(USE_SMART_BUILD),yes)
# Configuration files directory
ifeq ($(HALCONFDIR),)
ifeq ($(CONFDIR),)
HALCONFDIR = .
else
HALCONFDIR := $(CONFDIR)
endif
endif
HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define"))
endif #ifeq ($(USE_SMART_BUILD), yes)
# Drivers compatible with the platform.
include ${CHIBIOS_CONTRIB}/os/hal/ports/WB32/LLD/GPIOv1/driver.mk
include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/TIMv1/driver.mk
include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/I2Cv1/driver.mk
include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/UARTv1/driver.mk
include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/SPIv1/driver.mk
include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/USBv1/driver.mk
# Shared variables
ALLCSRC += $(PLATFORMSRC_CONTRIB)
ALLINC += $(PLATFORMINC_CONTRIB)

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/*
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file WB32FQ95xx/wb32_isr.c
* @brief WB32FQ95xx ISR handler code.
*
* @addtogroup WB32FQ95xx_ISR
* @{
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
#define exti_serve_irq(pr, channel) { \
if ((pr) & (1U << (channel))) { \
_pal_isr_code(channel); \
} \
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__)
#if !defined(WB32_DISABLE_EXTI0_HANDLER)
/**
* @brief EXTI[0] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(WB32_EXTI0_IRQ_VECTOR) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & EXTI_IMR_MR0;
EXTI->PR = pr;
exti_serve_irq(pr, 0);
OSAL_IRQ_EPILOGUE();
}
#endif
#if !defined(WB32_DISABLE_EXTI1_HANDLER)
/**
* @brief EXTI[1] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(WB32_EXTI1_IRQ_VECTOR) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & EXTI_IMR_MR1;
EXTI->PR = pr;
exti_serve_irq(pr, 1);
OSAL_IRQ_EPILOGUE();
}
#endif
#if !defined(WB32_DISABLE_EXTI2_HANDLER)
/**
* @brief EXTI[2] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(WB32_EXTI2_IRQ_VECTOR) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & EXTI_IMR_MR2;
EXTI->PR = pr;
exti_serve_irq(pr, 2);
OSAL_IRQ_EPILOGUE();
}
#endif
#if !defined(WB32_DISABLE_EXTI3_HANDLER)
/**
* @brief EXTI[3] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(WB32_EXTI3_IRQ_VECTOR) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & EXTI_IMR_MR3;
EXTI->PR = pr;
exti_serve_irq(pr, 3);
OSAL_IRQ_EPILOGUE();
}
#endif
#if !defined(WB32_DISABLE_EXTI4_HANDLER)
/**
* @brief EXTI[4] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(WB32_EXTI4_IRQ_VECTOR) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & EXTI_IMR_MR4;
EXTI->PR = pr;
exti_serve_irq(pr, 4);
OSAL_IRQ_EPILOGUE();
}
#endif
#if !defined(WB32_DISABLE_EXTI9_5_HANDLER)
/**
* @brief EXTI[5]...EXTI[9] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(WB32_EXTI9_5_IRQ_VECTOR) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & (EXTI_IMR_MR5 | EXTI_IMR_MR6 | EXTI_IMR_MR7 | EXTI_IMR_MR8 |
EXTI_IMR_MR9);
EXTI->PR = pr;
exti_serve_irq(pr, 5);
exti_serve_irq(pr, 6);
exti_serve_irq(pr, 7);
exti_serve_irq(pr, 8);
exti_serve_irq(pr, 9);
OSAL_IRQ_EPILOGUE();
}
#endif
#if !defined(WB32_DISABLE_EXTI15_10_HANDLER)
/**
* @brief EXTI[10]...EXTI[15] interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(WB32_EXTI15_10_IRQ_VECTOR) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & (EXTI_IMR_MR10 | EXTI_IMR_MR11 | EXTI_IMR_MR12 |
EXTI_IMR_MR13 | EXTI_IMR_MR14 | EXTI_IMR_MR15);
EXTI->PR = pr;
exti_serve_irq(pr, 10);
exti_serve_irq(pr, 11);
exti_serve_irq(pr, 12);
exti_serve_irq(pr, 13);
exti_serve_irq(pr, 14);
exti_serve_irq(pr, 15);
OSAL_IRQ_EPILOGUE();
}
#endif
#endif /* HAL_USE_PAL */
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Enables IRQ sources.
*
* @notapi
*/
void irqInit(void) {
#if HAL_USE_PAL
nvicEnableVector(EXTI0_IRQn, WB32_IRQ_EXTI0_PRIORITY);
nvicEnableVector(EXTI1_IRQn, WB32_IRQ_EXTI1_PRIORITY);
nvicEnableVector(EXTI2_IRQn, WB32_IRQ_EXTI2_PRIORITY);
nvicEnableVector(EXTI3_IRQn, WB32_IRQ_EXTI3_PRIORITY);
nvicEnableVector(EXTI4_IRQn, WB32_IRQ_EXTI4_PRIORITY);
nvicEnableVector(EXTI9_5_IRQn, WB32_IRQ_EXTI5_9_PRIORITY);
nvicEnableVector(EXTI15_10_IRQn, WB32_IRQ_EXTI10_15_PRIORITY);
#endif
}
/**
* @brief Disables IRQ sources.
*
* @notapi
*/
void irqDeinit(void) {
#if HAL_USE_PAL
nvicDisableVector(EXTI0_IRQn);
nvicDisableVector(EXTI1_IRQn);
nvicDisableVector(EXTI2_IRQn);
nvicDisableVector(EXTI3_IRQn);
nvicDisableVector(EXTI4_IRQn);
nvicDisableVector(EXTI9_5_IRQn);
nvicDisableVector(EXTI15_10_IRQn);
#endif
}
/** @} */

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/*
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file WB32FQ95xx/wb32_isr.h
* @brief WB32FQ95xx ISR handler header.
*
* @addtogroup WB32FQ95xx_ISR
* @{
*/
#ifndef WB32_ISR_H
#define WB32_ISR_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name ISR names and numbers remapping
* @{
*/
/*
* IWDG units.
*/
#define WB32_WWDG_IRQ_VECTOR Vector40
#define WB32_WWDG_NUMBER 0
/*
* PVD units.
*/
#define WB32_PVD_IRQ_VECTOR Vector44
#define WB32_PVD_NUMBER 1
/*
* TAMPER units.
*/
#define WB32_TAMPER_IRQ_VECTOR Vector48
#define WB32_TAMPER_NUMBER 2
/*
* RTC units.
*/
#define WB32_RTC_IRQ_VECTOR Vector4C
#define WB32_RTC_NUMBER 3
#define WB32_RTCAlarm_IRQ_VECTOR VectorC8
#define WB32_RTCAlarm_NUMBER 34
/*
* FMC units.
*/
#define WB32_FMC_IRQ_VECTOR Vector50
#define WB32_FMC_NUMBER 4
#define WB32_RCC_IRQ_VECTOR Vector54
#define WB32_RCC_NUMBER 5
/*
* EXTI units.
*/
#define WB32_EXTI0_IRQ_VECTOR Vector58
#define WB32_EXTI0_NUMBER 6
#define WB32_EXTI1_IRQ_VECTOR Vector5C
#define WB32_EXTI1_NUMBER 7
#define WB32_EXTI2_IRQ_VECTOR Vector60
#define WB32_EXTI2_NUMBER 8
#define WB32_EXTI3_IRQ_VECTOR Vector64
#define WB32_EXTI3_NUMBER 9
#define WB32_EXTI4_IRQ_VECTOR Vector68
#define WB32_EXTI4_NUMBER 10
#define WB32_EXTI9_5_IRQ_VECTOR Vector80
#define WB32_EXTI9_5_NUMBER 16
#define WB32_EXTI15_10_IRQ_VECTOR VectorC4
#define WB32_EXTI15_10_NUMBER 33
/*
* DMAC units.
*/
#define WB32_DMAC1_IRQ_VECTOR Vector6C
#define WB32_DMAC1_NUMBER 11
#define WB32_DMAC2_IRQ_VECTOR Vector70
#define WB32_DMAC2_NUMBER 12
/*
* ADC units.
*/
#define WB32_ADC_IRQ_VECTOR Vector74
#define WB32_ADC_NUMBER 13
/*
* USB units.
*/
#define WB32_USB1_IRQ_VECTOR Vector78
#define WB32_USB1_DMA_IRQ_VECTOR Vector7C
#define WB32_USBP1_WKUP_IRQ_VECTOR VectorCC
#define WB32_USB1_NUMBER 14
#define WB32_USB1_DMA_NUMBER 15
#define WB32_USBP1_WKUP_NUMBER 35
/*
* I2C units.
*/
#define WB32_I2C1_IRQ_VECTOR VectorA0
#define WB32_I2C1_NUMBER 24
#define WB32_I2C2_IRQ_VECTOR VectorA4
#define WB32_I2C2_NUMBER 25
/*
* I2S units.
*/
#define WB32_I2S_IRQ_VECTOR VectorD0
#define WB32_I2S_NUMBER 36
/*
* SPI units.
*/
#define WB32_QSPI_IRQ_VECTOR VectorA8
#define WB32_QSPI_NUMBER 26
#define WB32_SPIM2_IRQ_VECTOR VectorAC
#define WB32_SPIM2_NUMBER 27
#define WB32_SPIS1_IRQ_VECTOR VectorB0
#define WB32_SPIS1_NUMBER 28
#define WB32_SPIS2_IRQ_VECTOR VectorB4
#define WB32_SPIS2_NUMBER 29
/*
* TIM units.
*/
#define WB32_TIM1_BRK_IRQ_VECTOR Vector84
#define WB32_TIM1_UP_IRQ_VECTOR Vector88
#define WB32_TIM1_TRG_COM_IRQ_VECTOR Vector8C
#define WB32_TIM1_CC_IRQ_VECTOR Vector90
#define WB32_TIM1_BRK_NUMBER 17
#define WB32_TIM1_UP_NUMBER 18
#define WB32_TIM1_TRG_COM_NUMBER 19
#define WB32_TIM1_CC_NUMBER 20
#define WB32_TIM2_IRQ_VECTOR Vector94
#define WB32_TIM2_NUMBER 21
#define WB32_TIM3_IRQ_VECTOR Vector98
#define WB32_TIM3_NUMBER 22
#define WB32_TIM4_IRQ_VECTOR Vector9C
#define WB32_TIM4_NUMBER 23
/*
* USART units.
*/
#define WB32_UART1_IRQ_VECTOR VectorB8
#define WB32_UART1_NUMBER 30
#define WB32_UART2_IRQ_VECTOR VectorBC
#define WB32_UART2_NUMBER 31
#define WB32_UART3_IRQ_VECTOR VectorC0
#define WB32_UART3_NUMBER 32
/*
* ISO units.
*/
#define WB32_ISO_IRQ_VECTOR VectorD4
#define WB32_ISO_NUMBER 37
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief EXTI0 interrupt priority level setting.
*/
#if !defined(WB32_IRQ_EXTI0_PRIORITY) || defined(__DOXYGEN__)
#define WB32_IRQ_EXTI0_PRIORITY 6
#endif
/**
* @brief EXTI1 interrupt priority level setting.
*/
#if !defined(WB32_IRQ_EXTI1_PRIORITY) || defined(__DOXYGEN__)
#define WB32_IRQ_EXTI1_PRIORITY 6
#endif
/**
* @brief EXTI2 interrupt priority level setting.
*/
#if !defined(WB32_IRQ_EXTI2_PRIORITY) || defined(__DOXYGEN__)
#define WB32_IRQ_EXTI2_PRIORITY 6
#endif
/**
* @brief EXTI3 interrupt priority level setting.
*/
#if !defined(WB32_IRQ_EXTI3_PRIORITY) || defined(__DOXYGEN__)
#define WB32_IRQ_EXTI3_PRIORITY 6
#endif
/**
* @brief EXTI4 interrupt priority level setting.
*/
#if !defined(WB32_IRQ_EXTI4_PRIORITY) || defined(__DOXYGEN__)
#define WB32_IRQ_EXTI4_PRIORITY 6
#endif
/**
* @brief EXTI9..5 interrupt priority level setting.
*/
#if !defined(WB32_IRQ_EXTI5_9_PRIORITY) || defined(__DOXYGEN__)
#define WB32_IRQ_EXTI5_9_PRIORITY 6
#endif
/**
* @brief EXTI15..10 interrupt priority level setting.
*/
#if !defined(WB32_IRQ_EXTI10_15_PRIORITY) || defined(__DOXYGEN__)
#define WB32_IRQ_EXTI10_15_PRIORITY 6
#endif
/**
* @brief EXTI16 interrupt priority level setting.
*/
#if !defined(WB32_IRQ_EXTI16_PRIORITY) || defined(__DOXYGEN__)
#define WB32_IRQ_EXTI16_PRIORITY 6
#endif
/**
* @brief EXTI17 interrupt priority level setting.
*/
#if !defined(WB32_IRQ_EXTI17_PRIORITY) || defined(__DOXYGEN__)
#define WB32_IRQ_EXTI17_PRIORITY 6
#endif
/**
* @brief EXTI18 interrupt priority level setting.
*/
#if !defined(WB32_IRQ_EXTI18_PRIORITY) || defined(__DOXYGEN__)
#define WB32_IRQ_EXTI18_PRIORITY 6
#endif
/**
* @brief EXTI19 interrupt priority level setting.
*/
#if !defined(WB32_IRQ_EXTI19_PRIORITY) || defined(__DOXYGEN__)
#define WB32_IRQ_EXTI19_PRIORITY 6
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void irqInit(void);
void irqDeinit(void);
#ifdef __cplusplus
}
#endif
#endif /* WB32_ISR_H */
/** @} */

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/*
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file WB32FQ95xx/wb32_rcc.h
* @brief RCC helper driver header.
* @note This file requires definitions from the WB header file
* @p WB32fq95xx.h.
*
* @addtogroup WB32FQ95xx_RCC
* @{
*/
#ifndef WB32_RCC_H
#define WB32_RCC_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @name Generic RCC operations
* @{
*/
/**
* @brief Enables the clock of one or more peripheral on the APB1 bus.
*
* @param[in] mask APB1 peripherals mask
*
* @api
*/
#define rccEnableAPB1(mask) { \
RCC->APB1ENR |= (mask); \
(void)RCC->APB1ENR; \
}
/**
* @brief Disables the clock of one or more peripheral on the APB1 bus.
*
* @param[in] mask APB1 peripherals mask
*
* @api
*/
#define rccDisableAPB1(mask) { \
RCC->APB1ENR &= ~(mask); \
(void)RCC->APB1ENR; \
}
/**
* @brief Resets one or more peripheral on the APB1 bus.
*
* @param[in] mask APB1 peripherals mask
*
* @api
*/
#define rccResetAPB1(mask) { \
RCC->APB1RSTR |= (mask); \
RCC->APB1RSTR &= ~(mask); \
(void)RCC->APB1RSTR; \
}
/**
* @brief Enables the clock of one or more peripheral on the APB2 bus.
*
* @param[in] mask APB2 peripherals mask
*
* @api
*/
#define rccEnableAPB2(mask) { \
RCC->APB2ENR |= (mask); \
(void)RCC->APB2ENR; \
}
/**
* @brief Disables the clock of one or more peripheral on the APB2 bus.
*
* @param[in] mask APB2 peripherals mask
*
* @api
*/
#define rccDisableAPB2(mask) { \
RCC->APB2ENR &= ~(mask); \
(void)RCC->APB2ENR; \
}
/**
* @brief Resets one or more peripheral on the APB2 bus.
*
* @param[in] mask APB2 peripherals mask
*
* @api
*/
#define rccResetAPB2(mask) { \
RCC->APB2RSTR |= (mask); \
RCC->APB2RSTR &= ~(mask); \
(void)RCC->APB2RSTR; \
}
/**
* @brief Enables the clock of one or more peripheral on the AHB bus.
*
* @param[in] mask AHB peripherals mask
*
* @api
*/
#define rccEnableAHB(mask) { \
RCC->AHBENR |= (mask); \
(void)RCC->AHBENR; \
}
/**
* @brief Disables the clock of one or more peripheral on the AHB bus.
*
* @param[in] mask AHB peripherals mask
*
* @api
*/
#define rccDisableAHB(mask) { \
RCC->AHBENR &= ~(mask); \
(void)RCC->AHBENR; \
}
/**
* @brief Resets one or more peripheral on the AHB bus.
*
* @param[in] mask AHB peripherals mask
*
* @api
*/
#define rccResetAHB(mask) { \
RCC->AHBRSTR |= (mask); \
RCC->AHBRSTR &= ~(mask); \
(void)RCC->AHBRSTR; \
}
/** @} */
/**
* @name EXTI peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the EXTI peripheral clock.
*
* @api
*/
#define rccEnableEXTI() rccEnableAPB1(RCC_APB1ENR_EXTIEN | RCC_APB1ENR_AFIOEN)
/**
* @brief Disables the EXTI peripheral clock.
*
* @api
*/
#define rccDisableEXTI() rccDisableAPB1(RCC_APB1ENR_EXTIEN | RCC_APB1ENR_AFIOEN)
/**
* @brief Resets the EXTI peripheral.
*
* @api
*/
#define rccResetEXTI() rccResetAPB1(RCC_APB1RSTR_EXTIRST | RCC_APB1RSTR_AFIORST)
/** @} */
/**
* @name I2C peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the I2C1 peripheral clock.
*
* @api
*/
#define rccEnableI2C1() rccEnableAPB2(RCC_APB2ENR_I2C1EN)
/**
* @brief Disables the I2C1 peripheral clock.
*
* @api
*/
#define rccDisableI2C1() rccDisableAPB2(RCC_APB2ENR_I2C1EN)
/**
* @brief Resets the I2C1 peripheral.
*
* @api
*/
#define rccResetI2C1() rccResetAPB2(RCC_APB2RSTR_I2C1RST)
/**
* @brief Enables the I2C2 peripheral clock.
*
* @api
*/
#define rccEnableI2C2() rccEnableAPB2(RCC_APB2ENR_I2C2EN)
/**
* @brief Disables the I2C2 peripheral clock.
*
* @api
*/
#define rccDisableI2C2() rccDisableAPB2(RCC_APB2ENR_I2C2EN)
/**
* @brief Resets the I2C2 peripheral.
*
* @api
*/
#define rccResetI2C2() rccResetAPB2(RCC_APB2RSTR_I2C2RST)
/** @} */
/**
* @name SPI peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the QSPI peripheral clock.
*
* @api
*/
#define rccEnableQSPI() rccEnableAPB1(RCC_APB1ENR_QSPIEN)
/**
* @brief Disables the QSPI peripheral clock.
*
* @api
*/
#define rccDisableQSPI() rccDisableAPB1(RCC_APB1ENR_QSPIEN)
/**
* @brief Resets the QSPI peripheral.
*
* @api
*/
#define rccResetQSPI() rccResetAPB1(RCC_APB1RSTR_QSPIRST)
/**
* @brief Enables the SPIS1 peripheral clock.
*
* @api
*/
#define rccEnableSPIS1() do { \
rccEnableAPB1(RCC_APB1ENR_SPIS1EN); \
RCC->SPIS1CLKENR = RCC_SPIS1CLKENR_CLKEN; \
} while (false)
/**
* @brief Disables the SPIS1 peripheral clock.
*
* @api
*/
#define rccDisableSPIS1() do { \
RCC->SPIS1CLKENR = 0x00; \
rccDisableAPB1(RCC_APB1ENR_SPIS1EN); \
} while (false)
/**
* @brief Resets the SPIS1 peripheral.
*
* @api
*/
#define rccResetSPIS1() rccResetAPB1(RCC_APB1RSTR_SPIS1RST)
/**
* @brief Enables the SPIM2 peripheral clock.
*
* @api
*/
#define rccEnableSPIM2() rccEnableAPB2(RCC_APB2ENR_SPIM2EN)
/**
* @brief Disables the SPIM2 peripheral clock.
*
* @api
*/
#define rccDisableSPIM2() rccDisableAPB2(RCC_APB2ENR_SPIM2EN)
/**
* @brief Resets the SPIM2 peripheral.
*
* @api
*/
#define rccResetSPIM2() rccResetAPB2(RCC_APB2RSTR_SPIM2RST)
/**
* @brief Enables the SPIS2 peripheral clock.
*
* @api
*/
#define rccEnableSPIS2() do { \
rccEnableAPB2(RCC_APB2ENR_SPIS2EN); \
RCC->SPIS2CLKENR = RCC_SPIS2CLKENR_CLKEN; \
} while (false)
/**
* @brief Disables the SPIS2 peripheral clock.
*
* @api
*/
#define rccDisableSPIS2() do { \
RCC->SPIS2CLKENR = 0x00; \
rccDisableAPB2(RCC_APB2ENR_SPIS2EN); \
} while (false)
/**
* @brief Resets the SPIS2 peripheral.
*
* @api
*/
#define rccResetSPIS2() rccResetAPB2(RCC_APB2RSTR_SPIS2RST)
/** @} */
/**
* @name TIM peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the TIM1 peripheral clock.
*
* @api
*/
#define rccEnableTIM1() rccEnableAPB1(RCC_APB1ENR_TIM1EN)
/**
* @brief Disables the TIM1 peripheral clock.
*
* @api
*/
#define rccDisableTIM1() rccDisableAPB1(RCC_APB1ENR_TIM1EN)
/**
* @brief Resets the TIM1 peripheral.
*
* @api
*/
#define rccResetTIM1() rccResetAPB1(RCC_APB1RSTR_TIM1RST)
/**
* @brief Enables the TIM2 peripheral clock.
*
* @api
*/
#define rccEnableTIM2() rccEnableAPB1(RCC_APB1ENR_TIM2EN)
/**
* @brief Disables the TIM2 peripheral clock.
*
* @api
*/
#define rccDisableTIM2() rccDisableAPB1(RCC_APB1ENR_TIM2EN)
/**
* @brief Resets the TIM2 peripheral.
*
* @api
*/
#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
/**
* @brief Enables the TIM3 peripheral clock.
*
* @api
*/
#define rccEnableTIM3() rccEnableAPB1(RCC_APB1ENR_TIM3EN)
/**
* @brief Disables the TIM3 peripheral clock.
*
* @api
*/
#define rccDisableTIM3() rccDisableAPB1(RCC_APB1ENR_TIM3EN)
/**
* @brief Resets the TIM3 peripheral.
*
* @api
*/
#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
/**
* @brief Enables the TIM4 peripheral clock.
*
* @api
*/
#define rccEnableTIM4() rccEnableAPB1(RCC_APB1ENR_TIM4EN)
/**
* @brief Disables the TIM4 peripheral clock.
*
* @api
*/
#define rccDisableTIM4() rccDisableAPB1(RCC_APB1ENR_TIM4EN)
/**
* @brief Resets the TIM4 peripheral.
*
* @api
*/
#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
/** @} */
/**
* @name UART peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the UART1 peripheral clock.
*
* @api
*/
#define rccEnableUART1() rccEnableAPB1(RCC_APB1ENR_UART1EN)
/**
* @brief Disables the UART1 peripheral clock.
*
* @api
*/
#define rccDisableUART1() rccDisableAPB1(RCC_APB1ENR_UART1EN)
/**
* @brief Resets the UART1 peripheral.
*
* @api
*/
#define rccResetUART1() rccResetAPB1(RCC_APB1RSTR_UART1RST)
/**
* @brief Enables the UART2 peripheral clock.
*
* @api
*/
#define rccEnableUART2() rccEnableAPB2(RCC_APB2ENR_UART2EN)
/**
* @brief Disables the UART2 peripheral clock.
*
* @api
*/
#define rccDisableUART2() rccDisableAPB2(RCC_APB2ENR_UART2EN)
/**
* @brief Resets the UART2 peripheral.
*
* @api
*/
#define rccResetUART2() rccResetAPB2(RCC_APB2RSTR_UART2RST)
/**
* @brief Enables the UART3 peripheral clock.
*
* @api
*/
#define rccEnableUART3() rccEnableAPB2(RCC_APB2ENR_UART3EN)
/**
* @brief Disables the UART3 peripheral clock.
*
* @api
*/
#define rccDisableUART3() rccDisableAPB2(RCC_APB2ENR_UART3EN)
/**
* @brief Resets the UART3 peripheral.
*
* @api
*/
#define rccResetUART3() rccResetAPB2(RCC_APB2RSTR_UART3RST)
/** @} */
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* WB32_RCC_H */
/** @} */

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/*
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file WB32FQ95xx/wb32_registry.h
* @brief WB32FQ95xx capabilities registry.
*
* @addtogroup HAL
* @{
*/
#ifndef WB32_REGISTRY_H
#define WB32_REGISTRY_H
#if !defined(WB32FQ95xx)
#error "unsupported or unrecognized WB32FQ95xx member"
#endif
/*===========================================================================*/
/* Platform capabilities. */
/*===========================================================================*/
#if defined(WB32FQ95xx) || defined(__DOXYGEN__)
/**
* @name WB32FQ95xx capabilities
* @{
*/
/* GPIO attributes.*/
#define WB32_HAS_GPIOA TRUE
#define WB32_HAS_GPIOB TRUE
#define WB32_HAS_GPIOC TRUE
#define WB32_HAS_GPIOD TRUE
/* WWDG attributes */
#define WB32_HAS_WWDG TRUE
/* PVD attributes */
#define WB32_HAS_PVD TRUE
/* TAMPER attributes */
#define WB32_HAS_TAMPER TRUE
/* RTC attributes */
#define WB32_HAS_RTC TRUE
/* FMC attributes */
#define WB32_HAS_FMC TRUE
/* EXTI attributes */
#define WB32_HAS_EXTI TRUE
#define WB32_HAS_EXTI0 TRUE
#define WB32_HAS_EXTI1 TRUE
#define WB32_HAS_EXTI2 TRUE
#define WB32_HAS_EXTI3 TRUE
#define WB32_HAS_EXTI4 TRUE
#define WB32_HAS_EXTI9_5 TRUE
#define WB32_HAS_EXTI15_10 TRUE
#define WB32_EXTI_NUM_LINES 19
/* DMAC1 attributes */
#define WB32_HAS_DMAC TRUE
#define WB32_HAS_DMAC1 TRUE
#define WB32_DMAC1_NUM_CHANNELS 3
#define WB32_HAS_DMAC2 TRUE
#define WB32_DMAC2_NUM_CHANNELS 3
/* ADC attributes */
#define WB32_HAS_ADC TRUE
/* USB attributes */
#define WB32_HAS_USB TRUE
#define WB32_HAS_USB1 TRUE
#define WB32_HAS_USB1_DMA TRUE
#define WB32_HAS_USB1_WKUP TRUE
/* TIM attributes */
#define WB32_HAS_TIM TRUE
#define WB32_HAS_TIM1 TRUE
#define WB32_HAS_TIM2 TRUE
#define WB32_HAS_TIM3 TRUE
#define WB32_HAS_TIM4 TRUE
#define WB32_TIM1_IS_32BITS TRUE
#define WB32_TIM1_CHANNELS 4
#define WB32_TIM2_IS_32BITS TRUE
#define WB32_TIM2_CHANNELS 4
#define WB32_TIM3_IS_32BITS TRUE
#define WB32_TIM3_CHANNELS 4
#define WB32_TIM4_IS_32BITS TRUE
#define WB32_TIM4_CHANNELS 4
/* I2C attributes */
#define WB32_HAS_I2C TRUE
#define WB32_HAS_I2C1 TRUE
#define WB32_HAS_I2C2 TRUE
/* SPI attributes */
#define WB32_HAS_SPI TRUE
#define WB32_HAS_QSPI TRUE
#define WB32_HAS_SPIM2 TRUE
#define WB32_HAS_SPIS1 TRUE
#define WB32_HAS_SPIS2 TRUE
/* UART attributes */
#define WB32_HAS_UART TRUE
#define WB32_HAS_UART1 TRUE
#define WB32_HAS_UART2 TRUE
#define WB32_HAS_UART3 TRUE
/* I2S attributes */
#define WB32_HAS_I2S TRUE
/* ISO attributes */
#define WB32_HAS_ISO TRUE
/* IWDG attributes.*/
#define WB32_HAS_IWDG TRUE
/* CRC attributes.*/
#define WB32_HAS_CRC TRUE
/** @} */
#endif /* defined(WB32FQ95xx) */
#endif /* WB32_REGISTRY_H */
/** @} */