diff --git a/os/hal/boards/SIPEED_LONGAN_NANO/board.h b/os/hal/boards/SIPEED_LONGAN_NANO/board.h
index 60dc6e04..5ce1b871 100644
--- a/os/hal/boards/SIPEED_LONGAN_NANO/board.h
+++ b/os/hal/boards/SIPEED_LONGAN_NANO/board.h
@@ -55,7 +55,7 @@
 
 #define LINE_GREEN_LED         PAL_LINE(GPIOA, PIN_GREEN_LED)
 #define LINE_BLUE_LED          PAL_LINE(GPIOA, PIN_BLUE_LED)
-#define LINE_RED_LED           PAL_LINE(GPIOA, PIN_RED_LED)
+#define LINE_RED_LED           PAL_LINE(GPIOC, PIN_RED_LED)
 
 #define LINE_DISPLAY_MISO      PAL_LINE(GPIOA, PIN_DISPLAY_MISO)
 #define LINE_DISPLAY_MOSI      PAL_LINE(GPIOA, PIN_DISPLAY_MOSI)
@@ -113,9 +113,10 @@
 /*
  * Port C setup.
  * Everything input with pull-up except:
+ * C13 - RED LED - Push Pull output 50MHz
  */
 #define VAL_GPIOCCRL            0x88888888      /*  PC7...PC0 */
-#define VAL_GPIOCCRH            0x88888888      /* PC15...PC8 */
+#define VAL_GPIOCCRH            0x88388888      /* PC15...PC8 */
 #define VAL_GPIOCODR            0xFFFFFFFF
 
 /*
diff --git a/os/hal/ports/GD/GD32VF103/CRC/hal_crc_lld.c b/os/hal/ports/GD/GD32VF103/CRC/hal_crc_lld.c
index 9395c74d..8ea3d8e9 100755
--- a/os/hal/ports/GD/GD32VF103/CRC/hal_crc_lld.c
+++ b/os/hal/ports/GD/GD32VF103/CRC/hal_crc_lld.c
@@ -226,19 +226,11 @@ uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf) {
   crc_lld_start_calc(crcp, n, buf);
   (void) osalThreadSuspendS(&crcp->thread);
 #else
-  /**
-   * BUG: Only peform byte writes to DR reg if reflect_data is disabled.
-   * The GD32 hardware unit seems to incorrectly calculate CRCs when all
-   * of the following is true: reflect_data(rev_in) is 0, dma is disable, and
-   * you are writing more than a byte into the DR register.
-   */
-  if (crcp->config->reflect_data != 0) {
     while(n > 3) {
       _crc_lld_calc_word(crcp, *(uint32_t*)buf);
       buf+=4;
       n-=4;
     }
-  }
   osalDbgAssert(n == 0, "GD32 CRC Unit only supports WORD accesses");
 #endif
   return crcp->crc->DATA ^ crcp->config->final_val;