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Rename RCU registers

This commit is contained in:
Stefan Kerkmann 2021-04-05 19:36:41 +02:00
parent 9ef3cfcc3d
commit e6822d95ed
5 changed files with 244 additions and 248 deletions
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12
os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.c
View File

@ -31,13 +31,13 @@
/*===========================================================================*/
#if GD32_HAS_GPIOE
#define APB2_EN_MASK (RCU_APB2ENR_IOPAEN | RCU_APB2ENR_IOPBEN | \
RCU_APB2ENR_IOPCEN | RCU_APB2ENR_IOPDEN | \
RCU_APB2ENR_IOPEEN | RCU_APB2ENR_AFIOEN)
#define APB2_EN_MASK (RCU_APB2EN_PAEN | RCU_APB2EN_PBEN | \
RCU_APB2EN_PCEN | RCU_APB2EN_PDEN | \
RCU_APB2EN_PEEN | RCU_APB2EN_AFEN)
#else
#define APB2_EN_MASK (RCU_APB2ENR_IOPAEN | RCU_APB2ENR_IOPBEN | \
RCU_APB2ENR_IOPCEN | RCU_APB2ENR_IOPDEN | \
RCU_APB2ENR_AFIOEN)
#define APB2_EN_MASK (RCU_APB2EN_PAEN | RCU_APB2EN_PBEN | \
RCU_APB2EN_PCEN | RCU_APB2EN_PDEN | \
RCU_APB2EN_AFEN)
#endif
/*===========================================================================*/

102
os/hal/ports/GD/GD32VF103/gd32_rcu.h
View File

@ -184,14 +184,14 @@
*
* @api
*/
#define rcuEnableADC0(lp) rcuEnableAPB2(RCU_APB2ENR_ADC0EN, lp)
#define rcuEnableADC0(lp) rcuEnableAPB2(RCU_APB2EN_ADC0EN, lp)
/**
* @brief Disables the ADC0 peripheral clock.
*
* @api
*/
#define rcuDisableADC0() rcuDisableAPB2(RCU_APB2ENR_ADC0EN)
#define rcuDisableADC0() rcuDisableAPB2(RCU_APB2EN_ADC0EN)
/**
* @brief Resets the ADC0 peripheral.
@ -212,14 +212,14 @@
*
* @api
*/
#define rcuEnableDAC(lp) rcuEnableAPB1(RCU_APB1ENR_DACEN, lp)
#define rcuEnableDAC(lp) rcuEnableAPB1(RCU_APB1EN_DACEN, lp)
/**
* @brief Disables the DAC peripheral clock.
*
* @api
*/
#define rcuDisableDAC() rcuDisableAPB1(RCU_APB1ENR_DACEN)
#define rcuDisableDAC() rcuDisableAPB1(RCU_APB1EN_DACEN)
/**
* @brief Resets the DAC peripheral.
@ -241,28 +241,28 @@
*
* @api
*/
#define rcuEnableBKPInterface(lp) rcuEnableAPB1((RCU_APB1ENR_BKPEN), lp)
#define rcuEnableBKPInterface(lp) rcuEnableAPB1((RCU_APB1EN_BKPIEN), lp)
/**
* @brief Disables BKP interface clock.
*
* @api
*/
#define rcuDisableBKPInterface() rcuDisableAPB1(RCU_APB1ENR_BKPEN)
#define rcuDisableBKPInterface() rcuDisableAPB1(RCU_APB1EN_BKPIEN)
/**
* @brief Resets the Backup Domain interface.
*
* @api
*/
#define rcuResetBKPInterface() rcuResetAPB1(RCU_APB1ENR_BKPRST)
#define rcuResetBKPInterface() rcuResetAPB1(RCU_APB1EN_BKPRST)
/**
* @brief Resets the entire Backup Domain.
*
* @api
*/
#define rcuResetBKP() (RCU->BDCTL |= RCU_BDCR_BDRST)
#define rcuResetBKP() (RCU->BDCTL |= RCU_BDCTL_BKPRST)
/** @} */
/**
@ -277,14 +277,14 @@
*
* @api
*/
#define rcuEnablePMUInterface(lp) rcuEnableAPB1(RCU_APB1ENR_PMUEN, lp)
#define rcuEnablePMUInterface(lp) rcuEnableAPB1(RCU_APB1EN_PMUEN, lp)
/**
* @brief Disables PMU interface clock.
*
* @api
*/
#define rcuDisablePMUInterface() rcuDisableAPB1(RCU_APB1ENR_PMUEN)
#define rcuDisablePMUInterface() rcuDisableAPB1(RCU_APB1EN_PMUEN)
/**
* @brief Resets the PMU interface.
@ -306,14 +306,14 @@
*
* @api
*/
#define rcuEnableCAN0(lp) rcuEnableAPB1(RCU_APB1ENR_CAN0EN, lp)
#define rcuEnableCAN0(lp) rcuEnableAPB1(RCU_APB1EN_CAN0EN, lp)
/**
* @brief Disables the CAN0 peripheral clock.
*
* @api
*/
#define rcuDisableCAN0() rcuDisableAPB1(RCU_APB1ENR_CAN0EN)
#define rcuDisableCAN0() rcuDisableAPB1(RCU_APB1EN_CAN0EN)
/**
* @brief Resets the CAN0 peripheral.
@ -329,14 +329,14 @@
*
* @api
*/
#define rcuEnableCAN1(lp) rcuEnableAPB1(RCU_APB1ENR_CAN1EN, lp)
#define rcuEnableCAN1(lp) rcuEnableAPB1(RCU_APB1EN_CAN1EN, lp)
/**
* @brief Disables the CAN1 peripheral clock.
*
* @api
*/
#define rcuDisableCAN1() rcuDisableAPB1(RCU_APB1ENR_CAN1EN)
#define rcuDisableCAN1() rcuDisableAPB1(RCU_APB1EN_CAN1EN)
/**
* @brief Resets the CAN1 peripheral.
@ -413,14 +413,14 @@
*
* @api
*/
#define rcuEnableI2C0(lp) rcuEnableAPB1(RCU_APB1ENR_I2C0EN, lp)
#define rcuEnableI2C0(lp) rcuEnableAPB1(RCU_APB1EN_I2C0EN, lp)
/**
* @brief Disables the I2C0 peripheral clock.
*
* @api
*/
#define rcuDisableI2C0() rcuDisableAPB1(RCU_APB1ENR_I2C0EN)
#define rcuDisableI2C0() rcuDisableAPB1(RCU_APB1EN_I2C0EN)
/**
* @brief Resets the I2C0 peripheral.
@ -437,14 +437,14 @@
*
* @api
*/
#define rcuEnableI2C1(lp) rcuEnableAPB1(RCU_APB1ENR_I2C1EN, lp)
#define rcuEnableI2C1(lp) rcuEnableAPB1(RCU_APB1EN_I2C1EN, lp)
/**
* @brief Disables the I2C1 peripheral clock.
*
* @api
*/
#define rcuDisableI2C1() rcuDisableAPB1(RCU_APB1ENR_I2C1EN)
#define rcuDisableI2C1() rcuDisableAPB1(RCU_APB1EN_I2C1EN)
/**
* @brief Resets the I2C1 peripheral.
@ -479,7 +479,7 @@
*
* @api
*/
#define rcuResetUSBFS() rcuResetAHB(RCU_AHBRSTR_OTGFSRST)
#define rcuResetUSBFS() rcuResetAHB(RCU_AHBRST_USBFSRST)
/** @} */
/**
@ -494,14 +494,14 @@
*
* @api
*/
#define rcuEnableSPI0(lp) rcuEnableAPB2(RCU_APB2ENR_SPI0EN, lp)
#define rcuEnableSPI0(lp) rcuEnableAPB2(RCU_APB2EN_SPI0EN, lp)
/**
* @brief Disables the SPI0 peripheral clock.
*
* @api
*/
#define rcuDisableSPI0() rcuDisableAPB2(RCU_APB2ENR_SPI0EN)
#define rcuDisableSPI0() rcuDisableAPB2(RCU_APB2EN_SPI0EN)
/**
* @brief Resets the SPI0 peripheral.
@ -518,14 +518,14 @@
*
* @api
*/
#define rcuEnableSPI1(lp) rcuEnableAPB1(RCU_APB1ENR_SPI1EN, lp)
#define rcuEnableSPI1(lp) rcuEnableAPB1(RCU_APB1EN_SPI1EN, lp)
/**
* @brief Disables the SPI1 peripheral clock.
*
* @api
*/
#define rcuDisableSPI1() rcuDisableAPB1(RCU_APB1ENR_SPI1EN)
#define rcuDisableSPI1() rcuDisableAPB1(RCU_APB1EN_SPI1EN)
/**
* @brief Resets the SPI1 peripheral.
@ -542,14 +542,14 @@
*
* @api
*/
#define rcuEnableSPI2(lp) rcuEnableAPB1(RCU_APB1ENR_SPI2EN, lp)
#define rcuEnableSPI2(lp) rcuEnableAPB1(RCU_APB1EN_SPI2EN, lp)
/**
* @brief Disables the SPI2 peripheral clock.
*
* @api
*/
#define rcuDisableSPI2() rcuDisableAPB1(RCU_APB1ENR_SPI2EN)
#define rcuDisableSPI2() rcuDisableAPB1(RCU_APB1EN_SPI2EN)
/**
* @brief Resets the SPI2 peripheral.
@ -571,14 +571,14 @@
*
* @api
*/
#define rcuEnableTIM0(lp) rcuEnableAPB2(RCU_APB2ENR_TIM0EN, lp)
#define rcuEnableTIM0(lp) rcuEnableAPB2(RCU_APB2EN_TIMER0EN, lp)
/**
* @brief Disables the TIM0 peripheral clock.
*
* @api
*/
#define rcuDisableTIM0() rcuDisableAPB2(RCU_APB2ENR_TIM0EN)
#define rcuDisableTIM0() rcuDisableAPB2(RCU_APB2EN_TIMER0EN)
/**
* @brief Resets the TIM0 peripheral.
@ -595,14 +595,14 @@
*
* @api
*/
#define rcuEnableTIM1(lp) rcuEnableAPB1(RCU_APB1ENR_TIM1EN, lp)
#define rcuEnableTIM1(lp) rcuEnableAPB1(RCU_APB1EN_TIMER1EN, lp)
/**
* @brief Disables the TIM1 peripheral clock.
*
* @api
*/
#define rcuDisableTIM1() rcuDisableAPB1(RCU_APB1ENR_TIM1EN)
#define rcuDisableTIM1() rcuDisableAPB1(RCU_APB1EN_TIMER1EN)
/**
* @brief Resets the TIM1 peripheral.
@ -619,14 +619,14 @@
*
* @api
*/
#define rcuEnableTIM2(lp) rcuEnableAPB1(RCU_APB1ENR_TIM2EN, lp)
#define rcuEnableTIM2(lp) rcuEnableAPB1(RCU_APB1EN_TIMER2EN, lp)
/**
* @brief Disables the TIM2 peripheral clock.
*
* @api
*/
#define rcuDisableTIM2() rcuDisableAPB1(RCU_APB1ENR_TIM2EN)
#define rcuDisableTIM2() rcuDisableAPB1(RCU_APB1EN_TIMER2EN)
/**
* @brief Resets the TIM2 peripheral.
@ -643,14 +643,14 @@
*
* @api
*/
#define rcuEnableTIM3(lp) rcuEnableAPB1(RCU_APB1ENR_TIM3EN, lp)
#define rcuEnableTIM3(lp) rcuEnableAPB1(RCU_APB1EN_TIMER3EN, lp)
/**
* @brief Disables the TIM3 peripheral clock.
*
* @api
*/
#define rcuDisableTIM3() rcuDisableAPB1(RCU_APB1ENR_TIM3EN)
#define rcuDisableTIM3() rcuDisableAPB1(RCU_APB1EN_TIMER3EN)
/**
* @brief Resets the TIM3 peripheral.
@ -667,14 +667,14 @@
*
* @api
*/
#define rcuEnableTIM4(lp) rcuEnableAPB1(RCU_APB1ENR_TIM4EN, lp)
#define rcuEnableTIM4(lp) rcuEnableAPB1(RCU_APB1EN_TIMER4EN, lp)
/**
* @brief Disables the TIM4 peripheral clock.
*
* @api
*/
#define rcuDisableTIM4() rcuDisableAPB1(RCU_APB1ENR_TIM4EN)
#define rcuDisableTIM4() rcuDisableAPB1(RCU_APB1EN_TIMER4EN)
/**
* @brief Resets the TIM4 peripheral.
@ -690,14 +690,14 @@
*
* @api
*/
#define rcuEnableTIM5(lp) rcuEnableAPB1(RCU_APB1ENR_TIM5EN, lp)
#define rcuEnableTIM5(lp) rcuEnableAPB1(RCU_APB1EN_TIMER5EN, lp)
/**
* @brief Disables the TIM5 peripheral clock.
*
* @api
*/
#define rcuDisableTIM5() rcuDisableAPB1(RCU_APB1ENR_TIM5EN)
#define rcuDisableTIM5() rcuDisableAPB1(RCU_APB1EN_TIMER5EN)
/**
* @brief Resets the TIM5 peripheral.
@ -713,14 +713,14 @@
*
* @api
*/
#define rcuEnableTIM6(lp) rcuEnableAPB1(RCU_APB1ENR_TIM6EN, lp)
#define rcuEnableTIM6(lp) rcuEnableAPB1(RCU_APB1EN_TIMER6EN, lp)
/**
* @brief Disables the TIM6 peripheral clock.
*
* @api
*/
#define rcuDisableTIM6() rcuDisableAPB1(RCU_APB1ENR_TIM6EN)
#define rcuDisableTIM6() rcuDisableAPB1(RCU_APB1EN_TIMER6EN)
/**
* @brief Resets the TIM6 peripheral.
@ -744,14 +744,14 @@
*
* @api
*/
#define rcuEnableUSART0(lp) rcuEnableAPB2(RCU_APB2ENR_USART0EN, lp)
#define rcuEnableUSART0(lp) rcuEnableAPB2(RCU_APB2EN_USART0EN, lp)
/**
* @brief Disables the USART0 peripheral clock.
*
* @api
*/
#define rcuDisableUSART0() rcuDisableAPB2(RCU_APB2ENR_USART0EN)
#define rcuDisableUSART0() rcuDisableAPB2(RCU_APB2EN_USART0EN)
/**
* @brief Resets the USART0 peripheral.
@ -768,14 +768,14 @@
*
* @api
*/
#define rcuEnableUSART1(lp) rcuEnableAPB1(RCU_APB1ENR_USART1EN, lp)
#define rcuEnableUSART1(lp) rcuEnableAPB1(RCU_APB1EN_USART1EN, lp)
/**
* @brief Disables the USART1 peripheral clock.
*
* @api
*/
#define rcuDisableUSART1() rcuDisableAPB1(RCU_APB1ENR_USART1EN)
#define rcuDisableUSART1() rcuDisableAPB1(RCU_APB1EN_USART1EN)
/**
* @brief Resets the USART1 peripheral.
@ -792,14 +792,14 @@
*
* @api
*/
#define rcuEnableUSART2(lp) rcuEnableAPB1(RCU_APB1ENR_USART2EN, lp)
#define rcuEnableUSART2(lp) rcuEnableAPB1(RCU_APB1EN_USART2EN, lp)
/**
* @brief Disables the USART2 peripheral clock.
*
* @api
*/
#define rcuDisableUSART2() rcuDisableAPB1(RCU_APB1ENR_USART2EN)
#define rcuDisableUSART2() rcuDisableAPB1(RCU_APB1EN_USART2EN)
/**
* @brief Resets the USART2 peripheral.
@ -816,14 +816,14 @@
*
* @api
*/
#define rcuEnableUART3(lp) rcuEnableAPB1(RCU_APB1ENR_UART3EN, lp)
#define rcuEnableUART3(lp) rcuEnableAPB1(RCU_APB1EN_UART3EN, lp)
/**
* @brief Disables the UART3 peripheral clock.
*
* @api
*/
#define rcuDisableUART3() rcuDisableAPB1(RCU_APB1ENR_UART3EN)
#define rcuDisableUART3() rcuDisableAPB1(RCU_APB1EN_UART3EN)
/**
* @brief Resets the UART3 peripheral.
@ -840,14 +840,14 @@
*
* @api
*/
#define rcuEnableUART4(lp) rcuEnableAPB1(RCU_APB1ENR_UART4EN, lp)
#define rcuEnableUART4(lp) rcuEnableAPB1(RCU_APB1EN_UART4EN, lp)
/**
* @brief Disables the UART4 peripheral clock.
*
* @api
*/
#define rcuDisableUART4() rcuDisableAPB1(RCU_APB1ENR_UART4EN)
#define rcuDisableUART4() rcuDisableAPB1(RCU_APB1EN_UART4EN)
/**
* @brief Resets the UART4 peripheral.
@ -869,14 +869,14 @@
*
* @api
*/
#define rcuEnableUSB(lp) rcuEnableAPB1(RCU_APB1ENR_USBEN, lp)
#define rcuEnableUSB(lp) rcuEnableAPB1(RCU_APB1EN_USBEN, lp)
/**
* @brief Disables the USB peripheral clock
*
* @api
*/
#define rcuDisableUSB() rcuDisableAPB1(RCU_APB1ENR_USBEN)
#define rcuDisableUSB() rcuDisableAPB1(RCU_APB1EN_USBEN)
/**
* @brief Resets the USB peripheral.

24
os/hal/ports/GD/GD32VF103/hal_lld.c
View File

@ -58,9 +58,9 @@ static void hal_lld_backup_domain_init(void) {
#if HAL_USE_RTC
/* Reset BKP domain if different clock source selected.*/
if ((RCU->BDCTL & GD32_RTCSEL_MASK) != GD32_RTCSEL) {
if ((RCU->BDCTL & GD32_RTCSRC_MASK) != GD32_RTCSRC) {
/* Backup domain reset.*/
RCU->BDCTL = RCU_BDCR_BDRST;
RCU->BDCTL = RCU_BDCTL_BKPRST;
RCU->BDCTL = 0;
}
@ -68,29 +68,29 @@ static void hal_lld_backup_domain_init(void) {
#if GD32_LXTAL_ENABLED
#if defined(GD32_LXTAL_BYPASS)
/* LXTAL Bypass.*/
RCU->BDCTL |= RCU_BDCR_LXTALON | RCU_BDCR_LXTALBYP;
RCU->BDCTL |= RCU_BDCTL_LXTALEN | RCU_BDCTL_LXTALBPS;
#else
/* No LXTAL Bypass.*/
RCU->BDCTL |= RCU_BDCR_LXTALON;
RCU->BDCTL |= RCU_BDCTL_LXTALEN;
#endif
while ((RCU->BDCTL & RCU_BDCR_LXTALRDY) == 0)
while ((RCU->BDCTL & RCU_BDCTL_LXTALSTB) == 0)
; /* Waits until LXTAL is stable. */
#endif /* GD32_LXTAL_ENABLED */
#if GD32_RTCSEL != GD32_RTCSEL_NOCLOCK
#if GD32_RTCSRC != GD32_RTCSRC_NOCLOCK
/* If the backup domain hasn't been initialized yet then proceed with
initialization.*/
if ((RCU->BDCTL & RCU_BDCR_RTCEN) == 0) {
if ((RCU->BDCTL & RCU_BDCTL_RTCEN) == 0) {
/* Selects clock source.*/
RCU->BDCTL |= GD32_RTCSEL;
RCU->BDCTL |= GD32_RTCSRC;
/* Prescaler value loaded in registers.*/
rtc_lld_set_prescaler();
/* RTC clock enabled.*/
RCU->BDCTL |= RCU_BDCR_RTCEN;
RCU->BDCTL |= RCU_BDCTL_RTCEN;
}
#endif /* GD32_RTCSEL != GD32_RTCSEL_NOCLOCK */
#endif /* GD32_RTCSRC != GD32_RTCSRC_NOCLOCK */
#endif /* HAL_USE_RTC */
}
@ -178,8 +178,8 @@ void gd32_clock_init(void) {
#if GD32_IRC40K_ENABLED
/* IRC40K activation.*/
RCU->RSTSCK |= RCU_CSR_IRC40KON;
while ((RCU->RSTSCK & RCU_CSR_IRC40KRDY) == 0)
RCU->RSTSCK |= RCU_RSTSCK_IRC40KEN;
while ((RCU->RSTSCK & RCU_RSTSCK_IRC40KSTB) == 0)
; /* Waits until IRC40K is stable. */
#endif

36
os/hal/ports/GD/GD32VF103/hal_lld_gd32vf103.h
View File

@ -200,14 +200,14 @@
/** @} */
/**
* @name RCU_BDCR register bits definitions
* @name RCU_BDCTL register bits definitions
* @{
*/
#define GD32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
#define GD32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
#define GD32_RTCSEL_LXTAL (1 << 8) /**< LXTAL used as RTC clock. */
#define GD32_RTCSEL_IRC40K (2 << 8) /**< IRC40K used as RTC clock. */
#define GD32_RTCSEL_HXTALDIV (3 << 8) /**< HXTAL divided by 128 used as
#define GD32_RTCSRC_MASK (3 << 8) /**< RTC clock source mask. */
#define GD32_RTCSRC_NOCLOCK (0 << 8) /**< No clock. */
#define GD32_RTCSRC_LXTAL (1 << 8) /**< LXTAL used as RTC clock. */
#define GD32_RTCSRC_IRC40K (2 << 8) /**< IRC40K used as RTC clock. */
#define GD32_RTCSRC_HXTALDIV (3 << 8) /**< HXTAL divided by 128 used as
RTC clock. */
/** @} */
@ -363,8 +363,8 @@
/**
* @brief RTC clock source.
*/
#if !defined(GD32_RTCSEL) || defined(__DOXYGEN__)
#define GD32_RTCSEL GD32_RTCSEL_NOCLOCK
#if !defined(GD32_RTCSRC) || defined(__DOXYGEN__)
#define GD32_RTCSRC GD32_RTCSRC_NOCLOCK
#endif
/** @} */
@ -432,8 +432,8 @@
#error "HXTAL not enabled, required by GD32_CKOUT0SEL"
#endif
#if GD32_RTCSEL == GD32_RTCSEL_HXTALDIV
#error "HXTAL not enabled, required by GD32_RTCSEL"
#if GD32_RTCSRC == GD32_RTCSRC_HXTALDIV
#error "HXTAL not enabled, required by GD32_RTCSRC"
#endif
#endif /* !GD32_HXTAL_ENABLED */
@ -444,8 +444,8 @@
#if GD32_IRC40K_ENABLED
#else /* !GD32_IRC40K_ENABLED */
#if GD32_RTCSEL == GD32_RTCSEL_IRC40K
#error "IRC40K not enabled, required by GD32_RTCSEL"
#if GD32_RTCSRC == GD32_RTCSRC_IRC40K
#error "IRC40K not enabled, required by GD32_RTCSRC"
#endif
#endif /* !GD32_IRC40K_ENABLED */
@ -465,8 +465,8 @@
#else /* !GD32_LXTAL_ENABLED */
#if GD32_RTCSEL == GD32_RTCSEL_LXTAL
#error "LXTAL not enabled, required by GD32_RTCSEL"
#if GD32_RTCSRC == GD32_RTCSRC_LXTAL
#error "LXTAL not enabled, required by GD32_RTCSRC"
#endif
#endif /* !GD32_LXTAL_ENABLED */
@ -761,13 +761,13 @@
/**
* @brief RTC clock.
*/
#if (GD32_RTCSEL == GD32_RTCSEL_LXTAL) || defined(__DOXYGEN__)
#if (GD32_RTCSRC == GD32_RTCSRC_LXTAL) || defined(__DOXYGEN__)
#define GD32_RTCCLK GD32_LXTALCLK
#elif GD32_RTCSEL == GD32_RTCSEL_IRC40K
#elif GD32_RTCSRC == GD32_RTCSRC_IRC40K
#define GD32_RTCCLK GD32_IRC40KCLK
#elif GD32_RTCSEL == GD32_RTCSEL_HXTALDIV
#elif GD32_RTCSRC == GD32_RTCSRC_HXTALDIV
#define GD32_RTCCLK (GD32_HXTALCLK / 128)
#elif GD32_RTCSEL == GD32_RTCSEL_NOCLOCK
#elif GD32_RTCSRC == GD32_RTCSRC_NOCLOCK
#define GD32_RTCCLK 0
#else
#error "invalid source selected for RTC clock"

318
os/hal/ports/GD/GD32VF103/stm32f105xc.h
View File

@ -1442,182 +1442,178 @@ typedef struct
#define RCU_AHBEN_USBFSEN_Msk (0x1U << RCU_AHBEN_USBFSEN_Pos) /*!< 0x00001000 */
#define RCU_AHBEN_USBFSEN RCU_AHBEN_USBFSEN_Msk /*!< USB OTG FS clock enable */
/****************** Bit definition for RCU_APB2ENR register *****************/
#define RCU_APB2ENR_AFIOEN_Pos (0U)
#define RCU_APB2ENR_AFIOEN_Msk (0x1U << RCU_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
#define RCU_APB2ENR_AFIOEN RCU_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
#define RCU_APB2ENR_IOPAEN_Pos (2U)
#define RCU_APB2ENR_IOPAEN_Msk (0x1U << RCU_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
#define RCU_APB2ENR_IOPAEN RCU_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
#define RCU_APB2ENR_IOPBEN_Pos (3U)
#define RCU_APB2ENR_IOPBEN_Msk (0x1U << RCU_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
#define RCU_APB2ENR_IOPBEN RCU_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
#define RCU_APB2ENR_IOPCEN_Pos (4U)
#define RCU_APB2ENR_IOPCEN_Msk (0x1U << RCU_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
#define RCU_APB2ENR_IOPCEN RCU_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
#define RCU_APB2ENR_IOPDEN_Pos (5U)
#define RCU_APB2ENR_IOPDEN_Msk (0x1U << RCU_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
#define RCU_APB2ENR_IOPDEN RCU_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
#define RCU_APB2ENR_ADC0EN_Pos (9U)
#define RCU_APB2ENR_ADC0EN_Msk (0x1U << RCU_APB2ENR_ADC0EN_Pos) /*!< 0x00000200 */
#define RCU_APB2ENR_ADC0EN RCU_APB2ENR_ADC0EN_Msk /*!< ADC 1 interface clock enable */
/****************** Bit definition for RCU_APB2EN register *****************/
#define RCU_APB2EN_AFEN_Pos (0U)
#define RCU_APB2EN_AFEN_Msk (0x1U << RCU_APB2EN_AFEN_Pos) /*!< 0x00000001 */
#define RCU_APB2EN_AFEN RCU_APB2EN_AFEN_Msk /*!< Alternate Function I/O clock enable */
#define RCU_APB2EN_PAEN_Pos (2U)
#define RCU_APB2EN_PAEN_Msk (0x1U << RCU_APB2EN_PAEN_Pos) /*!< 0x00000004 */
#define RCU_APB2EN_PAEN RCU_APB2EN_PAEN_Msk /*!< I/O port A clock enable */
#define RCU_APB2EN_PBEN_Pos (3U)
#define RCU_APB2EN_PBEN_Msk (0x1U << RCU_APB2EN_PBEN_Pos) /*!< 0x00000008 */
#define RCU_APB2EN_PBEN RCU_APB2EN_PBEN_Msk /*!< I/O port B clock enable */
#define RCU_APB2EN_PCEN_Pos (4U)
#define RCU_APB2EN_PCEN_Msk (0x1U << RCU_APB2EN_PCEN_Pos) /*!< 0x00000010 */
#define RCU_APB2EN_PCEN RCU_APB2EN_PCEN_Msk /*!< I/O port C clock enable */
#define RCU_APB2EN_PDEN_Pos (5U)
#define RCU_APB2EN_PDEN_Msk (0x1U << RCU_APB2EN_PDEN_Pos) /*!< 0x00000020 */
#define RCU_APB2EN_PDEN RCU_APB2EN_PDEN_Msk /*!< I/O port D clock enable */
#define RCU_APB2EN_ADC0EN_Pos (9U)
#define RCU_APB2EN_ADC0EN_Msk (0x1U << RCU_APB2EN_ADC0EN_Pos) /*!< 0x00000200 */
#define RCU_APB2EN_ADC0EN RCU_APB2EN_ADC0EN_Msk /*!< ADC 1 interface clock enable */
#define RCU_APB2ENR_ADC1EN_Pos (10U)
#define RCU_APB2ENR_ADC1EN_Msk (0x1U << RCU_APB2ENR_ADC1EN_Pos) /*!< 0x00000400 */
#define RCU_APB2ENR_ADC1EN RCU_APB2ENR_ADC1EN_Msk /*!< ADC 2 interface clock enable */
#define RCU_APB2EN_ADC1EN_Pos (10U)
#define RCU_APB2EN_ADC1EN_Msk (0x1U << RCU_APB2EN_ADC1EN_Pos) /*!< 0x00000400 */
#define RCU_APB2EN_ADC1EN RCU_APB2EN_ADC1EN_Msk /*!< ADC 2 interface clock enable */
#define RCU_APB2ENR_TIM0EN_Pos (11U)
#define RCU_APB2ENR_TIM0EN_Msk (0x1U << RCU_APB2ENR_TIM0EN_Pos) /*!< 0x00000800 */
#define RCU_APB2ENR_TIM0EN RCU_APB2ENR_TIM0EN_Msk /*!< TIM0 Timer clock enable */
#define RCU_APB2ENR_SPI0EN_Pos (12U)
#define RCU_APB2ENR_SPI0EN_Msk (0x1U << RCU_APB2ENR_SPI0EN_Pos) /*!< 0x00001000 */
#define RCU_APB2ENR_SPI0EN RCU_APB2ENR_SPI0EN_Msk /*!< SPI 1 clock enable */
#define RCU_APB2ENR_USART0EN_Pos (14U)
#define RCU_APB2ENR_USART0EN_Msk (0x1U << RCU_APB2ENR_USART0EN_Pos) /*!< 0x00004000 */
#define RCU_APB2ENR_USART0EN RCU_APB2ENR_USART0EN_Msk /*!< USART0 clock enable */
#define RCU_APB2EN_TIMER0EN_Pos (11U)
#define RCU_APB2EN_TIMER0EN_Msk (0x1U << RCU_APB2EN_TIMER0EN_Pos) /*!< 0x00000800 */
#define RCU_APB2EN_TIMER0EN RCU_APB2EN_TIMER0EN_Msk /*!< TIM0 Timer clock enable */
#define RCU_APB2EN_SPI0EN_Pos (12U)
#define RCU_APB2EN_SPI0EN_Msk (0x1U << RCU_APB2EN_SPI0EN_Pos) /*!< 0x00001000 */
#define RCU_APB2EN_SPI0EN RCU_APB2EN_SPI0EN_Msk /*!< SPI 1 clock enable */
#define RCU_APB2EN_USART0EN_Pos (14U)
#define RCU_APB2EN_USART0EN_Msk (0x1U << RCU_APB2EN_USART0EN_Pos) /*!< 0x00004000 */
#define RCU_APB2EN_USART0EN RCU_APB2EN_USART0EN_Msk /*!< USART0 clock enable */
#define RCU_APB2EN_PEEN_Pos (6U)
#define RCU_APB2EN_PEEN_Msk (0x1U << RCU_APB2EN_PEEN_Pos) /*!< 0x00000040 */
#define RCU_APB2EN_PEEN RCU_APB2EN_PEEN_Msk /*!< I/O port E clock enable */
/***************** Bit definition for RCU_APB1EN register ******************/
#define RCU_APB1EN_TIMER1EN_Pos (0U)
#define RCU_APB1EN_TIMER1EN_Msk (0x1U << RCU_APB1EN_TIMER1EN_Pos) /*!< 0x00000001 */
#define RCU_APB1EN_TIMER1EN RCU_APB1EN_TIMER1EN_Msk /*!< Timer 2 clock enabled*/
#define RCU_APB1EN_TIMER2EN_Pos (1U)
#define RCU_APB1EN_TIMER2EN_Msk (0x1U << RCU_APB1EN_TIMER2EN_Pos) /*!< 0x00000002 */
#define RCU_APB1EN_TIMER2EN RCU_APB1EN_TIMER2EN_Msk /*!< Timer 3 clock enable */
#define RCU_APB1EN_WWDGTEN_Pos (11U)
#define RCU_APB1EN_WWDGTEN_Msk (0x1U << RCU_APB1EN_WWDGTEN_Pos) /*!< 0x00000800 */
#define RCU_APB1EN_WWDGTEN RCU_APB1EN_WWDGTEN_Msk /*!< Window Watchdog clock enable */
#define RCU_APB1EN_USART1EN_Pos (17U)
#define RCU_APB1EN_USART1EN_Msk (0x1U << RCU_APB1EN_USART1EN_Pos) /*!< 0x00020000 */
#define RCU_APB1EN_USART1EN RCU_APB1EN_USART1EN_Msk /*!< USART 2 clock enable */
#define RCU_APB1EN_I2C0EN_Pos (21U)
#define RCU_APB1EN_I2C0EN_Msk (0x1U << RCU_APB1EN_I2C0EN_Pos) /*!< 0x00200000 */
#define RCU_APB1EN_I2C0EN RCU_APB1EN_I2C0EN_Msk /*!< I2C 1 clock enable */
#define RCU_APB1EN_CAN0EN_Pos (25U)
#define RCU_APB1EN_CAN0EN_Msk (0x1U << RCU_APB1EN_CAN0EN_Pos) /*!< 0x02000000 */
#define RCU_APB1EN_CAN0EN RCU_APB1EN_CAN0EN_Msk /*!< CAN0 clock enable */
#define RCU_APB1EN_BKPIEN_Pos (27U)
#define RCU_APB1EN_BKPIEN_Msk (0x1U << RCU_APB1EN_BKPIEN_Pos) /*!< 0x08000000 */
#define RCU_APB1EN_BKPIEN RCU_APB1EN_BKPIEN_Msk /*!< Backup interface clock enable */
#define RCU_APB1EN_PMUEN_Pos (28U)
#define RCU_APB1EN_PMUEN_Msk (0x1U << RCU_APB1EN_PMUEN_Pos) /*!< 0x10000000 */
#define RCU_APB1EN_PMUEN RCU_APB1EN_PMUEN_Msk /*!< Power interface clock enable */
#define RCU_APB1EN_TIMER3EN_Pos (2U)
#define RCU_APB1EN_TIMER3EN_Msk (0x1U << RCU_APB1EN_TIMER3EN_Pos) /*!< 0x00000004 */
#define RCU_APB1EN_TIMER3EN RCU_APB1EN_TIMER3EN_Msk /*!< Timer 4 clock enable */
#define RCU_APB1EN_SPI1EN_Pos (14U)
#define RCU_APB1EN_SPI1EN_Msk (0x1U << RCU_APB1EN_SPI1EN_Pos) /*!< 0x00004000 */
#define RCU_APB1EN_SPI1EN RCU_APB1EN_SPI1EN_Msk /*!< SPI 2 clock enable */
#define RCU_APB1EN_USART2EN_Pos (18U)
#define RCU_APB1EN_USART2EN_Msk (0x1U << RCU_APB1EN_USART2EN_Pos) /*!< 0x00040000 */
#define RCU_APB1EN_USART2EN RCU_APB1EN_USART2EN_Msk /*!< USART 3 clock enable */
#define RCU_APB1EN_I2C1EN_Pos (22U)
#define RCU_APB1EN_I2C1EN_Msk (0x1U << RCU_APB1EN_I2C1EN_Pos) /*!< 0x00400000 */
#define RCU_APB1EN_I2C1EN RCU_APB1EN_I2C1EN_Msk /*!< I2C 2 clock enable */
#define RCU_APB2ENR_IOPEEN_Pos (6U)
#define RCU_APB2ENR_IOPEEN_Msk (0x1U << RCU_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
#define RCU_APB2ENR_IOPEEN RCU_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
#define RCU_APB1EN_TIMER4EN_Pos (3U)
#define RCU_APB1EN_TIMER4EN_Msk (0x1U << RCU_APB1EN_TIMER4EN_Pos) /*!< 0x00000008 */
#define RCU_APB1EN_TIMER4EN RCU_APB1EN_TIMER4EN_Msk /*!< Timer 5 clock enable */
#define RCU_APB1EN_TIMER5EN_Pos (4U)
#define RCU_APB1EN_TIMER5EN_Msk (0x1U << RCU_APB1EN_TIMER5EN_Pos) /*!< 0x00000010 */
#define RCU_APB1EN_TIMER5EN RCU_APB1EN_TIMER5EN_Msk /*!< Timer 6 clock enable */
#define RCU_APB1EN_TIMER6EN_Pos (5U)
#define RCU_APB1EN_TIMER6EN_Msk (0x1U << RCU_APB1EN_TIMER6EN_Pos) /*!< 0x00000020 */
#define RCU_APB1EN_TIMER6EN RCU_APB1EN_TIMER6EN_Msk /*!< Timer 7 clock enable */
#define RCU_APB1EN_SPI2EN_Pos (15U)
#define RCU_APB1EN_SPI2EN_Msk (0x1U << RCU_APB1EN_SPI2EN_Pos) /*!< 0x00008000 */
#define RCU_APB1EN_SPI2EN RCU_APB1EN_SPI2EN_Msk /*!< SPI 3 clock enable */
#define RCU_APB1EN_UART3EN_Pos (19U)
#define RCU_APB1EN_UART3EN_Msk (0x1U << RCU_APB1EN_UART3EN_Pos) /*!< 0x00080000 */
#define RCU_APB1EN_UART3EN RCU_APB1EN_UART3EN_Msk /*!< UART 4 clock enable */
#define RCU_APB1EN_UART4EN_Pos (20U)
#define RCU_APB1EN_UART4EN_Msk (0x1U << RCU_APB1EN_UART4EN_Pos) /*!< 0x00100000 */
#define RCU_APB1EN_UART4EN RCU_APB1EN_UART4EN_Msk /*!< UART 5 clock enable */
#define RCU_APB1EN_CAN1EN_Pos (26U)
#define RCU_APB1EN_CAN1EN_Msk (0x1U << RCU_APB1EN_CAN1EN_Pos) /*!< 0x04000000 */
#define RCU_APB1EN_CAN1EN RCU_APB1EN_CAN1EN_Msk /*!< CAN1 clock enable */
/***************** Bit definition for RCU_APB1ENR register ******************/
#define RCU_APB1ENR_TIM1EN_Pos (0U)
#define RCU_APB1ENR_TIM1EN_Msk (0x1U << RCU_APB1ENR_TIM1EN_Pos) /*!< 0x00000001 */
#define RCU_APB1ENR_TIM1EN RCU_APB1ENR_TIM1EN_Msk /*!< Timer 2 clock enabled*/
#define RCU_APB1ENR_TIM2EN_Pos (1U)
#define RCU_APB1ENR_TIM2EN_Msk (0x1U << RCU_APB1ENR_TIM2EN_Pos) /*!< 0x00000002 */
#define RCU_APB1ENR_TIM2EN RCU_APB1ENR_TIM2EN_Msk /*!< Timer 3 clock enable */
#define RCU_APB1ENR_WWDGEN_Pos (11U)
#define RCU_APB1ENR_WWDGEN_Msk (0x1U << RCU_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
#define RCU_APB1ENR_WWDGEN RCU_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
#define RCU_APB1ENR_USART1EN_Pos (17U)
#define RCU_APB1ENR_USART1EN_Msk (0x1U << RCU_APB1ENR_USART1EN_Pos) /*!< 0x00020000 */
#define RCU_APB1ENR_USART1EN RCU_APB1ENR_USART1EN_Msk /*!< USART 2 clock enable */
#define RCU_APB1ENR_I2C0EN_Pos (21U)
#define RCU_APB1ENR_I2C0EN_Msk (0x1U << RCU_APB1ENR_I2C0EN_Pos) /*!< 0x00200000 */
#define RCU_APB1ENR_I2C0EN RCU_APB1ENR_I2C0EN_Msk /*!< I2C 1 clock enable */
#define RCU_APB1EN_DACEN_Pos (29U)
#define RCU_APB1EN_DACEN_Msk (0x1U << RCU_APB1EN_DACEN_Pos) /*!< 0x20000000 */
#define RCU_APB1EN_DACEN RCU_APB1EN_DACEN_Msk /*!< DAC interface clock enable */
#define RCU_APB1ENR_CAN0EN_Pos (25U)
#define RCU_APB1ENR_CAN0EN_Msk (0x1U << RCU_APB1ENR_CAN0EN_Pos) /*!< 0x02000000 */
#define RCU_APB1ENR_CAN0EN RCU_APB1ENR_CAN0EN_Msk /*!< CAN0 clock enable */
/******************* Bit definition for RCU_BDCTL register *******************/
#define RCU_BDCTL_LXTALEN_Pos (0U)
#define RCU_BDCTL_LXTALEN_Msk (0x1U << RCU_BDCTL_LXTALEN_Pos) /*!< 0x00000001 */
#define RCU_BDCTL_LXTALEN RCU_BDCTL_LXTALEN_Msk /*!< External Low Speed oscillator enable */
#define RCU_BDCTL_LXTALSTB_Pos (1U)
#define RCU_BDCTL_LXTALSTB_Msk (0x1U << RCU_BDCTL_LXTALSTB_Pos) /*!< 0x00000002 */
#define RCU_BDCTL_LXTALSTB RCU_BDCTL_LXTALSTB_Msk /*!< External Low Speed oscillator Ready */
#define RCU_BDCTL_LXTALBPS_Pos (2U)
#define RCU_BDCTL_LXTALBPS_Msk (0x1U << RCU_BDCTL_LXTALBPS_Pos) /*!< 0x00000004 */
#define RCU_BDCTL_LXTALBPS RCU_BDCTL_LXTALBPS_Msk /*!< External Low Speed oscillator Bypass */
#define RCU_APB1ENR_BKPEN_Pos (27U)
#define RCU_APB1ENR_BKPEN_Msk (0x1U << RCU_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
#define RCU_APB1ENR_BKPEN RCU_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
#define RCU_APB1ENR_PMUEN_Pos (28U)
#define RCU_APB1ENR_PMUEN_Msk (0x1U << RCU_APB1ENR_PMUEN_Pos) /*!< 0x10000000 */
#define RCU_APB1ENR_PMUEN RCU_APB1ENR_PMUEN_Msk /*!< Power interface clock enable */
#define RCU_APB1ENR_TIM3EN_Pos (2U)
#define RCU_APB1ENR_TIM3EN_Msk (0x1U << RCU_APB1ENR_TIM3EN_Pos) /*!< 0x00000004 */
#define RCU_APB1ENR_TIM3EN RCU_APB1ENR_TIM3EN_Msk /*!< Timer 4 clock enable */
#define RCU_APB1ENR_SPI1EN_Pos (14U)
#define RCU_APB1ENR_SPI1EN_Msk (0x1U << RCU_APB1ENR_SPI1EN_Pos) /*!< 0x00004000 */
#define RCU_APB1ENR_SPI1EN RCU_APB1ENR_SPI1EN_Msk /*!< SPI 2 clock enable */
#define RCU_APB1ENR_USART2EN_Pos (18U)
#define RCU_APB1ENR_USART2EN_Msk (0x1U << RCU_APB1ENR_USART2EN_Pos) /*!< 0x00040000 */
#define RCU_APB1ENR_USART2EN RCU_APB1ENR_USART2EN_Msk /*!< USART 3 clock enable */
#define RCU_APB1ENR_I2C1EN_Pos (22U)
#define RCU_APB1ENR_I2C1EN_Msk (0x1U << RCU_APB1ENR_I2C1EN_Pos) /*!< 0x00400000 */
#define RCU_APB1ENR_I2C1EN RCU_APB1ENR_I2C1EN_Msk /*!< I2C 2 clock enable */
#define RCU_APB1ENR_TIM4EN_Pos (3U)
#define RCU_APB1ENR_TIM4EN_Msk (0x1U << RCU_APB1ENR_TIM4EN_Pos) /*!< 0x00000008 */
#define RCU_APB1ENR_TIM4EN RCU_APB1ENR_TIM4EN_Msk /*!< Timer 5 clock enable */
#define RCU_APB1ENR_TIM5EN_Pos (4U)
#define RCU_APB1ENR_TIM5EN_Msk (0x1U << RCU_APB1ENR_TIM5EN_Pos) /*!< 0x00000010 */
#define RCU_APB1ENR_TIM5EN RCU_APB1ENR_TIM5EN_Msk /*!< Timer 6 clock enable */
#define RCU_APB1ENR_TIM6EN_Pos (5U)
#define RCU_APB1ENR_TIM6EN_Msk (0x1U << RCU_APB1ENR_TIM6EN_Pos) /*!< 0x00000020 */
#define RCU_APB1ENR_TIM6EN RCU_APB1ENR_TIM6EN_Msk /*!< Timer 7 clock enable */
#define RCU_APB1ENR_SPI2EN_Pos (15U)
#define RCU_APB1ENR_SPI2EN_Msk (0x1U << RCU_APB1ENR_SPI2EN_Pos) /*!< 0x00008000 */
#define RCU_APB1ENR_SPI2EN RCU_APB1ENR_SPI2EN_Msk /*!< SPI 3 clock enable */
#define RCU_APB1ENR_UART3EN_Pos (19U)
#define RCU_APB1ENR_UART3EN_Msk (0x1U << RCU_APB1ENR_UART3EN_Pos) /*!< 0x00080000 */
#define RCU_APB1ENR_UART3EN RCU_APB1ENR_UART3EN_Msk /*!< UART 4 clock enable */
#define RCU_APB1ENR_UART4EN_Pos (20U)
#define RCU_APB1ENR_UART4EN_Msk (0x1U << RCU_APB1ENR_UART4EN_Pos) /*!< 0x00100000 */
#define RCU_APB1ENR_UART4EN RCU_APB1ENR_UART4EN_Msk /*!< UART 5 clock enable */
#define RCU_APB1ENR_CAN1EN_Pos (26U)
#define RCU_APB1ENR_CAN1EN_Msk (0x1U << RCU_APB1ENR_CAN1EN_Pos) /*!< 0x04000000 */
#define RCU_APB1ENR_CAN1EN RCU_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */
#define RCU_APB1ENR_DACEN_Pos (29U)
#define RCU_APB1ENR_DACEN_Msk (0x1U << RCU_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
#define RCU_APB1ENR_DACEN RCU_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */
/******************* Bit definition for RCU_BDCR register *******************/
#define RCU_BDCR_LXTALON_Pos (0U)
#define RCU_BDCR_LXTALON_Msk (0x1U << RCU_BDCR_LXTALON_Pos) /*!< 0x00000001 */
#define RCU_BDCR_LXTALON RCU_BDCR_LXTALON_Msk /*!< External Low Speed oscillator enable */
#define RCU_BDCR_LXTALRDY_Pos (1U)
#define RCU_BDCR_LXTALRDY_Msk (0x1U << RCU_BDCR_LXTALRDY_Pos) /*!< 0x00000002 */
#define RCU_BDCR_LXTALRDY RCU_BDCR_LXTALRDY_Msk /*!< External Low Speed oscillator Ready */
#define RCU_BDCR_LXTALBYP_Pos (2U)
#define RCU_BDCR_LXTALBYP_Msk (0x1U << RCU_BDCR_LXTALBYP_Pos) /*!< 0x00000004 */
#define RCU_BDCR_LXTALBYP RCU_BDCR_LXTALBYP_Msk /*!< External Low Speed oscillator Bypass */
#define RCU_BDCR_RTCSEL_Pos (8U)
#define RCU_BDCR_RTCSEL_Msk (0x3U << RCU_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
#define RCU_BDCR_RTCSEL RCU_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
#define RCU_BDCR_RTCSEL_0 (0x1U << RCU_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
#define RCU_BDCR_RTCSEL_1 (0x2U << RCU_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
#define RCU_BDCTL_RTCSRC_Pos (8U)
#define RCU_BDCTL_RTCSRC_Msk (0x3U << RCU_BDCTL_RTCSRC_Pos) /*!< 0x00000300 */
#define RCU_BDCTL_RTCSRC RCU_BDCTL_RTCSRC_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
#define RCU_BDCTL_RTCSRC_0 (0x1U << RCU_BDCTL_RTCSRC_Pos) /*!< 0x00000100 */
#define RCU_BDCTL_RTCSRC_1 (0x2U << RCU_BDCTL_RTCSRC_Pos) /*!< 0x00000200 */
/*!< RTC congiguration */
#define RCU_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
#define RCU_BDCR_RTCSEL_LXTAL 0x00000100U /*!< LXTAL oscillator clock used as RTC clock */
#define RCU_BDCR_RTCSEL_IRC40K 0x00000200U /*!< IRC40K oscillator clock used as RTC clock */
#define RCU_BDCR_RTCSEL_HXTAL 0x00000300U /*!< HXTAL oscillator clock divided by 128 used as RTC clock */
#define RCU_BDCTL_RTCSRC_NOCLOCK 0x00000000U /*!< No clock */
#define RCU_BDCTL_RTCSRC_LXTAL 0x00000100U /*!< LXTAL oscillator clock used as RTC clock */
#define RCU_BDCTL_RTCSRC_IRC40K 0x00000200U /*!< IRC40K oscillator clock used as RTC clock */
#define RCU_BDCTL_RTCSRC_HXTAL 0x00000300U /*!< HXTAL oscillator clock divided by 128 used as RTC clock */
#define RCU_BDCR_RTCEN_Pos (15U)
#define RCU_BDCR_RTCEN_Msk (0x1U << RCU_BDCR_RTCEN_Pos) /*!< 0x00008000 */
#define RCU_BDCR_RTCEN RCU_BDCR_RTCEN_Msk /*!< RTC clock enable */
#define RCU_BDCR_BDRST_Pos (16U)
#define RCU_BDCR_BDRST_Msk (0x1U << RCU_BDCR_BDRST_Pos) /*!< 0x00010000 */
#define RCU_BDCR_BDRST RCU_BDCR_BDRST_Msk /*!< Backup domain software reset */
#define RCU_BDCTL_RTCEN_Pos (15U)
#define RCU_BDCTL_RTCEN_Msk (0x1U << RCU_BDCTL_RTCEN_Pos) /*!< 0x00008000 */
#define RCU_BDCTL_RTCEN RCU_BDCTL_RTCEN_Msk /*!< RTC clock enable */
#define RCU_BDCTL_BKPRST_Pos (16U)
#define RCU_BDCTL_BKPRST_Msk (0x1U << RCU_BDCTL_BKPRST_Pos) /*!< 0x00010000 */
#define RCU_BDCTL_BKPRST RCU_BDCTL_BKPRST_Msk /*!< Backup domain software reset */
/******************* Bit definition for RCU_CSR register ********************/
#define RCU_CSR_IRC40KON_Pos (0U)
#define RCU_CSR_IRC40KON_Msk (0x1U << RCU_CSR_IRC40KON_Pos) /*!< 0x00000001 */
#define RCU_CSR_IRC40KON RCU_CSR_IRC40KON_Msk /*!< Internal Low Speed oscillator enable */
#define RCU_CSR_IRC40KRDY_Pos (1U)
#define RCU_CSR_IRC40KRDY_Msk (0x1U << RCU_CSR_IRC40KRDY_Pos) /*!< 0x00000002 */
#define RCU_CSR_IRC40KRDY RCU_CSR_IRC40KRDY_Msk /*!< Internal Low Speed oscillator Ready */
#define RCU_CSR_RMVF_Pos (24U)
#define RCU_CSR_RMVF_Msk (0x1U << RCU_CSR_RMVF_Pos) /*!< 0x01000000 */
#define RCU_CSR_RMVF RCU_CSR_RMVF_Msk /*!< Remove reset flag */
#define RCU_CSR_PINRSTF_Pos (26U)
#define RCU_CSR_PINRSTF_Msk (0x1U << RCU_CSR_PINRSTF_Pos) /*!< 0x04000000 */
#define RCU_CSR_PINRSTF RCU_CSR_PINRSTF_Msk /*!< PIN reset flag */
#define RCU_CSR_PORRSTF_Pos (27U)
#define RCU_CSR_PORRSTF_Msk (0x1U << RCU_CSR_PORRSTF_Pos) /*!< 0x08000000 */
#define RCU_CSR_PORRSTF RCU_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
#define RCU_CSR_SFTRSTF_Pos (28U)
#define RCU_CSR_SFTRSTF_Msk (0x1U << RCU_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
#define RCU_CSR_SFTRSTF RCU_CSR_SFTRSTF_Msk /*!< Software Reset flag */
#define RCU_CSR_FWDGTRSTF_Pos (29U)
#define RCU_CSR_FWDGTRSTF_Msk (0x1U << RCU_CSR_FWDGTRSTF_Pos) /*!< 0x20000000 */
#define RCU_CSR_FWDGTRSTF RCU_CSR_FWDGTRSTF_Msk /*!< Independent Watchdog reset flag */
#define RCU_CSR_WWDGRSTF_Pos (30U)
#define RCU_CSR_WWDGRSTF_Msk (0x1U << RCU_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
#define RCU_CSR_WWDGRSTF RCU_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
#define RCU_CSR_LPMURSTF_Pos (31U)
#define RCU_CSR_LPMURSTF_Msk (0x1U << RCU_CSR_LPMURSTF_Pos) /*!< 0x80000000 */
#define RCU_CSR_LPMURSTF RCU_CSR_LPMURSTF_Msk /*!< Low-Power reset flag */
/******************* Bit definition for RCU_RSTSCK register ********************/
#define RCU_RSTSCK_IRC40KEN_Pos (0U)
#define RCU_RSTSCK_IRC40KEN_Msk (0x1U << RCU_RSTSCK_IRC40KEN_Pos) /*!< 0x00000001 */
#define RCU_RSTSCK_IRC40KEN RCU_RSTSCK_IRC40KEN_Msk /*!< Internal Low Speed oscillator enable */
#define RCU_RSTSCK_IRC40KSTB_Pos (1U)
#define RCU_RSTSCK_IRC40KSTB_Msk (0x1U << RCU_RSTSCK_IRC40KSTB_Pos) /*!< 0x00000002 */
#define RCU_RSTSCK_IRC40KSTB RCU_RSTSCK_IRC40KSTB_Msk /*!< Internal Low Speed oscillator Ready */
#define RCU_RSTSCK_RSTCF_Pos (24U)
#define RCU_RSTSCK_RSTCF_Msk (0x1U << RCU_RSTSCK_RSTCF_Pos) /*!< 0x01000000 */
#define RCU_RSTSCK_RSTCF RCU_RSTSCK_RSTCF_Msk /*!< Remove reset flag */
#define RCU_RSTSCK_EPRSTF_Pos (26U)
#define RCU_RSTSCK_EPRSTF_Msk (0x1U << RCU_RSTSCK_EPRSTF_Pos) /*!< 0x04000000 */
#define RCU_RSTSCK_EPRSTF RCU_RSTSCK_EPRSTF_Msk /*!< PIN reset flag */
#define RCU_RSTSCK_PORRSTF_Pos (27U)
#define RCU_RSTSCK_PORRSTF_Msk (0x1U << RCU_RSTSCK_PORRSTF_Pos) /*!< 0x08000000 */
#define RCU_RSTSCK_PORRSTF RCU_RSTSCK_PORRSTF_Msk /*!< POR/PDR reset flag */
#define RCU_RSTSCK_SWRSTF_Pos (28U)
#define RCU_RSTSCK_SWRSTF_Msk (0x1U << RCU_RSTSCK_SWRSTF_Pos) /*!< 0x10000000 */
#define RCU_RSTSCK_SWRSTF RCU_RSTSCK_SWRSTF_Msk /*!< Software Reset flag */
#define RCU_RSTSCK_FWDGTRSTF_Pos (29U)
#define RCU_RSTSCK_FWDGTRSTF_Msk (0x1U << RCU_RSTSCK_FWDGTRSTF_Pos) /*!< 0x20000000 */
#define RCU_RSTSCK_FWDGTRSTF RCU_RSTSCK_FWDGTRSTF_Msk /*!< Independent Watchdog reset flag */
#define RCU_RSTSCK_WWDGTRSTF_Pos (30U)
#define RCU_RSTSCK_WWDGTRSTF_Msk (0x1U << RCU_RSTSCK_WWDGTRSTF_Pos) /*!< 0x40000000 */
#define RCU_RSTSCK_WWDGTRSTF RCU_RSTSCK_WWDGTRSTF_Msk /*!< Window watchdog reset flag */
#define RCU_RSTSCK_LPRSTF_Pos (31U)
#define RCU_RSTSCK_LPRSTF_Msk (0x1U << RCU_RSTSCK_LPRSTF_Pos) /*!< 0x80000000 */
#define RCU_RSTSCK_LPRSTF RCU_RSTSCK_LPRSTF_Msk /*!< Low-Power reset flag */
/******************* Bit definition for RCU_AHBRSTR register ****************/
#define RCU_AHBRSTR_OTGFSRST_Pos (12U)
#define RCU_AHBRSTR_OTGFSRST_Msk (0x1U << RCU_AHBRSTR_OTGFSRST_Pos) /*!< 0x00001000 */
#define RCU_AHBRSTR_OTGFSRST RCU_AHBRSTR_OTGFSRST_Msk /*!< USB OTG FS reset */
/******************* Bit definition for RCU_AHBRST register ****************/
#define RCU_AHBRST_USBFSRST_Pos (12U)
#define RCU_AHBRST_USBFSRST_Msk (0x1U << RCU_AHBRST_USBFSRST_Pos) /*!< 0x00001000 */
#define RCU_AHBRST_USBFSRST RCU_AHBRST_USBFSRST_Msk /*!< USB OTG FS reset */
/******************* Bit definition for RCU_CFGR2 register ******************/
/*!< PREDIV1 configuration */