diff --git a/os/common/ext/SONiX/SN32F2xx/SN32F200_Def.h b/os/common/ext/SONiX/SN32F2xx/SN32F200_Def.h new file mode 100644 index 00000000..3d1a4168 --- /dev/null +++ b/os/common/ext/SONiX/SN32F2xx/SN32F200_Def.h @@ -0,0 +1,63 @@ +#ifndef __SN32F200_DEF_H +#define __SN32F200_DEF_H + +/*_____ I N C L U D E S ____________________________________________________*/ + +/*_____ D E F I N I T I O N S ______________________________________________*/ + +//Ture or False +// #define TRUE 0x1 +// #define FALSE 0x0 + +//Enable or Disable +#define ENABLE 0x1 +#define DISABLE 0x0 + +//Error Status +#define OK 0x0 +#define FAIL 0x1 + +//Null +// #define NULL 0 + +//Interrupt Flag Parsing Method +#define POLLING_METHOD 0x0 +#define INTERRUPT_METHOD 0x1 + +//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +//SN32F230_PKG +#define SN32F239 0 +#define SN32F238 1 +#define SN32F237 2 +#define SN32F236 3 +#define SN32F235 4 + +//SN32F240_PKG +#define SN32F249 0 +#define SN32F248 1 +#define SN32F247 2 +#define SN32F246 3 +#define SN32F245 4 + +//SN32F240B_PKG +#define SN32F248B 0 +#define SN32F247B 1 +#define SN32F246B 2 +#define SN32F2451B 3 + +//SN32F260_PKG +#define SN32F268 0 +#define SN32F267 1 +#define SN32F265 2 +#define SN32F2641 3 +#define SN32F264 4 +#define SN32F263 5 +//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + + +#endif /*__SN32F200_DEF_H*/ diff --git a/os/common/ext/SONiX/SN32F2xx/SN32F240.h b/os/common/ext/SONiX/SN32F2xx/SN32F240.h new file mode 100644 index 00000000..bc620986 --- /dev/null +++ b/os/common/ext/SONiX/SN32F2xx/SN32F240.h @@ -0,0 +1,3279 @@ +/* + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontroller, but can be equally used for other + * suitable processor architectures. This file can be freely distributed. + * Modifications to this file shall be clearly marked. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * @file SN32F240.h + * @brief CMSIS HeaderFile + * @version 2.0 + * @date 09. January 2022 + * @note Generated by SVDConv V3.3.35 on Sunday, 09.01.2022 18:49:12 + * from File 'SN32F240.svd', + * last modified on Tuesday, 01.09.2020 10:52:27 + */ + + + +/** @addtogroup SONiX Technology Co., Ltd. + * @{ + */ + + +/** @addtogroup SN32F240 + * @{ + */ + + +#ifndef SN32F240_H +#define SN32F240_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M0 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== SN32F240 Specific Interrupt Numbers ========================================== */ + NDT_IRQn = 0, /*!< 0 NDT */ + USB_IRQn = 1, /*!< 1 USB */ + LCD_IRQn = 2, /*!< 2 LCD */ + I2S_IRQn = 3, /*!< 3 I2S */ + SSP0_IRQn = 6, /*!< 6 SSP0 */ + SSP1_IRQn = 7, /*!< 7 SSP1 */ + I2C0_IRQn = 10, /*!< 10 I2C0 */ + I2C1_IRQn = 11, /*!< 11 I2C1 */ + USART0_IRQn = 13, /*!< 13 USART0 */ + USART1_IRQn = 14, /*!< 14 USART1 */ + CT16B0_IRQn = 15, /*!< 15 CT16B0 */ + CT16B1_IRQn = 16, /*!< 16 CT16B1 */ + CT16B2_IRQn = 17, /*!< 17 CT16B2 */ + CT32B0_IRQn = 19, /*!< 19 CT32B0 */ + CT32B1_IRQn = 20, /*!< 20 CT32B1 */ + CT32B2_IRQn = 21, /*!< 21 CT32B2 */ + RTC_IRQn = 23, /*!< 23 RTC */ + ADC_IRQn = 24, /*!< 24 ADC */ + WDT_IRQn = 25, /*!< 25 WDT */ + LVD_IRQn = 26, /*!< 26 LVD */ + P3_IRQn = 28, /*!< 28 P3 */ + P2_IRQn = 29, /*!< 29 P2 */ + P1_IRQn = 30, /*!< 30 P1 */ + P0_IRQn = 31 /*!< 31 P0 */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M0 Processor and Core Peripherals =========================== */ +#define __CM0_REV 0x0000U /*!< CM0 Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 0 /*!< MPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0.h" /*!< ARM Cortex-M0 processor and core peripherals */ +#include "system_SN32F2xx.h" /*!< SN32F240 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SYS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System Control Registers (SN_SYS0) + */ + +typedef struct { /*!< (@ 0x40060000) SN_SYS0 Structure */ + + union { + __IOM uint32_t ANBCTRL; /*!< (@ 0x00000000) Offset:0x00 Analog Block Control Register */ + + struct { + __IOM uint32_t IHRCEN : 1; /*!< [0..0] IHRC enable */ + uint32_t : 1; + __IOM uint32_t ELSEN : 1; /*!< [2..2] ELS XTAL enable */ + uint32_t : 1; + __IOM uint32_t EHSEN : 1; /*!< [4..4] EHS XTAL enable */ + __IOM uint32_t EHSFREQ : 1; /*!< [5..5] EHS XTAL frequency range */ + uint32_t : 26; + } ANBCTRL_b; + } ; + + union { + __IOM uint32_t PLLCTRL; /*!< (@ 0x00000004) Offset:0x04 PLL Control Register */ + + struct { + __IOM uint32_t MSEL : 5; /*!< [4..0] M: 3~31 */ + __IOM uint32_t PSEL : 3; /*!< [7..5] P=PSEL*2 */ + __IOM uint32_t FSEL : 1; /*!< [8..8] F=POWER(2, FSEL) */ + uint32_t : 3; + __IOM uint32_t PLLCLKSEL : 2; /*!< [13..12] PLL clock source */ + uint32_t : 1; + __IOM uint32_t PLLEN : 1; /*!< [15..15] PLL enable */ + uint32_t : 16; + } PLLCTRL_b; + } ; + + union { + __IM uint32_t CSST; /*!< (@ 0x00000008) Offset:0x08 Clock Source Status Register */ + + struct { + __IM uint32_t IHRCRDY : 1; /*!< [0..0] IHRC ready flag */ + uint32_t : 1; + __IM uint32_t ELSRDY : 1; /*!< [2..2] ELS XTAL ready flag */ + uint32_t : 1; + __IM uint32_t EHSRDY : 1; /*!< [4..4] EHS XTAL ready flag */ + uint32_t : 1; + __IM uint32_t PLLRDY : 1; /*!< [6..6] PLL ready flag */ + uint32_t : 25; + } CSST_b; + } ; + + union { + __IOM uint32_t CLKCFG; /*!< (@ 0x0000000C) Offset:0x0C System Clock Configuration Register */ + + struct { + __IOM uint32_t SYSCLKSEL : 3; /*!< [2..0] System clock source selection */ + uint32_t : 1; + __IM uint32_t SYSCLKST : 3; /*!< [6..4] System clock switch status */ + uint32_t : 25; + } CLKCFG_b; + } ; + + union { + __IOM uint32_t AHBCP; /*!< (@ 0x00000010) Offset:0x10 AHB Clock Prescale Register */ + + struct { + __IOM uint32_t AHBPRE : 4; /*!< [3..0] AHB clock source prescaler */ + uint32_t : 28; + } AHBCP_b; + } ; + + union { + __IOM uint32_t RSTST; /*!< (@ 0x00000014) Offset:0x14 System Reset Status Register */ + + struct { + __IOM uint32_t SWRSTF : 1; /*!< [0..0] Software reset flag */ + __IOM uint32_t WDTRSTF : 1; /*!< [1..1] WDT reset flag */ + __IOM uint32_t LVDRSTF : 1; /*!< [2..2] LVD reset flag */ + __IOM uint32_t EXTRSTF : 1; /*!< [3..3] External reset flag */ + __IOM uint32_t PORRSTF : 1; /*!< [4..4] POR reset flag */ + uint32_t : 27; + } RSTST_b; + } ; + + union { + __IOM uint32_t LVDCTRL; /*!< (@ 0x00000018) Offset:0x18 LVD Control Register */ + + struct { + __IOM uint32_t LVDRSTLVL : 3; /*!< [2..0] LVD reset level */ + uint32_t : 1; + __IOM uint32_t LVDINTLVL : 3; /*!< [6..4] LVD interrupt level */ + uint32_t : 7; + __IOM uint32_t LVDRSTEN : 1; /*!< [14..14] LVD Reset enable */ + __IOM uint32_t LVDEN : 1; /*!< [15..15] LVD enable */ + uint32_t : 16; + } LVDCTRL_b; + } ; + + union { + __IOM uint32_t EXRSTCTRL; /*!< (@ 0x0000001C) Offset:0x1C External Reset Pin Control Register */ + + struct { + __IOM uint32_t RESETDIS : 1; /*!< [0..0] External reset pin disable */ + uint32_t : 31; + } EXRSTCTRL_b; + } ; + + union { + __IOM uint32_t SWDCTRL; /*!< (@ 0x00000020) Offset:0x20 SWD Pin Control Register */ + + struct { + __IOM uint32_t SWDDIS : 1; /*!< [0..0] SWD pin disable */ + uint32_t : 31; + } SWDCTRL_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t NDTCTRL; /*!< (@ 0x00000028) Offset:0x28 Noise Detect Control Register */ + + struct { + __IOM uint32_t NDT1_IE : 1; /*!< [0..0] NDT for Vcore interrupt enable bit */ + __IOM uint32_t NDT2_IE : 1; /*!< [1..1] NDT for VDD interrupt enable bit */ + uint32_t : 30; + } NDTCTRL_b; + } ; + + union { + __IOM uint32_t NDTSTS; /*!< (@ 0x0000002C) Offset:0x2C Noise Detect Status Register */ + + struct { + __IOM uint32_t NDT1_DET : 1; /*!< [0..0] Power noise status of NDT1 */ + __IOM uint32_t NDT2_DET : 1; /*!< [1..1] Power noise status of NDT2 */ + uint32_t : 30; + } NDTSTS_b; + } ; + + union { + __IOM uint32_t ANTIEFT; /*!< (@ 0x00000030) Offset:0x30 Anti-EFT Ability Control Register */ + + struct { + __IOM uint32_t AEFT : 3; /*!< [2..0] Anti-EFT ability */ + uint32_t : 29; + } ANTIEFT_b; + } ; +} SN_SYS0_Type; /*!< Size = 52 (0x34) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SYS1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System Control Registers (SN_SYS1) + */ + +typedef struct { /*!< (@ 0x4005E000) SN_SYS1 Structure */ + + union { + __IOM uint32_t AHBCLKEN; /*!< (@ 0x00000000) Offset:0x00 AHB Clock Enable Register */ + + struct { + __IOM uint32_t GPIOCLKEN : 1; /*!< [0..0] Enable AHB clock for GPIO */ + __IOM uint32_t USBCLKEN : 1; /*!< [1..1] Enable AHB clock for USB */ + __IOM uint32_t LCDCLKEN : 1; /*!< [2..2] Enable AHB clock for LCD */ + uint32_t : 2; + __IOM uint32_t CT16B0CLKEN : 1; /*!< [5..5] Enable AHB clock for CT16B0 */ + __IOM uint32_t CT16B1CLKEN : 1; /*!< [6..6] Enable AHB clock for CT16B1 */ + __IOM uint32_t CT16B2CLKEN : 1; /*!< [7..7] Enable AHB clock for CT16B2 */ + __IOM uint32_t CT32B0CLKEN : 1; /*!< [8..8] Enable AHB clock for CT32B0 */ + __IOM uint32_t CT32B1CLKEN : 1; /*!< [9..9] Enable AHB clock for CT32B1 */ + __IOM uint32_t CT32B2CLKEN : 1; /*!< [10..10] Enable AHB clock for CT32B2 */ + __IOM uint32_t ADCCLKEN : 1; /*!< [11..11] Enable AHB clock for ADC */ + __IOM uint32_t SSP0CLKEN : 1; /*!< [12..12] Enable AHB clock for SSP0 */ + __IOM uint32_t SSP1CLKEN : 1; /*!< [13..13] Enable AHB clock for SSP1 */ + uint32_t : 2; + __IOM uint32_t USART0CLKEN : 1; /*!< [16..16] Enable AHB clock for USART0 */ + __IOM uint32_t USART1CLKEN : 1; /*!< [17..17] Enable AHB clock for USART1 */ + uint32_t : 2; + __IOM uint32_t I2C1CLKEN : 1; /*!< [20..20] Enable AHB clock for I2C1 */ + __IOM uint32_t I2C0CLKEN : 1; /*!< [21..21] Enable AHB clock for I2C0 */ + __IOM uint32_t I2SCLKEN : 1; /*!< [22..22] Enable AHB clock for I2S */ + __IOM uint32_t RTCCLKEN : 1; /*!< [23..23] Enable AHB clock for RTC */ + __IOM uint32_t WDTCLKEN : 1; /*!< [24..24] Enable AHB clock for WDT */ + uint32_t : 3; + __IOM uint32_t CLKOUTSEL : 3; /*!< [30..28] Clock output source selection */ + uint32_t : 1; + } AHBCLKEN_b; + } ; + + union { + __IOM uint32_t APBCP0; /*!< (@ 0x00000004) Offset:0x04 APB Clock Prescale Register 0 */ + + struct { + __IOM uint32_t CT16B0PRE : 3; /*!< [2..0] CT16B0 APB clock source prescaler */ + uint32_t : 1; + __IOM uint32_t CT16B1PRE : 3; /*!< [6..4] CT16B1 APB clock source prescaler */ + uint32_t : 1; + __IOM uint32_t CT32B0PRE : 3; /*!< [10..8] CT32B0 APB clock source prescaler */ + uint32_t : 1; + __IOM uint32_t CT32B1PRE : 3; /*!< [14..12] CT32B1 APB clock source prescaler */ + uint32_t : 1; + __IOM uint32_t ADCPRE : 3; /*!< [18..16] ADC APB clock source prescaler */ + uint32_t : 1; + __IOM uint32_t SSP0PRE : 3; /*!< [22..20] SSP0 APB clock source prescaler */ + uint32_t : 1; + __IOM uint32_t SSP1PRE : 3; /*!< [26..24] SSP1 APB clock source prescaler */ + uint32_t : 1; + __IOM uint32_t CT32B2PRE : 3; /*!< [30..28] CT32B2 APB clock source prescaler */ + uint32_t : 1; + } APBCP0_b; + } ; + + union { + __IOM uint32_t APBCP1; /*!< (@ 0x00000008) Offset:0x08 APB Clock Prescale Register 1 */ + + struct { + __IOM uint32_t USART0PRE : 3; /*!< [2..0] USART0 APB clock source prescaler */ + uint32_t : 1; + __IOM uint32_t USART1PRE : 3; /*!< [6..4] USART1 APB clock source prescaler */ + uint32_t : 1; + __IOM uint32_t I2C0PRE : 3; /*!< [10..8] I2C0 APB clock source prescaler */ + uint32_t : 1; + __IOM uint32_t I2SPRE : 3; /*!< [14..12] I2S APB clock source prescaler */ + uint32_t : 1; + __IOM uint32_t SYSTICKPRE : 2; /*!< [17..16] SysTick APB clock source prescaler */ + uint32_t : 2; + __IOM uint32_t WDTPRE : 3; /*!< [22..20] WDT APB clock source prescaler */ + uint32_t : 1; + __IOM uint32_t I2C1PRE : 3; /*!< [26..24] I2C1 APB clock source prescaler */ + uint32_t : 1; + __IOM uint32_t CT16B2PRE : 3; /*!< [30..28] CT16B2 APB clock source prescaler */ + uint32_t : 1; + } APBCP1_b; + } ; + + union { + __IOM uint32_t APBCP2; /*!< (@ 0x0000000C) Offset:0x0C APB Clock Prescale Register 2 */ + + struct { + __IOM uint32_t CLKOUTPRE : 4; /*!< [3..0] CLKOUT APB clock source prescaler */ + uint32_t : 28; + } APBCP2_b; + } ; + + union { + __IOM uint32_t PRST; /*!< (@ 0x00000010) Offset:0x10 Peripheral Reset Register */ + + struct { + __IOM uint32_t GPIO0RST : 1; /*!< [0..0] GPIO0 Reset */ + __IOM uint32_t GPIO1RST : 1; /*!< [1..1] GPIO1 Reset */ + __IOM uint32_t GPIO2RST : 1; /*!< [2..2] GPIO2 Reset */ + __IOM uint32_t GPIO3RST : 1; /*!< [3..3] GPIO3 Reset */ + uint32_t : 1; + __IOM uint32_t CT16B0RST : 1; /*!< [5..5] CT16B0 Reset */ + __IOM uint32_t CT16B1RST : 1; /*!< [6..6] CT16B1 Reset */ + __IOM uint32_t CT16B2RST : 1; /*!< [7..7] CT16B2 Reset */ + __IOM uint32_t CT32B0RST : 1; /*!< [8..8] CT32B0 Reset */ + __IOM uint32_t CT32B1RST : 1; /*!< [9..9] CT32B1 Reset */ + __IOM uint32_t CT32B2RST : 1; /*!< [10..10] CT32B2 Reset */ + __IOM uint32_t ADCRST : 1; /*!< [11..11] ADC Reset */ + __IOM uint32_t SSP0RST : 1; /*!< [12..12] SSP0 Reset */ + __IOM uint32_t SSP1RST : 1; /*!< [13..13] SSP1 Reset */ + uint32_t : 1; + __IOM uint32_t LCDRST : 1; /*!< [15..15] LCD Reset */ + __IOM uint32_t USART0RST : 1; /*!< [16..16] USART0 Reset */ + __IOM uint32_t USART1RST : 1; /*!< [17..17] USART1 Reset */ + uint32_t : 2; + __IOM uint32_t I2C1RST : 1; /*!< [20..20] I2C1 Reset */ + __IOM uint32_t I2C0RST : 1; /*!< [21..21] I2C0 Reset */ + __IOM uint32_t I2SRST : 1; /*!< [22..22] I2S Reset */ + __IOM uint32_t RTCRST : 1; /*!< [23..23] RTC Reset */ + __IOM uint32_t WDTRST : 1; /*!< [24..24] WDT Reset */ + __IOM uint32_t USBRST : 1; /*!< [25..25] USB Reset */ + uint32_t : 6; + } PRST_b; + } ; + __IM uint32_t RESERVED[3]; + __IOM uint32_t DIVIDEND; /*!< (@ 0x00000020) Offset:0x20 Divider Dividend Register */ + __IOM uint32_t DIVISOR; /*!< (@ 0x00000024) Offset:0x24 Divider Dividend Register */ + __IM uint32_t QUOTIENT; /*!< (@ 0x00000028) Offset:0x28 Divider Quotient Register */ + __IM uint32_t REMAINDER; /*!< (@ 0x0000002C) Offset:0x2C Divider Remainder Register */ + + union { + __IOM uint32_t DIVCTRL; /*!< (@ 0x00000030) Offset:0x30 Divider Control Register */ + + struct { + __IOM uint32_t DIVS : 1; /*!< [0..0] Divider start control bit */ + uint32_t : 31; + } DIVCTRL_b; + } ; +} SN_SYS1_Type; /*!< Size = 52 (0x34) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose I/O (SN_GPIO0) + */ + +typedef struct { /*!< (@ 0x40044000) SN_GPIO0 Structure */ + + union { + __IOM uint32_t DATA; /*!< (@ 0x00000000) Offset:0x00 GPIO Port n Data Register */ + + struct { + __IOM uint32_t DATA0 : 1; /*!< [0..0] Data of Pn.0 */ + __IOM uint32_t DATA1 : 1; /*!< [1..1] Data of Pn.1 */ + __IOM uint32_t DATA2 : 1; /*!< [2..2] Data of Pn.2 */ + __IOM uint32_t DATA3 : 1; /*!< [3..3] Data of Pn.3 */ + __IOM uint32_t DATA4 : 1; /*!< [4..4] Data of Pn.4 */ + __IOM uint32_t DATA5 : 1; /*!< [5..5] Data of Pn.5 */ + __IOM uint32_t DATA6 : 1; /*!< [6..6] Data of Pn.6 */ + __IOM uint32_t DATA7 : 1; /*!< [7..7] Data of Pn.7 */ + __IOM uint32_t DATA8 : 1; /*!< [8..8] Data of Pn.8 */ + __IOM uint32_t DATA9 : 1; /*!< [9..9] Data of Pn.9 */ + __IOM uint32_t DATA10 : 1; /*!< [10..10] Data of Pn.10 */ + __IOM uint32_t DATA11 : 1; /*!< [11..11] Data of Pn.11 */ + __IOM uint32_t DATA12 : 1; /*!< [12..12] Data of Pn.12 */ + __IOM uint32_t DATA13 : 1; /*!< [13..13] Data of Pn.13 */ + __IOM uint32_t DATA14 : 1; /*!< [14..14] Data of Pn.14 */ + __IOM uint32_t DATA15 : 1; /*!< [15..15] Data of Pn.15 */ + uint32_t : 16; + } DATA_b; + } ; + + union { + __IOM uint32_t MODE; /*!< (@ 0x00000004) Offset:0x04 GPIO Port n Mode Register */ + + struct { + __IOM uint32_t MODE0 : 1; /*!< [0..0] Mode of Pn.0 */ + __IOM uint32_t MODE1 : 1; /*!< [1..1] Mode of Pn.1 */ + __IOM uint32_t MODE2 : 1; /*!< [2..2] Mode of Pn.2 */ + __IOM uint32_t MODE3 : 1; /*!< [3..3] Mode of Pn.3 */ + __IOM uint32_t MODE4 : 1; /*!< [4..4] Mode of Pn.4 */ + __IOM uint32_t MODE5 : 1; /*!< [5..5] Mode of Pn.5 */ + __IOM uint32_t MODE6 : 1; /*!< [6..6] Mode of Pn.6 */ + __IOM uint32_t MODE7 : 1; /*!< [7..7] Mode of Pn.7 */ + __IOM uint32_t MODE8 : 1; /*!< [8..8] Mode of Pn.8 */ + __IOM uint32_t MODE9 : 1; /*!< [9..9] Mode of Pn.9 */ + __IOM uint32_t MODE10 : 1; /*!< [10..10] Mode of Pn.10 */ + __IOM uint32_t MODE11 : 1; /*!< [11..11] Mode of Pn.11 */ + __IOM uint32_t MODE12 : 1; /*!< [12..12] Mode of Pn.12 */ + __IOM uint32_t MODE13 : 1; /*!< [13..13] Mode of Pn.13 */ + __IOM uint32_t MODE14 : 1; /*!< [14..14] Mode of Pn.14 */ + __IOM uint32_t MODE15 : 1; /*!< [15..15] Mode of Pn.15 */ + __IOM uint32_t CURRENT0 : 1; /*!< [16..16] Driving/Sinking current of Pn.0 */ + __IOM uint32_t CURRENT1 : 1; /*!< [17..17] Driving/Sinking current of Pn.1 */ + __IOM uint32_t CURRENT2 : 1; /*!< [18..18] Driving/Sinking current of Pn.2 */ + __IOM uint32_t CURRENT3 : 1; /*!< [19..19] Driving/Sinking current of Pn.3 */ + __IOM uint32_t CURRENT4 : 1; /*!< [20..20] Driving/Sinking current of Pn.4 */ + __IOM uint32_t CURRENT5 : 1; /*!< [21..21] Driving/Sinking current of Pn.5 */ + __IOM uint32_t CURRENT6 : 1; /*!< [22..22] Driving/Sinking current of Pn.6 */ + __IOM uint32_t CURRENT7 : 1; /*!< [23..23] Driving/Sinking current of Pn.7 */ + __IOM uint32_t CURRENT8 : 1; /*!< [24..24] Driving/Sinking current of Pn.8 */ + __IOM uint32_t CURRENT9 : 1; /*!< [25..25] Driving/Sinking current of Pn.9 */ + __IOM uint32_t CURRENT10 : 1; /*!< [26..26] Driving/Sinking current of Pn.10 */ + __IOM uint32_t CURRENT11 : 1; /*!< [27..27] Driving/Sinking current of Pn.11 */ + __IOM uint32_t CURRENT12 : 1; /*!< [28..28] Driving/Sinking current of Pn.12 */ + __IOM uint32_t CURRENT13 : 1; /*!< [29..29] Driving/Sinking current of Pn.13 */ + __IOM uint32_t CURRENT14 : 1; /*!< [30..30] Driving/Sinking current of Pn.14 */ + __IOM uint32_t CURRENT15 : 1; /*!< [31..31] Driving/Sinking current of Pn.15 */ + } MODE_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000008) Offset:0x08 GPIO Port n Configuration Register */ + + struct { + __IOM uint32_t CFG0 : 2; /*!< [1..0] Configuration of Pn.0 */ + __IOM uint32_t CFG1 : 2; /*!< [3..2] Configuration of Pn.1 */ + __IOM uint32_t CFG2 : 2; /*!< [5..4] Configuration of Pn.2 */ + __IOM uint32_t CFG3 : 2; /*!< [7..6] Configuration of Pn.3 */ + __IOM uint32_t CFG4 : 2; /*!< [9..8] Configuration of Pn.4 */ + __IOM uint32_t CFG5 : 2; /*!< [11..10] Configuration of Pn.5 */ + __IOM uint32_t CFG6 : 2; /*!< [13..12] Configuration of Pn.6 */ + __IOM uint32_t CFG7 : 2; /*!< [15..14] Configuration of Pn.7 */ + __IOM uint32_t CFG8 : 2; /*!< [17..16] Configuration of Pn.8 */ + __IOM uint32_t CFG9 : 2; /*!< [19..18] Configuration of Pn.9 */ + __IOM uint32_t CFG10 : 2; /*!< [21..20] Configuration of Pn.10 */ + __IOM uint32_t CFG11 : 2; /*!< [23..22] Configuration of Pn.11 */ + __IOM uint32_t CFG12 : 2; /*!< [25..24] Configuration of Pn.12 */ + __IOM uint32_t CFG13 : 2; /*!< [27..26] Configuration of Pn.13 */ + __IOM uint32_t CFG14 : 2; /*!< [29..28] Configuration of Pn.14 */ + __IOM uint32_t CFG15 : 2; /*!< [31..30] Configuration of Pn.15 */ + } CFG_b; + } ; + + union { + __IOM uint32_t IS; /*!< (@ 0x0000000C) Offset:0x0C GPIO Port n Interrupt Sense Register */ + + struct { + __IOM uint32_t IS0 : 1; /*!< [0..0] Interrupt on Pn.0 is event or edge sensitive */ + __IOM uint32_t IS1 : 1; /*!< [1..1] Interrupt on Pn.1 is event or edge sensitive */ + __IOM uint32_t IS2 : 1; /*!< [2..2] Interrupt on Pn.2 is event or edge sensitive */ + __IOM uint32_t IS3 : 1; /*!< [3..3] Interrupt on Pn.3 is event or edge sensitive */ + __IOM uint32_t IS4 : 1; /*!< [4..4] Interrupt on Pn.4 is event or edge sensitive */ + __IOM uint32_t IS5 : 1; /*!< [5..5] Interrupt on Pn.5 is event or edge sensitive */ + __IOM uint32_t IS6 : 1; /*!< [6..6] Interrupt on Pn.6 is event or edge sensitive */ + __IOM uint32_t IS7 : 1; /*!< [7..7] Interrupt on Pn.7 is event or edge sensitive */ + __IOM uint32_t IS8 : 1; /*!< [8..8] Interrupt on Pn.8 is event or edge sensitive */ + __IOM uint32_t IS9 : 1; /*!< [9..9] Interrupt on Pn.9 is event or edge sensitive */ + __IOM uint32_t IS10 : 1; /*!< [10..10] Interrupt on Pn.10 is event or edge sensitive */ + __IOM uint32_t IS11 : 1; /*!< [11..11] Interrupt on Pn.11 is event or edge sensitive */ + __IOM uint32_t IS12 : 1; /*!< [12..12] Interrupt on Pn.12 is event or edge sensitive */ + __IOM uint32_t IS13 : 1; /*!< [13..13] Interrupt on Pn.13 is event or edge sensitive */ + __IOM uint32_t IS14 : 1; /*!< [14..14] Interrupt on Pn.14 is event or edge sensitive */ + __IOM uint32_t IS15 : 1; /*!< [15..15] Interrupt on Pn.15 is event or edge sensitive */ + uint32_t : 16; + } IS_b; + } ; + + union { + __IOM uint32_t IBS; /*!< (@ 0x00000010) Offset:0x10 GPIO Port n Interrupt Both-edge Sense + Register */ + + struct { + __IOM uint32_t IBS0 : 1; /*!< [0..0] Interrupt on Pn.0 is triggered ob both edges */ + __IOM uint32_t IBS1 : 1; /*!< [1..1] Interrupt on Pn.1 is triggered ob both edges */ + __IOM uint32_t IBS2 : 1; /*!< [2..2] Interrupt on Pn.2 is triggered ob both edges */ + __IOM uint32_t IBS3 : 1; /*!< [3..3] Interrupt on Pn.3 is triggered ob both edges */ + __IOM uint32_t IBS4 : 1; /*!< [4..4] Interrupt on Pn.4 is triggered ob both edges */ + __IOM uint32_t IBS5 : 1; /*!< [5..5] Interrupt on Pn.5 is triggered ob both edges */ + __IOM uint32_t IBS6 : 1; /*!< [6..6] Interrupt on Pn.6 is triggered ob both edges */ + __IOM uint32_t IBS7 : 1; /*!< [7..7] Interrupt on Pn.7 is triggered ob both edges */ + __IOM uint32_t IBS8 : 1; /*!< [8..8] Interrupt on Pn.8 is triggered ob both edges */ + __IOM uint32_t IBS9 : 1; /*!< [9..9] Interrupt on Pn.9 is triggered ob both edges */ + __IOM uint32_t IBS10 : 1; /*!< [10..10] Interrupt on Pn.10 is triggered ob both edges */ + __IOM uint32_t IBS11 : 1; /*!< [11..11] Interrupt on Pn.11 is triggered ob both edges */ + __IOM uint32_t IBS12 : 1; /*!< [12..12] Interrupt on Pn.12 is triggered ob both edges */ + __IOM uint32_t IBS13 : 1; /*!< [13..13] Interrupt on Pn.13 is triggered ob both edges */ + __IOM uint32_t IBS14 : 1; /*!< [14..14] Interrupt on Pn.14 is triggered ob both edges */ + __IOM uint32_t IBS15 : 1; /*!< [15..15] Interrupt on Pn.15 is triggered ob both edges */ + uint32_t : 16; + } IBS_b; + } ; + + union { + __IOM uint32_t IEV; /*!< (@ 0x00000014) Offset:0x14 GPIO Port n Interrupt Event Register */ + + struct { + __IOM uint32_t IEV0 : 1; /*!< [0..0] Interrupt trigged evnet on Pn.0 */ + __IOM uint32_t IEV1 : 1; /*!< [1..1] Interrupt trigged evnet on Pn.1 */ + __IOM uint32_t IEV2 : 1; /*!< [2..2] Interrupt trigged evnet on Pn.2 */ + __IOM uint32_t IEV3 : 1; /*!< [3..3] Interrupt trigged evnet on Pn.3 */ + __IOM uint32_t IEV4 : 1; /*!< [4..4] Interrupt trigged evnet on Pn.4 */ + __IOM uint32_t IEV5 : 1; /*!< [5..5] Interrupt trigged evnet on Pn.5 */ + __IOM uint32_t IEV6 : 1; /*!< [6..6] Interrupt trigged evnet on Pn.6 */ + __IOM uint32_t IEV7 : 1; /*!< [7..7] Interrupt trigged evnet on Pn.7 */ + __IOM uint32_t IEV8 : 1; /*!< [8..8] Interrupt trigged evnet on Pn.8 */ + __IOM uint32_t IEV9 : 1; /*!< [9..9] Interrupt trigged evnet on Pn.9 */ + __IOM uint32_t IEV10 : 1; /*!< [10..10] Interrupt trigged evnet on Pn.10 */ + __IOM uint32_t IEV11 : 1; /*!< [11..11] Interrupt trigged evnet on Pn.11 */ + __IOM uint32_t IEV12 : 1; /*!< [12..12] Interrupt trigged evnet on Pn.12 */ + __IOM uint32_t IEV13 : 1; /*!< [13..13] Interrupt trigged evnet on Pn.13 */ + __IOM uint32_t IEV14 : 1; /*!< [14..14] Interrupt trigged evnet on Pn.14 */ + __IOM uint32_t IEV15 : 1; /*!< [15..15] Interrupt trigged evnet on Pn.15 */ + uint32_t : 16; + } IEV_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000018) Offset:0x18 GPIO Port n Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] Interrupt on Pn.0 enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] Interrupt on Pn.1 enable */ + __IOM uint32_t IE2 : 1; /*!< [2..2] Interrupt on Pn.2 enable */ + __IOM uint32_t IE3 : 1; /*!< [3..3] Interrupt on Pn.3 enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] Interrupt on Pn.4 enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] Interrupt on Pn.5 enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] Interrupt on Pn.6 enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] Interrupt on Pn.7 enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] Interrupt on Pn.8 enable */ + __IOM uint32_t IE9 : 1; /*!< [9..9] Interrupt on Pn.9 enable */ + __IOM uint32_t IE10 : 1; /*!< [10..10] Interrupt on Pn.10 enable */ + __IOM uint32_t IE11 : 1; /*!< [11..11] Interrupt on Pn.11 enable */ + __IOM uint32_t IE12 : 1; /*!< [12..12] Interrupt on Pn.11 enable */ + __IOM uint32_t IE13 : 1; /*!< [13..13] Interrupt on Pn.13 enable */ + __IOM uint32_t IE14 : 1; /*!< [14..14] Interrupt on Pn.14 enable */ + __IOM uint32_t IE15 : 1; /*!< [15..15] Interrupt on Pn.15 enable */ + uint32_t : 16; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x0000001C) Offset:0x1C GPIO Port n Raw Interrupt Status + Register */ + + struct { + __IM uint32_t IF0 : 1; /*!< [0..0] Pn.0 raw interrupt flag */ + __IM uint32_t IF1 : 1; /*!< [1..1] Pn.1 raw interrupt flag */ + __IM uint32_t IF2 : 1; /*!< [2..2] Pn.2 raw interrupt flag */ + __IM uint32_t IF3 : 1; /*!< [3..3] Pn.3 raw interrupt flag */ + __IM uint32_t IF4 : 1; /*!< [4..4] Pn.4 raw interrupt flag */ + __IM uint32_t IF5 : 1; /*!< [5..5] Pn.5 raw interrupt flag */ + __IM uint32_t IF6 : 1; /*!< [6..6] Pn.6 raw interrupt flag */ + __IM uint32_t IF7 : 1; /*!< [7..7] Pn.7 raw interrupt flag */ + __IM uint32_t IF8 : 1; /*!< [8..8] Pn.8 raw interrupt flag */ + __IM uint32_t IF9 : 1; /*!< [9..9] Pn.9 raw interrupt flag */ + __IM uint32_t IF10 : 1; /*!< [10..10] Pn.10 raw interrupt flag */ + __IM uint32_t IF11 : 1; /*!< [11..11] Pn.11 raw interrupt flag */ + __IM uint32_t IF12 : 1; /*!< [12..12] Pn.12 raw interrupt flag */ + __IM uint32_t IF13 : 1; /*!< [13..13] Pn.13 raw interrupt flag */ + __IM uint32_t IF14 : 1; /*!< [14..14] Pn.14 raw interrupt flag */ + __IM uint32_t IF15 : 1; /*!< [15..15] Pn.15 raw interrupt flag */ + uint32_t : 16; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000020) Offset:0x20 GPIO Port n Interrupt Clear Register */ + + struct { + __OM uint32_t IC0 : 1; /*!< [0..0] Pn.0 interrupt flag clear */ + __OM uint32_t IC1 : 1; /*!< [1..1] Pn.1 interrupt flag clear */ + __OM uint32_t IC2 : 1; /*!< [2..2] Pn.2 interrupt flag clear */ + __OM uint32_t IC3 : 1; /*!< [3..3] Pn.3 interrupt flag clear */ + __OM uint32_t IC4 : 1; /*!< [4..4] Pn.4 interrupt flag clear */ + __OM uint32_t IC5 : 1; /*!< [5..5] Pn.5 interrupt flag clear */ + __OM uint32_t IC6 : 1; /*!< [6..6] Pn.6 interrupt flag clear */ + __OM uint32_t IC7 : 1; /*!< [7..7] Pn.7 interrupt flag clear */ + __OM uint32_t IC8 : 1; /*!< [8..8] Pn.8 interrupt flag clear */ + __OM uint32_t IC9 : 1; /*!< [9..9] Pn.9 interrupt flag clear */ + __OM uint32_t IC10 : 1; /*!< [10..10] Pn.10 interrupt flag clear */ + __OM uint32_t IC11 : 1; /*!< [11..11] Pn.11 interrupt flag clear */ + __OM uint32_t IC12 : 1; /*!< [12..12] Pn.12 interrupt flag clear */ + __OM uint32_t IC13 : 1; /*!< [13..13] Pn.13 interrupt flag clear */ + __OM uint32_t IC14 : 1; /*!< [14..14] Pn.14 interrupt flag clear */ + __OM uint32_t IC15 : 1; /*!< [15..15] Pn.15 interrupt flag clear */ + uint32_t : 16; + } IC_b; + } ; + + union { + __OM uint32_t BSET; /*!< (@ 0x00000024) Offset:0x24 GPIO Port n Bits Set Operation Register */ + + struct { + __OM uint32_t BSET0 : 1; /*!< [0..0] Set Pn.0 */ + __OM uint32_t BSET1 : 1; /*!< [1..1] Set Pn.1 */ + __OM uint32_t BSET2 : 1; /*!< [2..2] Set Pn.2 */ + __OM uint32_t BSET3 : 1; /*!< [3..3] Set Pn.3 */ + __OM uint32_t BSET4 : 1; /*!< [4..4] Set Pn.4 */ + __OM uint32_t BSET5 : 1; /*!< [5..5] Set Pn.5 */ + __OM uint32_t BSET6 : 1; /*!< [6..6] Set Pn.6 */ + __OM uint32_t BSET7 : 1; /*!< [7..7] Set Pn.7 */ + __OM uint32_t BSET8 : 1; /*!< [8..8] Set Pn.8 */ + __OM uint32_t BSET9 : 1; /*!< [9..9] Set Pn.9 */ + __OM uint32_t BSET10 : 1; /*!< [10..10] Set Pn.10 */ + __OM uint32_t BSET11 : 1; /*!< [11..11] Set Pn.11 */ + __OM uint32_t BSET12 : 1; /*!< [12..12] Set Pn.12 */ + __OM uint32_t BSET13 : 1; /*!< [13..13] Set Pn.13 */ + __OM uint32_t BSET14 : 1; /*!< [14..14] Set Pn.14 */ + __OM uint32_t BSET15 : 1; /*!< [15..15] Set Pn.15 */ + uint32_t : 16; + } BSET_b; + } ; + + union { + __OM uint32_t BCLR; /*!< (@ 0x00000028) Offset:0x28 GPIO Port n Bits Clear Operation + Register */ + + struct { + __OM uint32_t BCLR0 : 1; /*!< [0..0] Clear Pn.0 */ + __OM uint32_t BCLR1 : 1; /*!< [1..1] Clear Pn.1 */ + __OM uint32_t BCLR2 : 1; /*!< [2..2] Clear Pn.2 */ + __OM uint32_t BCLR3 : 1; /*!< [3..3] Clear Pn.3 */ + __OM uint32_t BCLR4 : 1; /*!< [4..4] Clear Pn.4 */ + __OM uint32_t BCLR5 : 1; /*!< [5..5] Clear Pn.5 */ + __OM uint32_t BCLR6 : 1; /*!< [6..6] Clear Pn.6 */ + __OM uint32_t BCLR7 : 1; /*!< [7..7] Clear Pn.7 */ + __OM uint32_t BCLR8 : 1; /*!< [8..8] Clear Pn.8 */ + __OM uint32_t BCLR9 : 1; /*!< [9..9] Clear Pn.9 */ + __OM uint32_t BCLR10 : 1; /*!< [10..10] Clear Pn.10 */ + __OM uint32_t BCLR11 : 1; /*!< [11..11] Clear Pn.11 */ + __OM uint32_t BCLR12 : 1; /*!< [12..12] Clear Pn.12 */ + __OM uint32_t BCLR13 : 1; /*!< [13..13] Clear Pn.13 */ + __OM uint32_t BCLR14 : 1; /*!< [14..14] Clear Pn.14 */ + __OM uint32_t BCLR15 : 1; /*!< [15..15] Clear Pn.15 */ + uint32_t : 16; + } BCLR_b; + } ; + + union { + __IOM uint32_t ODCTRL; /*!< (@ 0x0000002C) Offset:0x2C GPIO Port n Open-drain Control Register */ + + struct { + __IOM uint32_t OC0 : 1; /*!< [0..0] Pn.0 open-drain control */ + __IOM uint32_t OC1 : 1; /*!< [1..1] Pn.1 open-drain control */ + __IOM uint32_t OC2 : 1; /*!< [2..2] Pn.2 open-drain control */ + __IOM uint32_t OC3 : 1; /*!< [3..3] Pn.3 open-drain control */ + __IOM uint32_t OC4 : 1; /*!< [4..4] Pn.4 open-drain control */ + __IOM uint32_t OC5 : 1; /*!< [5..5] Pn.5 open-drain control */ + __IOM uint32_t OC6 : 1; /*!< [6..6] Pn.6 open-drain control */ + __IOM uint32_t OC7 : 1; /*!< [7..7] Pn.7 open-drain control */ + __IOM uint32_t OC8 : 1; /*!< [8..8] Pn.8 open-drain control */ + __IOM uint32_t OC9 : 1; /*!< [9..9] Pn.9 open-drain control */ + __IOM uint32_t OC10 : 1; /*!< [10..10] Pn.10 open-drain control */ + __IOM uint32_t OC11 : 1; /*!< [11..11] Pn.11 open-drain control */ + __IOM uint32_t OC12 : 1; /*!< [12..12] Pn.12 open-drain control */ + __IOM uint32_t OC13 : 1; /*!< [13..13] Pn.13 open-drain control */ + __IOM uint32_t OC14 : 1; /*!< [14..14] Pn.14 open-drain control */ + __IOM uint32_t OC15 : 1; /*!< [15..15] Pn.15 open-drain control */ + uint32_t : 16; + } ODCTRL_b; + } ; +} SN_GPIO0_Type; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO2 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose I/O (SN_GPIO2) + */ + +typedef struct { /*!< (@ 0x40048000) SN_GPIO2 Structure */ + + union { + __IOM uint32_t DATA; /*!< (@ 0x00000000) Offset:0x00 GPIO Port n Data Register */ + + struct { + __IOM uint32_t DATA0 : 1; /*!< [0..0] Data of Pn.0 */ + __IOM uint32_t DATA1 : 1; /*!< [1..1] Data of Pn.1 */ + __IOM uint32_t DATA2 : 1; /*!< [2..2] Data of Pn.2 */ + __IOM uint32_t DATA3 : 1; /*!< [3..3] Data of Pn.3 */ + __IOM uint32_t DATA4 : 1; /*!< [4..4] Data of Pn.4 */ + __IOM uint32_t DATA5 : 1; /*!< [5..5] Data of Pn.5 */ + __IOM uint32_t DATA6 : 1; /*!< [6..6] Data of Pn.6 */ + __IOM uint32_t DATA7 : 1; /*!< [7..7] Data of Pn.7 */ + __IOM uint32_t DATA8 : 1; /*!< [8..8] Data of Pn.8 */ + __IOM uint32_t DATA9 : 1; /*!< [9..9] Data of Pn.9 */ + __IOM uint32_t DATA10 : 1; /*!< [10..10] Data of Pn.10 */ + __IOM uint32_t DATA11 : 1; /*!< [11..11] Data of Pn.11 */ + __IOM uint32_t DATA12 : 1; /*!< [12..12] Data of Pn.12 */ + __IOM uint32_t DATA13 : 1; /*!< [13..13] Data of Pn.13 */ + __IOM uint32_t DATA14 : 1; /*!< [14..14] Data of Pn.14 */ + __IOM uint32_t DATA15 : 1; /*!< [15..15] Data of Pn.15 */ + uint32_t : 16; + } DATA_b; + } ; + + union { + __IOM uint32_t MODE; /*!< (@ 0x00000004) Offset:0x04 GPIO Port n Mode Register */ + + struct { + __IOM uint32_t MODE0 : 1; /*!< [0..0] Mode of Pn.0 */ + __IOM uint32_t MODE1 : 1; /*!< [1..1] Mode of Pn.1 */ + __IOM uint32_t MODE2 : 1; /*!< [2..2] Mode of Pn.2 */ + __IOM uint32_t MODE3 : 1; /*!< [3..3] Mode of Pn.3 */ + __IOM uint32_t MODE4 : 1; /*!< [4..4] Mode of Pn.4 */ + __IOM uint32_t MODE5 : 1; /*!< [5..5] Mode of Pn.5 */ + __IOM uint32_t MODE6 : 1; /*!< [6..6] Mode of Pn.6 */ + __IOM uint32_t MODE7 : 1; /*!< [7..7] Mode of Pn.7 */ + __IOM uint32_t MODE8 : 1; /*!< [8..8] Mode of Pn.8 */ + __IOM uint32_t MODE9 : 1; /*!< [9..9] Mode of Pn.9 */ + __IOM uint32_t MODE10 : 1; /*!< [10..10] Mode of Pn.10 */ + __IOM uint32_t MODE11 : 1; /*!< [11..11] Mode of Pn.11 */ + __IOM uint32_t MODE12 : 1; /*!< [12..12] Mode of Pn.12 */ + __IOM uint32_t MODE13 : 1; /*!< [13..13] Mode of Pn.13 */ + __IOM uint32_t MODE14 : 1; /*!< [14..14] Mode of Pn.14 */ + __IOM uint32_t MODE15 : 1; /*!< [15..15] Mode of Pn.15 */ + __IOM uint32_t CURRENT0 : 1; /*!< [16..16] Driving/Sinking current of Pn.0 */ + __IOM uint32_t CURRENT1 : 1; /*!< [17..17] Driving/Sinking current of Pn.1 */ + __IOM uint32_t CURRENT2 : 1; /*!< [18..18] Driving/Sinking current of Pn.2 */ + __IOM uint32_t CURRENT3 : 1; /*!< [19..19] Driving/Sinking current of Pn.3 */ + __IOM uint32_t CURRENT4 : 1; /*!< [20..20] Driving/Sinking current of Pn.4 */ + __IOM uint32_t CURRENT5 : 1; /*!< [21..21] Driving/Sinking current of Pn.5 */ + __IOM uint32_t CURRENT6 : 1; /*!< [22..22] Driving/Sinking current of Pn.6 */ + __IOM uint32_t CURRENT7 : 1; /*!< [23..23] Driving/Sinking current of Pn.7 */ + __IOM uint32_t CURRENT8 : 1; /*!< [24..24] Driving/Sinking current of Pn.8 */ + __IOM uint32_t CURRENT9 : 1; /*!< [25..25] Driving/Sinking current of Pn.9 */ + __IOM uint32_t CURRENT10 : 1; /*!< [26..26] Driving/Sinking current of Pn.10 */ + __IOM uint32_t CURRENT11 : 1; /*!< [27..27] Driving/Sinking current of Pn.11 */ + __IOM uint32_t CURRENT12 : 1; /*!< [28..28] Driving/Sinking current of Pn.12 */ + __IOM uint32_t CURRENT13 : 1; /*!< [29..29] Driving/Sinking current of Pn.13 */ + __IOM uint32_t CURRENT14 : 1; /*!< [30..30] Driving/Sinking current of Pn.14 */ + __IOM uint32_t CURRENT15 : 1; /*!< [31..31] Driving/Sinking current of Pn.15 */ + } MODE_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000008) Offset:0x08 GPIO Port n Configuration Register */ + + struct { + __IOM uint32_t CFG0 : 2; /*!< [1..0] Configuration of Pn.0 */ + __IOM uint32_t CFG1 : 2; /*!< [3..2] Configuration of Pn.1 */ + __IOM uint32_t CFG2 : 2; /*!< [5..4] Configuration of Pn.2 */ + __IOM uint32_t CFG3 : 2; /*!< [7..6] Configuration of Pn.3 */ + __IOM uint32_t CFG4 : 2; /*!< [9..8] Configuration of Pn.4 */ + __IOM uint32_t CFG5 : 2; /*!< [11..10] Configuration of Pn.5 */ + __IOM uint32_t CFG6 : 2; /*!< [13..12] Configuration of Pn.6 */ + __IOM uint32_t CFG7 : 2; /*!< [15..14] Configuration of Pn.7 */ + __IOM uint32_t CFG8 : 2; /*!< [17..16] Configuration of Pn.8 */ + __IOM uint32_t CFG9 : 2; /*!< [19..18] Configuration of Pn.9 */ + __IOM uint32_t CFG10 : 2; /*!< [21..20] Configuration of Pn.10 */ + __IOM uint32_t CFG11 : 2; /*!< [23..22] Configuration of Pn.11 */ + __IOM uint32_t CFG12 : 2; /*!< [25..24] Configuration of Pn.12 */ + __IOM uint32_t CFG13 : 2; /*!< [27..26] Configuration of Pn.13 */ + __IOM uint32_t CFG14 : 2; /*!< [29..28] Configuration of Pn.14 */ + __IOM uint32_t CFG15 : 2; /*!< [31..30] Configuration of Pn.15 */ + } CFG_b; + } ; + + union { + __IOM uint32_t IS; /*!< (@ 0x0000000C) Offset:0x0C GPIO Port n Interrupt Sense Register */ + + struct { + __IOM uint32_t IS0 : 1; /*!< [0..0] Interrupt on Pn.0 is event or edge sensitive */ + __IOM uint32_t IS1 : 1; /*!< [1..1] Interrupt on Pn.1 is event or edge sensitive */ + __IOM uint32_t IS2 : 1; /*!< [2..2] Interrupt on Pn.2 is event or edge sensitive */ + __IOM uint32_t IS3 : 1; /*!< [3..3] Interrupt on Pn.3 is event or edge sensitive */ + __IOM uint32_t IS4 : 1; /*!< [4..4] Interrupt on Pn.4 is event or edge sensitive */ + __IOM uint32_t IS5 : 1; /*!< [5..5] Interrupt on Pn.5 is event or edge sensitive */ + __IOM uint32_t IS6 : 1; /*!< [6..6] Interrupt on Pn.6 is event or edge sensitive */ + __IOM uint32_t IS7 : 1; /*!< [7..7] Interrupt on Pn.7 is event or edge sensitive */ + __IOM uint32_t IS8 : 1; /*!< [8..8] Interrupt on Pn.8 is event or edge sensitive */ + __IOM uint32_t IS9 : 1; /*!< [9..9] Interrupt on Pn.9 is event or edge sensitive */ + __IOM uint32_t IS10 : 1; /*!< [10..10] Interrupt on Pn.10 is event or edge sensitive */ + __IOM uint32_t IS11 : 1; /*!< [11..11] Interrupt on Pn.11 is event or edge sensitive */ + __IOM uint32_t IS12 : 1; /*!< [12..12] Interrupt on Pn.12 is event or edge sensitive */ + __IOM uint32_t IS13 : 1; /*!< [13..13] Interrupt on Pn.13 is event or edge sensitive */ + __IOM uint32_t IS14 : 1; /*!< [14..14] Interrupt on Pn.14 is event or edge sensitive */ + __IOM uint32_t IS15 : 1; /*!< [15..15] Interrupt on Pn.15 is event or edge sensitive */ + uint32_t : 16; + } IS_b; + } ; + + union { + __IOM uint32_t IBS; /*!< (@ 0x00000010) Offset:0x10 GPIO Port n Interrupt Both-edge Sense + Register */ + + struct { + __IOM uint32_t IBS0 : 1; /*!< [0..0] Interrupt on Pn.0 is triggered ob both edges */ + __IOM uint32_t IBS1 : 1; /*!< [1..1] Interrupt on Pn.1 is triggered ob both edges */ + __IOM uint32_t IBS2 : 1; /*!< [2..2] Interrupt on Pn.2 is triggered ob both edges */ + __IOM uint32_t IBS3 : 1; /*!< [3..3] Interrupt on Pn.3 is triggered ob both edges */ + __IOM uint32_t IBS4 : 1; /*!< [4..4] Interrupt on Pn.4 is triggered ob both edges */ + __IOM uint32_t IBS5 : 1; /*!< [5..5] Interrupt on Pn.5 is triggered ob both edges */ + __IOM uint32_t IBS6 : 1; /*!< [6..6] Interrupt on Pn.6 is triggered ob both edges */ + __IOM uint32_t IBS7 : 1; /*!< [7..7] Interrupt on Pn.7 is triggered ob both edges */ + __IOM uint32_t IBS8 : 1; /*!< [8..8] Interrupt on Pn.8 is triggered ob both edges */ + __IOM uint32_t IBS9 : 1; /*!< [9..9] Interrupt on Pn.9 is triggered ob both edges */ + __IOM uint32_t IBS10 : 1; /*!< [10..10] Interrupt on Pn.10 is triggered ob both edges */ + __IOM uint32_t IBS11 : 1; /*!< [11..11] Interrupt on Pn.11 is triggered ob both edges */ + __IOM uint32_t IBS12 : 1; /*!< [12..12] Interrupt on Pn.12 is triggered ob both edges */ + __IOM uint32_t IBS13 : 1; /*!< [13..13] Interrupt on Pn.13 is triggered ob both edges */ + __IOM uint32_t IBS14 : 1; /*!< [14..14] Interrupt on Pn.14 is triggered ob both edges */ + __IOM uint32_t IBS15 : 1; /*!< [15..15] Interrupt on Pn.15 is triggered ob both edges */ + uint32_t : 16; + } IBS_b; + } ; + + union { + __IOM uint32_t IEV; /*!< (@ 0x00000014) Offset:0x14 GPIO Port n Interrupt Event Register */ + + struct { + __IOM uint32_t IEV0 : 1; /*!< [0..0] Interrupt trigged evnet on Pn.0 */ + __IOM uint32_t IEV1 : 1; /*!< [1..1] Interrupt trigged evnet on Pn.1 */ + __IOM uint32_t IEV2 : 1; /*!< [2..2] Interrupt trigged evnet on Pn.2 */ + __IOM uint32_t IEV3 : 1; /*!< [3..3] Interrupt trigged evnet on Pn.3 */ + __IOM uint32_t IEV4 : 1; /*!< [4..4] Interrupt trigged evnet on Pn.4 */ + __IOM uint32_t IEV5 : 1; /*!< [5..5] Interrupt trigged evnet on Pn.5 */ + __IOM uint32_t IEV6 : 1; /*!< [6..6] Interrupt trigged evnet on Pn.6 */ + __IOM uint32_t IEV7 : 1; /*!< [7..7] Interrupt trigged evnet on Pn.7 */ + __IOM uint32_t IEV8 : 1; /*!< [8..8] Interrupt trigged evnet on Pn.8 */ + __IOM uint32_t IEV9 : 1; /*!< [9..9] Interrupt trigged evnet on Pn.9 */ + __IOM uint32_t IEV10 : 1; /*!< [10..10] Interrupt trigged evnet on Pn.10 */ + __IOM uint32_t IEV11 : 1; /*!< [11..11] Interrupt trigged evnet on Pn.11 */ + __IOM uint32_t IEV12 : 1; /*!< [12..12] Interrupt trigged evnet on Pn.12 */ + __IOM uint32_t IEV13 : 1; /*!< [13..13] Interrupt trigged evnet on Pn.13 */ + __IOM uint32_t IEV14 : 1; /*!< [14..14] Interrupt trigged evnet on Pn.14 */ + __IOM uint32_t IEV15 : 1; /*!< [15..15] Interrupt trigged evnet on Pn.15 */ + uint32_t : 16; + } IEV_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000018) Offset:0x18 GPIO Port n Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] Interrupt on Pn.0 enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] Interrupt on Pn.1 enable */ + __IOM uint32_t IE2 : 1; /*!< [2..2] Interrupt on Pn.2 enable */ + __IOM uint32_t IE3 : 1; /*!< [3..3] Interrupt on Pn.3 enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] Interrupt on Pn.4 enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] Interrupt on Pn.5 enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] Interrupt on Pn.6 enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] Interrupt on Pn.7 enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] Interrupt on Pn.8 enable */ + __IOM uint32_t IE9 : 1; /*!< [9..9] Interrupt on Pn.9 enable */ + __IOM uint32_t IE10 : 1; /*!< [10..10] Interrupt on Pn.10 enable */ + __IOM uint32_t IE11 : 1; /*!< [11..11] Interrupt on Pn.11 enable */ + __IOM uint32_t IE12 : 1; /*!< [12..12] Interrupt on Pn.11 enable */ + __IOM uint32_t IE13 : 1; /*!< [13..13] Interrupt on Pn.13 enable */ + __IOM uint32_t IE14 : 1; /*!< [14..14] Interrupt on Pn.14 enable */ + __IOM uint32_t IE15 : 1; /*!< [15..15] Interrupt on Pn.15 enable */ + uint32_t : 16; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x0000001C) Offset:0x1C GPIO Port n Raw Interrupt Status + Register */ + + struct { + __IM uint32_t IF0 : 1; /*!< [0..0] Pn.0 raw interrupt flag */ + __IM uint32_t IF1 : 1; /*!< [1..1] Pn.1 raw interrupt flag */ + __IM uint32_t IF2 : 1; /*!< [2..2] Pn.2 raw interrupt flag */ + __IM uint32_t IF3 : 1; /*!< [3..3] Pn.3 raw interrupt flag */ + __IM uint32_t IF4 : 1; /*!< [4..4] Pn.4 raw interrupt flag */ + __IM uint32_t IF5 : 1; /*!< [5..5] Pn.5 raw interrupt flag */ + __IM uint32_t IF6 : 1; /*!< [6..6] Pn.6 raw interrupt flag */ + __IM uint32_t IF7 : 1; /*!< [7..7] Pn.7 raw interrupt flag */ + __IM uint32_t IF8 : 1; /*!< [8..8] Pn.8 raw interrupt flag */ + __IM uint32_t IF9 : 1; /*!< [9..9] Pn.9 raw interrupt flag */ + __IM uint32_t IF10 : 1; /*!< [10..10] Pn.10 raw interrupt flag */ + __IM uint32_t IF11 : 1; /*!< [11..11] Pn.11 raw interrupt flag */ + __IM uint32_t IF12 : 1; /*!< [12..12] Pn.12 raw interrupt flag */ + __IM uint32_t IF13 : 1; /*!< [13..13] Pn.13 raw interrupt flag */ + __IM uint32_t IF14 : 1; /*!< [14..14] Pn.14 raw interrupt flag */ + __IM uint32_t IF15 : 1; /*!< [15..15] Pn.15 raw interrupt flag */ + uint32_t : 16; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000020) Offset:0x20 GPIO Port n Interrupt Clear Register */ + + struct { + __OM uint32_t IC0 : 1; /*!< [0..0] Pn.0 interrupt flag clear */ + __OM uint32_t IC1 : 1; /*!< [1..1] Pn.1 interrupt flag clear */ + __OM uint32_t IC2 : 1; /*!< [2..2] Pn.2 interrupt flag clear */ + __OM uint32_t IC3 : 1; /*!< [3..3] Pn.3 interrupt flag clear */ + __OM uint32_t IC4 : 1; /*!< [4..4] Pn.4 interrupt flag clear */ + __OM uint32_t IC5 : 1; /*!< [5..5] Pn.5 interrupt flag clear */ + __OM uint32_t IC6 : 1; /*!< [6..6] Pn.6 interrupt flag clear */ + __OM uint32_t IC7 : 1; /*!< [7..7] Pn.7 interrupt flag clear */ + __OM uint32_t IC8 : 1; /*!< [8..8] Pn.8 interrupt flag clear */ + __OM uint32_t IC9 : 1; /*!< [9..9] Pn.9 interrupt flag clear */ + __OM uint32_t IC10 : 1; /*!< [10..10] Pn.10 interrupt flag clear */ + __OM uint32_t IC11 : 1; /*!< [11..11] Pn.11 interrupt flag clear */ + __OM uint32_t IC12 : 1; /*!< [12..12] Pn.12 interrupt flag clear */ + __OM uint32_t IC13 : 1; /*!< [13..13] Pn.13 interrupt flag clear */ + __OM uint32_t IC14 : 1; /*!< [14..14] Pn.14 interrupt flag clear */ + __OM uint32_t IC15 : 1; /*!< [15..15] Pn.15 interrupt flag clear */ + uint32_t : 16; + } IC_b; + } ; + + union { + __OM uint32_t BSET; /*!< (@ 0x00000024) Offset:0x24 GPIO Port n Bits Set Operation Register */ + + struct { + __OM uint32_t BSET0 : 1; /*!< [0..0] Set Pn.0 */ + __OM uint32_t BSET1 : 1; /*!< [1..1] Set Pn.1 */ + __OM uint32_t BSET2 : 1; /*!< [2..2] Set Pn.2 */ + __OM uint32_t BSET3 : 1; /*!< [3..3] Set Pn.3 */ + __OM uint32_t BSET4 : 1; /*!< [4..4] Set Pn.4 */ + __OM uint32_t BSET5 : 1; /*!< [5..5] Set Pn.5 */ + __OM uint32_t BSET6 : 1; /*!< [6..6] Set Pn.6 */ + __OM uint32_t BSET7 : 1; /*!< [7..7] Set Pn.7 */ + __OM uint32_t BSET8 : 1; /*!< [8..8] Set Pn.8 */ + __OM uint32_t BSET9 : 1; /*!< [9..9] Set Pn.9 */ + __OM uint32_t BSET10 : 1; /*!< [10..10] Set Pn.10 */ + __OM uint32_t BSET11 : 1; /*!< [11..11] Set Pn.11 */ + __OM uint32_t BSET12 : 1; /*!< [12..12] Set Pn.12 */ + __OM uint32_t BSET13 : 1; /*!< [13..13] Set Pn.13 */ + __OM uint32_t BSET14 : 1; /*!< [14..14] Set Pn.14 */ + __OM uint32_t BSET15 : 1; /*!< [15..15] Set Pn.15 */ + uint32_t : 16; + } BSET_b; + } ; + + union { + __OM uint32_t BCLR; /*!< (@ 0x00000028) Offset:0x28 GPIO Port n Bits Clear Operation + Register */ + + struct { + __OM uint32_t BCLR0 : 1; /*!< [0..0] Clear Pn.0 */ + __OM uint32_t BCLR1 : 1; /*!< [1..1] Clear Pn.1 */ + __OM uint32_t BCLR2 : 1; /*!< [2..2] Clear Pn.2 */ + __OM uint32_t BCLR3 : 1; /*!< [3..3] Clear Pn.3 */ + __OM uint32_t BCLR4 : 1; /*!< [4..4] Clear Pn.4 */ + __OM uint32_t BCLR5 : 1; /*!< [5..5] Clear Pn.5 */ + __OM uint32_t BCLR6 : 1; /*!< [6..6] Clear Pn.6 */ + __OM uint32_t BCLR7 : 1; /*!< [7..7] Clear Pn.7 */ + __OM uint32_t BCLR8 : 1; /*!< [8..8] Clear Pn.8 */ + __OM uint32_t BCLR9 : 1; /*!< [9..9] Clear Pn.9 */ + __OM uint32_t BCLR10 : 1; /*!< [10..10] Clear Pn.10 */ + __OM uint32_t BCLR11 : 1; /*!< [11..11] Clear Pn.11 */ + __OM uint32_t BCLR12 : 1; /*!< [12..12] Clear Pn.12 */ + __OM uint32_t BCLR13 : 1; /*!< [13..13] Clear Pn.13 */ + __OM uint32_t BCLR14 : 1; /*!< [14..14] Clear Pn.14 */ + __OM uint32_t BCLR15 : 1; /*!< [15..15] Clear Pn.15 */ + uint32_t : 16; + } BCLR_b; + } ; + + union { + __IOM uint32_t ODCTRL; /*!< (@ 0x0000002C) Offset:0x2C GPIO Port n Open-drain Control Register */ + + struct { + __IOM uint32_t OC0 : 1; /*!< [0..0] Pn.0 open-drain control */ + __IOM uint32_t OC1 : 1; /*!< [1..1] Pn.1 open-drain control */ + __IOM uint32_t OC2 : 1; /*!< [2..2] Pn.2 open-drain control */ + __IOM uint32_t OC3 : 1; /*!< [3..3] Pn.3 open-drain control */ + __IOM uint32_t OC4 : 1; /*!< [4..4] Pn.4 open-drain control */ + __IOM uint32_t OC5 : 1; /*!< [5..5] Pn.5 open-drain control */ + __IOM uint32_t OC6 : 1; /*!< [6..6] Pn.6 open-drain control */ + __IOM uint32_t OC7 : 1; /*!< [7..7] Pn.7 open-drain control */ + __IOM uint32_t OC8 : 1; /*!< [8..8] Pn.8 open-drain control */ + __IOM uint32_t OC9 : 1; /*!< [9..9] Pn.9 open-drain control */ + __IOM uint32_t OC10 : 1; /*!< [10..10] Pn.10 open-drain control */ + __IOM uint32_t OC11 : 1; /*!< [11..11] Pn.11 open-drain control */ + __IOM uint32_t OC12 : 1; /*!< [12..12] Pn.12 open-drain control */ + __IOM uint32_t OC13 : 1; /*!< [13..13] Pn.13 open-drain control */ + __IOM uint32_t OC14 : 1; /*!< [14..14] Pn.14 open-drain control */ + __IOM uint32_t OC15 : 1; /*!< [15..15] Pn.15 open-drain control */ + uint32_t : 16; + } ODCTRL_b; + } ; +} SN_GPIO2_Type; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ADC (SN_ADC) + */ + +typedef struct { /*!< (@ 0x40026000) SN_ADC Structure */ + + union { + __IOM uint32_t ADM; /*!< (@ 0x00000000) Offset:0x00 ADC Management Register */ + + struct { + __IOM uint32_t CHS : 4; /*!< [3..0] ADC input channel */ + __IOM uint32_t GCHS : 1; /*!< [4..4] ADC global channel enable */ + __IOM uint32_t EOC : 1; /*!< [5..5] ADC status */ + __IOM uint32_t ADS : 1; /*!< [6..6] ADC start control */ + __IOM uint32_t ADLEN : 1; /*!< [7..7] ADC resolution */ + __IOM uint32_t ADCKS : 3; /*!< [10..8] ADC clock source divider */ + __IOM uint32_t ADENB : 1; /*!< [11..11] ADC enable */ + __IOM uint32_t AVREFHSEL : 1; /*!< [12..12] ADC high reference voltage source */ + uint32_t : 4; + __IOM uint32_t TSENB : 1; /*!< [17..17] Temperature sensor enable bit */ + uint32_t : 14; + } ADM_b; + } ; + __IM uint32_t ADB; /*!< (@ 0x00000004) Offset:0x04 ADC Data Register */ + + union { + __IM uint32_t P2CON; /*!< (@ 0x00000008) Offset:0x08 ADC Port 2 Control Register */ + + struct { + __IM uint32_t P2CON0 : 1; /*!< [0..0] P2.0 Control */ + __IM uint32_t P2CON1 : 1; /*!< [1..1] P2.1 Control */ + __IM uint32_t P2CON2 : 1; /*!< [2..2] P2.2 Control */ + __IM uint32_t P2CON3 : 1; /*!< [3..3] P2.3 Control */ + __IM uint32_t P2CON4 : 1; /*!< [4..4] P2.4 Control */ + __IM uint32_t P2CON5 : 1; /*!< [5..5] P2.5 Control */ + __IM uint32_t P2CON6 : 1; /*!< [6..6] P2.6 Control */ + __IM uint32_t P2CON7 : 1; /*!< [7..7] P2.7 Control */ + __IM uint32_t P2CON8 : 1; /*!< [8..8] P2.8 Control */ + __IM uint32_t P2CON9 : 1; /*!< [9..9] P2.9 Control */ + __IM uint32_t P2CON10 : 1; /*!< [10..10] P2.10 Control */ + __IM uint32_t P2CON11 : 1; /*!< [11..11] P2.11 Control */ + __IM uint32_t P2CON12 : 1; /*!< [12..12] P2.12 Control */ + __IM uint32_t P2CON13 : 1; /*!< [13..13] P2.13 Control */ + __IM uint32_t P2CON14 : 1; /*!< [14..14] P2.14 Control */ + __IM uint32_t P2CON15 : 1; /*!< [15..15] P2.15 Control */ + uint32_t : 16; + } P2CON_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x0000000C) Offset:0x0C ADC Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] AIN0 interrupt enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] AIN1 interrupt enable */ + __IOM uint32_t IE2 : 1; /*!< [2..2] AIN2 interrupt enable */ + __IOM uint32_t IE3 : 1; /*!< [3..3] AIN3 interrupt enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] AIN4 interrupt enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] AIN5 interrupt enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] AIN6 interrupt enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] AIN7 interrupt enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] AIN8 interrupt enable */ + __IOM uint32_t IE9 : 1; /*!< [9..9] AIN9 interrupt enable */ + __IOM uint32_t IE10 : 1; /*!< [10..10] AIN10 interrupt enable */ + __IOM uint32_t IE11 : 1; /*!< [11..11] AIN11 interrupt enable */ + __IOM uint32_t IE12 : 1; /*!< [12..12] AIN12 interrupt enable */ + __IOM uint32_t IE13 : 1; /*!< [13..13] AIN13 interrupt enable */ + __IOM uint32_t IE14 : 1; /*!< [14..14] AIN14 interrupt enable */ + uint32_t : 17; + } IE_b; + } ; + + union { + __IOM uint32_t RIS; /*!< (@ 0x00000010) Offset:0x10 ADC Raw Interrupt Status Register */ + + struct { + __IOM uint32_t IF0 : 1; /*!< [0..0] AIN0 interrupt flag */ + __IOM uint32_t IF1 : 1; /*!< [1..1] AIN1 interrupt flag */ + __IOM uint32_t IF2 : 1; /*!< [2..2] AIN2 interrupt flag */ + __IOM uint32_t IF3 : 1; /*!< [3..3] AIN0 interrupt flag */ + __IOM uint32_t IF4 : 1; /*!< [4..4] AIN4 interrupt flag */ + __IOM uint32_t IF5 : 1; /*!< [5..5] AIN5 interrupt flag */ + __IOM uint32_t IF6 : 1; /*!< [6..6] AIN6 interrupt flag */ + __IOM uint32_t IF7 : 1; /*!< [7..7] AIN7 interrupt flag */ + __IOM uint32_t IF8 : 1; /*!< [8..8] AIN8 interrupt flag */ + __IOM uint32_t IF9 : 1; /*!< [9..9] AIN9 interrupt flag */ + __IOM uint32_t IF10 : 1; /*!< [10..10] AIN10 interrupt flag */ + __IOM uint32_t IF11 : 1; /*!< [11..11] AIN11 interrupt flag */ + __IOM uint32_t IF12 : 1; /*!< [12..12] AIN12 interrupt flag */ + __IOM uint32_t IF13 : 1; /*!< [13..13] AIN13 interrupt flag */ + __IOM uint32_t IF14 : 1; /*!< [14..14] AIN14 interrupt flag */ + uint32_t : 17; + } RIS_b; + } ; +} SN_ADC_Type; /*!< Size = 20 (0x14) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (SN_WDT) + */ + +typedef struct { /*!< (@ 0x40010000) SN_WDT Structure */ + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000000) Offset:0x00 WDT Configuration Register */ + + struct { + __IOM uint32_t WDTEN : 1; /*!< [0..0] WDT enable */ + __IOM uint32_t WDTIE : 1; /*!< [1..1] WDT interrupt enable */ + __IOM uint32_t WDTINT : 1; /*!< [2..2] WDT interrupt flag */ + uint32_t : 13; + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } CFG_b; + } ; + + union { + __IOM uint32_t CLKSOURCE; /*!< (@ 0x00000004) Offset:0x04 WDT Clock Source Register */ + + struct { + __IOM uint32_t CLKSEL : 2; /*!< [1..0] WDT clock source */ + uint32_t : 14; + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } CLKSOURCE_b; + } ; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000008) Offset:0x08 WDT Timer Constant Register */ + + struct { + __IOM uint32_t TC : 8; /*!< [7..0] Watchdog timer constant reload value */ + uint32_t : 8; + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } TC_b; + } ; + + union { + __OM uint32_t FEED; /*!< (@ 0x0000000C) Offset:0x0C WDT Feed Register */ + + struct { + __OM uint32_t FV : 16; /*!< [15..0] Watchdog feed value */ + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } FEED_b; + } ; +} SN_WDT_Type; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real-time Clock (SN_RTC) + */ + +typedef struct { /*!< (@ 0x40012000) SN_RTC Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 RTC Control Register */ + + struct { + __IOM uint32_t RTCEN : 1; /*!< [0..0] RTC enable */ + uint32_t : 31; + } CTRL_b; + } ; + + union { + __IOM uint32_t CLKS; /*!< (@ 0x00000004) Offset:0x04 RTC Clock Source Register */ + + struct { + __IOM uint32_t CLKSEL : 2; /*!< [1..0] RTC clock source */ + uint32_t : 30; + } CLKS_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000008) Offset:0x08 RTC Interrupt Enable Register */ + + struct { + __IOM uint32_t SECIE : 1; /*!< [0..0] Second interrupt enable */ + __IOM uint32_t ALMIE : 1; /*!< [1..1] Alarm interrupt enable */ + __IOM uint32_t OVFIE : 1; /*!< [2..2] Overflow interrupt enable */ + uint32_t : 29; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x0000000C) Offset:0x0C RTC Raw Interrupt Status Register */ + + struct { + __IM uint32_t SECIF : 1; /*!< [0..0] Second interrupt flag */ + __IM uint32_t ALMIF : 1; /*!< [1..1] Alarm interrupt flag */ + __IM uint32_t OVFIF : 1; /*!< [2..2] Overflow interrupt flag */ + uint32_t : 29; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000010) Offset:0x10 RTC Interrupt Clear Register */ + + struct { + __OM uint32_t SECIC : 1; /*!< [0..0] Second interrupt flag clear */ + __OM uint32_t ALMIC : 1; /*!< [1..1] Alarm interrupt flag clear */ + __OM uint32_t OVFIC : 1; /*!< [2..2] Overflow interrupt flag clear */ + uint32_t : 29; + } IC_b; + } ; + __IOM uint32_t SECCNTV; /*!< (@ 0x00000014) Offset:0x14 RTC Second Counter Reload Value Register */ + __IM uint32_t SECCNT; /*!< (@ 0x00000018) Offset:0x18 RTC Second Counter Register */ + __IOM uint32_t ALMCNTV; /*!< (@ 0x0000001C) Offset:0x1C RTC Alarm Counter Reload Value Register */ + __IM uint32_t ALMCNT; /*!< (@ 0x00000020) Offset:0x20 RTC Alarm Counter Register */ +} SN_RTC_Type; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CT16B0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 16-bit Timer 0 with Capture function (SN_CT16B0) + */ + +typedef struct { /*!< (@ 0x40000000) SN_CT16B0 Structure */ + + union { + __IOM uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT16Bn Timer Control Register */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] Counter enable */ + __IOM uint32_t CRST : 1; /*!< [1..1] Counter Reset */ + uint32_t : 2; + __IOM uint32_t CM : 3; /*!< [6..4] Counting Mode */ + uint32_t : 25; + } TMRCTRL_b; + } ; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT16Bn Timer Counter Register */ + + struct { + __IOM uint32_t TC : 16; /*!< [15..0] Timer Counter */ + uint32_t : 16; + } TC_b; + } ; + + union { + __IOM uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT16Bn Prescale Register */ + + struct { + __IOM uint32_t PRE : 16; /*!< [15..0] Prescaler */ + uint32_t : 16; + } PRE_b; + } ; + + union { + __IOM uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT16Bn Prescale Counter Register */ + + struct { + __IOM uint32_t PC : 16; /*!< [15..0] Prescaler Counter */ + uint32_t : 16; + } PC_b; + } ; + + union { + __IOM uint32_t CNTCTRL; /*!< (@ 0x00000010) Offset:0x10 CT16Bn Counter Control Register */ + + struct { + __IOM uint32_t CTM : 2; /*!< [1..0] Counter/Timer Mode */ + __IOM uint32_t CIS : 2; /*!< [3..2] Counter Input Select */ + uint32_t : 28; + } CNTCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT16Bn Match Control Register */ + + struct { + __IOM uint32_t MR0IE : 1; /*!< [0..0] Enable generating an interrupt when MR0 matches TC */ + __IOM uint32_t MR0RST : 1; /*!< [1..1] Enable reset TC when MR0 matches TC */ + __IOM uint32_t MR0STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR0 matches TC */ + __IOM uint32_t MR1IE : 1; /*!< [3..3] Enable generating an interrupt when MR1 matches TC */ + __IOM uint32_t MR1RST : 1; /*!< [4..4] Enable reset TC when MR1 matches TC */ + __IOM uint32_t MR1STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR1 matches TC */ + __IOM uint32_t MR2IE : 1; /*!< [6..6] Enable generating an interrupt when MR2 matches TC */ + __IOM uint32_t MR2RST : 1; /*!< [7..7] Enable reset TC when MR2 matches TC */ + __IOM uint32_t MR2STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR2 matches TC */ + __IOM uint32_t MR3IE : 1; /*!< [9..9] Enable generating an interrupt when MR3 matches TC */ + __IOM uint32_t MR3RST : 1; /*!< [10..10] Enable reset TC when MR3 matches TC */ + __IOM uint32_t MR3STOP : 1; /*!< [11..11] Stop TC and PC and clear CEN bit when MR3 matches TC */ + uint32_t : 20; + } MCTRL_b; + } ; + __IOM uint32_t MR0; /*!< (@ 0x00000018) Offset:0x18 CT16Bn MR0 Register */ + __IOM uint32_t MR1; /*!< (@ 0x0000001C) Offset:0x1C CT16Bn MR1 Register */ + __IOM uint32_t MR2; /*!< (@ 0x00000020) Offset:0x20 CT16Bn MR2 Register */ + __IOM uint32_t MR3; /*!< (@ 0x00000024) Offset:0x24 CT16Bn MR3 Register */ + + union { + __IOM uint32_t CAPCTRL; /*!< (@ 0x00000028) Offset:0x28 CT16Bn Capture Control Register */ + + struct { + __IOM uint32_t CAP0RE : 1; /*!< [0..0] Capture on CT16Bn_CAP0 rising edge */ + __IOM uint32_t CAP0FE : 1; /*!< [1..1] Capture on CT16Bn_CAP0 falling edge */ + __IOM uint32_t CAP0IE : 1; /*!< [2..2] Interrupt on CT16Bn_CAP0 event */ + __IOM uint32_t CAP0EN : 1; /*!< [3..3] CAP0 function enable */ + uint32_t : 28; + } CAPCTRL_b; + } ; + + union { + __IM uint32_t CAP0; /*!< (@ 0x0000002C) Offset:0x2C CT16Bn CAP0 Register */ + + struct { + __IM uint32_t CAP0 : 16; /*!< [15..0] Timer counter capture value */ + uint32_t : 16; + } CAP0_b; + } ; + + union { + __IOM uint32_t EM; /*!< (@ 0x00000030) Offset:0x30 CT16Bn External Match Register */ + + struct { + __IOM uint32_t EM0 : 1; /*!< [0..0] When the TC matches MR0, this bit will act according + to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output. */ + __IOM uint32_t EM1 : 1; /*!< [1..1] When the TC matches MR1, this bit will act according + to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output. */ + __IOM uint32_t EM2 : 1; /*!< [2..2] When the TC matches MR2, this bit will act according + to EMC2[1:0], and also drive the state of CT16Bn_PWM2 output. */ + uint32_t : 1; + __IOM uint32_t EMC0 : 2; /*!< [5..4] CT16Bn_PWM0 functionality */ + __IOM uint32_t EMC1 : 2; /*!< [7..6] CT16Bn_PWM1 functionality */ + __IOM uint32_t EMC2 : 2; /*!< [9..8] CT16Bn_PWM2 functionality */ + uint32_t : 22; + } EM_b; + } ; + + union { + __IOM uint32_t PWMCTRL; /*!< (@ 0x00000034) Offset:0x34 CT16Bn PWM Control Register */ + + struct { + __IOM uint32_t PWM0EN : 1; /*!< [0..0] PWM0 enable */ + __IOM uint32_t PWM1EN : 1; /*!< [1..1] PWM1 enable */ + __IOM uint32_t PWM2EN : 1; /*!< [2..2] PWM2 enable */ + uint32_t : 1; + __IOM uint32_t PWM0M0DE : 2; /*!< [5..4] PWM0 output mode */ + __IOM uint32_t PWM1M0DE : 2; /*!< [7..6] PWM1 output mode */ + __IOM uint32_t PWM2M0DE : 2; /*!< [9..8] PWM2 output mode */ + uint32_t : 10; + __IOM uint32_t PWM0IOEN : 1; /*!< [20..20] CT16Bn_PWM0/GPIO selection */ + __IOM uint32_t PWM1IOEN : 1; /*!< [21..21] CT16Bn_PWM1/GPIO selection */ + __IOM uint32_t PWM2IOEN : 1; /*!< [22..22] CT16Bn_PWM2/GPIO selection */ + uint32_t : 9; + } PWMCTRL_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x00000038) Offset:0x38 CT16Bn Raw Interrupt Status Register */ + + struct { + __IM uint32_t MR0IF : 1; /*!< [0..0] Match channel 0 interrupt flag */ + __IM uint32_t MR1IF : 1; /*!< [1..1] Match channel 1 interrupt flag */ + __IM uint32_t MR2IF : 1; /*!< [2..2] Match channel 2 interrupt flag */ + __IM uint32_t MR3IF : 1; /*!< [3..3] Match channel 3 interrupt flag */ + __IM uint32_t CAP0IF : 1; /*!< [4..4] Capture channel 0 interrupt flag */ + uint32_t : 27; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x0000003C) Offset:0x3C CT16Bn Interrupt Clear Register */ + + struct { + __OM uint32_t MR0IC : 1; /*!< [0..0] MR0IF clear bit */ + __OM uint32_t MR1IC : 1; /*!< [1..1] MR1IF clear bit */ + __OM uint32_t MR2IC : 1; /*!< [2..2] MR2IF clear bit */ + __OM uint32_t MR3IC : 1; /*!< [3..3] MR3IF clear bit */ + __OM uint32_t CAP0IC : 1; /*!< [4..4] CAP0IF clear bit */ + uint32_t : 27; + } IC_b; + } ; +} SN_CT16B0_Type; /*!< Size = 64 (0x40) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CT32B0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 32-bit Timer 0 with Capture function (SN_CT32B0) + */ + +typedef struct { /*!< (@ 0x40006000) SN_CT32B0 Structure */ + + union { + __IOM uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT32Bn Timer Control Register */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] Counter Enable */ + __IOM uint32_t CRST : 1; /*!< [1..1] Counter Reset */ + uint32_t : 2; + __IOM uint32_t CM : 3; /*!< [6..4] Counting Mode */ + uint32_t : 25; + } TMRCTRL_b; + } ; + __IOM uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT32Bn Timer Counter Register */ + __IOM uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT32Bn Prescale Register */ + __IOM uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT32Bn Prescale Counter Register */ + + union { + __IOM uint32_t CNTCTRL; /*!< (@ 0x00000010) Offset:0x10 CT32Bn Counter Control Register */ + + struct { + __IOM uint32_t CTM : 2; /*!< [1..0] Counter/Timer Mode */ + __IOM uint32_t CIS : 2; /*!< [3..2] Counter Input Select */ + uint32_t : 28; + } CNTCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT32Bn Match Control Register */ + + struct { + __IOM uint32_t MR0IE : 1; /*!< [0..0] Enable generating an interrupt when MR0 matches TC */ + __IOM uint32_t MR0RST : 1; /*!< [1..1] Enable reset TC when MR0 matches TC */ + __IOM uint32_t MR0STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR0 matches TC */ + __IOM uint32_t MR1IE : 1; /*!< [3..3] Enable generating an interrupt when MR1 matches TC */ + __IOM uint32_t MR1RST : 1; /*!< [4..4] Enable reset TC when MR1 matches TC */ + __IOM uint32_t MR1STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR1 matches TC */ + __IOM uint32_t MR2IE : 1; /*!< [6..6] Enable generating an interrupt when MR2 matches TC */ + __IOM uint32_t MR2RST : 1; /*!< [7..7] Enable reset TC when MR2 matches TC */ + __IOM uint32_t MR2STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR2 matches TC */ + __IOM uint32_t MR3IE : 1; /*!< [9..9] Enable generating an interrupt when MR3 matches TC */ + __IOM uint32_t MR3RST : 1; /*!< [10..10] Enable reset TC when MR3 matches TC */ + __IOM uint32_t MR3STOP : 1; /*!< [11..11] Stop TC and PC and clear CEN bit when MR3 matches TC */ + uint32_t : 20; + } MCTRL_b; + } ; + __IOM uint32_t MR0; /*!< (@ 0x00000018) Offset:0x18 CT32Bn MR0 Register */ + __IOM uint32_t MR1; /*!< (@ 0x0000001C) Offset:0x1C CT32Bn MR1 Register */ + __IOM uint32_t MR2; /*!< (@ 0x00000020) Offset:0x20 CT32Bn MR2 Register */ + __IOM uint32_t MR3; /*!< (@ 0x00000024) Offset:0x24 CT32Bn MR3 Register */ + + union { + __IOM uint32_t CAPCTRL; /*!< (@ 0x00000028) Offset:0x28 CT32Bn Capture Control Register */ + + struct { + __IOM uint32_t CAP0RE : 1; /*!< [0..0] Capture on CT32Bn_CAP0 rising edge */ + __IOM uint32_t CAP0FE : 1; /*!< [1..1] Capture on CT32Bn_CAP0 falling edge */ + __IOM uint32_t CAP0IE : 1; /*!< [2..2] Interrupt on CT32Bn_CAP0 event */ + __IOM uint32_t CAP0EN : 1; /*!< [3..3] CAP0 function enable */ + uint32_t : 28; + } CAPCTRL_b; + } ; + __IM uint32_t CAP0; /*!< (@ 0x0000002C) Offset:0x2C CT32Bn CAP0 Register */ + + union { + __IOM uint32_t EM; /*!< (@ 0x00000030) Offset:0x30 CT32Bn External Match Register */ + + struct { + __IOM uint32_t EM0 : 1; /*!< [0..0] When the TC matches MR0, this bit will act according + to EMC0[1:0], and also drive the state of CT32Bn_PWM0 output. */ + __IOM uint32_t EM1 : 1; /*!< [1..1] When the TC matches MR1, this bit will act according + to EMC1[1:0], and also drive the state of CT32Bn_PWM1 output. */ + __IOM uint32_t EM2 : 1; /*!< [2..2] When the TC matches MR2, this bit will act according + to EMC2[1:0], and also drive the state of CT32Bn_PWM2 output. */ + __IOM uint32_t EM3 : 1; /*!< [3..3] When the TC matches MR3, this bit will act according + to EMC3[1:0], and also drive the state of CT32Bn_PWM3 output. */ + __IOM uint32_t EMC0 : 2; /*!< [5..4] CT32Bn_PWM0 functionality */ + __IOM uint32_t EMC1 : 2; /*!< [7..6] CT32Bn_PWM1 functionality */ + __IOM uint32_t EMC2 : 2; /*!< [9..8] CT32Bn_PWM2 functionality */ + __IOM uint32_t EMC3 : 2; /*!< [11..10] CT32Bn_PWM3 functionality */ + uint32_t : 20; + } EM_b; + } ; + + union { + __IOM uint32_t PWMCTRL; /*!< (@ 0x00000034) Offset:0x34 CT32Bn PWM Control Register */ + + struct { + __IOM uint32_t PWM0EN : 1; /*!< [0..0] PWM0 enable */ + __IOM uint32_t PWM1EN : 1; /*!< [1..1] PWM1 enable */ + __IOM uint32_t PWM2EN : 1; /*!< [2..2] PWM2 enable */ + __IOM uint32_t PWM3EN : 1; /*!< [3..3] PWM3 enable */ + __IOM uint32_t PWM0M0DE : 2; /*!< [5..4] PWM0 output mode */ + __IOM uint32_t PWM1M0DE : 2; /*!< [7..6] PWM1 output mode */ + __IOM uint32_t PWM2M0DE : 2; /*!< [9..8] PWM2 output mode */ + __IOM uint32_t PWM3M0DE : 2; /*!< [11..10] PWM3 output mode */ + uint32_t : 8; + __IOM uint32_t PWM0IOEN : 1; /*!< [20..20] CT32Bn_PWM0/GPIO selection */ + __IOM uint32_t PWM1IOEN : 1; /*!< [21..21] CT16Bn_PWM1/GPIO selection */ + __IOM uint32_t PWM2IOEN : 1; /*!< [22..22] CT32Bn_PWM2/GPIO selection */ + __IOM uint32_t PWM3IOEN : 1; /*!< [23..23] CT32Bn_PWM3/GPIO selection */ + uint32_t : 8; + } PWMCTRL_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x00000038) Offset:0x38 CT32Bn Raw Interrupt Status Register */ + + struct { + __IM uint32_t MR0IF : 1; /*!< [0..0] Match channel 0 interrupt flag */ + __IM uint32_t MR1IF : 1; /*!< [1..1] Match channel 1 interrupt flag */ + __IM uint32_t MR2IF : 1; /*!< [2..2] Match channel 2 interrupt flag */ + __IM uint32_t MR3IF : 1; /*!< [3..3] Match channel 3 interrupt flag */ + __IM uint32_t CAP0IF : 1; /*!< [4..4] Capture channel 0 interrupt flag */ + uint32_t : 27; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x0000003C) Offset:0x3C CT32Bn Interrupt Clear Register */ + + struct { + __OM uint32_t MR0IC : 1; /*!< [0..0] MR0IF clear bit */ + __OM uint32_t MR1IC : 1; /*!< [1..1] MR1IF clear bit */ + __OM uint32_t MR2IC : 1; /*!< [2..2] MR2IF clear bit */ + __OM uint32_t MR3IC : 1; /*!< [3..3] MR3IF clear bit */ + __OM uint32_t CAP0IC : 1; /*!< [4..4] CAP0IF clear bit */ + uint32_t : 27; + } IC_b; + } ; +} SN_CT32B0_Type; /*!< Size = 64 (0x40) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_PMU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power Management Unit (SN_PMU) + */ + +typedef struct { /*!< (@ 0x40032000) SN_PMU Structure */ + + union { + __IOM uint32_t BKP0; /*!< (@ 0x00000000) Offset:0x00 PMU Backup Register 0 */ + + struct { + __IOM uint32_t BACKUPDATA : 8; /*!< [7..0] Data retained */ + uint32_t : 24; + } BKP0_b; + } ; + + union { + __IOM uint32_t BKP1; /*!< (@ 0x00000004) Offset:0x04 PMU Backup Register 1 */ + + struct { + __IOM uint32_t BACKUPDATA : 8; /*!< [7..0] Data retained */ + uint32_t : 24; + } BKP1_b; + } ; + + union { + __IOM uint32_t BKP2; /*!< (@ 0x00000008) Offset:0x08 PMU Backup Register 2 */ + + struct { + __IOM uint32_t BACKUPDATA : 8; /*!< [7..0] Data retained */ + uint32_t : 24; + } BKP2_b; + } ; + + union { + __IOM uint32_t BKP3; /*!< (@ 0x0000000C) Offset:0x0C PMU Backup Register 3 */ + + struct { + __IOM uint32_t BACKUPDATA : 8; /*!< [7..0] Data retained */ + uint32_t : 24; + } BKP3_b; + } ; + + union { + __IOM uint32_t BKP4; /*!< (@ 0x00000010) Offset:0x10 PMU Backup Register 4 */ + + struct { + __IOM uint32_t BACKUPDATA : 8; /*!< [7..0] Data retained */ + uint32_t : 24; + } BKP4_b; + } ; + + union { + __IOM uint32_t BKP5; /*!< (@ 0x00000014) Offset:0x14 PMU Backup Register 5 */ + + struct { + __IOM uint32_t BACKUPDATA : 8; /*!< [7..0] Data retained */ + uint32_t : 24; + } BKP5_b; + } ; + + union { + __IOM uint32_t BKP6; /*!< (@ 0x00000018) Offset:0x18 PMU Backup Register 6 */ + + struct { + __IOM uint32_t BACKUPDATA : 8; /*!< [7..0] Data retained */ + uint32_t : 24; + } BKP6_b; + } ; + + union { + __IOM uint32_t BKP7; /*!< (@ 0x0000001C) Offset:0x1C PMU Backup Register 7 */ + + struct { + __IOM uint32_t BACKUPDATA : 8; /*!< [7..0] Data retained */ + uint32_t : 24; + } BKP7_b; + } ; + + union { + __IOM uint32_t BKP8; /*!< (@ 0x00000020) Offset:0x20 PMU Backup Register 8 */ + + struct { + __IOM uint32_t BACKUPDATA : 8; /*!< [7..0] Data retained */ + uint32_t : 24; + } BKP8_b; + } ; + + union { + __IOM uint32_t BKP9; /*!< (@ 0x00000024) Offset:0x24 PMU Backup Register 9 */ + + struct { + __IOM uint32_t BACKUPDATA : 8; /*!< [7..0] Data retained */ + uint32_t : 24; + } BKP9_b; + } ; + + union { + __IOM uint32_t BKP10; /*!< (@ 0x00000028) Offset:0x28 PMU Backup Register 10 */ + + struct { + __IOM uint32_t BACKUPDATA : 8; /*!< [7..0] Data retained */ + uint32_t : 24; + } BKP10_b; + } ; + + union { + __IOM uint32_t BKP11; /*!< (@ 0x0000002C) Offset:0x2C PMU Backup Register 11 */ + + struct { + __IOM uint32_t BACKUPDATA : 8; /*!< [7..0] Data retained */ + uint32_t : 24; + } BKP11_b; + } ; + + union { + __IOM uint32_t BKP12; /*!< (@ 0x00000030) Offset:0x30 PMU Backup Register 12 */ + + struct { + __IOM uint32_t BACKUPDATA : 8; /*!< [7..0] Data retained */ + uint32_t : 24; + } BKP12_b; + } ; + + union { + __IOM uint32_t BKP13; /*!< (@ 0x00000034) Offset:0x34 PMU Backup Register 13 */ + + struct { + __IOM uint32_t BACKUPDATA : 8; /*!< [7..0] Data retained */ + uint32_t : 24; + } BKP13_b; + } ; + + union { + __IOM uint32_t BKP14; /*!< (@ 0x00000038) Offset:0x38 PMU Backup Register 14 */ + + struct { + __IOM uint32_t BACKUPDATA : 8; /*!< [7..0] Data retained */ + uint32_t : 24; + } BKP14_b; + } ; + + union { + __IOM uint32_t BKP15; /*!< (@ 0x0000003C) Offset:0x3C PMU Backup Register 15 */ + + struct { + __IOM uint32_t BACKUPDATA : 8; /*!< [7..0] Data retained */ + uint32_t : 24; + } BKP15_b; + } ; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000040) Offset:0x40 PMU Control Register */ + + struct { + __IOM uint32_t MODE : 3; /*!< [2..0] Low Power mode selection */ + uint32_t : 29; + } CTRL_b; + } ; + + union { + __IOM uint32_t LATCHCTRL1; /*!< (@ 0x00000044) Offset:0x44 PMU Latch Control Register 1 */ + + struct { + __IOM uint32_t LATCHEN : 1; /*!< [0..0] Latch enable bit */ + uint32_t : 15; + __OM uint32_t LATCHKEY : 16; /*!< [31..16] Latch register key */ + } LATCHCTRL1_b; + } ; + + union { + __IOM uint32_t LATCHCTRL2; /*!< (@ 0x00000048) Offset:0x48 PMU Latch Control Register 2 */ + + struct { + __IOM uint32_t LATCHDIS : 1; /*!< [0..0] Latch disable bit */ + uint32_t : 15; + __OM uint32_t LATCHKEY : 16; /*!< [31..16] Latch register key */ + } LATCHCTRL2_b; + } ; + + union { + __IM uint32_t LATCHST; /*!< (@ 0x0000004C) Offset:0x4C PMU Latch Status Register */ + + struct { + __IM uint32_t LATCHST : 1; /*!< [0..0] Latch status */ + uint32_t : 31; + } LATCHST_b; + } ; +} SN_PMU_Type; /*!< Size = 80 (0x50) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SSP0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SSP0 (SN_SSP0) + */ + +typedef struct { /*!< (@ 0x4001C000) SN_SSP0 Structure */ + + union { + __IOM uint32_t CTRL0; /*!< (@ 0x00000000) Offset:0x00 SSPn Control Register 0 */ + + struct { + __IOM uint32_t SSPEN : 1; /*!< [0..0] SSP enable */ + __IOM uint32_t LOOPBACK : 1; /*!< [1..1] Loopback mode enable */ + __IOM uint32_t SDODIS : 1; /*!< [2..2] Slave data out disable */ + __IOM uint32_t MS : 1; /*!< [3..3] Master/Slave selection */ + __IOM uint32_t FORMAT : 1; /*!< [4..4] Interface format */ + uint32_t : 1; + __OM uint32_t FRESET : 2; /*!< [7..6] SSP FSM and FIFO Reset */ + __IOM uint32_t DL : 4; /*!< [11..8] Data length = DL[3:0]+1 */ + __IOM uint32_t TXFIFOTH : 3; /*!< [14..12] TX FIFO Threshold level */ + __IOM uint32_t RXFIFOTH : 3; /*!< [17..15] RX FIFO Threshold level */ + __IOM uint32_t SELDIS : 1; /*!< [18..18] Auto-SEL disable bit */ + uint32_t : 13; + } CTRL0_b; + } ; + + union { + __IOM uint32_t CTRL1; /*!< (@ 0x00000004) Offset:0x04 SSPn Control Register 1 */ + + struct { + __IOM uint32_t MLSB : 1; /*!< [0..0] MSB/LSB seletion */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock priority selection */ + __IOM uint32_t CPHA : 1; /*!< [2..2] Clock phase of edge sampling */ + uint32_t : 29; + } CTRL1_b; + } ; + + union { + __IOM uint32_t CLKDIV; /*!< (@ 0x00000008) Offset:0x08 SSPn Clock Divider Register */ + + struct { + __IOM uint32_t DIV : 8; /*!< [7..0] SSPn SCK=SSPn_PCLK/(2*DIV+2) */ + uint32_t : 24; + } CLKDIV_b; + } ; + + union { + __IM uint32_t STAT; /*!< (@ 0x0000000C) Offset:0x0C SSPn Status Register */ + + struct { + __IM uint32_t TX_EMPTY : 1; /*!< [0..0] TX FIFO empty flag */ + __IM uint32_t TX_FULL : 1; /*!< [1..1] TX FIFO full flag */ + __IM uint32_t RX_EMPTY : 1; /*!< [2..2] RX FIFO empty flag */ + __IM uint32_t RX_FULL : 1; /*!< [3..3] RX FIFO full flag */ + __IM uint32_t BUSY : 1; /*!< [4..4] Busy flag */ + __IM uint32_t TXFIFOTHF : 1; /*!< [5..5] TX FIFO threshold flag */ + __IM uint32_t RXFIFOTHF : 1; /*!< [6..6] RX FIFO threshold flag */ + uint32_t : 25; + } STAT_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000010) Offset:0x10 SSPn Interrupt Enable Register */ + + struct { + __IOM uint32_t RXOVFIE : 1; /*!< [0..0] RX FIFO overflow interrupt enable */ + __IOM uint32_t RXTOIE : 1; /*!< [1..1] RX time-out interrupt enable */ + __IOM uint32_t RXFIFOTHIE : 1; /*!< [2..2] RX FIFO threshold interrupt enable */ + __IOM uint32_t TXFIFOTHIE : 1; /*!< [3..3] TX FIFO threshold interrupt enable */ + uint32_t : 28; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x00000014) Offset:0x14 SSPn Raw Interrupt Status Register */ + + struct { + __IM uint32_t RXOVFIF : 1; /*!< [0..0] RX FIFO overflow interrupt flag */ + __IM uint32_t RXTOIF : 1; /*!< [1..1] RX time-out interrupt flag */ + __IM uint32_t RXFIFOTHIF : 1; /*!< [2..2] RX FIFO threshold interrupt flag */ + __IM uint32_t TXFIFOTHIF : 1; /*!< [3..3] TX FIFO threshold interrupt flag */ + uint32_t : 28; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000018) Offset:0x18 SSPn Interrupt Clear Register */ + + struct { + __OM uint32_t RXOVFIC : 1; /*!< [0..0] RX FIFO overflow flag clear */ + __OM uint32_t RXTOIC : 1; /*!< [1..1] RX time-out interrupt flag clear */ + __OM uint32_t RXFIFOTHIC : 1; /*!< [2..2] RX Interrupt flag Clear */ + __OM uint32_t TXFIFOTHIC : 1; /*!< [3..3] TX Interrupt flag Clear */ + uint32_t : 28; + } IC_b; + } ; + + union { + __IOM uint32_t DATA; /*!< (@ 0x0000001C) Offset:0x1C SSPn Data Register */ + + struct { + __IOM uint32_t Data : 16; /*!< [15..0] Data */ + uint32_t : 16; + } DATA_b; + } ; + + union { + __IOM uint32_t DF; /*!< (@ 0x00000020) Offset:0x20 SSPn Data Fetch Register */ + + struct { + __IOM uint32_t DF : 1; /*!< [0..0] SSP data fetch control bit */ + uint32_t : 31; + } DF_b; + } ; +} SN_SSP0_Type; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_I2C0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C0 (SN_I2C0) + */ + +typedef struct { /*!< (@ 0x40018000) SN_I2C0 Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 I2Cn Control Register */ + + struct { + uint32_t : 1; + __IOM uint32_t NACK : 1; /*!< [1..1] NACK assert flag */ + __IOM uint32_t ACK : 1; /*!< [2..2] ACK assert flag */ + uint32_t : 1; + __IOM uint32_t STO : 1; /*!< [4..4] STOP assert flag */ + __IOM uint32_t STA : 1; /*!< [5..5] START assert flag */ + uint32_t : 1; + __IOM uint32_t I2CMODE : 1; /*!< [7..7] I2C mode */ + __IOM uint32_t I2CEN : 1; /*!< [8..8] I2Cn interface enable */ + uint32_t : 23; + } CTRL_b; + } ; + + union { + __IOM uint32_t STAT; /*!< (@ 0x00000004) Offset:0x04 I2Cn Status Register */ + + struct { + __IM uint32_t RX_DN : 1; /*!< [0..0] RX done status */ + __IM uint32_t ACK_STAT : 1; /*!< [1..1] ACK done status */ + __IM uint32_t NACK_STAT : 1; /*!< [2..2] NACK done status */ + __IM uint32_t STOP_DN : 1; /*!< [3..3] STOP done status */ + __IM uint32_t START_DN : 1; /*!< [4..4] START done status */ + __IM uint32_t MST : 1; /*!< [5..5] I2C master/slave status */ + __IM uint32_t SLV_RX_HIT : 1; /*!< [6..6] Slave RX address hit flag */ + __IM uint32_t SLV_TX_HIT : 1; /*!< [7..7] Slave TX address hit flag */ + __IM uint32_t LOST_ARB : 1; /*!< [8..8] Lost arbitration status */ + __IM uint32_t TIMEOUT : 1; /*!< [9..9] Time-out status */ + uint32_t : 5; + __IOM uint32_t I2CIF : 1; /*!< [15..15] I2C interrupt flag */ + uint32_t : 16; + } STAT_b; + } ; + + union { + __IOM uint32_t TXDATA; /*!< (@ 0x00000008) Offset:0x08 I2Cn TX Data Register */ + + struct { + __IOM uint32_t Data : 8; /*!< [7..0] TX Data */ + uint32_t : 24; + } TXDATA_b; + } ; + + union { + __IM uint32_t RXDATA; /*!< (@ 0x0000000C) Offset:0x0C I2Cn RX Data Register */ + + struct { + __IM uint32_t Data : 8; /*!< [7..0] RX Data received when RX_DN=1 */ + uint32_t : 24; + } RXDATA_b; + } ; + + union { + __IOM uint32_t SLVADDR0; /*!< (@ 0x00000010) Offset:0x10 I2Cn Slave Address 0 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 0 */ + uint32_t : 20; + __IOM uint32_t GCEN : 1; /*!< [30..30] General call address enable */ + __IOM uint32_t ADD_MODE : 1; /*!< [31..31] Slave address mode */ + } SLVADDR0_b; + } ; + + union { + __IOM uint32_t SLVADDR1; /*!< (@ 0x00000014) Offset:0x14 I2Cn Slave Address 1 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 1 */ + uint32_t : 22; + } SLVADDR1_b; + } ; + + union { + __IOM uint32_t SLVADDR2; /*!< (@ 0x00000018) Offset:0x18 I2Cn Slave Address 2 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 2 */ + uint32_t : 22; + } SLVADDR2_b; + } ; + + union { + __IOM uint32_t SLVADDR3; /*!< (@ 0x0000001C) Offset:0x1C I2Cn Slave Address 3 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 3 */ + uint32_t : 22; + } SLVADDR3_b; + } ; + + union { + __IOM uint32_t SCLHT; /*!< (@ 0x00000020) Offset:0x20 I2Cn SCL High Time Register */ + + struct { + __IOM uint32_t SCLH : 8; /*!< [7..0] SCLn High period time=(SCLHT+1)*I2Cn_PCLK cycle */ + uint32_t : 24; + } SCLHT_b; + } ; + + union { + __IOM uint32_t SCLLT; /*!< (@ 0x00000024) Offset:0x24 I2Cn SCL Low Time Register */ + + struct { + __IOM uint32_t SCLL : 8; /*!< [7..0] SCLn Low period time=(SCLLT+1)*I2Cn_PCLK cycle */ + uint32_t : 24; + } SCLLT_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t TOCTRL; /*!< (@ 0x0000002C) Offset:0x2C I2Cn Timeout Control Register */ + + struct { + __IOM uint32_t TO : 16; /*!< [15..0] Timeout period time = TO*32*I2Cn_PCLK cycle */ + uint32_t : 16; + } TOCTRL_b; + } ; + + union { + __IOM uint32_t MMCTRL; /*!< (@ 0x00000030) Offset:0x30 I2Cn Monitor Mode Control Register */ + + struct { + __IOM uint32_t MMEN : 1; /*!< [0..0] Monitor mode enable */ + __IOM uint32_t SCLOEN : 1; /*!< [1..1] SCLn output enable */ + __IOM uint32_t MATCH_ALL : 1; /*!< [2..2] Match address selection */ + uint32_t : 29; + } MMCTRL_b; + } ; +} SN_I2C0_Type; /*!< Size = 52 (0x34) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_USART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief USART0 (SN_USART0) + */ + +typedef struct { /*!< (@ 0x40016000) SN_USART0 Structure */ + + union { + union { + __IM uint32_t RB; /*!< (@ 0x00000000) Offset:0x00 USARTn Receiver Buffer Register */ + + struct { + __IM uint32_t RB : 8; /*!< [7..0] The oldest received byte in USART RX FIFO */ + uint32_t : 24; + } RB_b; + } ; + + union { + __IOM uint32_t TH; /*!< (@ 0x00000000) Offset:0x00 USARTn Transmit Holding Register */ + + struct { + __OM uint32_t TH : 8; /*!< [7..0] The oldest byte to be transmitted in USART TX FIFO when + transmitter is available */ + uint32_t : 24; + } TH_b; + } ; + + union { + __IOM uint32_t DLL; /*!< (@ 0x00000000) Offset:0x00 USARTn Divisor Latch LSB Register */ + + struct { + __IOM uint32_t DLL : 8; /*!< [7..0] DLL and DLM register determines the baud rate of USARTn */ + uint32_t : 24; + } DLL_b; + } ; + }; + + union { + union { + __IOM uint32_t DLM; /*!< (@ 0x00000004) Offset:0x04 USARTn Divisor Latch MSB Register */ + + struct { + __IOM uint32_t DLM : 8; /*!< [7..0] DLL and DLM register determines the baud rate of USARTn */ + uint32_t : 24; + } DLM_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000004) Offset:0x04 USARTn Interrupt Enable Register */ + + struct { + __IOM uint32_t RDAIE : 1; /*!< [0..0] RDA interrupt enable */ + __IOM uint32_t THREIE : 1; /*!< [1..1] THRE interrupt enable */ + __IOM uint32_t RLSIE : 1; /*!< [2..2] RLS interrupt enable */ + __IOM uint32_t MSIE : 1; /*!< [3..3] MS interrupt enable */ + __IOM uint32_t TEMTIE : 1; /*!< [4..4] TEMT interrupt enable */ + uint32_t : 3; + __IOM uint32_t ABEOIE : 1; /*!< [8..8] ABE0 interrupt enable */ + __IOM uint32_t ABTOIE : 1; /*!< [9..9] ABT0 interrupt enable */ + __IOM uint32_t TXERRIE : 1; /*!< [10..10] TXERR interrupt enable */ + uint32_t : 21; + } IE_b; + } ; + }; + + union { + union { + __IM uint32_t II; /*!< (@ 0x00000008) Offset:0x08 USARTn Interrupt Identification Register */ + + struct { + __IM uint32_t INTSTATUS : 1; /*!< [0..0] Interrupt status */ + __IM uint32_t INTID : 3; /*!< [3..1] Interrupt ID of RX FIFO */ + uint32_t : 2; + __IM uint32_t FIFOEN : 2; /*!< [7..6] Equal to FIFOEN bits in USARTn_FIFOCTRL register */ + __IM uint32_t ABEOIF : 1; /*!< [8..8] ABEO interrupt flag */ + __IM uint32_t ABTOIF : 1; /*!< [9..9] ABTO interrupt flag */ + __IM uint32_t TXERRIF : 1; /*!< [10..10] TXERR interrupt flag */ + uint32_t : 21; + } II_b; + } ; + + union { + __OM uint32_t FIFOCTRL; /*!< (@ 0x00000008) Offset:0x08 USARTn FIFO Control Register */ + + struct { + __OM uint32_t FIFOEN : 1; /*!< [0..0] FIFO enable */ + __OM uint32_t RXFIFORST : 1; /*!< [1..1] RX FIFO reset */ + __OM uint32_t TXFIFORST : 1; /*!< [2..2] TX FIFO reset */ + uint32_t : 3; + __OM uint32_t RXTL : 2; /*!< [7..6] RX trigger level */ + uint32_t : 24; + } FIFOCTRL_b; + } ; + }; + + union { + __IOM uint32_t LC; /*!< (@ 0x0000000C) Offset:0x0C USARTn Line Control Register */ + + struct { + __IOM uint32_t WLS : 2; /*!< [1..0] Word length selection */ + __IOM uint32_t SBS : 1; /*!< [2..2] Stop bit selection */ + __IOM uint32_t PE : 1; /*!< [3..3] Parity enable */ + __IOM uint32_t PS : 2; /*!< [5..4] Parity selection */ + __IOM uint32_t BC : 1; /*!< [6..6] Break control */ + __IOM uint32_t DLAB : 1; /*!< [7..7] Divisor Latch access */ + uint32_t : 24; + } LC_b; + } ; + + union { + __IOM uint32_t MC; /*!< (@ 0x00000010) Offset:0x10 USARTn Modem Control Register */ + + struct { + uint32_t : 1; + __IOM uint32_t RTSCTRL : 1; /*!< [1..1] Source from modem output (RTS) pin */ + uint32_t : 4; + __IOM uint32_t RTSEN : 1; /*!< [6..6] RTS enable */ + __IOM uint32_t CTSEN : 1; /*!< [7..7] CTS enable */ + uint32_t : 24; + } MC_b; + } ; + + union { + __IM uint32_t LS; /*!< (@ 0x00000014) Offset:0x14 USARTn Line Status Register */ + + struct { + __IM uint32_t RDR : 1; /*!< [0..0] Receiver data ready flag */ + __IM uint32_t OE : 1; /*!< [1..1] Overrun error flag */ + __IM uint32_t PE : 1; /*!< [2..2] Parity error flag */ + __IM uint32_t FE : 1; /*!< [3..3] Framing error flag */ + __IM uint32_t BI : 1; /*!< [4..4] Break interrupt flag */ + __IM uint32_t THRE : 1; /*!< [5..5] THR empty flag */ + __IM uint32_t TEMT : 1; /*!< [6..6] Transmitter empty flag */ + __IM uint32_t RXFE : 1; /*!< [7..7] Receiver FIFO error flag */ + __IM uint32_t TXERR : 1; /*!< [8..8] TX error flag */ + uint32_t : 23; + } LS_b; + } ; + + union { + __IM uint32_t MS; /*!< (@ 0x00000018) Offset:0x18 USARTn Modem Status Register */ + + struct { + __IM uint32_t DCTS : 1; /*!< [0..0] Delta CTS */ + uint32_t : 3; + __IM uint32_t CTS : 1; /*!< [4..4] Complement of CTS pin input signal */ + uint32_t : 27; + } MS_b; + } ; + + union { + __IOM uint32_t SP; /*!< (@ 0x0000001C) Offset:0x1C USARTn Scratch Pad Register */ + + struct { + __IOM uint32_t PAD : 8; /*!< [7..0] Pad informaton */ + uint32_t : 24; + } SP_b; + } ; + + union { + __IOM uint32_t ABCTRL; /*!< (@ 0x00000020) Offset:0x20 USARTn Auto-baud Control Register */ + + struct { + __IOM uint32_t START : 1; /*!< [0..0] Auto-baud run bit */ + __IOM uint32_t MODE : 1; /*!< [1..1] Auto-baud mode selection */ + __IOM uint32_t AUTORESTART : 1; /*!< [2..2] Restart mode selection */ + uint32_t : 5; + __OM uint32_t ABEOIFC : 1; /*!< [8..8] Clear ABEOIF flag */ + __OM uint32_t ABTOIFC : 1; /*!< [9..9] Clear ABTOIF flag */ + uint32_t : 22; + } ABCTRL_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t FD; /*!< (@ 0x00000028) Offset:0x28 USARTn Fractional Divider Register */ + + struct { + __IOM uint32_t DIVADDVAL : 4; /*!< [3..0] Baud rate generation prescaler divisor value */ + __IOM uint32_t MULVAL : 4; /*!< [7..4] Baud rate generation prescaler multiplier value */ + __IOM uint32_t OVER8 : 1; /*!< [8..8] Oversampling value */ + uint32_t : 23; + } FD_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000030) Offset:0x30 USARTn Control Register */ + + struct { + __IOM uint32_t USARTEN : 1; /*!< [0..0] USART enable */ + __IOM uint32_t MODE : 3; /*!< [3..1] USART mode */ + uint32_t : 2; + __IOM uint32_t RXEN : 1; /*!< [6..6] RX enable */ + __IOM uint32_t TXEN : 1; /*!< [7..7] TX enable */ + uint32_t : 24; + } CTRL_b; + } ; + + union { + __IOM uint32_t HDEN; /*!< (@ 0x00000034) Offset:0x34 USARTn Control Register */ + + struct { + __IOM uint32_t HDEN : 1; /*!< [0..0] Half-duplex mode enable */ + uint32_t : 31; + } HDEN_b; + } ; + + union { + __IOM uint32_t SCICTRL; /*!< (@ 0x00000038) Offset:0x38 USARTn Smartcard Interface Control + Register */ + + struct { + uint32_t : 1; + __IOM uint32_t NACKDIS : 1; /*!< [1..1] NACK response disable */ + __IOM uint32_t PROTSEL : 1; /*!< [2..2] ISO7816-3 protocol selection */ + __IOM uint32_t SCLKEN : 1; /*!< [3..3] SCLK enable */ + uint32_t : 1; + __IOM uint32_t TXRETRY : 3; /*!< [7..5] Maximal number of retransmissions that USART will attempt */ + __IOM uint32_t XTRAGUARD : 8; /*!< [15..8] Extra guard time */ + __IOM uint32_t TC : 8; /*!< [23..16] Count for SCLK clock cycle */ + uint32_t : 8; + } SCICTRL_b; + } ; + + union { + __IOM uint32_t RS485CTRL; /*!< (@ 0x0000003C) Offset:0x3C USARTn RS485 Control Register */ + + struct { + __IOM uint32_t NMMEN : 1; /*!< [0..0] RS-485 normal multidrop mode enable */ + __IOM uint32_t RXEN : 1; /*!< [1..1] RS-485 receiver enable */ + __IOM uint32_t AADEN : 1; /*!< [2..2] Auto address detect enable */ + uint32_t : 1; + __IOM uint32_t ADCEN : 1; /*!< [4..4] Auto direction control enable */ + __IOM uint32_t OINV : 1; /*!< [5..5] Polarity control */ + uint32_t : 26; + } RS485CTRL_b; + } ; + + union { + __IOM uint32_t RS485ADRMATCH; /*!< (@ 0x00000040) Offset:0x40 USARTn RS485 Address Match Register */ + + struct { + __IOM uint32_t MATCH : 8; /*!< [7..0] RS-485 address value to be matched */ + uint32_t : 24; + } RS485ADRMATCH_b; + } ; + + union { + __IOM uint32_t RS485DLYV; /*!< (@ 0x00000044) Offset:0x44 USARTn RS485 Delay Value Register */ + + struct { + __IOM uint32_t DLY : 8; /*!< [7..0] RTS delay value */ + uint32_t : 24; + } RS485DLYV_b; + } ; + + union { + __IOM uint32_t SYNCCTRL; /*!< (@ 0x00000048) Offset:0x48 USARTn Synchronous Mode Control Register */ + + struct { + uint32_t : 1; + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock polarity selection */ + __IOM uint32_t CPHA : 1; /*!< [2..2] Clock phase for edge sampling */ + uint32_t : 29; + } SYNCCTRL_b; + } ; +} SN_USART0_Type; /*!< Size = 76 (0x4c) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_I2S ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2S (SN_I2S) + */ + +typedef struct { /*!< (@ 0x4001A000) SN_I2S Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 I2S Control Register */ + + struct { + __IOM uint32_t START : 1; /*!< [0..0] Start Transmit/Receive */ + __IOM uint32_t MUTE : 1; /*!< [1..1] Mute enable */ + __IOM uint32_t MONO : 1; /*!< [2..2] Mono/stereo selection */ + __IOM uint32_t MS : 1; /*!< [3..3] Master/Slave selection bit */ + __IOM uint32_t FORMAT : 2; /*!< [5..4] I2S operation format */ + __IOM uint32_t TXEN : 1; /*!< [6..6] Transmit enable bit */ + __IOM uint32_t RXEN : 1; /*!< [7..7] Receiver enable bit */ + __OM uint32_t CLRTXFIFO : 1; /*!< [8..8] Clear I2S TX FIFO */ + __OM uint32_t CLRRXFIFO : 1; /*!< [9..9] Clear I2S RX FIFO */ + __IOM uint32_t DL : 2; /*!< [11..10] Data length */ + __IOM uint32_t TXFIFOTH : 3; /*!< [14..12] TX FIFO threshold level */ + uint32_t : 1; + __IOM uint32_t RXFIFOTH : 3; /*!< [18..16] RX FIFO threshold level */ + uint32_t : 1; + __IOM uint32_t CHLENGTH : 5; /*!< [24..20] Bit number of single channel */ + uint32_t : 6; + __IOM uint32_t I2SEN : 1; /*!< [31..31] I2S enable */ + } CTRL_b; + } ; + + union { + __IOM uint32_t CLK; /*!< (@ 0x00000004) Offset:0x04 I2S Clock Register */ + + struct { + __IOM uint32_t MCLKDIV : 3; /*!< [2..0] MCLK divider */ + __IOM uint32_t MCLKOEN : 1; /*!< [3..3] MLCK output enable */ + __IOM uint32_t MCLKSEL : 1; /*!< [4..4] MLCK source selection */ + uint32_t : 3; + __IOM uint32_t BCLKDIV : 8; /*!< [15..8] BCLK divider */ + __IOM uint32_t CLKSEL : 1; /*!< [16..16] I2S clock source */ + uint32_t : 15; + } CLK_b; + } ; + + union { + __IM uint32_t STATUS; /*!< (@ 0x00000008) Offset:0x08 I2S Status Register */ + + struct { + __IM uint32_t I2SINT : 1; /*!< [0..0] I2S interrupt flag */ + __IM uint32_t RIGHTCH : 1; /*!< [1..1] Current channel status */ + uint32_t : 4; + __IM uint32_t TXFIFOTHF : 1; /*!< [6..6] TX FIFO threshold flag */ + __IM uint32_t RXFIFOTHF : 1; /*!< [7..7] RX FIFO threshold flag */ + __IM uint32_t TXFIFOFULL : 1; /*!< [8..8] TX FIFO full flag */ + __IM uint32_t RXFIFOFULL : 1; /*!< [9..9] RX FIFO full flag */ + __IM uint32_t TXFIFOEMPTY : 1; /*!< [10..10] TX FIFO empty flag */ + __IM uint32_t RXFIFOEMPTY : 1; /*!< [11..11] RX FIFO empty flag */ + __IM uint32_t TXFIFOLV : 4; /*!< [15..12] TX FIFO used level */ + uint32_t : 1; + __IM uint32_t RXFIFOLV : 4; /*!< [20..17] RX FIFO used level */ + uint32_t : 11; + } STATUS_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x0000000C) Offset:0x0C I2S Interrupt Enable Register */ + + struct { + uint32_t : 4; + __IOM uint32_t TXFIFOOVFIEN : 1; /*!< [4..4] TX FIFO overflow interrupt enable */ + __IOM uint32_t RXFIFOUDFIEN : 1; /*!< [5..5] RX FIFO underflow interrupt enable */ + __IOM uint32_t TXFIFOTHIEN : 1; /*!< [6..6] TX FIFO threshold interrupt enable */ + __IOM uint32_t RXFIFOTHIEN : 1; /*!< [7..7] RX FIFO threshold interrupt enable */ + uint32_t : 24; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x00000010) Offset:0x10 I2S Raw Interrupt Status Register */ + + struct { + uint32_t : 4; + __IM uint32_t TXFIFOOVIF : 1; /*!< [4..4] TX FIFO overflow interrupt flag */ + __IM uint32_t RXFIFOUDIF : 1; /*!< [5..5] RX FIFO underflow interrupt flag */ + __IM uint32_t TXFIFOTHIF : 1; /*!< [6..6] TX FIFO threshold interrupt flag */ + __IM uint32_t RXFIFOTHIF : 1; /*!< [7..7] RX FIFO threshold interrupt flag */ + uint32_t : 24; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000014) Offset:0x14 I2S Interrupt Clear Register */ + + struct { + uint32_t : 4; + __OM uint32_t TXFIFOOVIC : 1; /*!< [4..4] TX FIFO overflow interrupt clear */ + __OM uint32_t RXFIFOUDIC : 1; /*!< [5..5] RX FIFO underflow interrupt clear */ + __OM uint32_t TXFIFOTHIC : 1; /*!< [6..6] TX FIFO threshold interrupt clear */ + __OM uint32_t RXFIFOTHIC : 1; /*!< [7..7] RX FIFO threshold interrupt clear */ + uint32_t : 24; + } IC_b; + } ; + __IM uint32_t RXFIFO; /*!< (@ 0x00000018) Offset:0x18 I2S RX FIFO Register */ + __OM uint32_t TXFIFO; /*!< (@ 0x0000001C) Offset:0x1C I2S TX FIFO Register */ +} SN_I2S_Type; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_FLASH ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FLASH Memory Control Registers (SN_FLASH) + */ + +typedef struct { /*!< (@ 0x40062000) SN_FLASH Structure */ + + union { + __IOM uint32_t LPCTRL; /*!< (@ 0x00000000) Offset:0x00 Flash Low Power Control Register */ + + struct { + __IOM uint32_t LPMODE : 2; /*!< [1..0] Flash Low Power mode enable bit */ + uint32_t : 30; + } LPCTRL_b; + } ; + + union { + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Offset:0x04 Flash Status Register */ + + struct { + __IM uint32_t BUSY : 1; /*!< [0..0] Busy flag */ + uint32_t : 1; + __IOM uint32_t PGERR : 1; /*!< [2..2] Programming error flag */ + uint32_t : 29; + } STATUS_b; + } ; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000008) Offset:0x08 Flash Control Register */ + + struct { + __IOM uint32_t PG : 1; /*!< [0..0] Flash program enable bit */ + __IOM uint32_t PER : 1; /*!< [1..1] Page erase enable bit */ + uint32_t : 4; + __IOM uint32_t STARTE : 1; /*!< [6..6] Start erase enable bit */ + __IOM uint32_t CHK : 1; /*!< [7..7] Checksum calculation choosen */ + uint32_t : 24; + } CTRL_b; + } ; + __IOM uint32_t DATA; /*!< (@ 0x0000000C) Offset:0x0C Flash Data Register */ + __IOM uint32_t ADDR; /*!< (@ 0x00000010) Offset:0x10 Flash Address Register */ + __IM uint32_t CHKSUM; /*!< (@ 0x00000014) Offset:0x14 Flash Checksum Register */ +} SN_FLASH_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_PFPA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Peripheral Function Pin Assignment (SN_PFPA) + */ + +typedef struct { /*!< (@ 0x40042000) SN_PFPA Structure */ + + union { + __IOM uint32_t UART; /*!< (@ 0x00000000) Offset:0x00 PFPA for UART Register */ + + struct { + __IOM uint32_t UTXD0 : 4; /*!< [3..0] UTXD0 assigned pin */ + __IOM uint32_t URXD0 : 4; /*!< [7..4] URXD0 assigned pin */ + __IOM uint32_t UTXD1 : 4; /*!< [11..8] UTXD1 assigned pin */ + __IOM uint32_t URXD1 : 4; /*!< [15..12] URXD1 assigned pin */ + uint32_t : 16; + } UART_b; + } ; + + union { + __IOM uint32_t I2C; /*!< (@ 0x00000004) Offset:0x04 PFPA for I2C Register */ + + struct { + __IOM uint32_t SDA0 : 4; /*!< [3..0] SDA0 assigned pin */ + __IOM uint32_t SCL0 : 4; /*!< [7..4] SCL0 assigned pin */ + __IOM uint32_t SDA1 : 4; /*!< [11..8] SDA1 assigned pin */ + __IOM uint32_t SCL1 : 4; /*!< [15..12] SCL1 assigned pin */ + uint32_t : 16; + } I2C_b; + } ; + + union { + __IOM uint32_t SSP; /*!< (@ 0x00000008) Offset:0x08 PFPA for SSP Register */ + + struct { + __IOM uint32_t MISO0 : 4; /*!< [3..0] MISO0 assigned pin */ + __IOM uint32_t MOSI0 : 4; /*!< [7..4] MOSI0 assigned pin */ + __IOM uint32_t SCK0 : 4; /*!< [11..8] SCK0 assigned pin */ + __IOM uint32_t SEL0 : 4; /*!< [15..12] SEL0 assigned pin */ + __IOM uint32_t MISO1 : 4; /*!< [19..16] MISO1 assigned pin */ + __IOM uint32_t MOSI1 : 4; /*!< [23..20] MOSI1 assigned pin */ + __IOM uint32_t SCK1 : 4; /*!< [27..24] SCK1 assigned pin */ + __IOM uint32_t SEL1 : 4; /*!< [31..28] SEL1 assigned pin */ + } SSP_b; + } ; + + union { + __IOM uint32_t I2S; /*!< (@ 0x0000000C) Offset:0x0C PFPA for I2S Register */ + + struct { + __IOM uint32_t MCLK : 4; /*!< [3..0] I2SMCLK assigned pin */ + __IOM uint32_t BCLK : 4; /*!< [7..4] I2SBCLK assigned pin */ + __IOM uint32_t WS : 4; /*!< [11..8] I2SWS assigned pin */ + __IOM uint32_t DOUT : 4; /*!< [15..12] I2SDOUT assigned pin */ + __IOM uint32_t DIN : 4; /*!< [19..16] I2SDIN assigned pin */ + uint32_t : 12; + } I2S_b; + } ; + + union { + __IOM uint32_t CT16B0; /*!< (@ 0x00000010) Offset:0x10 PFPA for CT16B0 Register */ + + struct { + __IOM uint32_t CAP0 : 4; /*!< [3..0] CT16B0_CAP0 assigned pin */ + __IOM uint32_t PWM0 : 4; /*!< [7..4] CT16B0_PWM0 assigned pin */ + __IOM uint32_t PWM1 : 4; /*!< [11..8] CT16B0_PWM1 assigned pin */ + __IOM uint32_t PWM2 : 4; /*!< [15..12] CT16B0_PWM2 assigned pin */ + uint32_t : 16; + } CT16B0_b; + } ; + + union { + __IOM uint32_t CT16B1; /*!< (@ 0x00000014) Offset:0x14 PFPA for CT16B1 Register */ + + struct { + __IOM uint32_t CAP0 : 4; /*!< [3..0] CT16B1_CAP0 assigned pin */ + __IOM uint32_t PWM0 : 4; /*!< [7..4] CT16B1_PWM0 assigned pin */ + __IOM uint32_t PWM1 : 4; /*!< [11..8] CT16B1_PWM1 assigned pin */ + __IOM uint32_t PWM2 : 4; /*!< [15..12] CT16B1_PWM2 assigned pin */ + uint32_t : 16; + } CT16B1_b; + } ; + + union { + __IOM uint32_t CT16B2; /*!< (@ 0x00000018) Offset:0x18 PFPA for CT16B2 Register */ + + struct { + __IOM uint32_t CAP0 : 4; /*!< [3..0] CT16B2_CAP0 assigned pin */ + __IOM uint32_t PWM0 : 4; /*!< [7..4] CT16B2_PWM0 assigned pin */ + __IOM uint32_t PWM1 : 4; /*!< [11..8] CT16B2_PWM1 assigned pin */ + __IOM uint32_t PWM2 : 4; /*!< [15..12] CT16B2_PWM2 assigned pin */ + uint32_t : 16; + } CT16B2_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t CT32B0; /*!< (@ 0x00000020) Offset:0x20 PFPA for CT32B0 Register */ + + struct { + __IOM uint32_t CAP0 : 4; /*!< [3..0] CT32B0_CAP0 assigned pin */ + __IOM uint32_t PWM0 : 4; /*!< [7..4] CT32B0_PWM0 assigned pin */ + __IOM uint32_t PWM1 : 4; /*!< [11..8] CT32B0_PWM1 assigned pin */ + __IOM uint32_t PWM2 : 4; /*!< [15..12] CT32B0_PWM2 assigned pin */ + __IOM uint32_t PWM3 : 4; /*!< [19..16] CT32B0_PWM3 assigned pin */ + uint32_t : 12; + } CT32B0_b; + } ; + + union { + __IOM uint32_t CT32B1; /*!< (@ 0x00000024) Offset:0x24 PFPA for CT32B1 Register */ + + struct { + __IOM uint32_t CAP0 : 4; /*!< [3..0] CT32B1_CAP0 assigned pin */ + __IOM uint32_t PWM0 : 4; /*!< [7..4] CT32B1_PWM0 assigned pin */ + __IOM uint32_t PWM1 : 4; /*!< [11..8] CT32B1_PWM1 assigned pin */ + __IOM uint32_t PWM2 : 4; /*!< [15..12] CT32B1_PWM2 assigned pin */ + __IOM uint32_t PWM3 : 4; /*!< [19..16] CT32B1_PWM3 assigned pin */ + uint32_t : 12; + } CT32B1_b; + } ; + + union { + __IOM uint32_t CT32B2; /*!< (@ 0x00000028) Offset:0x28 PFPA for CT32B2 Register */ + + struct { + __IOM uint32_t CAP0 : 4; /*!< [3..0] CT32B2_CAP0 assigned pin */ + __IOM uint32_t PWM0 : 4; /*!< [7..4] CT32B2_PWM0 assigned pin */ + __IOM uint32_t PWM1 : 4; /*!< [11..8] CT32B2_PWM1 assigned pin */ + __IOM uint32_t PWM2 : 4; /*!< [15..12] CT32B2_PWM2 assigned pin */ + __IOM uint32_t PWM3 : 4; /*!< [19..16] CT32B2_PWM3 assigned pin */ + uint32_t : 12; + } CT32B2_b; + } ; +} SN_PFPA_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_USB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal Serial Bus Full Speed Device Interface (USB) (SN_USB) + */ + +typedef struct { /*!< (@ 0x4005C000) SN_USB Structure */ + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000000) Offset:0x00 USB Interrupt Enable Register */ + + struct { + __IOM uint32_t EP1_NAK_EN : 1; /*!< [0..0] EP1 NAK Interrupt Enable */ + __IOM uint32_t EP2_NAK_EN : 1; /*!< [1..1] EP2 NAK Interrupt Enable */ + __IOM uint32_t EP3_NAK_EN : 1; /*!< [2..2] EP3 NAK Interrupt Enable */ + __IOM uint32_t EP4_NAK_EN : 1; /*!< [3..3] EP4 NAK Interrupt Enable */ + __IOM uint32_t EP5_NAK_EN : 1; /*!< [4..4] EP5 NAK Interrupt Enable */ + __IOM uint32_t EP6_NAK_EN : 1; /*!< [5..5] EP6 NAK Interrupt Enable */ + uint32_t : 23; + __IOM uint32_t USB_IE : 1; /*!< [29..29] USB Event Interrupt Enable */ + __IOM uint32_t USB_SOF_IE : 1; /*!< [30..30] USB SOF Interrupt Enable */ + __IOM uint32_t BUS_IE : 1; /*!< [31..31] Bus Event Interrupt Enable */ + } INTEN_b; + } ; + + union { + __IM uint32_t INSTS; /*!< (@ 0x00000004) Offset:0x04 USB Interrupt Event Status Register */ + + struct { + __IM uint32_t EP1_NAK : 1; /*!< [0..0] Endpoint 1 NAK transaction flag */ + __IM uint32_t EP2_NAK : 1; /*!< [1..1] Endpoint 2 NAK transaction flag */ + __IM uint32_t EP3_NAK : 1; /*!< [2..2] Endpoint 3 NAK transaction flag */ + __IM uint32_t EP4_NAK : 1; /*!< [3..3] Endpoint 4 NAK transaction flag */ + __IM uint32_t EP5_NAK : 1; /*!< [4..4] Endpoint 5 NAK transaction flag */ + __IM uint32_t EP6_NAK : 1; /*!< [5..5] Endpoint 6 NAK transaction flag */ + uint32_t : 2; + __IM uint32_t EP1_ACK : 1; /*!< [8..8] Endpoint 1 ACK transaction flag */ + __IM uint32_t EP2_ACK : 1; /*!< [9..9] Endpoint 2 ACK transaction flag */ + __IM uint32_t EP3_ACK : 1; /*!< [10..10] Endpoint 3 ACK transaction flag */ + __IM uint32_t EP4_ACK : 1; /*!< [11..11] Endpoint 4 ACK transaction flag */ + __IM uint32_t EP5_ACK : 1; /*!< [12..12] Endpoint 5 ACK transaction flag */ + __IM uint32_t EP6_ACK : 1; /*!< [13..13] Endpoint 6 ACK transaction flag */ + uint32_t : 3; + __IM uint32_t ERR_TIMEOUT : 1; /*!< [17..17] Timeout Status */ + __IM uint32_t ERR_SETUP : 1; /*!< [18..18] Wrong Setup data received */ + __IM uint32_t EP0_OUT_STALL : 1; /*!< [19..19] EP0 OUT STALL transaction */ + __IM uint32_t EP0_IN_STALL : 1; /*!< [20..20] EP0 IN STALL Transaction is completed */ + __IM uint32_t EP0_OUT : 1; /*!< [21..21] EP0 OUT ACK Transaction Flag */ + __IM uint32_t EP0_IN : 1; /*!< [22..22] EP0 IN ACK Transaction Flag */ + __IM uint32_t EP0_SETUP : 1; /*!< [23..23] EP0 Setup Transaction Flag */ + __IM uint32_t EP0_PRESETUP : 1; /*!< [24..24] EP0 Setup Token Packet Flag */ + __IM uint32_t BUS_WAKEUP : 1; /*!< [25..25] Bus Wakeup Flag */ + __IM uint32_t USB_SOF : 1; /*!< [26..26] USB SOF packet received flag */ + uint32_t : 2; + __IM uint32_t BUS_RESUME : 1; /*!< [29..29] USB Bus Resume signal flag */ + __IM uint32_t BUS_SUSPEND : 1; /*!< [30..30] USB Bus Suspend signal flag */ + __IM uint32_t BUS_RESET : 1; /*!< [31..31] USB Bus Reset signal flag */ + } INSTS_b; + } ; + + union { + __OM uint32_t INSTSC; /*!< (@ 0x00000008) Offset:0x08 USB Interrupt Event Status Clear + Register */ + + struct { + __OM uint32_t EP1_NAKC : 1; /*!< [0..0] EP1 NAK clear bit */ + __OM uint32_t EP2_NAKC : 1; /*!< [1..1] EP2 NAK clear bit */ + __OM uint32_t EP3_NAKC : 1; /*!< [2..2] EP3 NAK clear bit */ + __OM uint32_t EP4_NAKC : 1; /*!< [3..3] EP4 NAK clear bit */ + __OM uint32_t EP5_NAKC : 1; /*!< [4..4] EP5 NAK clear bit */ + __OM uint32_t EP6_NAKC : 1; /*!< [5..5] EP6 NAK clear bit */ + uint32_t : 2; + __OM uint32_t EP1_ACKC : 1; /*!< [8..8] EP1 ACK clear bit */ + __OM uint32_t EP2_ACKC : 1; /*!< [9..9] EP2 ACK clear bit */ + __OM uint32_t EP3_ACKC : 1; /*!< [10..10] EP3 ACK clear bit */ + __OM uint32_t EP4_ACKC : 1; /*!< [11..11] EP4 ACK clear bit */ + __OM uint32_t EP5_ACKC : 1; /*!< [12..12] EP5 ACK clear bit */ + __OM uint32_t EP6_ACKC : 1; /*!< [13..13] EP6 ACK clear bit */ + uint32_t : 3; + __OM uint32_t ERR_TIMEOUTC : 1; /*!< [17..17] Timeout Error clear bit */ + __OM uint32_t ERR_SETUPC : 1; /*!< [18..18] Error Setup clear bit */ + __OM uint32_t EP0_OUT_STALLC : 1; /*!< [19..19] EP0 OUT STALL clear bit */ + __OM uint32_t EP0_IN_STALLC : 1; /*!< [20..20] EP0 IN STALL clear bit */ + __OM uint32_t EP0_OUTC : 1; /*!< [21..21] EP0 OUT clear bit */ + __OM uint32_t EP0_INC : 1; /*!< [22..22] EP0 IN clear bit */ + __OM uint32_t EP0_SETUPC : 1; /*!< [23..23] EP0 SETUP clear bit */ + __OM uint32_t EP0_PRESETUPC : 1; /*!< [24..24] EP0 PRESETUP clear bit */ + __OM uint32_t BUS_WAKEUPC : 1; /*!< [25..25] Bus Wakeup clear bit */ + __OM uint32_t USB_SOFC : 1; /*!< [26..26] USB SOF clear bit */ + uint32_t : 2; + __OM uint32_t BUS_RESUMEC : 1; /*!< [29..29] USB Bus Resume clear bit */ + uint32_t : 1; + __OM uint32_t BUS_RESETC : 1; /*!< [31..31] USB Bus Reset clear bit */ + } INSTSC_b; + } ; + + union { + __IOM uint32_t ADDR; /*!< (@ 0x0000000C) Offset:0x0C USB Device Address Register */ + + struct { + __IOM uint32_t UADDR : 7; /*!< [6..0] USB device's address */ + uint32_t : 25; + } ADDR_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000010) Offset:0x10 USB Configuration Register */ + + struct { + __IOM uint32_t EP1_DIR : 1; /*!< [0..0] Endpoint 1 IN/OUT direction setting */ + __IOM uint32_t EP2_DIR : 1; /*!< [1..1] Endpoint 2 IN/OUT direction setting */ + __IOM uint32_t EP3_DIR : 1; /*!< [2..2] Endpoint 3 IN/OUT direction setting */ + __IOM uint32_t EP4_DIR : 1; /*!< [3..3] Endpoint 4 IN/OUT direction setting */ + __IOM uint32_t EP5_DIR : 1; /*!< [4..4] Endpoint 5 IN/OUT direction setting */ + __IOM uint32_t EP6_DIR : 1; /*!< [5..5] Endpoint 6 IN/OUT direction setting */ + uint32_t : 2; + __IOM uint32_t EP1_ISO : 1; /*!< [8..8] Endpoint 1 ISO mode setting */ + __IOM uint32_t EP2_ISO : 1; /*!< [9..9] Endpoint 2 ISO mode setting */ + __IOM uint32_t EP3_ISO : 1; /*!< [10..10] Endpoint 3 ISO mode setting */ + __IOM uint32_t EP4_ISO : 1; /*!< [11..11] Endpoint 4 ISO mode setting */ + __IOM uint32_t EP5_ISO : 1; /*!< [12..12] Endpoint 5 ISO mode setting */ + __IOM uint32_t EP6_ISO : 1; /*!< [13..13] Endpoint 6 ISO mode setting */ + uint32_t : 10; + __IOM uint32_t VREG33DIS_EN : 1; /*!< [24..24] Enable 400ohm discharge path of VREG33 to GND */ + __IOM uint32_t USBRAM_EN : 1; /*!< [25..25] Enable USB 512-byte RAM function */ + __IOM uint32_t FLTDET_PUEN : 1; /*!< [26..26] Enable internal D+ and D- weak pull-up resistor */ + __IOM uint32_t EMC_EN : 1; /*!< [27..27] Enable USB EMC protection */ + __IOM uint32_t SIE_EN : 1; /*!< [28..28] USB Serial Interface Engine Enable */ + __IOM uint32_t DPPU_EN : 1; /*!< [29..29] Enable internal D+ 1.5k pull-up resistor */ + __IOM uint32_t PHY_EN : 1; /*!< [30..30] PHY Transceiver Function Enable */ + __IOM uint32_t VREG33_EN : 1; /*!< [31..31] Enable the internal VREG33 ouput */ + } CFG_b; + } ; + + union { + __IOM uint32_t SGCTL; /*!< (@ 0x00000014) Offset:0x14 USB Signal Control Register */ + + struct { + __IOM uint32_t BUS_DN : 1; /*!< [0..0] USB D- state */ + __IOM uint32_t BUS_DP : 1; /*!< [1..1] USB DP state */ + __IOM uint32_t BUS_DRVEN : 1; /*!< [2..2] Enable to drive USB bus */ + uint32_t : 29; + } SGCTL_b; + } ; + + union { + __IOM uint32_t EP0CTL; /*!< (@ 0x00000018) Offset:0x18 USB Endpoint 0 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 20; + __IOM uint32_t OUT_STALL_EN : 1; /*!< [27..27] Enable EP0 OUT STALL handshake */ + __IOM uint32_t IN_STALL_EN : 1; /*!< [28..28] Enable EP0 IN STALL handshake */ + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Enable Endpoint 0 Function */ + } EP0CTL_b; + } ; + + union { + __IOM uint32_t EP1CTL; /*!< (@ 0x0000001C) Offset:0x1C USB Endpoint 1 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 9; /*!< [8..0] Endpoint byte count */ + uint32_t : 20; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 1 Function enable bit */ + } EP1CTL_b; + } ; + + union { + __IOM uint32_t EP2CTL; /*!< (@ 0x00000020) Offset:0x20 USB Endpoint 2 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 9; /*!< [8..0] Endpoint byte count */ + uint32_t : 20; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 2 Function enable bit */ + } EP2CTL_b; + } ; + + union { + __IOM uint32_t EP3CTL; /*!< (@ 0x00000024) Offset:0x24 USB Endpoint 3 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 9; /*!< [8..0] Endpoint byte count */ + uint32_t : 20; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 3 Function enable bit */ + } EP3CTL_b; + } ; + + union { + __IOM uint32_t EP4CTL; /*!< (@ 0x00000028) Offset:0x28 USB Endpoint 4 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 9; /*!< [8..0] Endpoint byte count */ + uint32_t : 20; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 4 Function enable bit */ + } EP4CTL_b; + } ; + + union { + __IOM uint32_t EP5CTL; /*!< (@ 0x0000002C) Offset:0x2C USB Endpoint 5 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 9; /*!< [8..0] Endpoint byte count */ + uint32_t : 20; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 5 Function enable bit */ + } EP5CTL_b; + } ; + + union { + __IOM uint32_t EP6CTL; /*!< (@ 0x00000030) Offset:0x30 USB Endpoint 6 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 9; /*!< [8..0] Endpoint byte count */ + uint32_t : 20; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 6 Function enable bit */ + } EP6CTL_b; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t EPTOGGLE; /*!< (@ 0x0000003C) Offset:0x3C USB Endpoint Data Toggle Register */ + + struct { + __IOM uint32_t ENDP1_DATA01 : 1; /*!< [0..0] Endpoint 1 data toggle bit */ + __IOM uint32_t ENDP2_DATA01 : 1; /*!< [1..1] Endpoint 2 data toggle bit */ + __IOM uint32_t ENDP3_DATA01 : 1; /*!< [2..2] Endpoint 3 data toggle bit */ + __IOM uint32_t ENDP4_DATA01 : 1; /*!< [3..3] Endpoint 4 data toggle bit */ + __IOM uint32_t ENDP5_DATA01 : 1; /*!< [4..4] Endpoint 5 data toggle bit */ + __IOM uint32_t ENDP6_DATA01 : 1; /*!< [5..5] Endpoint 6 data toggle bit */ + uint32_t : 26; + } EPTOGGLE_b; + } ; + __IM uint32_t RESERVED1[2]; + + union { + __IOM uint32_t EP1BUFOS; /*!< (@ 0x00000048) Offset:0x48 USB Endpoint 1 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP1BUFOS_b; + } ; + + union { + __IOM uint32_t EP2BUFOS; /*!< (@ 0x0000004C) Offset:0x4C USB Endpoint 2 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP2BUFOS_b; + } ; + + union { + __IOM uint32_t EP3BUFOS; /*!< (@ 0x00000050) Offset:0x50 USB Endpoint 3 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP3BUFOS_b; + } ; + + union { + __IOM uint32_t EP4BUFOS; /*!< (@ 0x00000054) Offset:0x54 USB Endpoint 4 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP4BUFOS_b; + } ; + + union { + __IOM uint32_t EP5BUFOS; /*!< (@ 0x00000058) Offset:0x58 USB Endpoint 5 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP5BUFOS_b; + } ; + + union { + __IOM uint32_t EP6BUFOS; /*!< (@ 0x0000005C) Offset:0x5C USB Endpoint 6 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP6BUFOS_b; + } ; + + union { + __IM uint32_t FRMNO; /*!< (@ 0x00000060) Offset:0x60 USB Frame Number Register */ + + struct { + __IOM uint32_t FRAME_NO : 11; /*!< [10..0] The 11-bit frame number of the SOF packet */ + uint32_t : 21; + } FRMNO_b; + } ; + + union { + __IOM uint32_t PHYPRM; /*!< (@ 0x00000064) Offset:0x64 USB PHY Parameter Register */ + + struct { + uint32_t : 26; + __IOM uint32_t PHY_PARAM : 6; /*!< [31..26] The USB PHY parameter value */ + } PHYPRM_b; + } ; + __IM uint32_t RESERVED2[38]; + __IOM uint32_t SRAM; /*!< (@ 0x00000100) Offset:0x100 USB SRAM starting address */ +} SN_USB_Type; /*!< Size = 260 (0x104) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_LCD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 4 x 32 LCD Driver (SN_LCD) + */ + +typedef struct { /*!< (@ 0x40034000) SN_LCD Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 LCD Control register */ + + struct { + __IOM uint32_t LCDENB : 1; /*!< [0..0] LCD driver enable bit */ + __IOM uint32_t ITB : 1; /*!< [1..1] Internal testing bit */ + __IOM uint32_t LCDTYPE : 2; /*!< [3..2] LCD type control bit */ + __IOM uint32_t BIAS : 1; /*!< [4..4] LCD bias selection */ + __IOM uint32_t SEGSEL1 : 1; /*!< [5..5] SEG12~23 enable bit */ + __IOM uint32_t SEGSEL2 : 1; /*!< [6..6] SEG24~31 enable bit */ + uint32_t : 1; + __IOM uint32_t DUTY : 2; /*!< [9..8] Duty selection */ + __IOM uint32_t LCDCLK : 1; /*!< [10..10] LCD clock source selection */ + __IOM uint32_t LCDRATE : 1; /*!< [11..11] LCD clock rate */ + uint32_t : 16; + __IOM uint32_t DRIVEP : 2; /*!< [29..28] LCD panel driving ability */ + uint32_t : 2; + } CTRL_b; + } ; + + union { + __IOM uint32_t CTRL1; /*!< (@ 0x00000004) Offset:0x04 LCD Control register 1 */ + + struct { + __IOM uint32_t LCDBNK : 1; /*!< [0..0] LCD blank control bit */ + __IOM uint32_t REF : 2; /*!< [2..1] Resistance selection for LCD Bias Voltage-division */ + uint32_t : 25; + __IOM uint32_t ITB : 1; /*!< [28..28] Internal testing bit */ + uint32_t : 3; + } CTRL1_b; + } ; + + union { + __IOM uint32_t CCTRL1; /*!< (@ 0x00000008) Offset:0x08 LCD C-Type Control register 1 */ + + struct { + __IOM uint32_t VCP : 4; /*!< [3..0] C-Type VLCD output voltage */ + uint32_t : 22; + __IOM uint32_t IT2 : 2; /*!< [27..26] Internal testing bits */ + __IOM uint32_t IT1 : 2; /*!< [29..28] Internal testing bits */ + uint32_t : 2; + } CCTRL1_b; + } ; + + union { + __IOM uint32_t CCTRL2; /*!< (@ 0x0000000C) Offset:0x0C LCD C-Type Control register 2 */ + + struct { + uint32_t : 1; + __IOM uint32_t IT : 3; /*!< [3..1] Internal testing bits */ + uint32_t : 28; + } CCTRL2_b; + } ; + + union { + __IOM uint32_t FCC; /*!< (@ 0x00000010) Offset:0x10 LCD Frame Counter Control register */ + + struct { + __IOM uint32_t FCENB : 1; /*!< [0..0] LCD frame counter enable bit */ + __IOM uint32_t FCT : 6; /*!< [6..1] LCD frame counter threshold value */ + __IOM uint32_t FCIE : 1; /*!< [7..7] LCD frame interrupt enable bit */ + uint32_t : 24; + } FCC_b; + } ; + + union { + __IOM uint32_t RIS; /*!< (@ 0x00000014) Offset:0x14 LCD Raw Interrupt Status register */ + + struct { + __IOM uint32_t FCIF : 1; /*!< [0..0] LCD frame interrupt flag */ + uint32_t : 31; + } RIS_b; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t SEGM0; /*!< (@ 0x00000020) Offset:0x20 LCD SEG Memory register 0 */ + + struct { + __IOM uint32_t SEG0 : 4; /*!< [3..0] SEG0 data for COM0~COM3 */ + __IOM uint32_t SEG1 : 4; /*!< [7..4] SEG1 data for COM0~COM3 */ + __IOM uint32_t SEG2 : 4; /*!< [11..8] SEG2 data for COM0~COM3 */ + __IOM uint32_t SEG3 : 4; /*!< [15..12] SEG3 data for COM0~COM3 */ + __IOM uint32_t SEG4 : 4; /*!< [19..16] SEG4 data for COM0~COM3 */ + __IOM uint32_t SEG5 : 4; /*!< [23..20] SEG5 data for COM0~COM3 */ + __IOM uint32_t SEG6 : 4; /*!< [27..24] SEG6 data for COM0~COM3 */ + __IOM uint32_t SEG7 : 4; /*!< [31..28] SEG7 data for COM0~COM3 */ + } SEGM0_b; + } ; + + union { + __IOM uint32_t SEGM1; /*!< (@ 0x00000024) Offset:0x24 LCD SEG Memory register 1 */ + + struct { + __IOM uint32_t SEG8 : 4; /*!< [3..0] SEG8 data for COM0~COM3 */ + __IOM uint32_t SEG9 : 4; /*!< [7..4] SEG9 data for COM0~COM3 */ + __IOM uint32_t SEG10 : 4; /*!< [11..8] SEG10 data for COM0~COM3 */ + __IOM uint32_t SEG11 : 4; /*!< [15..12] SEG11 data for COM0~COM3 */ + __IOM uint32_t SEG12 : 4; /*!< [19..16] SEG12 data for COM0~COM3 */ + __IOM uint32_t SEG13 : 4; /*!< [23..20] SEG13 data for COM0~COM3 */ + __IOM uint32_t SEG14 : 4; /*!< [27..24] SEG14 data for COM0~COM3 */ + __IOM uint32_t SEG15 : 4; /*!< [31..28] SEG15 data for COM0~COM3 */ + } SEGM1_b; + } ; + + union { + __IOM uint32_t SEGM2; /*!< (@ 0x00000028) Offset:0x28 LCD SEG Memory register 2 */ + + struct { + __IOM uint32_t SEG16 : 4; /*!< [3..0] SEG16 data for COM0~COM3 */ + __IOM uint32_t SEG17 : 4; /*!< [7..4] SEG17 data for COM0~COM3 */ + __IOM uint32_t SEG18 : 4; /*!< [11..8] SEG18 data for COM0~COM3 */ + __IOM uint32_t SEG19 : 4; /*!< [15..12] SEG19 data for COM0~COM3 */ + __IOM uint32_t SEG20 : 4; /*!< [19..16] SEG20 data for COM0~COM3 */ + __IOM uint32_t SEG21 : 4; /*!< [23..20] SEG21 data for COM0~COM3 */ + __IOM uint32_t SEG22 : 4; /*!< [27..24] SEG22 data for COM0~COM3 */ + __IOM uint32_t SEG23 : 4; /*!< [31..28] SEG23 data for COM0~COM3 */ + } SEGM2_b; + } ; + + union { + __IOM uint32_t SEGM3; /*!< (@ 0x0000002C) Offset:0x2C LCD SEG Memory register 3 */ + + struct { + __IOM uint32_t SEG24 : 4; /*!< [3..0] SEG24 data for COM0~COM3 */ + __IOM uint32_t SEG25 : 4; /*!< [7..4] SEG25 data for COM0~COM3 */ + __IOM uint32_t SEG26 : 4; /*!< [11..8] SEG26 data for COM0~COM3 */ + __IOM uint32_t SEG27 : 4; /*!< [15..12] SEG27 data for COM0~COM3 */ + __IOM uint32_t SEG28 : 4; /*!< [19..16] SEG28 data for COM0~COM3 */ + __IOM uint32_t SEG29 : 4; /*!< [23..20] SEG29 data for COM0~COM3 */ + __IOM uint32_t SEG30 : 4; /*!< [27..24] SEG30 data for COM0~COM3 */ + __IOM uint32_t SEG31 : 4; /*!< [31..28] SEG31 data for COM0~COM3 */ + } SEGM3_b; + } ; +} SN_LCD_Type; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_UC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UC Registers (SN_UC) + */ + +typedef struct { /*!< (@ 0x1FFF2C08) SN_UC Structure */ + __IM uint32_t L4BYTE; /*!< (@ 0x00000000) Offset:0x00 UC Low 4 Byte Register */ + __IM uint32_t H4BYTE; /*!< (@ 0x00000004) Offset:0x04 UC High 4 Byte Register */ +} SN_UC_Type; /*!< Size = 8 (0x8) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define SN_SYS0_BASE 0x40060000UL +#define SN_SYS1_BASE 0x4005E000UL +#define SN_GPIO0_BASE 0x40044000UL +#define SN_GPIO1_BASE 0x40046000UL +#define SN_GPIO3_BASE 0x4004A000UL +#define SN_GPIO2_BASE 0x40048000UL +#define SN_ADC_BASE 0x40026000UL +#define SN_WDT_BASE 0x40010000UL +#define SN_RTC_BASE 0x40012000UL +#define SN_CT16B0_BASE 0x40000000UL +#define SN_CT16B1_BASE 0x40002000UL +#define SN_CT16B2_BASE 0x40004000UL +#define SN_CT32B0_BASE 0x40006000UL +#define SN_CT32B1_BASE 0x40008000UL +#define SN_CT32B2_BASE 0x4000A000UL +#define SN_PMU_BASE 0x40032000UL +#define SN_SSP0_BASE 0x4001C000UL +#define SN_SSP1_BASE 0x40058000UL +#define SN_I2C0_BASE 0x40018000UL +#define SN_I2C1_BASE 0x4005A000UL +#define SN_USART0_BASE 0x40016000UL +#define SN_USART1_BASE 0x40056000UL +#define SN_I2S_BASE 0x4001A000UL +#define SN_FLASH_BASE 0x40062000UL +#define SN_PFPA_BASE 0x40042000UL +#define SN_USB_BASE 0x4005C000UL +#define SN_LCD_BASE 0x40034000UL +#define SN_UC_BASE 0x1FFF2C08UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define SN_SYS0 ((SN_SYS0_Type*) SN_SYS0_BASE) +#define SN_SYS1 ((SN_SYS1_Type*) SN_SYS1_BASE) +#define SN_GPIO0 ((SN_GPIO0_Type*) SN_GPIO0_BASE) +#define SN_GPIO1 ((SN_GPIO0_Type*) SN_GPIO1_BASE) +#define SN_GPIO3 ((SN_GPIO0_Type*) SN_GPIO3_BASE) +#define SN_GPIO2 ((SN_GPIO2_Type*) SN_GPIO2_BASE) +#define SN_ADC ((SN_ADC_Type*) SN_ADC_BASE) +#define SN_WDT ((SN_WDT_Type*) SN_WDT_BASE) +#define SN_RTC ((SN_RTC_Type*) SN_RTC_BASE) +#define SN_CT16B0 ((SN_CT16B0_Type*) SN_CT16B0_BASE) +#define SN_CT16B1 ((SN_CT16B0_Type*) SN_CT16B1_BASE) +#define SN_CT16B2 ((SN_CT16B0_Type*) SN_CT16B2_BASE) +#define SN_CT32B0 ((SN_CT32B0_Type*) SN_CT32B0_BASE) +#define SN_CT32B1 ((SN_CT32B0_Type*) SN_CT32B1_BASE) +#define SN_CT32B2 ((SN_CT32B0_Type*) SN_CT32B2_BASE) +#define SN_PMU ((SN_PMU_Type*) SN_PMU_BASE) +#define SN_SSP0 ((SN_SSP0_Type*) SN_SSP0_BASE) +#define SN_SSP1 ((SN_SSP0_Type*) SN_SSP1_BASE) +#define SN_I2C0 ((SN_I2C0_Type*) SN_I2C0_BASE) +#define SN_I2C1 ((SN_I2C0_Type*) SN_I2C1_BASE) +#define SN_USART0 ((SN_USART0_Type*) SN_USART0_BASE) +#define SN_USART1 ((SN_USART0_Type*) SN_USART1_BASE) +#define SN_I2S ((SN_I2S_Type*) SN_I2S_BASE) +#define SN_FLASH ((SN_FLASH_Type*) SN_FLASH_BASE) +#define SN_PFPA ((SN_PFPA_Type*) SN_PFPA_BASE) +#define SN_USB ((SN_USB_Type*) SN_USB_BASE) +#define SN_LCD ((SN_LCD_Type*) SN_LCD_BASE) +#define SN_UC ((SN_UC_Type*) SN_UC_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* SN32F240_H */ + + +/** @} */ /* End of group SN32F240 */ + +/** @} */ /* End of group SONiX Technology Co., Ltd. */ diff --git a/os/common/ext/SONiX/SN32F2xx/SN32F240B.h b/os/common/ext/SONiX/SN32F2xx/SN32F240B.h new file mode 100644 index 00000000..21c7bbe7 --- /dev/null +++ b/os/common/ext/SONiX/SN32F2xx/SN32F240B.h @@ -0,0 +1,2914 @@ +/* + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontroller, but can be equally used for other + * suitable processor architectures. This file can be freely distributed. + * Modifications to this file shall be clearly marked. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * @file SN32F240B.h + * @brief CMSIS HeaderFile + * @version 1.1 + * @date 09. January 2022 + * @note Generated by SVDConv V3.3.35 on Sunday, 09.01.2022 18:48:41 + * from File 'SN32F240B.svd', + * last modified on Tuesday, 01.09.2020 10:52:27 + */ + + + +/** @addtogroup SONiX Technology Co., Ltd. + * @{ + */ + + +/** @addtogroup SN32F240B + * @{ + */ + + +#ifndef SN32F240B_H +#define SN32F240B_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M0 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================= SN32F240B Specific Interrupt Numbers ========================================== */ + NDT_IRQn = 0, /*!< 0 NDT */ + USB_IRQn = 1, /*!< 1 USB */ + SPI0_IRQn = 6, /*!< 6 SPI0 */ + I2C0_IRQn = 10, /*!< 10 I2C0 */ + UART0_IRQn = 12, /*!< 12 UART0 */ + UART1_IRQn = 13, /*!< 13 UART1 */ + UART2_IRQn = 14, /*!< 14 UART2 */ + CT16B0_IRQn = 15, /*!< 15 CT16B0 */ + CT16B1_IRQn = 16, /*!< 16 CT16B1 */ + ADC_IRQn = 24, /*!< 24 ADC */ + WDT_IRQn = 25, /*!< 25 WDT */ + LVD_IRQn = 26, /*!< 26 LVD */ + P3_IRQn = 28, /*!< 28 P3 */ + P2_IRQn = 29, /*!< 29 P2 */ + P1_IRQn = 30, /*!< 30 P1 */ + P0_IRQn = 31 /*!< 31 P0 */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M0 Processor and Core Peripherals =========================== */ +#define __CM0_REV 0x0000U /*!< CM0 Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 0 /*!< MPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0.h" /*!< ARM Cortex-M0 processor and core peripherals */ +#include "system_SN32F2xx.h" /*!< SN32F240B System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SYS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System Control Registers (SN_SYS0) + */ + +typedef struct { /*!< (@ 0x40060000) SN_SYS0 Structure */ + + union { + __IOM uint32_t ANBCTRL; /*!< (@ 0x00000000) Offset:0x00 Analog Block Control Register */ + + struct { + __IOM uint32_t IHRCEN : 1; /*!< [0..0] IHRC enable */ + uint32_t : 31; + } ANBCTRL_b; + } ; + __IM uint32_t RESERVED; + + union { + __IM uint32_t CSST; /*!< (@ 0x00000008) Offset:0x08 Clock Source Status Register */ + + struct { + __IM uint32_t IHRCRDY : 1; /*!< [0..0] IHRC ready flag */ + uint32_t : 31; + } CSST_b; + } ; + + union { + __IOM uint32_t CLKCFG; /*!< (@ 0x0000000C) Offset:0x0C System Clock Configuration Register */ + + struct { + __IOM uint32_t SYSCLKSEL : 1; /*!< [0..0] System clock source selection */ + uint32_t : 3; + __IM uint32_t SYSCLKST : 1; /*!< [4..4] System clock switch status */ + uint32_t : 27; + } CLKCFG_b; + } ; + + union { + __IOM uint32_t AHBCP; /*!< (@ 0x00000010) Offset:0x10 AHB Clock Prescale Register */ + + struct { + __IOM uint32_t AHBPRE : 3; /*!< [2..0] AHB clock source prescaler */ + uint32_t : 29; + } AHBCP_b; + } ; + + union { + __IOM uint32_t RSTST; /*!< (@ 0x00000014) Offset:0x14 System Reset Status Register */ + + struct { + __IOM uint32_t SWRSTF : 1; /*!< [0..0] Software reset flag */ + __IOM uint32_t WDTRSTF : 1; /*!< [1..1] WDT reset flag */ + __IOM uint32_t LVDRSTF : 1; /*!< [2..2] LVD reset flag */ + __IOM uint32_t EXTRSTF : 1; /*!< [3..3] External reset flag */ + __IOM uint32_t PORRSTF : 1; /*!< [4..4] POR reset flag */ + uint32_t : 27; + } RSTST_b; + } ; + + union { + __IOM uint32_t LVDCTRL; /*!< (@ 0x00000018) Offset:0x18 LVD Control Register */ + + struct { + __IOM uint32_t LVDRSTLVL : 3; /*!< [2..0] LVD reset level */ + uint32_t : 1; + __IOM uint32_t LVDINTLVL : 3; /*!< [6..4] LVD interrupt level */ + uint32_t : 7; + __IOM uint32_t LVDRSTEN : 1; /*!< [14..14] LVD Reset enable */ + __IOM uint32_t LVDEN : 1; /*!< [15..15] LVD enable */ + uint32_t : 16; + } LVDCTRL_b; + } ; + + union { + __IOM uint32_t EXRSTCTRL; /*!< (@ 0x0000001C) Offset:0x1C External Reset Pin Control Register */ + + struct { + __IOM uint32_t RESETDIS : 1; /*!< [0..0] External reset pin disable */ + uint32_t : 31; + } EXRSTCTRL_b; + } ; + + union { + __IOM uint32_t SWDCTRL; /*!< (@ 0x00000020) Offset:0x20 SWD Pin Control Register */ + + struct { + __IOM uint32_t SWDDIS : 1; /*!< [0..0] SWD pin disable */ + uint32_t : 31; + } SWDCTRL_b; + } ; + + union { + __IOM uint32_t IVTM; /*!< (@ 0x00000024) Offset:0x24 Interrupt Vector Table Mapping register */ + + struct { + __IOM uint32_t IVTM : 2; /*!< [1..0] Interrupt table mapping selection */ + uint32_t : 14; + __OM uint32_t IVTMKEY : 16; /*!< [31..16] IVTM register key */ + } IVTM_b; + } ; + + union { + __IOM uint32_t NDTCTRL; /*!< (@ 0x00000028) Offset:0x28 Noise Detect Control Register */ + + struct { + uint32_t : 1; + __IOM uint32_t NDT5V_IE : 1; /*!< [1..1] NDT for VDD 5V interrupt enable bit */ + uint32_t : 30; + } NDTCTRL_b; + } ; + + union { + __IOM uint32_t NDTSTS; /*!< (@ 0x0000002C) Offset:0x2C Noise Detect Status Register */ + + struct { + uint32_t : 1; + __IOM uint32_t NDT5V_DET : 1; /*!< [1..1] Power noise status of NDT5V */ + uint32_t : 30; + } NDTSTS_b; + } ; + + union { + __IOM uint32_t ANTIEFT; /*!< (@ 0x00000030) Offset:0x30 Anti-EFT Ability Control Register */ + + struct { + __IOM uint32_t AEFT : 3; /*!< [2..0] Anti-EFT ability */ + uint32_t : 29; + } ANTIEFT_b; + } ; +} SN_SYS0_Type; /*!< Size = 52 (0x34) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SYS1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System Control Registers (SN_SYS1) + */ + +typedef struct { /*!< (@ 0x4005E000) SN_SYS1 Structure */ + + union { + __IOM uint32_t AHBCLKEN; /*!< (@ 0x00000000) Offset:0x00 AHB Clock Enable Register */ + + struct { + __IOM uint32_t P0CLKEN : 1; /*!< [0..0] Enable AHB clock for P0 */ + __IOM uint32_t P1CLKEN : 1; /*!< [1..1] Enable AHB clock for P1 */ + __IOM uint32_t P2CLKEN : 1; /*!< [2..2] Enable AHB clock for P2 */ + __IOM uint32_t P3CLKEN : 1; /*!< [3..3] Enable AHB clock for P3 */ + __IOM uint32_t USBCLKEN : 1; /*!< [4..4] Enable AHB clock for USB */ + uint32_t : 1; + __IOM uint32_t CT16B0CLKEN : 1; /*!< [6..6] Enable AHB clock for CT16B0 */ + __IOM uint32_t CT16B1CLKEN : 1; /*!< [7..7] Enable AHB clock for CT16B1 */ + uint32_t : 3; + __IOM uint32_t ADCCLKEN : 1; /*!< [11..11] Enable AHB clock for ADC */ + __IOM uint32_t SPI0CLKEN : 1; /*!< [12..12] Enable AHB clock for SPI0 */ + uint32_t : 3; + __IOM uint32_t UART0CLKEN : 1; /*!< [16..16] Enable AHB clock for UART0 */ + __IOM uint32_t UART1CLKEN : 1; /*!< [17..17] Enable AHB clock for UART1 */ + __IOM uint32_t UART2CLKEN : 1; /*!< [18..18] Enable AHB clock for UART2 */ + uint32_t : 2; + __IOM uint32_t I2C0CLKEN : 1; /*!< [21..21] Enable AHB clock for I2C0 */ + uint32_t : 2; + __IOM uint32_t WDTCLKEN : 1; /*!< [24..24] Enable AHB clock for WDT */ + uint32_t : 3; + __IOM uint32_t CLKOUTSEL : 3; /*!< [30..28] Clock output source selection */ + uint32_t : 1; + } AHBCLKEN_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t APBCP1; /*!< (@ 0x00000008) Offset:0x08 APB Clock Prescale Register 1 */ + + struct { + uint32_t : 20; + __IOM uint32_t WDTPRE : 3; /*!< [22..20] WDT APB clock source prescaler */ + uint32_t : 5; + __IOM uint32_t CLKOUTPRE : 3; /*!< [30..28] CLKOUT APB clock source prescaler */ + uint32_t : 1; + } APBCP1_b; + } ; +} SN_SYS1_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_PMU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power Management Unit (SN_PMU) + */ + +typedef struct { /*!< (@ 0x40032000) SN_PMU Structure */ + __IM uint32_t RESERVED[16]; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000040) Offset:0x40 PMU Control Register */ + + struct { + __IOM uint32_t MODE : 3; /*!< [2..0] Low Power mode selection */ + uint32_t : 29; + } CTRL_b; + } ; +} SN_PMU_Type; /*!< Size = 68 (0x44) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_PFPA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Peripheral Function Pin Assignment (SN_PFPA) + */ + +typedef struct { /*!< (@ 0x40042000) SN_PFPA Structure */ + + union { + __IOM uint32_t CT16B1; /*!< (@ 0x00000000) Offset:0x00 PFPA for CT16B1 Register */ + + struct { + __IOM uint32_t PWM00 : 1; /*!< [0..0] CT16B1_PWM00 assigned pin */ + __IOM uint32_t PWM01 : 1; /*!< [1..1] CT16B1_PWM01 assigned pin */ + __IOM uint32_t PWM02 : 1; /*!< [2..2] CT16B1_PWM02 assigned pin */ + __IOM uint32_t PWM03 : 1; /*!< [3..3] CT16B1_PWM03 assigned pin */ + __IOM uint32_t PWM04 : 1; /*!< [4..4] CT16B1_PWM04 assigned pin */ + __IOM uint32_t PWM05 : 1; /*!< [5..5] CT16B1_PWM05 assigned pin */ + __IOM uint32_t PWM06 : 1; /*!< [6..6] CT16B1_PWM06 assigned pin */ + __IOM uint32_t PWM07 : 1; /*!< [7..7] CT16B1_PWM07 assigned pin */ + __IOM uint32_t PWM08 : 1; /*!< [8..8] CT16B1_PWM08 assigned pin */ + __IOM uint32_t PWM09 : 1; /*!< [9..9] CT16B1_PWM09 assigned pin */ + __IOM uint32_t PWM10 : 1; /*!< [10..10] CT16B1_PWM10 assigned pin */ + __IOM uint32_t PWM11 : 1; /*!< [11..11] CT16B1_PWM11 assigned pin */ + __IOM uint32_t PWM12 : 1; /*!< [12..12] CT16B1_PWM12 assigned pin */ + __IOM uint32_t PWM13 : 1; /*!< [13..13] CT16B1_PWM13 assigned pin */ + __IOM uint32_t PWM14 : 1; /*!< [14..14] CT16B1_PWM14 assigned pin */ + __IOM uint32_t PWM15 : 1; /*!< [15..15] CT16B1_PWM15 assigned pin */ + __IOM uint32_t PWM16 : 1; /*!< [16..16] CT16B1_PWM16 assigned pin */ + __IOM uint32_t PWM17 : 1; /*!< [17..17] CT16B1_PWM17 assigned pin */ + __IOM uint32_t PWM18 : 1; /*!< [18..18] CT16B1_PWM18 assigned pin */ + __IOM uint32_t PWM19 : 1; /*!< [19..19] CT16B1_PWM19 assigned pin */ + __IOM uint32_t PWM20 : 1; /*!< [20..20] CT16B1_PWM20 assigned pin */ + __IOM uint32_t PWM21 : 1; /*!< [21..21] CT16B1_PWM21 assigned pin */ + __IOM uint32_t PWM22 : 1; /*!< [22..22] CT16B1_PWM22 assigned pin */ + __IOM uint32_t PWM23 : 1; /*!< [23..23] CT16B1_PWM23 assigned pin */ + uint32_t : 8; + } CT16B1_b; + } ; +} SN_PFPA_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose I/O (SN_GPIO0) + */ + +typedef struct { /*!< (@ 0x40044000) SN_GPIO0 Structure */ + + union { + __IOM uint32_t DATA; /*!< (@ 0x00000000) Offset:0x00 GPIO Port n Data Register */ + + struct { + __IOM uint32_t DATA0 : 1; /*!< [0..0] Data of Pn.0 */ + __IOM uint32_t DATA1 : 1; /*!< [1..1] Data of Pn.1 */ + __IOM uint32_t DATA2 : 1; /*!< [2..2] Data of Pn.2 */ + __IOM uint32_t DATA3 : 1; /*!< [3..3] Data of Pn.3 */ + __IOM uint32_t DATA4 : 1; /*!< [4..4] Data of Pn.4 */ + __IOM uint32_t DATA5 : 1; /*!< [5..5] Data of Pn.5 */ + __IOM uint32_t DATA6 : 1; /*!< [6..6] Data of Pn.6 */ + __IOM uint32_t DATA7 : 1; /*!< [7..7] Data of Pn.7 */ + __IOM uint32_t DATA8 : 1; /*!< [8..8] Data of Pn.8 */ + __IOM uint32_t DATA9 : 1; /*!< [9..9] Data of Pn.9 */ + __IOM uint32_t DATA10 : 1; /*!< [10..10] Data of Pn.10 */ + __IOM uint32_t DATA11 : 1; /*!< [11..11] Data of Pn.11 */ + __IOM uint32_t DATA12 : 1; /*!< [12..12] Data of Pn.12 */ + __IOM uint32_t DATA13 : 1; /*!< [13..13] Data of Pn.13 */ + __IOM uint32_t DATA14 : 1; /*!< [14..14] Data of Pn.14 */ + __IOM uint32_t DATA15 : 1; /*!< [15..15] Data of Pn.15 */ + uint32_t : 16; + } DATA_b; + } ; + + union { + __IOM uint32_t MODE; /*!< (@ 0x00000004) Offset:0x04 GPIO Port n Mode Register */ + + struct { + __IOM uint32_t MODE0 : 1; /*!< [0..0] Mode of Pn.0 */ + __IOM uint32_t MODE1 : 1; /*!< [1..1] Mode of Pn.1 */ + __IOM uint32_t MODE2 : 1; /*!< [2..2] Mode of Pn.2 */ + __IOM uint32_t MODE3 : 1; /*!< [3..3] Mode of Pn.3 */ + __IOM uint32_t MODE4 : 1; /*!< [4..4] Mode of Pn.4 */ + __IOM uint32_t MODE5 : 1; /*!< [5..5] Mode of Pn.5 */ + __IOM uint32_t MODE6 : 1; /*!< [6..6] Mode of Pn.6 */ + __IOM uint32_t MODE7 : 1; /*!< [7..7] Mode of Pn.7 */ + __IOM uint32_t MODE8 : 1; /*!< [8..8] Mode of Pn.8 */ + __IOM uint32_t MODE9 : 1; /*!< [9..9] Mode of Pn.9 */ + __IOM uint32_t MODE10 : 1; /*!< [10..10] Mode of Pn.10 */ + __IOM uint32_t MODE11 : 1; /*!< [11..11] Mode of Pn.11 */ + __IOM uint32_t MODE12 : 1; /*!< [12..12] Mode of Pn.12 */ + __IOM uint32_t MODE13 : 1; /*!< [13..13] Mode of Pn.13 */ + __IOM uint32_t MODE14 : 1; /*!< [14..14] Mode of Pn.14 */ + __IOM uint32_t MODE15 : 1; /*!< [15..15] Mode of Pn.15 */ + uint32_t : 16; + } MODE_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000008) Offset:0x08 GPIO Port n Configuration Register */ + + struct { + __IOM uint32_t CFG0 : 2; /*!< [1..0] Configuration of Pn.0 */ + __IOM uint32_t CFG1 : 2; /*!< [3..2] Configuration of Pn.1 */ + __IOM uint32_t CFG2 : 2; /*!< [5..4] Configuration of Pn.2 */ + __IOM uint32_t CFG3 : 2; /*!< [7..6] Configuration of Pn.3 */ + __IOM uint32_t CFG4 : 2; /*!< [9..8] Configuration of Pn.4 */ + __IOM uint32_t CFG5 : 2; /*!< [11..10] Configuration of Pn.5 */ + __IOM uint32_t CFG6 : 2; /*!< [13..12] Configuration of Pn.6 */ + __IOM uint32_t CFG7 : 2; /*!< [15..14] Configuration of Pn.7 */ + __IOM uint32_t CFG8 : 2; /*!< [17..16] Configuration of Pn.8 */ + __IOM uint32_t CFG9 : 2; /*!< [19..18] Configuration of Pn.9 */ + __IOM uint32_t CFG10 : 2; /*!< [21..20] Configuration of Pn.10 */ + __IOM uint32_t CFG11 : 2; /*!< [23..22] Configuration of Pn.11 */ + __IOM uint32_t CFG12 : 2; /*!< [25..24] Configuration of Pn.12 */ + __IOM uint32_t CFG13 : 2; /*!< [27..26] Configuration of Pn.13 */ + __IOM uint32_t CFG14 : 2; /*!< [29..28] Configuration of Pn.14 */ + __IOM uint32_t CFG15 : 2; /*!< [31..30] Configuration of Pn.15 */ + } CFG_b; + } ; + + union { + __IOM uint32_t IS; /*!< (@ 0x0000000C) Offset:0x0C GPIO Port n Interrupt Sense Register */ + + struct { + __IOM uint32_t IS0 : 1; /*!< [0..0] Interrupt on Pn.0 is event or edge sensitive */ + __IOM uint32_t IS1 : 1; /*!< [1..1] Interrupt on Pn.1 is event or edge sensitive */ + __IOM uint32_t IS2 : 1; /*!< [2..2] Interrupt on Pn.2 is event or edge sensitive */ + __IOM uint32_t IS3 : 1; /*!< [3..3] Interrupt on Pn.3 is event or edge sensitive */ + __IOM uint32_t IS4 : 1; /*!< [4..4] Interrupt on Pn.4 is event or edge sensitive */ + __IOM uint32_t IS5 : 1; /*!< [5..5] Interrupt on Pn.5 is event or edge sensitive */ + __IOM uint32_t IS6 : 1; /*!< [6..6] Interrupt on Pn.6 is event or edge sensitive */ + __IOM uint32_t IS7 : 1; /*!< [7..7] Interrupt on Pn.7 is event or edge sensitive */ + __IOM uint32_t IS8 : 1; /*!< [8..8] Interrupt on Pn.8 is event or edge sensitive */ + __IOM uint32_t IS9 : 1; /*!< [9..9] Interrupt on Pn.9 is event or edge sensitive */ + __IOM uint32_t IS10 : 1; /*!< [10..10] Interrupt on Pn.10 is event or edge sensitive */ + __IOM uint32_t IS11 : 1; /*!< [11..11] Interrupt on Pn.11 is event or edge sensitive */ + __IOM uint32_t IS12 : 1; /*!< [12..12] Interrupt on Pn.12 is event or edge sensitive */ + __IOM uint32_t IS13 : 1; /*!< [13..13] Interrupt on Pn.13 is event or edge sensitive */ + __IOM uint32_t IS14 : 1; /*!< [14..14] Interrupt on Pn.14 is event or edge sensitive */ + __IOM uint32_t IS15 : 1; /*!< [15..15] Interrupt on Pn.15 is event or edge sensitive */ + uint32_t : 16; + } IS_b; + } ; + + union { + __IOM uint32_t IBS; /*!< (@ 0x00000010) Offset:0x10 GPIO Port n Interrupt Both-edge Sense + Register */ + + struct { + __IOM uint32_t IBS0 : 1; /*!< [0..0] Interrupt on Pn.0 is triggered ob both edges */ + __IOM uint32_t IBS1 : 1; /*!< [1..1] Interrupt on Pn.1 is triggered ob both edges */ + __IOM uint32_t IBS2 : 1; /*!< [2..2] Interrupt on Pn.2 is triggered ob both edges */ + __IOM uint32_t IBS3 : 1; /*!< [3..3] Interrupt on Pn.3 is triggered ob both edges */ + __IOM uint32_t IBS4 : 1; /*!< [4..4] Interrupt on Pn.4 is triggered ob both edges */ + __IOM uint32_t IBS5 : 1; /*!< [5..5] Interrupt on Pn.5 is triggered ob both edges */ + __IOM uint32_t IBS6 : 1; /*!< [6..6] Interrupt on Pn.6 is triggered ob both edges */ + __IOM uint32_t IBS7 : 1; /*!< [7..7] Interrupt on Pn.7 is triggered ob both edges */ + __IOM uint32_t IBS8 : 1; /*!< [8..8] Interrupt on Pn.8 is triggered ob both edges */ + __IOM uint32_t IBS9 : 1; /*!< [9..9] Interrupt on Pn.9 is triggered ob both edges */ + __IOM uint32_t IBS10 : 1; /*!< [10..10] Interrupt on Pn.10 is triggered ob both edges */ + __IOM uint32_t IBS11 : 1; /*!< [11..11] Interrupt on Pn.11 is triggered ob both edges */ + __IOM uint32_t IBS12 : 1; /*!< [12..12] Interrupt on Pn.12 is triggered ob both edges */ + __IOM uint32_t IBS13 : 1; /*!< [13..13] Interrupt on Pn.13 is triggered ob both edges */ + __IOM uint32_t IBS14 : 1; /*!< [14..14] Interrupt on Pn.14 is triggered ob both edges */ + __IOM uint32_t IBS15 : 1; /*!< [15..15] Interrupt on Pn.15 is triggered ob both edges */ + uint32_t : 16; + } IBS_b; + } ; + + union { + __IOM uint32_t IEV; /*!< (@ 0x00000014) Offset:0x14 GPIO Port n Interrupt Event Register */ + + struct { + __IOM uint32_t IEV0 : 1; /*!< [0..0] Interrupt trigged evnet on Pn.0 */ + __IOM uint32_t IEV1 : 1; /*!< [1..1] Interrupt trigged evnet on Pn.1 */ + __IOM uint32_t IEV2 : 1; /*!< [2..2] Interrupt trigged evnet on Pn.2 */ + __IOM uint32_t IEV3 : 1; /*!< [3..3] Interrupt trigged evnet on Pn.3 */ + __IOM uint32_t IEV4 : 1; /*!< [4..4] Interrupt trigged evnet on Pn.4 */ + __IOM uint32_t IEV5 : 1; /*!< [5..5] Interrupt trigged evnet on Pn.5 */ + __IOM uint32_t IEV6 : 1; /*!< [6..6] Interrupt trigged evnet on Pn.6 */ + __IOM uint32_t IEV7 : 1; /*!< [7..7] Interrupt trigged evnet on Pn.7 */ + __IOM uint32_t IEV8 : 1; /*!< [8..8] Interrupt trigged evnet on Pn.8 */ + __IOM uint32_t IEV9 : 1; /*!< [9..9] Interrupt trigged evnet on Pn.9 */ + __IOM uint32_t IEV10 : 1; /*!< [10..10] Interrupt trigged evnet on Pn.10 */ + __IOM uint32_t IEV11 : 1; /*!< [11..11] Interrupt trigged evnet on Pn.11 */ + __IOM uint32_t IEV12 : 1; /*!< [12..12] Interrupt trigged evnet on Pn.12 */ + __IOM uint32_t IEV13 : 1; /*!< [13..13] Interrupt trigged evnet on Pn.13 */ + __IOM uint32_t IEV14 : 1; /*!< [14..14] Interrupt trigged evnet on Pn.14 */ + __IOM uint32_t IEV15 : 1; /*!< [15..15] Interrupt trigged evnet on Pn.15 */ + uint32_t : 16; + } IEV_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000018) Offset:0x18 GPIO Port n Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] Interrupt on Pn.0 enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] Interrupt on Pn.1 enable */ + __IOM uint32_t IE2 : 1; /*!< [2..2] Interrupt on Pn.2 enable */ + __IOM uint32_t IE3 : 1; /*!< [3..3] Interrupt on Pn.3 enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] Interrupt on Pn.4 enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] Interrupt on Pn.5 enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] Interrupt on Pn.6 enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] Interrupt on Pn.7 enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] Interrupt on Pn.8 enable */ + __IOM uint32_t IE9 : 1; /*!< [9..9] Interrupt on Pn.9 enable */ + __IOM uint32_t IE10 : 1; /*!< [10..10] Interrupt on Pn.10 enable */ + __IOM uint32_t IE11 : 1; /*!< [11..11] Interrupt on Pn.11 enable */ + __IOM uint32_t IE12 : 1; /*!< [12..12] Interrupt on Pn.11 enable */ + __IOM uint32_t IE13 : 1; /*!< [13..13] Interrupt on Pn.13 enable */ + __IOM uint32_t IE14 : 1; /*!< [14..14] Interrupt on Pn.14 enable */ + __IOM uint32_t IE15 : 1; /*!< [15..15] Interrupt on Pn.15 enable */ + uint32_t : 16; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x0000001C) Offset:0x1C GPIO Port n Raw Interrupt Status + Register */ + + struct { + __IM uint32_t IF0 : 1; /*!< [0..0] Pn.0 raw interrupt flag */ + __IM uint32_t IF1 : 1; /*!< [1..1] Pn.1 raw interrupt flag */ + __IM uint32_t IF2 : 1; /*!< [2..2] Pn.2 raw interrupt flag */ + __IM uint32_t IF3 : 1; /*!< [3..3] Pn.3 raw interrupt flag */ + __IM uint32_t IF4 : 1; /*!< [4..4] Pn.4 raw interrupt flag */ + __IM uint32_t IF5 : 1; /*!< [5..5] Pn.5 raw interrupt flag */ + __IM uint32_t IF6 : 1; /*!< [6..6] Pn.6 raw interrupt flag */ + __IM uint32_t IF7 : 1; /*!< [7..7] Pn.7 raw interrupt flag */ + __IM uint32_t IF8 : 1; /*!< [8..8] Pn.8 raw interrupt flag */ + __IM uint32_t IF9 : 1; /*!< [9..9] Pn.9 raw interrupt flag */ + __IM uint32_t IF10 : 1; /*!< [10..10] Pn.10 raw interrupt flag */ + __IM uint32_t IF11 : 1; /*!< [11..11] Pn.11 raw interrupt flag */ + __IM uint32_t IF12 : 1; /*!< [12..12] Pn.12 raw interrupt flag */ + __IM uint32_t IF13 : 1; /*!< [13..13] Pn.13 raw interrupt flag */ + __IM uint32_t IF14 : 1; /*!< [14..14] Pn.14 raw interrupt flag */ + __IM uint32_t IF15 : 1; /*!< [15..15] Pn.15 raw interrupt flag */ + uint32_t : 16; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000020) Offset:0x20 GPIO Port n Interrupt Clear Register */ + + struct { + __OM uint32_t IC0 : 1; /*!< [0..0] Pn.0 interrupt flag clear */ + __OM uint32_t IC1 : 1; /*!< [1..1] Pn.1 interrupt flag clear */ + __OM uint32_t IC2 : 1; /*!< [2..2] Pn.2 interrupt flag clear */ + __OM uint32_t IC3 : 1; /*!< [3..3] Pn.3 interrupt flag clear */ + __OM uint32_t IC4 : 1; /*!< [4..4] Pn.4 interrupt flag clear */ + __OM uint32_t IC5 : 1; /*!< [5..5] Pn.5 interrupt flag clear */ + __OM uint32_t IC6 : 1; /*!< [6..6] Pn.6 interrupt flag clear */ + __OM uint32_t IC7 : 1; /*!< [7..7] Pn.7 interrupt flag clear */ + __OM uint32_t IC8 : 1; /*!< [8..8] Pn.8 interrupt flag clear */ + __OM uint32_t IC9 : 1; /*!< [9..9] Pn.9 interrupt flag clear */ + __OM uint32_t IC10 : 1; /*!< [10..10] Pn.10 interrupt flag clear */ + __OM uint32_t IC11 : 1; /*!< [11..11] Pn.11 interrupt flag clear */ + __OM uint32_t IC12 : 1; /*!< [12..12] Pn.12 interrupt flag clear */ + __OM uint32_t IC13 : 1; /*!< [13..13] Pn.13 interrupt flag clear */ + __OM uint32_t IC14 : 1; /*!< [14..14] Pn.14 interrupt flag clear */ + __OM uint32_t IC15 : 1; /*!< [15..15] Pn.15 interrupt flag clear */ + uint32_t : 16; + } IC_b; + } ; + + union { + __OM uint32_t BSET; /*!< (@ 0x00000024) Offset:0x24 GPIO Port n Bits Set Operation Register */ + + struct { + __OM uint32_t BSET0 : 1; /*!< [0..0] Set Pn.0 */ + __OM uint32_t BSET1 : 1; /*!< [1..1] Set Pn.1 */ + __OM uint32_t BSET2 : 1; /*!< [2..2] Set Pn.2 */ + __OM uint32_t BSET3 : 1; /*!< [3..3] Set Pn.3 */ + __OM uint32_t BSET4 : 1; /*!< [4..4] Set Pn.4 */ + __OM uint32_t BSET5 : 1; /*!< [5..5] Set Pn.5 */ + __OM uint32_t BSET6 : 1; /*!< [6..6] Set Pn.6 */ + __OM uint32_t BSET7 : 1; /*!< [7..7] Set Pn.7 */ + __OM uint32_t BSET8 : 1; /*!< [8..8] Set Pn.8 */ + __OM uint32_t BSET9 : 1; /*!< [9..9] Set Pn.9 */ + __OM uint32_t BSET10 : 1; /*!< [10..10] Set Pn.10 */ + __OM uint32_t BSET11 : 1; /*!< [11..11] Set Pn.11 */ + __OM uint32_t BSET12 : 1; /*!< [12..12] Set Pn.12 */ + __OM uint32_t BSET13 : 1; /*!< [13..13] Set Pn.13 */ + __OM uint32_t BSET14 : 1; /*!< [14..14] Set Pn.14 */ + __OM uint32_t BSET15 : 1; /*!< [15..15] Set Pn.15 */ + uint32_t : 16; + } BSET_b; + } ; + + union { + __OM uint32_t BCLR; /*!< (@ 0x00000028) Offset:0x28 GPIO Port n Bits Clear Operation + Register */ + + struct { + __OM uint32_t BCLR0 : 1; /*!< [0..0] Clear Pn.0 */ + __OM uint32_t BCLR1 : 1; /*!< [1..1] Clear Pn.1 */ + __OM uint32_t BCLR2 : 1; /*!< [2..2] Clear Pn.2 */ + __OM uint32_t BCLR3 : 1; /*!< [3..3] Clear Pn.3 */ + __OM uint32_t BCLR4 : 1; /*!< [4..4] Clear Pn.4 */ + __OM uint32_t BCLR5 : 1; /*!< [5..5] Clear Pn.5 */ + __OM uint32_t BCLR6 : 1; /*!< [6..6] Clear Pn.6 */ + __OM uint32_t BCLR7 : 1; /*!< [7..7] Clear Pn.7 */ + __OM uint32_t BCLR8 : 1; /*!< [8..8] Clear Pn.8 */ + __OM uint32_t BCLR9 : 1; /*!< [9..9] Clear Pn.9 */ + __OM uint32_t BCLR10 : 1; /*!< [10..10] Clear Pn.10 */ + __OM uint32_t BCLR11 : 1; /*!< [11..11] Clear Pn.11 */ + __OM uint32_t BCLR12 : 1; /*!< [12..12] Clear Pn.12 */ + __OM uint32_t BCLR13 : 1; /*!< [13..13] Clear Pn.13 */ + __OM uint32_t BCLR14 : 1; /*!< [14..14] Clear Pn.14 */ + __OM uint32_t BCLR15 : 1; /*!< [15..15] Clear Pn.15 */ + uint32_t : 16; + } BCLR_b; + } ; +} SN_GPIO0_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO3 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose I/O (SN_GPIO3) + */ + +typedef struct { /*!< (@ 0x4004A000) SN_GPIO3 Structure */ + + union { + __IOM uint32_t DATA; /*!< (@ 0x00000000) Offset:0x00 GPIO Port n Data Register */ + + struct { + uint32_t : 3; + __IOM uint32_t DATA3 : 1; /*!< [3..3] Data of Pn.3 */ + __IOM uint32_t DATA4 : 1; /*!< [4..4] Data of Pn.4 */ + __IOM uint32_t DATA5 : 1; /*!< [5..5] Data of Pn.5 */ + __IOM uint32_t DATA6 : 1; /*!< [6..6] Data of Pn.6 */ + __IOM uint32_t DATA7 : 1; /*!< [7..7] Data of Pn.7 */ + __IOM uint32_t DATA8 : 1; /*!< [8..8] Data of Pn.8 */ + __IOM uint32_t DATA9 : 1; /*!< [9..9] Data of Pn.9 */ + __IOM uint32_t DATA10 : 1; /*!< [10..10] Data of Pn.10 */ + __IOM uint32_t DATA11 : 1; /*!< [11..11] Data of Pn.11 */ + uint32_t : 20; + } DATA_b; + } ; + + union { + __IOM uint32_t MODE; /*!< (@ 0x00000004) Offset:0x04 GPIO Port n Mode Register */ + + struct { + uint32_t : 3; + __IOM uint32_t MODE3 : 1; /*!< [3..3] Mode of Pn.3 */ + __IOM uint32_t MODE4 : 1; /*!< [4..4] Mode of Pn.4 */ + __IOM uint32_t MODE5 : 1; /*!< [5..5] Mode of Pn.5 */ + __IOM uint32_t MODE6 : 1; /*!< [6..6] Mode of Pn.6 */ + __IOM uint32_t MODE7 : 1; /*!< [7..7] Mode of Pn.7 */ + __IOM uint32_t MODE8 : 1; /*!< [8..8] Mode of Pn.8 */ + __IOM uint32_t MODE9 : 1; /*!< [9..9] Mode of Pn.9 */ + __IOM uint32_t MODE10 : 1; /*!< [10..10] Mode of Pn.10 */ + __IOM uint32_t MODE11 : 1; /*!< [11..11] Mode of Pn.11 */ + uint32_t : 20; + } MODE_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000008) Offset:0x08 GPIO Port n Configuration Register */ + + struct { + uint32_t : 6; + __IOM uint32_t CFG3 : 2; /*!< [7..6] Configuration of Pn.3 */ + __IOM uint32_t CFG4 : 2; /*!< [9..8] Configuration of Pn.4 */ + __IOM uint32_t CFG5 : 2; /*!< [11..10] Configuration of Pn.5 */ + __IOM uint32_t CFG6 : 2; /*!< [13..12] Configuration of Pn.6 */ + __IOM uint32_t CFG7 : 2; /*!< [15..14] Configuration of Pn.7 */ + __IOM uint32_t CFG8 : 2; /*!< [17..16] Configuration of Pn.8 */ + __IOM uint32_t CFG9 : 2; /*!< [19..18] Configuration of Pn.9 */ + __IOM uint32_t CFG10 : 2; /*!< [21..20] Configuration of Pn.10 */ + __IOM uint32_t CFG11 : 2; /*!< [23..22] Configuration of Pn.11 */ + uint32_t : 8; + } CFG_b; + } ; + + union { + __IOM uint32_t IS; /*!< (@ 0x0000000C) Offset:0x0C GPIO Port n Interrupt Sense Register */ + + struct { + uint32_t : 3; + __IOM uint32_t IS3 : 1; /*!< [3..3] Interrupt on Pn.3 is event or edge sensitive */ + __IOM uint32_t IS4 : 1; /*!< [4..4] Interrupt on Pn.4 is event or edge sensitive */ + __IOM uint32_t IS5 : 1; /*!< [5..5] Interrupt on Pn.5 is event or edge sensitive */ + __IOM uint32_t IS6 : 1; /*!< [6..6] Interrupt on Pn.6 is event or edge sensitive */ + __IOM uint32_t IS7 : 1; /*!< [7..7] Interrupt on Pn.7 is event or edge sensitive */ + __IOM uint32_t IS8 : 1; /*!< [8..8] Interrupt on Pn.8 is event or edge sensitive */ + __IOM uint32_t IS9 : 1; /*!< [9..9] Interrupt on Pn.9 is event or edge sensitive */ + __IOM uint32_t IS10 : 1; /*!< [10..10] Interrupt on Pn.10 is event or edge sensitive */ + __IOM uint32_t IS11 : 1; /*!< [11..11] Interrupt on Pn.11 is event or edge sensitive */ + uint32_t : 20; + } IS_b; + } ; + + union { + __IOM uint32_t IBS; /*!< (@ 0x00000010) Offset:0x10 GPIO Port n Interrupt Both-edge Sense + Register */ + + struct { + uint32_t : 3; + __IOM uint32_t IBS3 : 1; /*!< [3..3] Interrupt on Pn.3 is triggered ob both edges */ + __IOM uint32_t IBS4 : 1; /*!< [4..4] Interrupt on Pn.4 is triggered ob both edges */ + __IOM uint32_t IBS5 : 1; /*!< [5..5] Interrupt on Pn.5 is triggered ob both edges */ + __IOM uint32_t IBS6 : 1; /*!< [6..6] Interrupt on Pn.6 is triggered ob both edges */ + __IOM uint32_t IBS7 : 1; /*!< [7..7] Interrupt on Pn.7 is triggered ob both edges */ + __IOM uint32_t IBS8 : 1; /*!< [8..8] Interrupt on Pn.8 is triggered ob both edges */ + __IOM uint32_t IBS9 : 1; /*!< [9..9] Interrupt on Pn.9 is triggered ob both edges */ + __IOM uint32_t IBS10 : 1; /*!< [10..10] Interrupt on Pn.10 is triggered ob both edges */ + __IOM uint32_t IBS11 : 1; /*!< [11..11] Interrupt on Pn.11 is triggered ob both edges */ + uint32_t : 20; + } IBS_b; + } ; + + union { + __IOM uint32_t IEV; /*!< (@ 0x00000014) Offset:0x14 GPIO Port n Interrupt Event Register */ + + struct { + uint32_t : 3; + __IOM uint32_t IEV3 : 1; /*!< [3..3] Interrupt trigged evnet on Pn.3 */ + __IOM uint32_t IEV4 : 1; /*!< [4..4] Interrupt trigged evnet on Pn.4 */ + __IOM uint32_t IEV5 : 1; /*!< [5..5] Interrupt trigged evnet on Pn.5 */ + __IOM uint32_t IEV6 : 1; /*!< [6..6] Interrupt trigged evnet on Pn.6 */ + __IOM uint32_t IEV7 : 1; /*!< [7..7] Interrupt trigged evnet on Pn.7 */ + __IOM uint32_t IEV8 : 1; /*!< [8..8] Interrupt trigged evnet on Pn.8 */ + __IOM uint32_t IEV9 : 1; /*!< [9..9] Interrupt trigged evnet on Pn.9 */ + __IOM uint32_t IEV10 : 1; /*!< [10..10] Interrupt trigged evnet on Pn.10 */ + __IOM uint32_t IEV11 : 1; /*!< [11..11] Interrupt trigged evnet on Pn.11 */ + uint32_t : 20; + } IEV_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000018) Offset:0x18 GPIO Port n Interrupt Enable Register */ + + struct { + uint32_t : 3; + __IOM uint32_t IE3 : 1; /*!< [3..3] Interrupt on Pn.3 enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] Interrupt on Pn.4 enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] Interrupt on Pn.5 enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] Interrupt on Pn.6 enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] Interrupt on Pn.7 enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] Interrupt on Pn.8 enable */ + __IOM uint32_t IE9 : 1; /*!< [9..9] Interrupt on Pn.9 enable */ + __IOM uint32_t IE10 : 1; /*!< [10..10] Interrupt on Pn.10 enable */ + __IOM uint32_t IE11 : 1; /*!< [11..11] Interrupt on Pn.11 enable */ + uint32_t : 20; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x0000001C) Offset:0x1C GPIO Port n Raw Interrupt Status + Register */ + + struct { + uint32_t : 3; + __IM uint32_t IF3 : 1; /*!< [3..3] Pn.3 raw interrupt flag */ + __IM uint32_t IF4 : 1; /*!< [4..4] Pn.4 raw interrupt flag */ + __IM uint32_t IF5 : 1; /*!< [5..5] Pn.5 raw interrupt flag */ + __IM uint32_t IF6 : 1; /*!< [6..6] Pn.6 raw interrupt flag */ + __IM uint32_t IF7 : 1; /*!< [7..7] Pn.7 raw interrupt flag */ + __IM uint32_t IF8 : 1; /*!< [8..8] Pn.8 raw interrupt flag */ + __IM uint32_t IF9 : 1; /*!< [9..9] Pn.9 raw interrupt flag */ + __IM uint32_t IF10 : 1; /*!< [10..10] Pn.10 raw interrupt flag */ + __IM uint32_t IF11 : 1; /*!< [11..11] Pn.11 raw interrupt flag */ + uint32_t : 20; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000020) Offset:0x20 GPIO Port n Interrupt Clear Register */ + + struct { + uint32_t : 3; + __OM uint32_t IC3 : 1; /*!< [3..3] Pn.3 interrupt flag clear */ + __OM uint32_t IC4 : 1; /*!< [4..4] Pn.4 interrupt flag clear */ + __OM uint32_t IC5 : 1; /*!< [5..5] Pn.5 interrupt flag clear */ + __OM uint32_t IC6 : 1; /*!< [6..6] Pn.6 interrupt flag clear */ + __OM uint32_t IC7 : 1; /*!< [7..7] Pn.7 interrupt flag clear */ + __OM uint32_t IC8 : 1; /*!< [8..8] Pn.8 interrupt flag clear */ + __OM uint32_t IC9 : 1; /*!< [9..9] Pn.9 interrupt flag clear */ + __OM uint32_t IC10 : 1; /*!< [10..10] Pn.10 interrupt flag clear */ + __OM uint32_t IC11 : 1; /*!< [11..11] Pn.11 interrupt flag clear */ + uint32_t : 20; + } IC_b; + } ; + + union { + __OM uint32_t BSET; /*!< (@ 0x00000024) Offset:0x24 GPIO Port n Bits Set Operation Register */ + + struct { + uint32_t : 3; + __OM uint32_t BSET3 : 1; /*!< [3..3] Set Pn.3 */ + __OM uint32_t BSET4 : 1; /*!< [4..4] Set Pn.4 */ + __OM uint32_t BSET5 : 1; /*!< [5..5] Set Pn.5 */ + __OM uint32_t BSET6 : 1; /*!< [6..6] Set Pn.6 */ + __OM uint32_t BSET7 : 1; /*!< [7..7] Set Pn.7 */ + __OM uint32_t BSET8 : 1; /*!< [8..8] Set Pn.8 */ + __OM uint32_t BSET9 : 1; /*!< [9..9] Set Pn.9 */ + __OM uint32_t BSET10 : 1; /*!< [10..10] Set Pn.10 */ + __OM uint32_t BSET11 : 1; /*!< [11..11] Set Pn.11 */ + uint32_t : 20; + } BSET_b; + } ; + + union { + __OM uint32_t BCLR; /*!< (@ 0x00000028) Offset:0x28 GPIO Port n Bits Clear Operation + Register */ + + struct { + uint32_t : 3; + __OM uint32_t BCLR3 : 1; /*!< [3..3] Clear Pn.3 */ + __OM uint32_t BCLR4 : 1; /*!< [4..4] Clear Pn.4 */ + __OM uint32_t BCLR5 : 1; /*!< [5..5] Clear Pn.5 */ + __OM uint32_t BCLR6 : 1; /*!< [6..6] Clear Pn.6 */ + __OM uint32_t BCLR7 : 1; /*!< [7..7] Clear Pn.7 */ + __OM uint32_t BCLR8 : 1; /*!< [8..8] Clear Pn.8 */ + __OM uint32_t BCLR9 : 1; /*!< [9..9] Clear Pn.9 */ + __OM uint32_t BCLR10 : 1; /*!< [10..10] Clear Pn.10 */ + __OM uint32_t BCLR11 : 1; /*!< [11..11] Clear Pn.11 */ + uint32_t : 20; + } BCLR_b; + } ; +} SN_GPIO3_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ADC (SN_ADC) + */ + +typedef struct { /*!< (@ 0x40026000) SN_ADC Structure */ + + union { + __IOM uint32_t ADM; /*!< (@ 0x00000000) Offset:0x00 ADC Management Register */ + + struct { + __IOM uint32_t CHS : 5; /*!< [4..0] ADC input channel */ + __IOM uint32_t EOC : 1; /*!< [5..5] ADC status */ + __IOM uint32_t ADS : 1; /*!< [6..6] ADC start control */ + __IOM uint32_t ADLEN : 1; /*!< [7..7] ADC resolution */ + __IOM uint32_t ADCKS : 3; /*!< [10..8] ADC clock source divider */ + __IOM uint32_t ADENB : 1; /*!< [11..11] ADC enable */ + __IOM uint32_t AVREFHSEL : 1; /*!< [12..12] ADC high reference voltage source */ + __IOM uint32_t VHS : 3; /*!< [15..13] Internal Ref. voltage source */ + __IOM uint32_t GCHS : 1; /*!< [16..16] ADC global channel enable */ + uint32_t : 15; + } ADM_b; + } ; + __IM uint32_t ADB; /*!< (@ 0x00000004) Offset:0x04 ADC Data Register */ + __IM uint32_t RESERVED; + + union { + __IOM uint32_t IE; /*!< (@ 0x0000000C) Offset:0x0C ADC Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] AIN0 interrupt enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] AIN1 interrupt enable */ + __IOM uint32_t IE2 : 1; /*!< [2..2] AIN2 interrupt enable */ + __IOM uint32_t IE3 : 1; /*!< [3..3] AIN3 interrupt enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] AIN4 interrupt enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] AIN5 interrupt enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] AIN6 interrupt enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] AIN7 interrupt enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] AIN8 interrupt enable */ + __IOM uint32_t IE9 : 1; /*!< [9..9] AIN9 interrupt enable */ + __IOM uint32_t IE10 : 1; /*!< [10..10] AIN10 interrupt enable */ + __IOM uint32_t IE11 : 1; /*!< [11..11] AIN11 interrupt enable */ + __IOM uint32_t IE12 : 1; /*!< [12..12] AIN12 interrupt enable */ + __IOM uint32_t IE13 : 1; /*!< [13..13] AIN13 interrupt enable */ + __IOM uint32_t IE14 : 1; /*!< [14..14] AIN14 interrupt enable */ + __IOM uint32_t IE15 : 1; /*!< [15..15] AIN15 interrupt enable */ + __IOM uint32_t IE16 : 1; /*!< [16..16] AIN16 interrupt enable */ + __IOM uint32_t IE17 : 1; /*!< [17..17] AIN17 interrupt enable */ + __IOM uint32_t IE18 : 1; /*!< [18..18] AIN18 interrupt enable */ + uint32_t : 13; + } IE_b; + } ; + __IOM uint32_t RIS; /*!< (@ 0x00000010) Offset:0x10 ADC Raw Interrupt Status Register */ +} SN_ADC_Type; /*!< Size = 20 (0x14) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CT16B0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 16-bit Timer 0 with Capture function (SN_CT16B0) + */ + +typedef struct { /*!< (@ 0x40000000) SN_CT16B0 Structure */ + + union { + __IOM uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT16Bn Timer Control Register */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] Counter enable */ + __IOM uint32_t CRST : 1; /*!< [1..1] Counter Reset */ + uint32_t : 30; + } TMRCTRL_b; + } ; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT16Bn Timer Counter Register */ + + struct { + __IOM uint32_t TC : 16; /*!< [15..0] Timer Counter */ + uint32_t : 16; + } TC_b; + } ; + + union { + __IOM uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT16Bn Prescale Register */ + + struct { + __IOM uint32_t PRE : 8; /*!< [7..0] Prescaler */ + uint32_t : 24; + } PRE_b; + } ; + + union { + __IOM uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT16Bn Prescale Counter Register */ + + struct { + __IOM uint32_t PC : 8; /*!< [7..0] Prescaler Counter */ + uint32_t : 24; + } PC_b; + } ; + + union { + __IOM uint32_t CNTCTRL; /*!< (@ 0x00000010) Offset:0x10 CT16Bn Counter Control Register */ + + struct { + __IOM uint32_t CTM : 2; /*!< [1..0] Counter/Timer Mode */ + __IOM uint32_t CIS : 2; /*!< [3..2] Counter Input Select */ + uint32_t : 28; + } CNTCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT16Bn Match Control Register */ + + struct { + __IOM uint32_t MR0IE : 1; /*!< [0..0] Enable generating an interrupt when MR0 matches TC */ + __IOM uint32_t MR0RST : 1; /*!< [1..1] Enable reset TC when MR0 matches TC */ + __IOM uint32_t MR0STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR0 matches TC */ + uint32_t : 29; + } MCTRL_b; + } ; + __IM uint32_t RESERVED[2]; + __IOM uint32_t MR0; /*!< (@ 0x00000020) Offset:0x20 CT16Bn MR0 Register */ + __IM uint32_t RESERVED1[23]; + + union { + __IOM uint32_t CAPCTRL; /*!< (@ 0x00000080) Offset:0x80 CT16Bn Capture Control Register */ + + struct { + __IOM uint32_t CAP0RE : 1; /*!< [0..0] Capture on CT16Bn_CAP0 rising edge */ + __IOM uint32_t CAP0FE : 1; /*!< [1..1] Capture on CT16Bn_CAP0 falling edge */ + __IOM uint32_t CAP0IE : 1; /*!< [2..2] Interrupt on CT16Bn_CAP0 event */ + __IOM uint32_t CAP0EN : 1; /*!< [3..3] CAP0 function enable */ + uint32_t : 28; + } CAPCTRL_b; + } ; + + union { + __IM uint32_t CAP0; /*!< (@ 0x00000084) Offset:0x84 CT16Bn CAP0 Register */ + + struct { + __IM uint32_t CAP0 : 16; /*!< [15..0] Timer counter capture value */ + uint32_t : 16; + } CAP0_b; + } ; + __IM uint32_t RESERVED2[7]; + + union { + __IM uint32_t RIS; /*!< (@ 0x000000A4) Offset:0xA4 CT16Bn Raw Interrupt Status Register */ + + struct { + __IM uint32_t MR0IF : 1; /*!< [0..0] Match channel 0 interrupt flag */ + uint32_t : 24; + __IM uint32_t CAP0IF : 1; /*!< [25..25] Interrupt flag for capture channel 0 */ + uint32_t : 6; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x000000A8) Offset:0xA8 CT16Bn Interrupt Clear Register */ + + struct { + __OM uint32_t MR0IC : 1; /*!< [0..0] MR0IF clear bit */ + uint32_t : 24; + __OM uint32_t CAP0IC : 1; /*!< [25..25] CAP0IF clear bit */ + uint32_t : 6; + } IC_b; + } ; +} SN_CT16B0_Type; /*!< Size = 172 (0xac) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CT16B1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 16-bit Timer 0 with Capture function (SN_CT16B1) + */ + +typedef struct { /*!< (@ 0x40002000) SN_CT16B1 Structure */ + + union { + __IOM uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT16Bn Timer Control Register */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] Counter enable */ + __IOM uint32_t CRST : 1; /*!< [1..1] Counter Reset */ + uint32_t : 30; + } TMRCTRL_b; + } ; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT16Bn Timer Counter Register */ + + struct { + __IOM uint32_t TC : 16; /*!< [15..0] Timer Counter */ + uint32_t : 16; + } TC_b; + } ; + + union { + __IOM uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT16Bn Prescale Register */ + + struct { + __IOM uint32_t PRE : 8; /*!< [7..0] Prescaler */ + uint32_t : 24; + } PRE_b; + } ; + + union { + __IOM uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT16Bn Prescale Counter Register */ + + struct { + __IOM uint32_t PC : 8; /*!< [7..0] Prescaler Counter */ + uint32_t : 24; + } PC_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT16Bn Match Control Register */ + + struct { + __IOM uint32_t MR0IE : 1; /*!< [0..0] Enable generating an interrupt when MR0 matches TC */ + __IOM uint32_t MR0RST : 1; /*!< [1..1] Enable reset TC when MR0 matches TC */ + __IOM uint32_t MR0STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR0 matches TC */ + __IOM uint32_t MR1IE : 1; /*!< [3..3] Enable generating an interrupt when MR1 matches TC */ + __IOM uint32_t MR1RST : 1; /*!< [4..4] Enable reset TC when MR1 matches TC */ + __IOM uint32_t MR1STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR1 matches TC */ + __IOM uint32_t MR2IE : 1; /*!< [6..6] Enable generating an interrupt when MR2 matches TC */ + __IOM uint32_t MR2RST : 1; /*!< [7..7] Enable reset TC when MR2 matches TC */ + __IOM uint32_t MR2STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR2 matches TC */ + __IOM uint32_t MR3IE : 1; /*!< [9..9] Enable generating an interrupt when MR3 matches TC */ + __IOM uint32_t MR3RST : 1; /*!< [10..10] Enable reset TC when MR3 matches TC */ + __IOM uint32_t MR3STOP : 1; /*!< [11..11] Stop TC and PC and clear CEN bit when MR3 matches TC */ + __IOM uint32_t MR4IE : 1; /*!< [12..12] Enable generating an interrupt when MR4 matches TC */ + __IOM uint32_t MR4RST : 1; /*!< [13..13] Enable reset TC when MR4 matches TC */ + __IOM uint32_t MR4STOP : 1; /*!< [14..14] Stop TC and PC and clear CEN bit when MR4 matches TC */ + __IOM uint32_t MR5IE : 1; /*!< [15..15] Enable generating an interrupt when MR5 matches TC */ + __IOM uint32_t MR5RST : 1; /*!< [16..16] Enable reset TC when MR5 matches TC */ + __IOM uint32_t MR5STOP : 1; /*!< [17..17] Stop TC and PC and clear CEN bit when MR5 matches TC */ + __IOM uint32_t MR6IE : 1; /*!< [18..18] Enable generating an interrupt when MR6 matches TC */ + __IOM uint32_t MR6RST : 1; /*!< [19..19] Enable reset TC when MR6 matches TC */ + __IOM uint32_t MR6STOP : 1; /*!< [20..20] Stop TC and PC and clear CEN bit when MR6 matches TC */ + __IOM uint32_t MR7IE : 1; /*!< [21..21] Enable generating an interrupt when MR7 matches TC */ + __IOM uint32_t MR7RST : 1; /*!< [22..22] Enable reset TC when MR7 matches TC */ + __IOM uint32_t MR7STOP : 1; /*!< [23..23] Stop TC and PC and clear CEN bit when MR7 matches TC */ + __IOM uint32_t MR8IE : 1; /*!< [24..24] Enable generating an interrupt when MR8 matches TC */ + __IOM uint32_t MR8RST : 1; /*!< [25..25] Enable reset TC when MR8 matches TC */ + __IOM uint32_t MR8STOP : 1; /*!< [26..26] Stop TC and PC and clear CEN bit when MR8 matches TC */ + __IOM uint32_t MR9IE : 1; /*!< [27..27] Enable generating an interrupt when MR9 matches TC */ + __IOM uint32_t MR9RST : 1; /*!< [28..28] Enable reset TC when MR9 matches TC */ + __IOM uint32_t MR9STOP : 1; /*!< [29..29] Stop TC and PC and clear CEN bit when MR9 matches TC */ + uint32_t : 2; + } MCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL2; /*!< (@ 0x00000018) Offset:0x18 CT16Bn Match Control Register 2 */ + + struct { + __IOM uint32_t MR10IE : 1; /*!< [0..0] Enable generating an interrupt when MR10 matches TC */ + __IOM uint32_t MR10RST : 1; /*!< [1..1] Enable reset TC when MR10 matches TC */ + __IOM uint32_t MR10STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR10 matches TC */ + __IOM uint32_t MR11IE : 1; /*!< [3..3] Enable generating an interrupt when MR11 matches TC */ + __IOM uint32_t MR11RST : 1; /*!< [4..4] Enable reset TC when MR11 matches TC */ + __IOM uint32_t MR11STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR11 matches TC */ + __IOM uint32_t MR12IE : 1; /*!< [6..6] Enable generating an interrupt when MR12 matches TC */ + __IOM uint32_t MR12RST : 1; /*!< [7..7] Enable reset TC when MR12 matches TC */ + __IOM uint32_t MR12STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR12 matches TC */ + __IOM uint32_t MR13IE : 1; /*!< [9..9] Enable generating an interrupt when MR13 matches TC */ + __IOM uint32_t MR13RST : 1; /*!< [10..10] Enable reset TC when MR13 matches TC */ + __IOM uint32_t MR13STOP : 1; /*!< [11..11] Stop TC and PC and clear CEN bit when MR13 matches + TC */ + __IOM uint32_t MR14IE : 1; /*!< [12..12] Enable generating an interrupt when MR14 matches TC */ + __IOM uint32_t MR14RST : 1; /*!< [13..13] Enable reset TC when MR14 matches TC */ + __IOM uint32_t MR14STOP : 1; /*!< [14..14] Stop TC and PC and clear CEN bit when MR14 matches + TC */ + __IOM uint32_t MR15IE : 1; /*!< [15..15] Enable generating an interrupt when MR15 matches TC */ + __IOM uint32_t MR15RST : 1; /*!< [16..16] Enable reset TC when MR15 matches TC */ + __IOM uint32_t MR15STOP : 1; /*!< [17..17] Stop TC and PC and clear CEN bit when MR15 matches + TC */ + __IOM uint32_t MR16IE : 1; /*!< [18..18] Enable generating an interrupt when MR16 matches TC */ + __IOM uint32_t MR16RST : 1; /*!< [19..19] Enable reset TC when MR16 matches TC */ + __IOM uint32_t MR16STOP : 1; /*!< [20..20] Stop TC and PC and clear CEN bit when MR16 matches + TC */ + __IOM uint32_t MR17IE : 1; /*!< [21..21] Enable generating an interrupt when MR17 matches TC */ + __IOM uint32_t MR17RST : 1; /*!< [22..22] Enable reset TC when MR17 matches TC */ + __IOM uint32_t MR17STOP : 1; /*!< [23..23] Stop TC and PC and clear CEN bit when MR17 matches + TC */ + __IOM uint32_t MR18IE : 1; /*!< [24..24] Enable generating an interrupt when MR18 matches TC */ + __IOM uint32_t MR18RST : 1; /*!< [25..25] Enable reset TC when MR18 matches TC */ + __IOM uint32_t MR18STOP : 1; /*!< [26..26] Stop TC and PC and clear CEN bit when MR18 matches + TC */ + __IOM uint32_t MR19IE : 1; /*!< [27..27] Enable generating an interrupt when MR19 matches TC */ + __IOM uint32_t MR19RST : 1; /*!< [28..28] Enable reset TC when MR19 matches TC */ + __IOM uint32_t MR19STOP : 1; /*!< [29..29] Stop TC and PC and clear CEN bit when MR19 matches + TC */ + uint32_t : 2; + } MCTRL2_b; + } ; + + union { + __IOM uint32_t MCTRL3; /*!< (@ 0x0000001C) Offset:0x1C CT16Bn Match Control Register 3 */ + + struct { + __IOM uint32_t MR20IE : 1; /*!< [0..0] Enable generating an interrupt when MR20 matches TC */ + __IOM uint32_t MR20RST : 1; /*!< [1..1] Enable reset TC when MR20 matches TC */ + __IOM uint32_t MR20STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR20 matches TC */ + __IOM uint32_t MR21IE : 1; /*!< [3..3] Enable generating an interrupt when MR21 matches TC */ + __IOM uint32_t MR21RST : 1; /*!< [4..4] Enable reset TC when MR21 matches TC */ + __IOM uint32_t MR21STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR21 matches TC */ + __IOM uint32_t MR22IE : 1; /*!< [6..6] Enable generating an interrupt when MR22 matches TC */ + __IOM uint32_t MR22RST : 1; /*!< [7..7] Enable reset TC when MR22 matches TC */ + __IOM uint32_t MR22STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR22 matches TC */ + __IOM uint32_t MR23IE : 1; /*!< [9..9] Enable generating an interrupt when MR23 matches TC */ + __IOM uint32_t MR23RST : 1; /*!< [10..10] Enable reset TC when MR23 matches TC */ + __IOM uint32_t MR23STOP : 1; /*!< [11..11] Stop TC and PC and clear CEN bit when MR23 matches + TC */ + __IOM uint32_t MR24IE : 1; /*!< [12..12] Enable generating an interrupt when MR24 matches TC */ + __IOM uint32_t MR24RST : 1; /*!< [13..13] Enable reset TC when MR24 matches TC */ + __IOM uint32_t MR24STOP : 1; /*!< [14..14] Stop TC and PC and clear CEN bit when MR24 matches + TC */ + uint32_t : 17; + } MCTRL3_b; + } ; + __IOM uint32_t MR0; /*!< (@ 0x00000020) Offset:0x20 CT16Bn MR0 Register */ + __IOM uint32_t MR1; /*!< (@ 0x00000024) Offset:0x24 CT16Bn MR1 Register */ + __IOM uint32_t MR2; /*!< (@ 0x00000028) Offset:0x28 CT16Bn MR2 Register */ + __IOM uint32_t MR3; /*!< (@ 0x0000002C) Offset:0x2C CT16Bn MR3 Register */ + __IOM uint32_t MR4; /*!< (@ 0x00000030) Offset:0x30 CT16Bn MR4 Register */ + __IOM uint32_t MR5; /*!< (@ 0x00000034) Offset:0x34 CT16Bn MR5 Register */ + __IOM uint32_t MR6; /*!< (@ 0x00000038) Offset:0x38 CT16Bn MR6 Register */ + __IOM uint32_t MR7; /*!< (@ 0x0000003C) Offset:0x3C CT16Bn MR7 Register */ + __IOM uint32_t MR8; /*!< (@ 0x00000040) Offset:0x40 CT16Bn MR8 Register */ + __IOM uint32_t MR9; /*!< (@ 0x00000044) Offset:0x44 CT16Bn MR9 Register */ + __IOM uint32_t MR10; /*!< (@ 0x00000048) Offset:0x48 CT16Bn MR10 Register */ + __IOM uint32_t MR11; /*!< (@ 0x0000004C) Offset:0x4C CT16Bn MR11 Register */ + __IOM uint32_t MR12; /*!< (@ 0x00000050) Offset:0x50 CT16Bn MR12 Register */ + __IOM uint32_t MR13; /*!< (@ 0x00000054) Offset:0x54 CT16Bn MR13 Register */ + __IOM uint32_t MR14; /*!< (@ 0x00000058) Offset:0x58 CT16Bn MR14 Register */ + __IOM uint32_t MR15; /*!< (@ 0x0000005C) Offset:0x5C CT16Bn MR15 Register */ + __IOM uint32_t MR16; /*!< (@ 0x00000060) Offset:0x60 CT16Bn MR16 Register */ + __IOM uint32_t MR17; /*!< (@ 0x00000064) Offset:0x64 CT16Bn MR17 Register */ + __IOM uint32_t MR18; /*!< (@ 0x00000068) Offset:0x68 CT16Bn MR18 Register */ + __IOM uint32_t MR19; /*!< (@ 0x0000006C) Offset:0x6C CT16Bn MR19 Register */ + __IOM uint32_t MR20; /*!< (@ 0x00000070) Offset:0x70 CT16Bn MR20 Register */ + __IOM uint32_t MR21; /*!< (@ 0x00000074) Offset:0x74 CT16Bn MR21 Register */ + __IOM uint32_t MR22; /*!< (@ 0x00000078) Offset:0x78 CT16Bn MR22 Register */ + __IOM uint32_t MR23; /*!< (@ 0x0000007C) Offset:0x7C CT16Bn MR23 Register */ + __IOM uint32_t MR24; /*!< (@ 0x00000080) Offset:0x80 CT16Bn MR24 Register */ + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t EM; /*!< (@ 0x00000088) Offset:0x88 CT16Bn External Match Register */ + + struct { + __IOM uint32_t EM0 : 1; /*!< [0..0] When the TC doesn't match MR0 and EMC0 is not 0, this + bit will drive the state of CT16Bn_PWM0 output. */ + __IOM uint32_t EM1 : 1; /*!< [1..1] When the TC doesn't match MR1 and EMC1 is not 0, this + bit will drive the state of CT16Bn_PWM1 output. */ + __IOM uint32_t EM2 : 1; /*!< [2..2] When the TC doesn't match MR2 and EMC2 is not 0, this + bit will drive the state of CT16Bn_PWM2 output. */ + __IOM uint32_t EM3 : 1; /*!< [3..3] When the TC doesn't match MR3 and EMC3 is not 0, this + bit will drive the state of CT16Bn_PWM3 output. */ + __IOM uint32_t EM4 : 1; /*!< [4..4] When the TC doesn't match MR4 and EMC4 is not 0, this + bit will drive the state of CT16Bn_PWM4 output. */ + __IOM uint32_t EM5 : 1; /*!< [5..5] When the TC doesn't match MR5 and EMC5 is not 0, this + bit will drive the state of CT16Bn_PWM5 output. */ + __IOM uint32_t EM6 : 1; /*!< [6..6] When the TC doesn't match MR6 and EMC6 is not 0, this + bit will drive the state of CT16Bn_PWM6 output. */ + __IOM uint32_t EM7 : 1; /*!< [7..7] When the TC doesn't match MR7 and EMC7 is not 0, this + bit will drive the state of CT16Bn_PWM7 output. */ + __IOM uint32_t EM8 : 1; /*!< [8..8] When the TC doesn't match MR8 and EMC8 is not 0, this + bit will drive the state of CT16Bn_PWM8 output. */ + __IOM uint32_t EM9 : 1; /*!< [9..9] When the TC doesn't match MR9 and EMC9 is not 0, this + bit will drive the state of CT16Bn_PWM9 output. */ + __IOM uint32_t EM10 : 1; /*!< [10..10] When the TC doesn't match MR10 and EMC10 is not 0, + this bit will drive the state of CT16Bn_PWM10 output. */ + __IOM uint32_t EM11 : 1; /*!< [11..11] When the TC doesn't match MR11 and EMC11 is not 0, + this bit will drive the state of CT16Bn_PWM11 output. */ + __IOM uint32_t EM12 : 1; /*!< [12..12] When the TC doesn't match MR12 and EMC12 is not 0, + this bit will drive the state of CT16Bn_PWM12 output. */ + __IOM uint32_t EM13 : 1; /*!< [13..13] When the TC doesn't match MR13 and EMC13 is not 0, + this bit will drive the state of CT16Bn_PWM13 output. */ + __IOM uint32_t EM14 : 1; /*!< [14..14] When the TC doesn't match MR14 and EMC14 is not 0, + this bit will drive the state of CT16Bn_PWM14 output. */ + __IOM uint32_t EM15 : 1; /*!< [15..15] When the TC doesn't match MR15 and EMC15 is not 0, + this bit will drive the state of CT16Bn_PWM15 output. */ + __IOM uint32_t EM16 : 1; /*!< [16..16] When the TC doesn't match MR16 and EMC16 is not 0, + this bit will drive the state of CT16Bn_PWM16 output. */ + __IOM uint32_t EM17 : 1; /*!< [17..17] When the TC doesn't match MR17 and EMC17 is not 0, + this bit will drive the state of CT16Bn_PWM17 output. */ + __IOM uint32_t EM18 : 1; /*!< [18..18] When the TC doesn't match MR18 and EMC18 is not 0, + this bit will drive the state of CT16Bn_PWM18 output. */ + __IOM uint32_t EM19 : 1; /*!< [19..19] When the TC doesn't match MR19 and EMC19 is not 0, + this bit will drive the state of CT16Bn_PWM19 output. */ + __IOM uint32_t EM20 : 1; /*!< [20..20] When the TC doesn't match MR20 and EMC20 is not 0, + this bit will drive the state of CT16Bn_PWM20 output. */ + __IOM uint32_t EM21 : 1; /*!< [21..21] When the TC doesn't match MR21 and EMC21 is not 0, + this bit will drive the state of CT16Bn_PWM21 output. */ + __IOM uint32_t EM22 : 1; /*!< [22..22] When the TC doesn't match MR22 and EMC22 is not 0, + this bit will drive the state of CT16Bn_PWM22 output. */ + __IOM uint32_t EM23 : 1; /*!< [23..23] When the TC doesn't match MR23 and EMC23 is not 0, + this bit will drive the state of CT16Bn_PWM23 output. */ + uint32_t : 8; + } EM_b; + } ; + + union { + __IOM uint32_t EMC; /*!< (@ 0x0000008C) Offset:0x8C CT16Bn External Match Control register */ + + struct { + __IOM uint32_t EMC0 : 2; /*!< [1..0] CT16Bn_PWM0 functionality when the TC matches MR0 */ + __IOM uint32_t EMC1 : 2; /*!< [3..2] CT16Bn_PWM1 functionality when the TC matches MR1 */ + __IOM uint32_t EMC2 : 2; /*!< [5..4] CT16Bn_PWM2 functionality when the TC matches MR2 */ + __IOM uint32_t EMC3 : 2; /*!< [7..6] CT16Bn_PWM3 functionality when the TC matches MR3 */ + __IOM uint32_t EMC4 : 2; /*!< [9..8] CT16Bn_PWM4 functionality when the TC matches MR4 */ + __IOM uint32_t EMC5 : 2; /*!< [11..10] CT16Bn_PWM5 functionality when the TC matches MR5 */ + __IOM uint32_t EMC6 : 2; /*!< [13..12] CT16Bn_PWM6 functionality when the TC matches MR6 */ + __IOM uint32_t EMC7 : 2; /*!< [15..14] CT16Bn_PWM7 functionality when the TC matches MR7 */ + __IOM uint32_t EMC8 : 2; /*!< [17..16] CT16Bn_PWM8 functionality when the TC matches MR8 */ + __IOM uint32_t EMC9 : 2; /*!< [19..18] CT16Bn_PWM9 functionality when the TC matches MR9 */ + __IOM uint32_t EMC10 : 2; /*!< [21..20] CT16Bn_PWM10 functionality when the TC matches MR10 */ + __IOM uint32_t EMC11 : 2; /*!< [23..22] CT16Bn_PWM11 functionality when the TC matches MR11 */ + __IOM uint32_t EMC12 : 2; /*!< [25..24] CT16Bn_PWM12 functionality when the TC matches MR12 */ + __IOM uint32_t EMC13 : 2; /*!< [27..26] CT16Bn_PWM13 functionality when the TC matches MR13 */ + __IOM uint32_t EMC14 : 2; /*!< [29..28] CT16Bn_PWM14 functionality when the TC matches MR14 */ + __IOM uint32_t EMC15 : 2; /*!< [31..30] CT16Bn_PWM15 functionality when the TC matches MR15 */ + } EMC_b; + } ; + + union { + __IOM uint32_t EMC2; /*!< (@ 0x00000090) Offset:0x90 CT16Bn External Match Control register + 2 */ + + struct { + __IOM uint32_t EMC16 : 2; /*!< [1..0] CT16Bn_PWM16 functionality when the TC matches MR16 */ + __IOM uint32_t EMC17 : 2; /*!< [3..2] CT16Bn_PWM17 functionality when the TC matches MR17 */ + __IOM uint32_t EMC18 : 2; /*!< [5..4] CT16Bn_PWM18 functionality when the TC matches MR18 */ + __IOM uint32_t EMC19 : 2; /*!< [7..6] CT16Bn_PWM19 functionality when the TC matches MR19 */ + __IOM uint32_t EMC20 : 2; /*!< [9..8] CT16Bn_PWM20 functionality when the TC matches MR20 */ + __IOM uint32_t EMC21 : 2; /*!< [11..10] CT16Bn_PWM21 functionality when the TC matches MR21 */ + __IOM uint32_t EMC22 : 2; /*!< [13..12] CT16Bn_PWM22 functionality when the TC matches MR22 */ + __IOM uint32_t EMC23 : 2; /*!< [15..14] CT16Bn_PWM23 functionality when the TC matches MR23 */ + uint32_t : 16; + } EMC2_b; + } ; + + union { + __IOM uint32_t PWMCTRL; /*!< (@ 0x00000094) Offset:0x94 CT16Bn PWM Control Register */ + + struct { + __IOM uint32_t PWM0MODE : 2; /*!< [1..0] PWM0 output mode */ + __IOM uint32_t PWM1MODE : 2; /*!< [3..2] PWM1 output mode */ + __IOM uint32_t PWM2MODE : 2; /*!< [5..4] PWM2 output mode */ + __IOM uint32_t PWM3MODE : 2; /*!< [7..6] PWM3 output mode */ + __IOM uint32_t PWM4MODE : 2; /*!< [9..8] PWM4 output mode */ + __IOM uint32_t PWM5MODE : 2; /*!< [11..10] PWM5 output mode */ + __IOM uint32_t PWM6MODE : 2; /*!< [13..12] PWM6 output mode */ + __IOM uint32_t PWM7MODE : 2; /*!< [15..14] PWM7 output mode */ + __IOM uint32_t PWM8MODE : 2; /*!< [17..16] PWM8 output mode */ + __IOM uint32_t PWM9MODE : 2; /*!< [19..18] PWM9 output mode */ + __IOM uint32_t PWM10MODE : 2; /*!< [21..20] PWM10 output mode */ + __IOM uint32_t PWM11MODE : 2; /*!< [23..22] PWM11 output mode */ + __IOM uint32_t PWM12MODE : 2; /*!< [25..24] PWM12 output mode */ + __IOM uint32_t PWM13MODE : 2; /*!< [27..26] PWM13 output mode */ + __IOM uint32_t PWM14MODE : 2; /*!< [29..28] PWM14 output mode */ + __IOM uint32_t PWM15MODE : 2; /*!< [31..30] PWM15 output mode */ + } PWMCTRL_b; + } ; + + union { + __IOM uint32_t PWMCTRL2; /*!< (@ 0x00000098) Offset:0x98 CT16Bn PWM Control Register 2 */ + + struct { + __IOM uint32_t PWM16MODE : 2; /*!< [1..0] PWM16 output mode */ + __IOM uint32_t PWM17MODE : 2; /*!< [3..2] PWM17 output mode */ + __IOM uint32_t PWM18MODE : 2; /*!< [5..4] PWM18 output mode */ + __IOM uint32_t PWM19MODE : 2; /*!< [7..6] PWM19 output mode */ + __IOM uint32_t PWM20MODE : 2; /*!< [9..8] PWM20 output mode */ + __IOM uint32_t PWM21MODE : 2; /*!< [11..10] PWM21 output mode */ + __IOM uint32_t PWM22MODE : 2; /*!< [13..12] PWM22 output mode */ + __IOM uint32_t PWM23MODE : 2; /*!< [15..14] PWM23 output mode */ + uint32_t : 16; + } PWMCTRL2_b; + } ; + + union { + __IOM uint32_t PWMENB; /*!< (@ 0x0000009C) Offset:0x9C CT16Bn PWM Enable register */ + + struct { + __IOM uint32_t PWM0EN : 1; /*!< [0..0] PWM0 enable */ + __IOM uint32_t PWM1EN : 1; /*!< [1..1] PWM1 enable */ + __IOM uint32_t PWM2EN : 1; /*!< [2..2] PWM2 enable */ + __IOM uint32_t PWM3EN : 1; /*!< [3..3] PWM3 enable */ + __IOM uint32_t PWM4EN : 1; /*!< [4..4] PWM4 enable */ + __IOM uint32_t PWM5EN : 1; /*!< [5..5] PWM5 enable */ + __IOM uint32_t PWM6EN : 1; /*!< [6..6] PWM6 enable */ + __IOM uint32_t PWM7EN : 1; /*!< [7..7] PWM7 enable */ + __IOM uint32_t PWM8EN : 1; /*!< [8..8] PWM8 enable */ + __IOM uint32_t PWM9EN : 1; /*!< [9..9] PWM9 enable */ + __IOM uint32_t PWM10EN : 1; /*!< [10..10] PWM10 enable */ + __IOM uint32_t PWM11EN : 1; /*!< [11..11] PWM11 enable */ + __IOM uint32_t PWM12EN : 1; /*!< [12..12] PWM12 enable */ + __IOM uint32_t PWM13EN : 1; /*!< [13..13] PWM13 enable */ + __IOM uint32_t PWM14EN : 1; /*!< [14..14] PWM14 enable */ + __IOM uint32_t PWM15EN : 1; /*!< [15..15] PWM15 enable */ + __IOM uint32_t PWM16EN : 1; /*!< [16..16] PWM16 enable */ + __IOM uint32_t PWM17EN : 1; /*!< [17..17] PWM17 enable */ + __IOM uint32_t PWM18EN : 1; /*!< [18..18] PWM18 enable */ + __IOM uint32_t PWM19EN : 1; /*!< [19..19] PWM19 enable */ + __IOM uint32_t PWM20EN : 1; /*!< [20..20] PWM20 enable */ + __IOM uint32_t PWM21EN : 1; /*!< [21..21] PWM21 enable */ + __IOM uint32_t PWM22EN : 1; /*!< [22..22] PWM22 enable */ + __IOM uint32_t PWM23EN : 1; /*!< [23..23] PWM23 enable */ + uint32_t : 8; + } PWMENB_b; + } ; + + union { + __IOM uint32_t PWMIOENB; /*!< (@ 0x000000A0) Offset:0xA0 CT16Bn PWM IO Enable register */ + + struct { + __IOM uint32_t PWM0IOEN : 1; /*!< [0..0] CT16Bn_PWM0/GPIO selection */ + __IOM uint32_t PWM1IOEN : 1; /*!< [1..1] CT16Bn_PWM1/GPIO selection */ + __IOM uint32_t PWM2IOEN : 1; /*!< [2..2] CT16Bn_PWM2/GPIO selection */ + __IOM uint32_t PWM3IOEN : 1; /*!< [3..3] CT16Bn_PWM3/GPIO selection */ + __IOM uint32_t PWM4IOEN : 1; /*!< [4..4] CT16Bn_PWM4/GPIO selection */ + __IOM uint32_t PWM5IOEN : 1; /*!< [5..5] CT16Bn_PWM5/GPIO selection */ + __IOM uint32_t PWM6IOEN : 1; /*!< [6..6] CT16Bn_PWM6/GPIO selection */ + __IOM uint32_t PWM7IOEN : 1; /*!< [7..7] CT16Bn_PWM7/GPIO selection */ + __IOM uint32_t PWM8IOEN : 1; /*!< [8..8] CT16Bn_PWM8/GPIO selection */ + __IOM uint32_t PWM9IOEN : 1; /*!< [9..9] CT16Bn_PWM9/GPIO selection */ + __IOM uint32_t PWM10IOEN : 1; /*!< [10..10] CT16Bn_PWM10/GPIO selection */ + __IOM uint32_t PWM11IOEN : 1; /*!< [11..11] CT16Bn_PWM11/GPIO selection */ + __IOM uint32_t PWM12IOEN : 1; /*!< [12..12] CT16Bn_PWM12/GPIO selection */ + __IOM uint32_t PWM13IOEN : 1; /*!< [13..13] CT16Bn_PWM13/GPIO selection */ + __IOM uint32_t PWM14IOEN : 1; /*!< [14..14] CT16Bn_PWM14/GPIO selection */ + __IOM uint32_t PWM15IOEN : 1; /*!< [15..15] CT16Bn_PWM15/GPIO selection */ + __IOM uint32_t PWM16IOEN : 1; /*!< [16..16] CT16Bn_PWM16/GPIO selection */ + __IOM uint32_t PWM17IOEN : 1; /*!< [17..17] CT16Bn_PWM17/GPIO selection */ + __IOM uint32_t PWM18IOEN : 1; /*!< [18..18] CT16Bn_PWM18/GPIO selection */ + __IOM uint32_t PWM19IOEN : 1; /*!< [19..19] CT16Bn_PWM19/GPIO selection */ + __IOM uint32_t PWM20IOEN : 1; /*!< [20..20] CT16Bn_PWM20/GPIO selection */ + __IOM uint32_t PWM21IOEN : 1; /*!< [21..21] CT16Bn_PWM21/GPIO selection */ + __IOM uint32_t PWM22IOEN : 1; /*!< [22..22] CT16Bn_PWM22/GPIO selection */ + __IOM uint32_t PWM23IOEN : 1; /*!< [23..23] CT16Bn_PWM23/GPIO selection */ + uint32_t : 8; + } PWMIOENB_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x000000A4) Offset:0xA4 CT16Bn Raw Interrupt Status Register */ + + struct { + __IM uint32_t MR0IF : 1; /*!< [0..0] Match channel 0 interrupt flag */ + __IM uint32_t MR1IF : 1; /*!< [1..1] Match channel 1 interrupt flag */ + __IM uint32_t MR2IF : 1; /*!< [2..2] Match channel 2 interrupt flag */ + __IM uint32_t MR3IF : 1; /*!< [3..3] Match channel 3 interrupt flag */ + __IM uint32_t MR4IF : 1; /*!< [4..4] Match channel 4 interrupt flag */ + __IM uint32_t MR5IF : 1; /*!< [5..5] Match channel 5 interrupt flag */ + __IM uint32_t MR6IF : 1; /*!< [6..6] Match channel 6 interrupt flag */ + __IM uint32_t MR7IF : 1; /*!< [7..7] Match channel 7 interrupt flag */ + __IM uint32_t MR8IF : 1; /*!< [8..8] Match channel 8 interrupt flag */ + __IM uint32_t MR9IF : 1; /*!< [9..9] Match channel 9 interrupt flag */ + __IM uint32_t MR10IF : 1; /*!< [10..10] Match channel 10 interrupt flag */ + __IM uint32_t MR11IF : 1; /*!< [11..11] Match channel 11 interrupt flag */ + __IM uint32_t MR12IF : 1; /*!< [12..12] Match channel 12 interrupt flag */ + __IM uint32_t MR13IF : 1; /*!< [13..13] Match channel 13 interrupt flag */ + __IM uint32_t MR14IF : 1; /*!< [14..14] Match channel 14 interrupt flag */ + __IM uint32_t MR15IF : 1; /*!< [15..15] Match channel 15 interrupt flag */ + __IM uint32_t MR16IF : 1; /*!< [16..16] Match channel 16 interrupt flag */ + __IM uint32_t MR17IF : 1; /*!< [17..17] Match channel 17 interrupt flag */ + __IM uint32_t MR18IF : 1; /*!< [18..18] Match channel 18 interrupt flag */ + __IM uint32_t MR19IF : 1; /*!< [19..19] Match channel 19 interrupt flag */ + __IM uint32_t MR20IF : 1; /*!< [20..20] Match channel 20 interrupt flag */ + __IM uint32_t MR21IF : 1; /*!< [21..21] Match channel 21 interrupt flag */ + __IM uint32_t MR22IF : 1; /*!< [22..22] Match channel 22 interrupt flag */ + __IM uint32_t MR23IF : 1; /*!< [23..23] Match channel 23 interrupt flag */ + __IM uint32_t MR24IF : 1; /*!< [24..24] Match channel 24 interrupt flag */ + uint32_t : 7; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x000000A8) Offset:0xA8 CT16Bn Interrupt Clear Register */ + + struct { + __OM uint32_t MR0IC : 1; /*!< [0..0] MR0IF clear bit */ + __OM uint32_t MR1IC : 1; /*!< [1..1] MR1IF clear bit */ + __OM uint32_t MR2IC : 1; /*!< [2..2] MR2IF clear bit */ + __OM uint32_t MR3IC : 1; /*!< [3..3] MR3IF clear bit */ + __OM uint32_t MR4IC : 1; /*!< [4..4] MR4IF clear bit */ + __OM uint32_t MR5IC : 1; /*!< [5..5] MR5IF clear bit */ + __OM uint32_t MR6IC : 1; /*!< [6..6] MR6IF clear bit */ + __OM uint32_t MR7IC : 1; /*!< [7..7] MR7IF clear bit */ + __OM uint32_t MR8IC : 1; /*!< [8..8] MR8IF clear bit */ + __OM uint32_t MR9IC : 1; /*!< [9..9] MR9IF clear bit */ + __OM uint32_t MR10IC : 1; /*!< [10..10] MR10IF clear bit */ + __OM uint32_t MR11IC : 1; /*!< [11..11] MR11IF clear bit */ + __OM uint32_t MR12IC : 1; /*!< [12..12] MR12IF clear bit */ + __OM uint32_t MR13IC : 1; /*!< [13..13] MR13IF clear bit */ + __OM uint32_t MR14IC : 1; /*!< [14..14] MR14IF clear bit */ + __OM uint32_t MR15IC : 1; /*!< [15..15] MR15IF clear bit */ + __OM uint32_t MR16IC : 1; /*!< [16..16] MR16IF clear bit */ + __OM uint32_t MR17IC : 1; /*!< [17..17] MR17IF clear bit */ + __OM uint32_t MR18IC : 1; /*!< [18..18] MR18IF clear bit */ + __OM uint32_t MR19IC : 1; /*!< [19..19] MR19IF clear bit */ + __OM uint32_t MR20IC : 1; /*!< [20..20] MR20IF clear bit */ + __OM uint32_t MR21IC : 1; /*!< [21..21] MR21IF clear bit */ + __OM uint32_t MR22IC : 1; /*!< [22..22] MR22IF clear bit */ + __OM uint32_t MR23IC : 1; /*!< [23..23] MR23IF clear bit */ + __OM uint32_t MR24IC : 1; /*!< [24..24] MR24IF clear bit */ + uint32_t : 7; + } IC_b; + } ; +} SN_CT16B1_Type; /*!< Size = 172 (0xac) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (SN_WDT) + */ + +typedef struct { /*!< (@ 0x40010000) SN_WDT Structure */ + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000000) Offset:0x00 WDT Configuration Register */ + + struct { + __IOM uint32_t WDTEN : 1; /*!< [0..0] WDT enable */ + __IOM uint32_t WDTIE : 1; /*!< [1..1] WDT interrupt enable */ + __IOM uint32_t WDTINT : 1; /*!< [2..2] WDT interrupt flag */ + uint32_t : 13; + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } CFG_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000008) Offset:0x08 WDT Timer Constant Register */ + + struct { + __IOM uint32_t TC : 8; /*!< [7..0] Watchdog timer constant reload value */ + uint32_t : 8; + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } TC_b; + } ; + + union { + __OM uint32_t FEED; /*!< (@ 0x0000000C) Offset:0x0C WDT Feed Register */ + + struct { + __OM uint32_t FV : 16; /*!< [15..0] Watchdog feed value */ + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } FEED_b; + } ; +} SN_WDT_Type; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI0 (SN_SPI0) + */ + +typedef struct { /*!< (@ 0x4001C000) SN_SPI0 Structure */ + + union { + __IOM uint32_t CTRL0; /*!< (@ 0x00000000) Offset:0x00 SPI0 Control Register 0 */ + + struct { + __IOM uint32_t SPIEN : 1; /*!< [0..0] SPI enable */ + __IOM uint32_t LOOPBACK : 1; /*!< [1..1] Loopback mode enable */ + __IOM uint32_t SDODIS : 1; /*!< [2..2] Slave data out disable */ + __IOM uint32_t MS : 1; /*!< [3..3] Master/Slave selection */ + __IOM uint32_t FORMAT : 1; /*!< [4..4] Interface format */ + uint32_t : 1; + __OM uint32_t FRESET : 2; /*!< [7..6] SPI FSM and FIFO Reset */ + __IOM uint32_t DL : 4; /*!< [11..8] Data length = DL[3:0]+1 */ + __IOM uint32_t TXFIFOTH : 3; /*!< [14..12] TX FIFO Threshold level */ + __IOM uint32_t RXFIFOTH : 3; /*!< [17..15] RX FIFO Threshold level */ + __IOM uint32_t SELDIS : 1; /*!< [18..18] Auto-SEL disable bit */ + uint32_t : 13; + } CTRL0_b; + } ; + + union { + __IOM uint32_t CTRL1; /*!< (@ 0x00000004) Offset:0x04 SPI0 Control Register 1 */ + + struct { + __IOM uint32_t MLSB : 1; /*!< [0..0] MSB/LSB seletion */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock priority selection */ + __IOM uint32_t CPHA : 1; /*!< [2..2] Clock phase of edge sampling */ + uint32_t : 29; + } CTRL1_b; + } ; + + union { + __IOM uint32_t CLKDIV; /*!< (@ 0x00000008) Offset:0x08 SPI0 Clock Divider Register */ + + struct { + __IOM uint32_t DIV : 8; /*!< [7..0] SPI0 SCK */ + uint32_t : 24; + } CLKDIV_b; + } ; + + union { + __IM uint32_t STAT; /*!< (@ 0x0000000C) Offset:0x0C SPI0 Status Register */ + + struct { + __IM uint32_t TX_EMPTY : 1; /*!< [0..0] TX FIFO empty flag */ + __IM uint32_t TX_FULL : 1; /*!< [1..1] TX FIFO full flag */ + __IM uint32_t RX_EMPTY : 1; /*!< [2..2] RX FIFO empty flag */ + __IM uint32_t RX_FULL : 1; /*!< [3..3] RX FIFO full flag */ + __IM uint32_t BUSY : 1; /*!< [4..4] Busy flag */ + __IM uint32_t TXFIFOTHF : 1; /*!< [5..5] TX FIFO threshold flag */ + __IM uint32_t RXFIFOTHF : 1; /*!< [6..6] RX FIFO threshold flag */ + uint32_t : 25; + } STAT_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000010) Offset:0x10 SPI0 Interrupt Enable Register */ + + struct { + __IOM uint32_t RXOVFIE : 1; /*!< [0..0] RX FIFO overflow interrupt enable */ + __IOM uint32_t RXTOIE : 1; /*!< [1..1] RX time-out interrupt enable */ + __IOM uint32_t RXFIFOTHIE : 1; /*!< [2..2] RX FIFO threshold interrupt enable */ + __IOM uint32_t TXFIFOTHIE : 1; /*!< [3..3] TX FIFO threshold interrupt enable */ + uint32_t : 28; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x00000014) Offset:0x14 SPI0 Raw Interrupt Status Register */ + + struct { + __IM uint32_t RXOVFIF : 1; /*!< [0..0] RX FIFO overflow interrupt flag */ + __IM uint32_t RXTOIF : 1; /*!< [1..1] RX time-out interrupt flag */ + __IM uint32_t RXFIFOTHIF : 1; /*!< [2..2] RX FIFO threshold interrupt flag */ + __IM uint32_t TXFIFOTHIF : 1; /*!< [3..3] TX FIFO threshold interrupt flag */ + uint32_t : 28; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000018) Offset:0x18 SPI0 Interrupt Clear Register */ + + struct { + __OM uint32_t RXOVFIC : 1; /*!< [0..0] RX FIFO overflow flag clear */ + __OM uint32_t RXTOIC : 1; /*!< [1..1] RX time-out interrupt flag clear */ + __OM uint32_t RXFIFOTHIC : 1; /*!< [2..2] RX Interrupt flag Clear */ + __OM uint32_t TXFIFOTHIC : 1; /*!< [3..3] TX Interrupt flag Clear */ + uint32_t : 28; + } IC_b; + } ; + + union { + __IOM uint32_t DATA; /*!< (@ 0x0000001C) Offset:0x1C SPI0 Data Register */ + + struct { + __IOM uint32_t Data : 16; /*!< [15..0] Data */ + uint32_t : 16; + } DATA_b; + } ; + + union { + __IOM uint32_t DFDLY; /*!< (@ 0x00000020) Offset:0x20 SPI0 Data Fetch Register */ + + struct { + __IOM uint32_t DFETCH_EN : 1; /*!< [0..0] SPI0 data fetch control bit */ + uint32_t : 31; + } DFDLY_b; + } ; +} SN_SPI0_Type; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_I2C0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C0 (SN_I2C0) + */ + +typedef struct { /*!< (@ 0x40018000) SN_I2C0 Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 I2Cn Control Register */ + + struct { + uint32_t : 1; + __IOM uint32_t NACK : 1; /*!< [1..1] NACK assert flag */ + __IOM uint32_t ACK : 1; /*!< [2..2] ACK assert flag */ + uint32_t : 1; + __IOM uint32_t STO : 1; /*!< [4..4] STOP assert flag */ + __IOM uint32_t STA : 1; /*!< [5..5] START assert flag */ + uint32_t : 1; + __IOM uint32_t I2CMODE : 1; /*!< [7..7] I2C mode */ + __IOM uint32_t I2CEN : 1; /*!< [8..8] I2Cn interface enable */ + uint32_t : 23; + } CTRL_b; + } ; + + union { + __IOM uint32_t STAT; /*!< (@ 0x00000004) Offset:0x04 I2Cn Status Register */ + + struct { + __IM uint32_t RX_DN : 1; /*!< [0..0] RX done status */ + __IM uint32_t ACK_STAT : 1; /*!< [1..1] ACK done status */ + __IM uint32_t NACK_STAT : 1; /*!< [2..2] NACK done status */ + __IM uint32_t STOP_DN : 1; /*!< [3..3] STOP done status */ + __IM uint32_t START_DN : 1; /*!< [4..4] START done status */ + __IM uint32_t MST : 1; /*!< [5..5] I2C master/slave status */ + __IM uint32_t SLV_RX_HIT : 1; /*!< [6..6] Slave RX address hit flag */ + __IM uint32_t SLV_TX_HIT : 1; /*!< [7..7] Slave TX address hit flag */ + __IM uint32_t LOST_ARB : 1; /*!< [8..8] Lost arbitration status */ + __IM uint32_t TIMEOUT : 1; /*!< [9..9] Time-out status */ + uint32_t : 5; + __IOM uint32_t I2CIF : 1; /*!< [15..15] I2C interrupt flag */ + uint32_t : 16; + } STAT_b; + } ; + + union { + __IOM uint32_t TXDATA; /*!< (@ 0x00000008) Offset:0x08 I2Cn TX Data Register */ + + struct { + __IOM uint32_t Data : 8; /*!< [7..0] TX Data */ + uint32_t : 24; + } TXDATA_b; + } ; + + union { + __IM uint32_t RXDATA; /*!< (@ 0x0000000C) Offset:0x0C I2Cn RX Data Register */ + + struct { + __IM uint32_t Data : 8; /*!< [7..0] RX Data received when RX_DN=1 */ + uint32_t : 24; + } RXDATA_b; + } ; + + union { + __IOM uint32_t SLVADDR0; /*!< (@ 0x00000010) Offset:0x10 I2Cn Slave Address 0 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 0 */ + uint32_t : 20; + __IOM uint32_t GCEN : 1; /*!< [30..30] General call address enable */ + __IOM uint32_t ADD_MODE : 1; /*!< [31..31] Slave address mode */ + } SLVADDR0_b; + } ; + + union { + __IOM uint32_t SLVADDR1; /*!< (@ 0x00000014) Offset:0x14 I2Cn Slave Address 1 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 1 */ + uint32_t : 22; + } SLVADDR1_b; + } ; + + union { + __IOM uint32_t SLVADDR2; /*!< (@ 0x00000018) Offset:0x18 I2Cn Slave Address 2 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 2 */ + uint32_t : 22; + } SLVADDR2_b; + } ; + + union { + __IOM uint32_t SLVADDR3; /*!< (@ 0x0000001C) Offset:0x1C I2Cn Slave Address 3 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 3 */ + uint32_t : 22; + } SLVADDR3_b; + } ; + + union { + __IOM uint32_t SCLHT; /*!< (@ 0x00000020) Offset:0x20 I2Cn SCL High Time Register */ + + struct { + __IOM uint32_t SCLH : 8; /*!< [7..0] SCLn High period time=(SCLHT+1)*I2Cn_PCLK cycle */ + uint32_t : 24; + } SCLHT_b; + } ; + + union { + __IOM uint32_t SCLLT; /*!< (@ 0x00000024) Offset:0x24 I2Cn SCL Low Time Register */ + + struct { + __IOM uint32_t SCLL : 8; /*!< [7..0] SCLn Low period time=(SCLLT+1)*I2Cn_PCLK cycle */ + uint32_t : 24; + } SCLLT_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t TOCTRL; /*!< (@ 0x0000002C) Offset:0x2C I2Cn Timeout Control Register */ + + struct { + __IOM uint32_t TO : 16; /*!< [15..0] Timeout period time = TO*I2Cn_PCLK cycle */ + uint32_t : 16; + } TOCTRL_b; + } ; +} SN_I2C0_Type; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART0 (SN_UART0) + */ + +typedef struct { /*!< (@ 0x40016000) SN_UART0 Structure */ + + union { + union { + __IM uint32_t RB; /*!< (@ 0x00000000) Offset:0x00 UARTn Receiver Buffer Register */ + + struct { + __IM uint32_t RB : 8; /*!< [7..0] The received byte in UART RX FIFO */ + uint32_t : 24; + } RB_b; + } ; + + union { + __OM uint32_t TH; /*!< (@ 0x00000000) Offset:0x00 UARTn Transmit Holding Register */ + + struct { + __OM uint32_t TH : 8; /*!< [7..0] The byte to be transmitted in UART TX FIFO when transmitter + is available */ + uint32_t : 24; + } TH_b; + } ; + + union { + __IOM uint32_t DLL; /*!< (@ 0x00000000) Offset:0x00 UARTn Divisor Latch LSB Register */ + + struct { + __IOM uint32_t DLL : 8; /*!< [7..0] DLL and DLM register determines the baud rate of UARTn */ + uint32_t : 24; + } DLL_b; + } ; + }; + + union { + union { + __IOM uint32_t DLM; /*!< (@ 0x00000004) Offset:0x04 UARTn Divisor Latch MSB Register */ + + struct { + __IOM uint32_t DLM : 8; /*!< [7..0] DLL and DLM register determines the baud rate of USARTn */ + uint32_t : 24; + } DLM_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000004) Offset:0x04 UARTn Interrupt Enable Register */ + + struct { + __IOM uint32_t RDAIE : 1; /*!< [0..0] RDA interrupt enable */ + __IOM uint32_t THREIE : 1; /*!< [1..1] THRE interrupt enable */ + __IOM uint32_t RLSIE : 1; /*!< [2..2] RLS interrupt enable */ + uint32_t : 1; + __IOM uint32_t TEMTIE : 1; /*!< [4..4] TEMT interrupt enable */ + uint32_t : 3; + __IOM uint32_t ABEOIE : 1; /*!< [8..8] ABE0 interrupt enable */ + __IOM uint32_t ABTOIE : 1; /*!< [9..9] ABT0 interrupt enable */ + uint32_t : 22; + } IE_b; + } ; + }; + + union { + union { + __IM uint32_t II; /*!< (@ 0x00000008) Offset:0x08 UARTn Interrupt Identification Register */ + + struct { + __IM uint32_t INTSTATUS : 1; /*!< [0..0] Interrupt status */ + __IM uint32_t INTID : 3; /*!< [3..1] Interrupt ID of RX FIFO */ + uint32_t : 2; + __IM uint32_t FIFOEN : 2; /*!< [7..6] Equal to FIFOEN bits in USARTn_FIFOCTRL register */ + __IM uint32_t ABEOIF : 1; /*!< [8..8] ABEO interrupt flag */ + __IM uint32_t ABTOIF : 1; /*!< [9..9] ABTO interrupt flag */ + uint32_t : 22; + } II_b; + } ; + + union { + __OM uint32_t FIFOCTRL; /*!< (@ 0x00000008) Offset:0x08 UARTn FIFO Control Register */ + + struct { + __OM uint32_t FIFOEN : 1; /*!< [0..0] FIFO enable */ + uint32_t : 5; + __OM uint32_t RXTL : 2; /*!< [7..6] RX trigger level */ + uint32_t : 24; + } FIFOCTRL_b; + } ; + }; + + union { + __IOM uint32_t LC; /*!< (@ 0x0000000C) Offset:0x0C UARTn Line Control Register */ + + struct { + __IOM uint32_t WLS : 2; /*!< [1..0] Word length selection */ + __IOM uint32_t SBS : 1; /*!< [2..2] Stop bit selection */ + __IOM uint32_t PE : 1; /*!< [3..3] Parity enable */ + __IOM uint32_t PS : 2; /*!< [5..4] Parity selection */ + __IOM uint32_t BC : 1; /*!< [6..6] Break control */ + __IOM uint32_t DLAB : 1; /*!< [7..7] Divisor Latch access */ + uint32_t : 24; + } LC_b; + } ; + __IM uint32_t RESERVED; + + union { + __IM uint32_t LS; /*!< (@ 0x00000014) Offset:0x14 UARTn Line Status Register */ + + struct { + __IM uint32_t RDR : 1; /*!< [0..0] Receiver data ready flag */ + __IM uint32_t OE : 1; /*!< [1..1] Overrun error flag */ + __IM uint32_t PE : 1; /*!< [2..2] Parity error flag */ + __IM uint32_t FE : 1; /*!< [3..3] Framing error flag */ + __IM uint32_t BI : 1; /*!< [4..4] Break interrupt flag */ + __IM uint32_t THRE : 1; /*!< [5..5] THR empty flag */ + __IM uint32_t TEMT : 1; /*!< [6..6] Transmitter empty flag */ + __IM uint32_t RXFE : 1; /*!< [7..7] Receiver FIFO error flag */ + uint32_t : 24; + } LS_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t SP; /*!< (@ 0x0000001C) Offset:0x1C UARTn Scratch Pad Register */ + + struct { + __IOM uint32_t PAD : 8; /*!< [7..0] Pad informaton */ + uint32_t : 24; + } SP_b; + } ; + + union { + __IOM uint32_t ABCTRL; /*!< (@ 0x00000020) Offset:0x20 UARTn Auto-baud Control Register */ + + struct { + __IOM uint32_t START : 1; /*!< [0..0] Auto-baud run bit */ + __IOM uint32_t MODE : 1; /*!< [1..1] Auto-baud mode selection */ + __IOM uint32_t AUTORESTART : 1; /*!< [2..2] Restart mode selection */ + uint32_t : 5; + __OM uint32_t ABEOIFC : 1; /*!< [8..8] Clear ABEOIF flag */ + __OM uint32_t ABTOIFC : 1; /*!< [9..9] Clear ABTOIF flag */ + uint32_t : 22; + } ABCTRL_b; + } ; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t FD; /*!< (@ 0x00000028) Offset:0x28 UARTn Fractional Divider Register */ + + struct { + __IOM uint32_t DIVADDVAL : 4; /*!< [3..0] Baud rate generation prescaler divisor value */ + __IOM uint32_t MULVAL : 4; /*!< [7..4] Baud rate generation prescaler multiplier value */ + __IOM uint32_t OVER8 : 1; /*!< [8..8] Oversampling value */ + uint32_t : 23; + } FD_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000030) Offset:0x30 UARTn Control Register */ + + struct { + __IOM uint32_t UARTEN : 1; /*!< [0..0] USART enable */ + __IOM uint32_t MODE : 3; /*!< [3..1] UART mode */ + uint32_t : 2; + __IOM uint32_t RXEN : 1; /*!< [6..6] RX enable */ + __IOM uint32_t TXEN : 1; /*!< [7..7] TX enable */ + uint32_t : 24; + } CTRL_b; + } ; + + union { + __IOM uint32_t HDEN; /*!< (@ 0x00000034) Offset:0x34 UARTn Control Register */ + + struct { + __IOM uint32_t HDEN : 1; /*!< [0..0] Half-duplex mode enable */ + uint32_t : 31; + } HDEN_b; + } ; +} SN_UART0_Type; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_UART1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART1 (SN_UART1) + */ + +typedef struct { /*!< (@ 0x40014000) SN_UART1 Structure */ + + union { + union { + __IM uint32_t RB; /*!< (@ 0x00000000) Offset:0x00 UARTn Receiver Buffer Register */ + + struct { + __IM uint32_t RB : 8; /*!< [7..0] The received byte in UART RX FIFO */ + uint32_t : 24; + } RB_b; + } ; + + union { + __OM uint32_t TH; /*!< (@ 0x00000000) Offset:0x00 UARTn Transmit Holding Register */ + + struct { + __OM uint32_t TH : 8; /*!< [7..0] The byte to be transmitted in UART TX FIFO when transmitter + is available */ + uint32_t : 24; + } TH_b; + } ; + + union { + __IOM uint32_t DLL; /*!< (@ 0x00000000) Offset:0x00 UARTn Divisor Latch LSB Register */ + + struct { + __IOM uint32_t DLL : 8; /*!< [7..0] DLL and DLM register determines the baud rate of UARTn */ + uint32_t : 24; + } DLL_b; + } ; + }; + + union { + union { + __IOM uint32_t DLM; /*!< (@ 0x00000004) Offset:0x04 UARTn Divisor Latch MSB Register */ + + struct { + __IOM uint32_t DLM : 8; /*!< [7..0] DLL and DLM register determines the baud rate of USARTn */ + uint32_t : 24; + } DLM_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000004) Offset:0x04 UARTn Interrupt Enable Register */ + + struct { + __IOM uint32_t RDAIE : 1; /*!< [0..0] RDA interrupt enable */ + __IOM uint32_t THREIE : 1; /*!< [1..1] THRE interrupt enable */ + __IOM uint32_t RLSIE : 1; /*!< [2..2] RLS interrupt enable */ + uint32_t : 1; + __IOM uint32_t TEMTIE : 1; /*!< [4..4] TEMT interrupt enable */ + uint32_t : 3; + __IOM uint32_t ABEOIE : 1; /*!< [8..8] ABE0 interrupt enable */ + __IOM uint32_t ABTOIE : 1; /*!< [9..9] ABT0 interrupt enable */ + uint32_t : 22; + } IE_b; + } ; + }; + + union { + union { + __IM uint32_t II; /*!< (@ 0x00000008) Offset:0x08 UARTn Interrupt Identification Register */ + + struct { + __IM uint32_t INTSTATUS : 1; /*!< [0..0] Interrupt status */ + __IM uint32_t INTID : 3; /*!< [3..1] Interrupt ID of RX FIFO */ + uint32_t : 2; + __IM uint32_t FIFOEN : 2; /*!< [7..6] Equal to FIFOEN bits in USARTn_FIFOCTRL register */ + __IM uint32_t ABEOIF : 1; /*!< [8..8] ABEO interrupt flag */ + __IM uint32_t ABTOIF : 1; /*!< [9..9] ABTO interrupt flag */ + uint32_t : 22; + } II_b; + } ; + + union { + __OM uint32_t FIFOCTRL; /*!< (@ 0x00000008) Offset:0x08 UARTn FIFO Control Register */ + + struct { + __OM uint32_t FIFOEN : 1; /*!< [0..0] FIFO enable */ + uint32_t : 5; + __OM uint32_t RXTL : 2; /*!< [7..6] RX trigger level */ + uint32_t : 24; + } FIFOCTRL_b; + } ; + }; + + union { + __IOM uint32_t LC; /*!< (@ 0x0000000C) Offset:0x0C UARTn Line Control Register */ + + struct { + __IOM uint32_t WLS : 2; /*!< [1..0] Word length selection */ + __IOM uint32_t SBS : 1; /*!< [2..2] Stop bit selection */ + __IOM uint32_t PE : 1; /*!< [3..3] Parity enable */ + __IOM uint32_t PS : 2; /*!< [5..4] Parity selection */ + __IOM uint32_t BC : 1; /*!< [6..6] Break control */ + __IOM uint32_t DLAB : 1; /*!< [7..7] Divisor Latch access */ + uint32_t : 24; + } LC_b; + } ; + __IM uint32_t RESERVED; + + union { + __IM uint32_t LS; /*!< (@ 0x00000014) Offset:0x14 UARTn Line Status Register */ + + struct { + __IM uint32_t RDR : 1; /*!< [0..0] Receiver data ready flag */ + __IM uint32_t OE : 1; /*!< [1..1] Overrun error flag */ + __IM uint32_t PE : 1; /*!< [2..2] Parity error flag */ + __IM uint32_t FE : 1; /*!< [3..3] Framing error flag */ + __IM uint32_t BI : 1; /*!< [4..4] Break interrupt flag */ + __IM uint32_t THRE : 1; /*!< [5..5] THR empty flag */ + __IM uint32_t TEMT : 1; /*!< [6..6] Transmitter empty flag */ + __IM uint32_t RXFE : 1; /*!< [7..7] Receiver FIFO error flag */ + uint32_t : 24; + } LS_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t SP; /*!< (@ 0x0000001C) Offset:0x1C UARTn Scratch Pad Register */ + + struct { + __IOM uint32_t PAD : 8; /*!< [7..0] Pad informaton */ + uint32_t : 24; + } SP_b; + } ; + + union { + __IOM uint32_t ABCTRL; /*!< (@ 0x00000020) Offset:0x20 UARTn Auto-baud Control Register */ + + struct { + __IOM uint32_t START : 1; /*!< [0..0] Auto-baud run bit */ + __IOM uint32_t MODE : 1; /*!< [1..1] Auto-baud mode selection */ + __IOM uint32_t AUTORESTART : 1; /*!< [2..2] Restart mode selection */ + uint32_t : 5; + __OM uint32_t ABEOIFC : 1; /*!< [8..8] Clear ABEOIF flag */ + __OM uint32_t ABTOIFC : 1; /*!< [9..9] Clear ABTOIF flag */ + uint32_t : 22; + } ABCTRL_b; + } ; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t FD; /*!< (@ 0x00000028) Offset:0x28 UARTn Fractional Divider Register */ + + struct { + __IOM uint32_t DIVADDVAL : 4; /*!< [3..0] Baud rate generation prescaler divisor value */ + __IOM uint32_t MULVAL : 4; /*!< [7..4] Baud rate generation prescaler multiplier value */ + __IOM uint32_t OVER8 : 1; /*!< [8..8] Oversampling value */ + uint32_t : 23; + } FD_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000030) Offset:0x30 UARTn Control Register */ + + struct { + __IOM uint32_t UARTEN : 1; /*!< [0..0] USART enable */ + __IOM uint32_t MODE : 3; /*!< [3..1] UART mode */ + uint32_t : 2; + __IOM uint32_t RXEN : 1; /*!< [6..6] RX enable */ + __IOM uint32_t TXEN : 1; /*!< [7..7] TX enable */ + uint32_t : 24; + } CTRL_b; + } ; + + union { + __IOM uint32_t HDEN; /*!< (@ 0x00000034) Offset:0x34 UARTn Control Register */ + + struct { + __IOM uint32_t HDEN : 1; /*!< [0..0] Half-duplex mode enable */ + uint32_t : 31; + } HDEN_b; + } ; +} SN_UART1_Type; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_UART2 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART2 (SN_UART2) + */ + +typedef struct { /*!< (@ 0x40012000) SN_UART2 Structure */ + + union { + union { + __IM uint32_t RB; /*!< (@ 0x00000000) Offset:0x00 UARTn Receiver Buffer Register */ + + struct { + __IM uint32_t RB : 8; /*!< [7..0] The received byte in UART RX FIFO */ + uint32_t : 24; + } RB_b; + } ; + + union { + __OM uint32_t TH; /*!< (@ 0x00000000) Offset:0x00 UARTn Transmit Holding Register */ + + struct { + __OM uint32_t TH : 8; /*!< [7..0] The byte to be transmitted in UART TX FIFO when transmitter + is available */ + uint32_t : 24; + } TH_b; + } ; + + union { + __IOM uint32_t DLL; /*!< (@ 0x00000000) Offset:0x00 UARTn Divisor Latch LSB Register */ + + struct { + __IOM uint32_t DLL : 8; /*!< [7..0] DLL and DLM register determines the baud rate of UARTn */ + uint32_t : 24; + } DLL_b; + } ; + }; + + union { + union { + __IOM uint32_t DLM; /*!< (@ 0x00000004) Offset:0x04 UARTn Divisor Latch MSB Register */ + + struct { + __IOM uint32_t DLM : 8; /*!< [7..0] DLL and DLM register determines the baud rate of USARTn */ + uint32_t : 24; + } DLM_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000004) Offset:0x04 UARTn Interrupt Enable Register */ + + struct { + __IOM uint32_t RDAIE : 1; /*!< [0..0] RDA interrupt enable */ + __IOM uint32_t THREIE : 1; /*!< [1..1] THRE interrupt enable */ + __IOM uint32_t RLSIE : 1; /*!< [2..2] RLS interrupt enable */ + uint32_t : 1; + __IOM uint32_t TEMTIE : 1; /*!< [4..4] TEMT interrupt enable */ + uint32_t : 3; + __IOM uint32_t ABEOIE : 1; /*!< [8..8] ABE0 interrupt enable */ + __IOM uint32_t ABTOIE : 1; /*!< [9..9] ABT0 interrupt enable */ + uint32_t : 22; + } IE_b; + } ; + }; + + union { + union { + __IM uint32_t II; /*!< (@ 0x00000008) Offset:0x08 UARTn Interrupt Identification Register */ + + struct { + __IM uint32_t INTSTATUS : 1; /*!< [0..0] Interrupt status */ + __IM uint32_t INTID : 3; /*!< [3..1] Interrupt ID of RX FIFO */ + uint32_t : 2; + __IM uint32_t FIFOEN : 2; /*!< [7..6] Equal to FIFOEN bits in USARTn_FIFOCTRL register */ + __IM uint32_t ABEOIF : 1; /*!< [8..8] ABEO interrupt flag */ + __IM uint32_t ABTOIF : 1; /*!< [9..9] ABTO interrupt flag */ + uint32_t : 22; + } II_b; + } ; + + union { + __OM uint32_t FIFOCTRL; /*!< (@ 0x00000008) Offset:0x08 UARTn FIFO Control Register */ + + struct { + __OM uint32_t FIFOEN : 1; /*!< [0..0] FIFO enable */ + uint32_t : 5; + __OM uint32_t RXTL : 2; /*!< [7..6] RX trigger level */ + uint32_t : 24; + } FIFOCTRL_b; + } ; + }; + + union { + __IOM uint32_t LC; /*!< (@ 0x0000000C) Offset:0x0C UARTn Line Control Register */ + + struct { + __IOM uint32_t WLS : 2; /*!< [1..0] Word length selection */ + __IOM uint32_t SBS : 1; /*!< [2..2] Stop bit selection */ + __IOM uint32_t PE : 1; /*!< [3..3] Parity enable */ + __IOM uint32_t PS : 2; /*!< [5..4] Parity selection */ + __IOM uint32_t BC : 1; /*!< [6..6] Break control */ + __IOM uint32_t DLAB : 1; /*!< [7..7] Divisor Latch access */ + uint32_t : 24; + } LC_b; + } ; + __IM uint32_t RESERVED; + + union { + __IM uint32_t LS; /*!< (@ 0x00000014) Offset:0x14 UARTn Line Status Register */ + + struct { + __IM uint32_t RDR : 1; /*!< [0..0] Receiver data ready flag */ + __IM uint32_t OE : 1; /*!< [1..1] Overrun error flag */ + __IM uint32_t PE : 1; /*!< [2..2] Parity error flag */ + __IM uint32_t FE : 1; /*!< [3..3] Framing error flag */ + __IM uint32_t BI : 1; /*!< [4..4] Break interrupt flag */ + __IM uint32_t THRE : 1; /*!< [5..5] THR empty flag */ + __IM uint32_t TEMT : 1; /*!< [6..6] Transmitter empty flag */ + __IM uint32_t RXFE : 1; /*!< [7..7] Receiver FIFO error flag */ + uint32_t : 24; + } LS_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t SP; /*!< (@ 0x0000001C) Offset:0x1C UARTn Scratch Pad Register */ + + struct { + __IOM uint32_t PAD : 8; /*!< [7..0] Pad informaton */ + uint32_t : 24; + } SP_b; + } ; + + union { + __IOM uint32_t ABCTRL; /*!< (@ 0x00000020) Offset:0x20 UARTn Auto-baud Control Register */ + + struct { + __IOM uint32_t START : 1; /*!< [0..0] Auto-baud run bit */ + __IOM uint32_t MODE : 1; /*!< [1..1] Auto-baud mode selection */ + __IOM uint32_t AUTORESTART : 1; /*!< [2..2] Restart mode selection */ + uint32_t : 5; + __OM uint32_t ABEOIFC : 1; /*!< [8..8] Clear ABEOIF flag */ + __OM uint32_t ABTOIFC : 1; /*!< [9..9] Clear ABTOIF flag */ + uint32_t : 22; + } ABCTRL_b; + } ; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t FD; /*!< (@ 0x00000028) Offset:0x28 UARTn Fractional Divider Register */ + + struct { + __IOM uint32_t DIVADDVAL : 4; /*!< [3..0] Baud rate generation prescaler divisor value */ + __IOM uint32_t MULVAL : 4; /*!< [7..4] Baud rate generation prescaler multiplier value */ + __IOM uint32_t OVER8 : 1; /*!< [8..8] Oversampling value */ + uint32_t : 23; + } FD_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000030) Offset:0x30 UARTn Control Register */ + + struct { + __IOM uint32_t UARTEN : 1; /*!< [0..0] USART enable */ + __IOM uint32_t MODE : 3; /*!< [3..1] UART mode */ + uint32_t : 2; + __IOM uint32_t RXEN : 1; /*!< [6..6] RX enable */ + __IOM uint32_t TXEN : 1; /*!< [7..7] TX enable */ + uint32_t : 24; + } CTRL_b; + } ; + + union { + __IOM uint32_t HDEN; /*!< (@ 0x00000034) Offset:0x34 UARTn Control Register */ + + struct { + __IOM uint32_t HDEN : 1; /*!< [0..0] Half-duplex mode enable */ + uint32_t : 31; + } HDEN_b; + } ; +} SN_UART2_Type; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_USB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal Serial Bus Full Speed Device Interface (USB) (SN_USB) + */ + +typedef struct { /*!< (@ 0x4005C000) SN_USB Structure */ + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000000) Offset:0x00 USB Interrupt Enable Register */ + + struct { + __IOM uint32_t EP1_NAK_EN : 1; /*!< [0..0] EP1 NAK Interrupt Enable */ + __IOM uint32_t EP2_NAK_EN : 1; /*!< [1..1] EP2 NAK Interrupt Enable */ + __IOM uint32_t EP3_NAK_EN : 1; /*!< [2..2] EP3 NAK Interrupt Enable */ + __IOM uint32_t EP4_NAK_EN : 1; /*!< [3..3] EP4 NAK Interrupt Enable */ + __IOM uint32_t EPN_ACK_EN : 1; /*!< [4..4] EPN ACK Interrupt Enable */ + uint32_t : 23; + __IOM uint32_t BUSWK_IE : 1; /*!< [28..28] USB Bus Wake Up Interrupt Enable */ + __IOM uint32_t USB_IE : 1; /*!< [29..29] USB Event Interrupt Enable */ + __IOM uint32_t USB_SOF_IE : 1; /*!< [30..30] USB SOF Interrupt Enable */ + __IOM uint32_t BUS_IE : 1; /*!< [31..31] Bus Event Interrupt Enable */ + } INTEN_b; + } ; + + union { + __IM uint32_t INSTS; /*!< (@ 0x00000004) Offset:0x04 USB Interrupt Event Status Register */ + + struct { + __IM uint32_t EP1_NAK : 1; /*!< [0..0] Endpoint 1 NAK transaction flag */ + __IM uint32_t EP2_NAK : 1; /*!< [1..1] Endpoint 2 NAK transaction flag */ + __IM uint32_t EP3_NAK : 1; /*!< [2..2] Endpoint 3 NAK transaction flag */ + __IM uint32_t EP4_NAK : 1; /*!< [3..3] Endpoint 4 NAK transaction flag */ + uint32_t : 4; + __IM uint32_t EP1_ACK : 1; /*!< [8..8] Endpoint 1 ACK transaction flag */ + __IM uint32_t EP2_ACK : 1; /*!< [9..9] Endpoint 2 ACK transaction flag */ + __IM uint32_t EP3_ACK : 1; /*!< [10..10] Endpoint 3 ACK transaction flag */ + __IM uint32_t EP4_ACK : 1; /*!< [11..11] Endpoint 4 ACK transaction flag */ + uint32_t : 5; + __IM uint32_t ERR_TIMEOUT : 1; /*!< [17..17] Timeout Status */ + __IM uint32_t ERR_SETUP : 1; /*!< [18..18] Wrong Setup data received */ + __IM uint32_t EP0_OUT_STALL : 1; /*!< [19..19] EP0 OUT STALL transaction */ + __IM uint32_t EP0_IN_STALL : 1; /*!< [20..20] EP0 IN STALL Transaction is completed */ + __IM uint32_t EP0_OUT : 1; /*!< [21..21] EP0 OUT ACK Transaction Flag */ + __IM uint32_t EP0_IN : 1; /*!< [22..22] EP0 IN ACK Transaction Flag */ + __IM uint32_t EP0_SETUP : 1; /*!< [23..23] EP0 Setup Transaction Flag */ + __IM uint32_t EP0_PRESETUP : 1; /*!< [24..24] EP0 Setup Token Packet Flag */ + __IM uint32_t BUS_WAKEUP : 1; /*!< [25..25] Bus Wakeup Flag */ + __IM uint32_t USB_SOF : 1; /*!< [26..26] USB SOF packet received flag */ + uint32_t : 2; + __IM uint32_t BUS_RESUME : 1; /*!< [29..29] USB Bus Resume signal flag */ + __IM uint32_t BUS_SUSPEND : 1; /*!< [30..30] USB Bus Suspend signal flag */ + __IM uint32_t BUS_RESET : 1; /*!< [31..31] USB Bus Reset signal flag */ + } INSTS_b; + } ; + + union { + __OM uint32_t INSTSC; /*!< (@ 0x00000008) Offset:0x08 USB Interrupt Event Status Clear + Register */ + + struct { + __OM uint32_t EP1_NAKC : 1; /*!< [0..0] EP1 NAK clear bit */ + __OM uint32_t EP2_NAKC : 1; /*!< [1..1] EP2 NAK clear bit */ + __OM uint32_t EP3_NAKC : 1; /*!< [2..2] EP3 NAK clear bit */ + __OM uint32_t EP4_NAKC : 1; /*!< [3..3] EP4 NAK clear bit */ + uint32_t : 4; + __OM uint32_t EP1_ACKC : 1; /*!< [8..8] EP1 ACK clear bit */ + __OM uint32_t EP2_ACKC : 1; /*!< [9..9] EP2 ACK clear bit */ + __OM uint32_t EP3_ACKC : 1; /*!< [10..10] EP3 ACK clear bit */ + __OM uint32_t EP4_ACKC : 1; /*!< [11..11] EP4 ACK clear bit */ + uint32_t : 5; + __OM uint32_t ERR_TIMEOUTC : 1; /*!< [17..17] Timeout Error clear bit */ + __OM uint32_t ERR_SETUPC : 1; /*!< [18..18] Error Setup clear bit */ + __OM uint32_t EP0_OUT_STALLC : 1; /*!< [19..19] EP0 OUT STALL clear bit */ + __OM uint32_t EP0_IN_STALLC : 1; /*!< [20..20] EP0 IN STALL clear bit */ + __OM uint32_t EP0_OUTC : 1; /*!< [21..21] EP0 OUT clear bit */ + __OM uint32_t EP0_INC : 1; /*!< [22..22] EP0 IN clear bit */ + __OM uint32_t EP0_SETUPC : 1; /*!< [23..23] EP0 SETUP clear bit */ + __OM uint32_t EP0_PRESETUPC : 1; /*!< [24..24] EP0 PRESETUP clear bit */ + __OM uint32_t BUS_WAKEUPC : 1; /*!< [25..25] Bus Wakeup clear bit */ + __OM uint32_t USB_SOFC : 1; /*!< [26..26] USB SOF clear bit */ + uint32_t : 2; + __OM uint32_t BUS_RESUMEC : 1; /*!< [29..29] USB Bus Resume clear bit */ + uint32_t : 1; + __OM uint32_t BUS_RESETC : 1; /*!< [31..31] USB Bus Reset clear bit */ + } INSTSC_b; + } ; + + union { + __IOM uint32_t ADDR; /*!< (@ 0x0000000C) Offset:0x0C USB Device Address Register */ + + struct { + __IOM uint32_t UADDR : 7; /*!< [6..0] USB device's address */ + uint32_t : 25; + } ADDR_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000010) Offset:0x10 USB Configuration Register */ + + struct { + __IOM uint32_t EP1_DIR : 1; /*!< [0..0] Endpoint 1 IN/OUT direction setting */ + __IOM uint32_t EP2_DIR : 1; /*!< [1..1] Endpoint 2 IN/OUT direction setting */ + __IOM uint32_t EP3_DIR : 1; /*!< [2..2] Endpoint 3 IN/OUT direction setting */ + __IOM uint32_t EP4_DIR : 1; /*!< [3..3] Endpoint 4 IN/OUT direction setting */ + uint32_t : 22; + __IOM uint32_t DIS_PDEN : 1; /*!< [26..26] Enable internal D+ and D- 175k pull-down resistor */ + __IOM uint32_t ESD_EN : 1; /*!< [27..27] Enable USB anti-ESD protection */ + __IOM uint32_t SIE_EN : 1; /*!< [28..28] USB Serial Interface Engine Enable */ + __IOM uint32_t DPPU_EN : 1; /*!< [29..29] Enable internal D+ 1.5k pull-up resistor */ + __IOM uint32_t PHY_EN : 1; /*!< [30..30] PHY Transceiver Function Enable */ + __IOM uint32_t VREG33_EN : 1; /*!< [31..31] Enable the internal VREG33 ouput */ + } CFG_b; + } ; + + union { + __IOM uint32_t SGCTL; /*!< (@ 0x00000014) Offset:0x14 USB Signal Control Register */ + + struct { + __IOM uint32_t BUS_DN : 1; /*!< [0..0] USB D- state */ + __IOM uint32_t BUS_DP : 1; /*!< [1..1] USB DP state */ + __IOM uint32_t BUS_DRVEN : 1; /*!< [2..2] Enable to drive USB bus */ + uint32_t : 29; + } SGCTL_b; + } ; + + union { + __IOM uint32_t EP0CTL; /*!< (@ 0x00000018) Offset:0x18 USB Endpoint 0 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 20; + __IOM uint32_t OUT_STALL_EN : 1; /*!< [27..27] Enable EP0 OUT STALL handshake */ + __IOM uint32_t IN_STALL_EN : 1; /*!< [28..28] Enable EP0 IN STALL handshake */ + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Enable Endpoint 0 Function */ + } EP0CTL_b; + } ; + + union { + __IOM uint32_t EP1CTL; /*!< (@ 0x0000001C) Offset:0x1C USB Endpoint 1 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 1 Function enable bit */ + } EP1CTL_b; + } ; + + union { + __IOM uint32_t EP2CTL; /*!< (@ 0x00000020) Offset:0x20 USB Endpoint 2 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 2 Function enable bit */ + } EP2CTL_b; + } ; + + union { + __IOM uint32_t EP3CTL; /*!< (@ 0x00000024) Offset:0x24 USB Endpoint 3 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 3 Function enable bit */ + } EP3CTL_b; + } ; + + union { + __IOM uint32_t EP4CTL; /*!< (@ 0x00000028) Offset:0x28 USB Endpoint 4 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 4 Function enable bit */ + } EP4CTL_b; + } ; + __IM uint32_t RESERVED[4]; + + union { + __IOM uint32_t EPTOGGLE; /*!< (@ 0x0000003C) Offset:0x3C USB Endpoint Data Toggle Register */ + + struct { + __IOM uint32_t ENDP1_DATA01 : 1; /*!< [0..0] Endpoint 1 data toggle bit */ + __IOM uint32_t ENDP2_DATA01 : 1; /*!< [1..1] Endpoint 2 data toggle bit */ + __IOM uint32_t ENDP3_DATA01 : 1; /*!< [2..2] Endpoint 3 data toggle bit */ + __IOM uint32_t ENDP4_DATA01 : 1; /*!< [3..3] Endpoint 4 data toggle bit */ + uint32_t : 28; + } EPTOGGLE_b; + } ; + __IM uint32_t RESERVED1[2]; + + union { + __IOM uint32_t EP1BUFOS; /*!< (@ 0x00000048) Offset:0x48 USB Endpoint 1 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 6; /*!< [7..2] The offset address for endpoint data buffer */ + uint32_t : 24; + } EP1BUFOS_b; + } ; + + union { + __IOM uint32_t EP2BUFOS; /*!< (@ 0x0000004C) Offset:0x4C USB Endpoint 2 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 6; /*!< [7..2] The offset address for endpoint data buffer */ + uint32_t : 24; + } EP2BUFOS_b; + } ; + + union { + __IOM uint32_t EP3BUFOS; /*!< (@ 0x00000050) Offset:0x50 USB Endpoint 3 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 6; /*!< [7..2] The offset address for endpoint data buffer */ + uint32_t : 24; + } EP3BUFOS_b; + } ; + + union { + __IOM uint32_t EP4BUFOS; /*!< (@ 0x00000054) Offset:0x54 USB Endpoint 4 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 6; /*!< [7..2] The offset address for endpoint data buffer */ + uint32_t : 24; + } EP4BUFOS_b; + } ; + __IM uint32_t RESERVED2[2]; + + union { + __IM uint32_t FRMNO; /*!< (@ 0x00000060) Offset:0x60 USB Frame Number Register */ + + struct { + __IM uint32_t FRAME_NO : 11; /*!< [10..0] The 11-bit frame number of the SOF packet */ + uint32_t : 21; + } FRMNO_b; + } ; + + union { + __IOM uint32_t PHYPRM; /*!< (@ 0x00000064) Offset:0x64 USB PHY Parameter Register */ + + struct { + __IOM uint32_t PHY_PARAM : 6; /*!< [5..0] USB PHY parameter */ + uint32_t : 26; + } PHYPRM_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t PHYPRM2; /*!< (@ 0x0000006C) Offset:0x6C USB PHY Parameter 2 Register */ + + struct { + __IOM uint32_t PHY_PS : 15; /*!< [14..0] USB PHY parameter 2 */ + uint32_t : 17; + } PHYPRM2_b; + } ; + + union { + __IOM uint32_t PS2CTL; /*!< (@ 0x00000070) Offset:0x70 PS/2 Control Register */ + + struct { + __IOM uint32_t SCKM : 1; /*!< [0..0] PS/2 SCK mode control bit */ + __IOM uint32_t SDAM : 1; /*!< [1..1] PS/2 SDA mode control bit */ + __IOM uint32_t SCK : 1; /*!< [2..2] PS/2 SCK data buffer */ + __IOM uint32_t SDA : 1; /*!< [3..3] PS/2 SDA data buffer */ + uint32_t : 27; + __IOM uint32_t PS2ENB : 1; /*!< [31..31] PS/2 internal 5kohm pull-up resistor control bit */ + } PS2CTL_b; + } ; + __IM uint32_t RESERVED4; + + union { + __IOM uint32_t RWADDR; /*!< (@ 0x00000078) Offset:0x78 USB Read/Write Address Register */ + + struct { + uint32_t : 2; + __IOM uint32_t RWADDR : 6; /*!< [7..2] USB FIFO address to be read or written from/to USB FIFO */ + uint32_t : 24; + } RWADDR_b; + } ; + + union { + __IOM uint32_t RWDATA; /*!< (@ 0x0000007C) Offset:0x7C USB Read/Write Data Register */ + + struct { + __IOM uint32_t RWDATA : 32; /*!< [31..0] Data to be read or written from/to USB FIFO */ + } RWDATA_b; + } ; + + union { + __IOM uint32_t RWSTATUS; /*!< (@ 0x00000080) Offset:0x80 USB Read/Write Status Register */ + + struct { + __IOM uint32_t W_STATUS : 1; /*!< [0..0] Write status of USB FIFO */ + __IOM uint32_t R_STATUS : 1; /*!< [1..1] WRead status of USB FIFO */ + uint32_t : 30; + } RWSTATUS_b; + } ; + + union { + __IOM uint32_t RWADDR2; /*!< (@ 0x00000084) Offset:0x84 USB Read/Write Address Register 2 */ + + struct { + uint32_t : 2; + __IOM uint32_t RWADDR : 6; /*!< [7..2] USB FIFO address to be read or written from/to USB FIFO */ + uint32_t : 24; + } RWADDR2_b; + } ; + + union { + __IOM uint32_t RWDATA2; /*!< (@ 0x00000088) Offset:0x88 USB Read/Write Data Register 2 */ + + struct { + __IOM uint32_t RWDATA : 32; /*!< [31..0] Data to be read or written from/to USB FIFO */ + } RWDATA2_b; + } ; + + union { + __IOM uint32_t RWSTATUS2; /*!< (@ 0x0000008C) Offset:0x8C USB Read/Write Status Register 2 */ + + struct { + __IOM uint32_t W_STATUS : 1; /*!< [0..0] Write status of USB FIFO */ + __IOM uint32_t R_STATUS : 1; /*!< [1..1] WRead status of USB FIFO */ + uint32_t : 30; + } RWSTATUS2_b; + } ; +} SN_USB_Type; /*!< Size = 144 (0x90) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_FLASH ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FLASH Memory Control Registers (SN_FLASH) + */ + +typedef struct { /*!< (@ 0x40062000) SN_FLASH Structure */ + + union { + __IOM uint32_t LPCTRL; /*!< (@ 0x00000000) Offset:0x00 Flash Low Power Control Register */ + + struct { + __IOM uint32_t LPMODE : 4; /*!< [3..0] Flash Low Power mode selection bit */ + uint32_t : 12; + __OM uint32_t FMCKEY : 16; /*!< [31..16] FMC verify key */ + } LPCTRL_b; + } ; + + union { + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Offset:0x04 Flash Status Register */ + + struct { + __IM uint32_t BUSY : 1; /*!< [0..0] Busy flag */ + uint32_t : 1; + __IOM uint32_t ERR : 1; /*!< [2..2] Erase/Error flag */ + uint32_t : 29; + } STATUS_b; + } ; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000008) Offset:0x08 Flash Control Register */ + + struct { + __IOM uint32_t PG : 1; /*!< [0..0] Flash program mode chosen bit */ + __IOM uint32_t PER : 1; /*!< [1..1] Page erase mode chosen bit */ + __IOM uint32_t MER : 1; /*!< [2..2] Mass erase mode chosen bit */ + uint32_t : 3; + __IOM uint32_t START : 1; /*!< [6..6] Start erase/program operation */ + __IOM uint32_t CHK : 1; /*!< [7..7] Checksum calculation chosen */ + uint32_t : 24; + } CTRL_b; + } ; + __IOM uint32_t DATA; /*!< (@ 0x0000000C) Offset:0x0C Flash Data Register */ + __IOM uint32_t ADDR; /*!< (@ 0x00000010) Offset:0x10 Flash Address Register */ + + union { + __IM uint32_t CHKSUM; /*!< (@ 0x00000014) Offset:0x14 Flash Checksum Register */ + + struct { + __IM uint32_t UserROM : 16; /*!< [15..0] Checksum of User ROM */ + __IM uint32_t BootROM : 16; /*!< [31..16] Checksum of Boot ROM */ + } CHKSUM_b; + } ; +} SN_FLASH_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_UC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UC Registers (SN_UC) + */ + +typedef struct { /*!< (@ 0x1FFF2228) SN_UC Structure */ + __IM uint32_t L4BYTE; /*!< (@ 0x00000000) Offset:0x00 UC Low 4 Byte Register */ + __IM uint32_t H4BYTE; /*!< (@ 0x00000004) Offset:0x04 UC High 4 Byte Register */ +} SN_UC_Type; /*!< Size = 8 (0x8) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define SN_SYS0_BASE 0x40060000UL +#define SN_SYS1_BASE 0x4005E000UL +#define SN_PMU_BASE 0x40032000UL +#define SN_PFPA_BASE 0x40042000UL +#define SN_GPIO0_BASE 0x40044000UL +#define SN_GPIO1_BASE 0x40046000UL +#define SN_GPIO2_BASE 0x40048000UL +#define SN_GPIO3_BASE 0x4004A000UL +#define SN_ADC_BASE 0x40026000UL +#define SN_CT16B0_BASE 0x40000000UL +#define SN_CT16B1_BASE 0x40002000UL +#define SN_WDT_BASE 0x40010000UL +#define SN_SPI0_BASE 0x4001C000UL +#define SN_I2C0_BASE 0x40018000UL +#define SN_UART0_BASE 0x40016000UL +#define SN_UART1_BASE 0x40014000UL +#define SN_UART2_BASE 0x40012000UL +#define SN_USB_BASE 0x4005C000UL +#define SN_FLASH_BASE 0x40062000UL +#define SN_UC_BASE 0x1FFF2228UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define SN_SYS0 ((SN_SYS0_Type*) SN_SYS0_BASE) +#define SN_SYS1 ((SN_SYS1_Type*) SN_SYS1_BASE) +#define SN_PMU ((SN_PMU_Type*) SN_PMU_BASE) +#define SN_PFPA ((SN_PFPA_Type*) SN_PFPA_BASE) +#define SN_GPIO0 ((SN_GPIO0_Type*) SN_GPIO0_BASE) +#define SN_GPIO1 ((SN_GPIO0_Type*) SN_GPIO1_BASE) +#define SN_GPIO2 ((SN_GPIO0_Type*) SN_GPIO2_BASE) +#define SN_GPIO3 ((SN_GPIO3_Type*) SN_GPIO3_BASE) +#define SN_ADC ((SN_ADC_Type*) SN_ADC_BASE) +#define SN_CT16B0 ((SN_CT16B0_Type*) SN_CT16B0_BASE) +#define SN_CT16B1 ((SN_CT16B1_Type*) SN_CT16B1_BASE) +#define SN_WDT ((SN_WDT_Type*) SN_WDT_BASE) +#define SN_SPI0 ((SN_SPI0_Type*) SN_SPI0_BASE) +#define SN_I2C0 ((SN_I2C0_Type*) SN_I2C0_BASE) +#define SN_UART0 ((SN_UART0_Type*) SN_UART0_BASE) +#define SN_UART1 ((SN_UART1_Type*) SN_UART1_BASE) +#define SN_UART2 ((SN_UART2_Type*) SN_UART2_BASE) +#define SN_USB ((SN_USB_Type*) SN_USB_BASE) +#define SN_FLASH ((SN_FLASH_Type*) SN_FLASH_BASE) +#define SN_UC ((SN_UC_Type*) SN_UC_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* SN32F240B_H */ + + +/** @} */ /* End of group SN32F240B */ + +/** @} */ /* End of group SONiX Technology Co., Ltd. */ diff --git a/os/common/ext/SONiX/SN32F2xx/SN32F260.h b/os/common/ext/SONiX/SN32F2xx/SN32F260.h new file mode 100644 index 00000000..9609f81f --- /dev/null +++ b/os/common/ext/SONiX/SN32F2xx/SN32F260.h @@ -0,0 +1,2617 @@ +/* + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontroller, but can be equally used for other + * suitable processor architectures. This file can be freely distributed. + * Modifications to this file shall be clearly marked. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * @file SN32F260.h + * @brief CMSIS HeaderFile + * @version 1.1 + * @date 09. January 2022 + * @note Generated by SVDConv V3.3.35 on Sunday, 09.01.2022 18:49:17 + * from File 'SN32F260.svd', + * last modified on Tuesday, 01.09.2020 10:52:27 + */ + + + +/** @addtogroup SONiX Technology Co., Ltd. + * @{ + */ + + +/** @addtogroup SN32F260 + * @{ + */ + + +#ifndef SN32F260_H +#define SN32F260_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M0 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== SN32F260 Specific Interrupt Numbers ========================================== */ + NDT_IRQn = 0, /*!< 0 NDT */ + USB_IRQn = 1, /*!< 1 USB */ + SPI0_IRQn = 13, /*!< 13 SPI0 */ + I2C0_IRQn = 15, /*!< 15 I2C0 */ + CT16B0_IRQn = 16, /*!< 16 CT16B0 */ + CT16B1_IRQn = 17, /*!< 17 CT16B1 */ + WDT_IRQn = 25, /*!< 25 WDT */ + LVD_IRQn = 26, /*!< 26 LVD */ + P3_IRQn = 28, /*!< 28 P3 */ + P2_IRQn = 29, /*!< 29 P2 */ + P1_IRQn = 30, /*!< 30 P1 */ + P0_IRQn = 31 /*!< 31 P0 */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M0 Processor and Core Peripherals =========================== */ +#define __CM0_REV 0x0000U /*!< CM0 Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 0 /*!< MPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0.h" /*!< ARM Cortex-M0 processor and core peripherals */ +#include "system_SN32F2xx.h" /*!< SN32F260 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SYS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System Control Registers (SN_SYS0) + */ + +typedef struct { /*!< (@ 0x40060000) SN_SYS0 Structure */ + + union { + __IOM uint32_t ANBCTRL; /*!< (@ 0x00000000) Offset:0x00 Analog Block Control Register */ + + struct { + __IOM uint32_t IHRCEN : 1; /*!< [0..0] IHRC enable */ + uint32_t : 31; + } ANBCTRL_b; + } ; + __IM uint32_t RESERVED; + + union { + __IM uint32_t CSST; /*!< (@ 0x00000008) Offset:0x08 Clock Source Status Register */ + + struct { + __IM uint32_t IHRCRDY : 1; /*!< [0..0] IHRC ready flag */ + uint32_t : 31; + } CSST_b; + } ; + + union { + __IOM uint32_t CLKCFG; /*!< (@ 0x0000000C) Offset:0x0C System Clock Configuration Register */ + + struct { + __IOM uint32_t SYSCLKSEL : 3; /*!< [2..0] System clock source selection */ + uint32_t : 1; + __IM uint32_t SYSCLKST : 3; /*!< [6..4] System clock switch status */ + uint32_t : 25; + } CLKCFG_b; + } ; + + union { + __IOM uint32_t AHBCP; /*!< (@ 0x00000010) Offset:0x10 AHB Clock Prescale Register */ + + struct { + __IOM uint32_t AHBPRE : 3; /*!< [2..0] AHB clock source prescaler */ + uint32_t : 29; + } AHBCP_b; + } ; + + union { + __IOM uint32_t RSTST; /*!< (@ 0x00000014) Offset:0x14 System Reset Status Register */ + + struct { + __IOM uint32_t SWRSTF : 1; /*!< [0..0] Software reset flag */ + __IOM uint32_t WDTRSTF : 1; /*!< [1..1] WDT reset flag */ + __IOM uint32_t LVDRSTF : 1; /*!< [2..2] LVD reset flag */ + __IOM uint32_t EXTRSTF : 1; /*!< [3..3] External reset flag */ + __IOM uint32_t PORRSTF : 1; /*!< [4..4] POR reset flag */ + uint32_t : 27; + } RSTST_b; + } ; + + union { + __IOM uint32_t LVDCTRL; /*!< (@ 0x00000018) Offset:0x18 LVD Control Register */ + + struct { + __IOM uint32_t LVDRSTLVL : 3; /*!< [2..0] LVD reset level */ + uint32_t : 2; + __IOM uint32_t LVDINTLVL : 2; /*!< [6..5] LVD interrupt level */ + uint32_t : 7; + __IOM uint32_t LVDRSTEN : 1; /*!< [14..14] LVD Reset enable */ + __IOM uint32_t LVDEN : 1; /*!< [15..15] LVD enable */ + uint32_t : 16; + } LVDCTRL_b; + } ; + + union { + __IOM uint32_t EXRSTCTRL; /*!< (@ 0x0000001C) Offset:0x1C External Reset Pin Control Register */ + + struct { + __IOM uint32_t RESETDIS : 1; /*!< [0..0] External reset pin disable */ + uint32_t : 31; + } EXRSTCTRL_b; + } ; + + union { + __IOM uint32_t SWDCTRL; /*!< (@ 0x00000020) Offset:0x20 SWD Pin Control Register */ + + struct { + __IOM uint32_t SWDDIS : 1; /*!< [0..0] SWD pin disable */ + uint32_t : 31; + } SWDCTRL_b; + } ; + + union { + __IOM uint32_t IVTM; /*!< (@ 0x00000024) Offset:0x24 Interrupt Vector Table Mapping Register */ + + struct { + __IOM uint32_t IVTM : 2; /*!< [1..0] Interrupt table mapping selection */ + uint32_t : 14; + __OM uint32_t IVTMKEY : 16; /*!< [31..16] IVTMKEY register key */ + } IVTM_b; + } ; + + union { + __IOM uint32_t NDTCTRL; /*!< (@ 0x00000028) Offset:0x28 Noise Detect Control Register */ + + struct { + uint32_t : 1; + __IOM uint32_t NDT5V_IE : 1; /*!< [1..1] NDT for VDD interrupt enable bit */ + uint32_t : 30; + } NDTCTRL_b; + } ; + + union { + __IOM uint32_t NDTSTS; /*!< (@ 0x0000002C) Offset:0x2C Noise Detect Status Register */ + + struct { + uint32_t : 1; + __IOM uint32_t NDT5V_DET : 1; /*!< [1..1] Power noise status of NDT5V IP */ + uint32_t : 30; + } NDTSTS_b; + } ; + + union { + __IOM uint32_t ANTIEFT; /*!< (@ 0x00000030) Offset:0x30 Anti-EFT Ability Control Register */ + + struct { + __IOM uint32_t AEFT : 3; /*!< [2..0] Anti-EFT ability */ + uint32_t : 29; + } ANTIEFT_b; + } ; +} SN_SYS0_Type; /*!< Size = 52 (0x34) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SYS1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System Control Registers (SN_SYS1) + */ + +typedef struct { /*!< (@ 0x4005E000) SN_SYS1 Structure */ + + union { + __IOM uint32_t AHBCLKEN; /*!< (@ 0x00000000) Offset:0x00 AHB Clock Enable Register */ + + struct { + __IOM uint32_t P0CLKEN : 1; /*!< [0..0] Enable AHB clock for P0 */ + __IOM uint32_t P1CLKEN : 1; /*!< [1..1] Enable AHB clock for P1 */ + __IOM uint32_t P2CLKEN : 1; /*!< [2..2] Enable AHB clock for P2 */ + __IOM uint32_t P3CLKEN : 1; /*!< [3..3] Enable AHB clock for P3 */ + __IOM uint32_t USBCLKEN : 1; /*!< [4..4] Enable AHB clock for USB */ + uint32_t : 1; + __IOM uint32_t CT16B0CLKEN : 1; /*!< [6..6] Enable AHB clock for CT16B0 */ + __IOM uint32_t CT16B1CLKEN : 1; /*!< [7..7] Enable AHB clock for CT16B1 */ + uint32_t : 4; + __IOM uint32_t SPI0CLKEN : 1; /*!< [12..12] Enable AHB clock for SPI0 */ + uint32_t : 8; + __IOM uint32_t I2C0CLKEN : 1; /*!< [21..21] Enable AHB clock for I2C0 */ + uint32_t : 2; + __IOM uint32_t WDTCLKEN : 1; /*!< [24..24] Enable AHB clock for WDT */ + uint32_t : 3; + __IOM uint32_t CLKOUTSEL : 3; /*!< [30..28] Clock output source selection */ + uint32_t : 1; + } AHBCLKEN_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t APBCP1; /*!< (@ 0x00000008) Offset:0x08 APB Clock Prescale Register 1 */ + + struct { + uint32_t : 16; + __IOM uint32_t SYSTICKPRE : 2; /*!< [17..16] SysTick APB clock source prescaler */ + uint32_t : 2; + __IOM uint32_t WDTPRE : 3; /*!< [22..20] WDT APB clock source prescaler */ + uint32_t : 5; + __IOM uint32_t CLKOUTPRE : 3; /*!< [30..28] CLKOUT APB clock source prescaler */ + uint32_t : 1; + } APBCP1_b; + } ; +} SN_SYS1_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_USB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal Serial Bus Full Speed Device Interface (USB) (SN_USB) + */ + +typedef struct { /*!< (@ 0x4005C000) SN_USB Structure */ + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000000) Offset:0x00 USB Interrupt Enable Register */ + + struct { + __IOM uint32_t EP1_NAK_EN : 1; /*!< [0..0] EP1 NAK Interrupt Enable */ + __IOM uint32_t EP2_NAK_EN : 1; /*!< [1..1] EP2 NAK Interrupt Enable */ + __IOM uint32_t EP3_NAK_EN : 1; /*!< [2..2] EP3 NAK Interrupt Enable */ + __IOM uint32_t EP4_NAK_EN : 1; /*!< [3..3] EP4 NAK Interrupt Enable */ + __IOM uint32_t EPN_ACK_EN : 1; /*!< [4..4] Enable all of EP(1~4) ACK Interrupt */ + uint32_t : 23; + __IOM uint32_t BUSWK_IE : 1; /*!< [28..28] Bus Wake Up Interrupt Enable */ + __IOM uint32_t USB_IE : 1; /*!< [29..29] USB Event Interrupt Enable */ + __IOM uint32_t USB_SOF_IE : 1; /*!< [30..30] USB SOF Interrupt Enable */ + __IOM uint32_t BUS_IE : 1; /*!< [31..31] Bus Event Interrupt Enable */ + } INTEN_b; + } ; + + union { + __IM uint32_t INSTS; /*!< (@ 0x00000004) Offset:0x04 USB Interrupt Event Status Register */ + + struct { + __IM uint32_t EP1_NAK : 1; /*!< [0..0] Endpoint 1 NAK transaction flag */ + __IM uint32_t EP2_NAK : 1; /*!< [1..1] Endpoint 2 NAK transaction flag */ + __IM uint32_t EP3_NAK : 1; /*!< [2..2] Endpoint 3 NAK transaction flag */ + __IM uint32_t EP4_NAK : 1; /*!< [3..3] Endpoint 4 NAK transaction flag */ + uint32_t : 4; + __IM uint32_t EP1_ACK : 1; /*!< [8..8] Endpoint 1 ACK transaction flag */ + __IM uint32_t EP2_ACK : 1; /*!< [9..9] Endpoint 2 ACK transaction flag */ + __IM uint32_t EP3_ACK : 1; /*!< [10..10] Endpoint 3 ACK transaction flag */ + __IM uint32_t EP4_ACK : 1; /*!< [11..11] Endpoint 4 ACK transaction flag */ + uint32_t : 5; + __IM uint32_t ERR_TIMEOUT : 1; /*!< [17..17] Timeout Status */ + __IM uint32_t ERR_SETUP : 1; /*!< [18..18] Wrong Setup data received */ + __IM uint32_t EP0_OUT_STALL : 1; /*!< [19..19] EP0 OUT STALL transaction */ + __IM uint32_t EP0_IN_STALL : 1; /*!< [20..20] EP0 IN STALL Transaction is completed */ + __IM uint32_t EP0_OUT : 1; /*!< [21..21] EP0 OUT ACK Transaction Flag */ + __IM uint32_t EP0_IN : 1; /*!< [22..22] EP0 IN ACK Transaction Flag */ + __IM uint32_t EP0_SETUP : 1; /*!< [23..23] EP0 Setup Transaction Flag */ + __IM uint32_t EP0_PRESETUP : 1; /*!< [24..24] EP0 Setup Token Packet Flag */ + uint32_t : 1; + __IM uint32_t USB_SOF : 1; /*!< [26..26] USB SOF packet received flag */ + uint32_t : 2; + __IM uint32_t BUS_RESUME : 1; /*!< [29..29] USB Bus Resume signal flag */ + __IM uint32_t BUS_SUSPEND : 1; /*!< [30..30] USB Bus Suspend signal flag */ + __IM uint32_t BUS_RESET : 1; /*!< [31..31] USB Bus Reset signal flag */ + } INSTS_b; + } ; + + union { + __OM uint32_t INSTSC; /*!< (@ 0x00000008) Offset:0x08 USB Interrupt Event Status Clear + Register */ + + struct { + __OM uint32_t EP1_NAKC : 1; /*!< [0..0] EP1 NAK clear bit */ + __OM uint32_t EP2_NAKC : 1; /*!< [1..1] EP2 NAK clear bit */ + __OM uint32_t EP3_NAKC : 1; /*!< [2..2] EP3 NAK clear bit */ + __OM uint32_t EP4_NAKC : 1; /*!< [3..3] EP4 NAK clear bit */ + uint32_t : 4; + __OM uint32_t EP1_ACKC : 1; /*!< [8..8] EP1 ACK clear bit */ + __OM uint32_t EP2_ACKC : 1; /*!< [9..9] EP2 ACK clear bit */ + __OM uint32_t EP3_ACKC : 1; /*!< [10..10] EP3 ACK clear bit */ + __OM uint32_t EP4_ACKC : 1; /*!< [11..11] EP4 ACK clear bit */ + uint32_t : 5; + __OM uint32_t ERR_TIMEOUTC : 1; /*!< [17..17] Timeout Error clear bit */ + __OM uint32_t ERR_SETUPC : 1; /*!< [18..18] Error Setup clear bit */ + __OM uint32_t EP0_OUT_STALLC : 1; /*!< [19..19] EP0 OUT STALL clear bit */ + __OM uint32_t EP0_IN_STALLC : 1; /*!< [20..20] EP0 IN STALL clear bit */ + __OM uint32_t EP0_OUTC : 1; /*!< [21..21] EP0 OUT clear bit */ + __OM uint32_t EP0_INC : 1; /*!< [22..22] EP0 IN clear bit */ + __OM uint32_t EP0_SETUPC : 1; /*!< [23..23] EP0 SETUP clear bit */ + __OM uint32_t EP0_PRESETUPC : 1; /*!< [24..24] EP0 PRESETUP clear bit */ + __OM uint32_t BUS_WAKEUPC : 1; /*!< [25..25] Bus Wakeup clear bit */ + __OM uint32_t USB_SOFC : 1; /*!< [26..26] USB SOF clear bit */ + uint32_t : 2; + __OM uint32_t BUS_RESUMEC : 1; /*!< [29..29] USB Bus Resume clear bit */ + uint32_t : 1; + __OM uint32_t BUS_RESETC : 1; /*!< [31..31] USB Bus Reset clear bit */ + } INSTSC_b; + } ; + + union { + __IOM uint32_t ADDR; /*!< (@ 0x0000000C) Offset:0x0C USB Device Address Register */ + + struct { + __IOM uint32_t UADDR : 7; /*!< [6..0] USB device's address */ + uint32_t : 25; + } ADDR_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000010) Offset:0x10 USB Configuration Register */ + + struct { + __IOM uint32_t EP1_DIR : 1; /*!< [0..0] Endpoint 1 IN/OUT direction setting */ + __IOM uint32_t EP2_DIR : 1; /*!< [1..1] Endpoint 2 IN/OUT direction setting */ + __IOM uint32_t EP3_DIR : 1; /*!< [2..2] Endpoint 3 IN/OUT direction setting */ + __IOM uint32_t EP4_DIR : 1; /*!< [3..3] Endpoint 4 IN/OUT direction setting */ + uint32_t : 22; + __IOM uint32_t DIS_PDEN : 1; /*!< [26..26] Enable internal D+ and D- 175k pull-down resistor */ + __IOM uint32_t ESD_EN : 1; /*!< [27..27] Enable USB anti-ESD protection */ + __IOM uint32_t SIE_EN : 1; /*!< [28..28] USB Serial Interface Engine Enable */ + __IOM uint32_t DPPU_EN : 1; /*!< [29..29] Enable internal D+ 1.5k pull-up resistor */ + __IOM uint32_t PHY_EN : 1; /*!< [30..30] PHY Transceiver Function Enable */ + __IOM uint32_t VREG33_EN : 1; /*!< [31..31] Enable the internal VREG33 ouput */ + } CFG_b; + } ; + + union { + __IOM uint32_t SGCTL; /*!< (@ 0x00000014) Offset:0x14 USB Signal Control Register */ + + struct { + __IOM uint32_t BUS_DN : 1; /*!< [0..0] USB D- state */ + __IOM uint32_t BUS_DP : 1; /*!< [1..1] USB DP state */ + __IOM uint32_t BUS_DRVEN : 1; /*!< [2..2] Enable to drive USB bus */ + uint32_t : 29; + } SGCTL_b; + } ; + + union { + __IOM uint32_t EP0CTL; /*!< (@ 0x00000018) Offset:0x18 USB Endpoint 0 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 20; + __IOM uint32_t OUT_STALL_EN : 1; /*!< [27..27] Enable EP0 OUT STALL handshake */ + __IOM uint32_t IN_STALL_EN : 1; /*!< [28..28] Enable EP0 IN STALL handshake */ + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Enable Endpoint 0 Function */ + } EP0CTL_b; + } ; + + union { + __IOM uint32_t EP1CTL; /*!< (@ 0x0000001C) Offset:0x1C USB Endpoint 1 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 1 Function enable bit */ + } EP1CTL_b; + } ; + + union { + __IOM uint32_t EP2CTL; /*!< (@ 0x00000020) Offset:0x20 USB Endpoint 2 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 2 Function enable bit */ + } EP2CTL_b; + } ; + + union { + __IOM uint32_t EP3CTL; /*!< (@ 0x00000024) Offset:0x24 USB Endpoint 3 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 3 Function enable bit */ + } EP3CTL_b; + } ; + + union { + __IOM uint32_t EP4CTL; /*!< (@ 0x00000028) Offset:0x28 USB Endpoint 4 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 4 Function enable bit */ + } EP4CTL_b; + } ; + __IM uint32_t RESERVED[4]; + + union { + __IOM uint32_t EPTOGGLE; /*!< (@ 0x0000003C) Offset:0x3C USB Endpoint Data Toggle Register */ + + struct { + __IOM uint32_t ENDP1_DATA01 : 1; /*!< [0..0] Endpoint 1 data toggle bit */ + __IOM uint32_t ENDP2_DATA01 : 1; /*!< [1..1] Endpoint 2 data toggle bit */ + __IOM uint32_t ENDP3_DATA01 : 1; /*!< [2..2] Endpoint 3 data toggle bit */ + __IOM uint32_t ENDP4_DATA01 : 1; /*!< [3..3] Endpoint 4 data toggle bit */ + uint32_t : 28; + } EPTOGGLE_b; + } ; + __IM uint32_t RESERVED1[2]; + + union { + __IOM uint32_t EP1BUFOS; /*!< (@ 0x00000048) Offset:0x48 USB Endpoint 1 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP1BUFOS_b; + } ; + + union { + __IOM uint32_t EP2BUFOS; /*!< (@ 0x0000004C) Offset:0x4C USB Endpoint 2 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP2BUFOS_b; + } ; + + union { + __IOM uint32_t EP3BUFOS; /*!< (@ 0x00000050) Offset:0x50 USB Endpoint 3 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP3BUFOS_b; + } ; + + union { + __IOM uint32_t EP4BUFOS; /*!< (@ 0x00000054) Offset:0x54 USB Endpoint 4 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP4BUFOS_b; + } ; + __IM uint32_t RESERVED2[2]; + + union { + __IM uint32_t FRMNO; /*!< (@ 0x00000060) Offset:0x60 USB Frame Number Register */ + + struct { + __IOM uint32_t FRAME_NO : 11; /*!< [10..0] The 11-bit frame number of the SOF packet */ + uint32_t : 21; + } FRMNO_b; + } ; + + union { + __IOM uint32_t PHYPRM; /*!< (@ 0x00000064) Offset:0x64 USB PHY Parameter Register */ + + struct { + __IOM uint32_t PHY_PARAM : 6; /*!< [5..0] USB PHY parameter */ + uint32_t : 26; + } PHYPRM_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t PHYPRM2; /*!< (@ 0x0000006C) Offset:0x6C USB PHY Parameter Register 2 */ + + struct { + __IOM uint32_t PHY_PS : 15; /*!< [14..0] USB PHY parameter 2 */ + uint32_t : 17; + } PHYPRM2_b; + } ; + + union { + __IOM uint32_t PS2CTL; /*!< (@ 0x00000070) Offset:0x70 PS/2 Control Register */ + + struct { + __IOM uint32_t SCKM : 1; /*!< [0..0] PS/2 SCK mode control bit */ + __IOM uint32_t SDAM : 1; /*!< [1..1] PS/2 SDA mode control bit */ + __IOM uint32_t SCK : 1; /*!< [2..2] PS/2 SCK data buffer */ + __IOM uint32_t SDA : 1; /*!< [3..3] PS/2 SDA data buffer */ + uint32_t : 27; + __IOM uint32_t PS2ENB : 1; /*!< [31..31] PS/2 internal 5kohm pull-up resistor control bit */ + } PS2CTL_b; + } ; + __IM uint32_t RESERVED4; + + union { + __IOM uint32_t RWADDR; /*!< (@ 0x00000078) Offset:0x78 USB Read/Write Address Register */ + + struct { + uint32_t : 2; + __IOM uint32_t RWADDR : 6; /*!< [7..2] USB FIFO address to be read or written from/to USB FIFO */ + uint32_t : 24; + } RWADDR_b; + } ; + + union { + __IOM uint32_t RWDATA; /*!< (@ 0x0000007C) Offset:0x7C USB Read/Write Data Register */ + + struct { + __IOM uint32_t RWDATA : 32; /*!< [31..0] Data to be read or written from/to USB FIFO */ + } RWDATA_b; + } ; + + union { + __IOM uint32_t RWSTATUS; /*!< (@ 0x00000080) Offset:0x80 USB Read/Write Status Register */ + + struct { + __IOM uint32_t W_STATUS : 1; /*!< [0..0] Write status of USB FIFO */ + __IOM uint32_t R_STATUS : 1; /*!< [1..1] WRead status of USB FIFO */ + uint32_t : 30; + } RWSTATUS_b; + } ; + + union { + __IOM uint32_t RWADDR2; /*!< (@ 0x00000084) Offset:0x84 USB Read/Write Address Register 2 */ + + struct { + uint32_t : 2; + __IOM uint32_t RWADDR : 6; /*!< [7..2] USB FIFO address to be read or written from/to USB FIFO */ + uint32_t : 24; + } RWADDR2_b; + } ; + + union { + __IOM uint32_t RWDATA2; /*!< (@ 0x00000088) Offset:0x88 USB Read/Write Data Register 2 */ + + struct { + __IOM uint32_t RWDATA : 32; /*!< [31..0] Data to be read or written from/to USB FIFO */ + } RWDATA2_b; + } ; + + union { + __IOM uint32_t RWSTATUS2; /*!< (@ 0x0000008C) Offset:0x8C USB Read/Write Status Register 2 */ + + struct { + __IOM uint32_t W_STATUS : 1; /*!< [0..0] Write status of USB FIFO */ + __IOM uint32_t R_STATUS : 1; /*!< [1..1] WRead status of USB FIFO */ + uint32_t : 30; + } RWSTATUS2_b; + } ; +} SN_USB_Type; /*!< Size = 144 (0x90) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose I/O (SN_GPIO0) + */ + +typedef struct { /*!< (@ 0x40044000) SN_GPIO0 Structure */ + + union { + __IOM uint32_t DATA; /*!< (@ 0x00000000) Offset:0x00 GPIO Port n Data Register */ + + struct { + __IOM uint32_t DATA0 : 1; /*!< [0..0] Data of Pn.0 */ + __IOM uint32_t DATA1 : 1; /*!< [1..1] Data of Pn.1 */ + __IOM uint32_t DATA2 : 1; /*!< [2..2] Data of Pn.2 */ + __IOM uint32_t DATA3 : 1; /*!< [3..3] Data of Pn.3 */ + __IOM uint32_t DATA4 : 1; /*!< [4..4] Data of Pn.4 */ + __IOM uint32_t DATA5 : 1; /*!< [5..5] Data of Pn.5 */ + __IOM uint32_t DATA6 : 1; /*!< [6..6] Data of Pn.6 */ + __IOM uint32_t DATA7 : 1; /*!< [7..7] Data of Pn.7 */ + __IOM uint32_t DATA8 : 1; /*!< [8..8] Data of Pn.8 */ + __IOM uint32_t DATA9 : 1; /*!< [9..9] Data of Pn.9 */ + __IOM uint32_t DATA10 : 1; /*!< [10..10] Data of Pn.10 */ + __IOM uint32_t DATA11 : 1; /*!< [11..11] Data of Pn.11 */ + __IOM uint32_t DATA12 : 1; /*!< [12..12] Data of Pn.12 */ + __IOM uint32_t DATA13 : 1; /*!< [13..13] Data of Pn.13 */ + __IOM uint32_t DATA14 : 1; /*!< [14..14] Data of Pn.14 */ + __IOM uint32_t DATA15 : 1; /*!< [15..15] Data of Pn.15 */ + uint32_t : 16; + } DATA_b; + } ; + + union { + __IOM uint32_t MODE; /*!< (@ 0x00000004) Offset:0x04 GPIO Port n Mode Register */ + + struct { + __IOM uint32_t MODE0 : 1; /*!< [0..0] Mode of Pn.0 */ + __IOM uint32_t MODE1 : 1; /*!< [1..1] Mode of Pn.1 */ + __IOM uint32_t MODE2 : 1; /*!< [2..2] Mode of Pn.2 */ + __IOM uint32_t MODE3 : 1; /*!< [3..3] Mode of Pn.3 */ + __IOM uint32_t MODE4 : 1; /*!< [4..4] Mode of Pn.4 */ + __IOM uint32_t MODE5 : 1; /*!< [5..5] Mode of Pn.5 */ + __IOM uint32_t MODE6 : 1; /*!< [6..6] Mode of Pn.6 */ + __IOM uint32_t MODE7 : 1; /*!< [7..7] Mode of Pn.7 */ + __IOM uint32_t MODE8 : 1; /*!< [8..8] Mode of Pn.8 */ + __IOM uint32_t MODE9 : 1; /*!< [9..9] Mode of Pn.9 */ + __IOM uint32_t MODE10 : 1; /*!< [10..10] Mode of Pn.10 */ + __IOM uint32_t MODE11 : 1; /*!< [11..11] Mode of Pn.11 */ + __IOM uint32_t MODE12 : 1; /*!< [12..12] Mode of Pn.12 */ + __IOM uint32_t MODE13 : 1; /*!< [13..13] Mode of Pn.13 */ + __IOM uint32_t MODE14 : 1; /*!< [14..14] Mode of Pn.14 */ + __IOM uint32_t MODE15 : 1; /*!< [15..15] Mode of Pn.15 */ + uint32_t : 16; + } MODE_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000008) Offset:0x08 GPIO Port n Configuration Register */ + + struct { + __IOM uint32_t CFG0 : 2; /*!< [1..0] Configuration of Pn.0 */ + __IOM uint32_t CFG1 : 2; /*!< [3..2] Configuration of Pn.1 */ + __IOM uint32_t CFG2 : 2; /*!< [5..4] Configuration of Pn.2 */ + __IOM uint32_t CFG3 : 2; /*!< [7..6] Configuration of Pn.3 */ + __IOM uint32_t CFG4 : 2; /*!< [9..8] Configuration of Pn.4 */ + __IOM uint32_t CFG5 : 2; /*!< [11..10] Configuration of Pn.5 */ + __IOM uint32_t CFG6 : 2; /*!< [13..12] Configuration of Pn.6 */ + __IOM uint32_t CFG7 : 2; /*!< [15..14] Configuration of Pn.7 */ + __IOM uint32_t CFG8 : 2; /*!< [17..16] Configuration of Pn.8 */ + __IOM uint32_t CFG9 : 2; /*!< [19..18] Configuration of Pn.9 */ + __IOM uint32_t CFG10 : 2; /*!< [21..20] Configuration of Pn.10 */ + __IOM uint32_t CFG11 : 2; /*!< [23..22] Configuration of Pn.11 */ + __IOM uint32_t CFG12 : 2; /*!< [25..24] Configuration of Pn.12 */ + __IOM uint32_t CFG13 : 2; /*!< [27..26] Configuration of Pn.13 */ + __IOM uint32_t CFG14 : 2; /*!< [29..28] Configuration of Pn.14 */ + __IOM uint32_t CFG15 : 2; /*!< [31..30] Configuration of Pn.15 */ + } CFG_b; + } ; + + union { + __IOM uint32_t IS; /*!< (@ 0x0000000C) Offset:0x0C GPIO Port n Interrupt Sense Register */ + + struct { + __IOM uint32_t IS0 : 1; /*!< [0..0] Interrupt on Pn.0 is event or edge sensitive */ + __IOM uint32_t IS1 : 1; /*!< [1..1] Interrupt on Pn.1 is event or edge sensitive */ + __IOM uint32_t IS2 : 1; /*!< [2..2] Interrupt on Pn.2 is event or edge sensitive */ + __IOM uint32_t IS3 : 1; /*!< [3..3] Interrupt on Pn.3 is event or edge sensitive */ + __IOM uint32_t IS4 : 1; /*!< [4..4] Interrupt on Pn.4 is event or edge sensitive */ + __IOM uint32_t IS5 : 1; /*!< [5..5] Interrupt on Pn.5 is event or edge sensitive */ + __IOM uint32_t IS6 : 1; /*!< [6..6] Interrupt on Pn.6 is event or edge sensitive */ + __IOM uint32_t IS7 : 1; /*!< [7..7] Interrupt on Pn.7 is event or edge sensitive */ + __IOM uint32_t IS8 : 1; /*!< [8..8] Interrupt on Pn.8 is event or edge sensitive */ + __IOM uint32_t IS9 : 1; /*!< [9..9] Interrupt on Pn.9 is event or edge sensitive */ + __IOM uint32_t IS10 : 1; /*!< [10..10] Interrupt on Pn.10 is event or edge sensitive */ + __IOM uint32_t IS11 : 1; /*!< [11..11] Interrupt on Pn.11 is event or edge sensitive */ + __IOM uint32_t IS12 : 1; /*!< [12..12] Interrupt on Pn.12 is event or edge sensitive */ + __IOM uint32_t IS13 : 1; /*!< [13..13] Interrupt on Pn.13 is event or edge sensitive */ + __IOM uint32_t IS14 : 1; /*!< [14..14] Interrupt on Pn.14 is event or edge sensitive */ + __IOM uint32_t IS15 : 1; /*!< [15..15] Interrupt on Pn.15 is event or edge sensitive */ + uint32_t : 16; + } IS_b; + } ; + + union { + __IOM uint32_t IBS; /*!< (@ 0x00000010) Offset:0x10 GPIO Port n Interrupt Both-edge Sense + Register */ + + struct { + __IOM uint32_t IBS0 : 1; /*!< [0..0] Interrupt on Pn.0 is triggered ob both edges */ + __IOM uint32_t IBS1 : 1; /*!< [1..1] Interrupt on Pn.1 is triggered ob both edges */ + __IOM uint32_t IBS2 : 1; /*!< [2..2] Interrupt on Pn.2 is triggered ob both edges */ + __IOM uint32_t IBS3 : 1; /*!< [3..3] Interrupt on Pn.3 is triggered ob both edges */ + __IOM uint32_t IBS4 : 1; /*!< [4..4] Interrupt on Pn.4 is triggered ob both edges */ + __IOM uint32_t IBS5 : 1; /*!< [5..5] Interrupt on Pn.5 is triggered ob both edges */ + __IOM uint32_t IBS6 : 1; /*!< [6..6] Interrupt on Pn.6 is triggered ob both edges */ + __IOM uint32_t IBS7 : 1; /*!< [7..7] Interrupt on Pn.7 is triggered ob both edges */ + __IOM uint32_t IBS8 : 1; /*!< [8..8] Interrupt on Pn.8 is triggered ob both edges */ + __IOM uint32_t IBS9 : 1; /*!< [9..9] Interrupt on Pn.9 is triggered ob both edges */ + __IOM uint32_t IBS10 : 1; /*!< [10..10] Interrupt on Pn.10 is triggered ob both edges */ + __IOM uint32_t IBS11 : 1; /*!< [11..11] Interrupt on Pn.11 is triggered ob both edges */ + __IOM uint32_t IBS12 : 1; /*!< [12..12] Interrupt on Pn.12 is triggered ob both edges */ + __IOM uint32_t IBS13 : 1; /*!< [13..13] Interrupt on Pn.13 is triggered ob both edges */ + __IOM uint32_t IBS14 : 1; /*!< [14..14] Interrupt on Pn.14 is triggered ob both edges */ + __IOM uint32_t IBS15 : 1; /*!< [15..15] Interrupt on Pn.15 is triggered ob both edges */ + uint32_t : 16; + } IBS_b; + } ; + + union { + __IOM uint32_t IEV; /*!< (@ 0x00000014) Offset:0x14 GPIO Port n Interrupt Event Register */ + + struct { + __IOM uint32_t IEV0 : 1; /*!< [0..0] Interrupt trigged evnet on Pn.0 */ + __IOM uint32_t IEV1 : 1; /*!< [1..1] Interrupt trigged evnet on Pn.1 */ + __IOM uint32_t IEV2 : 1; /*!< [2..2] Interrupt trigged evnet on Pn.2 */ + __IOM uint32_t IEV3 : 1; /*!< [3..3] Interrupt trigged evnet on Pn.3 */ + __IOM uint32_t IEV4 : 1; /*!< [4..4] Interrupt trigged evnet on Pn.4 */ + __IOM uint32_t IEV5 : 1; /*!< [5..5] Interrupt trigged evnet on Pn.5 */ + __IOM uint32_t IEV6 : 1; /*!< [6..6] Interrupt trigged evnet on Pn.6 */ + __IOM uint32_t IEV7 : 1; /*!< [7..7] Interrupt trigged evnet on Pn.7 */ + __IOM uint32_t IEV8 : 1; /*!< [8..8] Interrupt trigged evnet on Pn.8 */ + __IOM uint32_t IEV9 : 1; /*!< [9..9] Interrupt trigged evnet on Pn.9 */ + __IOM uint32_t IEV10 : 1; /*!< [10..10] Interrupt trigged evnet on Pn.10 */ + __IOM uint32_t IEV11 : 1; /*!< [11..11] Interrupt trigged evnet on Pn.11 */ + __IOM uint32_t IEV12 : 1; /*!< [12..12] Interrupt trigged evnet on Pn.12 */ + __IOM uint32_t IEV13 : 1; /*!< [13..13] Interrupt trigged evnet on Pn.13 */ + __IOM uint32_t IEV14 : 1; /*!< [14..14] Interrupt trigged evnet on Pn.14 */ + __IOM uint32_t IEV15 : 1; /*!< [15..15] Interrupt trigged evnet on Pn.15 */ + uint32_t : 16; + } IEV_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000018) Offset:0x18 GPIO Port n Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] Interrupt on Pn.0 enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] Interrupt on Pn.1 enable */ + __IOM uint32_t IE2 : 1; /*!< [2..2] Interrupt on Pn.2 enable */ + __IOM uint32_t IE3 : 1; /*!< [3..3] Interrupt on Pn.3 enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] Interrupt on Pn.4 enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] Interrupt on Pn.5 enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] Interrupt on Pn.6 enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] Interrupt on Pn.7 enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] Interrupt on Pn.8 enable */ + __IOM uint32_t IE9 : 1; /*!< [9..9] Interrupt on Pn.9 enable */ + __IOM uint32_t IE10 : 1; /*!< [10..10] Interrupt on Pn.10 enable */ + __IOM uint32_t IE11 : 1; /*!< [11..11] Interrupt on Pn.11 enable */ + __IOM uint32_t IE12 : 1; /*!< [12..12] Interrupt on Pn.12 enable */ + __IOM uint32_t IE13 : 1; /*!< [13..13] Interrupt on Pn.13 enable */ + __IOM uint32_t IE14 : 1; /*!< [14..14] Interrupt on Pn.14 enable */ + __IOM uint32_t IE15 : 1; /*!< [15..15] Interrupt on Pn.15 enable */ + uint32_t : 16; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x0000001C) Offset:0x1C GPIO Port n Raw Interrupt Status + Register */ + + struct { + __IM uint32_t IF0 : 1; /*!< [0..0] Pn.0 raw interrupt flag */ + __IM uint32_t IF1 : 1; /*!< [1..1] Pn.1 raw interrupt flag */ + __IM uint32_t IF2 : 1; /*!< [2..2] Pn.2 raw interrupt flag */ + __IM uint32_t IF3 : 1; /*!< [3..3] Pn.3 raw interrupt flag */ + __IM uint32_t IF4 : 1; /*!< [4..4] Pn.4 raw interrupt flag */ + __IM uint32_t IF5 : 1; /*!< [5..5] Pn.5 raw interrupt flag */ + __IM uint32_t IF6 : 1; /*!< [6..6] Pn.6 raw interrupt flag */ + __IM uint32_t IF7 : 1; /*!< [7..7] Pn.7 raw interrupt flag */ + __IM uint32_t IF8 : 1; /*!< [8..8] Pn.8 raw interrupt flag */ + __IM uint32_t IF9 : 1; /*!< [9..9] Pn.9 raw interrupt flag */ + __IM uint32_t IF10 : 1; /*!< [10..10] Pn.10 raw interrupt flag */ + __IM uint32_t IF11 : 1; /*!< [11..11] Pn.11 raw interrupt flag */ + __IM uint32_t IF12 : 1; /*!< [12..12] Pn.12 raw interrupt flag */ + __IM uint32_t IF13 : 1; /*!< [13..13] Pn.13 raw interrupt flag */ + __IM uint32_t IF14 : 1; /*!< [14..14] Pn.14 raw interrupt flag */ + __IM uint32_t IF15 : 1; /*!< [15..15] Pn.15 raw interrupt flag */ + uint32_t : 16; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000020) Offset:0x20 GPIO Port n Interrupt Clear Register */ + + struct { + __OM uint32_t IC0 : 1; /*!< [0..0] Pn.0 interrupt flag clear */ + __OM uint32_t IC1 : 1; /*!< [1..1] Pn.1 interrupt flag clear */ + __OM uint32_t IC2 : 1; /*!< [2..2] Pn.2 interrupt flag clear */ + __OM uint32_t IC3 : 1; /*!< [3..3] Pn.3 interrupt flag clear */ + __OM uint32_t IC4 : 1; /*!< [4..4] Pn.4 interrupt flag clear */ + __OM uint32_t IC5 : 1; /*!< [5..5] Pn.5 interrupt flag clear */ + __OM uint32_t IC6 : 1; /*!< [6..6] Pn.6 interrupt flag clear */ + __OM uint32_t IC7 : 1; /*!< [7..7] Pn.7 interrupt flag clear */ + __OM uint32_t IC8 : 1; /*!< [8..8] Pn.8 interrupt flag clear */ + __OM uint32_t IC9 : 1; /*!< [9..9] Pn.9 interrupt flag clear */ + __OM uint32_t IC10 : 1; /*!< [10..10] Pn.10 interrupt flag clear */ + __OM uint32_t IC11 : 1; /*!< [11..11] Pn.11 interrupt flag clear */ + __OM uint32_t IC12 : 1; /*!< [12..12] Pn.12 interrupt flag clear */ + __OM uint32_t IC13 : 1; /*!< [13..13] Pn.13 interrupt flag clear */ + __OM uint32_t IC14 : 1; /*!< [14..14] Pn.14 interrupt flag clear */ + __OM uint32_t IC15 : 1; /*!< [15..15] Pn.15 interrupt flag clear */ + uint32_t : 16; + } IC_b; + } ; + + union { + __OM uint32_t BSET; /*!< (@ 0x00000024) Offset:0x24 GPIO Port n Bits Set Operation Register */ + + struct { + __OM uint32_t BSET0 : 1; /*!< [0..0] Set Pn.0 */ + __OM uint32_t BSET1 : 1; /*!< [1..1] Set Pn.1 */ + __OM uint32_t BSET2 : 1; /*!< [2..2] Set Pn.2 */ + __OM uint32_t BSET3 : 1; /*!< [3..3] Set Pn.3 */ + __OM uint32_t BSET4 : 1; /*!< [4..4] Set Pn.4 */ + __OM uint32_t BSET5 : 1; /*!< [5..5] Set Pn.5 */ + __OM uint32_t BSET6 : 1; /*!< [6..6] Set Pn.6 */ + __OM uint32_t BSET7 : 1; /*!< [7..7] Set Pn.7 */ + __OM uint32_t BSET8 : 1; /*!< [8..8] Set Pn.8 */ + __OM uint32_t BSET9 : 1; /*!< [9..9] Set Pn.9 */ + __OM uint32_t BSET10 : 1; /*!< [10..10] Set Pn.10 */ + __OM uint32_t BSET11 : 1; /*!< [11..11] Set Pn.11 */ + __OM uint32_t BSET12 : 1; /*!< [12..12] Set Pn.12 */ + __OM uint32_t BSET13 : 1; /*!< [13..13] Set Pn.13 */ + __OM uint32_t BSET14 : 1; /*!< [14..14] Set Pn.14 */ + __OM uint32_t BSET15 : 1; /*!< [15..15] Set Pn.15 */ + uint32_t : 16; + } BSET_b; + } ; + + union { + __OM uint32_t BCLR; /*!< (@ 0x00000028) Offset:0x28 GPIO Port n Bits Clear Operation + Register */ + + struct { + __OM uint32_t BCLR0 : 1; /*!< [0..0] Clear Pn.0 */ + __OM uint32_t BCLR1 : 1; /*!< [1..1] Clear Pn.1 */ + __OM uint32_t BCLR2 : 1; /*!< [2..2] Clear Pn.2 */ + __OM uint32_t BCLR3 : 1; /*!< [3..3] Clear Pn.3 */ + __OM uint32_t BCLR4 : 1; /*!< [4..4] Clear Pn.4 */ + __OM uint32_t BCLR5 : 1; /*!< [5..5] Clear Pn.5 */ + __OM uint32_t BCLR6 : 1; /*!< [6..6] Clear Pn.6 */ + __OM uint32_t BCLR7 : 1; /*!< [7..7] Clear Pn.7 */ + __OM uint32_t BCLR8 : 1; /*!< [8..8] Clear Pn.8 */ + __OM uint32_t BCLR9 : 1; /*!< [9..9] Clear Pn.9 */ + __OM uint32_t BCLR10 : 1; /*!< [10..10] Clear Pn.10 */ + __OM uint32_t BCLR11 : 1; /*!< [11..11] Clear Pn.11 */ + __OM uint32_t BCLR12 : 1; /*!< [12..12] Clear Pn.12 */ + __OM uint32_t BCLR13 : 1; /*!< [13..13] Clear Pn.13 */ + __OM uint32_t BCLR14 : 1; /*!< [14..14] Clear Pn.14 */ + __OM uint32_t BCLR15 : 1; /*!< [15..15] Clear Pn.15 */ + uint32_t : 16; + } BCLR_b; + } ; +} SN_GPIO0_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose I/O (SN_GPIO1) + */ + +typedef struct { /*!< (@ 0x40046000) SN_GPIO1 Structure */ + + union { + __IOM uint32_t DATA; /*!< (@ 0x00000000) Offset:0x00 GPIO Port n Data Register */ + + struct { + __IOM uint32_t DATA0 : 1; /*!< [0..0] Data of Pn.0 */ + __IOM uint32_t DATA1 : 1; /*!< [1..1] Data of Pn.1 */ + __IOM uint32_t DATA2 : 1; /*!< [2..2] Data of Pn.2 */ + __IOM uint32_t DATA3 : 1; /*!< [3..3] Data of Pn.3 */ + __IOM uint32_t DATA4 : 1; /*!< [4..4] Data of Pn.4 */ + __IOM uint32_t DATA5 : 1; /*!< [5..5] Data of Pn.5 */ + uint32_t : 26; + } DATA_b; + } ; + + union { + __IOM uint32_t MODE; /*!< (@ 0x00000004) Offset:0x04 GPIO Port n Mode Register */ + + struct { + __IOM uint32_t MODE0 : 1; /*!< [0..0] Mode of Pn.0 */ + __IOM uint32_t MODE1 : 1; /*!< [1..1] Mode of Pn.1 */ + __IOM uint32_t MODE2 : 1; /*!< [2..2] Mode of Pn.2 */ + __IOM uint32_t MODE3 : 1; /*!< [3..3] Mode of Pn.3 */ + __IOM uint32_t MODE4 : 1; /*!< [4..4] Mode of Pn.4 */ + __IOM uint32_t MODE5 : 1; /*!< [5..5] Mode of Pn.5 */ + uint32_t : 26; + } MODE_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000008) Offset:0x08 GPIO Port n Configuration Register */ + + struct { + __IOM uint32_t CFG0 : 2; /*!< [1..0] Configuration of Pn.0 */ + __IOM uint32_t CFG1 : 2; /*!< [3..2] Configuration of Pn.1 */ + __IOM uint32_t CFG2 : 2; /*!< [5..4] Configuration of Pn.2 */ + __IOM uint32_t CFG3 : 2; /*!< [7..6] Configuration of Pn.3 */ + __IOM uint32_t CFG4 : 2; /*!< [9..8] Configuration of Pn.4 */ + __IOM uint32_t CFG5 : 2; /*!< [11..10] Configuration of Pn.5 */ + uint32_t : 20; + } CFG_b; + } ; + + union { + __IOM uint32_t IS; /*!< (@ 0x0000000C) Offset:0x0C GPIO Port n Interrupt Sense Register */ + + struct { + __IOM uint32_t IS0 : 1; /*!< [0..0] Interrupt on Pn.0 is event or edge sensitive */ + __IOM uint32_t IS1 : 1; /*!< [1..1] Interrupt on Pn.1 is event or edge sensitive */ + __IOM uint32_t IS2 : 1; /*!< [2..2] Interrupt on Pn.2 is event or edge sensitive */ + __IOM uint32_t IS3 : 1; /*!< [3..3] Interrupt on Pn.3 is event or edge sensitive */ + __IOM uint32_t IS4 : 1; /*!< [4..4] Interrupt on Pn.4 is event or edge sensitive */ + __IOM uint32_t IS5 : 1; /*!< [5..5] Interrupt on Pn.5 is event or edge sensitive */ + uint32_t : 26; + } IS_b; + } ; + + union { + __IOM uint32_t IBS; /*!< (@ 0x00000010) Offset:0x10 GPIO Port n Interrupt Both-edge Sense + Register */ + + struct { + __IOM uint32_t IBS0 : 1; /*!< [0..0] Interrupt on Pn.0 is triggered ob both edges */ + __IOM uint32_t IBS1 : 1; /*!< [1..1] Interrupt on Pn.1 is triggered ob both edges */ + __IOM uint32_t IBS2 : 1; /*!< [2..2] Interrupt on Pn.2 is triggered ob both edges */ + __IOM uint32_t IBS3 : 1; /*!< [3..3] Interrupt on Pn.3 is triggered ob both edges */ + __IOM uint32_t IBS4 : 1; /*!< [4..4] Interrupt on Pn.4 is triggered ob both edges */ + __IOM uint32_t IBS5 : 1; /*!< [5..5] Interrupt on Pn.5 is triggered ob both edges */ + uint32_t : 26; + } IBS_b; + } ; + + union { + __IOM uint32_t IEV; /*!< (@ 0x00000014) Offset:0x14 GPIO Port n Interrupt Event Register */ + + struct { + __IOM uint32_t IEV0 : 1; /*!< [0..0] Interrupt trigged evnet on Pn.0 */ + __IOM uint32_t IEV1 : 1; /*!< [1..1] Interrupt trigged evnet on Pn.1 */ + __IOM uint32_t IEV2 : 1; /*!< [2..2] Interrupt trigged evnet on Pn.2 */ + __IOM uint32_t IEV3 : 1; /*!< [3..3] Interrupt trigged evnet on Pn.3 */ + __IOM uint32_t IEV4 : 1; /*!< [4..4] Interrupt trigged evnet on Pn.4 */ + __IOM uint32_t IEV5 : 1; /*!< [5..5] Interrupt trigged evnet on Pn.5 */ + uint32_t : 26; + } IEV_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000018) Offset:0x18 GPIO Port n Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] Interrupt on Pn.0 enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] Interrupt on Pn.1 enable */ + __IOM uint32_t IE2 : 1; /*!< [2..2] Interrupt on Pn.2 enable */ + __IOM uint32_t IE3 : 1; /*!< [3..3] Interrupt on Pn.3 enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] Interrupt on Pn.4 enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] Interrupt on Pn.5 enable */ + uint32_t : 26; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x0000001C) Offset:0x1C GPIO Port n Raw Interrupt Status + Register */ + + struct { + __IM uint32_t IF0 : 1; /*!< [0..0] Pn.0 raw interrupt flag */ + __IM uint32_t IF1 : 1; /*!< [1..1] Pn.1 raw interrupt flag */ + __IM uint32_t IF2 : 1; /*!< [2..2] Pn.2 raw interrupt flag */ + __IM uint32_t IF3 : 1; /*!< [3..3] Pn.3 raw interrupt flag */ + __IM uint32_t IF4 : 1; /*!< [4..4] Pn.4 raw interrupt flag */ + __IM uint32_t IF5 : 1; /*!< [5..5] Pn.5 raw interrupt flag */ + uint32_t : 26; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000020) Offset:0x20 GPIO Port n Interrupt Clear Register */ + + struct { + __OM uint32_t IC0 : 1; /*!< [0..0] Pn.0 interrupt flag clear */ + __OM uint32_t IC1 : 1; /*!< [1..1] Pn.1 interrupt flag clear */ + __OM uint32_t IC2 : 1; /*!< [2..2] Pn.2 interrupt flag clear */ + __OM uint32_t IC3 : 1; /*!< [3..3] Pn.3 interrupt flag clear */ + __OM uint32_t IC4 : 1; /*!< [4..4] Pn.4 interrupt flag clear */ + __OM uint32_t IC5 : 1; /*!< [5..5] Pn.5 interrupt flag clear */ + uint32_t : 26; + } IC_b; + } ; + + union { + __OM uint32_t BSET; /*!< (@ 0x00000024) Offset:0x24 GPIO Port n Bits Set Operation Register */ + + struct { + __OM uint32_t BSET0 : 1; /*!< [0..0] Set Pn.0 */ + __OM uint32_t BSET1 : 1; /*!< [1..1] Set Pn.1 */ + __OM uint32_t BSET2 : 1; /*!< [2..2] Set Pn.2 */ + __OM uint32_t BSET3 : 1; /*!< [3..3] Set Pn.3 */ + __OM uint32_t BSET4 : 1; /*!< [4..4] Set Pn.4 */ + __OM uint32_t BSET5 : 1; /*!< [5..5] Set Pn.5 */ + uint32_t : 26; + } BSET_b; + } ; + + union { + __OM uint32_t BCLR; /*!< (@ 0x00000028) Offset:0x28 GPIO Port n Bits Clear Operation + Register */ + + struct { + __OM uint32_t BCLR0 : 1; /*!< [0..0] Clear Pn.0 */ + __OM uint32_t BCLR1 : 1; /*!< [1..1] Clear Pn.1 */ + __OM uint32_t BCLR2 : 1; /*!< [2..2] Clear Pn.2 */ + __OM uint32_t BCLR3 : 1; /*!< [3..3] Clear Pn.3 */ + __OM uint32_t BCLR4 : 1; /*!< [4..4] Clear Pn.4 */ + __OM uint32_t BCLR5 : 1; /*!< [5..5] Clear Pn.5 */ + uint32_t : 26; + } BCLR_b; + } ; +} SN_GPIO1_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO2 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose I/O (SN_GPIO2) + */ + +typedef struct { /*!< (@ 0x40048000) SN_GPIO2 Structure */ + + union { + __IOM uint32_t DATA; /*!< (@ 0x00000000) Offset:0x00 GPIO Port n Data Register */ + + struct { + __IOM uint32_t DATA0 : 1; /*!< [0..0] Data of Pn.0 */ + __IOM uint32_t DATA1 : 1; /*!< [1..1] Data of Pn.1 */ + __IOM uint32_t DATA2 : 1; /*!< [2..2] Data of Pn.2 */ + __IOM uint32_t DATA3 : 1; /*!< [3..3] Data of Pn.3 */ + __IOM uint32_t DATA4 : 1; /*!< [4..4] Data of Pn.4 */ + __IOM uint32_t DATA5 : 1; /*!< [5..5] Data of Pn.5 */ + __IOM uint32_t DATA6 : 1; /*!< [6..6] Data of Pn.6 */ + __IOM uint32_t DATA7 : 1; /*!< [7..7] Data of Pn.7 */ + __IOM uint32_t DATA8 : 1; /*!< [8..8] Data of Pn.8 */ + __IOM uint32_t DATA9 : 1; /*!< [9..9] Data of Pn.9 */ + __IOM uint32_t DATA10 : 1; /*!< [10..10] Data of Pn.10 */ + uint32_t : 21; + } DATA_b; + } ; + + union { + __IOM uint32_t MODE; /*!< (@ 0x00000004) Offset:0x04 GPIO Port n Mode Register */ + + struct { + __IOM uint32_t MODE0 : 1; /*!< [0..0] Mode of Pn.0 */ + __IOM uint32_t MODE1 : 1; /*!< [1..1] Mode of Pn.1 */ + __IOM uint32_t MODE2 : 1; /*!< [2..2] Mode of Pn.2 */ + __IOM uint32_t MODE3 : 1; /*!< [3..3] Mode of Pn.3 */ + __IOM uint32_t MODE4 : 1; /*!< [4..4] Mode of Pn.4 */ + __IOM uint32_t MODE5 : 1; /*!< [5..5] Mode of Pn.5 */ + __IOM uint32_t MODE6 : 1; /*!< [6..6] Mode of Pn.6 */ + __IOM uint32_t MODE7 : 1; /*!< [7..7] Mode of Pn.7 */ + __IOM uint32_t MODE8 : 1; /*!< [8..8] Mode of Pn.8 */ + __IOM uint32_t MODE9 : 1; /*!< [9..9] Mode of Pn.9 */ + __IOM uint32_t MODE10 : 1; /*!< [10..10] Mode of Pn.10 */ + uint32_t : 21; + } MODE_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000008) Offset:0x08 GPIO Port n Configuration Register */ + + struct { + __IOM uint32_t CFG0 : 2; /*!< [1..0] Configuration of Pn.0 */ + __IOM uint32_t CFG1 : 2; /*!< [3..2] Configuration of Pn.1 */ + __IOM uint32_t CFG2 : 2; /*!< [5..4] Configuration of Pn.2 */ + __IOM uint32_t CFG3 : 2; /*!< [7..6] Configuration of Pn.3 */ + __IOM uint32_t CFG4 : 2; /*!< [9..8] Configuration of Pn.4 */ + __IOM uint32_t CFG5 : 2; /*!< [11..10] Configuration of Pn.5 */ + __IOM uint32_t CFG6 : 2; /*!< [13..12] Configuration of Pn.6 */ + __IOM uint32_t CFG7 : 2; /*!< [15..14] Configuration of Pn.7 */ + __IOM uint32_t CFG8 : 2; /*!< [17..16] Configuration of Pn.8 */ + __IOM uint32_t CFG9 : 2; /*!< [19..18] Configuration of Pn.9 */ + __IOM uint32_t CFG10 : 2; /*!< [21..20] Configuration of Pn.10 */ + uint32_t : 10; + } CFG_b; + } ; + + union { + __IOM uint32_t IS; /*!< (@ 0x0000000C) Offset:0x0C GPIO Port n Interrupt Sense Register */ + + struct { + __IOM uint32_t IS0 : 1; /*!< [0..0] Interrupt on Pn.0 is event or edge sensitive */ + __IOM uint32_t IS1 : 1; /*!< [1..1] Interrupt on Pn.1 is event or edge sensitive */ + __IOM uint32_t IS2 : 1; /*!< [2..2] Interrupt on Pn.2 is event or edge sensitive */ + __IOM uint32_t IS3 : 1; /*!< [3..3] Interrupt on Pn.3 is event or edge sensitive */ + __IOM uint32_t IS4 : 1; /*!< [4..4] Interrupt on Pn.4 is event or edge sensitive */ + __IOM uint32_t IS5 : 1; /*!< [5..5] Interrupt on Pn.5 is event or edge sensitive */ + __IOM uint32_t IS6 : 1; /*!< [6..6] Interrupt on Pn.6 is event or edge sensitive */ + __IOM uint32_t IS7 : 1; /*!< [7..7] Interrupt on Pn.7 is event or edge sensitive */ + __IOM uint32_t IS8 : 1; /*!< [8..8] Interrupt on Pn.8 is event or edge sensitive */ + __IOM uint32_t IS9 : 1; /*!< [9..9] Interrupt on Pn.9 is event or edge sensitive */ + __IOM uint32_t IS10 : 1; /*!< [10..10] Interrupt on Pn.10 is event or edge sensitive */ + uint32_t : 21; + } IS_b; + } ; + + union { + __IOM uint32_t IBS; /*!< (@ 0x00000010) Offset:0x10 GPIO Port n Interrupt Both-edge Sense + Register */ + + struct { + __IOM uint32_t IBS0 : 1; /*!< [0..0] Interrupt on Pn.0 is triggered ob both edges */ + __IOM uint32_t IBS1 : 1; /*!< [1..1] Interrupt on Pn.1 is triggered ob both edges */ + __IOM uint32_t IBS2 : 1; /*!< [2..2] Interrupt on Pn.2 is triggered ob both edges */ + __IOM uint32_t IBS3 : 1; /*!< [3..3] Interrupt on Pn.3 is triggered ob both edges */ + __IOM uint32_t IBS4 : 1; /*!< [4..4] Interrupt on Pn.4 is triggered ob both edges */ + __IOM uint32_t IBS5 : 1; /*!< [5..5] Interrupt on Pn.5 is triggered ob both edges */ + __IOM uint32_t IBS6 : 1; /*!< [6..6] Interrupt on Pn.6 is triggered ob both edges */ + __IOM uint32_t IBS7 : 1; /*!< [7..7] Interrupt on Pn.7 is triggered ob both edges */ + __IOM uint32_t IBS8 : 1; /*!< [8..8] Interrupt on Pn.8 is triggered ob both edges */ + __IOM uint32_t IBS9 : 1; /*!< [9..9] Interrupt on Pn.9 is triggered ob both edges */ + __IOM uint32_t IBS10 : 1; /*!< [10..10] Interrupt on Pn.10 is triggered ob both edges */ + uint32_t : 21; + } IBS_b; + } ; + + union { + __IOM uint32_t IEV; /*!< (@ 0x00000014) Offset:0x14 GPIO Port n Interrupt Event Register */ + + struct { + __IOM uint32_t IEV0 : 1; /*!< [0..0] Interrupt trigged evnet on Pn.0 */ + __IOM uint32_t IEV1 : 1; /*!< [1..1] Interrupt trigged evnet on Pn.1 */ + __IOM uint32_t IEV2 : 1; /*!< [2..2] Interrupt trigged evnet on Pn.2 */ + __IOM uint32_t IEV3 : 1; /*!< [3..3] Interrupt trigged evnet on Pn.3 */ + __IOM uint32_t IEV4 : 1; /*!< [4..4] Interrupt trigged evnet on Pn.4 */ + __IOM uint32_t IEV5 : 1; /*!< [5..5] Interrupt trigged evnet on Pn.5 */ + __IOM uint32_t IEV6 : 1; /*!< [6..6] Interrupt trigged evnet on Pn.6 */ + __IOM uint32_t IEV7 : 1; /*!< [7..7] Interrupt trigged evnet on Pn.7 */ + __IOM uint32_t IEV8 : 1; /*!< [8..8] Interrupt trigged evnet on Pn.8 */ + __IOM uint32_t IEV9 : 1; /*!< [9..9] Interrupt trigged evnet on Pn.9 */ + __IOM uint32_t IEV10 : 1; /*!< [10..10] Interrupt trigged evnet on Pn.10 */ + uint32_t : 21; + } IEV_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000018) Offset:0x18 GPIO Port n Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] Interrupt on Pn.0 enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] Interrupt on Pn.1 enable */ + __IOM uint32_t IE2 : 1; /*!< [2..2] Interrupt on Pn.2 enable */ + __IOM uint32_t IE3 : 1; /*!< [3..3] Interrupt on Pn.3 enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] Interrupt on Pn.4 enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] Interrupt on Pn.5 enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] Interrupt on Pn.6 enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] Interrupt on Pn.7 enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] Interrupt on Pn.8 enable */ + __IOM uint32_t IE9 : 1; /*!< [9..9] Interrupt on Pn.9 enable */ + __IOM uint32_t IE10 : 1; /*!< [10..10] Interrupt on Pn.10 enable */ + uint32_t : 21; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x0000001C) Offset:0x1C GPIO Port n Raw Interrupt Status + Register */ + + struct { + __IM uint32_t IF0 : 1; /*!< [0..0] Pn.0 raw interrupt flag */ + __IM uint32_t IF1 : 1; /*!< [1..1] Pn.1 raw interrupt flag */ + __IM uint32_t IF2 : 1; /*!< [2..2] Pn.2 raw interrupt flag */ + __IM uint32_t IF3 : 1; /*!< [3..3] Pn.3 raw interrupt flag */ + __IM uint32_t IF4 : 1; /*!< [4..4] Pn.4 raw interrupt flag */ + __IM uint32_t IF5 : 1; /*!< [5..5] Pn.5 raw interrupt flag */ + __IM uint32_t IF6 : 1; /*!< [6..6] Pn.6 raw interrupt flag */ + __IM uint32_t IF7 : 1; /*!< [7..7] Pn.7 raw interrupt flag */ + __IM uint32_t IF8 : 1; /*!< [8..8] Pn.8 raw interrupt flag */ + __IM uint32_t IF9 : 1; /*!< [9..9] Pn.9 raw interrupt flag */ + __IM uint32_t IF10 : 1; /*!< [10..10] Pn.10 raw interrupt flag */ + uint32_t : 21; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000020) Offset:0x20 GPIO Port n Interrupt Clear Register */ + + struct { + __OM uint32_t IC0 : 1; /*!< [0..0] Pn.0 interrupt flag clear */ + __OM uint32_t IC1 : 1; /*!< [1..1] Pn.1 interrupt flag clear */ + __OM uint32_t IC2 : 1; /*!< [2..2] Pn.2 interrupt flag clear */ + __OM uint32_t IC3 : 1; /*!< [3..3] Pn.3 interrupt flag clear */ + __OM uint32_t IC4 : 1; /*!< [4..4] Pn.4 interrupt flag clear */ + __OM uint32_t IC5 : 1; /*!< [5..5] Pn.5 interrupt flag clear */ + __OM uint32_t IC6 : 1; /*!< [6..6] Pn.6 interrupt flag clear */ + __OM uint32_t IC7 : 1; /*!< [7..7] Pn.7 interrupt flag clear */ + __OM uint32_t IC8 : 1; /*!< [8..8] Pn.8 interrupt flag clear */ + __OM uint32_t IC9 : 1; /*!< [9..9] Pn.9 interrupt flag clear */ + __OM uint32_t IC10 : 1; /*!< [10..10] Pn.10 interrupt flag clear */ + uint32_t : 21; + } IC_b; + } ; + + union { + __OM uint32_t BSET; /*!< (@ 0x00000024) Offset:0x24 GPIO Port n Bits Set Operation Register */ + + struct { + __OM uint32_t BSET0 : 1; /*!< [0..0] Set Pn.0 */ + __OM uint32_t BSET1 : 1; /*!< [1..1] Set Pn.1 */ + __OM uint32_t BSET2 : 1; /*!< [2..2] Set Pn.2 */ + __OM uint32_t BSET3 : 1; /*!< [3..3] Set Pn.3 */ + __OM uint32_t BSET4 : 1; /*!< [4..4] Set Pn.4 */ + __OM uint32_t BSET5 : 1; /*!< [5..5] Set Pn.5 */ + __OM uint32_t BSET6 : 1; /*!< [6..6] Set Pn.6 */ + __OM uint32_t BSET7 : 1; /*!< [7..7] Set Pn.7 */ + __OM uint32_t BSET8 : 1; /*!< [8..8] Set Pn.8 */ + __OM uint32_t BSET9 : 1; /*!< [9..9] Set Pn.9 */ + __OM uint32_t BSET10 : 1; /*!< [10..10] Set Pn.10 */ + uint32_t : 21; + } BSET_b; + } ; + + union { + __OM uint32_t BCLR; /*!< (@ 0x00000028) Offset:0x28 GPIO Port n Bits Clear Operation + Register */ + + struct { + __OM uint32_t BCLR0 : 1; /*!< [0..0] Clear Pn.0 */ + __OM uint32_t BCLR1 : 1; /*!< [1..1] Clear Pn.1 */ + __OM uint32_t BCLR2 : 1; /*!< [2..2] Clear Pn.2 */ + __OM uint32_t BCLR3 : 1; /*!< [3..3] Clear Pn.3 */ + __OM uint32_t BCLR4 : 1; /*!< [4..4] Clear Pn.4 */ + __OM uint32_t BCLR5 : 1; /*!< [5..5] Clear Pn.5 */ + __OM uint32_t BCLR6 : 1; /*!< [6..6] Clear Pn.6 */ + __OM uint32_t BCLR7 : 1; /*!< [7..7] Clear Pn.7 */ + __OM uint32_t BCLR8 : 1; /*!< [8..8] Clear Pn.8 */ + __OM uint32_t BCLR9 : 1; /*!< [9..9] Clear Pn.9 */ + __OM uint32_t BCLR10 : 1; /*!< [10..10] Clear Pn.10 */ + uint32_t : 21; + } BCLR_b; + } ; +} SN_GPIO2_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO3 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose I/O (SN_GPIO3) + */ + +typedef struct { /*!< (@ 0x4004A000) SN_GPIO3 Structure */ + + union { + __IOM uint32_t DATA; /*!< (@ 0x00000000) Offset:0x00 GPIO Port n Data Register */ + + struct { + __IOM uint32_t DATA0 : 1; /*!< [0..0] Data of Pn.0 */ + __IOM uint32_t DATA1 : 1; /*!< [1..1] Data of Pn.1 */ + __IOM uint32_t DATA2 : 1; /*!< [2..2] Data of Pn.2 */ + __IOM uint32_t DATA3 : 1; /*!< [3..3] Data of Pn.3 */ + __IOM uint32_t DATA4 : 1; /*!< [4..4] Data of Pn.4 */ + __IOM uint32_t DATA5 : 1; /*!< [5..5] Data of Pn.5 */ + __IOM uint32_t DATA6 : 1; /*!< [6..6] Data of Pn.6 */ + __IOM uint32_t DATA7 : 1; /*!< [7..7] Data of Pn.7 */ + __IOM uint32_t DATA8 : 1; /*!< [8..8] Data of Pn.8 */ + uint32_t : 23; + } DATA_b; + } ; + + union { + __IOM uint32_t MODE; /*!< (@ 0x00000004) Offset:0x04 GPIO Port n Mode Register */ + + struct { + __IOM uint32_t MODE0 : 1; /*!< [0..0] Mode of Pn.0 */ + __IOM uint32_t MODE1 : 1; /*!< [1..1] Mode of Pn.1 */ + __IOM uint32_t MODE2 : 1; /*!< [2..2] Mode of Pn.2 */ + __IOM uint32_t MODE3 : 1; /*!< [3..3] Mode of Pn.3 */ + __IOM uint32_t MODE4 : 1; /*!< [4..4] Mode of Pn.4 */ + __IOM uint32_t MODE5 : 1; /*!< [5..5] Mode of Pn.5 */ + __IOM uint32_t MODE6 : 1; /*!< [6..6] Mode of Pn.6 */ + __IOM uint32_t MODE7 : 1; /*!< [7..7] Mode of Pn.7 */ + __IOM uint32_t MODE8 : 1; /*!< [8..8] Mode of Pn.8 */ + uint32_t : 23; + } MODE_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000008) Offset:0x08 GPIO Port n Configuration Register */ + + struct { + __IOM uint32_t CFG0 : 2; /*!< [1..0] Configuration of Pn.0 */ + __IOM uint32_t CFG1 : 2; /*!< [3..2] Configuration of Pn.1 */ + __IOM uint32_t CFG2 : 2; /*!< [5..4] Configuration of Pn.2 */ + __IOM uint32_t CFG3 : 2; /*!< [7..6] Configuration of Pn.3 */ + __IOM uint32_t CFG4 : 2; /*!< [9..8] Configuration of Pn.4 */ + __IOM uint32_t CFG5 : 2; /*!< [11..10] Configuration of Pn.5 */ + __IOM uint32_t CFG6 : 2; /*!< [13..12] Configuration of Pn.6 */ + __IOM uint32_t CFG7 : 2; /*!< [15..14] Configuration of Pn.7 */ + __IOM uint32_t CFG8 : 2; /*!< [17..16] Configuration of Pn.8 */ + uint32_t : 14; + } CFG_b; + } ; + + union { + __IOM uint32_t IS; /*!< (@ 0x0000000C) Offset:0x0C GPIO Port n Interrupt Sense Register */ + + struct { + __IOM uint32_t IS0 : 1; /*!< [0..0] Interrupt on Pn.0 is event or edge sensitive */ + __IOM uint32_t IS1 : 1; /*!< [1..1] Interrupt on Pn.1 is event or edge sensitive */ + __IOM uint32_t IS2 : 1; /*!< [2..2] Interrupt on Pn.2 is event or edge sensitive */ + __IOM uint32_t IS3 : 1; /*!< [3..3] Interrupt on Pn.3 is event or edge sensitive */ + __IOM uint32_t IS4 : 1; /*!< [4..4] Interrupt on Pn.4 is event or edge sensitive */ + __IOM uint32_t IS5 : 1; /*!< [5..5] Interrupt on Pn.5 is event or edge sensitive */ + __IOM uint32_t IS6 : 1; /*!< [6..6] Interrupt on Pn.6 is event or edge sensitive */ + __IOM uint32_t IS7 : 1; /*!< [7..7] Interrupt on Pn.7 is event or edge sensitive */ + __IOM uint32_t IS8 : 1; /*!< [8..8] Interrupt on Pn.8 is event or edge sensitive */ + uint32_t : 23; + } IS_b; + } ; + + union { + __IOM uint32_t IBS; /*!< (@ 0x00000010) Offset:0x10 GPIO Port n Interrupt Both-edge Sense + Register */ + + struct { + __IOM uint32_t IBS0 : 1; /*!< [0..0] Interrupt on Pn.0 is triggered ob both edges */ + __IOM uint32_t IBS1 : 1; /*!< [1..1] Interrupt on Pn.1 is triggered ob both edges */ + __IOM uint32_t IBS2 : 1; /*!< [2..2] Interrupt on Pn.2 is triggered ob both edges */ + __IOM uint32_t IBS3 : 1; /*!< [3..3] Interrupt on Pn.3 is triggered ob both edges */ + __IOM uint32_t IBS4 : 1; /*!< [4..4] Interrupt on Pn.4 is triggered ob both edges */ + __IOM uint32_t IBS5 : 1; /*!< [5..5] Interrupt on Pn.5 is triggered ob both edges */ + __IOM uint32_t IBS6 : 1; /*!< [6..6] Interrupt on Pn.6 is triggered ob both edges */ + __IOM uint32_t IBS7 : 1; /*!< [7..7] Interrupt on Pn.7 is triggered ob both edges */ + __IOM uint32_t IBS8 : 1; /*!< [8..8] Interrupt on Pn.8 is triggered ob both edges */ + uint32_t : 23; + } IBS_b; + } ; + + union { + __IOM uint32_t IEV; /*!< (@ 0x00000014) Offset:0x14 GPIO Port n Interrupt Event Register */ + + struct { + __IOM uint32_t IEV0 : 1; /*!< [0..0] Interrupt trigged evnet on Pn.0 */ + __IOM uint32_t IEV1 : 1; /*!< [1..1] Interrupt trigged evnet on Pn.1 */ + __IOM uint32_t IEV2 : 1; /*!< [2..2] Interrupt trigged evnet on Pn.2 */ + __IOM uint32_t IEV3 : 1; /*!< [3..3] Interrupt trigged evnet on Pn.3 */ + __IOM uint32_t IEV4 : 1; /*!< [4..4] Interrupt trigged evnet on Pn.4 */ + __IOM uint32_t IEV5 : 1; /*!< [5..5] Interrupt trigged evnet on Pn.5 */ + __IOM uint32_t IEV6 : 1; /*!< [6..6] Interrupt trigged evnet on Pn.6 */ + __IOM uint32_t IEV7 : 1; /*!< [7..7] Interrupt trigged evnet on Pn.7 */ + __IOM uint32_t IEV8 : 1; /*!< [8..8] Interrupt trigged evnet on Pn.8 */ + uint32_t : 23; + } IEV_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000018) Offset:0x18 GPIO Port n Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] Interrupt on Pn.0 enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] Interrupt on Pn.1 enable */ + __IOM uint32_t IE2 : 1; /*!< [2..2] Interrupt on Pn.2 enable */ + __IOM uint32_t IE3 : 1; /*!< [3..3] Interrupt on Pn.3 enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] Interrupt on Pn.4 enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] Interrupt on Pn.5 enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] Interrupt on Pn.6 enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] Interrupt on Pn.7 enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] Interrupt on Pn.8 enable */ + uint32_t : 23; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x0000001C) Offset:0x1C GPIO Port n Raw Interrupt Status + Register */ + + struct { + __IM uint32_t IF0 : 1; /*!< [0..0] Pn.0 raw interrupt flag */ + __IM uint32_t IF1 : 1; /*!< [1..1] Pn.1 raw interrupt flag */ + __IM uint32_t IF2 : 1; /*!< [2..2] Pn.2 raw interrupt flag */ + __IM uint32_t IF3 : 1; /*!< [3..3] Pn.3 raw interrupt flag */ + __IM uint32_t IF4 : 1; /*!< [4..4] Pn.4 raw interrupt flag */ + __IM uint32_t IF5 : 1; /*!< [5..5] Pn.5 raw interrupt flag */ + __IM uint32_t IF6 : 1; /*!< [6..6] Pn.6 raw interrupt flag */ + __IM uint32_t IF7 : 1; /*!< [7..7] Pn.7 raw interrupt flag */ + __IM uint32_t IF8 : 1; /*!< [8..8] Pn.8 raw interrupt flag */ + uint32_t : 23; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000020) Offset:0x20 GPIO Port n Interrupt Clear Register */ + + struct { + __OM uint32_t IC0 : 1; /*!< [0..0] Pn.0 interrupt flag clear */ + __OM uint32_t IC1 : 1; /*!< [1..1] Pn.1 interrupt flag clear */ + __OM uint32_t IC2 : 1; /*!< [2..2] Pn.2 interrupt flag clear */ + __OM uint32_t IC3 : 1; /*!< [3..3] Pn.3 interrupt flag clear */ + __OM uint32_t IC4 : 1; /*!< [4..4] Pn.4 interrupt flag clear */ + __OM uint32_t IC5 : 1; /*!< [5..5] Pn.5 interrupt flag clear */ + __OM uint32_t IC6 : 1; /*!< [6..6] Pn.6 interrupt flag clear */ + __OM uint32_t IC7 : 1; /*!< [7..7] Pn.7 interrupt flag clear */ + __OM uint32_t IC8 : 1; /*!< [8..8] Pn.8 interrupt flag clear */ + uint32_t : 23; + } IC_b; + } ; + + union { + __OM uint32_t BSET; /*!< (@ 0x00000024) Offset:0x24 GPIO Port n Bits Set Operation Register */ + + struct { + __OM uint32_t BSET0 : 1; /*!< [0..0] Set Pn.0 */ + __OM uint32_t BSET1 : 1; /*!< [1..1] Set Pn.1 */ + __OM uint32_t BSET2 : 1; /*!< [2..2] Set Pn.2 */ + __OM uint32_t BSET3 : 1; /*!< [3..3] Set Pn.3 */ + __OM uint32_t BSET4 : 1; /*!< [4..4] Set Pn.4 */ + __OM uint32_t BSET5 : 1; /*!< [5..5] Set Pn.5 */ + __OM uint32_t BSET6 : 1; /*!< [6..6] Set Pn.6 */ + __OM uint32_t BSET7 : 1; /*!< [7..7] Set Pn.7 */ + __OM uint32_t BSET8 : 1; /*!< [8..8] Set Pn.8 */ + uint32_t : 23; + } BSET_b; + } ; + + union { + __OM uint32_t BCLR; /*!< (@ 0x00000028) Offset:0x28 GPIO Port n Bits Clear Operation + Register */ + + struct { + __OM uint32_t BCLR0 : 1; /*!< [0..0] Clear Pn.0 */ + __OM uint32_t BCLR1 : 1; /*!< [1..1] Clear Pn.1 */ + __OM uint32_t BCLR2 : 1; /*!< [2..2] Clear Pn.2 */ + __OM uint32_t BCLR3 : 1; /*!< [3..3] Clear Pn.3 */ + __OM uint32_t BCLR4 : 1; /*!< [4..4] Clear Pn.4 */ + __OM uint32_t BCLR5 : 1; /*!< [5..5] Clear Pn.5 */ + __OM uint32_t BCLR6 : 1; /*!< [6..6] Clear Pn.6 */ + __OM uint32_t BCLR7 : 1; /*!< [7..7] Clear Pn.7 */ + __OM uint32_t BCLR8 : 1; /*!< [8..8] Clear Pn.8 */ + uint32_t : 23; + } BCLR_b; + } ; +} SN_GPIO3_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (SN_WDT) + */ + +typedef struct { /*!< (@ 0x40010000) SN_WDT Structure */ + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000000) Offset:0x00 WDT Configuration Register */ + + struct { + __IOM uint32_t WDTEN : 1; /*!< [0..0] WDT enable */ + __IOM uint32_t WDTIE : 1; /*!< [1..1] WDT interrupt enable */ + __IOM uint32_t WDTINT : 1; /*!< [2..2] WDT interrupt flag */ + uint32_t : 13; + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } CFG_b; + } ; + + union { + __IOM uint32_t CLKSOURCE; /*!< (@ 0x00000004) Offset:0x04 WDT Clock Source Register */ + + struct { + __IOM uint32_t CLKSEL : 2; /*!< [1..0] WDT clock source */ + uint32_t : 14; + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } CLKSOURCE_b; + } ; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000008) Offset:0x08 WDT Timer Constant Register */ + + struct { + __IOM uint32_t TC : 8; /*!< [7..0] Watchdog timer constant reload value */ + uint32_t : 8; + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } TC_b; + } ; + + union { + __OM uint32_t FEED; /*!< (@ 0x0000000C) Offset:0x0C WDT Feed Register */ + + struct { + __OM uint32_t FV : 16; /*!< [15..0] Watchdog feed value */ + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } FEED_b; + } ; +} SN_WDT_Type; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CT16B0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 16-bit Timer 0 with Capture function (SN_CT16B0) + */ + +typedef struct { /*!< (@ 0x40000000) SN_CT16B0 Structure */ + + union { + __IOM uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT16Bn Timer Control Register */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] Counter enable */ + __IOM uint32_t CRST : 1; /*!< [1..1] Counter Reset */ + uint32_t : 30; + } TMRCTRL_b; + } ; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT16Bn Timer Counter Register */ + + struct { + __IOM uint32_t TC : 16; /*!< [15..0] Timer Counter */ + uint32_t : 16; + } TC_b; + } ; + + union { + __IOM uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT16Bn Prescale Register */ + + struct { + __IOM uint32_t PRE : 8; /*!< [7..0] Prescaler */ + uint32_t : 24; + } PRE_b; + } ; + + union { + __IOM uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT16Bn Prescale Counter Register */ + + struct { + __IOM uint32_t PC : 8; /*!< [7..0] Prescaler Counter */ + uint32_t : 24; + } PC_b; + } ; + + union { + __IOM uint32_t CNTCTRL; /*!< (@ 0x00000010) Offset:0x10 CT16Bn Counter Control Register */ + + struct { + __IOM uint32_t CTM : 2; /*!< [1..0] Counter/Timer Mode */ + __IOM uint32_t CIS : 2; /*!< [3..2] Counter Input Select */ + uint32_t : 28; + } CNTCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT16Bn Match Control Register */ + + struct { + __IOM uint32_t MR0IE : 1; /*!< [0..0] Enable generating an interrupt when MR0 matches TC */ + __IOM uint32_t MR0RST : 1; /*!< [1..1] Enable reset TC when MR0 matches TC */ + __IOM uint32_t MR0STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR0 matches TC */ + uint32_t : 29; + } MCTRL_b; + } ; + __IM uint32_t RESERVED[2]; + __IOM uint32_t MR0; /*!< (@ 0x00000020) Offset:0x20 CT16Bn MR0 Register */ + __IM uint32_t RESERVED1[23]; + + union { + __IOM uint32_t CAPCTRL; /*!< (@ 0x00000080) Offset:0x80 CT16Bn Capture Control Register */ + + struct { + __IOM uint32_t CAP0RE : 1; /*!< [0..0] Capture on CT16Bn_CAP0 rising edge */ + __IOM uint32_t CAP0FE : 1; /*!< [1..1] Capture on CT16Bn_CAP0 falling edge */ + __IOM uint32_t CAP0IE : 1; /*!< [2..2] Interrupt on CT16Bn_CAP0 event */ + __IOM uint32_t CAP0EN : 1; /*!< [3..3] CAP0 function enable */ + uint32_t : 28; + } CAPCTRL_b; + } ; + + union { + __IM uint32_t CAP0; /*!< (@ 0x00000084) Offset:0x84 CT16Bn CAP0 Register */ + + struct { + __IM uint32_t CAP0 : 16; /*!< [15..0] Timer counter capture value */ + uint32_t : 16; + } CAP0_b; + } ; + __IM uint32_t RESERVED2[7]; + + union { + __IM uint32_t RIS; /*!< (@ 0x000000A4) Offset:0xA4 CT16Bn Raw Interrupt Status Register */ + + struct { + __IM uint32_t MR0IF : 1; /*!< [0..0] Match channel 0 interrupt flag */ + uint32_t : 23; + __IM uint32_t CAP0IF : 1; /*!< [24..24] Capture channel 0 interrupt flag */ + uint32_t : 7; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x000000A8) Offset:0xA8 CT16Bn Interrupt Clear Register */ + + struct { + __OM uint32_t MR0IC : 1; /*!< [0..0] MR0IF clear bit */ + uint32_t : 23; + __OM uint32_t CAP0IC : 1; /*!< [24..24] CAP0IF clear bit */ + uint32_t : 7; + } IC_b; + } ; +} SN_CT16B0_Type; /*!< Size = 172 (0xac) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CT16B1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 16-bit Timer 1 with Capture function (SN_CT16B1) + */ + +typedef struct { /*!< (@ 0x40002000) SN_CT16B1 Structure */ + + union { + __IOM uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT16Bn Timer Control Register */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] Counter enable */ + __IOM uint32_t CRST : 1; /*!< [1..1] Counter Reset */ + uint32_t : 30; + } TMRCTRL_b; + } ; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT16Bn Timer Counter Register */ + + struct { + __IOM uint32_t TC : 16; /*!< [15..0] Timer Counter */ + uint32_t : 16; + } TC_b; + } ; + + union { + __IOM uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT16Bn Prescale Register */ + + struct { + __IOM uint32_t PRE : 8; /*!< [7..0] Prescaler */ + uint32_t : 24; + } PRE_b; + } ; + + union { + __IOM uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT16Bn Prescale Counter Register */ + + struct { + __IOM uint32_t PC : 8; /*!< [7..0] Prescaler Counter */ + uint32_t : 24; + } PC_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT16Bn Match Control Register */ + + struct { + __IOM uint32_t MR0IE : 1; /*!< [0..0] Enable generating an interrupt when MR0 matches TC */ + __IOM uint32_t MR0RST : 1; /*!< [1..1] Enable reset TC when MR0 matches TC */ + __IOM uint32_t MR0STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR0 matches TC */ + __IOM uint32_t MR1IE : 1; /*!< [3..3] Enable generating an interrupt when MR1 matches TC */ + __IOM uint32_t MR1RST : 1; /*!< [4..4] Enable reset TC when MR1 matches TC */ + __IOM uint32_t MR1STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR1 matches TC */ + __IOM uint32_t MR2IE : 1; /*!< [6..6] Enable generating an interrupt when MR2 matches TC */ + __IOM uint32_t MR2RST : 1; /*!< [7..7] Enable reset TC when MR2 matches TC */ + __IOM uint32_t MR2STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR2 matches TC */ + __IOM uint32_t MR3IE : 1; /*!< [9..9] Enable generating an interrupt when MR3 matches TC */ + __IOM uint32_t MR3RST : 1; /*!< [10..10] Enable reset TC when MR3 matches TC */ + __IOM uint32_t MR3STOP : 1; /*!< [11..11] Stop TC and PC and clear CEN bit when MR3 matches TC */ + __IOM uint32_t MR4IE : 1; /*!< [12..12] Enable generating an interrupt when MR4 matches TC */ + __IOM uint32_t MR4RST : 1; /*!< [13..13] Enable reset TC when MR4 matches TC */ + __IOM uint32_t MR4STOP : 1; /*!< [14..14] Stop TC and PC and clear CEN bit when MR4 matches TC */ + __IOM uint32_t MR5IE : 1; /*!< [15..15] Enable generating an interrupt when MR5 matches TC */ + __IOM uint32_t MR5RST : 1; /*!< [16..16] Enable reset TC when MR5 matches TC */ + __IOM uint32_t MR5STOP : 1; /*!< [17..17] Stop TC and PC and clear CEN bit when MR5 matches TC */ + __IOM uint32_t MR6IE : 1; /*!< [18..18] Enable generating an interrupt when MR6 matches TC */ + __IOM uint32_t MR6RST : 1; /*!< [19..19] Enable reset TC when MR6 matches TC */ + __IOM uint32_t MR6STOP : 1; /*!< [20..20] Stop TC and PC and clear CEN bit when MR6 matches TC */ + __IOM uint32_t MR7IE : 1; /*!< [21..21] Enable generating an interrupt when MR7 matches TC */ + __IOM uint32_t MR7RST : 1; /*!< [22..22] Enable reset TC when MR7 matches TC */ + __IOM uint32_t MR7STOP : 1; /*!< [23..23] Stop TC and PC and clear CEN bit when MR7 matches TC */ + __IOM uint32_t MR8IE : 1; /*!< [24..24] Enable generating an interrupt when MR8 matches TC */ + __IOM uint32_t MR8RST : 1; /*!< [25..25] Enable reset TC when MR8 matches TC */ + __IOM uint32_t MR8STOP : 1; /*!< [26..26] Stop TC and PC and clear CEN bit when MR8 matches TC */ + __IOM uint32_t MR9IE : 1; /*!< [27..27] Enable generating an interrupt based on CM[2:0] when + MR9 matches the value in the TC */ + __IOM uint32_t MR9RST : 1; /*!< [28..28] Enable reset TC when MR9 matches TC */ + __IOM uint32_t MR9STOP : 1; /*!< [29..29] Stop TC and PC and clear CEN bit when MR9 matches TC */ + uint32_t : 2; + } MCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL2; /*!< (@ 0x00000018) Offset:0x18 CT16Bn Match Control Register */ + + struct { + __IOM uint32_t MR10IE : 1; /*!< [0..0] Enable generating an interrupt when MR10 matches TC */ + __IOM uint32_t MR10RST : 1; /*!< [1..1] Enable reset TC when MR10 matches TC */ + __IOM uint32_t MR10STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR10 matches TC */ + __IOM uint32_t MR11IE : 1; /*!< [3..3] Enable generating an interrupt when MR11 matches TC */ + __IOM uint32_t MR11RST : 1; /*!< [4..4] Enable reset TC when MR11 matches TC */ + __IOM uint32_t MR11STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR11 matches TC */ + __IOM uint32_t MR12IE : 1; /*!< [6..6] Enable generating an interrupt when MR12 matches TC */ + __IOM uint32_t MR12RST : 1; /*!< [7..7] Enable reset TC when MR12 matches TC */ + __IOM uint32_t MR12STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR12 matches TC */ + __IOM uint32_t MR13IE : 1; /*!< [9..9] Enable generating an interrupt when MR13 matches TC */ + __IOM uint32_t MR13RST : 1; /*!< [10..10] Enable reset TC when MR13 matches TC */ + __IOM uint32_t MR13STOP : 1; /*!< [11..11] Stop TC and PC and clear CEN bit when MR13 matches + TC */ + __IOM uint32_t MR14IE : 1; /*!< [12..12] Enable generating an interrupt when MR14 matches TC */ + __IOM uint32_t MR14RST : 1; /*!< [13..13] Enable reset TC when MR14 matches TC */ + __IOM uint32_t MR14STOP : 1; /*!< [14..14] Stop TC and PC and clear CEN bit when MR14 matches + TC */ + __IOM uint32_t MR15IE : 1; /*!< [15..15] Enable generating an interrupt when MR15 matches TC */ + __IOM uint32_t MR15RST : 1; /*!< [16..16] Enable reset TC when MR15 matches TC */ + __IOM uint32_t MR15STOP : 1; /*!< [17..17] Stop TC and PC and clear CEN bit when MR15 matches + TC */ + __IOM uint32_t MR16IE : 1; /*!< [18..18] Enable generating an interrupt when MR16 matches TC */ + __IOM uint32_t MR16RST : 1; /*!< [19..19] Enable reset TC when MR16 matches TC */ + __IOM uint32_t MR16STOP : 1; /*!< [20..20] Stop TC and PC and clear CEN bit when MR16 matches + TC */ + __IOM uint32_t MR17IE : 1; /*!< [21..21] Enable generating an interrupt when MR17 matches TC */ + __IOM uint32_t MR17RST : 1; /*!< [22..22] Enable reset TC when MR17 matches TC */ + __IOM uint32_t MR17STOP : 1; /*!< [23..23] Stop TC and PC and clear CEN bit when MR17 matches + TC */ + __IOM uint32_t MR18IE : 1; /*!< [24..24] Enable generating an interrupt when MR18 matches TC */ + __IOM uint32_t MR18RST : 1; /*!< [25..25] Enable reset TC when MR18 matches TC */ + __IOM uint32_t MR18STOP : 1; /*!< [26..26] Stop TC and PC and clear CEN bit when MR18 matches + TC */ + __IOM uint32_t MR19IE : 1; /*!< [27..27] Enable generating an interrupt based on CM[2:0] when + MR19 matches the value in the TC */ + __IOM uint32_t MR19RST : 1; /*!< [28..28] Enable reset TC when MR19 matches TC */ + __IOM uint32_t MR19STOP : 1; /*!< [29..29] Stop TC and PC and clear CEN bit when MR19 matches + TC */ + uint32_t : 2; + } MCTRL2_b; + } ; + + union { + __IOM uint32_t MCTRL3; /*!< (@ 0x0000001C) Offset:0x1C CT16Bn Match Control Register */ + + struct { + __IOM uint32_t MR20IE : 1; /*!< [0..0] Enable generating an interrupt when MR20 matches TC */ + __IOM uint32_t MR20RST : 1; /*!< [1..1] Enable reset TC when MR20 matches TC */ + __IOM uint32_t MR20STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR20 matches TC */ + __IOM uint32_t MR21IE : 1; /*!< [3..3] Enable generating an interrupt when MR21 matches TC */ + __IOM uint32_t MR21RST : 1; /*!< [4..4] Enable reset TC when MR21 matches TC */ + __IOM uint32_t MR21STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR21 matches TC */ + __IOM uint32_t MR22IE : 1; /*!< [6..6] Enable generating an interrupt when MR22 matches TC */ + __IOM uint32_t MR22RST : 1; /*!< [7..7] Enable reset TC when MR22 matches TC */ + __IOM uint32_t MR22STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR22 matches TC */ + __IOM uint32_t MR23IE : 1; /*!< [9..9] Enable generating an interrupt when MR23 matches TC */ + __IOM uint32_t MR23RST : 1; /*!< [10..10] Enable reset TC when MR23 matches TC */ + __IOM uint32_t MR23STOP : 1; /*!< [11..11] Stop TC and PC and clear CEN bit when MR23 matches + TC */ + uint32_t : 20; + } MCTRL3_b; + } ; + __IOM uint32_t MR0; /*!< (@ 0x00000020) Offset:0x20 CT16Bn MR0 Register */ + __IOM uint32_t MR1; /*!< (@ 0x00000024) Offset:0x24 CT16Bn MR1 Register */ + __IOM uint32_t MR2; /*!< (@ 0x00000028) Offset:0x28 CT16Bn MR2 Register */ + __IOM uint32_t MR3; /*!< (@ 0x0000002C) Offset:0x2C CT16Bn MR3 Register */ + __IOM uint32_t MR4; /*!< (@ 0x00000030) Offset:0x30 CT16Bn MR4 Register */ + __IOM uint32_t MR5; /*!< (@ 0x00000034) Offset:0x34 CT16Bn MR5 Register */ + __IOM uint32_t MR6; /*!< (@ 0x00000038) Offset:0x38 CT16Bn MR6 Register */ + __IOM uint32_t MR7; /*!< (@ 0x0000003C) Offset:0x3C CT16Bn MR7 Register */ + __IOM uint32_t MR8; /*!< (@ 0x00000040) Offset:0x40 CT16Bn MR8 Register */ + __IOM uint32_t MR9; /*!< (@ 0x00000044) Offset:0x44 CT16Bn MR9 Register */ + __IOM uint32_t MR10; /*!< (@ 0x00000048) Offset:0x48 CT16Bn MR10 Register */ + __IOM uint32_t MR11; /*!< (@ 0x0000004C) Offset:0x4C CT16Bn MR11 Register */ + __IOM uint32_t MR12; /*!< (@ 0x00000050) Offset:0x50 CT16Bn MR12 Register */ + __IOM uint32_t MR13; /*!< (@ 0x00000054) Offset:0x54 CT16Bn MR13 Register */ + __IOM uint32_t MR14; /*!< (@ 0x00000058) Offset:0x58 CT16Bn MR14 Register */ + __IOM uint32_t MR15; /*!< (@ 0x0000005C) Offset:0x5C CT16Bn MR15 Register */ + __IOM uint32_t MR16; /*!< (@ 0x00000060) Offset:0x60 CT16Bn MR16 Register */ + __IOM uint32_t MR17; /*!< (@ 0x00000064) Offset:0x64 CT16Bn MR17 Register */ + __IOM uint32_t MR18; /*!< (@ 0x00000068) Offset:0x68 CT16Bn MR18 Register */ + __IOM uint32_t MR19; /*!< (@ 0x0000006C) Offset:0x6C CT16Bn MR19 Register */ + __IOM uint32_t MR20; /*!< (@ 0x00000070) Offset:0x70 CT16Bn MR20 Register */ + __IOM uint32_t MR21; /*!< (@ 0x00000074) Offset:0x74 CT16Bn MR21 Register */ + __IOM uint32_t MR22; /*!< (@ 0x00000078) Offset:0x78 CT16Bn MR22 Register */ + __IOM uint32_t MR23; /*!< (@ 0x0000007C) Offset:0x7C CT16Bn MR23 Register */ + __IM uint32_t RESERVED1[2]; + + union { + __IOM uint32_t EM; /*!< (@ 0x00000088) Offset:0x88 CT16Bn External Match Register */ + + struct { + __IOM uint32_t EM0 : 1; /*!< [0..0] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM0 output high or Low. */ + __IOM uint32_t EM1 : 1; /*!< [1..1] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM1 output high or Low. */ + __IOM uint32_t EM2 : 1; /*!< [2..2] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM2 output high or Low. */ + __IOM uint32_t EM3 : 1; /*!< [3..3] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM3 output high or Low. */ + __IOM uint32_t EM4 : 1; /*!< [4..4] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM4 output high or Low. */ + __IOM uint32_t EM5 : 1; /*!< [5..5] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM5 output high or Low. */ + __IOM uint32_t EM6 : 1; /*!< [6..6] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM6 output high or Low. */ + __IOM uint32_t EM7 : 1; /*!< [7..7] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM7 output high or Low. */ + __IOM uint32_t EM8 : 1; /*!< [8..8] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM8 output high or Low. */ + __IOM uint32_t EM9 : 1; /*!< [9..9] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM9 output high or Low. */ + __IOM uint32_t EM10 : 1; /*!< [10..10] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM10 output high or Low. */ + __IOM uint32_t EM11 : 1; /*!< [11..11] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM11 output high or Low. */ + __IOM uint32_t EM12 : 1; /*!< [12..12] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM12 output high or Low. */ + __IOM uint32_t EM13 : 1; /*!< [13..13] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM13 output high or Low. */ + __IOM uint32_t EM14 : 1; /*!< [14..14] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM14 output high or Low. */ + __IOM uint32_t EM15 : 1; /*!< [15..15] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM15 output high or Low. */ + __IOM uint32_t EM16 : 1; /*!< [16..16] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM16 output high or Low. */ + __IOM uint32_t EM17 : 1; /*!< [17..17] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM17 output high or Low. */ + __IOM uint32_t EM18 : 1; /*!< [18..18] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM18 output high or Low. */ + __IOM uint32_t EM19 : 1; /*!< [19..19] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM19 output high or Low. */ + __IOM uint32_t EM20 : 1; /*!< [20..20] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM20 output high or Low. */ + __IOM uint32_t EM21 : 1; /*!< [21..21] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM21 output high or Low. */ + __IOM uint32_t EM22 : 1; /*!< [22..22] When FW write this bit 1/0, MCU will drive the state + of CT16Bn_PWM22 output high or Low. */ + uint32_t : 9; + } EM_b; + } ; + + union { + __IOM uint32_t EMC; /*!< (@ 0x0000008C) Offset:0x8C CT16Bn External Match Control register */ + + struct { + __IOM uint32_t EMC0 : 2; /*!< [1..0] CT16Bn_PWM0 functionality */ + __IOM uint32_t EMC1 : 2; /*!< [3..2] CT16Bn_PWM1 functionality */ + __IOM uint32_t EMC2 : 2; /*!< [5..4] CT16Bn_PWM2 functionality */ + __IOM uint32_t EMC3 : 2; /*!< [7..6] CT16Bn_PWM3 functionality */ + __IOM uint32_t EMC4 : 2; /*!< [9..8] CT16Bn_PWM4 functionality */ + __IOM uint32_t EMC5 : 2; /*!< [11..10] CT16Bn_PWM5 functionality */ + __IOM uint32_t EMC6 : 2; /*!< [13..12] CT16Bn_PWM6 functionality */ + __IOM uint32_t EMC7 : 2; /*!< [15..14] CT16Bn_PWM7 functionality */ + __IOM uint32_t EMC8 : 2; /*!< [17..16] CT16Bn_PWM8 functionality */ + __IOM uint32_t EMC9 : 2; /*!< [19..18] CT16Bn_PWM9 functionality */ + __IOM uint32_t EMC10 : 2; /*!< [21..20] CT16Bn_PWM10 functionality */ + __IOM uint32_t EMC11 : 2; /*!< [23..22] CT16Bn_PWM11 functionality */ + __IOM uint32_t EMC12 : 2; /*!< [25..24] CT16Bn_PWM12 functionality */ + __IOM uint32_t EMC13 : 2; /*!< [27..26] CT16Bn_PWM13 functionality */ + __IOM uint32_t EMC14 : 2; /*!< [29..28] CT16Bn_PWM14 functionality */ + __IOM uint32_t EMC15 : 2; /*!< [31..30] CT16Bn_PWM15 functionality */ + } EMC_b; + } ; + + union { + __IOM uint32_t EMC2; /*!< (@ 0x00000090) Offset:0x90 CT16Bn External Match Control register + 2 */ + + struct { + __IOM uint32_t EMC16 : 2; /*!< [1..0] CT16Bn_PWM16 functionality */ + __IOM uint32_t EMC17 : 2; /*!< [3..2] CT16Bn_PWM17 functionality */ + __IOM uint32_t EMC18 : 2; /*!< [5..4] CT16Bn_PWM18 functionality */ + __IOM uint32_t EMC19 : 2; /*!< [7..6] CT16Bn_PWM19 functionality */ + __IOM uint32_t EMC20 : 2; /*!< [9..8] CT16Bn_PWM20 functionality */ + __IOM uint32_t EMC21 : 2; /*!< [11..10] CT16Bn_PWM21 functionality */ + __IOM uint32_t EMC22 : 2; /*!< [13..12] CT16Bn_PWM22 functionality */ + uint32_t : 18; + } EMC2_b; + } ; + + union { + __IOM uint32_t PWMCTRL; /*!< (@ 0x00000094) Offset:0x94 CT16Bn PWM Control Register */ + + struct { + __IOM uint32_t PWM0MODE : 2; /*!< [1..0] PWM0 output mode */ + __IOM uint32_t PWM1MODE : 2; /*!< [3..2] PWM1 output mode */ + __IOM uint32_t PWM2MODE : 2; /*!< [5..4] PWM2 output mode */ + __IOM uint32_t PWM3MODE : 2; /*!< [7..6] PWM3 output mode */ + __IOM uint32_t PWM4MODE : 2; /*!< [9..8] PWM4 output mode */ + __IOM uint32_t PWM5MODE : 2; /*!< [11..10] PWM5 output mode */ + __IOM uint32_t PWM6MODE : 2; /*!< [13..12] PWM6 output mode */ + __IOM uint32_t PWM7MODE : 2; /*!< [15..14] PWM7 output mode */ + __IOM uint32_t PWM8MODE : 2; /*!< [17..16] PWM8 output mode */ + __IOM uint32_t PWM9MODE : 2; /*!< [19..18] PWM9 output mode */ + __IOM uint32_t PWM10MODE : 2; /*!< [21..20] PWM10 output mode */ + __IOM uint32_t PWM11MODE : 2; /*!< [23..22] PWM11 output mode */ + __IOM uint32_t PWM12MODE : 2; /*!< [25..24] PWM12 output mode */ + __IOM uint32_t PWM13MODE : 2; /*!< [27..26] PWM13 output mode */ + __IOM uint32_t PWM14MODE : 2; /*!< [29..28] PWM14 output mode */ + __IOM uint32_t PWM15MODE : 2; /*!< [31..30] PWM15 output mode */ + } PWMCTRL_b; + } ; + + union { + __IOM uint32_t PWMCTRL2; /*!< (@ 0x00000098) Offset:0x98 CT16Bn PWM Control Register 2 */ + + struct { + __IOM uint32_t PWM16MODE : 2; /*!< [1..0] PWM16 output mode */ + __IOM uint32_t PWM17MODE : 2; /*!< [3..2] PWM17 output mode */ + __IOM uint32_t PWM18MODE : 2; /*!< [5..4] PWM18 output mode */ + __IOM uint32_t PWM19MODE : 2; /*!< [7..6] PWM19 output mode */ + __IOM uint32_t PWM20MODE : 2; /*!< [9..8] PWM20 output mode */ + __IOM uint32_t PWM21MODE : 2; /*!< [11..10] PWM21 output mode */ + __IOM uint32_t PWM22MODE : 2; /*!< [13..12] PWM22 output mode */ + uint32_t : 18; + } PWMCTRL2_b; + } ; + + union { + __IOM uint32_t PWMENB; /*!< (@ 0x0000009C) Offset:0x9C CT16Bn PWM Enable register */ + + struct { + __IOM uint32_t PWM0EN : 1; /*!< [0..0] PWM0 enable */ + __IOM uint32_t PWM1EN : 1; /*!< [1..1] PWM1 enable */ + __IOM uint32_t PWM2EN : 1; /*!< [2..2] PWM2 enable */ + __IOM uint32_t PWM3EN : 1; /*!< [3..3] PWM3 enable */ + __IOM uint32_t PWM4EN : 1; /*!< [4..4] PWM4 enable */ + __IOM uint32_t PWM5EN : 1; /*!< [5..5] PWM5 enable */ + __IOM uint32_t PWM6EN : 1; /*!< [6..6] PWM6 enable */ + __IOM uint32_t PWM7EN : 1; /*!< [7..7] PWM7 enable */ + __IOM uint32_t PWM8EN : 1; /*!< [8..8] PWM8 enable */ + __IOM uint32_t PWM9EN : 1; /*!< [9..9] PWM9 enable */ + __IOM uint32_t PWM10EN : 1; /*!< [10..10] PWM10 enable */ + __IOM uint32_t PWM11EN : 1; /*!< [11..11] PWM11 enable */ + __IOM uint32_t PWM12EN : 1; /*!< [12..12] PWM12 enable */ + __IOM uint32_t PWM13EN : 1; /*!< [13..13] PWM13 enable */ + __IOM uint32_t PWM14EN : 1; /*!< [14..14] PWM14 enable */ + __IOM uint32_t PWM15EN : 1; /*!< [15..15] PWM15 enable */ + __IOM uint32_t PWM16EN : 1; /*!< [16..16] PWM16 enable */ + __IOM uint32_t PWM17EN : 1; /*!< [17..17] PWM17 enable */ + __IOM uint32_t PWM18EN : 1; /*!< [18..18] PWM18 enable */ + __IOM uint32_t PWM19EN : 1; /*!< [19..19] PWM19 enable */ + __IOM uint32_t PWM20EN : 1; /*!< [20..20] PWM20 enable */ + __IOM uint32_t PWM21EN : 1; /*!< [21..21] PWM21 enable */ + __IOM uint32_t PWM22EN : 1; /*!< [22..22] PWM22 enable */ + uint32_t : 9; + } PWMENB_b; + } ; + + union { + __IOM uint32_t PWMIOENB; /*!< (@ 0x000000A0) Offset:0xA0 CT16Bn PWM IO Enable register */ + + struct { + __IOM uint32_t PWM0IOEN : 1; /*!< [0..0] CT16Bn_PWM0/GPIO selection */ + __IOM uint32_t PWM1IOEN : 1; /*!< [1..1] CT16Bn_PWM1/GPIO selection */ + __IOM uint32_t PWM2IOEN : 1; /*!< [2..2] CT16Bn_PWM2/GPIO selection */ + __IOM uint32_t PWM3IOEN : 1; /*!< [3..3] CT16Bn_PWM3/GPIO selection */ + __IOM uint32_t PWM4IOEN : 1; /*!< [4..4] CT16Bn_PWM4/GPIO selection */ + __IOM uint32_t PWM5IOEN : 1; /*!< [5..5] CT16Bn_PWM5/GPIO selection */ + __IOM uint32_t PWM6IOEN : 1; /*!< [6..6] CT16Bn_PWM6/GPIO selection */ + __IOM uint32_t PWM7IOEN : 1; /*!< [7..7] CT16Bn_PWM7/GPIO selection */ + __IOM uint32_t PWM8IOEN : 1; /*!< [8..8] CT16Bn_PWM8/GPIO selection */ + __IOM uint32_t PWM9IOEN : 1; /*!< [9..9] CT16Bn_PWM9/GPIO selection */ + __IOM uint32_t PWM10IOEN : 1; /*!< [10..10] CT16Bn_PWM10/GPIO selection */ + __IOM uint32_t PWM11IOEN : 1; /*!< [11..11] CT16Bn_PWM11/GPIO selection */ + __IOM uint32_t PWM12IOEN : 1; /*!< [12..12] CT16Bn_PWM12/GPIO selection */ + __IOM uint32_t PWM13IOEN : 1; /*!< [13..13] CT16Bn_PWM13/GPIO selection */ + __IOM uint32_t PWM14IOEN : 1; /*!< [14..14] CT16Bn_PWM14/GPIO selection */ + __IOM uint32_t PWM15IOEN : 1; /*!< [15..15] CT16Bn_PWM15/GPIO selection */ + __IOM uint32_t PWM16IOEN : 1; /*!< [16..16] CT16Bn_PWM16/GPIO selection */ + __IOM uint32_t PWM17IOEN : 1; /*!< [17..17] CT16Bn_PWM17/GPIO selection */ + __IOM uint32_t PWM18IOEN : 1; /*!< [18..18] CT16Bn_PWM18/GPIO selection */ + __IOM uint32_t PWM19IOEN : 1; /*!< [19..19] CT16Bn_PWM19/GPIO selection */ + __IOM uint32_t PWM20IOEN : 1; /*!< [20..20] CT16Bn_PWM20/GPIO selection */ + __IOM uint32_t PWM21IOEN : 1; /*!< [21..21] CT16Bn_PWM21/GPIO selection */ + __IOM uint32_t PWM22IOEN : 1; /*!< [22..22] CT16Bn_PWM22/GPIO selection */ + uint32_t : 9; + } PWMIOENB_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x000000A4) Offset:0xA4 CT16Bn Raw Interrupt Status Register */ + + struct { + __IM uint32_t MR0IF : 1; /*!< [0..0] Match channel 0 interrupt flag */ + __IM uint32_t MR1IF : 1; /*!< [1..1] Match channel 1 interrupt flag */ + __IM uint32_t MR2IF : 1; /*!< [2..2] Match channel 2 interrupt flag */ + __IM uint32_t MR3IF : 1; /*!< [3..3] Match channel 3 interrupt flag */ + __IM uint32_t MR4IF : 1; /*!< [4..4] Match channel 4 interrupt flag */ + __IM uint32_t MR5IF : 1; /*!< [5..5] Match channel 5 interrupt flag */ + __IM uint32_t MR6IF : 1; /*!< [6..6] Match channel 6 interrupt flag */ + __IM uint32_t MR7IF : 1; /*!< [7..7] Match channel 7 interrupt flag */ + __IM uint32_t MR8IF : 1; /*!< [8..8] Match channel 8 interrupt flag */ + __IM uint32_t MR9IF : 1; /*!< [9..9] Match channel 9 interrupt flag */ + __IM uint32_t MR10IF : 1; /*!< [10..10] Match channel 10 interrupt flag */ + __IM uint32_t MR11IF : 1; /*!< [11..11] Match channel 11 interrupt flag */ + __IM uint32_t MR12IF : 1; /*!< [12..12] Match channel 12 interrupt flag */ + __IM uint32_t MR13IF : 1; /*!< [13..13] Match channel 13 interrupt flag */ + __IM uint32_t MR14IF : 1; /*!< [14..14] Match channel 14 interrupt flag */ + __IM uint32_t MR15IF : 1; /*!< [15..15] Match channel 15 interrupt flag */ + __IM uint32_t MR16IF : 1; /*!< [16..16] Match channel 16 interrupt flag */ + __IM uint32_t MR17IF : 1; /*!< [17..17] Match channel 17 interrupt flag */ + __IM uint32_t MR18IF : 1; /*!< [18..18] Match channel 18 interrupt flag */ + __IM uint32_t MR19IF : 1; /*!< [19..19] Match channel 19 interrupt flag */ + __IM uint32_t MR20IF : 1; /*!< [20..20] Match channel 20 interrupt flag */ + __IM uint32_t MR21IF : 1; /*!< [21..21] Match channel 21 interrupt flag */ + __IM uint32_t MR22IF : 1; /*!< [22..22] Match channel 22 interrupt flag */ + __IM uint32_t MR23IF : 1; /*!< [23..23] Match channel 23 interrupt flag */ + uint32_t : 8; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x000000A8) Offset:0xA8 CT16Bn Interrupt Clear Register */ + + struct { + __OM uint32_t MR0IC : 1; /*!< [0..0] MR0IF clear bit */ + __OM uint32_t MR1IC : 1; /*!< [1..1] MR1IF clear bit */ + __OM uint32_t MR2IC : 1; /*!< [2..2] MR2IF clear bit */ + __OM uint32_t MR3IC : 1; /*!< [3..3] MR3IF clear bit */ + __OM uint32_t MR4IC : 1; /*!< [4..4] MR4IF clear bit */ + __OM uint32_t MR5IC : 1; /*!< [5..5] MR5IF clear bit */ + __OM uint32_t MR6IC : 1; /*!< [6..6] MR6IF clear bit */ + __OM uint32_t MR7IC : 1; /*!< [7..7] MR7IF clear bit */ + __OM uint32_t MR8IC : 1; /*!< [8..8] MR8IF clear bit */ + __OM uint32_t MR9IC : 1; /*!< [9..9] MR9IF clear bit */ + __OM uint32_t MR10IC : 1; /*!< [10..10] MR10IF clear bit */ + __OM uint32_t MR11IC : 1; /*!< [11..11] MR11IF clear bit */ + __OM uint32_t MR12IC : 1; /*!< [12..12] MR12IF clear bit */ + __OM uint32_t MR13IC : 1; /*!< [13..13] MR13IF clear bit */ + __OM uint32_t MR14IC : 1; /*!< [14..14] MR14IF clear bit */ + __OM uint32_t MR15IC : 1; /*!< [15..15] MR15IF clear bit */ + __OM uint32_t MR16IC : 1; /*!< [16..16] MR16IF clear bit */ + __OM uint32_t MR17IC : 1; /*!< [17..17] MR17IF clear bit */ + __OM uint32_t MR18IC : 1; /*!< [18..18] MR18IF clear bit */ + __OM uint32_t MR19IC : 1; /*!< [19..19] MR19IF clear bit */ + __OM uint32_t MR20IC : 1; /*!< [20..20] MR20IF clear bit */ + __OM uint32_t MR21IC : 1; /*!< [21..21] MR21IF clear bit */ + __OM uint32_t MR22IC : 1; /*!< [22..22] MR22IF clear bit */ + __OM uint32_t MR23IC : 1; /*!< [23..23] MR23IF clear bit */ + uint32_t : 8; + } IC_b; + } ; +} SN_CT16B1_Type; /*!< Size = 172 (0xac) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_PMU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power Management Unit (SN_PMU) + */ + +typedef struct { /*!< (@ 0x40032000) SN_PMU Structure */ + __IM uint32_t RESERVED[16]; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000040) Offset:0x40 PMU Control Register */ + + struct { + __IOM uint32_t MODE : 3; /*!< [2..0] Low Power mode selection */ + uint32_t : 29; + } CTRL_b; + } ; +} SN_PMU_Type; /*!< Size = 68 (0x44) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI0 (SN_SPI0) + */ + +typedef struct { /*!< (@ 0x4001C000) SN_SPI0 Structure */ + + union { + __IOM uint32_t CTRL0; /*!< (@ 0x00000000) Offset:0x00 SPIn Control Register 0 */ + + struct { + __IOM uint32_t SSPEN : 1; /*!< [0..0] SSP enable bit */ + __IOM uint32_t LOOPBACK : 1; /*!< [1..1] Loopback mode enable */ + __IOM uint32_t SDODIS : 1; /*!< [2..2] Slave data out disable */ + __IOM uint32_t MS : 1; /*!< [3..3] Master/Slave selection */ + __IOM uint32_t FORMAT : 1; /*!< [4..4] Interface format */ + uint32_t : 1; + __OM uint32_t FRESET : 2; /*!< [7..6] SPI FSM and FIFO Reset */ + __IOM uint32_t DL : 4; /*!< [11..8] Data length = DL[3:0]+1 */ + __IOM uint32_t TXFIFOTH : 3; /*!< [14..12] TX FIFO Threshold level */ + __IOM uint32_t RXFIFOTH : 3; /*!< [17..15] RX FIFO Threshold level */ + __IOM uint32_t SELDIS : 1; /*!< [18..18] Auto-SEL disable bit. For SPI mode only */ + uint32_t : 13; + } CTRL0_b; + } ; + + union { + __IOM uint32_t CTRL1; /*!< (@ 0x00000004) Offset:0x04 SPIn Control Register 1 */ + + struct { + __IOM uint32_t MLSB : 1; /*!< [0..0] MSB/LSB seletion */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock priority selection */ + __IOM uint32_t CPHA : 1; /*!< [2..2] Clock phase of edge sampling */ + uint32_t : 29; + } CTRL1_b; + } ; + + union { + __IOM uint32_t CLKDIV; /*!< (@ 0x00000008) Offset:0x08 SPIn Clock Divider Register */ + + struct { + __IOM uint32_t DIV : 8; /*!< [7..0] SPIn SCK=SPIn_PCLK/(2*DIV+2) */ + uint32_t : 24; + } CLKDIV_b; + } ; + + union { + __IM uint32_t STAT; /*!< (@ 0x0000000C) Offset:0x0C SPIn Status Register */ + + struct { + __IM uint32_t TX_EMPTY : 1; /*!< [0..0] TX FIFO empty flag */ + __IM uint32_t TX_FULL : 1; /*!< [1..1] TX FIFO full flag */ + __IM uint32_t RX_EMPTY : 1; /*!< [2..2] RX FIFO empty flag */ + __IM uint32_t RX_FULL : 1; /*!< [3..3] RX FIFO full flag */ + __IM uint32_t BUSY : 1; /*!< [4..4] Busy flag */ + __IM uint32_t TXFIFOTHF : 1; /*!< [5..5] TX FIFO threshold flag */ + __IM uint32_t RXFIFOTHF : 1; /*!< [6..6] RX FIFO threshold flag */ + uint32_t : 25; + } STAT_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000010) Offset:0x10 SPIn Interrupt Enable Register */ + + struct { + __IOM uint32_t RXOVFIE : 1; /*!< [0..0] RX FIFO overflow interrupt enable */ + __IOM uint32_t RXTOIE : 1; /*!< [1..1] RX time-out interrupt enable */ + __IOM uint32_t RXFIFOTHIE : 1; /*!< [2..2] RX FIFO threshold interrupt enable */ + __IOM uint32_t TXFIFOTHIE : 1; /*!< [3..3] TX FIFO threshold interrupt enable */ + uint32_t : 28; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x00000014) Offset:0x14 SPIn Raw Interrupt Status Register */ + + struct { + __IM uint32_t RXOVFIF : 1; /*!< [0..0] RX FIFO overflow interrupt flag */ + __IM uint32_t RXTOIF : 1; /*!< [1..1] RX time-out interrupt flag */ + __IM uint32_t RXFIFOTHIF : 1; /*!< [2..2] RX FIFO threshold interrupt flag */ + __IM uint32_t TXFIFOTHIF : 1; /*!< [3..3] TX FIFO threshold interrupt flag */ + uint32_t : 28; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000018) Offset:0x18 SPIn Interrupt Clear Register */ + + struct { + __OM uint32_t RXOVFIC : 1; /*!< [0..0] RX FIFO overflow flag clear */ + __OM uint32_t RXTOIC : 1; /*!< [1..1] RX time-out interrupt flag clear */ + __OM uint32_t RXFIFOTHIC : 1; /*!< [2..2] RX Interrupt flag Clear */ + __OM uint32_t TXFIFOTHIC : 1; /*!< [3..3] TX Interrupt flag Clear */ + uint32_t : 28; + } IC_b; + } ; + + union { + __IOM uint32_t DATA; /*!< (@ 0x0000001C) Offset:0x1C SPIn Data Register */ + + struct { + __IOM uint32_t Data : 16; /*!< [15..0] Data */ + uint32_t : 16; + } DATA_b; + } ; + + union { + __IOM uint32_t DF; /*!< (@ 0x00000020) Offset:0x20 SPIn Data Fetch Register */ + + struct { + __IOM uint32_t DF : 1; /*!< [0..0] SPI data fetch delay enable */ + uint32_t : 31; + } DF_b; + } ; +} SN_SPI0_Type; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_I2C0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C0 (SN_I2C0) + */ + +typedef struct { /*!< (@ 0x40018000) SN_I2C0 Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 I2Cn Control Register */ + + struct { + uint32_t : 1; + __IOM uint32_t NACK : 1; /*!< [1..1] NACK assert flag */ + __IOM uint32_t ACK : 1; /*!< [2..2] ACK assert flag */ + uint32_t : 1; + __IOM uint32_t STO : 1; /*!< [4..4] STOP assert flag */ + __IOM uint32_t STA : 1; /*!< [5..5] START assert flag */ + uint32_t : 1; + __IOM uint32_t MODE : 1; /*!< [7..7] I2C mode */ + __IOM uint32_t I2CEN : 1; /*!< [8..8] I2Cn interface enable */ + uint32_t : 23; + } CTRL_b; + } ; + + union { + __IOM uint32_t STAT; /*!< (@ 0x00000004) Offset:0x04 I2Cn Status Register */ + + struct { + __IM uint32_t RX_DN : 1; /*!< [0..0] RX done status */ + __IM uint32_t ACK_STAT : 1; /*!< [1..1] ACK done status */ + __IM uint32_t NACK_STAT : 1; /*!< [2..2] NACK done status */ + __IM uint32_t STOP_DN : 1; /*!< [3..3] STOP done status */ + __IM uint32_t START_DN : 1; /*!< [4..4] START done status */ + __IM uint32_t MST : 1; /*!< [5..5] I2C master/slave status */ + __IM uint32_t SLV_RX_HIT : 1; /*!< [6..6] Slave RX address hit flag */ + __IM uint32_t SLV_TX_HIT : 1; /*!< [7..7] Slave TX address hit flag */ + __IM uint32_t LOST_ARB : 1; /*!< [8..8] Lost arbitration status */ + __IM uint32_t TIMEOUT : 1; /*!< [9..9] Time-out status */ + uint32_t : 5; + __IOM uint32_t I2CIF : 1; /*!< [15..15] I2C interrupt flag */ + uint32_t : 16; + } STAT_b; + } ; + + union { + __IOM uint32_t TXDATA; /*!< (@ 0x00000008) Offset:0x08 I2Cn TX Data Register */ + + struct { + __IOM uint32_t Data : 8; /*!< [7..0] TX Data */ + uint32_t : 24; + } TXDATA_b; + } ; + + union { + __IM uint32_t RXDATA; /*!< (@ 0x0000000C) Offset:0x0C I2Cn RX Data Register */ + + struct { + __IM uint32_t Data : 8; /*!< [7..0] RX Data received when RX_DN=1 */ + uint32_t : 24; + } RXDATA_b; + } ; + + union { + __IOM uint32_t SLVADDR0; /*!< (@ 0x00000010) Offset:0x10 I2Cn Slave Address 0 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 0 */ + uint32_t : 20; + __IOM uint32_t GCEN : 1; /*!< [30..30] General call address enable */ + __IOM uint32_t ADD_MODE : 1; /*!< [31..31] Slave address mode */ + } SLVADDR0_b; + } ; + + union { + __IOM uint32_t SLVADDR1; /*!< (@ 0x00000014) Offset:0x14 I2Cn Slave Address 1 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 1 */ + uint32_t : 22; + } SLVADDR1_b; + } ; + + union { + __IOM uint32_t SLVADDR2; /*!< (@ 0x00000018) Offset:0x18 I2Cn Slave Address 2 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 2 */ + uint32_t : 22; + } SLVADDR2_b; + } ; + + union { + __IOM uint32_t SLVADDR3; /*!< (@ 0x0000001C) Offset:0x1C I2Cn Slave Address 3 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 3 */ + uint32_t : 22; + } SLVADDR3_b; + } ; + + union { + __IOM uint32_t SCLHT; /*!< (@ 0x00000020) Offset:0x20 I2Cn SCL High Time Register */ + + struct { + __IOM uint32_t SCLH : 8; /*!< [7..0] SCLn High period time=(SCLHT+1)*I2Cn_PCLK cycle */ + uint32_t : 24; + } SCLHT_b; + } ; + + union { + __IOM uint32_t SCLLT; /*!< (@ 0x00000024) Offset:0x24 I2Cn SCL Low Time Register */ + + struct { + __IOM uint32_t SCLL : 8; /*!< [7..0] SCLn Low period time=(SCLLT+1)*I2Cn_PCLK cycle */ + uint32_t : 24; + } SCLLT_b; + } ; + + union { + __IOM uint32_t SCLCT; /*!< (@ 0x00000028) Offset:0x28 I2C SCL Check Time register */ + + struct { + __IOM uint32_t SCLCT : 4; /*!< [3..0] Count for checking SCL arbitration in Master mode. */ + uint32_t : 28; + } SCLCT_b; + } ; + + union { + __IOM uint32_t TOCTRL; /*!< (@ 0x0000002C) Offset:0x2C I2Cn Timeout Control Register */ + + struct { + __IOM uint32_t TO : 16; /*!< [15..0] Timeout period time = TO*I2Cn_PCLK cycle */ + uint32_t : 16; + } TOCTRL_b; + } ; +} SN_I2C0_Type; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_FLASH ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FLASH Memory Control Registers (SN_FLASH) + */ + +typedef struct { /*!< (@ 0x40062000) SN_FLASH Structure */ + + union { + __IOM uint32_t LPCTRL; /*!< (@ 0x00000000) Offset:0x00 Flash Low Power Control Register */ + + struct { + __IOM uint32_t LPMODE : 4; /*!< [3..0] Flash Low Power mode selection bit */ + uint32_t : 28; + } LPCTRL_b; + } ; + + union { + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Offset:0x04 Flash Status Register */ + + struct { + __IM uint32_t BUSY : 1; /*!< [0..0] Busy flag */ + uint32_t : 1; + __IOM uint32_t ERR : 1; /*!< [2..2] Erase/Error flag */ + uint32_t : 29; + } STATUS_b; + } ; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000008) Offset:0x08 Flash Control Register */ + + struct { + __IOM uint32_t PG : 1; /*!< [0..0] Flash program mode chosen bit */ + __IOM uint32_t PER : 1; /*!< [1..1] Page erase mode chosen bit */ + __IOM uint32_t MER : 1; /*!< [2..2] Mass erase mode chosen bit */ + uint32_t : 3; + __IOM uint32_t START : 1; /*!< [6..6] Start erase/program operation */ + __IOM uint32_t CHK : 1; /*!< [7..7] Checksum calculation chosen */ + uint32_t : 24; + } CTRL_b; + } ; + __IOM uint32_t DATA; /*!< (@ 0x0000000C) Offset:0x0C Flash Data Register */ + __IOM uint32_t ADDR; /*!< (@ 0x00000010) Offset:0x10 Flash Address Register */ + + union { + __IM uint32_t CHKSUM; /*!< (@ 0x00000014) Offset:0x14 Flash Checksum Register */ + + struct { + __IM uint32_t UserROM : 16; /*!< [15..0] Checksum of User ROM */ + __IM uint32_t BootROM : 16; /*!< [31..16] Checksum of Boot ROM */ + } CHKSUM_b; + } ; +} SN_FLASH_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_UC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UC Registers (SN_UC) + */ + +typedef struct { /*!< (@ 0x1FFF2220) SN_UC Structure */ + __IM uint32_t L4BYTE; /*!< (@ 0x00000000) Offset:0x00 UC Low 4 Byte Register */ + __IM uint32_t H4BYTE; /*!< (@ 0x00000004) Offset:0x04 UC High 4 Byte Register */ +} SN_UC_Type; /*!< Size = 8 (0x8) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define SN_SYS0_BASE 0x40060000UL +#define SN_SYS1_BASE 0x4005E000UL +#define SN_USB_BASE 0x4005C000UL +#define SN_GPIO0_BASE 0x40044000UL +#define SN_GPIO1_BASE 0x40046000UL +#define SN_GPIO2_BASE 0x40048000UL +#define SN_GPIO3_BASE 0x4004A000UL +#define SN_WDT_BASE 0x40010000UL +#define SN_CT16B0_BASE 0x40000000UL +#define SN_CT16B1_BASE 0x40002000UL +#define SN_PMU_BASE 0x40032000UL +#define SN_SPI0_BASE 0x4001C000UL +#define SN_I2C0_BASE 0x40018000UL +#define SN_FLASH_BASE 0x40062000UL +#define SN_UC_BASE 0x1FFF2220UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define SN_SYS0 ((SN_SYS0_Type*) SN_SYS0_BASE) +#define SN_SYS1 ((SN_SYS1_Type*) SN_SYS1_BASE) +#define SN_USB ((SN_USB_Type*) SN_USB_BASE) +#define SN_GPIO0 ((SN_GPIO0_Type*) SN_GPIO0_BASE) +#define SN_GPIO1 ((SN_GPIO1_Type*) SN_GPIO1_BASE) +#define SN_GPIO2 ((SN_GPIO2_Type*) SN_GPIO2_BASE) +#define SN_GPIO3 ((SN_GPIO3_Type*) SN_GPIO3_BASE) +#define SN_WDT ((SN_WDT_Type*) SN_WDT_BASE) +#define SN_CT16B0 ((SN_CT16B0_Type*) SN_CT16B0_BASE) +#define SN_CT16B1 ((SN_CT16B1_Type*) SN_CT16B1_BASE) +#define SN_PMU ((SN_PMU_Type*) SN_PMU_BASE) +#define SN_SPI0 ((SN_SPI0_Type*) SN_SPI0_BASE) +#define SN_I2C0 ((SN_I2C0_Type*) SN_I2C0_BASE) +#define SN_FLASH ((SN_FLASH_Type*) SN_FLASH_BASE) +#define SN_UC ((SN_UC_Type*) SN_UC_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* SN32F260_H */ + + +/** @} */ /* End of group SN32F260 */ + +/** @} */ /* End of group SONiX Technology Co., Ltd. */ diff --git a/os/common/ext/SONiX/SN32F2xx/SN32F260_defines.h b/os/common/ext/SONiX/SN32F2xx/SN32F260_defines.h new file mode 100644 index 00000000..4e30aabc --- /dev/null +++ b/os/common/ext/SONiX/SN32F2xx/SN32F260_defines.h @@ -0,0 +1,2211 @@ +/* + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontroller, but can be equally used for other + * suitable processor architectures. This file can be freely distributed. + * Modifications to this file shall be clearly marked. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * @file SN32F260_defines.h + * @brief CMSIS HeaderFile + * @version 1.1 + * @date 04. October 2021 + * @note Generated by SVDConv V3.3.35 on Monday, 04.10.2021 13:03:21 + * from File 'SN32F260.svd', + * last modified on Tuesday, 01.09.2020 10:52:27 + */ + + + +/** @addtogroup SONiX Technology Co., Ltd. + * @{ + */ + + +/** @addtogroup SN32F260 + * @{ + */ + + +#ifndef SN32F260_DEFINES_H +#define SN32F260_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ SN_SYS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== ANBCTRL ======================================================== */ +#define SN_SYS0_ANBCTRL_IHRCEN_Pos (0UL) /*!< IHRCEN (Bit 0) */ +#define SN_SYS0_ANBCTRL_IHRCEN_Msk (0x1UL) /*!< IHRCEN (Bitfield-Mask: 0x01) */ +/* ========================================================= CSST ========================================================== */ +#define SN_SYS0_CSST_IHRCRDY_Pos (0UL) /*!< IHRCRDY (Bit 0) */ +#define SN_SYS0_CSST_IHRCRDY_Msk (0x1UL) /*!< IHRCRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CLKCFG ========================================================= */ +#define SN_SYS0_CLKCFG_SYSCLKSEL_Pos (0UL) /*!< SYSCLKSEL (Bit 0) */ +#define SN_SYS0_CLKCFG_SYSCLKSEL_Msk (0x7UL) /*!< SYSCLKSEL (Bitfield-Mask: 0x07) */ +#define SN_SYS0_CLKCFG_SYSCLKST_Pos (4UL) /*!< SYSCLKST (Bit 4) */ +#define SN_SYS0_CLKCFG_SYSCLKST_Msk (0x70UL) /*!< SYSCLKST (Bitfield-Mask: 0x07) */ +/* ========================================================= AHBCP ========================================================= */ +#define SN_SYS0_AHBCP_AHBPRE_Pos (0UL) /*!< AHBPRE (Bit 0) */ +#define SN_SYS0_AHBCP_AHBPRE_Msk (0x7UL) /*!< AHBPRE (Bitfield-Mask: 0x07) */ +/* ========================================================= RSTST ========================================================= */ +#define SN_SYS0_RSTST_SWRSTF_Pos (0UL) /*!< SWRSTF (Bit 0) */ +#define SN_SYS0_RSTST_SWRSTF_Msk (0x1UL) /*!< SWRSTF (Bitfield-Mask: 0x01) */ +#define SN_SYS0_RSTST_WDTRSTF_Pos (1UL) /*!< WDTRSTF (Bit 1) */ +#define SN_SYS0_RSTST_WDTRSTF_Msk (0x2UL) /*!< WDTRSTF (Bitfield-Mask: 0x01) */ +#define SN_SYS0_RSTST_LVDRSTF_Pos (2UL) /*!< LVDRSTF (Bit 2) */ +#define SN_SYS0_RSTST_LVDRSTF_Msk (0x4UL) /*!< LVDRSTF (Bitfield-Mask: 0x01) */ +#define SN_SYS0_RSTST_EXTRSTF_Pos (3UL) /*!< EXTRSTF (Bit 3) */ +#define SN_SYS0_RSTST_EXTRSTF_Msk (0x8UL) /*!< EXTRSTF (Bitfield-Mask: 0x01) */ +#define SN_SYS0_RSTST_PORRSTF_Pos (4UL) /*!< PORRSTF (Bit 4) */ +#define SN_SYS0_RSTST_PORRSTF_Msk (0x10UL) /*!< PORRSTF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDCTRL ======================================================== */ +#define SN_SYS0_LVDCTRL_LVDRSTLVL_Pos (0UL) /*!< LVDRSTLVL (Bit 0) */ +#define SN_SYS0_LVDCTRL_LVDRSTLVL_Msk (0x7UL) /*!< LVDRSTLVL (Bitfield-Mask: 0x07) */ +#define SN_SYS0_LVDCTRL_LVDINTLVL_Pos (5UL) /*!< LVDINTLVL (Bit 5) */ +#define SN_SYS0_LVDCTRL_LVDINTLVL_Msk (0x60UL) /*!< LVDINTLVL (Bitfield-Mask: 0x03) */ +#define SN_SYS0_LVDCTRL_LVDRSTEN_Pos (14UL) /*!< LVDRSTEN (Bit 14) */ +#define SN_SYS0_LVDCTRL_LVDRSTEN_Msk (0x4000UL) /*!< LVDRSTEN (Bitfield-Mask: 0x01) */ +#define SN_SYS0_LVDCTRL_LVDEN_Pos (15UL) /*!< LVDEN (Bit 15) */ +#define SN_SYS0_LVDCTRL_LVDEN_Msk (0x8000UL) /*!< LVDEN (Bitfield-Mask: 0x01) */ +/* ======================================================= EXRSTCTRL ======================================================= */ +#define SN_SYS0_EXRSTCTRL_RESETDIS_Pos (0UL) /*!< RESETDIS (Bit 0) */ +#define SN_SYS0_EXRSTCTRL_RESETDIS_Msk (0x1UL) /*!< RESETDIS (Bitfield-Mask: 0x01) */ +/* ======================================================== SWDCTRL ======================================================== */ +#define SN_SYS0_SWDCTRL_SWDDIS_Pos (0UL) /*!< SWDDIS (Bit 0) */ +#define SN_SYS0_SWDCTRL_SWDDIS_Msk (0x1UL) /*!< SWDDIS (Bitfield-Mask: 0x01) */ +/* ========================================================= IVTM ========================================================== */ +#define SN_SYS0_IVTM_IVTM_Pos (0UL) /*!< IVTM (Bit 0) */ +#define SN_SYS0_IVTM_IVTM_Msk (0x3UL) /*!< IVTM (Bitfield-Mask: 0x03) */ +#define SN_SYS0_IVTM_IVTMKEY_Pos (16UL) /*!< IVTMKEY (Bit 16) */ +#define SN_SYS0_IVTM_IVTMKEY_Msk (0xffff0000UL) /*!< IVTMKEY (Bitfield-Mask: 0xffff) */ +/* ======================================================== NDTCTRL ======================================================== */ +#define SN_SYS0_NDTCTRL_NDT5V_IE_Pos (1UL) /*!< NDT5V_IE (Bit 1) */ +#define SN_SYS0_NDTCTRL_NDT5V_IE_Msk (0x2UL) /*!< NDT5V_IE (Bitfield-Mask: 0x01) */ +/* ======================================================== NDTSTS ========================================================= */ +#define SN_SYS0_NDTSTS_NDT5V_DET_Pos (1UL) /*!< NDT5V_DET (Bit 1) */ +#define SN_SYS0_NDTSTS_NDT5V_DET_Msk (0x2UL) /*!< NDT5V_DET (Bitfield-Mask: 0x01) */ +/* ======================================================== ANTIEFT ======================================================== */ +#define SN_SYS0_ANTIEFT_AEFT_Pos (0UL) /*!< AEFT (Bit 0) */ +#define SN_SYS0_ANTIEFT_AEFT_Msk (0x7UL) /*!< AEFT (Bitfield-Mask: 0x07) */ + + +/* =========================================================================================================================== */ +/* ================ SN_SYS1 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= AHBCLKEN ======================================================== */ +#define SN_SYS1_AHBCLKEN_P0CLKEN_Pos (0UL) /*!< P0CLKEN (Bit 0) */ +#define SN_SYS1_AHBCLKEN_P0CLKEN_Msk (0x1UL) /*!< P0CLKEN (Bitfield-Mask: 0x01) */ +#define SN_SYS1_AHBCLKEN_P1CLKEN_Pos (1UL) /*!< P1CLKEN (Bit 1) */ +#define SN_SYS1_AHBCLKEN_P1CLKEN_Msk (0x2UL) /*!< P1CLKEN (Bitfield-Mask: 0x01) */ +#define SN_SYS1_AHBCLKEN_P2CLKEN_Pos (2UL) /*!< P2CLKEN (Bit 2) */ +#define SN_SYS1_AHBCLKEN_P2CLKEN_Msk (0x4UL) /*!< P2CLKEN (Bitfield-Mask: 0x01) */ +#define SN_SYS1_AHBCLKEN_P3CLKEN_Pos (3UL) /*!< P3CLKEN (Bit 3) */ +#define SN_SYS1_AHBCLKEN_P3CLKEN_Msk (0x8UL) /*!< P3CLKEN (Bitfield-Mask: 0x01) */ +#define SN_SYS1_AHBCLKEN_USBCLKEN_Pos (4UL) /*!< USBCLKEN (Bit 4) */ +#define SN_SYS1_AHBCLKEN_USBCLKEN_Msk (0x10UL) /*!< USBCLKEN (Bitfield-Mask: 0x01) */ +#define SN_SYS1_AHBCLKEN_CT16B0CLKEN_Pos (6UL) /*!< CT16B0CLKEN (Bit 6) */ +#define SN_SYS1_AHBCLKEN_CT16B0CLKEN_Msk (0x40UL) /*!< CT16B0CLKEN (Bitfield-Mask: 0x01) */ +#define SN_SYS1_AHBCLKEN_CT16B1CLKEN_Pos (7UL) /*!< CT16B1CLKEN (Bit 7) */ +#define SN_SYS1_AHBCLKEN_CT16B1CLKEN_Msk (0x80UL) /*!< CT16B1CLKEN (Bitfield-Mask: 0x01) */ +#define SN_SYS1_AHBCLKEN_SPI0CLKEN_Pos (12UL) /*!< SPI0CLKEN (Bit 12) */ +#define SN_SYS1_AHBCLKEN_SPI0CLKEN_Msk (0x1000UL) /*!< SPI0CLKEN (Bitfield-Mask: 0x01) */ +#define SN_SYS1_AHBCLKEN_I2C0CLKEN_Pos (21UL) /*!< I2C0CLKEN (Bit 21) */ +#define SN_SYS1_AHBCLKEN_I2C0CLKEN_Msk (0x200000UL) /*!< I2C0CLKEN (Bitfield-Mask: 0x01) */ +#define SN_SYS1_AHBCLKEN_WDTCLKEN_Pos (24UL) /*!< WDTCLKEN (Bit 24) */ +#define SN_SYS1_AHBCLKEN_WDTCLKEN_Msk (0x1000000UL) /*!< WDTCLKEN (Bitfield-Mask: 0x01) */ +#define SN_SYS1_AHBCLKEN_CLKOUTSEL_Pos (28UL) /*!< CLKOUTSEL (Bit 28) */ +#define SN_SYS1_AHBCLKEN_CLKOUTSEL_Msk (0x70000000UL) /*!< CLKOUTSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== APBCP1 ========================================================= */ +#define SN_SYS1_APBCP1_SYSTICKPRE_Pos (16UL) /*!< SYSTICKPRE (Bit 16) */ +#define SN_SYS1_APBCP1_SYSTICKPRE_Msk (0x30000UL) /*!< SYSTICKPRE (Bitfield-Mask: 0x03) */ +#define SN_SYS1_APBCP1_WDTPRE_Pos (20UL) /*!< WDTPRE (Bit 20) */ +#define SN_SYS1_APBCP1_WDTPRE_Msk (0x700000UL) /*!< WDTPRE (Bitfield-Mask: 0x07) */ +#define SN_SYS1_APBCP1_CLKOUTPRE_Pos (28UL) /*!< CLKOUTPRE (Bit 28) */ +#define SN_SYS1_APBCP1_CLKOUTPRE_Msk (0x70000000UL) /*!< CLKOUTPRE (Bitfield-Mask: 0x07) */ + + +/* =========================================================================================================================== */ +/* ================ SN_USB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= INTEN ========================================================= */ +#define SN_USB_INTEN_EP1_NAK_EN_Pos (0UL) /*!< EP1_NAK_EN (Bit 0) */ +#define SN_USB_INTEN_EP1_NAK_EN_Msk (0x1UL) /*!< EP1_NAK_EN (Bitfield-Mask: 0x01) */ +#define SN_USB_INTEN_EP2_NAK_EN_Pos (1UL) /*!< EP2_NAK_EN (Bit 1) */ +#define SN_USB_INTEN_EP2_NAK_EN_Msk (0x2UL) /*!< EP2_NAK_EN (Bitfield-Mask: 0x01) */ +#define SN_USB_INTEN_EP3_NAK_EN_Pos (2UL) /*!< EP3_NAK_EN (Bit 2) */ +#define SN_USB_INTEN_EP3_NAK_EN_Msk (0x4UL) /*!< EP3_NAK_EN (Bitfield-Mask: 0x01) */ +#define SN_USB_INTEN_EP4_NAK_EN_Pos (3UL) /*!< EP4_NAK_EN (Bit 3) */ +#define SN_USB_INTEN_EP4_NAK_EN_Msk (0x8UL) /*!< EP4_NAK_EN (Bitfield-Mask: 0x01) */ +#define SN_USB_INTEN_EPN_ACK_EN_Pos (4UL) /*!< EPN_ACK_EN (Bit 4) */ +#define SN_USB_INTEN_EPN_ACK_EN_Msk (0x10UL) /*!< EPN_ACK_EN (Bitfield-Mask: 0x01) */ +#define SN_USB_INTEN_BUSWK_IE_Pos (28UL) /*!< BUSWK_IE (Bit 28) */ +#define SN_USB_INTEN_BUSWK_IE_Msk (0x10000000UL) /*!< BUSWK_IE (Bitfield-Mask: 0x01) */ +#define SN_USB_INTEN_USB_IE_Pos (29UL) /*!< USB_IE (Bit 29) */ +#define SN_USB_INTEN_USB_IE_Msk (0x20000000UL) /*!< USB_IE (Bitfield-Mask: 0x01) */ +#define SN_USB_INTEN_USB_SOF_IE_Pos (30UL) /*!< USB_SOF_IE (Bit 30) */ +#define SN_USB_INTEN_USB_SOF_IE_Msk (0x40000000UL) /*!< USB_SOF_IE (Bitfield-Mask: 0x01) */ +#define SN_USB_INTEN_BUS_IE_Pos (31UL) /*!< BUS_IE (Bit 31) */ +#define SN_USB_INTEN_BUS_IE_Msk (0x80000000UL) /*!< BUS_IE (Bitfield-Mask: 0x01) */ +/* ========================================================= INSTS ========================================================= */ +#define SN_USB_INSTS_EP1_NAK_Pos (0UL) /*!< EP1_NAK (Bit 0) */ +#define SN_USB_INSTS_EP1_NAK_Msk (0x1UL) /*!< EP1_NAK (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTS_EP2_NAK_Pos (1UL) /*!< EP2_NAK (Bit 1) */ +#define SN_USB_INSTS_EP2_NAK_Msk (0x2UL) /*!< EP2_NAK (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTS_EP3_NAK_Pos (2UL) /*!< EP3_NAK (Bit 2) */ +#define SN_USB_INSTS_EP3_NAK_Msk (0x4UL) /*!< EP3_NAK (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTS_EP4_NAK_Pos (3UL) /*!< EP4_NAK (Bit 3) */ +#define SN_USB_INSTS_EP4_NAK_Msk (0x8UL) /*!< EP4_NAK (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTS_EP1_ACK_Pos (8UL) /*!< EP1_ACK (Bit 8) */ +#define SN_USB_INSTS_EP1_ACK_Msk (0x100UL) /*!< EP1_ACK (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTS_EP2_ACK_Pos (9UL) /*!< EP2_ACK (Bit 9) */ +#define SN_USB_INSTS_EP2_ACK_Msk (0x200UL) /*!< EP2_ACK (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTS_EP3_ACK_Pos (10UL) /*!< EP3_ACK (Bit 10) */ +#define SN_USB_INSTS_EP3_ACK_Msk (0x400UL) /*!< EP3_ACK (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTS_EP4_ACK_Pos (11UL) /*!< EP4_ACK (Bit 11) */ +#define SN_USB_INSTS_EP4_ACK_Msk (0x800UL) /*!< EP4_ACK (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTS_ERR_TIMEOUT_Pos (17UL) /*!< ERR_TIMEOUT (Bit 17) */ +#define SN_USB_INSTS_ERR_TIMEOUT_Msk (0x20000UL) /*!< ERR_TIMEOUT (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTS_ERR_SETUP_Pos (18UL) /*!< ERR_SETUP (Bit 18) */ +#define SN_USB_INSTS_ERR_SETUP_Msk (0x40000UL) /*!< ERR_SETUP (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTS_EP0_OUT_STALL_Pos (19UL) /*!< EP0_OUT_STALL (Bit 19) */ +#define SN_USB_INSTS_EP0_OUT_STALL_Msk (0x80000UL) /*!< EP0_OUT_STALL (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTS_EP0_IN_STALL_Pos (20UL) /*!< EP0_IN_STALL (Bit 20) */ +#define SN_USB_INSTS_EP0_IN_STALL_Msk (0x100000UL) /*!< EP0_IN_STALL (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTS_EP0_OUT_Pos (21UL) /*!< EP0_OUT (Bit 21) */ +#define SN_USB_INSTS_EP0_OUT_Msk (0x200000UL) /*!< EP0_OUT (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTS_EP0_IN_Pos (22UL) /*!< EP0_IN (Bit 22) */ +#define SN_USB_INSTS_EP0_IN_Msk (0x400000UL) /*!< EP0_IN (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTS_EP0_SETUP_Pos (23UL) /*!< EP0_SETUP (Bit 23) */ +#define SN_USB_INSTS_EP0_SETUP_Msk (0x800000UL) /*!< EP0_SETUP (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTS_EP0_PRESETUP_Pos (24UL) /*!< EP0_PRESETUP (Bit 24) */ +#define SN_USB_INSTS_EP0_PRESETUP_Msk (0x1000000UL) /*!< EP0_PRESETUP (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTS_USB_SOF_Pos (26UL) /*!< USB_SOF (Bit 26) */ +#define SN_USB_INSTS_USB_SOF_Msk (0x4000000UL) /*!< USB_SOF (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTS_BUS_RESUME_Pos (29UL) /*!< BUS_RESUME (Bit 29) */ +#define SN_USB_INSTS_BUS_RESUME_Msk (0x20000000UL) /*!< BUS_RESUME (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTS_BUS_SUSPEND_Pos (30UL) /*!< BUS_SUSPEND (Bit 30) */ +#define SN_USB_INSTS_BUS_SUSPEND_Msk (0x40000000UL) /*!< BUS_SUSPEND (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTS_BUS_RESET_Pos (31UL) /*!< BUS_RESET (Bit 31) */ +#define SN_USB_INSTS_BUS_RESET_Msk (0x80000000UL) /*!< BUS_RESET (Bitfield-Mask: 0x01) */ +/* ======================================================== INSTSC ========================================================= */ +#define SN_USB_INSTSC_EP1_NAKC_Pos (0UL) /*!< EP1_NAKC (Bit 0) */ +#define SN_USB_INSTSC_EP1_NAKC_Msk (0x1UL) /*!< EP1_NAKC (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTSC_EP2_NAKC_Pos (1UL) /*!< EP2_NAKC (Bit 1) */ +#define SN_USB_INSTSC_EP2_NAKC_Msk (0x2UL) /*!< EP2_NAKC (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTSC_EP3_NAKC_Pos (2UL) /*!< EP3_NAKC (Bit 2) */ +#define SN_USB_INSTSC_EP3_NAKC_Msk (0x4UL) /*!< EP3_NAKC (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTSC_EP4_NAKC_Pos (3UL) /*!< EP4_NAKC (Bit 3) */ +#define SN_USB_INSTSC_EP4_NAKC_Msk (0x8UL) /*!< EP4_NAKC (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTSC_EP1_ACKC_Pos (8UL) /*!< EP1_ACKC (Bit 8) */ +#define SN_USB_INSTSC_EP1_ACKC_Msk (0x100UL) /*!< EP1_ACKC (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTSC_EP2_ACKC_Pos (9UL) /*!< EP2_ACKC (Bit 9) */ +#define SN_USB_INSTSC_EP2_ACKC_Msk (0x200UL) /*!< EP2_ACKC (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTSC_EP3_ACKC_Pos (10UL) /*!< EP3_ACKC (Bit 10) */ +#define SN_USB_INSTSC_EP3_ACKC_Msk (0x400UL) /*!< EP3_ACKC (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTSC_EP4_ACKC_Pos (11UL) /*!< EP4_ACKC (Bit 11) */ +#define SN_USB_INSTSC_EP4_ACKC_Msk (0x800UL) /*!< EP4_ACKC (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTSC_ERR_TIMEOUTC_Pos (17UL) /*!< ERR_TIMEOUTC (Bit 17) */ +#define SN_USB_INSTSC_ERR_TIMEOUTC_Msk (0x20000UL) /*!< ERR_TIMEOUTC (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTSC_ERR_SETUPC_Pos (18UL) /*!< ERR_SETUPC (Bit 18) */ +#define SN_USB_INSTSC_ERR_SETUPC_Msk (0x40000UL) /*!< ERR_SETUPC (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTSC_EP0_OUT_STALLC_Pos (19UL) /*!< EP0_OUT_STALLC (Bit 19) */ +#define SN_USB_INSTSC_EP0_OUT_STALLC_Msk (0x80000UL) /*!< EP0_OUT_STALLC (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTSC_EP0_IN_STALLC_Pos (20UL) /*!< EP0_IN_STALLC (Bit 20) */ +#define SN_USB_INSTSC_EP0_IN_STALLC_Msk (0x100000UL) /*!< EP0_IN_STALLC (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTSC_EP0_OUTC_Pos (21UL) /*!< EP0_OUTC (Bit 21) */ +#define SN_USB_INSTSC_EP0_OUTC_Msk (0x200000UL) /*!< EP0_OUTC (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTSC_EP0_INC_Pos (22UL) /*!< EP0_INC (Bit 22) */ +#define SN_USB_INSTSC_EP0_INC_Msk (0x400000UL) /*!< EP0_INC (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTSC_EP0_SETUPC_Pos (23UL) /*!< EP0_SETUPC (Bit 23) */ +#define SN_USB_INSTSC_EP0_SETUPC_Msk (0x800000UL) /*!< EP0_SETUPC (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTSC_EP0_PRESETUPC_Pos (24UL) /*!< EP0_PRESETUPC (Bit 24) */ +#define SN_USB_INSTSC_EP0_PRESETUPC_Msk (0x1000000UL) /*!< EP0_PRESETUPC (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTSC_BUS_WAKEUPC_Pos (25UL) /*!< BUS_WAKEUPC (Bit 25) */ +#define SN_USB_INSTSC_BUS_WAKEUPC_Msk (0x2000000UL) /*!< BUS_WAKEUPC (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTSC_USB_SOFC_Pos (26UL) /*!< USB_SOFC (Bit 26) */ +#define SN_USB_INSTSC_USB_SOFC_Msk (0x4000000UL) /*!< USB_SOFC (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTSC_BUS_RESUMEC_Pos (29UL) /*!< BUS_RESUMEC (Bit 29) */ +#define SN_USB_INSTSC_BUS_RESUMEC_Msk (0x20000000UL) /*!< BUS_RESUMEC (Bitfield-Mask: 0x01) */ +#define SN_USB_INSTSC_BUS_RESETC_Pos (31UL) /*!< BUS_RESETC (Bit 31) */ +#define SN_USB_INSTSC_BUS_RESETC_Msk (0x80000000UL) /*!< BUS_RESETC (Bitfield-Mask: 0x01) */ +/* ========================================================= ADDR ========================================================== */ +#define SN_USB_ADDR_UADDR_Pos (0UL) /*!< UADDR (Bit 0) */ +#define SN_USB_ADDR_UADDR_Msk (0x7fUL) /*!< UADDR (Bitfield-Mask: 0x7f) */ +/* ========================================================== CFG ========================================================== */ +#define SN_USB_CFG_EP1_DIR_Pos (0UL) /*!< EP1_DIR (Bit 0) */ +#define SN_USB_CFG_EP1_DIR_Msk (0x1UL) /*!< EP1_DIR (Bitfield-Mask: 0x01) */ +#define SN_USB_CFG_EP2_DIR_Pos (1UL) /*!< EP2_DIR (Bit 1) */ +#define SN_USB_CFG_EP2_DIR_Msk (0x2UL) /*!< EP2_DIR (Bitfield-Mask: 0x01) */ +#define SN_USB_CFG_EP3_DIR_Pos (2UL) /*!< EP3_DIR (Bit 2) */ +#define SN_USB_CFG_EP3_DIR_Msk (0x4UL) /*!< EP3_DIR (Bitfield-Mask: 0x01) */ +#define SN_USB_CFG_EP4_DIR_Pos (3UL) /*!< EP4_DIR (Bit 3) */ +#define SN_USB_CFG_EP4_DIR_Msk (0x8UL) /*!< EP4_DIR (Bitfield-Mask: 0x01) */ +#define SN_USB_CFG_DIS_PDEN_Pos (26UL) /*!< DIS_PDEN (Bit 26) */ +#define SN_USB_CFG_DIS_PDEN_Msk (0x4000000UL) /*!< DIS_PDEN (Bitfield-Mask: 0x01) */ +#define SN_USB_CFG_ESD_EN_Pos (27UL) /*!< ESD_EN (Bit 27) */ +#define SN_USB_CFG_ESD_EN_Msk (0x8000000UL) /*!< ESD_EN (Bitfield-Mask: 0x01) */ +#define SN_USB_CFG_SIE_EN_Pos (28UL) /*!< SIE_EN (Bit 28) */ +#define SN_USB_CFG_SIE_EN_Msk (0x10000000UL) /*!< SIE_EN (Bitfield-Mask: 0x01) */ +#define SN_USB_CFG_DPPU_EN_Pos (29UL) /*!< DPPU_EN (Bit 29) */ +#define SN_USB_CFG_DPPU_EN_Msk (0x20000000UL) /*!< DPPU_EN (Bitfield-Mask: 0x01) */ +#define SN_USB_CFG_PHY_EN_Pos (30UL) /*!< PHY_EN (Bit 30) */ +#define SN_USB_CFG_PHY_EN_Msk (0x40000000UL) /*!< PHY_EN (Bitfield-Mask: 0x01) */ +#define SN_USB_CFG_VREG33_EN_Pos (31UL) /*!< VREG33_EN (Bit 31) */ +#define SN_USB_CFG_VREG33_EN_Msk (0x80000000UL) /*!< VREG33_EN (Bitfield-Mask: 0x01) */ +/* ========================================================= SGCTL ========================================================= */ +#define SN_USB_SGCTL_BUS_DN_Pos (0UL) /*!< BUS_DN (Bit 0) */ +#define SN_USB_SGCTL_BUS_DN_Msk (0x1UL) /*!< BUS_DN (Bitfield-Mask: 0x01) */ +#define SN_USB_SGCTL_BUS_DP_Pos (1UL) /*!< BUS_DP (Bit 1) */ +#define SN_USB_SGCTL_BUS_DP_Msk (0x2UL) /*!< BUS_DP (Bitfield-Mask: 0x01) */ +#define SN_USB_SGCTL_BUS_DRVEN_Pos (2UL) /*!< BUS_DRVEN (Bit 2) */ +#define SN_USB_SGCTL_BUS_DRVEN_Msk (0x4UL) /*!< BUS_DRVEN (Bitfield-Mask: 0x01) */ +/* ======================================================== EP0CTL ========================================================= */ +#define SN_USB_EP0CTL_ENDP_CNT_Pos (0UL) /*!< ENDP_CNT (Bit 0) */ +#define SN_USB_EP0CTL_ENDP_CNT_Msk (0x7fUL) /*!< ENDP_CNT (Bitfield-Mask: 0x7f) */ +#define SN_USB_EP0CTL_OUT_STALL_EN_Pos (27UL) /*!< OUT_STALL_EN (Bit 27) */ +#define SN_USB_EP0CTL_OUT_STALL_EN_Msk (0x8000000UL) /*!< OUT_STALL_EN (Bitfield-Mask: 0x01) */ +#define SN_USB_EP0CTL_IN_STALL_EN_Pos (28UL) /*!< IN_STALL_EN (Bit 28) */ +#define SN_USB_EP0CTL_IN_STALL_EN_Msk (0x10000000UL) /*!< IN_STALL_EN (Bitfield-Mask: 0x01) */ +#define SN_USB_EP0CTL_ENDP_STATE_Pos (29UL) /*!< ENDP_STATE (Bit 29) */ +#define SN_USB_EP0CTL_ENDP_STATE_Msk (0x60000000UL) /*!< ENDP_STATE (Bitfield-Mask: 0x03) */ +#define SN_USB_EP0CTL_ENDP_EN_Pos (31UL) /*!< ENDP_EN (Bit 31) */ +#define SN_USB_EP0CTL_ENDP_EN_Msk (0x80000000UL) /*!< ENDP_EN (Bitfield-Mask: 0x01) */ +/* ======================================================== EP1CTL ========================================================= */ +#define SN_USB_EP1CTL_ENDP_CNT_Pos (0UL) /*!< ENDP_CNT (Bit 0) */ +#define SN_USB_EP1CTL_ENDP_CNT_Msk (0x7fUL) /*!< ENDP_CNT (Bitfield-Mask: 0x7f) */ +#define SN_USB_EP1CTL_ENDP_STATE_Pos (29UL) /*!< ENDP_STATE (Bit 29) */ +#define SN_USB_EP1CTL_ENDP_STATE_Msk (0x60000000UL) /*!< ENDP_STATE (Bitfield-Mask: 0x03) */ +#define SN_USB_EP1CTL_ENDP_EN_Pos (31UL) /*!< ENDP_EN (Bit 31) */ +#define SN_USB_EP1CTL_ENDP_EN_Msk (0x80000000UL) /*!< ENDP_EN (Bitfield-Mask: 0x01) */ +/* ======================================================== EP2CTL ========================================================= */ +#define SN_USB_EP2CTL_ENDP_CNT_Pos (0UL) /*!< ENDP_CNT (Bit 0) */ +#define SN_USB_EP2CTL_ENDP_CNT_Msk (0x7fUL) /*!< ENDP_CNT (Bitfield-Mask: 0x7f) */ +#define SN_USB_EP2CTL_ENDP_STATE_Pos (29UL) /*!< ENDP_STATE (Bit 29) */ +#define SN_USB_EP2CTL_ENDP_STATE_Msk (0x60000000UL) /*!< ENDP_STATE (Bitfield-Mask: 0x03) */ +#define SN_USB_EP2CTL_ENDP_EN_Pos (31UL) /*!< ENDP_EN (Bit 31) */ +#define SN_USB_EP2CTL_ENDP_EN_Msk (0x80000000UL) /*!< ENDP_EN (Bitfield-Mask: 0x01) */ +/* ======================================================== EP3CTL ========================================================= */ +#define SN_USB_EP3CTL_ENDP_CNT_Pos (0UL) /*!< ENDP_CNT (Bit 0) */ +#define SN_USB_EP3CTL_ENDP_CNT_Msk (0x7fUL) /*!< ENDP_CNT (Bitfield-Mask: 0x7f) */ +#define SN_USB_EP3CTL_ENDP_STATE_Pos (29UL) /*!< ENDP_STATE (Bit 29) */ +#define SN_USB_EP3CTL_ENDP_STATE_Msk (0x60000000UL) /*!< ENDP_STATE (Bitfield-Mask: 0x03) */ +#define SN_USB_EP3CTL_ENDP_EN_Pos (31UL) /*!< ENDP_EN (Bit 31) */ +#define SN_USB_EP3CTL_ENDP_EN_Msk (0x80000000UL) /*!< ENDP_EN (Bitfield-Mask: 0x01) */ +/* ======================================================== EP4CTL ========================================================= */ +#define SN_USB_EP4CTL_ENDP_CNT_Pos (0UL) /*!< ENDP_CNT (Bit 0) */ +#define SN_USB_EP4CTL_ENDP_CNT_Msk (0x7fUL) /*!< ENDP_CNT (Bitfield-Mask: 0x7f) */ +#define SN_USB_EP4CTL_ENDP_STATE_Pos (29UL) /*!< ENDP_STATE (Bit 29) */ +#define SN_USB_EP4CTL_ENDP_STATE_Msk (0x60000000UL) /*!< ENDP_STATE (Bitfield-Mask: 0x03) */ +#define SN_USB_EP4CTL_ENDP_EN_Pos (31UL) /*!< ENDP_EN (Bit 31) */ +#define SN_USB_EP4CTL_ENDP_EN_Msk (0x80000000UL) /*!< ENDP_EN (Bitfield-Mask: 0x01) */ +/* ======================================================= EPTOGGLE ======================================================== */ +#define SN_USB_EPTOGGLE_ENDP1_DATA01_Pos (0UL) /*!< ENDP1_DATA01 (Bit 0) */ +#define SN_USB_EPTOGGLE_ENDP1_DATA01_Msk (0x1UL) /*!< ENDP1_DATA01 (Bitfield-Mask: 0x01) */ +#define SN_USB_EPTOGGLE_ENDP2_DATA01_Pos (1UL) /*!< ENDP2_DATA01 (Bit 1) */ +#define SN_USB_EPTOGGLE_ENDP2_DATA01_Msk (0x2UL) /*!< ENDP2_DATA01 (Bitfield-Mask: 0x01) */ +#define SN_USB_EPTOGGLE_ENDP3_DATA01_Pos (2UL) /*!< ENDP3_DATA01 (Bit 2) */ +#define SN_USB_EPTOGGLE_ENDP3_DATA01_Msk (0x4UL) /*!< ENDP3_DATA01 (Bitfield-Mask: 0x01) */ +#define SN_USB_EPTOGGLE_ENDP4_DATA01_Pos (3UL) /*!< ENDP4_DATA01 (Bit 3) */ +#define SN_USB_EPTOGGLE_ENDP4_DATA01_Msk (0x8UL) /*!< ENDP4_DATA01 (Bitfield-Mask: 0x01) */ +/* ======================================================= EP1BUFOS ======================================================== */ +#define SN_USB_EP1BUFOS_OFFSET_Pos (2UL) /*!< OFFSET (Bit 2) */ +#define SN_USB_EP1BUFOS_OFFSET_Msk (0x1fcUL) /*!< OFFSET (Bitfield-Mask: 0x7f) */ +/* ======================================================= EP2BUFOS ======================================================== */ +#define SN_USB_EP2BUFOS_OFFSET_Pos (2UL) /*!< OFFSET (Bit 2) */ +#define SN_USB_EP2BUFOS_OFFSET_Msk (0x1fcUL) /*!< OFFSET (Bitfield-Mask: 0x7f) */ +/* ======================================================= EP3BUFOS ======================================================== */ +#define SN_USB_EP3BUFOS_OFFSET_Pos (2UL) /*!< OFFSET (Bit 2) */ +#define SN_USB_EP3BUFOS_OFFSET_Msk (0x1fcUL) /*!< OFFSET (Bitfield-Mask: 0x7f) */ +/* ======================================================= EP4BUFOS ======================================================== */ +#define SN_USB_EP4BUFOS_OFFSET_Pos (2UL) /*!< OFFSET (Bit 2) */ +#define SN_USB_EP4BUFOS_OFFSET_Msk (0x1fcUL) /*!< OFFSET (Bitfield-Mask: 0x7f) */ +/* ========================================================= FRMNO ========================================================= */ +#define SN_USB_FRMNO_FRAME_NO_Pos (0UL) /*!< FRAME_NO (Bit 0) */ +#define SN_USB_FRMNO_FRAME_NO_Msk (0x7ffUL) /*!< FRAME_NO (Bitfield-Mask: 0x7ff) */ +/* ======================================================== PHYPRM ========================================================= */ +#define SN_USB_PHYPRM_PHY_PARAM_Pos (0UL) /*!< PHY_PARAM (Bit 0) */ +#define SN_USB_PHYPRM_PHY_PARAM_Msk (0x3fUL) /*!< PHY_PARAM (Bitfield-Mask: 0x3f) */ +/* ======================================================== PHYPRM2 ======================================================== */ +#define SN_USB_PHYPRM2_PHY_PS_Pos (0UL) /*!< PHY_PS (Bit 0) */ +#define SN_USB_PHYPRM2_PHY_PS_Msk (0x7fffUL) /*!< PHY_PS (Bitfield-Mask: 0x7fff) */ +/* ======================================================== PS2CTL ========================================================= */ +#define SN_USB_PS2CTL_SCKM_Pos (0UL) /*!< SCKM (Bit 0) */ +#define SN_USB_PS2CTL_SCKM_Msk (0x1UL) /*!< SCKM (Bitfield-Mask: 0x01) */ +#define SN_USB_PS2CTL_SDAM_Pos (1UL) /*!< SDAM (Bit 1) */ +#define SN_USB_PS2CTL_SDAM_Msk (0x2UL) /*!< SDAM (Bitfield-Mask: 0x01) */ +#define SN_USB_PS2CTL_SCK_Pos (2UL) /*!< SCK (Bit 2) */ +#define SN_USB_PS2CTL_SCK_Msk (0x4UL) /*!< SCK (Bitfield-Mask: 0x01) */ +#define SN_USB_PS2CTL_SDA_Pos (3UL) /*!< SDA (Bit 3) */ +#define SN_USB_PS2CTL_SDA_Msk (0x8UL) /*!< SDA (Bitfield-Mask: 0x01) */ +#define SN_USB_PS2CTL_PS2ENB_Pos (31UL) /*!< PS2ENB (Bit 31) */ +#define SN_USB_PS2CTL_PS2ENB_Msk (0x80000000UL) /*!< PS2ENB (Bitfield-Mask: 0x01) */ +/* ======================================================== RWADDR ========================================================= */ +#define SN_USB_RWADDR_RWADDR_Pos (2UL) /*!< RWADDR (Bit 2) */ +#define SN_USB_RWADDR_RWADDR_Msk (0xfcUL) /*!< RWADDR (Bitfield-Mask: 0x3f) */ +/* ======================================================== RWDATA ========================================================= */ +#define SN_USB_RWDATA_RWDATA_Pos (0UL) /*!< RWDATA (Bit 0) */ +#define SN_USB_RWDATA_RWDATA_Msk (0xffffffffUL) /*!< RWDATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= RWSTATUS ======================================================== */ +#define SN_USB_RWSTATUS_W_STATUS_Pos (0UL) /*!< W_STATUS (Bit 0) */ +#define SN_USB_RWSTATUS_W_STATUS_Msk (0x1UL) /*!< W_STATUS (Bitfield-Mask: 0x01) */ +#define SN_USB_RWSTATUS_R_STATUS_Pos (1UL) /*!< R_STATUS (Bit 1) */ +#define SN_USB_RWSTATUS_R_STATUS_Msk (0x2UL) /*!< R_STATUS (Bitfield-Mask: 0x01) */ +/* ======================================================== RWADDR2 ======================================================== */ +#define SN_USB_RWADDR2_RWADDR_Pos (2UL) /*!< RWADDR (Bit 2) */ +#define SN_USB_RWADDR2_RWADDR_Msk (0xfcUL) /*!< RWADDR (Bitfield-Mask: 0x3f) */ +/* ======================================================== RWDATA2 ======================================================== */ +#define SN_USB_RWDATA2_RWDATA_Pos (0UL) /*!< RWDATA (Bit 0) */ +#define SN_USB_RWDATA2_RWDATA_Msk (0xffffffffUL) /*!< RWDATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= RWSTATUS2 ======================================================= */ +#define SN_USB_RWSTATUS2_W_STATUS_Pos (0UL) /*!< W_STATUS (Bit 0) */ +#define SN_USB_RWSTATUS2_W_STATUS_Msk (0x1UL) /*!< W_STATUS (Bitfield-Mask: 0x01) */ +#define SN_USB_RWSTATUS2_R_STATUS_Pos (1UL) /*!< R_STATUS (Bit 1) */ +#define SN_USB_RWSTATUS2_R_STATUS_Msk (0x2UL) /*!< R_STATUS (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DATA ========================================================== */ +#define SN_GPIO0_DATA_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ +#define SN_GPIO0_DATA_DATA0_Msk (0x1UL) /*!< DATA0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_DATA_DATA1_Pos (1UL) /*!< DATA1 (Bit 1) */ +#define SN_GPIO0_DATA_DATA1_Msk (0x2UL) /*!< DATA1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_DATA_DATA2_Pos (2UL) /*!< DATA2 (Bit 2) */ +#define SN_GPIO0_DATA_DATA2_Msk (0x4UL) /*!< DATA2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_DATA_DATA3_Pos (3UL) /*!< DATA3 (Bit 3) */ +#define SN_GPIO0_DATA_DATA3_Msk (0x8UL) /*!< DATA3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_DATA_DATA4_Pos (4UL) /*!< DATA4 (Bit 4) */ +#define SN_GPIO0_DATA_DATA4_Msk (0x10UL) /*!< DATA4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_DATA_DATA5_Pos (5UL) /*!< DATA5 (Bit 5) */ +#define SN_GPIO0_DATA_DATA5_Msk (0x20UL) /*!< DATA5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_DATA_DATA6_Pos (6UL) /*!< DATA6 (Bit 6) */ +#define SN_GPIO0_DATA_DATA6_Msk (0x40UL) /*!< DATA6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_DATA_DATA7_Pos (7UL) /*!< DATA7 (Bit 7) */ +#define SN_GPIO0_DATA_DATA7_Msk (0x80UL) /*!< DATA7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_DATA_DATA8_Pos (8UL) /*!< DATA8 (Bit 8) */ +#define SN_GPIO0_DATA_DATA8_Msk (0x100UL) /*!< DATA8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_DATA_DATA9_Pos (9UL) /*!< DATA9 (Bit 9) */ +#define SN_GPIO0_DATA_DATA9_Msk (0x200UL) /*!< DATA9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_DATA_DATA10_Pos (10UL) /*!< DATA10 (Bit 10) */ +#define SN_GPIO0_DATA_DATA10_Msk (0x400UL) /*!< DATA10 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_DATA_DATA11_Pos (11UL) /*!< DATA11 (Bit 11) */ +#define SN_GPIO0_DATA_DATA11_Msk (0x800UL) /*!< DATA11 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_DATA_DATA12_Pos (12UL) /*!< DATA12 (Bit 12) */ +#define SN_GPIO0_DATA_DATA12_Msk (0x1000UL) /*!< DATA12 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_DATA_DATA13_Pos (13UL) /*!< DATA13 (Bit 13) */ +#define SN_GPIO0_DATA_DATA13_Msk (0x2000UL) /*!< DATA13 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_DATA_DATA14_Pos (14UL) /*!< DATA14 (Bit 14) */ +#define SN_GPIO0_DATA_DATA14_Msk (0x4000UL) /*!< DATA14 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_DATA_DATA15_Pos (15UL) /*!< DATA15 (Bit 15) */ +#define SN_GPIO0_DATA_DATA15_Msk (0x8000UL) /*!< DATA15 (Bitfield-Mask: 0x01) */ +/* ========================================================= MODE ========================================================== */ +#define SN_GPIO0_MODE_MODE0_Pos (0UL) /*!< MODE0 (Bit 0) */ +#define SN_GPIO0_MODE_MODE0_Msk (0x1UL) /*!< MODE0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_MODE_MODE1_Pos (1UL) /*!< MODE1 (Bit 1) */ +#define SN_GPIO0_MODE_MODE1_Msk (0x2UL) /*!< MODE1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_MODE_MODE2_Pos (2UL) /*!< MODE2 (Bit 2) */ +#define SN_GPIO0_MODE_MODE2_Msk (0x4UL) /*!< MODE2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_MODE_MODE3_Pos (3UL) /*!< MODE3 (Bit 3) */ +#define SN_GPIO0_MODE_MODE3_Msk (0x8UL) /*!< MODE3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_MODE_MODE4_Pos (4UL) /*!< MODE4 (Bit 4) */ +#define SN_GPIO0_MODE_MODE4_Msk (0x10UL) /*!< MODE4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_MODE_MODE5_Pos (5UL) /*!< MODE5 (Bit 5) */ +#define SN_GPIO0_MODE_MODE5_Msk (0x20UL) /*!< MODE5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_MODE_MODE6_Pos (6UL) /*!< MODE6 (Bit 6) */ +#define SN_GPIO0_MODE_MODE6_Msk (0x40UL) /*!< MODE6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_MODE_MODE7_Pos (7UL) /*!< MODE7 (Bit 7) */ +#define SN_GPIO0_MODE_MODE7_Msk (0x80UL) /*!< MODE7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_MODE_MODE8_Pos (8UL) /*!< MODE8 (Bit 8) */ +#define SN_GPIO0_MODE_MODE8_Msk (0x100UL) /*!< MODE8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_MODE_MODE9_Pos (9UL) /*!< MODE9 (Bit 9) */ +#define SN_GPIO0_MODE_MODE9_Msk (0x200UL) /*!< MODE9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_MODE_MODE10_Pos (10UL) /*!< MODE10 (Bit 10) */ +#define SN_GPIO0_MODE_MODE10_Msk (0x400UL) /*!< MODE10 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_MODE_MODE11_Pos (11UL) /*!< MODE11 (Bit 11) */ +#define SN_GPIO0_MODE_MODE11_Msk (0x800UL) /*!< MODE11 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_MODE_MODE12_Pos (12UL) /*!< MODE12 (Bit 12) */ +#define SN_GPIO0_MODE_MODE12_Msk (0x1000UL) /*!< MODE12 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_MODE_MODE13_Pos (13UL) /*!< MODE13 (Bit 13) */ +#define SN_GPIO0_MODE_MODE13_Msk (0x2000UL) /*!< MODE13 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_MODE_MODE14_Pos (14UL) /*!< MODE14 (Bit 14) */ +#define SN_GPIO0_MODE_MODE14_Msk (0x4000UL) /*!< MODE14 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_MODE_MODE15_Pos (15UL) /*!< MODE15 (Bit 15) */ +#define SN_GPIO0_MODE_MODE15_Msk (0x8000UL) /*!< MODE15 (Bitfield-Mask: 0x01) */ +/* ========================================================== CFG ========================================================== */ +#define SN_GPIO0_CFG_CFG0_Pos (0UL) /*!< CFG0 (Bit 0) */ +#define SN_GPIO0_CFG_CFG0_Msk (0x3UL) /*!< CFG0 (Bitfield-Mask: 0x03) */ +#define SN_GPIO0_CFG_CFG1_Pos (2UL) /*!< CFG1 (Bit 2) */ +#define SN_GPIO0_CFG_CFG1_Msk (0xcUL) /*!< CFG1 (Bitfield-Mask: 0x03) */ +#define SN_GPIO0_CFG_CFG2_Pos (4UL) /*!< CFG2 (Bit 4) */ +#define SN_GPIO0_CFG_CFG2_Msk (0x30UL) /*!< CFG2 (Bitfield-Mask: 0x03) */ +#define SN_GPIO0_CFG_CFG3_Pos (6UL) /*!< CFG3 (Bit 6) */ +#define SN_GPIO0_CFG_CFG3_Msk (0xc0UL) /*!< CFG3 (Bitfield-Mask: 0x03) */ +#define SN_GPIO0_CFG_CFG4_Pos (8UL) /*!< CFG4 (Bit 8) */ +#define SN_GPIO0_CFG_CFG4_Msk (0x300UL) /*!< CFG4 (Bitfield-Mask: 0x03) */ +#define SN_GPIO0_CFG_CFG5_Pos (10UL) /*!< CFG5 (Bit 10) */ +#define SN_GPIO0_CFG_CFG5_Msk (0xc00UL) /*!< CFG5 (Bitfield-Mask: 0x03) */ +#define SN_GPIO0_CFG_CFG6_Pos (12UL) /*!< CFG6 (Bit 12) */ +#define SN_GPIO0_CFG_CFG6_Msk (0x3000UL) /*!< CFG6 (Bitfield-Mask: 0x03) */ +#define SN_GPIO0_CFG_CFG7_Pos (14UL) /*!< CFG7 (Bit 14) */ +#define SN_GPIO0_CFG_CFG7_Msk (0xc000UL) /*!< CFG7 (Bitfield-Mask: 0x03) */ +#define SN_GPIO0_CFG_CFG8_Pos (16UL) /*!< CFG8 (Bit 16) */ +#define SN_GPIO0_CFG_CFG8_Msk (0x30000UL) /*!< CFG8 (Bitfield-Mask: 0x03) */ +#define SN_GPIO0_CFG_CFG9_Pos (18UL) /*!< CFG9 (Bit 18) */ +#define SN_GPIO0_CFG_CFG9_Msk (0xc0000UL) /*!< CFG9 (Bitfield-Mask: 0x03) */ +#define SN_GPIO0_CFG_CFG10_Pos (20UL) /*!< CFG10 (Bit 20) */ +#define SN_GPIO0_CFG_CFG10_Msk (0x300000UL) /*!< CFG10 (Bitfield-Mask: 0x03) */ +#define SN_GPIO0_CFG_CFG11_Pos (22UL) /*!< CFG11 (Bit 22) */ +#define SN_GPIO0_CFG_CFG11_Msk (0xc00000UL) /*!< CFG11 (Bitfield-Mask: 0x03) */ +#define SN_GPIO0_CFG_CFG12_Pos (24UL) /*!< CFG12 (Bit 24) */ +#define SN_GPIO0_CFG_CFG12_Msk (0x3000000UL) /*!< CFG12 (Bitfield-Mask: 0x03) */ +#define SN_GPIO0_CFG_CFG13_Pos (26UL) /*!< CFG13 (Bit 26) */ +#define SN_GPIO0_CFG_CFG13_Msk (0xc000000UL) /*!< CFG13 (Bitfield-Mask: 0x03) */ +#define SN_GPIO0_CFG_CFG14_Pos (28UL) /*!< CFG14 (Bit 28) */ +#define SN_GPIO0_CFG_CFG14_Msk (0x30000000UL) /*!< CFG14 (Bitfield-Mask: 0x03) */ +#define SN_GPIO0_CFG_CFG15_Pos (30UL) /*!< CFG15 (Bit 30) */ +#define SN_GPIO0_CFG_CFG15_Msk (0xc0000000UL) /*!< CFG15 (Bitfield-Mask: 0x03) */ +/* ========================================================== IS =========================================================== */ +#define SN_GPIO0_IS_IS0_Pos (0UL) /*!< IS0 (Bit 0) */ +#define SN_GPIO0_IS_IS0_Msk (0x1UL) /*!< IS0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IS_IS1_Pos (1UL) /*!< IS1 (Bit 1) */ +#define SN_GPIO0_IS_IS1_Msk (0x2UL) /*!< IS1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IS_IS2_Pos (2UL) /*!< IS2 (Bit 2) */ +#define SN_GPIO0_IS_IS2_Msk (0x4UL) /*!< IS2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IS_IS3_Pos (3UL) /*!< IS3 (Bit 3) */ +#define SN_GPIO0_IS_IS3_Msk (0x8UL) /*!< IS3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IS_IS4_Pos (4UL) /*!< IS4 (Bit 4) */ +#define SN_GPIO0_IS_IS4_Msk (0x10UL) /*!< IS4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IS_IS5_Pos (5UL) /*!< IS5 (Bit 5) */ +#define SN_GPIO0_IS_IS5_Msk (0x20UL) /*!< IS5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IS_IS6_Pos (6UL) /*!< IS6 (Bit 6) */ +#define SN_GPIO0_IS_IS6_Msk (0x40UL) /*!< IS6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IS_IS7_Pos (7UL) /*!< IS7 (Bit 7) */ +#define SN_GPIO0_IS_IS7_Msk (0x80UL) /*!< IS7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IS_IS8_Pos (8UL) /*!< IS8 (Bit 8) */ +#define SN_GPIO0_IS_IS8_Msk (0x100UL) /*!< IS8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IS_IS9_Pos (9UL) /*!< IS9 (Bit 9) */ +#define SN_GPIO0_IS_IS9_Msk (0x200UL) /*!< IS9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IS_IS10_Pos (10UL) /*!< IS10 (Bit 10) */ +#define SN_GPIO0_IS_IS10_Msk (0x400UL) /*!< IS10 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IS_IS11_Pos (11UL) /*!< IS11 (Bit 11) */ +#define SN_GPIO0_IS_IS11_Msk (0x800UL) /*!< IS11 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IS_IS12_Pos (12UL) /*!< IS12 (Bit 12) */ +#define SN_GPIO0_IS_IS12_Msk (0x1000UL) /*!< IS12 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IS_IS13_Pos (13UL) /*!< IS13 (Bit 13) */ +#define SN_GPIO0_IS_IS13_Msk (0x2000UL) /*!< IS13 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IS_IS14_Pos (14UL) /*!< IS14 (Bit 14) */ +#define SN_GPIO0_IS_IS14_Msk (0x4000UL) /*!< IS14 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IS_IS15_Pos (15UL) /*!< IS15 (Bit 15) */ +#define SN_GPIO0_IS_IS15_Msk (0x8000UL) /*!< IS15 (Bitfield-Mask: 0x01) */ +/* ========================================================== IBS ========================================================== */ +#define SN_GPIO0_IBS_IBS0_Pos (0UL) /*!< IBS0 (Bit 0) */ +#define SN_GPIO0_IBS_IBS0_Msk (0x1UL) /*!< IBS0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IBS_IBS1_Pos (1UL) /*!< IBS1 (Bit 1) */ +#define SN_GPIO0_IBS_IBS1_Msk (0x2UL) /*!< IBS1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IBS_IBS2_Pos (2UL) /*!< IBS2 (Bit 2) */ +#define SN_GPIO0_IBS_IBS2_Msk (0x4UL) /*!< IBS2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IBS_IBS3_Pos (3UL) /*!< IBS3 (Bit 3) */ +#define SN_GPIO0_IBS_IBS3_Msk (0x8UL) /*!< IBS3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IBS_IBS4_Pos (4UL) /*!< IBS4 (Bit 4) */ +#define SN_GPIO0_IBS_IBS4_Msk (0x10UL) /*!< IBS4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IBS_IBS5_Pos (5UL) /*!< IBS5 (Bit 5) */ +#define SN_GPIO0_IBS_IBS5_Msk (0x20UL) /*!< IBS5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IBS_IBS6_Pos (6UL) /*!< IBS6 (Bit 6) */ +#define SN_GPIO0_IBS_IBS6_Msk (0x40UL) /*!< IBS6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IBS_IBS7_Pos (7UL) /*!< IBS7 (Bit 7) */ +#define SN_GPIO0_IBS_IBS7_Msk (0x80UL) /*!< IBS7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IBS_IBS8_Pos (8UL) /*!< IBS8 (Bit 8) */ +#define SN_GPIO0_IBS_IBS8_Msk (0x100UL) /*!< IBS8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IBS_IBS9_Pos (9UL) /*!< IBS9 (Bit 9) */ +#define SN_GPIO0_IBS_IBS9_Msk (0x200UL) /*!< IBS9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IBS_IBS10_Pos (10UL) /*!< IBS10 (Bit 10) */ +#define SN_GPIO0_IBS_IBS10_Msk (0x400UL) /*!< IBS10 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IBS_IBS11_Pos (11UL) /*!< IBS11 (Bit 11) */ +#define SN_GPIO0_IBS_IBS11_Msk (0x800UL) /*!< IBS11 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IBS_IBS12_Pos (12UL) /*!< IBS12 (Bit 12) */ +#define SN_GPIO0_IBS_IBS12_Msk (0x1000UL) /*!< IBS12 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IBS_IBS13_Pos (13UL) /*!< IBS13 (Bit 13) */ +#define SN_GPIO0_IBS_IBS13_Msk (0x2000UL) /*!< IBS13 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IBS_IBS14_Pos (14UL) /*!< IBS14 (Bit 14) */ +#define SN_GPIO0_IBS_IBS14_Msk (0x4000UL) /*!< IBS14 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IBS_IBS15_Pos (15UL) /*!< IBS15 (Bit 15) */ +#define SN_GPIO0_IBS_IBS15_Msk (0x8000UL) /*!< IBS15 (Bitfield-Mask: 0x01) */ +/* ========================================================== IEV ========================================================== */ +#define SN_GPIO0_IEV_IEV0_Pos (0UL) /*!< IEV0 (Bit 0) */ +#define SN_GPIO0_IEV_IEV0_Msk (0x1UL) /*!< IEV0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IEV_IEV1_Pos (1UL) /*!< IEV1 (Bit 1) */ +#define SN_GPIO0_IEV_IEV1_Msk (0x2UL) /*!< IEV1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IEV_IEV2_Pos (2UL) /*!< IEV2 (Bit 2) */ +#define SN_GPIO0_IEV_IEV2_Msk (0x4UL) /*!< IEV2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IEV_IEV3_Pos (3UL) /*!< IEV3 (Bit 3) */ +#define SN_GPIO0_IEV_IEV3_Msk (0x8UL) /*!< IEV3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IEV_IEV4_Pos (4UL) /*!< IEV4 (Bit 4) */ +#define SN_GPIO0_IEV_IEV4_Msk (0x10UL) /*!< IEV4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IEV_IEV5_Pos (5UL) /*!< IEV5 (Bit 5) */ +#define SN_GPIO0_IEV_IEV5_Msk (0x20UL) /*!< IEV5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IEV_IEV6_Pos (6UL) /*!< IEV6 (Bit 6) */ +#define SN_GPIO0_IEV_IEV6_Msk (0x40UL) /*!< IEV6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IEV_IEV7_Pos (7UL) /*!< IEV7 (Bit 7) */ +#define SN_GPIO0_IEV_IEV7_Msk (0x80UL) /*!< IEV7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IEV_IEV8_Pos (8UL) /*!< IEV8 (Bit 8) */ +#define SN_GPIO0_IEV_IEV8_Msk (0x100UL) /*!< IEV8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IEV_IEV9_Pos (9UL) /*!< IEV9 (Bit 9) */ +#define SN_GPIO0_IEV_IEV9_Msk (0x200UL) /*!< IEV9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IEV_IEV10_Pos (10UL) /*!< IEV10 (Bit 10) */ +#define SN_GPIO0_IEV_IEV10_Msk (0x400UL) /*!< IEV10 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IEV_IEV11_Pos (11UL) /*!< IEV11 (Bit 11) */ +#define SN_GPIO0_IEV_IEV11_Msk (0x800UL) /*!< IEV11 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IEV_IEV12_Pos (12UL) /*!< IEV12 (Bit 12) */ +#define SN_GPIO0_IEV_IEV12_Msk (0x1000UL) /*!< IEV12 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IEV_IEV13_Pos (13UL) /*!< IEV13 (Bit 13) */ +#define SN_GPIO0_IEV_IEV13_Msk (0x2000UL) /*!< IEV13 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IEV_IEV14_Pos (14UL) /*!< IEV14 (Bit 14) */ +#define SN_GPIO0_IEV_IEV14_Msk (0x4000UL) /*!< IEV14 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IEV_IEV15_Pos (15UL) /*!< IEV15 (Bit 15) */ +#define SN_GPIO0_IEV_IEV15_Msk (0x8000UL) /*!< IEV15 (Bitfield-Mask: 0x01) */ +/* ========================================================== IE =========================================================== */ +#define SN_GPIO0_IE_IE0_Pos (0UL) /*!< IE0 (Bit 0) */ +#define SN_GPIO0_IE_IE0_Msk (0x1UL) /*!< IE0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IE_IE1_Pos (1UL) /*!< IE1 (Bit 1) */ +#define SN_GPIO0_IE_IE1_Msk (0x2UL) /*!< IE1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IE_IE2_Pos (2UL) /*!< IE2 (Bit 2) */ +#define SN_GPIO0_IE_IE2_Msk (0x4UL) /*!< IE2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IE_IE3_Pos (3UL) /*!< IE3 (Bit 3) */ +#define SN_GPIO0_IE_IE3_Msk (0x8UL) /*!< IE3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IE_IE4_Pos (4UL) /*!< IE4 (Bit 4) */ +#define SN_GPIO0_IE_IE4_Msk (0x10UL) /*!< IE4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IE_IE5_Pos (5UL) /*!< IE5 (Bit 5) */ +#define SN_GPIO0_IE_IE5_Msk (0x20UL) /*!< IE5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IE_IE6_Pos (6UL) /*!< IE6 (Bit 6) */ +#define SN_GPIO0_IE_IE6_Msk (0x40UL) /*!< IE6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IE_IE7_Pos (7UL) /*!< IE7 (Bit 7) */ +#define SN_GPIO0_IE_IE7_Msk (0x80UL) /*!< IE7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IE_IE8_Pos (8UL) /*!< IE8 (Bit 8) */ +#define SN_GPIO0_IE_IE8_Msk (0x100UL) /*!< IE8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IE_IE9_Pos (9UL) /*!< IE9 (Bit 9) */ +#define SN_GPIO0_IE_IE9_Msk (0x200UL) /*!< IE9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IE_IE10_Pos (10UL) /*!< IE10 (Bit 10) */ +#define SN_GPIO0_IE_IE10_Msk (0x400UL) /*!< IE10 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IE_IE11_Pos (11UL) /*!< IE11 (Bit 11) */ +#define SN_GPIO0_IE_IE11_Msk (0x800UL) /*!< IE11 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IE_IE12_Pos (12UL) /*!< IE12 (Bit 12) */ +#define SN_GPIO0_IE_IE12_Msk (0x1000UL) /*!< IE12 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IE_IE13_Pos (13UL) /*!< IE13 (Bit 13) */ +#define SN_GPIO0_IE_IE13_Msk (0x2000UL) /*!< IE13 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IE_IE14_Pos (14UL) /*!< IE14 (Bit 14) */ +#define SN_GPIO0_IE_IE14_Msk (0x4000UL) /*!< IE14 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IE_IE15_Pos (15UL) /*!< IE15 (Bit 15) */ +#define SN_GPIO0_IE_IE15_Msk (0x8000UL) /*!< IE15 (Bitfield-Mask: 0x01) */ +/* ========================================================== RIS ========================================================== */ +#define SN_GPIO0_RIS_IF0_Pos (0UL) /*!< IF0 (Bit 0) */ +#define SN_GPIO0_RIS_IF0_Msk (0x1UL) /*!< IF0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_RIS_IF1_Pos (1UL) /*!< IF1 (Bit 1) */ +#define SN_GPIO0_RIS_IF1_Msk (0x2UL) /*!< IF1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_RIS_IF2_Pos (2UL) /*!< IF2 (Bit 2) */ +#define SN_GPIO0_RIS_IF2_Msk (0x4UL) /*!< IF2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_RIS_IF3_Pos (3UL) /*!< IF3 (Bit 3) */ +#define SN_GPIO0_RIS_IF3_Msk (0x8UL) /*!< IF3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_RIS_IF4_Pos (4UL) /*!< IF4 (Bit 4) */ +#define SN_GPIO0_RIS_IF4_Msk (0x10UL) /*!< IF4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_RIS_IF5_Pos (5UL) /*!< IF5 (Bit 5) */ +#define SN_GPIO0_RIS_IF5_Msk (0x20UL) /*!< IF5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_RIS_IF6_Pos (6UL) /*!< IF6 (Bit 6) */ +#define SN_GPIO0_RIS_IF6_Msk (0x40UL) /*!< IF6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_RIS_IF7_Pos (7UL) /*!< IF7 (Bit 7) */ +#define SN_GPIO0_RIS_IF7_Msk (0x80UL) /*!< IF7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_RIS_IF8_Pos (8UL) /*!< IF8 (Bit 8) */ +#define SN_GPIO0_RIS_IF8_Msk (0x100UL) /*!< IF8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_RIS_IF9_Pos (9UL) /*!< IF9 (Bit 9) */ +#define SN_GPIO0_RIS_IF9_Msk (0x200UL) /*!< IF9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_RIS_IF10_Pos (10UL) /*!< IF10 (Bit 10) */ +#define SN_GPIO0_RIS_IF10_Msk (0x400UL) /*!< IF10 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_RIS_IF11_Pos (11UL) /*!< IF11 (Bit 11) */ +#define SN_GPIO0_RIS_IF11_Msk (0x800UL) /*!< IF11 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_RIS_IF12_Pos (12UL) /*!< IF12 (Bit 12) */ +#define SN_GPIO0_RIS_IF12_Msk (0x1000UL) /*!< IF12 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_RIS_IF13_Pos (13UL) /*!< IF13 (Bit 13) */ +#define SN_GPIO0_RIS_IF13_Msk (0x2000UL) /*!< IF13 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_RIS_IF14_Pos (14UL) /*!< IF14 (Bit 14) */ +#define SN_GPIO0_RIS_IF14_Msk (0x4000UL) /*!< IF14 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_RIS_IF15_Pos (15UL) /*!< IF15 (Bit 15) */ +#define SN_GPIO0_RIS_IF15_Msk (0x8000UL) /*!< IF15 (Bitfield-Mask: 0x01) */ +/* ========================================================== IC =========================================================== */ +#define SN_GPIO0_IC_IC0_Pos (0UL) /*!< IC0 (Bit 0) */ +#define SN_GPIO0_IC_IC0_Msk (0x1UL) /*!< IC0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IC_IC1_Pos (1UL) /*!< IC1 (Bit 1) */ +#define SN_GPIO0_IC_IC1_Msk (0x2UL) /*!< IC1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IC_IC2_Pos (2UL) /*!< IC2 (Bit 2) */ +#define SN_GPIO0_IC_IC2_Msk (0x4UL) /*!< IC2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IC_IC3_Pos (3UL) /*!< IC3 (Bit 3) */ +#define SN_GPIO0_IC_IC3_Msk (0x8UL) /*!< IC3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IC_IC4_Pos (4UL) /*!< IC4 (Bit 4) */ +#define SN_GPIO0_IC_IC4_Msk (0x10UL) /*!< IC4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IC_IC5_Pos (5UL) /*!< IC5 (Bit 5) */ +#define SN_GPIO0_IC_IC5_Msk (0x20UL) /*!< IC5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IC_IC6_Pos (6UL) /*!< IC6 (Bit 6) */ +#define SN_GPIO0_IC_IC6_Msk (0x40UL) /*!< IC6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IC_IC7_Pos (7UL) /*!< IC7 (Bit 7) */ +#define SN_GPIO0_IC_IC7_Msk (0x80UL) /*!< IC7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IC_IC8_Pos (8UL) /*!< IC8 (Bit 8) */ +#define SN_GPIO0_IC_IC8_Msk (0x100UL) /*!< IC8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IC_IC9_Pos (9UL) /*!< IC9 (Bit 9) */ +#define SN_GPIO0_IC_IC9_Msk (0x200UL) /*!< IC9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IC_IC10_Pos (10UL) /*!< IC10 (Bit 10) */ +#define SN_GPIO0_IC_IC10_Msk (0x400UL) /*!< IC10 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IC_IC11_Pos (11UL) /*!< IC11 (Bit 11) */ +#define SN_GPIO0_IC_IC11_Msk (0x800UL) /*!< IC11 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IC_IC12_Pos (12UL) /*!< IC12 (Bit 12) */ +#define SN_GPIO0_IC_IC12_Msk (0x1000UL) /*!< IC12 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IC_IC13_Pos (13UL) /*!< IC13 (Bit 13) */ +#define SN_GPIO0_IC_IC13_Msk (0x2000UL) /*!< IC13 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IC_IC14_Pos (14UL) /*!< IC14 (Bit 14) */ +#define SN_GPIO0_IC_IC14_Msk (0x4000UL) /*!< IC14 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_IC_IC15_Pos (15UL) /*!< IC15 (Bit 15) */ +#define SN_GPIO0_IC_IC15_Msk (0x8000UL) /*!< IC15 (Bitfield-Mask: 0x01) */ +/* ========================================================= BSET ========================================================== */ +#define SN_GPIO0_BSET_BSET0_Pos (0UL) /*!< BSET0 (Bit 0) */ +#define SN_GPIO0_BSET_BSET0_Msk (0x1UL) /*!< BSET0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BSET_BSET1_Pos (1UL) /*!< BSET1 (Bit 1) */ +#define SN_GPIO0_BSET_BSET1_Msk (0x2UL) /*!< BSET1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BSET_BSET2_Pos (2UL) /*!< BSET2 (Bit 2) */ +#define SN_GPIO0_BSET_BSET2_Msk (0x4UL) /*!< BSET2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BSET_BSET3_Pos (3UL) /*!< BSET3 (Bit 3) */ +#define SN_GPIO0_BSET_BSET3_Msk (0x8UL) /*!< BSET3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BSET_BSET4_Pos (4UL) /*!< BSET4 (Bit 4) */ +#define SN_GPIO0_BSET_BSET4_Msk (0x10UL) /*!< BSET4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BSET_BSET5_Pos (5UL) /*!< BSET5 (Bit 5) */ +#define SN_GPIO0_BSET_BSET5_Msk (0x20UL) /*!< BSET5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BSET_BSET6_Pos (6UL) /*!< BSET6 (Bit 6) */ +#define SN_GPIO0_BSET_BSET6_Msk (0x40UL) /*!< BSET6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BSET_BSET7_Pos (7UL) /*!< BSET7 (Bit 7) */ +#define SN_GPIO0_BSET_BSET7_Msk (0x80UL) /*!< BSET7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BSET_BSET8_Pos (8UL) /*!< BSET8 (Bit 8) */ +#define SN_GPIO0_BSET_BSET8_Msk (0x100UL) /*!< BSET8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BSET_BSET9_Pos (9UL) /*!< BSET9 (Bit 9) */ +#define SN_GPIO0_BSET_BSET9_Msk (0x200UL) /*!< BSET9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BSET_BSET10_Pos (10UL) /*!< BSET10 (Bit 10) */ +#define SN_GPIO0_BSET_BSET10_Msk (0x400UL) /*!< BSET10 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BSET_BSET11_Pos (11UL) /*!< BSET11 (Bit 11) */ +#define SN_GPIO0_BSET_BSET11_Msk (0x800UL) /*!< BSET11 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BSET_BSET12_Pos (12UL) /*!< BSET12 (Bit 12) */ +#define SN_GPIO0_BSET_BSET12_Msk (0x1000UL) /*!< BSET12 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BSET_BSET13_Pos (13UL) /*!< BSET13 (Bit 13) */ +#define SN_GPIO0_BSET_BSET13_Msk (0x2000UL) /*!< BSET13 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BSET_BSET14_Pos (14UL) /*!< BSET14 (Bit 14) */ +#define SN_GPIO0_BSET_BSET14_Msk (0x4000UL) /*!< BSET14 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BSET_BSET15_Pos (15UL) /*!< BSET15 (Bit 15) */ +#define SN_GPIO0_BSET_BSET15_Msk (0x8000UL) /*!< BSET15 (Bitfield-Mask: 0x01) */ +/* ========================================================= BCLR ========================================================== */ +#define SN_GPIO0_BCLR_BCLR0_Pos (0UL) /*!< BCLR0 (Bit 0) */ +#define SN_GPIO0_BCLR_BCLR0_Msk (0x1UL) /*!< BCLR0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BCLR_BCLR1_Pos (1UL) /*!< BCLR1 (Bit 1) */ +#define SN_GPIO0_BCLR_BCLR1_Msk (0x2UL) /*!< BCLR1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BCLR_BCLR2_Pos (2UL) /*!< BCLR2 (Bit 2) */ +#define SN_GPIO0_BCLR_BCLR2_Msk (0x4UL) /*!< BCLR2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BCLR_BCLR3_Pos (3UL) /*!< BCLR3 (Bit 3) */ +#define SN_GPIO0_BCLR_BCLR3_Msk (0x8UL) /*!< BCLR3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BCLR_BCLR4_Pos (4UL) /*!< BCLR4 (Bit 4) */ +#define SN_GPIO0_BCLR_BCLR4_Msk (0x10UL) /*!< BCLR4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BCLR_BCLR5_Pos (5UL) /*!< BCLR5 (Bit 5) */ +#define SN_GPIO0_BCLR_BCLR5_Msk (0x20UL) /*!< BCLR5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BCLR_BCLR6_Pos (6UL) /*!< BCLR6 (Bit 6) */ +#define SN_GPIO0_BCLR_BCLR6_Msk (0x40UL) /*!< BCLR6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BCLR_BCLR7_Pos (7UL) /*!< BCLR7 (Bit 7) */ +#define SN_GPIO0_BCLR_BCLR7_Msk (0x80UL) /*!< BCLR7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BCLR_BCLR8_Pos (8UL) /*!< BCLR8 (Bit 8) */ +#define SN_GPIO0_BCLR_BCLR8_Msk (0x100UL) /*!< BCLR8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BCLR_BCLR9_Pos (9UL) /*!< BCLR9 (Bit 9) */ +#define SN_GPIO0_BCLR_BCLR9_Msk (0x200UL) /*!< BCLR9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BCLR_BCLR10_Pos (10UL) /*!< BCLR10 (Bit 10) */ +#define SN_GPIO0_BCLR_BCLR10_Msk (0x400UL) /*!< BCLR10 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BCLR_BCLR11_Pos (11UL) /*!< BCLR11 (Bit 11) */ +#define SN_GPIO0_BCLR_BCLR11_Msk (0x800UL) /*!< BCLR11 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BCLR_BCLR12_Pos (12UL) /*!< BCLR12 (Bit 12) */ +#define SN_GPIO0_BCLR_BCLR12_Msk (0x1000UL) /*!< BCLR12 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BCLR_BCLR13_Pos (13UL) /*!< BCLR13 (Bit 13) */ +#define SN_GPIO0_BCLR_BCLR13_Msk (0x2000UL) /*!< BCLR13 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BCLR_BCLR14_Pos (14UL) /*!< BCLR14 (Bit 14) */ +#define SN_GPIO0_BCLR_BCLR14_Msk (0x4000UL) /*!< BCLR14 (Bitfield-Mask: 0x01) */ +#define SN_GPIO0_BCLR_BCLR15_Pos (15UL) /*!< BCLR15 (Bit 15) */ +#define SN_GPIO0_BCLR_BCLR15_Msk (0x8000UL) /*!< BCLR15 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DATA ========================================================== */ +#define SN_GPIO1_DATA_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ +#define SN_GPIO1_DATA_DATA0_Msk (0x1UL) /*!< DATA0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_DATA_DATA1_Pos (1UL) /*!< DATA1 (Bit 1) */ +#define SN_GPIO1_DATA_DATA1_Msk (0x2UL) /*!< DATA1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_DATA_DATA2_Pos (2UL) /*!< DATA2 (Bit 2) */ +#define SN_GPIO1_DATA_DATA2_Msk (0x4UL) /*!< DATA2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_DATA_DATA3_Pos (3UL) /*!< DATA3 (Bit 3) */ +#define SN_GPIO1_DATA_DATA3_Msk (0x8UL) /*!< DATA3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_DATA_DATA4_Pos (4UL) /*!< DATA4 (Bit 4) */ +#define SN_GPIO1_DATA_DATA4_Msk (0x10UL) /*!< DATA4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_DATA_DATA5_Pos (5UL) /*!< DATA5 (Bit 5) */ +#define SN_GPIO1_DATA_DATA5_Msk (0x20UL) /*!< DATA5 (Bitfield-Mask: 0x01) */ +/* ========================================================= MODE ========================================================== */ +#define SN_GPIO1_MODE_MODE0_Pos (0UL) /*!< MODE0 (Bit 0) */ +#define SN_GPIO1_MODE_MODE0_Msk (0x1UL) /*!< MODE0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_MODE_MODE1_Pos (1UL) /*!< MODE1 (Bit 1) */ +#define SN_GPIO1_MODE_MODE1_Msk (0x2UL) /*!< MODE1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_MODE_MODE2_Pos (2UL) /*!< MODE2 (Bit 2) */ +#define SN_GPIO1_MODE_MODE2_Msk (0x4UL) /*!< MODE2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_MODE_MODE3_Pos (3UL) /*!< MODE3 (Bit 3) */ +#define SN_GPIO1_MODE_MODE3_Msk (0x8UL) /*!< MODE3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_MODE_MODE4_Pos (4UL) /*!< MODE4 (Bit 4) */ +#define SN_GPIO1_MODE_MODE4_Msk (0x10UL) /*!< MODE4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_MODE_MODE5_Pos (5UL) /*!< MODE5 (Bit 5) */ +#define SN_GPIO1_MODE_MODE5_Msk (0x20UL) /*!< MODE5 (Bitfield-Mask: 0x01) */ +/* ========================================================== CFG ========================================================== */ +#define SN_GPIO1_CFG_CFG0_Pos (0UL) /*!< CFG0 (Bit 0) */ +#define SN_GPIO1_CFG_CFG0_Msk (0x3UL) /*!< CFG0 (Bitfield-Mask: 0x03) */ +#define SN_GPIO1_CFG_CFG1_Pos (2UL) /*!< CFG1 (Bit 2) */ +#define SN_GPIO1_CFG_CFG1_Msk (0xcUL) /*!< CFG1 (Bitfield-Mask: 0x03) */ +#define SN_GPIO1_CFG_CFG2_Pos (4UL) /*!< CFG2 (Bit 4) */ +#define SN_GPIO1_CFG_CFG2_Msk (0x30UL) /*!< CFG2 (Bitfield-Mask: 0x03) */ +#define SN_GPIO1_CFG_CFG3_Pos (6UL) /*!< CFG3 (Bit 6) */ +#define SN_GPIO1_CFG_CFG3_Msk (0xc0UL) /*!< CFG3 (Bitfield-Mask: 0x03) */ +#define SN_GPIO1_CFG_CFG4_Pos (8UL) /*!< CFG4 (Bit 8) */ +#define SN_GPIO1_CFG_CFG4_Msk (0x300UL) /*!< CFG4 (Bitfield-Mask: 0x03) */ +#define SN_GPIO1_CFG_CFG5_Pos (10UL) /*!< CFG5 (Bit 10) */ +#define SN_GPIO1_CFG_CFG5_Msk (0xc00UL) /*!< CFG5 (Bitfield-Mask: 0x03) */ +/* ========================================================== IS =========================================================== */ +#define SN_GPIO1_IS_IS0_Pos (0UL) /*!< IS0 (Bit 0) */ +#define SN_GPIO1_IS_IS0_Msk (0x1UL) /*!< IS0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IS_IS1_Pos (1UL) /*!< IS1 (Bit 1) */ +#define SN_GPIO1_IS_IS1_Msk (0x2UL) /*!< IS1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IS_IS2_Pos (2UL) /*!< IS2 (Bit 2) */ +#define SN_GPIO1_IS_IS2_Msk (0x4UL) /*!< IS2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IS_IS3_Pos (3UL) /*!< IS3 (Bit 3) */ +#define SN_GPIO1_IS_IS3_Msk (0x8UL) /*!< IS3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IS_IS4_Pos (4UL) /*!< IS4 (Bit 4) */ +#define SN_GPIO1_IS_IS4_Msk (0x10UL) /*!< IS4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IS_IS5_Pos (5UL) /*!< IS5 (Bit 5) */ +#define SN_GPIO1_IS_IS5_Msk (0x20UL) /*!< IS5 (Bitfield-Mask: 0x01) */ +/* ========================================================== IBS ========================================================== */ +#define SN_GPIO1_IBS_IBS0_Pos (0UL) /*!< IBS0 (Bit 0) */ +#define SN_GPIO1_IBS_IBS0_Msk (0x1UL) /*!< IBS0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IBS_IBS1_Pos (1UL) /*!< IBS1 (Bit 1) */ +#define SN_GPIO1_IBS_IBS1_Msk (0x2UL) /*!< IBS1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IBS_IBS2_Pos (2UL) /*!< IBS2 (Bit 2) */ +#define SN_GPIO1_IBS_IBS2_Msk (0x4UL) /*!< IBS2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IBS_IBS3_Pos (3UL) /*!< IBS3 (Bit 3) */ +#define SN_GPIO1_IBS_IBS3_Msk (0x8UL) /*!< IBS3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IBS_IBS4_Pos (4UL) /*!< IBS4 (Bit 4) */ +#define SN_GPIO1_IBS_IBS4_Msk (0x10UL) /*!< IBS4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IBS_IBS5_Pos (5UL) /*!< IBS5 (Bit 5) */ +#define SN_GPIO1_IBS_IBS5_Msk (0x20UL) /*!< IBS5 (Bitfield-Mask: 0x01) */ +/* ========================================================== IEV ========================================================== */ +#define SN_GPIO1_IEV_IEV0_Pos (0UL) /*!< IEV0 (Bit 0) */ +#define SN_GPIO1_IEV_IEV0_Msk (0x1UL) /*!< IEV0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IEV_IEV1_Pos (1UL) /*!< IEV1 (Bit 1) */ +#define SN_GPIO1_IEV_IEV1_Msk (0x2UL) /*!< IEV1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IEV_IEV2_Pos (2UL) /*!< IEV2 (Bit 2) */ +#define SN_GPIO1_IEV_IEV2_Msk (0x4UL) /*!< IEV2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IEV_IEV3_Pos (3UL) /*!< IEV3 (Bit 3) */ +#define SN_GPIO1_IEV_IEV3_Msk (0x8UL) /*!< IEV3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IEV_IEV4_Pos (4UL) /*!< IEV4 (Bit 4) */ +#define SN_GPIO1_IEV_IEV4_Msk (0x10UL) /*!< IEV4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IEV_IEV5_Pos (5UL) /*!< IEV5 (Bit 5) */ +#define SN_GPIO1_IEV_IEV5_Msk (0x20UL) /*!< IEV5 (Bitfield-Mask: 0x01) */ +/* ========================================================== IE =========================================================== */ +#define SN_GPIO1_IE_IE0_Pos (0UL) /*!< IE0 (Bit 0) */ +#define SN_GPIO1_IE_IE0_Msk (0x1UL) /*!< IE0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IE_IE1_Pos (1UL) /*!< IE1 (Bit 1) */ +#define SN_GPIO1_IE_IE1_Msk (0x2UL) /*!< IE1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IE_IE2_Pos (2UL) /*!< IE2 (Bit 2) */ +#define SN_GPIO1_IE_IE2_Msk (0x4UL) /*!< IE2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IE_IE3_Pos (3UL) /*!< IE3 (Bit 3) */ +#define SN_GPIO1_IE_IE3_Msk (0x8UL) /*!< IE3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IE_IE4_Pos (4UL) /*!< IE4 (Bit 4) */ +#define SN_GPIO1_IE_IE4_Msk (0x10UL) /*!< IE4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IE_IE5_Pos (5UL) /*!< IE5 (Bit 5) */ +#define SN_GPIO1_IE_IE5_Msk (0x20UL) /*!< IE5 (Bitfield-Mask: 0x01) */ +/* ========================================================== RIS ========================================================== */ +#define SN_GPIO1_RIS_IF0_Pos (0UL) /*!< IF0 (Bit 0) */ +#define SN_GPIO1_RIS_IF0_Msk (0x1UL) /*!< IF0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_RIS_IF1_Pos (1UL) /*!< IF1 (Bit 1) */ +#define SN_GPIO1_RIS_IF1_Msk (0x2UL) /*!< IF1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_RIS_IF2_Pos (2UL) /*!< IF2 (Bit 2) */ +#define SN_GPIO1_RIS_IF2_Msk (0x4UL) /*!< IF2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_RIS_IF3_Pos (3UL) /*!< IF3 (Bit 3) */ +#define SN_GPIO1_RIS_IF3_Msk (0x8UL) /*!< IF3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_RIS_IF4_Pos (4UL) /*!< IF4 (Bit 4) */ +#define SN_GPIO1_RIS_IF4_Msk (0x10UL) /*!< IF4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_RIS_IF5_Pos (5UL) /*!< IF5 (Bit 5) */ +#define SN_GPIO1_RIS_IF5_Msk (0x20UL) /*!< IF5 (Bitfield-Mask: 0x01) */ +/* ========================================================== IC =========================================================== */ +#define SN_GPIO1_IC_IC0_Pos (0UL) /*!< IC0 (Bit 0) */ +#define SN_GPIO1_IC_IC0_Msk (0x1UL) /*!< IC0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IC_IC1_Pos (1UL) /*!< IC1 (Bit 1) */ +#define SN_GPIO1_IC_IC1_Msk (0x2UL) /*!< IC1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IC_IC2_Pos (2UL) /*!< IC2 (Bit 2) */ +#define SN_GPIO1_IC_IC2_Msk (0x4UL) /*!< IC2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IC_IC3_Pos (3UL) /*!< IC3 (Bit 3) */ +#define SN_GPIO1_IC_IC3_Msk (0x8UL) /*!< IC3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IC_IC4_Pos (4UL) /*!< IC4 (Bit 4) */ +#define SN_GPIO1_IC_IC4_Msk (0x10UL) /*!< IC4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_IC_IC5_Pos (5UL) /*!< IC5 (Bit 5) */ +#define SN_GPIO1_IC_IC5_Msk (0x20UL) /*!< IC5 (Bitfield-Mask: 0x01) */ +/* ========================================================= BSET ========================================================== */ +#define SN_GPIO1_BSET_BSET0_Pos (0UL) /*!< BSET0 (Bit 0) */ +#define SN_GPIO1_BSET_BSET0_Msk (0x1UL) /*!< BSET0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_BSET_BSET1_Pos (1UL) /*!< BSET1 (Bit 1) */ +#define SN_GPIO1_BSET_BSET1_Msk (0x2UL) /*!< BSET1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_BSET_BSET2_Pos (2UL) /*!< BSET2 (Bit 2) */ +#define SN_GPIO1_BSET_BSET2_Msk (0x4UL) /*!< BSET2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_BSET_BSET3_Pos (3UL) /*!< BSET3 (Bit 3) */ +#define SN_GPIO1_BSET_BSET3_Msk (0x8UL) /*!< BSET3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_BSET_BSET4_Pos (4UL) /*!< BSET4 (Bit 4) */ +#define SN_GPIO1_BSET_BSET4_Msk (0x10UL) /*!< BSET4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_BSET_BSET5_Pos (5UL) /*!< BSET5 (Bit 5) */ +#define SN_GPIO1_BSET_BSET5_Msk (0x20UL) /*!< BSET5 (Bitfield-Mask: 0x01) */ +/* ========================================================= BCLR ========================================================== */ +#define SN_GPIO1_BCLR_BCLR0_Pos (0UL) /*!< BCLR0 (Bit 0) */ +#define SN_GPIO1_BCLR_BCLR0_Msk (0x1UL) /*!< BCLR0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_BCLR_BCLR1_Pos (1UL) /*!< BCLR1 (Bit 1) */ +#define SN_GPIO1_BCLR_BCLR1_Msk (0x2UL) /*!< BCLR1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_BCLR_BCLR2_Pos (2UL) /*!< BCLR2 (Bit 2) */ +#define SN_GPIO1_BCLR_BCLR2_Msk (0x4UL) /*!< BCLR2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_BCLR_BCLR3_Pos (3UL) /*!< BCLR3 (Bit 3) */ +#define SN_GPIO1_BCLR_BCLR3_Msk (0x8UL) /*!< BCLR3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_BCLR_BCLR4_Pos (4UL) /*!< BCLR4 (Bit 4) */ +#define SN_GPIO1_BCLR_BCLR4_Msk (0x10UL) /*!< BCLR4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO1_BCLR_BCLR5_Pos (5UL) /*!< BCLR5 (Bit 5) */ +#define SN_GPIO1_BCLR_BCLR5_Msk (0x20UL) /*!< BCLR5 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DATA ========================================================== */ +#define SN_GPIO2_DATA_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ +#define SN_GPIO2_DATA_DATA0_Msk (0x1UL) /*!< DATA0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_DATA_DATA1_Pos (1UL) /*!< DATA1 (Bit 1) */ +#define SN_GPIO2_DATA_DATA1_Msk (0x2UL) /*!< DATA1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_DATA_DATA2_Pos (2UL) /*!< DATA2 (Bit 2) */ +#define SN_GPIO2_DATA_DATA2_Msk (0x4UL) /*!< DATA2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_DATA_DATA3_Pos (3UL) /*!< DATA3 (Bit 3) */ +#define SN_GPIO2_DATA_DATA3_Msk (0x8UL) /*!< DATA3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_DATA_DATA4_Pos (4UL) /*!< DATA4 (Bit 4) */ +#define SN_GPIO2_DATA_DATA4_Msk (0x10UL) /*!< DATA4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_DATA_DATA5_Pos (5UL) /*!< DATA5 (Bit 5) */ +#define SN_GPIO2_DATA_DATA5_Msk (0x20UL) /*!< DATA5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_DATA_DATA6_Pos (6UL) /*!< DATA6 (Bit 6) */ +#define SN_GPIO2_DATA_DATA6_Msk (0x40UL) /*!< DATA6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_DATA_DATA7_Pos (7UL) /*!< DATA7 (Bit 7) */ +#define SN_GPIO2_DATA_DATA7_Msk (0x80UL) /*!< DATA7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_DATA_DATA8_Pos (8UL) /*!< DATA8 (Bit 8) */ +#define SN_GPIO2_DATA_DATA8_Msk (0x100UL) /*!< DATA8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_DATA_DATA9_Pos (9UL) /*!< DATA9 (Bit 9) */ +#define SN_GPIO2_DATA_DATA9_Msk (0x200UL) /*!< DATA9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_DATA_DATA10_Pos (10UL) /*!< DATA10 (Bit 10) */ +#define SN_GPIO2_DATA_DATA10_Msk (0x400UL) /*!< DATA10 (Bitfield-Mask: 0x01) */ +/* ========================================================= MODE ========================================================== */ +#define SN_GPIO2_MODE_MODE0_Pos (0UL) /*!< MODE0 (Bit 0) */ +#define SN_GPIO2_MODE_MODE0_Msk (0x1UL) /*!< MODE0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_MODE_MODE1_Pos (1UL) /*!< MODE1 (Bit 1) */ +#define SN_GPIO2_MODE_MODE1_Msk (0x2UL) /*!< MODE1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_MODE_MODE2_Pos (2UL) /*!< MODE2 (Bit 2) */ +#define SN_GPIO2_MODE_MODE2_Msk (0x4UL) /*!< MODE2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_MODE_MODE3_Pos (3UL) /*!< MODE3 (Bit 3) */ +#define SN_GPIO2_MODE_MODE3_Msk (0x8UL) /*!< MODE3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_MODE_MODE4_Pos (4UL) /*!< MODE4 (Bit 4) */ +#define SN_GPIO2_MODE_MODE4_Msk (0x10UL) /*!< MODE4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_MODE_MODE5_Pos (5UL) /*!< MODE5 (Bit 5) */ +#define SN_GPIO2_MODE_MODE5_Msk (0x20UL) /*!< MODE5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_MODE_MODE6_Pos (6UL) /*!< MODE6 (Bit 6) */ +#define SN_GPIO2_MODE_MODE6_Msk (0x40UL) /*!< MODE6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_MODE_MODE7_Pos (7UL) /*!< MODE7 (Bit 7) */ +#define SN_GPIO2_MODE_MODE7_Msk (0x80UL) /*!< MODE7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_MODE_MODE8_Pos (8UL) /*!< MODE8 (Bit 8) */ +#define SN_GPIO2_MODE_MODE8_Msk (0x100UL) /*!< MODE8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_MODE_MODE9_Pos (9UL) /*!< MODE9 (Bit 9) */ +#define SN_GPIO2_MODE_MODE9_Msk (0x200UL) /*!< MODE9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_MODE_MODE10_Pos (10UL) /*!< MODE10 (Bit 10) */ +#define SN_GPIO2_MODE_MODE10_Msk (0x400UL) /*!< MODE10 (Bitfield-Mask: 0x01) */ +/* ========================================================== CFG ========================================================== */ +#define SN_GPIO2_CFG_CFG0_Pos (0UL) /*!< CFG0 (Bit 0) */ +#define SN_GPIO2_CFG_CFG0_Msk (0x3UL) /*!< CFG0 (Bitfield-Mask: 0x03) */ +#define SN_GPIO2_CFG_CFG1_Pos (2UL) /*!< CFG1 (Bit 2) */ +#define SN_GPIO2_CFG_CFG1_Msk (0xcUL) /*!< CFG1 (Bitfield-Mask: 0x03) */ +#define SN_GPIO2_CFG_CFG2_Pos (4UL) /*!< CFG2 (Bit 4) */ +#define SN_GPIO2_CFG_CFG2_Msk (0x30UL) /*!< CFG2 (Bitfield-Mask: 0x03) */ +#define SN_GPIO2_CFG_CFG3_Pos (6UL) /*!< CFG3 (Bit 6) */ +#define SN_GPIO2_CFG_CFG3_Msk (0xc0UL) /*!< CFG3 (Bitfield-Mask: 0x03) */ +#define SN_GPIO2_CFG_CFG4_Pos (8UL) /*!< CFG4 (Bit 8) */ +#define SN_GPIO2_CFG_CFG4_Msk (0x300UL) /*!< CFG4 (Bitfield-Mask: 0x03) */ +#define SN_GPIO2_CFG_CFG5_Pos (10UL) /*!< CFG5 (Bit 10) */ +#define SN_GPIO2_CFG_CFG5_Msk (0xc00UL) /*!< CFG5 (Bitfield-Mask: 0x03) */ +#define SN_GPIO2_CFG_CFG6_Pos (12UL) /*!< CFG6 (Bit 12) */ +#define SN_GPIO2_CFG_CFG6_Msk (0x3000UL) /*!< CFG6 (Bitfield-Mask: 0x03) */ +#define SN_GPIO2_CFG_CFG7_Pos (14UL) /*!< CFG7 (Bit 14) */ +#define SN_GPIO2_CFG_CFG7_Msk (0xc000UL) /*!< CFG7 (Bitfield-Mask: 0x03) */ +#define SN_GPIO2_CFG_CFG8_Pos (16UL) /*!< CFG8 (Bit 16) */ +#define SN_GPIO2_CFG_CFG8_Msk (0x30000UL) /*!< CFG8 (Bitfield-Mask: 0x03) */ +#define SN_GPIO2_CFG_CFG9_Pos (18UL) /*!< CFG9 (Bit 18) */ +#define SN_GPIO2_CFG_CFG9_Msk (0xc0000UL) /*!< CFG9 (Bitfield-Mask: 0x03) */ +#define SN_GPIO2_CFG_CFG10_Pos (20UL) /*!< CFG10 (Bit 20) */ +#define SN_GPIO2_CFG_CFG10_Msk (0x300000UL) /*!< CFG10 (Bitfield-Mask: 0x03) */ +/* ========================================================== IS =========================================================== */ +#define SN_GPIO2_IS_IS0_Pos (0UL) /*!< IS0 (Bit 0) */ +#define SN_GPIO2_IS_IS0_Msk (0x1UL) /*!< IS0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IS_IS1_Pos (1UL) /*!< IS1 (Bit 1) */ +#define SN_GPIO2_IS_IS1_Msk (0x2UL) /*!< IS1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IS_IS2_Pos (2UL) /*!< IS2 (Bit 2) */ +#define SN_GPIO2_IS_IS2_Msk (0x4UL) /*!< IS2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IS_IS3_Pos (3UL) /*!< IS3 (Bit 3) */ +#define SN_GPIO2_IS_IS3_Msk (0x8UL) /*!< IS3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IS_IS4_Pos (4UL) /*!< IS4 (Bit 4) */ +#define SN_GPIO2_IS_IS4_Msk (0x10UL) /*!< IS4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IS_IS5_Pos (5UL) /*!< IS5 (Bit 5) */ +#define SN_GPIO2_IS_IS5_Msk (0x20UL) /*!< IS5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IS_IS6_Pos (6UL) /*!< IS6 (Bit 6) */ +#define SN_GPIO2_IS_IS6_Msk (0x40UL) /*!< IS6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IS_IS7_Pos (7UL) /*!< IS7 (Bit 7) */ +#define SN_GPIO2_IS_IS7_Msk (0x80UL) /*!< IS7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IS_IS8_Pos (8UL) /*!< IS8 (Bit 8) */ +#define SN_GPIO2_IS_IS8_Msk (0x100UL) /*!< IS8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IS_IS9_Pos (9UL) /*!< IS9 (Bit 9) */ +#define SN_GPIO2_IS_IS9_Msk (0x200UL) /*!< IS9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IS_IS10_Pos (10UL) /*!< IS10 (Bit 10) */ +#define SN_GPIO2_IS_IS10_Msk (0x400UL) /*!< IS10 (Bitfield-Mask: 0x01) */ +/* ========================================================== IBS ========================================================== */ +#define SN_GPIO2_IBS_IBS0_Pos (0UL) /*!< IBS0 (Bit 0) */ +#define SN_GPIO2_IBS_IBS0_Msk (0x1UL) /*!< IBS0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IBS_IBS1_Pos (1UL) /*!< IBS1 (Bit 1) */ +#define SN_GPIO2_IBS_IBS1_Msk (0x2UL) /*!< IBS1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IBS_IBS2_Pos (2UL) /*!< IBS2 (Bit 2) */ +#define SN_GPIO2_IBS_IBS2_Msk (0x4UL) /*!< IBS2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IBS_IBS3_Pos (3UL) /*!< IBS3 (Bit 3) */ +#define SN_GPIO2_IBS_IBS3_Msk (0x8UL) /*!< IBS3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IBS_IBS4_Pos (4UL) /*!< IBS4 (Bit 4) */ +#define SN_GPIO2_IBS_IBS4_Msk (0x10UL) /*!< IBS4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IBS_IBS5_Pos (5UL) /*!< IBS5 (Bit 5) */ +#define SN_GPIO2_IBS_IBS5_Msk (0x20UL) /*!< IBS5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IBS_IBS6_Pos (6UL) /*!< IBS6 (Bit 6) */ +#define SN_GPIO2_IBS_IBS6_Msk (0x40UL) /*!< IBS6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IBS_IBS7_Pos (7UL) /*!< IBS7 (Bit 7) */ +#define SN_GPIO2_IBS_IBS7_Msk (0x80UL) /*!< IBS7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IBS_IBS8_Pos (8UL) /*!< IBS8 (Bit 8) */ +#define SN_GPIO2_IBS_IBS8_Msk (0x100UL) /*!< IBS8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IBS_IBS9_Pos (9UL) /*!< IBS9 (Bit 9) */ +#define SN_GPIO2_IBS_IBS9_Msk (0x200UL) /*!< IBS9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IBS_IBS10_Pos (10UL) /*!< IBS10 (Bit 10) */ +#define SN_GPIO2_IBS_IBS10_Msk (0x400UL) /*!< IBS10 (Bitfield-Mask: 0x01) */ +/* ========================================================== IEV ========================================================== */ +#define SN_GPIO2_IEV_IEV0_Pos (0UL) /*!< IEV0 (Bit 0) */ +#define SN_GPIO2_IEV_IEV0_Msk (0x1UL) /*!< IEV0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IEV_IEV1_Pos (1UL) /*!< IEV1 (Bit 1) */ +#define SN_GPIO2_IEV_IEV1_Msk (0x2UL) /*!< IEV1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IEV_IEV2_Pos (2UL) /*!< IEV2 (Bit 2) */ +#define SN_GPIO2_IEV_IEV2_Msk (0x4UL) /*!< IEV2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IEV_IEV3_Pos (3UL) /*!< IEV3 (Bit 3) */ +#define SN_GPIO2_IEV_IEV3_Msk (0x8UL) /*!< IEV3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IEV_IEV4_Pos (4UL) /*!< IEV4 (Bit 4) */ +#define SN_GPIO2_IEV_IEV4_Msk (0x10UL) /*!< IEV4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IEV_IEV5_Pos (5UL) /*!< IEV5 (Bit 5) */ +#define SN_GPIO2_IEV_IEV5_Msk (0x20UL) /*!< IEV5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IEV_IEV6_Pos (6UL) /*!< IEV6 (Bit 6) */ +#define SN_GPIO2_IEV_IEV6_Msk (0x40UL) /*!< IEV6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IEV_IEV7_Pos (7UL) /*!< IEV7 (Bit 7) */ +#define SN_GPIO2_IEV_IEV7_Msk (0x80UL) /*!< IEV7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IEV_IEV8_Pos (8UL) /*!< IEV8 (Bit 8) */ +#define SN_GPIO2_IEV_IEV8_Msk (0x100UL) /*!< IEV8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IEV_IEV9_Pos (9UL) /*!< IEV9 (Bit 9) */ +#define SN_GPIO2_IEV_IEV9_Msk (0x200UL) /*!< IEV9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IEV_IEV10_Pos (10UL) /*!< IEV10 (Bit 10) */ +#define SN_GPIO2_IEV_IEV10_Msk (0x400UL) /*!< IEV10 (Bitfield-Mask: 0x01) */ +/* ========================================================== IE =========================================================== */ +#define SN_GPIO2_IE_IE0_Pos (0UL) /*!< IE0 (Bit 0) */ +#define SN_GPIO2_IE_IE0_Msk (0x1UL) /*!< IE0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IE_IE1_Pos (1UL) /*!< IE1 (Bit 1) */ +#define SN_GPIO2_IE_IE1_Msk (0x2UL) /*!< IE1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IE_IE2_Pos (2UL) /*!< IE2 (Bit 2) */ +#define SN_GPIO2_IE_IE2_Msk (0x4UL) /*!< IE2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IE_IE3_Pos (3UL) /*!< IE3 (Bit 3) */ +#define SN_GPIO2_IE_IE3_Msk (0x8UL) /*!< IE3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IE_IE4_Pos (4UL) /*!< IE4 (Bit 4) */ +#define SN_GPIO2_IE_IE4_Msk (0x10UL) /*!< IE4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IE_IE5_Pos (5UL) /*!< IE5 (Bit 5) */ +#define SN_GPIO2_IE_IE5_Msk (0x20UL) /*!< IE5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IE_IE6_Pos (6UL) /*!< IE6 (Bit 6) */ +#define SN_GPIO2_IE_IE6_Msk (0x40UL) /*!< IE6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IE_IE7_Pos (7UL) /*!< IE7 (Bit 7) */ +#define SN_GPIO2_IE_IE7_Msk (0x80UL) /*!< IE7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IE_IE8_Pos (8UL) /*!< IE8 (Bit 8) */ +#define SN_GPIO2_IE_IE8_Msk (0x100UL) /*!< IE8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IE_IE9_Pos (9UL) /*!< IE9 (Bit 9) */ +#define SN_GPIO2_IE_IE9_Msk (0x200UL) /*!< IE9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IE_IE10_Pos (10UL) /*!< IE10 (Bit 10) */ +#define SN_GPIO2_IE_IE10_Msk (0x400UL) /*!< IE10 (Bitfield-Mask: 0x01) */ +/* ========================================================== RIS ========================================================== */ +#define SN_GPIO2_RIS_IF0_Pos (0UL) /*!< IF0 (Bit 0) */ +#define SN_GPIO2_RIS_IF0_Msk (0x1UL) /*!< IF0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_RIS_IF1_Pos (1UL) /*!< IF1 (Bit 1) */ +#define SN_GPIO2_RIS_IF1_Msk (0x2UL) /*!< IF1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_RIS_IF2_Pos (2UL) /*!< IF2 (Bit 2) */ +#define SN_GPIO2_RIS_IF2_Msk (0x4UL) /*!< IF2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_RIS_IF3_Pos (3UL) /*!< IF3 (Bit 3) */ +#define SN_GPIO2_RIS_IF3_Msk (0x8UL) /*!< IF3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_RIS_IF4_Pos (4UL) /*!< IF4 (Bit 4) */ +#define SN_GPIO2_RIS_IF4_Msk (0x10UL) /*!< IF4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_RIS_IF5_Pos (5UL) /*!< IF5 (Bit 5) */ +#define SN_GPIO2_RIS_IF5_Msk (0x20UL) /*!< IF5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_RIS_IF6_Pos (6UL) /*!< IF6 (Bit 6) */ +#define SN_GPIO2_RIS_IF6_Msk (0x40UL) /*!< IF6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_RIS_IF7_Pos (7UL) /*!< IF7 (Bit 7) */ +#define SN_GPIO2_RIS_IF7_Msk (0x80UL) /*!< IF7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_RIS_IF8_Pos (8UL) /*!< IF8 (Bit 8) */ +#define SN_GPIO2_RIS_IF8_Msk (0x100UL) /*!< IF8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_RIS_IF9_Pos (9UL) /*!< IF9 (Bit 9) */ +#define SN_GPIO2_RIS_IF9_Msk (0x200UL) /*!< IF9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_RIS_IF10_Pos (10UL) /*!< IF10 (Bit 10) */ +#define SN_GPIO2_RIS_IF10_Msk (0x400UL) /*!< IF10 (Bitfield-Mask: 0x01) */ +/* ========================================================== IC =========================================================== */ +#define SN_GPIO2_IC_IC0_Pos (0UL) /*!< IC0 (Bit 0) */ +#define SN_GPIO2_IC_IC0_Msk (0x1UL) /*!< IC0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IC_IC1_Pos (1UL) /*!< IC1 (Bit 1) */ +#define SN_GPIO2_IC_IC1_Msk (0x2UL) /*!< IC1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IC_IC2_Pos (2UL) /*!< IC2 (Bit 2) */ +#define SN_GPIO2_IC_IC2_Msk (0x4UL) /*!< IC2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IC_IC3_Pos (3UL) /*!< IC3 (Bit 3) */ +#define SN_GPIO2_IC_IC3_Msk (0x8UL) /*!< IC3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IC_IC4_Pos (4UL) /*!< IC4 (Bit 4) */ +#define SN_GPIO2_IC_IC4_Msk (0x10UL) /*!< IC4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IC_IC5_Pos (5UL) /*!< IC5 (Bit 5) */ +#define SN_GPIO2_IC_IC5_Msk (0x20UL) /*!< IC5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IC_IC6_Pos (6UL) /*!< IC6 (Bit 6) */ +#define SN_GPIO2_IC_IC6_Msk (0x40UL) /*!< IC6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IC_IC7_Pos (7UL) /*!< IC7 (Bit 7) */ +#define SN_GPIO2_IC_IC7_Msk (0x80UL) /*!< IC7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IC_IC8_Pos (8UL) /*!< IC8 (Bit 8) */ +#define SN_GPIO2_IC_IC8_Msk (0x100UL) /*!< IC8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IC_IC9_Pos (9UL) /*!< IC9 (Bit 9) */ +#define SN_GPIO2_IC_IC9_Msk (0x200UL) /*!< IC9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_IC_IC10_Pos (10UL) /*!< IC10 (Bit 10) */ +#define SN_GPIO2_IC_IC10_Msk (0x400UL) /*!< IC10 (Bitfield-Mask: 0x01) */ +/* ========================================================= BSET ========================================================== */ +#define SN_GPIO2_BSET_BSET0_Pos (0UL) /*!< BSET0 (Bit 0) */ +#define SN_GPIO2_BSET_BSET0_Msk (0x1UL) /*!< BSET0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BSET_BSET1_Pos (1UL) /*!< BSET1 (Bit 1) */ +#define SN_GPIO2_BSET_BSET1_Msk (0x2UL) /*!< BSET1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BSET_BSET2_Pos (2UL) /*!< BSET2 (Bit 2) */ +#define SN_GPIO2_BSET_BSET2_Msk (0x4UL) /*!< BSET2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BSET_BSET3_Pos (3UL) /*!< BSET3 (Bit 3) */ +#define SN_GPIO2_BSET_BSET3_Msk (0x8UL) /*!< BSET3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BSET_BSET4_Pos (4UL) /*!< BSET4 (Bit 4) */ +#define SN_GPIO2_BSET_BSET4_Msk (0x10UL) /*!< BSET4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BSET_BSET5_Pos (5UL) /*!< BSET5 (Bit 5) */ +#define SN_GPIO2_BSET_BSET5_Msk (0x20UL) /*!< BSET5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BSET_BSET6_Pos (6UL) /*!< BSET6 (Bit 6) */ +#define SN_GPIO2_BSET_BSET6_Msk (0x40UL) /*!< BSET6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BSET_BSET7_Pos (7UL) /*!< BSET7 (Bit 7) */ +#define SN_GPIO2_BSET_BSET7_Msk (0x80UL) /*!< BSET7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BSET_BSET8_Pos (8UL) /*!< BSET8 (Bit 8) */ +#define SN_GPIO2_BSET_BSET8_Msk (0x100UL) /*!< BSET8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BSET_BSET9_Pos (9UL) /*!< BSET9 (Bit 9) */ +#define SN_GPIO2_BSET_BSET9_Msk (0x200UL) /*!< BSET9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BSET_BSET10_Pos (10UL) /*!< BSET10 (Bit 10) */ +#define SN_GPIO2_BSET_BSET10_Msk (0x400UL) /*!< BSET10 (Bitfield-Mask: 0x01) */ +/* ========================================================= BCLR ========================================================== */ +#define SN_GPIO2_BCLR_BCLR0_Pos (0UL) /*!< BCLR0 (Bit 0) */ +#define SN_GPIO2_BCLR_BCLR0_Msk (0x1UL) /*!< BCLR0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BCLR_BCLR1_Pos (1UL) /*!< BCLR1 (Bit 1) */ +#define SN_GPIO2_BCLR_BCLR1_Msk (0x2UL) /*!< BCLR1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BCLR_BCLR2_Pos (2UL) /*!< BCLR2 (Bit 2) */ +#define SN_GPIO2_BCLR_BCLR2_Msk (0x4UL) /*!< BCLR2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BCLR_BCLR3_Pos (3UL) /*!< BCLR3 (Bit 3) */ +#define SN_GPIO2_BCLR_BCLR3_Msk (0x8UL) /*!< BCLR3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BCLR_BCLR4_Pos (4UL) /*!< BCLR4 (Bit 4) */ +#define SN_GPIO2_BCLR_BCLR4_Msk (0x10UL) /*!< BCLR4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BCLR_BCLR5_Pos (5UL) /*!< BCLR5 (Bit 5) */ +#define SN_GPIO2_BCLR_BCLR5_Msk (0x20UL) /*!< BCLR5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BCLR_BCLR6_Pos (6UL) /*!< BCLR6 (Bit 6) */ +#define SN_GPIO2_BCLR_BCLR6_Msk (0x40UL) /*!< BCLR6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BCLR_BCLR7_Pos (7UL) /*!< BCLR7 (Bit 7) */ +#define SN_GPIO2_BCLR_BCLR7_Msk (0x80UL) /*!< BCLR7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BCLR_BCLR8_Pos (8UL) /*!< BCLR8 (Bit 8) */ +#define SN_GPIO2_BCLR_BCLR8_Msk (0x100UL) /*!< BCLR8 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BCLR_BCLR9_Pos (9UL) /*!< BCLR9 (Bit 9) */ +#define SN_GPIO2_BCLR_BCLR9_Msk (0x200UL) /*!< BCLR9 (Bitfield-Mask: 0x01) */ +#define SN_GPIO2_BCLR_BCLR10_Pos (10UL) /*!< BCLR10 (Bit 10) */ +#define SN_GPIO2_BCLR_BCLR10_Msk (0x400UL) /*!< BCLR10 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO3 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DATA ========================================================== */ +#define SN_GPIO3_DATA_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */ +#define SN_GPIO3_DATA_DATA0_Msk (0x1UL) /*!< DATA0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_DATA_DATA1_Pos (1UL) /*!< DATA1 (Bit 1) */ +#define SN_GPIO3_DATA_DATA1_Msk (0x2UL) /*!< DATA1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_DATA_DATA2_Pos (2UL) /*!< DATA2 (Bit 2) */ +#define SN_GPIO3_DATA_DATA2_Msk (0x4UL) /*!< DATA2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_DATA_DATA3_Pos (3UL) /*!< DATA3 (Bit 3) */ +#define SN_GPIO3_DATA_DATA3_Msk (0x8UL) /*!< DATA3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_DATA_DATA4_Pos (4UL) /*!< DATA4 (Bit 4) */ +#define SN_GPIO3_DATA_DATA4_Msk (0x10UL) /*!< DATA4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_DATA_DATA5_Pos (5UL) /*!< DATA5 (Bit 5) */ +#define SN_GPIO3_DATA_DATA5_Msk (0x20UL) /*!< DATA5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_DATA_DATA6_Pos (6UL) /*!< DATA6 (Bit 6) */ +#define SN_GPIO3_DATA_DATA6_Msk (0x40UL) /*!< DATA6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_DATA_DATA7_Pos (7UL) /*!< DATA7 (Bit 7) */ +#define SN_GPIO3_DATA_DATA7_Msk (0x80UL) /*!< DATA7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_DATA_DATA8_Pos (8UL) /*!< DATA8 (Bit 8) */ +#define SN_GPIO3_DATA_DATA8_Msk (0x100UL) /*!< DATA8 (Bitfield-Mask: 0x01) */ +/* ========================================================= MODE ========================================================== */ +#define SN_GPIO3_MODE_MODE0_Pos (0UL) /*!< MODE0 (Bit 0) */ +#define SN_GPIO3_MODE_MODE0_Msk (0x1UL) /*!< MODE0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_MODE_MODE1_Pos (1UL) /*!< MODE1 (Bit 1) */ +#define SN_GPIO3_MODE_MODE1_Msk (0x2UL) /*!< MODE1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_MODE_MODE2_Pos (2UL) /*!< MODE2 (Bit 2) */ +#define SN_GPIO3_MODE_MODE2_Msk (0x4UL) /*!< MODE2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_MODE_MODE3_Pos (3UL) /*!< MODE3 (Bit 3) */ +#define SN_GPIO3_MODE_MODE3_Msk (0x8UL) /*!< MODE3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_MODE_MODE4_Pos (4UL) /*!< MODE4 (Bit 4) */ +#define SN_GPIO3_MODE_MODE4_Msk (0x10UL) /*!< MODE4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_MODE_MODE5_Pos (5UL) /*!< MODE5 (Bit 5) */ +#define SN_GPIO3_MODE_MODE5_Msk (0x20UL) /*!< MODE5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_MODE_MODE6_Pos (6UL) /*!< MODE6 (Bit 6) */ +#define SN_GPIO3_MODE_MODE6_Msk (0x40UL) /*!< MODE6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_MODE_MODE7_Pos (7UL) /*!< MODE7 (Bit 7) */ +#define SN_GPIO3_MODE_MODE7_Msk (0x80UL) /*!< MODE7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_MODE_MODE8_Pos (8UL) /*!< MODE8 (Bit 8) */ +#define SN_GPIO3_MODE_MODE8_Msk (0x100UL) /*!< MODE8 (Bitfield-Mask: 0x01) */ +/* ========================================================== CFG ========================================================== */ +#define SN_GPIO3_CFG_CFG0_Pos (0UL) /*!< CFG0 (Bit 0) */ +#define SN_GPIO3_CFG_CFG0_Msk (0x3UL) /*!< CFG0 (Bitfield-Mask: 0x03) */ +#define SN_GPIO3_CFG_CFG1_Pos (2UL) /*!< CFG1 (Bit 2) */ +#define SN_GPIO3_CFG_CFG1_Msk (0xcUL) /*!< CFG1 (Bitfield-Mask: 0x03) */ +#define SN_GPIO3_CFG_CFG2_Pos (4UL) /*!< CFG2 (Bit 4) */ +#define SN_GPIO3_CFG_CFG2_Msk (0x30UL) /*!< CFG2 (Bitfield-Mask: 0x03) */ +#define SN_GPIO3_CFG_CFG3_Pos (6UL) /*!< CFG3 (Bit 6) */ +#define SN_GPIO3_CFG_CFG3_Msk (0xc0UL) /*!< CFG3 (Bitfield-Mask: 0x03) */ +#define SN_GPIO3_CFG_CFG4_Pos (8UL) /*!< CFG4 (Bit 8) */ +#define SN_GPIO3_CFG_CFG4_Msk (0x300UL) /*!< CFG4 (Bitfield-Mask: 0x03) */ +#define SN_GPIO3_CFG_CFG5_Pos (10UL) /*!< CFG5 (Bit 10) */ +#define SN_GPIO3_CFG_CFG5_Msk (0xc00UL) /*!< CFG5 (Bitfield-Mask: 0x03) */ +#define SN_GPIO3_CFG_CFG6_Pos (12UL) /*!< CFG6 (Bit 12) */ +#define SN_GPIO3_CFG_CFG6_Msk (0x3000UL) /*!< CFG6 (Bitfield-Mask: 0x03) */ +#define SN_GPIO3_CFG_CFG7_Pos (14UL) /*!< CFG7 (Bit 14) */ +#define SN_GPIO3_CFG_CFG7_Msk (0xc000UL) /*!< CFG7 (Bitfield-Mask: 0x03) */ +#define SN_GPIO3_CFG_CFG8_Pos (16UL) /*!< CFG8 (Bit 16) */ +#define SN_GPIO3_CFG_CFG8_Msk (0x30000UL) /*!< CFG8 (Bitfield-Mask: 0x03) */ +/* ========================================================== IS =========================================================== */ +#define SN_GPIO3_IS_IS0_Pos (0UL) /*!< IS0 (Bit 0) */ +#define SN_GPIO3_IS_IS0_Msk (0x1UL) /*!< IS0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IS_IS1_Pos (1UL) /*!< IS1 (Bit 1) */ +#define SN_GPIO3_IS_IS1_Msk (0x2UL) /*!< IS1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IS_IS2_Pos (2UL) /*!< IS2 (Bit 2) */ +#define SN_GPIO3_IS_IS2_Msk (0x4UL) /*!< IS2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IS_IS3_Pos (3UL) /*!< IS3 (Bit 3) */ +#define SN_GPIO3_IS_IS3_Msk (0x8UL) /*!< IS3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IS_IS4_Pos (4UL) /*!< IS4 (Bit 4) */ +#define SN_GPIO3_IS_IS4_Msk (0x10UL) /*!< IS4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IS_IS5_Pos (5UL) /*!< IS5 (Bit 5) */ +#define SN_GPIO3_IS_IS5_Msk (0x20UL) /*!< IS5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IS_IS6_Pos (6UL) /*!< IS6 (Bit 6) */ +#define SN_GPIO3_IS_IS6_Msk (0x40UL) /*!< IS6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IS_IS7_Pos (7UL) /*!< IS7 (Bit 7) */ +#define SN_GPIO3_IS_IS7_Msk (0x80UL) /*!< IS7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IS_IS8_Pos (8UL) /*!< IS8 (Bit 8) */ +#define SN_GPIO3_IS_IS8_Msk (0x100UL) /*!< IS8 (Bitfield-Mask: 0x01) */ +/* ========================================================== IBS ========================================================== */ +#define SN_GPIO3_IBS_IBS0_Pos (0UL) /*!< IBS0 (Bit 0) */ +#define SN_GPIO3_IBS_IBS0_Msk (0x1UL) /*!< IBS0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IBS_IBS1_Pos (1UL) /*!< IBS1 (Bit 1) */ +#define SN_GPIO3_IBS_IBS1_Msk (0x2UL) /*!< IBS1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IBS_IBS2_Pos (2UL) /*!< IBS2 (Bit 2) */ +#define SN_GPIO3_IBS_IBS2_Msk (0x4UL) /*!< IBS2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IBS_IBS3_Pos (3UL) /*!< IBS3 (Bit 3) */ +#define SN_GPIO3_IBS_IBS3_Msk (0x8UL) /*!< IBS3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IBS_IBS4_Pos (4UL) /*!< IBS4 (Bit 4) */ +#define SN_GPIO3_IBS_IBS4_Msk (0x10UL) /*!< IBS4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IBS_IBS5_Pos (5UL) /*!< IBS5 (Bit 5) */ +#define SN_GPIO3_IBS_IBS5_Msk (0x20UL) /*!< IBS5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IBS_IBS6_Pos (6UL) /*!< IBS6 (Bit 6) */ +#define SN_GPIO3_IBS_IBS6_Msk (0x40UL) /*!< IBS6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IBS_IBS7_Pos (7UL) /*!< IBS7 (Bit 7) */ +#define SN_GPIO3_IBS_IBS7_Msk (0x80UL) /*!< IBS7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IBS_IBS8_Pos (8UL) /*!< IBS8 (Bit 8) */ +#define SN_GPIO3_IBS_IBS8_Msk (0x100UL) /*!< IBS8 (Bitfield-Mask: 0x01) */ +/* ========================================================== IEV ========================================================== */ +#define SN_GPIO3_IEV_IEV0_Pos (0UL) /*!< IEV0 (Bit 0) */ +#define SN_GPIO3_IEV_IEV0_Msk (0x1UL) /*!< IEV0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IEV_IEV1_Pos (1UL) /*!< IEV1 (Bit 1) */ +#define SN_GPIO3_IEV_IEV1_Msk (0x2UL) /*!< IEV1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IEV_IEV2_Pos (2UL) /*!< IEV2 (Bit 2) */ +#define SN_GPIO3_IEV_IEV2_Msk (0x4UL) /*!< IEV2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IEV_IEV3_Pos (3UL) /*!< IEV3 (Bit 3) */ +#define SN_GPIO3_IEV_IEV3_Msk (0x8UL) /*!< IEV3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IEV_IEV4_Pos (4UL) /*!< IEV4 (Bit 4) */ +#define SN_GPIO3_IEV_IEV4_Msk (0x10UL) /*!< IEV4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IEV_IEV5_Pos (5UL) /*!< IEV5 (Bit 5) */ +#define SN_GPIO3_IEV_IEV5_Msk (0x20UL) /*!< IEV5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IEV_IEV6_Pos (6UL) /*!< IEV6 (Bit 6) */ +#define SN_GPIO3_IEV_IEV6_Msk (0x40UL) /*!< IEV6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IEV_IEV7_Pos (7UL) /*!< IEV7 (Bit 7) */ +#define SN_GPIO3_IEV_IEV7_Msk (0x80UL) /*!< IEV7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IEV_IEV8_Pos (8UL) /*!< IEV8 (Bit 8) */ +#define SN_GPIO3_IEV_IEV8_Msk (0x100UL) /*!< IEV8 (Bitfield-Mask: 0x01) */ +/* ========================================================== IE =========================================================== */ +#define SN_GPIO3_IE_IE0_Pos (0UL) /*!< IE0 (Bit 0) */ +#define SN_GPIO3_IE_IE0_Msk (0x1UL) /*!< IE0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IE_IE1_Pos (1UL) /*!< IE1 (Bit 1) */ +#define SN_GPIO3_IE_IE1_Msk (0x2UL) /*!< IE1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IE_IE2_Pos (2UL) /*!< IE2 (Bit 2) */ +#define SN_GPIO3_IE_IE2_Msk (0x4UL) /*!< IE2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IE_IE3_Pos (3UL) /*!< IE3 (Bit 3) */ +#define SN_GPIO3_IE_IE3_Msk (0x8UL) /*!< IE3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IE_IE4_Pos (4UL) /*!< IE4 (Bit 4) */ +#define SN_GPIO3_IE_IE4_Msk (0x10UL) /*!< IE4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IE_IE5_Pos (5UL) /*!< IE5 (Bit 5) */ +#define SN_GPIO3_IE_IE5_Msk (0x20UL) /*!< IE5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IE_IE6_Pos (6UL) /*!< IE6 (Bit 6) */ +#define SN_GPIO3_IE_IE6_Msk (0x40UL) /*!< IE6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IE_IE7_Pos (7UL) /*!< IE7 (Bit 7) */ +#define SN_GPIO3_IE_IE7_Msk (0x80UL) /*!< IE7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IE_IE8_Pos (8UL) /*!< IE8 (Bit 8) */ +#define SN_GPIO3_IE_IE8_Msk (0x100UL) /*!< IE8 (Bitfield-Mask: 0x01) */ +/* ========================================================== RIS ========================================================== */ +#define SN_GPIO3_RIS_IF0_Pos (0UL) /*!< IF0 (Bit 0) */ +#define SN_GPIO3_RIS_IF0_Msk (0x1UL) /*!< IF0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_RIS_IF1_Pos (1UL) /*!< IF1 (Bit 1) */ +#define SN_GPIO3_RIS_IF1_Msk (0x2UL) /*!< IF1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_RIS_IF2_Pos (2UL) /*!< IF2 (Bit 2) */ +#define SN_GPIO3_RIS_IF2_Msk (0x4UL) /*!< IF2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_RIS_IF3_Pos (3UL) /*!< IF3 (Bit 3) */ +#define SN_GPIO3_RIS_IF3_Msk (0x8UL) /*!< IF3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_RIS_IF4_Pos (4UL) /*!< IF4 (Bit 4) */ +#define SN_GPIO3_RIS_IF4_Msk (0x10UL) /*!< IF4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_RIS_IF5_Pos (5UL) /*!< IF5 (Bit 5) */ +#define SN_GPIO3_RIS_IF5_Msk (0x20UL) /*!< IF5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_RIS_IF6_Pos (6UL) /*!< IF6 (Bit 6) */ +#define SN_GPIO3_RIS_IF6_Msk (0x40UL) /*!< IF6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_RIS_IF7_Pos (7UL) /*!< IF7 (Bit 7) */ +#define SN_GPIO3_RIS_IF7_Msk (0x80UL) /*!< IF7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_RIS_IF8_Pos (8UL) /*!< IF8 (Bit 8) */ +#define SN_GPIO3_RIS_IF8_Msk (0x100UL) /*!< IF8 (Bitfield-Mask: 0x01) */ +/* ========================================================== IC =========================================================== */ +#define SN_GPIO3_IC_IC0_Pos (0UL) /*!< IC0 (Bit 0) */ +#define SN_GPIO3_IC_IC0_Msk (0x1UL) /*!< IC0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IC_IC1_Pos (1UL) /*!< IC1 (Bit 1) */ +#define SN_GPIO3_IC_IC1_Msk (0x2UL) /*!< IC1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IC_IC2_Pos (2UL) /*!< IC2 (Bit 2) */ +#define SN_GPIO3_IC_IC2_Msk (0x4UL) /*!< IC2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IC_IC3_Pos (3UL) /*!< IC3 (Bit 3) */ +#define SN_GPIO3_IC_IC3_Msk (0x8UL) /*!< IC3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IC_IC4_Pos (4UL) /*!< IC4 (Bit 4) */ +#define SN_GPIO3_IC_IC4_Msk (0x10UL) /*!< IC4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IC_IC5_Pos (5UL) /*!< IC5 (Bit 5) */ +#define SN_GPIO3_IC_IC5_Msk (0x20UL) /*!< IC5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IC_IC6_Pos (6UL) /*!< IC6 (Bit 6) */ +#define SN_GPIO3_IC_IC6_Msk (0x40UL) /*!< IC6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IC_IC7_Pos (7UL) /*!< IC7 (Bit 7) */ +#define SN_GPIO3_IC_IC7_Msk (0x80UL) /*!< IC7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_IC_IC8_Pos (8UL) /*!< IC8 (Bit 8) */ +#define SN_GPIO3_IC_IC8_Msk (0x100UL) /*!< IC8 (Bitfield-Mask: 0x01) */ +/* ========================================================= BSET ========================================================== */ +#define SN_GPIO3_BSET_BSET0_Pos (0UL) /*!< BSET0 (Bit 0) */ +#define SN_GPIO3_BSET_BSET0_Msk (0x1UL) /*!< BSET0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_BSET_BSET1_Pos (1UL) /*!< BSET1 (Bit 1) */ +#define SN_GPIO3_BSET_BSET1_Msk (0x2UL) /*!< BSET1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_BSET_BSET2_Pos (2UL) /*!< BSET2 (Bit 2) */ +#define SN_GPIO3_BSET_BSET2_Msk (0x4UL) /*!< BSET2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_BSET_BSET3_Pos (3UL) /*!< BSET3 (Bit 3) */ +#define SN_GPIO3_BSET_BSET3_Msk (0x8UL) /*!< BSET3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_BSET_BSET4_Pos (4UL) /*!< BSET4 (Bit 4) */ +#define SN_GPIO3_BSET_BSET4_Msk (0x10UL) /*!< BSET4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_BSET_BSET5_Pos (5UL) /*!< BSET5 (Bit 5) */ +#define SN_GPIO3_BSET_BSET5_Msk (0x20UL) /*!< BSET5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_BSET_BSET6_Pos (6UL) /*!< BSET6 (Bit 6) */ +#define SN_GPIO3_BSET_BSET6_Msk (0x40UL) /*!< BSET6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_BSET_BSET7_Pos (7UL) /*!< BSET7 (Bit 7) */ +#define SN_GPIO3_BSET_BSET7_Msk (0x80UL) /*!< BSET7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_BSET_BSET8_Pos (8UL) /*!< BSET8 (Bit 8) */ +#define SN_GPIO3_BSET_BSET8_Msk (0x100UL) /*!< BSET8 (Bitfield-Mask: 0x01) */ +/* ========================================================= BCLR ========================================================== */ +#define SN_GPIO3_BCLR_BCLR0_Pos (0UL) /*!< BCLR0 (Bit 0) */ +#define SN_GPIO3_BCLR_BCLR0_Msk (0x1UL) /*!< BCLR0 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_BCLR_BCLR1_Pos (1UL) /*!< BCLR1 (Bit 1) */ +#define SN_GPIO3_BCLR_BCLR1_Msk (0x2UL) /*!< BCLR1 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_BCLR_BCLR2_Pos (2UL) /*!< BCLR2 (Bit 2) */ +#define SN_GPIO3_BCLR_BCLR2_Msk (0x4UL) /*!< BCLR2 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_BCLR_BCLR3_Pos (3UL) /*!< BCLR3 (Bit 3) */ +#define SN_GPIO3_BCLR_BCLR3_Msk (0x8UL) /*!< BCLR3 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_BCLR_BCLR4_Pos (4UL) /*!< BCLR4 (Bit 4) */ +#define SN_GPIO3_BCLR_BCLR4_Msk (0x10UL) /*!< BCLR4 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_BCLR_BCLR5_Pos (5UL) /*!< BCLR5 (Bit 5) */ +#define SN_GPIO3_BCLR_BCLR5_Msk (0x20UL) /*!< BCLR5 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_BCLR_BCLR6_Pos (6UL) /*!< BCLR6 (Bit 6) */ +#define SN_GPIO3_BCLR_BCLR6_Msk (0x40UL) /*!< BCLR6 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_BCLR_BCLR7_Pos (7UL) /*!< BCLR7 (Bit 7) */ +#define SN_GPIO3_BCLR_BCLR7_Msk (0x80UL) /*!< BCLR7 (Bitfield-Mask: 0x01) */ +#define SN_GPIO3_BCLR_BCLR8_Pos (8UL) /*!< BCLR8 (Bit 8) */ +#define SN_GPIO3_BCLR_BCLR8_Msk (0x100UL) /*!< BCLR8 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ SN_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CFG ========================================================== */ +#define SN_WDT_CFG_WDTEN_Pos (0UL) /*!< WDTEN (Bit 0) */ +#define SN_WDT_CFG_WDTEN_Msk (0x1UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ +#define SN_WDT_CFG_WDTIE_Pos (1UL) /*!< WDTIE (Bit 1) */ +#define SN_WDT_CFG_WDTIE_Msk (0x2UL) /*!< WDTIE (Bitfield-Mask: 0x01) */ +#define SN_WDT_CFG_WDTINT_Pos (2UL) /*!< WDTINT (Bit 2) */ +#define SN_WDT_CFG_WDTINT_Msk (0x4UL) /*!< WDTINT (Bitfield-Mask: 0x01) */ +#define SN_WDT_CFG_WDKEY_Pos (16UL) /*!< WDKEY (Bit 16) */ +#define SN_WDT_CFG_WDKEY_Msk (0xffff0000UL) /*!< WDKEY (Bitfield-Mask: 0xffff) */ +/* ======================================================= CLKSOURCE ======================================================= */ +#define SN_WDT_CLKSOURCE_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ +#define SN_WDT_CLKSOURCE_CLKSEL_Msk (0x3UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ +#define SN_WDT_CLKSOURCE_WDKEY_Pos (16UL) /*!< WDKEY (Bit 16) */ +#define SN_WDT_CLKSOURCE_WDKEY_Msk (0xffff0000UL) /*!< WDKEY (Bitfield-Mask: 0xffff) */ +/* ========================================================== TC =========================================================== */ +#define SN_WDT_TC_TC_Pos (0UL) /*!< TC (Bit 0) */ +#define SN_WDT_TC_TC_Msk (0xffUL) /*!< TC (Bitfield-Mask: 0xff) */ +#define SN_WDT_TC_WDKEY_Pos (16UL) /*!< WDKEY (Bit 16) */ +#define SN_WDT_TC_WDKEY_Msk (0xffff0000UL) /*!< WDKEY (Bitfield-Mask: 0xffff) */ +/* ========================================================= FEED ========================================================== */ +#define SN_WDT_FEED_FV_Pos (0UL) /*!< FV (Bit 0) */ +#define SN_WDT_FEED_FV_Msk (0xffffUL) /*!< FV (Bitfield-Mask: 0xffff) */ +#define SN_WDT_FEED_WDKEY_Pos (16UL) /*!< WDKEY (Bit 16) */ +#define SN_WDT_FEED_WDKEY_Msk (0xffff0000UL) /*!< WDKEY (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ SN_CT16B0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TMRCTRL ======================================================== */ +#define SN_CT16B0_TMRCTRL_CEN_Pos (0UL) /*!< CEN (Bit 0) */ +#define SN_CT16B0_TMRCTRL_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B0_TMRCTRL_CRST_Pos (1UL) /*!< CRST (Bit 1) */ +#define SN_CT16B0_TMRCTRL_CRST_Msk (0x2UL) /*!< CRST (Bitfield-Mask: 0x01) */ +/* ========================================================== TC =========================================================== */ +#define SN_CT16B0_TC_TC_Pos (0UL) /*!< TC (Bit 0) */ +#define SN_CT16B0_TC_TC_Msk (0xffffUL) /*!< TC (Bitfield-Mask: 0xffff) */ +/* ========================================================== PRE ========================================================== */ +#define SN_CT16B0_PRE_PRE_Pos (0UL) /*!< PRE (Bit 0) */ +#define SN_CT16B0_PRE_PRE_Msk (0xffUL) /*!< PRE (Bitfield-Mask: 0xff) */ +/* ========================================================== PC =========================================================== */ +#define SN_CT16B0_PC_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define SN_CT16B0_PC_PC_Msk (0xffUL) /*!< PC (Bitfield-Mask: 0xff) */ +/* ======================================================== CNTCTRL ======================================================== */ +#define SN_CT16B0_CNTCTRL_CTM_Pos (0UL) /*!< CTM (Bit 0) */ +#define SN_CT16B0_CNTCTRL_CTM_Msk (0x3UL) /*!< CTM (Bitfield-Mask: 0x03) */ +#define SN_CT16B0_CNTCTRL_CIS_Pos (2UL) /*!< CIS (Bit 2) */ +#define SN_CT16B0_CNTCTRL_CIS_Msk (0xcUL) /*!< CIS (Bitfield-Mask: 0x03) */ +/* ========================================================= MCTRL ========================================================= */ +#define SN_CT16B0_MCTRL_MR0IE_Pos (0UL) /*!< MR0IE (Bit 0) */ +#define SN_CT16B0_MCTRL_MR0IE_Msk (0x1UL) /*!< MR0IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B0_MCTRL_MR0RST_Pos (1UL) /*!< MR0RST (Bit 1) */ +#define SN_CT16B0_MCTRL_MR0RST_Msk (0x2UL) /*!< MR0RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B0_MCTRL_MR0STOP_Pos (2UL) /*!< MR0STOP (Bit 2) */ +#define SN_CT16B0_MCTRL_MR0STOP_Msk (0x4UL) /*!< MR0STOP (Bitfield-Mask: 0x01) */ +/* ========================================================== MR0 ========================================================== */ +/* ======================================================== CAPCTRL ======================================================== */ +#define SN_CT16B0_CAPCTRL_CAP0RE_Pos (0UL) /*!< CAP0RE (Bit 0) */ +#define SN_CT16B0_CAPCTRL_CAP0RE_Msk (0x1UL) /*!< CAP0RE (Bitfield-Mask: 0x01) */ +#define SN_CT16B0_CAPCTRL_CAP0FE_Pos (1UL) /*!< CAP0FE (Bit 1) */ +#define SN_CT16B0_CAPCTRL_CAP0FE_Msk (0x2UL) /*!< CAP0FE (Bitfield-Mask: 0x01) */ +#define SN_CT16B0_CAPCTRL_CAP0IE_Pos (2UL) /*!< CAP0IE (Bit 2) */ +#define SN_CT16B0_CAPCTRL_CAP0IE_Msk (0x4UL) /*!< CAP0IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B0_CAPCTRL_CAP0EN_Pos (3UL) /*!< CAP0EN (Bit 3) */ +#define SN_CT16B0_CAPCTRL_CAP0EN_Msk (0x8UL) /*!< CAP0EN (Bitfield-Mask: 0x01) */ +/* ========================================================= CAP0 ========================================================== */ +#define SN_CT16B0_CAP0_CAP0_Pos (0UL) /*!< CAP0 (Bit 0) */ +#define SN_CT16B0_CAP0_CAP0_Msk (0xffffUL) /*!< CAP0 (Bitfield-Mask: 0xffff) */ +/* ========================================================== RIS ========================================================== */ +#define SN_CT16B0_RIS_MR0IF_Pos (0UL) /*!< MR0IF (Bit 0) */ +#define SN_CT16B0_RIS_MR0IF_Msk (0x1UL) /*!< MR0IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B0_RIS_CAP0IF_Pos (24UL) /*!< CAP0IF (Bit 24) */ +#define SN_CT16B0_RIS_CAP0IF_Msk (0x1000000UL) /*!< CAP0IF (Bitfield-Mask: 0x01) */ +/* ========================================================== IC =========================================================== */ +#define SN_CT16B0_IC_MR0IC_Pos (0UL) /*!< MR0IC (Bit 0) */ +#define SN_CT16B0_IC_MR0IC_Msk (0x1UL) /*!< MR0IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B0_IC_CAP0IC_Pos (24UL) /*!< CAP0IC (Bit 24) */ +#define SN_CT16B0_IC_CAP0IC_Msk (0x1000000UL) /*!< CAP0IC (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ SN_CT16B1 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TMRCTRL ======================================================== */ +#define SN_CT16B1_TMRCTRL_CEN_Pos (0UL) /*!< CEN (Bit 0) */ +#define SN_CT16B1_TMRCTRL_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_TMRCTRL_CRST_Pos (1UL) /*!< CRST (Bit 1) */ +#define SN_CT16B1_TMRCTRL_CRST_Msk (0x2UL) /*!< CRST (Bitfield-Mask: 0x01) */ +/* ========================================================== TC =========================================================== */ +#define SN_CT16B1_TC_TC_Pos (0UL) /*!< TC (Bit 0) */ +#define SN_CT16B1_TC_TC_Msk (0xffffUL) /*!< TC (Bitfield-Mask: 0xffff) */ +/* ========================================================== PRE ========================================================== */ +#define SN_CT16B1_PRE_PRE_Pos (0UL) /*!< PRE (Bit 0) */ +#define SN_CT16B1_PRE_PRE_Msk (0xffUL) /*!< PRE (Bitfield-Mask: 0xff) */ +/* ========================================================== PC =========================================================== */ +#define SN_CT16B1_PC_PC_Pos (0UL) /*!< PC (Bit 0) */ +#define SN_CT16B1_PC_PC_Msk (0xffUL) /*!< PC (Bitfield-Mask: 0xff) */ +/* ========================================================= MCTRL ========================================================= */ +#define SN_CT16B1_MCTRL_MR0IE_Pos (0UL) /*!< MR0IE (Bit 0) */ +#define SN_CT16B1_MCTRL_MR0IE_Msk (0x1UL) /*!< MR0IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR0RST_Pos (1UL) /*!< MR0RST (Bit 1) */ +#define SN_CT16B1_MCTRL_MR0RST_Msk (0x2UL) /*!< MR0RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR0STOP_Pos (2UL) /*!< MR0STOP (Bit 2) */ +#define SN_CT16B1_MCTRL_MR0STOP_Msk (0x4UL) /*!< MR0STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR1IE_Pos (3UL) /*!< MR1IE (Bit 3) */ +#define SN_CT16B1_MCTRL_MR1IE_Msk (0x8UL) /*!< MR1IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR1RST_Pos (4UL) /*!< MR1RST (Bit 4) */ +#define SN_CT16B1_MCTRL_MR1RST_Msk (0x10UL) /*!< MR1RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR1STOP_Pos (5UL) /*!< MR1STOP (Bit 5) */ +#define SN_CT16B1_MCTRL_MR1STOP_Msk (0x20UL) /*!< MR1STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR2IE_Pos (6UL) /*!< MR2IE (Bit 6) */ +#define SN_CT16B1_MCTRL_MR2IE_Msk (0x40UL) /*!< MR2IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR2RST_Pos (7UL) /*!< MR2RST (Bit 7) */ +#define SN_CT16B1_MCTRL_MR2RST_Msk (0x80UL) /*!< MR2RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR2STOP_Pos (8UL) /*!< MR2STOP (Bit 8) */ +#define SN_CT16B1_MCTRL_MR2STOP_Msk (0x100UL) /*!< MR2STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR3IE_Pos (9UL) /*!< MR3IE (Bit 9) */ +#define SN_CT16B1_MCTRL_MR3IE_Msk (0x200UL) /*!< MR3IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR3RST_Pos (10UL) /*!< MR3RST (Bit 10) */ +#define SN_CT16B1_MCTRL_MR3RST_Msk (0x400UL) /*!< MR3RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR3STOP_Pos (11UL) /*!< MR3STOP (Bit 11) */ +#define SN_CT16B1_MCTRL_MR3STOP_Msk (0x800UL) /*!< MR3STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR4IE_Pos (12UL) /*!< MR4IE (Bit 12) */ +#define SN_CT16B1_MCTRL_MR4IE_Msk (0x1000UL) /*!< MR4IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR4RST_Pos (13UL) /*!< MR4RST (Bit 13) */ +#define SN_CT16B1_MCTRL_MR4RST_Msk (0x2000UL) /*!< MR4RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR4STOP_Pos (14UL) /*!< MR4STOP (Bit 14) */ +#define SN_CT16B1_MCTRL_MR4STOP_Msk (0x4000UL) /*!< MR4STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR5IE_Pos (15UL) /*!< MR5IE (Bit 15) */ +#define SN_CT16B1_MCTRL_MR5IE_Msk (0x8000UL) /*!< MR5IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR5RST_Pos (16UL) /*!< MR5RST (Bit 16) */ +#define SN_CT16B1_MCTRL_MR5RST_Msk (0x10000UL) /*!< MR5RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR5STOP_Pos (17UL) /*!< MR5STOP (Bit 17) */ +#define SN_CT16B1_MCTRL_MR5STOP_Msk (0x20000UL) /*!< MR5STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR6IE_Pos (18UL) /*!< MR6IE (Bit 18) */ +#define SN_CT16B1_MCTRL_MR6IE_Msk (0x40000UL) /*!< MR6IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR6RST_Pos (19UL) /*!< MR6RST (Bit 19) */ +#define SN_CT16B1_MCTRL_MR6RST_Msk (0x80000UL) /*!< MR6RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR6STOP_Pos (20UL) /*!< MR6STOP (Bit 20) */ +#define SN_CT16B1_MCTRL_MR6STOP_Msk (0x100000UL) /*!< MR6STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR7IE_Pos (21UL) /*!< MR7IE (Bit 21) */ +#define SN_CT16B1_MCTRL_MR7IE_Msk (0x200000UL) /*!< MR7IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR7RST_Pos (22UL) /*!< MR7RST (Bit 22) */ +#define SN_CT16B1_MCTRL_MR7RST_Msk (0x400000UL) /*!< MR7RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR7STOP_Pos (23UL) /*!< MR7STOP (Bit 23) */ +#define SN_CT16B1_MCTRL_MR7STOP_Msk (0x800000UL) /*!< MR7STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR8IE_Pos (24UL) /*!< MR8IE (Bit 24) */ +#define SN_CT16B1_MCTRL_MR8IE_Msk (0x1000000UL) /*!< MR8IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR8RST_Pos (25UL) /*!< MR8RST (Bit 25) */ +#define SN_CT16B1_MCTRL_MR8RST_Msk (0x2000000UL) /*!< MR8RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR8STOP_Pos (26UL) /*!< MR8STOP (Bit 26) */ +#define SN_CT16B1_MCTRL_MR8STOP_Msk (0x4000000UL) /*!< MR8STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR9IE_Pos (27UL) /*!< MR9IE (Bit 27) */ +#define SN_CT16B1_MCTRL_MR9IE_Msk (0x8000000UL) /*!< MR9IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR9RST_Pos (28UL) /*!< MR9RST (Bit 28) */ +#define SN_CT16B1_MCTRL_MR9RST_Msk (0x10000000UL) /*!< MR9RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL_MR9STOP_Pos (29UL) /*!< MR9STOP (Bit 29) */ +#define SN_CT16B1_MCTRL_MR9STOP_Msk (0x20000000UL) /*!< MR9STOP (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTRL2 ========================================================= */ +#define SN_CT16B1_MCTRL2_MR10IE_Pos (0UL) /*!< MR10IE (Bit 0) */ +#define SN_CT16B1_MCTRL2_MR10IE_Msk (0x1UL) /*!< MR10IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR10RST_Pos (1UL) /*!< MR10RST (Bit 1) */ +#define SN_CT16B1_MCTRL2_MR10RST_Msk (0x2UL) /*!< MR10RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR10STOP_Pos (2UL) /*!< MR10STOP (Bit 2) */ +#define SN_CT16B1_MCTRL2_MR10STOP_Msk (0x4UL) /*!< MR10STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR11IE_Pos (3UL) /*!< MR11IE (Bit 3) */ +#define SN_CT16B1_MCTRL2_MR11IE_Msk (0x8UL) /*!< MR11IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR11RST_Pos (4UL) /*!< MR11RST (Bit 4) */ +#define SN_CT16B1_MCTRL2_MR11RST_Msk (0x10UL) /*!< MR11RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR11STOP_Pos (5UL) /*!< MR11STOP (Bit 5) */ +#define SN_CT16B1_MCTRL2_MR11STOP_Msk (0x20UL) /*!< MR11STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR12IE_Pos (6UL) /*!< MR12IE (Bit 6) */ +#define SN_CT16B1_MCTRL2_MR12IE_Msk (0x40UL) /*!< MR12IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR12RST_Pos (7UL) /*!< MR12RST (Bit 7) */ +#define SN_CT16B1_MCTRL2_MR12RST_Msk (0x80UL) /*!< MR12RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR12STOP_Pos (8UL) /*!< MR12STOP (Bit 8) */ +#define SN_CT16B1_MCTRL2_MR12STOP_Msk (0x100UL) /*!< MR12STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR13IE_Pos (9UL) /*!< MR13IE (Bit 9) */ +#define SN_CT16B1_MCTRL2_MR13IE_Msk (0x200UL) /*!< MR13IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR13RST_Pos (10UL) /*!< MR13RST (Bit 10) */ +#define SN_CT16B1_MCTRL2_MR13RST_Msk (0x400UL) /*!< MR13RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR13STOP_Pos (11UL) /*!< MR13STOP (Bit 11) */ +#define SN_CT16B1_MCTRL2_MR13STOP_Msk (0x800UL) /*!< MR13STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR14IE_Pos (12UL) /*!< MR14IE (Bit 12) */ +#define SN_CT16B1_MCTRL2_MR14IE_Msk (0x1000UL) /*!< MR14IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR14RST_Pos (13UL) /*!< MR14RST (Bit 13) */ +#define SN_CT16B1_MCTRL2_MR14RST_Msk (0x2000UL) /*!< MR14RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR14STOP_Pos (14UL) /*!< MR14STOP (Bit 14) */ +#define SN_CT16B1_MCTRL2_MR14STOP_Msk (0x4000UL) /*!< MR14STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR15IE_Pos (15UL) /*!< MR15IE (Bit 15) */ +#define SN_CT16B1_MCTRL2_MR15IE_Msk (0x8000UL) /*!< MR15IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR15RST_Pos (16UL) /*!< MR15RST (Bit 16) */ +#define SN_CT16B1_MCTRL2_MR15RST_Msk (0x10000UL) /*!< MR15RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR15STOP_Pos (17UL) /*!< MR15STOP (Bit 17) */ +#define SN_CT16B1_MCTRL2_MR15STOP_Msk (0x20000UL) /*!< MR15STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR16IE_Pos (18UL) /*!< MR16IE (Bit 18) */ +#define SN_CT16B1_MCTRL2_MR16IE_Msk (0x40000UL) /*!< MR16IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR16RST_Pos (19UL) /*!< MR16RST (Bit 19) */ +#define SN_CT16B1_MCTRL2_MR16RST_Msk (0x80000UL) /*!< MR16RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR16STOP_Pos (20UL) /*!< MR16STOP (Bit 20) */ +#define SN_CT16B1_MCTRL2_MR16STOP_Msk (0x100000UL) /*!< MR16STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR17IE_Pos (21UL) /*!< MR17IE (Bit 21) */ +#define SN_CT16B1_MCTRL2_MR17IE_Msk (0x200000UL) /*!< MR17IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR17RST_Pos (22UL) /*!< MR17RST (Bit 22) */ +#define SN_CT16B1_MCTRL2_MR17RST_Msk (0x400000UL) /*!< MR17RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR17STOP_Pos (23UL) /*!< MR17STOP (Bit 23) */ +#define SN_CT16B1_MCTRL2_MR17STOP_Msk (0x800000UL) /*!< MR17STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR18IE_Pos (24UL) /*!< MR18IE (Bit 24) */ +#define SN_CT16B1_MCTRL2_MR18IE_Msk (0x1000000UL) /*!< MR18IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR18RST_Pos (25UL) /*!< MR18RST (Bit 25) */ +#define SN_CT16B1_MCTRL2_MR18RST_Msk (0x2000000UL) /*!< MR18RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR18STOP_Pos (26UL) /*!< MR18STOP (Bit 26) */ +#define SN_CT16B1_MCTRL2_MR18STOP_Msk (0x4000000UL) /*!< MR18STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR19IE_Pos (27UL) /*!< MR19IE (Bit 27) */ +#define SN_CT16B1_MCTRL2_MR19IE_Msk (0x8000000UL) /*!< MR19IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR19RST_Pos (28UL) /*!< MR19RST (Bit 28) */ +#define SN_CT16B1_MCTRL2_MR19RST_Msk (0x10000000UL) /*!< MR19RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL2_MR19STOP_Pos (29UL) /*!< MR19STOP (Bit 29) */ +#define SN_CT16B1_MCTRL2_MR19STOP_Msk (0x20000000UL) /*!< MR19STOP (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTRL3 ========================================================= */ +#define SN_CT16B1_MCTRL3_MR20IE_Pos (0UL) /*!< MR20IE (Bit 0) */ +#define SN_CT16B1_MCTRL3_MR20IE_Msk (0x1UL) /*!< MR20IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL3_MR20RST_Pos (1UL) /*!< MR20RST (Bit 1) */ +#define SN_CT16B1_MCTRL3_MR20RST_Msk (0x2UL) /*!< MR20RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL3_MR20STOP_Pos (2UL) /*!< MR20STOP (Bit 2) */ +#define SN_CT16B1_MCTRL3_MR20STOP_Msk (0x4UL) /*!< MR20STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL3_MR21IE_Pos (3UL) /*!< MR21IE (Bit 3) */ +#define SN_CT16B1_MCTRL3_MR21IE_Msk (0x8UL) /*!< MR21IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL3_MR21RST_Pos (4UL) /*!< MR21RST (Bit 4) */ +#define SN_CT16B1_MCTRL3_MR21RST_Msk (0x10UL) /*!< MR21RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL3_MR21STOP_Pos (5UL) /*!< MR21STOP (Bit 5) */ +#define SN_CT16B1_MCTRL3_MR21STOP_Msk (0x20UL) /*!< MR21STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL3_MR22IE_Pos (6UL) /*!< MR22IE (Bit 6) */ +#define SN_CT16B1_MCTRL3_MR22IE_Msk (0x40UL) /*!< MR22IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL3_MR22RST_Pos (7UL) /*!< MR22RST (Bit 7) */ +#define SN_CT16B1_MCTRL3_MR22RST_Msk (0x80UL) /*!< MR22RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL3_MR22STOP_Pos (8UL) /*!< MR22STOP (Bit 8) */ +#define SN_CT16B1_MCTRL3_MR22STOP_Msk (0x100UL) /*!< MR22STOP (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL3_MR23IE_Pos (9UL) /*!< MR23IE (Bit 9) */ +#define SN_CT16B1_MCTRL3_MR23IE_Msk (0x200UL) /*!< MR23IE (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL3_MR23RST_Pos (10UL) /*!< MR23RST (Bit 10) */ +#define SN_CT16B1_MCTRL3_MR23RST_Msk (0x400UL) /*!< MR23RST (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_MCTRL3_MR23STOP_Pos (11UL) /*!< MR23STOP (Bit 11) */ +#define SN_CT16B1_MCTRL3_MR23STOP_Msk (0x800UL) /*!< MR23STOP (Bitfield-Mask: 0x01) */ +/* ========================================================== MR0 ========================================================== */ +/* ========================================================== MR1 ========================================================== */ +/* ========================================================== MR2 ========================================================== */ +/* ========================================================== MR3 ========================================================== */ +/* ========================================================== MR4 ========================================================== */ +/* ========================================================== MR5 ========================================================== */ +/* ========================================================== MR6 ========================================================== */ +/* ========================================================== MR7 ========================================================== */ +/* ========================================================== MR8 ========================================================== */ +/* ========================================================== MR9 ========================================================== */ +/* ========================================================= MR10 ========================================================== */ +/* ========================================================= MR11 ========================================================== */ +/* ========================================================= MR12 ========================================================== */ +/* ========================================================= MR13 ========================================================== */ +/* ========================================================= MR14 ========================================================== */ +/* ========================================================= MR15 ========================================================== */ +/* ========================================================= MR16 ========================================================== */ +/* ========================================================= MR17 ========================================================== */ +/* ========================================================= MR18 ========================================================== */ +/* ========================================================= MR19 ========================================================== */ +/* ========================================================= MR20 ========================================================== */ +/* ========================================================= MR21 ========================================================== */ +/* ========================================================= MR22 ========================================================== */ +/* ========================================================= MR23 ========================================================== */ +/* ========================================================== EM =========================================================== */ +#define SN_CT16B1_EM_EM0_Pos (0UL) /*!< EM0 (Bit 0) */ +#define SN_CT16B1_EM_EM0_Msk (0x1UL) /*!< EM0 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM1_Pos (1UL) /*!< EM1 (Bit 1) */ +#define SN_CT16B1_EM_EM1_Msk (0x2UL) /*!< EM1 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM2_Pos (2UL) /*!< EM2 (Bit 2) */ +#define SN_CT16B1_EM_EM2_Msk (0x4UL) /*!< EM2 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM3_Pos (3UL) /*!< EM3 (Bit 3) */ +#define SN_CT16B1_EM_EM3_Msk (0x8UL) /*!< EM3 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM4_Pos (4UL) /*!< EM4 (Bit 4) */ +#define SN_CT16B1_EM_EM4_Msk (0x10UL) /*!< EM4 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM5_Pos (5UL) /*!< EM5 (Bit 5) */ +#define SN_CT16B1_EM_EM5_Msk (0x20UL) /*!< EM5 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM6_Pos (6UL) /*!< EM6 (Bit 6) */ +#define SN_CT16B1_EM_EM6_Msk (0x40UL) /*!< EM6 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM7_Pos (7UL) /*!< EM7 (Bit 7) */ +#define SN_CT16B1_EM_EM7_Msk (0x80UL) /*!< EM7 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM8_Pos (8UL) /*!< EM8 (Bit 8) */ +#define SN_CT16B1_EM_EM8_Msk (0x100UL) /*!< EM8 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM9_Pos (9UL) /*!< EM9 (Bit 9) */ +#define SN_CT16B1_EM_EM9_Msk (0x200UL) /*!< EM9 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM10_Pos (10UL) /*!< EM10 (Bit 10) */ +#define SN_CT16B1_EM_EM10_Msk (0x400UL) /*!< EM10 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM11_Pos (11UL) /*!< EM11 (Bit 11) */ +#define SN_CT16B1_EM_EM11_Msk (0x800UL) /*!< EM11 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM12_Pos (12UL) /*!< EM12 (Bit 12) */ +#define SN_CT16B1_EM_EM12_Msk (0x1000UL) /*!< EM12 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM13_Pos (13UL) /*!< EM13 (Bit 13) */ +#define SN_CT16B1_EM_EM13_Msk (0x2000UL) /*!< EM13 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM14_Pos (14UL) /*!< EM14 (Bit 14) */ +#define SN_CT16B1_EM_EM14_Msk (0x4000UL) /*!< EM14 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM15_Pos (15UL) /*!< EM15 (Bit 15) */ +#define SN_CT16B1_EM_EM15_Msk (0x8000UL) /*!< EM15 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM16_Pos (16UL) /*!< EM16 (Bit 16) */ +#define SN_CT16B1_EM_EM16_Msk (0x10000UL) /*!< EM16 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM17_Pos (17UL) /*!< EM17 (Bit 17) */ +#define SN_CT16B1_EM_EM17_Msk (0x20000UL) /*!< EM17 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM18_Pos (18UL) /*!< EM18 (Bit 18) */ +#define SN_CT16B1_EM_EM18_Msk (0x40000UL) /*!< EM18 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM19_Pos (19UL) /*!< EM19 (Bit 19) */ +#define SN_CT16B1_EM_EM19_Msk (0x80000UL) /*!< EM19 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM20_Pos (20UL) /*!< EM20 (Bit 20) */ +#define SN_CT16B1_EM_EM20_Msk (0x100000UL) /*!< EM20 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM21_Pos (21UL) /*!< EM21 (Bit 21) */ +#define SN_CT16B1_EM_EM21_Msk (0x200000UL) /*!< EM21 (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_EM_EM22_Pos (22UL) /*!< EM22 (Bit 22) */ +#define SN_CT16B1_EM_EM22_Msk (0x400000UL) /*!< EM22 (Bitfield-Mask: 0x01) */ +/* ========================================================== EMC ========================================================== */ +#define SN_CT16B1_EMC_EMC0_Pos (0UL) /*!< EMC0 (Bit 0) */ +#define SN_CT16B1_EMC_EMC0_Msk (0x3UL) /*!< EMC0 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC_EMC1_Pos (2UL) /*!< EMC1 (Bit 2) */ +#define SN_CT16B1_EMC_EMC1_Msk (0xcUL) /*!< EMC1 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC_EMC2_Pos (4UL) /*!< EMC2 (Bit 4) */ +#define SN_CT16B1_EMC_EMC2_Msk (0x30UL) /*!< EMC2 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC_EMC3_Pos (6UL) /*!< EMC3 (Bit 6) */ +#define SN_CT16B1_EMC_EMC3_Msk (0xc0UL) /*!< EMC3 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC_EMC4_Pos (8UL) /*!< EMC4 (Bit 8) */ +#define SN_CT16B1_EMC_EMC4_Msk (0x300UL) /*!< EMC4 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC_EMC5_Pos (10UL) /*!< EMC5 (Bit 10) */ +#define SN_CT16B1_EMC_EMC5_Msk (0xc00UL) /*!< EMC5 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC_EMC6_Pos (12UL) /*!< EMC6 (Bit 12) */ +#define SN_CT16B1_EMC_EMC6_Msk (0x3000UL) /*!< EMC6 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC_EMC7_Pos (14UL) /*!< EMC7 (Bit 14) */ +#define SN_CT16B1_EMC_EMC7_Msk (0xc000UL) /*!< EMC7 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC_EMC8_Pos (16UL) /*!< EMC8 (Bit 16) */ +#define SN_CT16B1_EMC_EMC8_Msk (0x30000UL) /*!< EMC8 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC_EMC9_Pos (18UL) /*!< EMC9 (Bit 18) */ +#define SN_CT16B1_EMC_EMC9_Msk (0xc0000UL) /*!< EMC9 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC_EMC10_Pos (20UL) /*!< EMC10 (Bit 20) */ +#define SN_CT16B1_EMC_EMC10_Msk (0x300000UL) /*!< EMC10 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC_EMC11_Pos (22UL) /*!< EMC11 (Bit 22) */ +#define SN_CT16B1_EMC_EMC11_Msk (0xc00000UL) /*!< EMC11 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC_EMC12_Pos (24UL) /*!< EMC12 (Bit 24) */ +#define SN_CT16B1_EMC_EMC12_Msk (0x3000000UL) /*!< EMC12 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC_EMC13_Pos (26UL) /*!< EMC13 (Bit 26) */ +#define SN_CT16B1_EMC_EMC13_Msk (0xc000000UL) /*!< EMC13 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC_EMC14_Pos (28UL) /*!< EMC14 (Bit 28) */ +#define SN_CT16B1_EMC_EMC14_Msk (0x30000000UL) /*!< EMC14 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC_EMC15_Pos (30UL) /*!< EMC15 (Bit 30) */ +#define SN_CT16B1_EMC_EMC15_Msk (0xc0000000UL) /*!< EMC15 (Bitfield-Mask: 0x03) */ +/* ========================================================= EMC2 ========================================================== */ +#define SN_CT16B1_EMC2_EMC16_Pos (0UL) /*!< EMC16 (Bit 0) */ +#define SN_CT16B1_EMC2_EMC16_Msk (0x3UL) /*!< EMC16 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC2_EMC17_Pos (2UL) /*!< EMC17 (Bit 2) */ +#define SN_CT16B1_EMC2_EMC17_Msk (0xcUL) /*!< EMC17 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC2_EMC18_Pos (4UL) /*!< EMC18 (Bit 4) */ +#define SN_CT16B1_EMC2_EMC18_Msk (0x30UL) /*!< EMC18 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC2_EMC19_Pos (6UL) /*!< EMC19 (Bit 6) */ +#define SN_CT16B1_EMC2_EMC19_Msk (0xc0UL) /*!< EMC19 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC2_EMC20_Pos (8UL) /*!< EMC20 (Bit 8) */ +#define SN_CT16B1_EMC2_EMC20_Msk (0x300UL) /*!< EMC20 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC2_EMC21_Pos (10UL) /*!< EMC21 (Bit 10) */ +#define SN_CT16B1_EMC2_EMC21_Msk (0xc00UL) /*!< EMC21 (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_EMC2_EMC22_Pos (12UL) /*!< EMC22 (Bit 12) */ +#define SN_CT16B1_EMC2_EMC22_Msk (0x3000UL) /*!< EMC22 (Bitfield-Mask: 0x03) */ +/* ======================================================== PWMCTRL ======================================================== */ +#define SN_CT16B1_PWMCTRL_PWM0MODE_Pos (0UL) /*!< PWM0MODE (Bit 0) */ +#define SN_CT16B1_PWMCTRL_PWM0MODE_Msk (0x3UL) /*!< PWM0MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL_PWM1MODE_Pos (2UL) /*!< PWM1MODE (Bit 2) */ +#define SN_CT16B1_PWMCTRL_PWM1MODE_Msk (0xcUL) /*!< PWM1MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL_PWM2MODE_Pos (4UL) /*!< PWM2MODE (Bit 4) */ +#define SN_CT16B1_PWMCTRL_PWM2MODE_Msk (0x30UL) /*!< PWM2MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL_PWM3MODE_Pos (6UL) /*!< PWM3MODE (Bit 6) */ +#define SN_CT16B1_PWMCTRL_PWM3MODE_Msk (0xc0UL) /*!< PWM3MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL_PWM4MODE_Pos (8UL) /*!< PWM4MODE (Bit 8) */ +#define SN_CT16B1_PWMCTRL_PWM4MODE_Msk (0x300UL) /*!< PWM4MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL_PWM5MODE_Pos (10UL) /*!< PWM5MODE (Bit 10) */ +#define SN_CT16B1_PWMCTRL_PWM5MODE_Msk (0xc00UL) /*!< PWM5MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL_PWM6MODE_Pos (12UL) /*!< PWM6MODE (Bit 12) */ +#define SN_CT16B1_PWMCTRL_PWM6MODE_Msk (0x3000UL) /*!< PWM6MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL_PWM7MODE_Pos (14UL) /*!< PWM7MODE (Bit 14) */ +#define SN_CT16B1_PWMCTRL_PWM7MODE_Msk (0xc000UL) /*!< PWM7MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL_PWM8MODE_Pos (16UL) /*!< PWM8MODE (Bit 16) */ +#define SN_CT16B1_PWMCTRL_PWM8MODE_Msk (0x30000UL) /*!< PWM8MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL_PWM9MODE_Pos (18UL) /*!< PWM9MODE (Bit 18) */ +#define SN_CT16B1_PWMCTRL_PWM9MODE_Msk (0xc0000UL) /*!< PWM9MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL_PWM10MODE_Pos (20UL) /*!< PWM10MODE (Bit 20) */ +#define SN_CT16B1_PWMCTRL_PWM10MODE_Msk (0x300000UL) /*!< PWM10MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL_PWM11MODE_Pos (22UL) /*!< PWM11MODE (Bit 22) */ +#define SN_CT16B1_PWMCTRL_PWM11MODE_Msk (0xc00000UL) /*!< PWM11MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL_PWM12MODE_Pos (24UL) /*!< PWM12MODE (Bit 24) */ +#define SN_CT16B1_PWMCTRL_PWM12MODE_Msk (0x3000000UL) /*!< PWM12MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL_PWM13MODE_Pos (26UL) /*!< PWM13MODE (Bit 26) */ +#define SN_CT16B1_PWMCTRL_PWM13MODE_Msk (0xc000000UL) /*!< PWM13MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL_PWM14MODE_Pos (28UL) /*!< PWM14MODE (Bit 28) */ +#define SN_CT16B1_PWMCTRL_PWM14MODE_Msk (0x30000000UL) /*!< PWM14MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL_PWM15MODE_Pos (30UL) /*!< PWM15MODE (Bit 30) */ +#define SN_CT16B1_PWMCTRL_PWM15MODE_Msk (0xc0000000UL) /*!< PWM15MODE (Bitfield-Mask: 0x03) */ +/* ======================================================= PWMCTRL2 ======================================================== */ +#define SN_CT16B1_PWMCTRL2_PWM16MODE_Pos (0UL) /*!< PWM16MODE (Bit 0) */ +#define SN_CT16B1_PWMCTRL2_PWM16MODE_Msk (0x3UL) /*!< PWM16MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL2_PWM17MODE_Pos (2UL) /*!< PWM17MODE (Bit 2) */ +#define SN_CT16B1_PWMCTRL2_PWM17MODE_Msk (0xcUL) /*!< PWM17MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL2_PWM18MODE_Pos (4UL) /*!< PWM18MODE (Bit 4) */ +#define SN_CT16B1_PWMCTRL2_PWM18MODE_Msk (0x30UL) /*!< PWM18MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL2_PWM19MODE_Pos (6UL) /*!< PWM19MODE (Bit 6) */ +#define SN_CT16B1_PWMCTRL2_PWM19MODE_Msk (0xc0UL) /*!< PWM19MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL2_PWM20MODE_Pos (8UL) /*!< PWM20MODE (Bit 8) */ +#define SN_CT16B1_PWMCTRL2_PWM20MODE_Msk (0x300UL) /*!< PWM20MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL2_PWM21MODE_Pos (10UL) /*!< PWM21MODE (Bit 10) */ +#define SN_CT16B1_PWMCTRL2_PWM21MODE_Msk (0xc00UL) /*!< PWM21MODE (Bitfield-Mask: 0x03) */ +#define SN_CT16B1_PWMCTRL2_PWM22MODE_Pos (12UL) /*!< PWM22MODE (Bit 12) */ +#define SN_CT16B1_PWMCTRL2_PWM22MODE_Msk (0x3000UL) /*!< PWM22MODE (Bitfield-Mask: 0x03) */ +/* ======================================================== PWMENB ========================================================= */ +#define SN_CT16B1_PWMENB_PWM0EN_Pos (0UL) /*!< PWM0EN (Bit 0) */ +#define SN_CT16B1_PWMENB_PWM0EN_Msk (0x1UL) /*!< PWM0EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM1EN_Pos (1UL) /*!< PWM1EN (Bit 1) */ +#define SN_CT16B1_PWMENB_PWM1EN_Msk (0x2UL) /*!< PWM1EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM2EN_Pos (2UL) /*!< PWM2EN (Bit 2) */ +#define SN_CT16B1_PWMENB_PWM2EN_Msk (0x4UL) /*!< PWM2EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM3EN_Pos (3UL) /*!< PWM3EN (Bit 3) */ +#define SN_CT16B1_PWMENB_PWM3EN_Msk (0x8UL) /*!< PWM3EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM4EN_Pos (4UL) /*!< PWM4EN (Bit 4) */ +#define SN_CT16B1_PWMENB_PWM4EN_Msk (0x10UL) /*!< PWM4EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM5EN_Pos (5UL) /*!< PWM5EN (Bit 5) */ +#define SN_CT16B1_PWMENB_PWM5EN_Msk (0x20UL) /*!< PWM5EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM6EN_Pos (6UL) /*!< PWM6EN (Bit 6) */ +#define SN_CT16B1_PWMENB_PWM6EN_Msk (0x40UL) /*!< PWM6EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM7EN_Pos (7UL) /*!< PWM7EN (Bit 7) */ +#define SN_CT16B1_PWMENB_PWM7EN_Msk (0x80UL) /*!< PWM7EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM8EN_Pos (8UL) /*!< PWM8EN (Bit 8) */ +#define SN_CT16B1_PWMENB_PWM8EN_Msk (0x100UL) /*!< PWM8EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM9EN_Pos (9UL) /*!< PWM9EN (Bit 9) */ +#define SN_CT16B1_PWMENB_PWM9EN_Msk (0x200UL) /*!< PWM9EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM10EN_Pos (10UL) /*!< PWM10EN (Bit 10) */ +#define SN_CT16B1_PWMENB_PWM10EN_Msk (0x400UL) /*!< PWM10EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM11EN_Pos (11UL) /*!< PWM11EN (Bit 11) */ +#define SN_CT16B1_PWMENB_PWM11EN_Msk (0x800UL) /*!< PWM11EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM12EN_Pos (12UL) /*!< PWM12EN (Bit 12) */ +#define SN_CT16B1_PWMENB_PWM12EN_Msk (0x1000UL) /*!< PWM12EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM13EN_Pos (13UL) /*!< PWM13EN (Bit 13) */ +#define SN_CT16B1_PWMENB_PWM13EN_Msk (0x2000UL) /*!< PWM13EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM14EN_Pos (14UL) /*!< PWM14EN (Bit 14) */ +#define SN_CT16B1_PWMENB_PWM14EN_Msk (0x4000UL) /*!< PWM14EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM15EN_Pos (15UL) /*!< PWM15EN (Bit 15) */ +#define SN_CT16B1_PWMENB_PWM15EN_Msk (0x8000UL) /*!< PWM15EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM16EN_Pos (16UL) /*!< PWM16EN (Bit 16) */ +#define SN_CT16B1_PWMENB_PWM16EN_Msk (0x10000UL) /*!< PWM16EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM17EN_Pos (17UL) /*!< PWM17EN (Bit 17) */ +#define SN_CT16B1_PWMENB_PWM17EN_Msk (0x20000UL) /*!< PWM17EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM18EN_Pos (18UL) /*!< PWM18EN (Bit 18) */ +#define SN_CT16B1_PWMENB_PWM18EN_Msk (0x40000UL) /*!< PWM18EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM19EN_Pos (19UL) /*!< PWM19EN (Bit 19) */ +#define SN_CT16B1_PWMENB_PWM19EN_Msk (0x80000UL) /*!< PWM19EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM20EN_Pos (20UL) /*!< PWM20EN (Bit 20) */ +#define SN_CT16B1_PWMENB_PWM20EN_Msk (0x100000UL) /*!< PWM20EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM21EN_Pos (21UL) /*!< PWM21EN (Bit 21) */ +#define SN_CT16B1_PWMENB_PWM21EN_Msk (0x200000UL) /*!< PWM21EN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMENB_PWM22EN_Pos (22UL) /*!< PWM22EN (Bit 22) */ +#define SN_CT16B1_PWMENB_PWM22EN_Msk (0x400000UL) /*!< PWM22EN (Bitfield-Mask: 0x01) */ +/* ======================================================= PWMIOENB ======================================================== */ +#define SN_CT16B1_PWMIOENB_PWM0IOEN_Pos (0UL) /*!< PWM0IOEN (Bit 0) */ +#define SN_CT16B1_PWMIOENB_PWM0IOEN_Msk (0x1UL) /*!< PWM0IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM1IOEN_Pos (1UL) /*!< PWM1IOEN (Bit 1) */ +#define SN_CT16B1_PWMIOENB_PWM1IOEN_Msk (0x2UL) /*!< PWM1IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM2IOEN_Pos (2UL) /*!< PWM2IOEN (Bit 2) */ +#define SN_CT16B1_PWMIOENB_PWM2IOEN_Msk (0x4UL) /*!< PWM2IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM3IOEN_Pos (3UL) /*!< PWM3IOEN (Bit 3) */ +#define SN_CT16B1_PWMIOENB_PWM3IOEN_Msk (0x8UL) /*!< PWM3IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM4IOEN_Pos (4UL) /*!< PWM4IOEN (Bit 4) */ +#define SN_CT16B1_PWMIOENB_PWM4IOEN_Msk (0x10UL) /*!< PWM4IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM5IOEN_Pos (5UL) /*!< PWM5IOEN (Bit 5) */ +#define SN_CT16B1_PWMIOENB_PWM5IOEN_Msk (0x20UL) /*!< PWM5IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM6IOEN_Pos (6UL) /*!< PWM6IOEN (Bit 6) */ +#define SN_CT16B1_PWMIOENB_PWM6IOEN_Msk (0x40UL) /*!< PWM6IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM7IOEN_Pos (7UL) /*!< PWM7IOEN (Bit 7) */ +#define SN_CT16B1_PWMIOENB_PWM7IOEN_Msk (0x80UL) /*!< PWM7IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM8IOEN_Pos (8UL) /*!< PWM8IOEN (Bit 8) */ +#define SN_CT16B1_PWMIOENB_PWM8IOEN_Msk (0x100UL) /*!< PWM8IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM9IOEN_Pos (9UL) /*!< PWM9IOEN (Bit 9) */ +#define SN_CT16B1_PWMIOENB_PWM9IOEN_Msk (0x200UL) /*!< PWM9IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM10IOEN_Pos (10UL) /*!< PWM10IOEN (Bit 10) */ +#define SN_CT16B1_PWMIOENB_PWM10IOEN_Msk (0x400UL) /*!< PWM10IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM11IOEN_Pos (11UL) /*!< PWM11IOEN (Bit 11) */ +#define SN_CT16B1_PWMIOENB_PWM11IOEN_Msk (0x800UL) /*!< PWM11IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM12IOEN_Pos (12UL) /*!< PWM12IOEN (Bit 12) */ +#define SN_CT16B1_PWMIOENB_PWM12IOEN_Msk (0x1000UL) /*!< PWM12IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM13IOEN_Pos (13UL) /*!< PWM13IOEN (Bit 13) */ +#define SN_CT16B1_PWMIOENB_PWM13IOEN_Msk (0x2000UL) /*!< PWM13IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM14IOEN_Pos (14UL) /*!< PWM14IOEN (Bit 14) */ +#define SN_CT16B1_PWMIOENB_PWM14IOEN_Msk (0x4000UL) /*!< PWM14IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM15IOEN_Pos (15UL) /*!< PWM15IOEN (Bit 15) */ +#define SN_CT16B1_PWMIOENB_PWM15IOEN_Msk (0x8000UL) /*!< PWM15IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM16IOEN_Pos (16UL) /*!< PWM16IOEN (Bit 16) */ +#define SN_CT16B1_PWMIOENB_PWM16IOEN_Msk (0x10000UL) /*!< PWM16IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM17IOEN_Pos (17UL) /*!< PWM17IOEN (Bit 17) */ +#define SN_CT16B1_PWMIOENB_PWM17IOEN_Msk (0x20000UL) /*!< PWM17IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM18IOEN_Pos (18UL) /*!< PWM18IOEN (Bit 18) */ +#define SN_CT16B1_PWMIOENB_PWM18IOEN_Msk (0x40000UL) /*!< PWM18IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM19IOEN_Pos (19UL) /*!< PWM19IOEN (Bit 19) */ +#define SN_CT16B1_PWMIOENB_PWM19IOEN_Msk (0x80000UL) /*!< PWM19IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM20IOEN_Pos (20UL) /*!< PWM20IOEN (Bit 20) */ +#define SN_CT16B1_PWMIOENB_PWM20IOEN_Msk (0x100000UL) /*!< PWM20IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM21IOEN_Pos (21UL) /*!< PWM21IOEN (Bit 21) */ +#define SN_CT16B1_PWMIOENB_PWM21IOEN_Msk (0x200000UL) /*!< PWM21IOEN (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_PWMIOENB_PWM22IOEN_Pos (22UL) /*!< PWM22IOEN (Bit 22) */ +#define SN_CT16B1_PWMIOENB_PWM22IOEN_Msk (0x400000UL) /*!< PWM22IOEN (Bitfield-Mask: 0x01) */ +/* ========================================================== RIS ========================================================== */ +#define SN_CT16B1_RIS_MR0IF_Pos (0UL) /*!< MR0IF (Bit 0) */ +#define SN_CT16B1_RIS_MR0IF_Msk (0x1UL) /*!< MR0IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR1IF_Pos (1UL) /*!< MR1IF (Bit 1) */ +#define SN_CT16B1_RIS_MR1IF_Msk (0x2UL) /*!< MR1IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR2IF_Pos (2UL) /*!< MR2IF (Bit 2) */ +#define SN_CT16B1_RIS_MR2IF_Msk (0x4UL) /*!< MR2IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR3IF_Pos (3UL) /*!< MR3IF (Bit 3) */ +#define SN_CT16B1_RIS_MR3IF_Msk (0x8UL) /*!< MR3IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR4IF_Pos (4UL) /*!< MR4IF (Bit 4) */ +#define SN_CT16B1_RIS_MR4IF_Msk (0x10UL) /*!< MR4IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR5IF_Pos (5UL) /*!< MR5IF (Bit 5) */ +#define SN_CT16B1_RIS_MR5IF_Msk (0x20UL) /*!< MR5IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR6IF_Pos (6UL) /*!< MR6IF (Bit 6) */ +#define SN_CT16B1_RIS_MR6IF_Msk (0x40UL) /*!< MR6IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR7IF_Pos (7UL) /*!< MR7IF (Bit 7) */ +#define SN_CT16B1_RIS_MR7IF_Msk (0x80UL) /*!< MR7IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR8IF_Pos (8UL) /*!< MR8IF (Bit 8) */ +#define SN_CT16B1_RIS_MR8IF_Msk (0x100UL) /*!< MR8IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR9IF_Pos (9UL) /*!< MR9IF (Bit 9) */ +#define SN_CT16B1_RIS_MR9IF_Msk (0x200UL) /*!< MR9IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR10IF_Pos (10UL) /*!< MR10IF (Bit 10) */ +#define SN_CT16B1_RIS_MR10IF_Msk (0x400UL) /*!< MR10IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR11IF_Pos (11UL) /*!< MR11IF (Bit 11) */ +#define SN_CT16B1_RIS_MR11IF_Msk (0x800UL) /*!< MR11IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR12IF_Pos (12UL) /*!< MR12IF (Bit 12) */ +#define SN_CT16B1_RIS_MR12IF_Msk (0x1000UL) /*!< MR12IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR13IF_Pos (13UL) /*!< MR13IF (Bit 13) */ +#define SN_CT16B1_RIS_MR13IF_Msk (0x2000UL) /*!< MR13IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR14IF_Pos (14UL) /*!< MR14IF (Bit 14) */ +#define SN_CT16B1_RIS_MR14IF_Msk (0x4000UL) /*!< MR14IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR15IF_Pos (15UL) /*!< MR15IF (Bit 15) */ +#define SN_CT16B1_RIS_MR15IF_Msk (0x8000UL) /*!< MR15IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR16IF_Pos (16UL) /*!< MR16IF (Bit 16) */ +#define SN_CT16B1_RIS_MR16IF_Msk (0x10000UL) /*!< MR16IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR17IF_Pos (17UL) /*!< MR17IF (Bit 17) */ +#define SN_CT16B1_RIS_MR17IF_Msk (0x20000UL) /*!< MR17IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR18IF_Pos (18UL) /*!< MR18IF (Bit 18) */ +#define SN_CT16B1_RIS_MR18IF_Msk (0x40000UL) /*!< MR18IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR19IF_Pos (19UL) /*!< MR19IF (Bit 19) */ +#define SN_CT16B1_RIS_MR19IF_Msk (0x80000UL) /*!< MR19IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR20IF_Pos (20UL) /*!< MR20IF (Bit 20) */ +#define SN_CT16B1_RIS_MR20IF_Msk (0x100000UL) /*!< MR20IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR21IF_Pos (21UL) /*!< MR21IF (Bit 21) */ +#define SN_CT16B1_RIS_MR21IF_Msk (0x200000UL) /*!< MR21IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR22IF_Pos (22UL) /*!< MR22IF (Bit 22) */ +#define SN_CT16B1_RIS_MR22IF_Msk (0x400000UL) /*!< MR22IF (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_RIS_MR23IF_Pos (23UL) /*!< MR23IF (Bit 23) */ +#define SN_CT16B1_RIS_MR23IF_Msk (0x800000UL) /*!< MR23IF (Bitfield-Mask: 0x01) */ +/* ========================================================== IC =========================================================== */ +#define SN_CT16B1_IC_MR0IC_Pos (0UL) /*!< MR0IC (Bit 0) */ +#define SN_CT16B1_IC_MR0IC_Msk (0x1UL) /*!< MR0IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR1IC_Pos (1UL) /*!< MR1IC (Bit 1) */ +#define SN_CT16B1_IC_MR1IC_Msk (0x2UL) /*!< MR1IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR2IC_Pos (2UL) /*!< MR2IC (Bit 2) */ +#define SN_CT16B1_IC_MR2IC_Msk (0x4UL) /*!< MR2IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR3IC_Pos (3UL) /*!< MR3IC (Bit 3) */ +#define SN_CT16B1_IC_MR3IC_Msk (0x8UL) /*!< MR3IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR4IC_Pos (4UL) /*!< MR4IC (Bit 4) */ +#define SN_CT16B1_IC_MR4IC_Msk (0x10UL) /*!< MR4IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR5IC_Pos (5UL) /*!< MR5IC (Bit 5) */ +#define SN_CT16B1_IC_MR5IC_Msk (0x20UL) /*!< MR5IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR6IC_Pos (6UL) /*!< MR6IC (Bit 6) */ +#define SN_CT16B1_IC_MR6IC_Msk (0x40UL) /*!< MR6IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR7IC_Pos (7UL) /*!< MR7IC (Bit 7) */ +#define SN_CT16B1_IC_MR7IC_Msk (0x80UL) /*!< MR7IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR8IC_Pos (8UL) /*!< MR8IC (Bit 8) */ +#define SN_CT16B1_IC_MR8IC_Msk (0x100UL) /*!< MR8IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR9IC_Pos (9UL) /*!< MR9IC (Bit 9) */ +#define SN_CT16B1_IC_MR9IC_Msk (0x200UL) /*!< MR9IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR10IC_Pos (10UL) /*!< MR10IC (Bit 10) */ +#define SN_CT16B1_IC_MR10IC_Msk (0x400UL) /*!< MR10IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR11IC_Pos (11UL) /*!< MR11IC (Bit 11) */ +#define SN_CT16B1_IC_MR11IC_Msk (0x800UL) /*!< MR11IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR12IC_Pos (12UL) /*!< MR12IC (Bit 12) */ +#define SN_CT16B1_IC_MR12IC_Msk (0x1000UL) /*!< MR12IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR13IC_Pos (13UL) /*!< MR13IC (Bit 13) */ +#define SN_CT16B1_IC_MR13IC_Msk (0x2000UL) /*!< MR13IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR14IC_Pos (14UL) /*!< MR14IC (Bit 14) */ +#define SN_CT16B1_IC_MR14IC_Msk (0x4000UL) /*!< MR14IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR15IC_Pos (15UL) /*!< MR15IC (Bit 15) */ +#define SN_CT16B1_IC_MR15IC_Msk (0x8000UL) /*!< MR15IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR16IC_Pos (16UL) /*!< MR16IC (Bit 16) */ +#define SN_CT16B1_IC_MR16IC_Msk (0x10000UL) /*!< MR16IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR17IC_Pos (17UL) /*!< MR17IC (Bit 17) */ +#define SN_CT16B1_IC_MR17IC_Msk (0x20000UL) /*!< MR17IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR18IC_Pos (18UL) /*!< MR18IC (Bit 18) */ +#define SN_CT16B1_IC_MR18IC_Msk (0x40000UL) /*!< MR18IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR19IC_Pos (19UL) /*!< MR19IC (Bit 19) */ +#define SN_CT16B1_IC_MR19IC_Msk (0x80000UL) /*!< MR19IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR20IC_Pos (20UL) /*!< MR20IC (Bit 20) */ +#define SN_CT16B1_IC_MR20IC_Msk (0x100000UL) /*!< MR20IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR21IC_Pos (21UL) /*!< MR21IC (Bit 21) */ +#define SN_CT16B1_IC_MR21IC_Msk (0x200000UL) /*!< MR21IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR22IC_Pos (22UL) /*!< MR22IC (Bit 22) */ +#define SN_CT16B1_IC_MR22IC_Msk (0x400000UL) /*!< MR22IC (Bitfield-Mask: 0x01) */ +#define SN_CT16B1_IC_MR23IC_Pos (23UL) /*!< MR23IC (Bit 23) */ +#define SN_CT16B1_IC_MR23IC_Msk (0x800000UL) /*!< MR23IC (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ SN_PMU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +#define SN_PMU_CTRL_MODE_Pos (0UL) /*!< MODE (Bit 0) */ +#define SN_PMU_CTRL_MODE_Msk (0x7UL) /*!< MODE (Bitfield-Mask: 0x07) */ + + +/* =========================================================================================================================== */ +/* ================ SN_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL0 ========================================================= */ +#define SN_SPI0_CTRL0_SSPEN_Pos (0UL) /*!< SSPEN (Bit 0) */ +#define SN_SPI0_CTRL0_SSPEN_Msk (0x1UL) /*!< SSPEN (Bitfield-Mask: 0x01) */ +#define SN_SPI0_CTRL0_LOOPBACK_Pos (1UL) /*!< LOOPBACK (Bit 1) */ +#define SN_SPI0_CTRL0_LOOPBACK_Msk (0x2UL) /*!< LOOPBACK (Bitfield-Mask: 0x01) */ +#define SN_SPI0_CTRL0_SDODIS_Pos (2UL) /*!< SDODIS (Bit 2) */ +#define SN_SPI0_CTRL0_SDODIS_Msk (0x4UL) /*!< SDODIS (Bitfield-Mask: 0x01) */ +#define SN_SPI0_CTRL0_MS_Pos (3UL) /*!< MS (Bit 3) */ +#define SN_SPI0_CTRL0_MS_Msk (0x8UL) /*!< MS (Bitfield-Mask: 0x01) */ +#define SN_SPI0_CTRL0_FORMAT_Pos (4UL) /*!< FORMAT (Bit 4) */ +#define SN_SPI0_CTRL0_FORMAT_Msk (0x10UL) /*!< FORMAT (Bitfield-Mask: 0x01) */ +#define SN_SPI0_CTRL0_FRESET_Pos (6UL) /*!< FRESET (Bit 6) */ +#define SN_SPI0_CTRL0_FRESET_Msk (0xc0UL) /*!< FRESET (Bitfield-Mask: 0x03) */ +#define SN_SPI0_CTRL0_DL_Pos (8UL) /*!< DL (Bit 8) */ +#define SN_SPI0_CTRL0_DL_Msk (0xf00UL) /*!< DL (Bitfield-Mask: 0x0f) */ +#define SN_SPI0_CTRL0_TXFIFOTH_Pos (12UL) /*!< TXFIFOTH (Bit 12) */ +#define SN_SPI0_CTRL0_TXFIFOTH_Msk (0x7000UL) /*!< TXFIFOTH (Bitfield-Mask: 0x07) */ +#define SN_SPI0_CTRL0_RXFIFOTH_Pos (15UL) /*!< RXFIFOTH (Bit 15) */ +#define SN_SPI0_CTRL0_RXFIFOTH_Msk (0x38000UL) /*!< RXFIFOTH (Bitfield-Mask: 0x07) */ +#define SN_SPI0_CTRL0_SELDIS_Pos (18UL) /*!< SELDIS (Bit 18) */ +#define SN_SPI0_CTRL0_SELDIS_Msk (0x40000UL) /*!< SELDIS (Bitfield-Mask: 0x01) */ +/* ========================================================= CTRL1 ========================================================= */ +#define SN_SPI0_CTRL1_MLSB_Pos (0UL) /*!< MLSB (Bit 0) */ +#define SN_SPI0_CTRL1_MLSB_Msk (0x1UL) /*!< MLSB (Bitfield-Mask: 0x01) */ +#define SN_SPI0_CTRL1_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ +#define SN_SPI0_CTRL1_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ +#define SN_SPI0_CTRL1_CPHA_Pos (2UL) /*!< CPHA (Bit 2) */ +#define SN_SPI0_CTRL1_CPHA_Msk (0x4UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== CLKDIV ========================================================= */ +#define SN_SPI0_CLKDIV_DIV_Pos (0UL) /*!< DIV (Bit 0) */ +#define SN_SPI0_CLKDIV_DIV_Msk (0xffUL) /*!< DIV (Bitfield-Mask: 0xff) */ +/* ========================================================= STAT ========================================================== */ +#define SN_SPI0_STAT_TX_EMPTY_Pos (0UL) /*!< TX_EMPTY (Bit 0) */ +#define SN_SPI0_STAT_TX_EMPTY_Msk (0x1UL) /*!< TX_EMPTY (Bitfield-Mask: 0x01) */ +#define SN_SPI0_STAT_TX_FULL_Pos (1UL) /*!< TX_FULL (Bit 1) */ +#define SN_SPI0_STAT_TX_FULL_Msk (0x2UL) /*!< TX_FULL (Bitfield-Mask: 0x01) */ +#define SN_SPI0_STAT_RX_EMPTY_Pos (2UL) /*!< RX_EMPTY (Bit 2) */ +#define SN_SPI0_STAT_RX_EMPTY_Msk (0x4UL) /*!< RX_EMPTY (Bitfield-Mask: 0x01) */ +#define SN_SPI0_STAT_RX_FULL_Pos (3UL) /*!< RX_FULL (Bit 3) */ +#define SN_SPI0_STAT_RX_FULL_Msk (0x8UL) /*!< RX_FULL (Bitfield-Mask: 0x01) */ +#define SN_SPI0_STAT_BUSY_Pos (4UL) /*!< BUSY (Bit 4) */ +#define SN_SPI0_STAT_BUSY_Msk (0x10UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define SN_SPI0_STAT_TXFIFOTHF_Pos (5UL) /*!< TXFIFOTHF (Bit 5) */ +#define SN_SPI0_STAT_TXFIFOTHF_Msk (0x20UL) /*!< TXFIFOTHF (Bitfield-Mask: 0x01) */ +#define SN_SPI0_STAT_RXFIFOTHF_Pos (6UL) /*!< RXFIFOTHF (Bit 6) */ +#define SN_SPI0_STAT_RXFIFOTHF_Msk (0x40UL) /*!< RXFIFOTHF (Bitfield-Mask: 0x01) */ +/* ========================================================== IE =========================================================== */ +#define SN_SPI0_IE_RXOVFIE_Pos (0UL) /*!< RXOVFIE (Bit 0) */ +#define SN_SPI0_IE_RXOVFIE_Msk (0x1UL) /*!< RXOVFIE (Bitfield-Mask: 0x01) */ +#define SN_SPI0_IE_RXTOIE_Pos (1UL) /*!< RXTOIE (Bit 1) */ +#define SN_SPI0_IE_RXTOIE_Msk (0x2UL) /*!< RXTOIE (Bitfield-Mask: 0x01) */ +#define SN_SPI0_IE_RXFIFOTHIE_Pos (2UL) /*!< RXFIFOTHIE (Bit 2) */ +#define SN_SPI0_IE_RXFIFOTHIE_Msk (0x4UL) /*!< RXFIFOTHIE (Bitfield-Mask: 0x01) */ +#define SN_SPI0_IE_TXFIFOTHIE_Pos (3UL) /*!< TXFIFOTHIE (Bit 3) */ +#define SN_SPI0_IE_TXFIFOTHIE_Msk (0x8UL) /*!< TXFIFOTHIE (Bitfield-Mask: 0x01) */ +/* ========================================================== RIS ========================================================== */ +#define SN_SPI0_RIS_RXOVFIF_Pos (0UL) /*!< RXOVFIF (Bit 0) */ +#define SN_SPI0_RIS_RXOVFIF_Msk (0x1UL) /*!< RXOVFIF (Bitfield-Mask: 0x01) */ +#define SN_SPI0_RIS_RXTOIF_Pos (1UL) /*!< RXTOIF (Bit 1) */ +#define SN_SPI0_RIS_RXTOIF_Msk (0x2UL) /*!< RXTOIF (Bitfield-Mask: 0x01) */ +#define SN_SPI0_RIS_RXFIFOTHIF_Pos (2UL) /*!< RXFIFOTHIF (Bit 2) */ +#define SN_SPI0_RIS_RXFIFOTHIF_Msk (0x4UL) /*!< RXFIFOTHIF (Bitfield-Mask: 0x01) */ +#define SN_SPI0_RIS_TXFIFOTHIF_Pos (3UL) /*!< TXFIFOTHIF (Bit 3) */ +#define SN_SPI0_RIS_TXFIFOTHIF_Msk (0x8UL) /*!< TXFIFOTHIF (Bitfield-Mask: 0x01) */ +/* ========================================================== IC =========================================================== */ +#define SN_SPI0_IC_RXOVFIC_Pos (0UL) /*!< RXOVFIC (Bit 0) */ +#define SN_SPI0_IC_RXOVFIC_Msk (0x1UL) /*!< RXOVFIC (Bitfield-Mask: 0x01) */ +#define SN_SPI0_IC_RXTOIC_Pos (1UL) /*!< RXTOIC (Bit 1) */ +#define SN_SPI0_IC_RXTOIC_Msk (0x2UL) /*!< RXTOIC (Bitfield-Mask: 0x01) */ +#define SN_SPI0_IC_RXFIFOTHIC_Pos (2UL) /*!< RXFIFOTHIC (Bit 2) */ +#define SN_SPI0_IC_RXFIFOTHIC_Msk (0x4UL) /*!< RXFIFOTHIC (Bitfield-Mask: 0x01) */ +#define SN_SPI0_IC_TXFIFOTHIC_Pos (3UL) /*!< TXFIFOTHIC (Bit 3) */ +#define SN_SPI0_IC_TXFIFOTHIC_Msk (0x8UL) /*!< TXFIFOTHIC (Bitfield-Mask: 0x01) */ +/* ========================================================= DATA ========================================================== */ +#define SN_SPI0_DATA_Data_Pos (0UL) /*!< Data (Bit 0) */ +#define SN_SPI0_DATA_Data_Msk (0xffffUL) /*!< Data (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ +#define SN_SPI0_DF_DF_Pos (0UL) /*!< DF (Bit 0) */ +#define SN_SPI0_DF_DF_Msk (0x1UL) /*!< DF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ SN_I2C0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +#define SN_I2C0_CTRL_NACK_Pos (1UL) /*!< NACK (Bit 1) */ +#define SN_I2C0_CTRL_NACK_Msk (0x2UL) /*!< NACK (Bitfield-Mask: 0x01) */ +#define SN_I2C0_CTRL_ACK_Pos (2UL) /*!< ACK (Bit 2) */ +#define SN_I2C0_CTRL_ACK_Msk (0x4UL) /*!< ACK (Bitfield-Mask: 0x01) */ +#define SN_I2C0_CTRL_STO_Pos (4UL) /*!< STO (Bit 4) */ +#define SN_I2C0_CTRL_STO_Msk (0x10UL) /*!< STO (Bitfield-Mask: 0x01) */ +#define SN_I2C0_CTRL_STA_Pos (5UL) /*!< STA (Bit 5) */ +#define SN_I2C0_CTRL_STA_Msk (0x20UL) /*!< STA (Bitfield-Mask: 0x01) */ +#define SN_I2C0_CTRL_MODE_Pos (7UL) /*!< MODE (Bit 7) */ +#define SN_I2C0_CTRL_MODE_Msk (0x80UL) /*!< MODE (Bitfield-Mask: 0x01) */ +#define SN_I2C0_CTRL_I2CEN_Pos (8UL) /*!< I2CEN (Bit 8) */ +#define SN_I2C0_CTRL_I2CEN_Msk (0x100UL) /*!< I2CEN (Bitfield-Mask: 0x01) */ +/* ========================================================= STAT ========================================================== */ +#define SN_I2C0_STAT_RX_DN_Pos (0UL) /*!< RX_DN (Bit 0) */ +#define SN_I2C0_STAT_RX_DN_Msk (0x1UL) /*!< RX_DN (Bitfield-Mask: 0x01) */ +#define SN_I2C0_STAT_ACK_STAT_Pos (1UL) /*!< ACK_STAT (Bit 1) */ +#define SN_I2C0_STAT_ACK_STAT_Msk (0x2UL) /*!< ACK_STAT (Bitfield-Mask: 0x01) */ +#define SN_I2C0_STAT_NACK_STAT_Pos (2UL) /*!< NACK_STAT (Bit 2) */ +#define SN_I2C0_STAT_NACK_STAT_Msk (0x4UL) /*!< NACK_STAT (Bitfield-Mask: 0x01) */ +#define SN_I2C0_STAT_STOP_DN_Pos (3UL) /*!< STOP_DN (Bit 3) */ +#define SN_I2C0_STAT_STOP_DN_Msk (0x8UL) /*!< STOP_DN (Bitfield-Mask: 0x01) */ +#define SN_I2C0_STAT_START_DN_Pos (4UL) /*!< START_DN (Bit 4) */ +#define SN_I2C0_STAT_START_DN_Msk (0x10UL) /*!< START_DN (Bitfield-Mask: 0x01) */ +#define SN_I2C0_STAT_MST_Pos (5UL) /*!< MST (Bit 5) */ +#define SN_I2C0_STAT_MST_Msk (0x20UL) /*!< MST (Bitfield-Mask: 0x01) */ +#define SN_I2C0_STAT_SLV_RX_HIT_Pos (6UL) /*!< SLV_RX_HIT (Bit 6) */ +#define SN_I2C0_STAT_SLV_RX_HIT_Msk (0x40UL) /*!< SLV_RX_HIT (Bitfield-Mask: 0x01) */ +#define SN_I2C0_STAT_SLV_TX_HIT_Pos (7UL) /*!< SLV_TX_HIT (Bit 7) */ +#define SN_I2C0_STAT_SLV_TX_HIT_Msk (0x80UL) /*!< SLV_TX_HIT (Bitfield-Mask: 0x01) */ +#define SN_I2C0_STAT_LOST_ARB_Pos (8UL) /*!< LOST_ARB (Bit 8) */ +#define SN_I2C0_STAT_LOST_ARB_Msk (0x100UL) /*!< LOST_ARB (Bitfield-Mask: 0x01) */ +#define SN_I2C0_STAT_TIMEOUT_Pos (9UL) /*!< TIMEOUT (Bit 9) */ +#define SN_I2C0_STAT_TIMEOUT_Msk (0x200UL) /*!< TIMEOUT (Bitfield-Mask: 0x01) */ +#define SN_I2C0_STAT_I2CIF_Pos (15UL) /*!< I2CIF (Bit 15) */ +#define SN_I2C0_STAT_I2CIF_Msk (0x8000UL) /*!< I2CIF (Bitfield-Mask: 0x01) */ +/* ======================================================== TXDATA ========================================================= */ +#define SN_I2C0_TXDATA_Data_Pos (0UL) /*!< Data (Bit 0) */ +#define SN_I2C0_TXDATA_Data_Msk (0xffUL) /*!< Data (Bitfield-Mask: 0xff) */ +/* ======================================================== RXDATA ========================================================= */ +#define SN_I2C0_RXDATA_Data_Pos (0UL) /*!< Data (Bit 0) */ +#define SN_I2C0_RXDATA_Data_Msk (0xffUL) /*!< Data (Bitfield-Mask: 0xff) */ +/* ======================================================= SLVADDR0 ======================================================== */ +#define SN_I2C0_SLVADDR0_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define SN_I2C0_SLVADDR0_ADDR_Msk (0x3ffUL) /*!< ADDR (Bitfield-Mask: 0x3ff) */ +#define SN_I2C0_SLVADDR0_GCEN_Pos (30UL) /*!< GCEN (Bit 30) */ +#define SN_I2C0_SLVADDR0_GCEN_Msk (0x40000000UL) /*!< GCEN (Bitfield-Mask: 0x01) */ +#define SN_I2C0_SLVADDR0_ADD_MODE_Pos (31UL) /*!< ADD_MODE (Bit 31) */ +#define SN_I2C0_SLVADDR0_ADD_MODE_Msk (0x80000000UL) /*!< ADD_MODE (Bitfield-Mask: 0x01) */ +/* ======================================================= SLVADDR1 ======================================================== */ +#define SN_I2C0_SLVADDR1_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define SN_I2C0_SLVADDR1_ADDR_Msk (0x3ffUL) /*!< ADDR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= SLVADDR2 ======================================================== */ +#define SN_I2C0_SLVADDR2_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define SN_I2C0_SLVADDR2_ADDR_Msk (0x3ffUL) /*!< ADDR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= SLVADDR3 ======================================================== */ +#define SN_I2C0_SLVADDR3_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define SN_I2C0_SLVADDR3_ADDR_Msk (0x3ffUL) /*!< ADDR (Bitfield-Mask: 0x3ff) */ +/* ========================================================= SCLHT ========================================================= */ +#define SN_I2C0_SCLHT_SCLH_Pos (0UL) /*!< SCLH (Bit 0) */ +#define SN_I2C0_SCLHT_SCLH_Msk (0xffUL) /*!< SCLH (Bitfield-Mask: 0xff) */ +/* ========================================================= SCLLT ========================================================= */ +#define SN_I2C0_SCLLT_SCLL_Pos (0UL) /*!< SCLL (Bit 0) */ +#define SN_I2C0_SCLLT_SCLL_Msk (0xffUL) /*!< SCLL (Bitfield-Mask: 0xff) */ +/* ========================================================= SCLCT ========================================================= */ +#define SN_I2C0_SCLCT_SCLCT_Pos (0UL) /*!< SCLCT (Bit 0) */ +#define SN_I2C0_SCLCT_SCLCT_Msk (0xfUL) /*!< SCLCT (Bitfield-Mask: 0x0f) */ +/* ======================================================== TOCTRL ========================================================= */ +#define SN_I2C0_TOCTRL_TO_Pos (0UL) /*!< TO (Bit 0) */ +#define SN_I2C0_TOCTRL_TO_Msk (0xffffUL) /*!< TO (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ SN_FLASH ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== LPCTRL ========================================================= */ +#define SN_FLASH_LPCTRL_LPMODE_Pos (0UL) /*!< LPMODE (Bit 0) */ +#define SN_FLASH_LPCTRL_LPMODE_Msk (0xfUL) /*!< LPMODE (Bitfield-Mask: 0x0f) */ +/* ======================================================== STATUS ========================================================= */ +#define SN_FLASH_STATUS_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */ +#define SN_FLASH_STATUS_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +#define SN_FLASH_STATUS_ERR_Pos (2UL) /*!< ERR (Bit 2) */ +#define SN_FLASH_STATUS_ERR_Msk (0x4UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ========================================================= CTRL ========================================================== */ +#define SN_FLASH_CTRL_PG_Pos (0UL) /*!< PG (Bit 0) */ +#define SN_FLASH_CTRL_PG_Msk (0x1UL) /*!< PG (Bitfield-Mask: 0x01) */ +#define SN_FLASH_CTRL_PER_Pos (1UL) /*!< PER (Bit 1) */ +#define SN_FLASH_CTRL_PER_Msk (0x2UL) /*!< PER (Bitfield-Mask: 0x01) */ +#define SN_FLASH_CTRL_MER_Pos (2UL) /*!< MER (Bit 2) */ +#define SN_FLASH_CTRL_MER_Msk (0x4UL) /*!< MER (Bitfield-Mask: 0x01) */ +#define SN_FLASH_CTRL_START_Pos (6UL) /*!< START (Bit 6) */ +#define SN_FLASH_CTRL_START_Msk (0x40UL) /*!< START (Bitfield-Mask: 0x01) */ +#define SN_FLASH_CTRL_CHK_Pos (7UL) /*!< CHK (Bit 7) */ +#define SN_FLASH_CTRL_CHK_Msk (0x80UL) /*!< CHK (Bitfield-Mask: 0x01) */ +/* ========================================================= DATA ========================================================== */ +/* ========================================================= ADDR ========================================================== */ +/* ======================================================== CHKSUM ========================================================= */ +#define SN_FLASH_CHKSUM_UserROM_Pos (0UL) /*!< UserROM (Bit 0) */ +#define SN_FLASH_CHKSUM_UserROM_Msk (0xffffUL) /*!< UserROM (Bitfield-Mask: 0xffff) */ +#define SN_FLASH_CHKSUM_BootROM_Pos (16UL) /*!< BootROM (Bit 16) */ +#define SN_FLASH_CHKSUM_BootROM_Msk (0xffff0000UL) /*!< BootROM (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ SN_UC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== L4BYTE ========================================================= */ +/* ======================================================== H4BYTE ========================================================= */ + +/** @} */ /* End of group PosMask_peripherals */ + + +#ifdef __cplusplus +} +#endif + +#endif /* SN32F260_DEFINES_H */ + + +/** @} */ /* End of group SN32F260 */ + +/** @} */ /* End of group SONiX Technology Co., Ltd. */ diff --git a/os/common/ext/SONiX/SN32F2xx/SN32F280.h b/os/common/ext/SONiX/SN32F2xx/SN32F280.h new file mode 100644 index 00000000..17167672 --- /dev/null +++ b/os/common/ext/SONiX/SN32F2xx/SN32F280.h @@ -0,0 +1,4896 @@ +/* + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontroller, but can be equally used for other + * suitable processor architectures. This file can be freely distributed. + * Modifications to this file shall be clearly marked. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * @file SN32F280.h + * @brief CMSIS HeaderFile + * @version 0.65 + * @date 09. January 2022 + * @note Generated by SVDConv V3.3.35 on Sunday, 09.01.2022 18:50:19 + * from File 'SN32F280.svd', + * last modified on Tuesday, 01.09.2020 10:52:27 + */ + + + +/** @addtogroup SONiX Technology Co., Ltd. + * @{ + */ + + +/** @addtogroup SN32F280 + * @{ + */ + + +#ifndef SN32F280_H +#define SN32F280_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M0 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== SN32F280 Specific Interrupt Numbers ========================================== */ + NDT_IRQn = 0, /*!< 0 Noise Detection */ + USB_IRQn = 1, /*!< 1 USB */ + LCD_IRQn = 2, /*!< 2 LCD Driver */ + I2S0_IRQn = 3, /*!< 3 I2S0 */ + I2S1_IRQn = 4, /*!< 4 I2S1 */ + CMP3_IRQn = 5, /*!< 5 CMP3 */ + SPI0_IRQn = 6, /*!< 6 SPI0 */ + SPI1_IRQn = 7, /*!< 7 SPI1 */ + UART2_IRQn = 8, /*!< 8 UART2 */ + UART3_IRQn = 9, /*!< 9 UART3 */ + I2C0_IRQn = 10, /*!< 10 I2C0 */ + I2C1_IRQn = 11, /*!< 11 I2C1 */ + CMP2_IRQn = 12, /*!< 12 CMP2 */ + UART0_IRQn = 13, /*!< 13 UART0 */ + UART1_IRQn = 14, /*!< 14 UART1 */ + CT16B0_IRQn = 15, /*!< 15 16-bit Timer 0 */ + CT16B1_IRQn = 16, /*!< 16 CT16B1 */ + CT16B2_IRQn = 17, /*!< 17 16-bit Timer 2 */ + CMP1_IRQn = 18, /*!< 18 CMP1 */ + CT16B3_IRQn = 19, /*!< 19 16-bit Timer 3 */ + CT16B4_IRQn = 20, /*!< 20 16-bit Timer 4 */ + CT16B5_IRQn = 21, /*!< 21 16-bit Timer 5 */ + EBI_IRQn = 22, /*!< 22 External Bus Interface */ + RTC_IRQn = 23, /*!< 23 Real-time Clock */ + ADC_IRQn = 24, /*!< 24 ADC */ + WDT_IRQn = 25, /*!< 25 Watchdog Timer */ + LVD_IRQn = 26, /*!< 26 Low Voltage Detection */ + CMP0_IRQn = 27, /*!< 27 CMP0 */ + P3_IRQn = 28, /*!< 28 GPIO3 */ + P2_IRQn = 29, /*!< 29 GPIO2 */ + P1_IRQn = 30, /*!< 30 GPIO1 */ + P0_IRQn = 31 /*!< 31 GPIO0 */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M0 Processor and Core Peripherals =========================== */ +#define __CM0_REV 0x0000U /*!< CM0 Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 0 /*!< MPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0.h" /*!< ARM Cortex-M0 processor and core peripherals */ +#include "system_SN32F2xx.h" /*!< SN32F280 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SYS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System Control Registers 0 (SN_SYS0) + */ + +typedef struct { /*!< (@ 0x40060000) SN_SYS0 Structure */ + + union { + __IOM uint32_t ANBCTRL; /*!< (@ 0x00000000) Offset:0x00 Analog Block Control Register */ + + struct { + __IOM uint32_t IHRCEN : 1; /*!< [0..0] IHRC enable */ + uint32_t : 1; + __IOM uint32_t ELSEN : 1; /*!< [2..2] ELS XTAL enable */ + uint32_t : 1; + __IOM uint32_t EHSEN : 1; /*!< [4..4] EHS XTAL enable */ + __IOM uint32_t EHSFREQ : 1; /*!< [5..5] EHS XTAL frequency range */ + uint32_t : 26; + } ANBCTRL_b; + } ; + + union { + __IOM uint32_t PLLCTRL; /*!< (@ 0x00000004) Offset:0x04 PLL Control Register */ + + struct { + __IOM uint32_t MSEL : 3; /*!< [2..0] M value */ + uint32_t : 2; + __IOM uint32_t PSEL : 1; /*!< [5..5] P value */ + uint32_t : 6; + __IOM uint32_t PLLCLKSEL : 1; /*!< [12..12] PLL clock source */ + uint32_t : 2; + __IOM uint32_t PLLEN : 1; /*!< [15..15] PLL enable */ + uint32_t : 16; + } PLLCTRL_b; + } ; + + union { + __IM uint32_t CSST; /*!< (@ 0x00000008) Offset:0x08 Clock Source Status Register */ + + struct { + __IM uint32_t IHRCRDY : 1; /*!< [0..0] IHRC ready flag */ + uint32_t : 1; + __IM uint32_t ELSRDY : 1; /*!< [2..2] ELS XTAL ready flag */ + uint32_t : 1; + __IM uint32_t EHSRDY : 1; /*!< [4..4] EHS XTAL ready flag */ + uint32_t : 1; + __IM uint32_t PLLRDY : 1; /*!< [6..6] PLL ready flag */ + uint32_t : 25; + } CSST_b; + } ; + + union { + __IOM uint32_t CLKCFG; /*!< (@ 0x0000000C) Offset:0x0C System Clock Configuration Register */ + + struct { + __IOM uint32_t SYSCLKSEL : 3; /*!< [2..0] System clock source selection */ + uint32_t : 1; + __IM uint32_t SYSCLKST : 3; /*!< [6..4] System clock switch status */ + uint32_t : 25; + } CLKCFG_b; + } ; + + union { + __IOM uint32_t AHBCP; /*!< (@ 0x00000010) Offset:0x10 AHB Clock Prescale Register */ + + struct { + __IOM uint32_t AHBPRE : 3; /*!< [2..0] AHB clock source prescaler */ + __IOM uint32_t DIV1P5 : 1; /*!< [3..3] SYSCLK prescaler */ + uint32_t : 28; + } AHBCP_b; + } ; + + union { + __IOM uint32_t RSTST; /*!< (@ 0x00000014) Offset:0x14 System Reset Status Register */ + + struct { + __IOM uint32_t SWRSTF : 1; /*!< [0..0] Software reset flag */ + __IOM uint32_t WDTRSTF : 1; /*!< [1..1] WDT reset flag */ + __IOM uint32_t LVDRSTF : 1; /*!< [2..2] LVD reset flag */ + __IOM uint32_t EXTRSTF : 1; /*!< [3..3] External reset flag */ + __IOM uint32_t PORRSTF : 1; /*!< [4..4] POR reset flag */ + uint32_t : 27; + } RSTST_b; + } ; + + union { + __IOM uint32_t LVDCTRL; /*!< (@ 0x00000018) Offset:0x18 LVD Control Register */ + + struct { + __IOM uint32_t LVDRSTLVL : 3; /*!< [2..0] LVD reset level */ + uint32_t : 1; + __IOM uint32_t LVDINTLVL : 3; /*!< [6..4] LVD interrupt level */ + uint32_t : 7; + __IOM uint32_t LVDRSTEN : 1; /*!< [14..14] LVD Reset enable */ + __IOM uint32_t LVDEN : 1; /*!< [15..15] LVD enable */ + uint32_t : 16; + } LVDCTRL_b; + } ; + + union { + __IOM uint32_t EXRSTCTRL; /*!< (@ 0x0000001C) Offset:0x1C External Reset Pin Control Register */ + + struct { + __IOM uint32_t RESETDIS : 1; /*!< [0..0] External reset pin disable */ + uint32_t : 31; + } EXRSTCTRL_b; + } ; + + union { + __IOM uint32_t SWDCTRL; /*!< (@ 0x00000020) Offset:0x20 SWD Pin Control Register */ + + struct { + __IOM uint32_t SWDDIS : 1; /*!< [0..0] SWD pin disable */ + uint32_t : 31; + } SWDCTRL_b; + } ; + + union { + __IOM uint32_t IVTM; /*!< (@ 0x00000024) Offset:0x24 Interrupt Vector Table Mapping register */ + + struct { + __IOM uint32_t IVTM : 3; /*!< [2..0] Interrupt table mapping selection */ + uint32_t : 13; + __OM uint32_t IVTMKEY : 16; /*!< [31..16] IVTM register key */ + } IVTM_b; + } ; + + union { + __IOM uint32_t NDTCTRL; /*!< (@ 0x00000028) Offset:0x28 Noise Detect Control Register */ + + struct { + uint32_t : 1; + __IOM uint32_t NDT5V_IE : 1; /*!< [1..1] NDT for VDD 5V interrupt enable bit */ + uint32_t : 30; + } NDTCTRL_b; + } ; + + union { + __IOM uint32_t NDTSTS; /*!< (@ 0x0000002C) Offset:0x2C Noise Detect Status Register */ + + struct { + uint32_t : 1; + __IOM uint32_t NDT5V_DET : 1; /*!< [1..1] Power noise status of NDT5V */ + uint32_t : 30; + } NDTSTS_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t IHRCADJ; /*!< (@ 0x00000034) Offset:0x34 IHRC Frequency Adjustment register */ + + struct { + __IOM uint32_t ADJEN : 1; /*!< [0..0] IHRC frequency adjustment enable bit */ + __IOM uint32_t DIR : 1; /*!< [1..1] IHRC frequency adjusting direction bit */ + uint32_t : 2; + __IOM uint32_t ADJ : 8; /*!< [11..4] IHRC frequency adjusting bits */ + uint32_t : 4; + __OM uint32_t SYSKEY : 16; /*!< [31..16] System register key */ + } IHRCADJ_b; + } ; +} SN_SYS0_Type; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SYS1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System Control Registers 1 (SN_SYS1) + */ + +typedef struct { /*!< (@ 0x4005E000) SN_SYS1 Structure */ + + union { + __IOM uint32_t AHBCLKEN; /*!< (@ 0x00000000) Offset:0x00 AHB Clock Enable Register */ + + struct { + uint32_t : 3; + __IOM uint32_t OPACLKEN : 1; /*!< [3..3] Enable AHB clock for OPA */ + __IOM uint32_t USBCLKEN : 1; /*!< [4..4] Enable AHB clock for USB */ + __IOM uint32_t CT16B0CLKEN : 1; /*!< [5..5] Enable AHB clock for CT16B0 */ + __IOM uint32_t CT16B1CLKEN : 1; /*!< [6..6] Enable AHB clock for CT16B1 */ + __IOM uint32_t CT16B2CLKEN : 1; /*!< [7..7] Enable AHB clock for CT16B2 */ + __IOM uint32_t CT16B3CLKEN : 1; /*!< [8..8] Enable AHB clock for CT16B3 */ + __IOM uint32_t CT16B4CLKEN : 1; /*!< [9..9] Enable AHB clock for CT16B4 */ + __IOM uint32_t CT16B5CLKEN : 1; /*!< [10..10] Enable AHB clock for CT16B5 */ + __IOM uint32_t ADCCLKEN : 1; /*!< [11..11] Enable AHB clock for ADC */ + __IOM uint32_t SPI0CLKEN : 1; /*!< [12..12] Enable AHB clock for SPI0 */ + __IOM uint32_t SPI1CLKEN : 1; /*!< [13..13] Enable AHB clock for SPI1 */ + __IOM uint32_t CMPCLKEN : 1; /*!< [14..14] Enable AHB clock for CMP */ + __IOM uint32_t EBICLKEN : 1; /*!< [15..15] Enable AHB clock for EBI */ + __IOM uint32_t UART0CLKEN : 1; /*!< [16..16] Enable AHB clock for UART0 */ + __IOM uint32_t UART1CLKEN : 1; /*!< [17..17] Enable AHB clock for UART1 */ + __IOM uint32_t UART2CLKEN : 1; /*!< [18..18] Enable AHB clock for UART2 */ + __IOM uint32_t UART3CLKEN : 1; /*!< [19..19] Enable AHB clock for UART3 */ + __IOM uint32_t I2C1CLKEN : 1; /*!< [20..20] Enable AHB clock for I2C1 */ + __IOM uint32_t I2C0CLKEN : 1; /*!< [21..21] Enable AHB clock for I2C0 */ + __IOM uint32_t I2S0CLKEN : 1; /*!< [22..22] Enable AHB clock for I2S0 */ + __IOM uint32_t RTCCLKEN : 1; /*!< [23..23] Enable AHB clock for RTC */ + __IOM uint32_t WDTCLKEN : 1; /*!< [24..24] Enable AHB clock for WDT */ + __IOM uint32_t I2S1CLKEN : 1; /*!< [25..25] Enable AHB clock for I2S1 */ + __IOM uint32_t LCDCLKEN : 1; /*!< [26..26] Enable AHB clock for LCD */ + __IOM uint32_t CRCCLKEN : 1; /*!< [27..27] Enable AHB clock for CRC */ + __IOM uint32_t CLKOUTSEL : 3; /*!< [30..28] Clock output source selection */ + uint32_t : 1; + } AHBCLKEN_b; + } ; + + union { + __IOM uint32_t APBCP0; /*!< (@ 0x00000004) Offset:0x04 APB Clock Prescale Register 0 */ + + struct { + uint32_t : 16; + __IOM uint32_t ADCPRE : 3; /*!< [18..16] ADC APB clock source prescaler */ + uint32_t : 13; + } APBCP0_b; + } ; + + union { + __IOM uint32_t APBCP1; /*!< (@ 0x00000008) Offset:0x08 APB Clock Prescale Register 1 */ + + struct { + uint32_t : 8; + __OM uint32_t I2C0PRE : 3; /*!< [10..8] I2C0 APB clock source prescaler */ + uint32_t : 1; + __IOM uint32_t I2S0PRE : 3; /*!< [14..12] I2S0 APB clock source prescaler */ + __IOM uint32_t I2S1PRE : 3; /*!< [17..15] I2S1 APB clock source prescaler */ + uint32_t : 2; + __IOM uint32_t WDTPRE : 3; /*!< [22..20] WDT APB clock source prescaler */ + uint32_t : 1; + __OM uint32_t I2C1PRE : 3; /*!< [26..24] I2C1 APB clock source prescaler */ + uint32_t : 1; + __IOM uint32_t CLKOUTPRE : 3; /*!< [30..28] CLKOUT APB clock source prescaler */ + uint32_t : 1; + } APBCP1_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t PRST; /*!< (@ 0x00000010) Offset:0x10 Peripheral Reset Register */ + + struct { + __IOM uint32_t GPIO0RST : 1; /*!< [0..0] GPIO0 Reset */ + __IOM uint32_t GPIO1RST : 1; /*!< [1..1] GPIO1 Reset */ + __IOM uint32_t GPIO2RST : 1; /*!< [2..2] GPIO2 Reset */ + __IOM uint32_t GPIO3RST : 1; /*!< [3..3] GPIO3 Reset */ + __IOM uint32_t EBIRST : 1; /*!< [4..4] EBI Reset */ + __IOM uint32_t CT16B0RST : 1; /*!< [5..5] CT16B0 Reset */ + __IOM uint32_t CT16B1RST : 1; /*!< [6..6] CT16B1 Reset */ + __IOM uint32_t CT16B2RST : 1; /*!< [7..7] CT16B2 Reset */ + __IOM uint32_t CT16B3RST : 1; /*!< [8..8] CT16B3 Reset */ + __IOM uint32_t CT16B4RST : 1; /*!< [9..9] CT16B4 Reset */ + __IOM uint32_t CT16B5RST : 1; /*!< [10..10] CT16B5 Reset */ + __IOM uint32_t ADCRST : 1; /*!< [11..11] ADC Reset */ + __IOM uint32_t SPI0RST : 1; /*!< [12..12] SPI0 Reset */ + __IOM uint32_t SPI1RST : 1; /*!< [13..13] SPI1 Reset */ + __IOM uint32_t CMPRST : 1; /*!< [14..14] CMP Reset */ + __IOM uint32_t LCDRST : 1; /*!< [15..15] LCD Reset */ + __IOM uint32_t UART0RST : 1; /*!< [16..16] UART0 Reset */ + __IOM uint32_t UART1RST : 1; /*!< [17..17] UART1 Reset */ + __IOM uint32_t UART2RST : 1; /*!< [18..18] UART2 Reset */ + __IOM uint32_t UART3RST : 1; /*!< [19..19] UART1 Reset */ + __IOM uint32_t I2C1RST : 1; /*!< [20..20] I2C1 Reset */ + __IOM uint32_t I2C0RST : 1; /*!< [21..21] I2C0 Reset */ + __IOM uint32_t I2S0RST : 1; /*!< [22..22] I2S0 Reset */ + __IOM uint32_t RTCRST : 1; /*!< [23..23] RTC Reset */ + __IOM uint32_t WDTRST : 1; /*!< [24..24] WDT Reset */ + __IOM uint32_t I2S1RST : 1; /*!< [25..25] I2S1 Reset */ + __IOM uint32_t CRCRST : 1; /*!< [26..26] CRC Reset */ + __IOM uint32_t USBRST : 1; /*!< [27..27] USB Reset */ + __IOM uint32_t OPARST : 1; /*!< [28..28] USB Reset */ + uint32_t : 3; + } PRST_b; + } ; +} SN_SYS1_Type; /*!< Size = 20 (0x14) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_PMU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power Management Unit (SN_PMU) + */ + +typedef struct { /*!< (@ 0x40032000) SN_PMU Structure */ + __IM uint32_t RESERVED[16]; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000040) Offset:0x40 PMU Control Register */ + + struct { + __IOM uint32_t MODE : 3; /*!< [2..0] Low Power mode selection */ + uint32_t : 29; + } CTRL_b; + } ; +} SN_PMU_Type; /*!< Size = 68 (0x44) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_PFPA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Peripheral Function Pin Assignment (SN_PFPA) + */ + +typedef struct { /*!< (@ 0x40042000) SN_PFPA Structure */ + + union { + __IOM uint32_t CT16B0; /*!< (@ 0x00000000) Offset:0x00 PFPA for CT16B0 Register */ + + struct { + __IOM uint32_t PWM0 : 2; /*!< [1..0] CT16B0_PWM0 assigned pin */ + __IOM uint32_t PWM0N : 2; /*!< [3..2] CT16B0_PWM0N assigned pin */ + __IOM uint32_t PWM1 : 2; /*!< [5..4] CT16B0_PWM1 assigned pin */ + __IOM uint32_t PWM1N : 2; /*!< [7..6] CT16B0_PWM1N assigned pin */ + __IOM uint32_t PWM2 : 2; /*!< [9..8] CT16B0_PWM2 assigned pin */ + __IOM uint32_t PWM2N : 2; /*!< [11..10] CT16B0_PWM2N assigned pin */ + __IOM uint32_t PWM3 : 2; /*!< [13..12] CT16B0_PWM3 assigned pin */ + __IOM uint32_t PWM3N : 2; /*!< [15..14] CT16B0_PWM3N assigned pin */ + uint32_t : 16; + } CT16B0_b; + } ; + + union { + __IOM uint32_t CT16B1; /*!< (@ 0x00000004) Offset:0x04 PFPA for CT16B1 Register */ + + struct { + __IOM uint32_t PWM00 : 1; /*!< [0..0] CT16B1_PWM00 assigned pin */ + __IOM uint32_t PWM01 : 1; /*!< [1..1] CT16B1_PWM01 assigned pin */ + __IOM uint32_t PWM02 : 1; /*!< [2..2] CT16B1_PWM02 assigned pin */ + __IOM uint32_t PWM03 : 1; /*!< [3..3] CT16B1_PWM03 assigned pin */ + __IOM uint32_t PWM04 : 1; /*!< [4..4] CT16B1_PWM04 assigned pin */ + __IOM uint32_t PWM05 : 1; /*!< [5..5] CT16B1_PWM05 assigned pin */ + __IOM uint32_t PWM06 : 1; /*!< [6..6] CT16B1_PWM06 assigned pin */ + __IOM uint32_t PWM07 : 1; /*!< [7..7] CT16B1_PWM07 assigned pin */ + __IOM uint32_t PWM08 : 1; /*!< [8..8] CT16B1_PWM08 assigned pin */ + __IOM uint32_t PWM09 : 1; /*!< [9..9] CT16B1_PWM09 assigned pin */ + __IOM uint32_t PWM10 : 1; /*!< [10..10] CT16B1_PWM10 assigned pin */ + __IOM uint32_t PWM11 : 1; /*!< [11..11] CT16B1_PWM11 assigned pin */ + uint32_t : 20; + } CT16B1_b; + } ; + + union { + __IOM uint32_t UART; /*!< (@ 0x00000008) Offset:0x08 PFPA for UART Register */ + + struct { + __IOM uint32_t UTXD0 : 2; /*!< [1..0] UTXD0 assigned pin */ + __IOM uint32_t URXD0 : 2; /*!< [3..2] URXD0 assigned pin */ + __IOM uint32_t UTXD1 : 2; /*!< [5..4] UTXD1 assigned pin */ + __IOM uint32_t URXD1 : 2; /*!< [7..6] URXD1 assigned pin */ + __IOM uint32_t UTXD2 : 2; /*!< [9..8] UTXD2 assigned pin */ + __IOM uint32_t URXD2 : 2; /*!< [11..10] URXD2 assigned pin */ + __IOM uint32_t UTXD3 : 2; /*!< [13..12] UTXD3 assigned pin */ + __IOM uint32_t URXD3 : 2; /*!< [15..14] URXD3 assigned pin */ + uint32_t : 16; + } UART_b; + } ; + + union { + __IOM uint32_t I2C; /*!< (@ 0x0000000C) Offset:0x0C PFPA for I2C Register */ + + struct { + __IOM uint32_t SDA0 : 2; /*!< [1..0] SDA0 assigned pin */ + __IOM uint32_t SCL0 : 2; /*!< [3..2] SCL0 assigned pin */ + __IOM uint32_t SDA1 : 2; /*!< [5..4] SDA1 assigned pin */ + __IOM uint32_t SCL1 : 2; /*!< [7..6] SCL1 assigned pin */ + uint32_t : 24; + } I2C_b; + } ; + + union { + __IOM uint32_t SPI; /*!< (@ 0x00000010) Offset:0x10 PFPA for SPI Register */ + + struct { + __IOM uint32_t MISO0 : 2; /*!< [1..0] MISO0 assigned pin */ + __IOM uint32_t MOSI0 : 2; /*!< [3..2] MOSI0 assigned pin */ + __IOM uint32_t SCK0 : 2; /*!< [5..4] SCK0 assigned pin */ + __IOM uint32_t SEL0 : 2; /*!< [7..6] SEL0 assigned pin */ + __IOM uint32_t MISO1 : 2; /*!< [9..8] MISO1 assigned pin */ + __IOM uint32_t MOSI1 : 2; /*!< [11..10] MOSI1 assigned pin */ + __IOM uint32_t SCK1 : 2; /*!< [13..12] SCK1 assigned pin */ + __IOM uint32_t SEL1 : 2; /*!< [15..14] SEL1 assigned pin */ + uint32_t : 16; + } SPI_b; + } ; + + union { + __IOM uint32_t I2S; /*!< (@ 0x00000014) Offset:0x14 PFPA for I2S Register */ + + struct { + __IOM uint32_t MCLK0 : 2; /*!< [1..0] MCLK0 assigned pin */ + __IOM uint32_t BCLK0 : 2; /*!< [3..2] BCLK0 assigned pin */ + __IOM uint32_t WS0 : 2; /*!< [5..4] WS0 assigned pin */ + __IOM uint32_t DOUT0 : 2; /*!< [7..6] DOUT0 assigned pin */ + __IOM uint32_t DIN0 : 2; /*!< [9..8] DIN0 assigned pin */ + __IOM uint32_t MCLK1 : 2; /*!< [11..10] MCLK1 assigned pin */ + __IOM uint32_t BCLK1 : 2; /*!< [13..12] BCLK1 assigned pin */ + __IOM uint32_t WS1 : 2; /*!< [15..14] WS1 assigned pin */ + __IOM uint32_t DOUT1 : 2; /*!< [17..16] DOUT1 assigned pin */ + __IOM uint32_t DIN1 : 2; /*!< [19..18] DIN1 assigned pin */ + uint32_t : 12; + } I2S_b; + } ; + + union { + __IOM uint32_t CT16B2; /*!< (@ 0x00000018) Offset:0x18 PFPA for CT16B2 Register */ + + struct { + __IOM uint32_t PWM0 : 2; /*!< [1..0] CT16B2_PWM0 assigned pin */ + __IOM uint32_t PWM1 : 2; /*!< [3..2] CT16B2_PWM1 assigned pin */ + __IOM uint32_t PWM2 : 2; /*!< [5..4] CT16B2_PWM2 assigned pin */ + __IOM uint32_t PWM3 : 2; /*!< [7..6] CT16B2_PWM3 assigned pin */ + uint32_t : 24; + } CT16B2_b; + } ; + + union { + __IOM uint32_t CT16B3; /*!< (@ 0x0000001C) Offset:0x1C PFPA for CT16B3 Register */ + + struct { + __IOM uint32_t PWM0 : 2; /*!< [1..0] CT16B3_PWM0 assigned pin */ + __IOM uint32_t PWM0N : 2; /*!< [3..2] CT16B3_PWM0N assigned pin */ + __IOM uint32_t PWM1 : 2; /*!< [5..4] CT16B3_PWM1 assigned pin */ + __IOM uint32_t PWM1N : 2; /*!< [7..6] CT16B0_PWM1N assigned pin */ + uint32_t : 24; + } CT16B3_b; + } ; + + union { + __IOM uint32_t CT16B4; /*!< (@ 0x00000020) Offset:0x20 PFPA for CT16B4 Register */ + + struct { + __IOM uint32_t PWM0 : 2; /*!< [1..0] CT16B4_PWM0 assigned pin */ + __IOM uint32_t PWM0N : 2; /*!< [3..2] CT16B4_PWM0N assigned pin */ + __IOM uint32_t PWM1 : 2; /*!< [5..4] CT16B4_PWM1 assigned pin */ + __IOM uint32_t PWM1N : 2; /*!< [7..6] CT16B4_PWM1N assigned pin */ + uint32_t : 24; + } CT16B4_b; + } ; + + union { + __IOM uint32_t CT16B5; /*!< (@ 0x00000024) Offset:0x24 PFPA for CT16B5 Register */ + + struct { + __IOM uint32_t PWM0 : 2; /*!< [1..0] CT16B5_PWM0 assigned pin */ + __IOM uint32_t PWM1 : 2; /*!< [3..2] CT16B5_PWM1 assigned pin */ + __IOM uint32_t PWM2 : 2; /*!< [5..4] CT16B5_PWM2 assigned pin */ + __IOM uint32_t PWM3 : 2; /*!< [7..6] CT16B5_PWM3 assigned pin */ + uint32_t : 24; + } CT16B5_b; + } ; +} SN_PFPA_Type; /*!< Size = 40 (0x28) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose I/O (SN_GPIO1) + */ + +typedef struct { /*!< (@ 0x40046000) SN_GPIO1 Structure */ + + union { + __IOM uint32_t DATA; /*!< (@ 0x00000000) Offset:0x00 GPIO Port n Data Register */ + + struct { + __IOM uint32_t DATA0 : 1; /*!< [0..0] Data of Pn.0 */ + __IOM uint32_t DATA1 : 1; /*!< [1..1] Data of Pn.1 */ + __IOM uint32_t DATA2 : 1; /*!< [2..2] Data of Pn.2 */ + __IOM uint32_t DATA3 : 1; /*!< [3..3] Data of Pn.3 */ + __IOM uint32_t DATA4 : 1; /*!< [4..4] Data of Pn.4 */ + __IOM uint32_t DATA5 : 1; /*!< [5..5] Data of Pn.5 */ + __IOM uint32_t DATA6 : 1; /*!< [6..6] Data of Pn.6 */ + __IOM uint32_t DATA7 : 1; /*!< [7..7] Data of Pn.7 */ + __IOM uint32_t DATA8 : 1; /*!< [8..8] Data of Pn.8 */ + __IOM uint32_t DATA9 : 1; /*!< [9..9] Data of Pn.9 */ + __IOM uint32_t DATA10 : 1; /*!< [10..10] Data of Pn.10 */ + __IOM uint32_t DATA11 : 1; /*!< [11..11] Data of Pn.11 */ + __IOM uint32_t DATA12 : 1; /*!< [12..12] Data of Pn.12 */ + __IOM uint32_t DATA13 : 1; /*!< [13..13] Data of Pn.13 */ + __IOM uint32_t DATA14 : 1; /*!< [14..14] Data of Pn.14 */ + __IOM uint32_t DATA15 : 1; /*!< [15..15] Data of Pn.15 */ + __IOM uint32_t DATA16 : 1; /*!< [16..16] Data of Pn.16 */ + __IOM uint32_t DATA17 : 1; /*!< [17..17] Data of Pn.17 */ + __IOM uint32_t DATA18 : 1; /*!< [18..18] Data of Pn.18 */ + __IOM uint32_t DATA19 : 1; /*!< [19..19] Data of Pn.19 */ + uint32_t : 12; + } DATA_b; + } ; + + union { + __IOM uint32_t MODE; /*!< (@ 0x00000004) Offset:0x04 GPIO Port n Mode Register */ + + struct { + __IOM uint32_t MODE0 : 1; /*!< [0..0] Mode of Pn.0 */ + __IOM uint32_t MODE1 : 1; /*!< [1..1] Mode of Pn.1 */ + __IOM uint32_t MODE2 : 1; /*!< [2..2] Mode of Pn.2 */ + __IOM uint32_t MODE3 : 1; /*!< [3..3] Mode of Pn.3 */ + __IOM uint32_t MODE4 : 1; /*!< [4..4] Mode of Pn.4 */ + __IOM uint32_t MODE5 : 1; /*!< [5..5] Mode of Pn.5 */ + __IOM uint32_t MODE6 : 1; /*!< [6..6] Mode of Pn.6 */ + __IOM uint32_t MODE7 : 1; /*!< [7..7] Mode of Pn.7 */ + __IOM uint32_t MODE8 : 1; /*!< [8..8] Mode of Pn.8 */ + __IOM uint32_t MODE9 : 1; /*!< [9..9] Mode of Pn.9 */ + __IOM uint32_t MODE10 : 1; /*!< [10..10] Mode of Pn.10 */ + __IOM uint32_t MODE11 : 1; /*!< [11..11] Mode of Pn.11 */ + __IOM uint32_t MODE12 : 1; /*!< [12..12] Mode of Pn.12 */ + __IOM uint32_t MODE13 : 1; /*!< [13..13] Mode of Pn.13 */ + __IOM uint32_t MODE14 : 1; /*!< [14..14] Mode of Pn.14 */ + __IOM uint32_t MODE15 : 1; /*!< [15..15] Mode of Pn.15 */ + __IOM uint32_t MODE16 : 1; /*!< [16..16] Mode of Pn.16 */ + __IOM uint32_t MODE17 : 1; /*!< [17..17] Mode of Pn.17 */ + __IOM uint32_t MODE18 : 1; /*!< [18..18] Mode of Pn.18 */ + __IOM uint32_t MODE19 : 1; /*!< [19..19] Mode of Pn.19 */ + uint32_t : 12; + } MODE_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000008) Offset:0x08 GPIO Port n Configuration Register */ + + struct { + __IOM uint32_t CFG0 : 2; /*!< [1..0] Configuration of Pn.0 */ + __IOM uint32_t CFG1 : 2; /*!< [3..2] Configuration of Pn.1 */ + __IOM uint32_t CFG2 : 2; /*!< [5..4] Configuration of Pn.2 */ + __IOM uint32_t CFG3 : 2; /*!< [7..6] Configuration of Pn.3 */ + __IOM uint32_t CFG4 : 2; /*!< [9..8] Configuration of Pn.4 */ + __IOM uint32_t CFG5 : 2; /*!< [11..10] Configuration of Pn.5 */ + __IOM uint32_t CFG6 : 2; /*!< [13..12] Configuration of Pn.6 */ + __IOM uint32_t CFG7 : 2; /*!< [15..14] Configuration of Pn.7 */ + __IOM uint32_t CFG8 : 2; /*!< [17..16] Configuration of Pn.8 */ + __IOM uint32_t CFG9 : 2; /*!< [19..18] Configuration of Pn.9 */ + __IOM uint32_t CFG10 : 2; /*!< [21..20] Configuration of Pn.10 */ + __IOM uint32_t CFG11 : 2; /*!< [23..22] Configuration of Pn.11 */ + __IOM uint32_t CFG12 : 2; /*!< [25..24] Configuration of Pn.12 */ + __IOM uint32_t CFG13 : 2; /*!< [27..26] Configuration of Pn.13 */ + __IOM uint32_t CFG14 : 2; /*!< [29..28] Configuration of Pn.14 */ + __IOM uint32_t CFG15 : 2; /*!< [31..30] Configuration of Pn.15 */ + } CFG_b; + } ; + + union { + __IOM uint32_t IS; /*!< (@ 0x0000000C) Offset:0x0C GPIO Port n Interrupt Sense Register */ + + struct { + __IOM uint32_t IS0 : 1; /*!< [0..0] Interrupt on Pn.0 is event or edge sensitive */ + __IOM uint32_t IS1 : 1; /*!< [1..1] Interrupt on Pn.1 is event or edge sensitive */ + __IOM uint32_t IS2 : 1; /*!< [2..2] Interrupt on Pn.2 is event or edge sensitive */ + __IOM uint32_t IS3 : 1; /*!< [3..3] Interrupt on Pn.3 is event or edge sensitive */ + __IOM uint32_t IS4 : 1; /*!< [4..4] Interrupt on Pn.4 is event or edge sensitive */ + __IOM uint32_t IS5 : 1; /*!< [5..5] Interrupt on Pn.5 is event or edge sensitive */ + __IOM uint32_t IS6 : 1; /*!< [6..6] Interrupt on Pn.6 is event or edge sensitive */ + __IOM uint32_t IS7 : 1; /*!< [7..7] Interrupt on Pn.7 is event or edge sensitive */ + __IOM uint32_t IS8 : 1; /*!< [8..8] Interrupt on Pn.8 is event or edge sensitive */ + __IOM uint32_t IS9 : 1; /*!< [9..9] Interrupt on Pn.9 is event or edge sensitive */ + __IOM uint32_t IS10 : 1; /*!< [10..10] Interrupt on Pn.10 is event or edge sensitive */ + __IOM uint32_t IS11 : 1; /*!< [11..11] Interrupt on Pn.11 is event or edge sensitive */ + __IOM uint32_t IS12 : 1; /*!< [12..12] Interrupt on Pn.12 is event or edge sensitive */ + __IOM uint32_t IS13 : 1; /*!< [13..13] Interrupt on Pn.13 is event or edge sensitive */ + __IOM uint32_t IS14 : 1; /*!< [14..14] Interrupt on Pn.14 is event or edge sensitive */ + __IOM uint32_t IS15 : 1; /*!< [15..15] Interrupt on Pn.15 is event or edge sensitive */ + __IOM uint32_t IS16 : 1; /*!< [16..16] Interrupt on Pn.16 is event or edge sensitive */ + __IOM uint32_t IS17 : 1; /*!< [17..17] Interrupt on Pn.17 is event or edge sensitive */ + __IOM uint32_t IS18 : 1; /*!< [18..18] Interrupt on Pn.18 is event or edge sensitive */ + __IOM uint32_t IS19 : 1; /*!< [19..19] Interrupt on Pn.19 is event or edge sensitive */ + uint32_t : 12; + } IS_b; + } ; + + union { + __IOM uint32_t IBS; /*!< (@ 0x00000010) Offset:0x10 GPIO Port n Interrupt Both-edge Sense + Register */ + + struct { + __IOM uint32_t IBS0 : 1; /*!< [0..0] Interrupt on Pn.0 is triggered ob both edges */ + __IOM uint32_t IBS1 : 1; /*!< [1..1] Interrupt on Pn.1 is triggered ob both edges */ + __IOM uint32_t IBS2 : 1; /*!< [2..2] Interrupt on Pn.2 is triggered ob both edges */ + __IOM uint32_t IBS3 : 1; /*!< [3..3] Interrupt on Pn.3 is triggered ob both edges */ + __IOM uint32_t IBS4 : 1; /*!< [4..4] Interrupt on Pn.4 is triggered ob both edges */ + __IOM uint32_t IBS5 : 1; /*!< [5..5] Interrupt on Pn.5 is triggered ob both edges */ + __IOM uint32_t IBS6 : 1; /*!< [6..6] Interrupt on Pn.6 is triggered ob both edges */ + __IOM uint32_t IBS7 : 1; /*!< [7..7] Interrupt on Pn.7 is triggered ob both edges */ + __IOM uint32_t IBS8 : 1; /*!< [8..8] Interrupt on Pn.8 is triggered ob both edges */ + __IOM uint32_t IBS9 : 1; /*!< [9..9] Interrupt on Pn.9 is triggered ob both edges */ + __IOM uint32_t IBS10 : 1; /*!< [10..10] Interrupt on Pn.10 is triggered ob both edges */ + __IOM uint32_t IBS11 : 1; /*!< [11..11] Interrupt on Pn.11 is triggered ob both edges */ + __IOM uint32_t IBS12 : 1; /*!< [12..12] Interrupt on Pn.12 is triggered ob both edges */ + __IOM uint32_t IBS13 : 1; /*!< [13..13] Interrupt on Pn.13 is triggered ob both edges */ + __IOM uint32_t IBS14 : 1; /*!< [14..14] Interrupt on Pn.14 is triggered ob both edges */ + __IOM uint32_t IBS15 : 1; /*!< [15..15] Interrupt on Pn.15 is triggered ob both edges */ + __IOM uint32_t IBS16 : 1; /*!< [16..16] Interrupt on Pn.16 is triggered ob both edges */ + __IOM uint32_t IBS17 : 1; /*!< [17..17] Interrupt on Pn.17 is triggered ob both edges */ + __IOM uint32_t IBS18 : 1; /*!< [18..18] Interrupt on Pn.18 is triggered ob both edges */ + __IOM uint32_t IBS19 : 1; /*!< [19..19] Interrupt on Pn.19 is triggered ob both edges */ + uint32_t : 12; + } IBS_b; + } ; + + union { + __IOM uint32_t IEV; /*!< (@ 0x00000014) Offset:0x14 GPIO Port n Interrupt Event Register */ + + struct { + __IOM uint32_t IEV0 : 1; /*!< [0..0] Interrupt trigged evnet on Pn.0 */ + __IOM uint32_t IEV1 : 1; /*!< [1..1] Interrupt trigged evnet on Pn.1 */ + __IOM uint32_t IEV2 : 1; /*!< [2..2] Interrupt trigged evnet on Pn.2 */ + __IOM uint32_t IEV3 : 1; /*!< [3..3] Interrupt trigged evnet on Pn.3 */ + __IOM uint32_t IEV4 : 1; /*!< [4..4] Interrupt trigged evnet on Pn.4 */ + __IOM uint32_t IEV5 : 1; /*!< [5..5] Interrupt trigged evnet on Pn.5 */ + __IOM uint32_t IEV6 : 1; /*!< [6..6] Interrupt trigged evnet on Pn.6 */ + __IOM uint32_t IEV7 : 1; /*!< [7..7] Interrupt trigged evnet on Pn.7 */ + __IOM uint32_t IEV8 : 1; /*!< [8..8] Interrupt trigged evnet on Pn.8 */ + __IOM uint32_t IEV9 : 1; /*!< [9..9] Interrupt trigged evnet on Pn.9 */ + __IOM uint32_t IEV10 : 1; /*!< [10..10] Interrupt trigged evnet on Pn.10 */ + __IOM uint32_t IEV11 : 1; /*!< [11..11] Interrupt trigged evnet on Pn.11 */ + __IOM uint32_t IEV12 : 1; /*!< [12..12] Interrupt trigged evnet on Pn.12 */ + __IOM uint32_t IEV13 : 1; /*!< [13..13] Interrupt trigged evnet on Pn.13 */ + __IOM uint32_t IEV14 : 1; /*!< [14..14] Interrupt trigged evnet on Pn.14 */ + __IOM uint32_t IEV15 : 1; /*!< [15..15] Interrupt trigged evnet on Pn.15 */ + __IOM uint32_t IEV16 : 1; /*!< [16..16] Interrupt trigged evnet on Pn.16 */ + __IOM uint32_t IEV17 : 1; /*!< [17..17] Interrupt trigged evnet on Pn.17 */ + __IOM uint32_t IEV18 : 1; /*!< [18..18] Interrupt trigged evnet on Pn.18 */ + __IOM uint32_t IEV19 : 1; /*!< [19..19] Interrupt trigged evnet on Pn.19 */ + uint32_t : 12; + } IEV_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000018) Offset:0x18 GPIO Port n Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] Interrupt on Pn.0 enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] Interrupt on Pn.1 enable */ + __IOM uint32_t IE2 : 1; /*!< [2..2] Interrupt on Pn.2 enable */ + __IOM uint32_t IE3 : 1; /*!< [3..3] Interrupt on Pn.3 enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] Interrupt on Pn.4 enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] Interrupt on Pn.5 enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] Interrupt on Pn.6 enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] Interrupt on Pn.7 enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] Interrupt on Pn.8 enable */ + __IOM uint32_t IE9 : 1; /*!< [9..9] Interrupt on Pn.9 enable */ + __IOM uint32_t IE10 : 1; /*!< [10..10] Interrupt on Pn.10 enable */ + __IOM uint32_t IE11 : 1; /*!< [11..11] Interrupt on Pn.11 enable */ + __IOM uint32_t IE12 : 1; /*!< [12..12] Interrupt on Pn.11 enable */ + __IOM uint32_t IE13 : 1; /*!< [13..13] Interrupt on Pn.13 enable */ + __IOM uint32_t IE14 : 1; /*!< [14..14] Interrupt on Pn.14 enable */ + __IOM uint32_t IE15 : 1; /*!< [15..15] Interrupt on Pn.15 enable */ + __IOM uint32_t IE16 : 1; /*!< [16..16] Interrupt on Pn.16 enable */ + __IOM uint32_t IE17 : 1; /*!< [17..17] Interrupt on Pn.17 enable */ + __IOM uint32_t IE18 : 1; /*!< [18..18] Interrupt on Pn.18 enable */ + __IOM uint32_t IE19 : 1; /*!< [19..19] Interrupt on Pn.19 enable */ + uint32_t : 12; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x0000001C) Offset:0x1C GPIO Port n Raw Interrupt Status + Register */ + + struct { + __IM uint32_t IF0 : 1; /*!< [0..0] Pn.0 raw interrupt flag */ + __IM uint32_t IF1 : 1; /*!< [1..1] Pn.1 raw interrupt flag */ + __IM uint32_t IF2 : 1; /*!< [2..2] Pn.2 raw interrupt flag */ + __IM uint32_t IF3 : 1; /*!< [3..3] Pn.3 raw interrupt flag */ + __IM uint32_t IF4 : 1; /*!< [4..4] Pn.4 raw interrupt flag */ + __IM uint32_t IF5 : 1; /*!< [5..5] Pn.5 raw interrupt flag */ + __IM uint32_t IF6 : 1; /*!< [6..6] Pn.6 raw interrupt flag */ + __IM uint32_t IF7 : 1; /*!< [7..7] Pn.7 raw interrupt flag */ + __IM uint32_t IF8 : 1; /*!< [8..8] Pn.8 raw interrupt flag */ + __IM uint32_t IF9 : 1; /*!< [9..9] Pn.9 raw interrupt flag */ + __IM uint32_t IF10 : 1; /*!< [10..10] Pn.10 raw interrupt flag */ + __IM uint32_t IF11 : 1; /*!< [11..11] Pn.11 raw interrupt flag */ + __IM uint32_t IF12 : 1; /*!< [12..12] Pn.12 raw interrupt flag */ + __IM uint32_t IF13 : 1; /*!< [13..13] Pn.13 raw interrupt flag */ + __IM uint32_t IF14 : 1; /*!< [14..14] Pn.14 raw interrupt flag */ + __IM uint32_t IF15 : 1; /*!< [15..15] Pn.15 raw interrupt flag */ + __IM uint32_t IF16 : 1; /*!< [16..16] Pn.16 raw interrupt flag */ + __IM uint32_t IF17 : 1; /*!< [17..17] Pn.17 raw interrupt flag */ + __IM uint32_t IF18 : 1; /*!< [18..18] Pn.18 raw interrupt flag */ + __IM uint32_t IF19 : 1; /*!< [19..19] Pn.19 raw interrupt flag */ + uint32_t : 12; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000020) Offset:0x20 GPIO Port n Interrupt Clear Register */ + + struct { + __OM uint32_t IC0 : 1; /*!< [0..0] Pn.0 interrupt flag clear */ + __OM uint32_t IC1 : 1; /*!< [1..1] Pn.1 interrupt flag clear */ + __OM uint32_t IC2 : 1; /*!< [2..2] Pn.2 interrupt flag clear */ + __OM uint32_t IC3 : 1; /*!< [3..3] Pn.3 interrupt flag clear */ + __OM uint32_t IC4 : 1; /*!< [4..4] Pn.4 interrupt flag clear */ + __OM uint32_t IC5 : 1; /*!< [5..5] Pn.5 interrupt flag clear */ + __OM uint32_t IC6 : 1; /*!< [6..6] Pn.6 interrupt flag clear */ + __OM uint32_t IC7 : 1; /*!< [7..7] Pn.7 interrupt flag clear */ + __OM uint32_t IC8 : 1; /*!< [8..8] Pn.8 interrupt flag clear */ + __OM uint32_t IC9 : 1; /*!< [9..9] Pn.9 interrupt flag clear */ + __OM uint32_t IC10 : 1; /*!< [10..10] Pn.10 interrupt flag clear */ + __OM uint32_t IC11 : 1; /*!< [11..11] Pn.11 interrupt flag clear */ + __OM uint32_t IC12 : 1; /*!< [12..12] Pn.12 interrupt flag clear */ + __OM uint32_t IC13 : 1; /*!< [13..13] Pn.13 interrupt flag clear */ + __OM uint32_t IC14 : 1; /*!< [14..14] Pn.14 interrupt flag clear */ + __OM uint32_t IC15 : 1; /*!< [15..15] Pn.15 interrupt flag clear */ + __OM uint32_t IC16 : 1; /*!< [16..16] Pn.16 interrupt flag clear */ + __OM uint32_t IC17 : 1; /*!< [17..17] Pn.17 interrupt flag clear */ + __OM uint32_t IC18 : 1; /*!< [18..18] Pn.18 interrupt flag clear */ + __OM uint32_t IC19 : 1; /*!< [19..19] Pn.19 interrupt flag clear */ + uint32_t : 12; + } IC_b; + } ; + + union { + __OM uint32_t BSET; /*!< (@ 0x00000024) Offset:0x24 GPIO Port n Bits Set Operation Register */ + + struct { + __OM uint32_t BSET0 : 1; /*!< [0..0] Set Pn.0 */ + __OM uint32_t BSET1 : 1; /*!< [1..1] Set Pn.1 */ + __OM uint32_t BSET2 : 1; /*!< [2..2] Set Pn.2 */ + __OM uint32_t BSET3 : 1; /*!< [3..3] Set Pn.3 */ + __OM uint32_t BSET4 : 1; /*!< [4..4] Set Pn.4 */ + __OM uint32_t BSET5 : 1; /*!< [5..5] Set Pn.5 */ + __OM uint32_t BSET6 : 1; /*!< [6..6] Set Pn.6 */ + __OM uint32_t BSET7 : 1; /*!< [7..7] Set Pn.7 */ + __OM uint32_t BSET8 : 1; /*!< [8..8] Set Pn.8 */ + __OM uint32_t BSET9 : 1; /*!< [9..9] Set Pn.9 */ + __OM uint32_t BSET10 : 1; /*!< [10..10] Set Pn.10 */ + __OM uint32_t BSET11 : 1; /*!< [11..11] Set Pn.11 */ + __OM uint32_t BSET12 : 1; /*!< [12..12] Set Pn.12 */ + __OM uint32_t BSET13 : 1; /*!< [13..13] Set Pn.13 */ + __OM uint32_t BSET14 : 1; /*!< [14..14] Set Pn.14 */ + __OM uint32_t BSET15 : 1; /*!< [15..15] Set Pn.15 */ + __OM uint32_t BSET16 : 1; /*!< [16..16] Set Pn.16 */ + __OM uint32_t BSET17 : 1; /*!< [17..17] Set Pn.17 */ + __OM uint32_t BSET18 : 1; /*!< [18..18] Set Pn.18 */ + __OM uint32_t BSET19 : 1; /*!< [19..19] Set Pn.19 */ + uint32_t : 12; + } BSET_b; + } ; + + union { + __OM uint32_t BCLR; /*!< (@ 0x00000028) Offset:0x28 GPIO Port n Bits Clear Operation + Register */ + + struct { + __OM uint32_t BCLR0 : 1; /*!< [0..0] Clear Pn.0 */ + __OM uint32_t BCLR1 : 1; /*!< [1..1] Clear Pn.1 */ + __OM uint32_t BCLR2 : 1; /*!< [2..2] Clear Pn.2 */ + __OM uint32_t BCLR3 : 1; /*!< [3..3] Clear Pn.3 */ + __OM uint32_t BCLR4 : 1; /*!< [4..4] Clear Pn.4 */ + __OM uint32_t BCLR5 : 1; /*!< [5..5] Clear Pn.5 */ + __OM uint32_t BCLR6 : 1; /*!< [6..6] Clear Pn.6 */ + __OM uint32_t BCLR7 : 1; /*!< [7..7] Clear Pn.7 */ + __OM uint32_t BCLR8 : 1; /*!< [8..8] Clear Pn.8 */ + __OM uint32_t BCLR9 : 1; /*!< [9..9] Clear Pn.9 */ + __OM uint32_t BCLR10 : 1; /*!< [10..10] Clear Pn.10 */ + __OM uint32_t BCLR11 : 1; /*!< [11..11] Clear Pn.11 */ + __OM uint32_t BCLR12 : 1; /*!< [12..12] Clear Pn.12 */ + __OM uint32_t BCLR13 : 1; /*!< [13..13] Clear Pn.13 */ + __OM uint32_t BCLR14 : 1; /*!< [14..14] Clear Pn.14 */ + __OM uint32_t BCLR15 : 1; /*!< [15..15] Clear Pn.15 */ + __OM uint32_t BCLR16 : 1; /*!< [16..16] Clear Pn.16 */ + __OM uint32_t BCLR17 : 1; /*!< [17..17] Clear Pn.17 */ + __OM uint32_t BCLR18 : 1; /*!< [18..18] Clear Pn.18 */ + __OM uint32_t BCLR19 : 1; /*!< [19..19] Clear Pn.19 */ + uint32_t : 12; + } BCLR_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t CFG1; /*!< (@ 0x00000030) Offset:0x30 GPIO Port n Configuration Register + 1 */ + + struct { + __IOM uint32_t CFG16 : 2; /*!< [1..0] Configuration of Pn.16 */ + __IOM uint32_t CFG17 : 2; /*!< [3..2] Configuration of Pn.17 */ + __IOM uint32_t CFG18 : 2; /*!< [5..4] Configuration of Pn.18 */ + __IOM uint32_t CFG19 : 2; /*!< [7..6] Configuration of Pn.19 */ + uint32_t : 24; + } CFG1_b; + } ; +} SN_GPIO1_Type; /*!< Size = 52 (0x34) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO2 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose I/O (SN_GPIO2) + */ + +typedef struct { /*!< (@ 0x40048000) SN_GPIO2 Structure */ + + union { + __IOM uint32_t DATA; /*!< (@ 0x00000000) Offset:0x00 GPIO Port n Data Register */ + + struct { + __IOM uint32_t DATA0 : 1; /*!< [0..0] Data of Pn.0 */ + __IOM uint32_t DATA1 : 1; /*!< [1..1] Data of Pn.1 */ + __IOM uint32_t DATA2 : 1; /*!< [2..2] Data of Pn.2 */ + __IOM uint32_t DATA3 : 1; /*!< [3..3] Data of Pn.3 */ + __IOM uint32_t DATA4 : 1; /*!< [4..4] Data of Pn.4 */ + __IOM uint32_t DATA5 : 1; /*!< [5..5] Data of Pn.5 */ + __IOM uint32_t DATA6 : 1; /*!< [6..6] Data of Pn.6 */ + __IOM uint32_t DATA7 : 1; /*!< [7..7] Data of Pn.7 */ + __IOM uint32_t DATA8 : 1; /*!< [8..8] Data of Pn.8 */ + __IOM uint32_t DATA9 : 1; /*!< [9..9] Data of Pn.9 */ + __IOM uint32_t DATA10 : 1; /*!< [10..10] Data of Pn.10 */ + __IOM uint32_t DATA11 : 1; /*!< [11..11] Data of Pn.11 */ + __IOM uint32_t DATA12 : 1; /*!< [12..12] Data of Pn.12 */ + __IOM uint32_t DATA13 : 1; /*!< [13..13] Data of Pn.13 */ + __IOM uint32_t DATA14 : 1; /*!< [14..14] Data of Pn.14 */ + __IOM uint32_t DATA15 : 1; /*!< [15..15] Data of Pn.15 */ + uint32_t : 16; + } DATA_b; + } ; + + union { + __IOM uint32_t MODE; /*!< (@ 0x00000004) Offset:0x04 GPIO Port n Mode Register */ + + struct { + __IOM uint32_t MODE0 : 1; /*!< [0..0] Mode of Pn.0 */ + __IOM uint32_t MODE1 : 1; /*!< [1..1] Mode of Pn.1 */ + __IOM uint32_t MODE2 : 1; /*!< [2..2] Mode of Pn.2 */ + __IOM uint32_t MODE3 : 1; /*!< [3..3] Mode of Pn.3 */ + __IOM uint32_t MODE4 : 1; /*!< [4..4] Mode of Pn.4 */ + __IOM uint32_t MODE5 : 1; /*!< [5..5] Mode of Pn.5 */ + __IOM uint32_t MODE6 : 1; /*!< [6..6] Mode of Pn.6 */ + __IOM uint32_t MODE7 : 1; /*!< [7..7] Mode of Pn.7 */ + __IOM uint32_t MODE8 : 1; /*!< [8..8] Mode of Pn.8 */ + __IOM uint32_t MODE9 : 1; /*!< [9..9] Mode of Pn.9 */ + __IOM uint32_t MODE10 : 1; /*!< [10..10] Mode of Pn.10 */ + __IOM uint32_t MODE11 : 1; /*!< [11..11] Mode of Pn.11 */ + __IOM uint32_t MODE12 : 1; /*!< [12..12] Mode of Pn.12 */ + __IOM uint32_t MODE13 : 1; /*!< [13..13] Mode of Pn.13 */ + __IOM uint32_t MODE14 : 1; /*!< [14..14] Mode of Pn.14 */ + __IOM uint32_t MODE15 : 1; /*!< [15..15] Mode of Pn.15 */ + uint32_t : 16; + } MODE_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000008) Offset:0x08 GPIO Port n Configuration Register */ + + struct { + __IOM uint32_t CFG0 : 2; /*!< [1..0] Configuration of Pn.0 */ + __IOM uint32_t CFG1 : 2; /*!< [3..2] Configuration of Pn.1 */ + __IOM uint32_t CFG2 : 2; /*!< [5..4] Configuration of Pn.2 */ + __IOM uint32_t CFG3 : 2; /*!< [7..6] Configuration of Pn.3 */ + __IOM uint32_t CFG4 : 2; /*!< [9..8] Configuration of Pn.4 */ + __IOM uint32_t CFG5 : 2; /*!< [11..10] Configuration of Pn.5 */ + __IOM uint32_t CFG6 : 2; /*!< [13..12] Configuration of Pn.6 */ + __IOM uint32_t CFG7 : 2; /*!< [15..14] Configuration of Pn.7 */ + __IOM uint32_t CFG8 : 2; /*!< [17..16] Configuration of Pn.8 */ + __IOM uint32_t CFG9 : 2; /*!< [19..18] Configuration of Pn.9 */ + __IOM uint32_t CFG10 : 2; /*!< [21..20] Configuration of Pn.10 */ + __IOM uint32_t CFG11 : 2; /*!< [23..22] Configuration of Pn.11 */ + __IOM uint32_t CFG12 : 2; /*!< [25..24] Configuration of Pn.12 */ + __IOM uint32_t CFG13 : 2; /*!< [27..26] Configuration of Pn.13 */ + __IOM uint32_t CFG14 : 2; /*!< [29..28] Configuration of Pn.14 */ + __IOM uint32_t CFG15 : 2; /*!< [31..30] Configuration of Pn.15 */ + } CFG_b; + } ; + + union { + __IOM uint32_t IS; /*!< (@ 0x0000000C) Offset:0x0C GPIO Port n Interrupt Sense Register */ + + struct { + __IOM uint32_t IS0 : 1; /*!< [0..0] Interrupt on Pn.0 is event or edge sensitive */ + __IOM uint32_t IS1 : 1; /*!< [1..1] Interrupt on Pn.1 is event or edge sensitive */ + __IOM uint32_t IS2 : 1; /*!< [2..2] Interrupt on Pn.2 is event or edge sensitive */ + __IOM uint32_t IS3 : 1; /*!< [3..3] Interrupt on Pn.3 is event or edge sensitive */ + __IOM uint32_t IS4 : 1; /*!< [4..4] Interrupt on Pn.4 is event or edge sensitive */ + __IOM uint32_t IS5 : 1; /*!< [5..5] Interrupt on Pn.5 is event or edge sensitive */ + __IOM uint32_t IS6 : 1; /*!< [6..6] Interrupt on Pn.6 is event or edge sensitive */ + __IOM uint32_t IS7 : 1; /*!< [7..7] Interrupt on Pn.7 is event or edge sensitive */ + __IOM uint32_t IS8 : 1; /*!< [8..8] Interrupt on Pn.8 is event or edge sensitive */ + __IOM uint32_t IS9 : 1; /*!< [9..9] Interrupt on Pn.9 is event or edge sensitive */ + __IOM uint32_t IS10 : 1; /*!< [10..10] Interrupt on Pn.10 is event or edge sensitive */ + __IOM uint32_t IS11 : 1; /*!< [11..11] Interrupt on Pn.11 is event or edge sensitive */ + __IOM uint32_t IS12 : 1; /*!< [12..12] Interrupt on Pn.12 is event or edge sensitive */ + __IOM uint32_t IS13 : 1; /*!< [13..13] Interrupt on Pn.13 is event or edge sensitive */ + __IOM uint32_t IS14 : 1; /*!< [14..14] Interrupt on Pn.14 is event or edge sensitive */ + __IOM uint32_t IS15 : 1; /*!< [15..15] Interrupt on Pn.15 is event or edge sensitive */ + uint32_t : 16; + } IS_b; + } ; + + union { + __IOM uint32_t IBS; /*!< (@ 0x00000010) Offset:0x10 GPIO Port n Interrupt Both-edge Sense + Register */ + + struct { + __IOM uint32_t IBS0 : 1; /*!< [0..0] Interrupt on Pn.0 is triggered ob both edges */ + __IOM uint32_t IBS1 : 1; /*!< [1..1] Interrupt on Pn.1 is triggered ob both edges */ + __IOM uint32_t IBS2 : 1; /*!< [2..2] Interrupt on Pn.2 is triggered ob both edges */ + __IOM uint32_t IBS3 : 1; /*!< [3..3] Interrupt on Pn.3 is triggered ob both edges */ + __IOM uint32_t IBS4 : 1; /*!< [4..4] Interrupt on Pn.4 is triggered ob both edges */ + __IOM uint32_t IBS5 : 1; /*!< [5..5] Interrupt on Pn.5 is triggered ob both edges */ + __IOM uint32_t IBS6 : 1; /*!< [6..6] Interrupt on Pn.6 is triggered ob both edges */ + __IOM uint32_t IBS7 : 1; /*!< [7..7] Interrupt on Pn.7 is triggered ob both edges */ + __IOM uint32_t IBS8 : 1; /*!< [8..8] Interrupt on Pn.8 is triggered ob both edges */ + __IOM uint32_t IBS9 : 1; /*!< [9..9] Interrupt on Pn.9 is triggered ob both edges */ + __IOM uint32_t IBS10 : 1; /*!< [10..10] Interrupt on Pn.10 is triggered ob both edges */ + __IOM uint32_t IBS11 : 1; /*!< [11..11] Interrupt on Pn.11 is triggered ob both edges */ + __IOM uint32_t IBS12 : 1; /*!< [12..12] Interrupt on Pn.12 is triggered ob both edges */ + __IOM uint32_t IBS13 : 1; /*!< [13..13] Interrupt on Pn.13 is triggered ob both edges */ + __IOM uint32_t IBS14 : 1; /*!< [14..14] Interrupt on Pn.14 is triggered ob both edges */ + __IOM uint32_t IBS15 : 1; /*!< [15..15] Interrupt on Pn.15 is triggered ob both edges */ + uint32_t : 16; + } IBS_b; + } ; + + union { + __IOM uint32_t IEV; /*!< (@ 0x00000014) Offset:0x14 GPIO Port n Interrupt Event Register */ + + struct { + __IOM uint32_t IEV0 : 1; /*!< [0..0] Interrupt trigged evnet on Pn.0 */ + __IOM uint32_t IEV1 : 1; /*!< [1..1] Interrupt trigged evnet on Pn.1 */ + __IOM uint32_t IEV2 : 1; /*!< [2..2] Interrupt trigged evnet on Pn.2 */ + __IOM uint32_t IEV3 : 1; /*!< [3..3] Interrupt trigged evnet on Pn.3 */ + __IOM uint32_t IEV4 : 1; /*!< [4..4] Interrupt trigged evnet on Pn.4 */ + __IOM uint32_t IEV5 : 1; /*!< [5..5] Interrupt trigged evnet on Pn.5 */ + __IOM uint32_t IEV6 : 1; /*!< [6..6] Interrupt trigged evnet on Pn.6 */ + __IOM uint32_t IEV7 : 1; /*!< [7..7] Interrupt trigged evnet on Pn.7 */ + __IOM uint32_t IEV8 : 1; /*!< [8..8] Interrupt trigged evnet on Pn.8 */ + __IOM uint32_t IEV9 : 1; /*!< [9..9] Interrupt trigged evnet on Pn.9 */ + __IOM uint32_t IEV10 : 1; /*!< [10..10] Interrupt trigged evnet on Pn.10 */ + __IOM uint32_t IEV11 : 1; /*!< [11..11] Interrupt trigged evnet on Pn.11 */ + __IOM uint32_t IEV12 : 1; /*!< [12..12] Interrupt trigged evnet on Pn.12 */ + __IOM uint32_t IEV13 : 1; /*!< [13..13] Interrupt trigged evnet on Pn.13 */ + __IOM uint32_t IEV14 : 1; /*!< [14..14] Interrupt trigged evnet on Pn.14 */ + __IOM uint32_t IEV15 : 1; /*!< [15..15] Interrupt trigged evnet on Pn.15 */ + uint32_t : 16; + } IEV_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000018) Offset:0x18 GPIO Port n Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] Interrupt on Pn.0 enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] Interrupt on Pn.1 enable */ + __IOM uint32_t IE2 : 1; /*!< [2..2] Interrupt on Pn.2 enable */ + __IOM uint32_t IE3 : 1; /*!< [3..3] Interrupt on Pn.3 enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] Interrupt on Pn.4 enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] Interrupt on Pn.5 enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] Interrupt on Pn.6 enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] Interrupt on Pn.7 enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] Interrupt on Pn.8 enable */ + __IOM uint32_t IE9 : 1; /*!< [9..9] Interrupt on Pn.9 enable */ + __IOM uint32_t IE10 : 1; /*!< [10..10] Interrupt on Pn.10 enable */ + __IOM uint32_t IE11 : 1; /*!< [11..11] Interrupt on Pn.11 enable */ + __IOM uint32_t IE12 : 1; /*!< [12..12] Interrupt on Pn.11 enable */ + __IOM uint32_t IE13 : 1; /*!< [13..13] Interrupt on Pn.13 enable */ + __IOM uint32_t IE14 : 1; /*!< [14..14] Interrupt on Pn.14 enable */ + __IOM uint32_t IE15 : 1; /*!< [15..15] Interrupt on Pn.15 enable */ + uint32_t : 16; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x0000001C) Offset:0x1C GPIO Port n Raw Interrupt Status + Register */ + + struct { + __IM uint32_t IF0 : 1; /*!< [0..0] Pn.0 raw interrupt flag */ + __IM uint32_t IF1 : 1; /*!< [1..1] Pn.1 raw interrupt flag */ + __IM uint32_t IF2 : 1; /*!< [2..2] Pn.2 raw interrupt flag */ + __IM uint32_t IF3 : 1; /*!< [3..3] Pn.3 raw interrupt flag */ + __IM uint32_t IF4 : 1; /*!< [4..4] Pn.4 raw interrupt flag */ + __IM uint32_t IF5 : 1; /*!< [5..5] Pn.5 raw interrupt flag */ + __IM uint32_t IF6 : 1; /*!< [6..6] Pn.6 raw interrupt flag */ + __IM uint32_t IF7 : 1; /*!< [7..7] Pn.7 raw interrupt flag */ + __IM uint32_t IF8 : 1; /*!< [8..8] Pn.8 raw interrupt flag */ + __IM uint32_t IF9 : 1; /*!< [9..9] Pn.9 raw interrupt flag */ + __IM uint32_t IF10 : 1; /*!< [10..10] Pn.10 raw interrupt flag */ + __IM uint32_t IF11 : 1; /*!< [11..11] Pn.11 raw interrupt flag */ + __IM uint32_t IF12 : 1; /*!< [12..12] Pn.12 raw interrupt flag */ + __IM uint32_t IF13 : 1; /*!< [13..13] Pn.13 raw interrupt flag */ + __IM uint32_t IF14 : 1; /*!< [14..14] Pn.14 raw interrupt flag */ + __IM uint32_t IF15 : 1; /*!< [15..15] Pn.15 raw interrupt flag */ + uint32_t : 16; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000020) Offset:0x20 GPIO Port n Interrupt Clear Register */ + + struct { + __OM uint32_t IC0 : 1; /*!< [0..0] Pn.0 interrupt flag clear */ + __OM uint32_t IC1 : 1; /*!< [1..1] Pn.1 interrupt flag clear */ + __OM uint32_t IC2 : 1; /*!< [2..2] Pn.2 interrupt flag clear */ + __OM uint32_t IC3 : 1; /*!< [3..3] Pn.3 interrupt flag clear */ + __OM uint32_t IC4 : 1; /*!< [4..4] Pn.4 interrupt flag clear */ + __OM uint32_t IC5 : 1; /*!< [5..5] Pn.5 interrupt flag clear */ + __OM uint32_t IC6 : 1; /*!< [6..6] Pn.6 interrupt flag clear */ + __OM uint32_t IC7 : 1; /*!< [7..7] Pn.7 interrupt flag clear */ + __OM uint32_t IC8 : 1; /*!< [8..8] Pn.8 interrupt flag clear */ + __OM uint32_t IC9 : 1; /*!< [9..9] Pn.9 interrupt flag clear */ + __OM uint32_t IC10 : 1; /*!< [10..10] Pn.10 interrupt flag clear */ + __OM uint32_t IC11 : 1; /*!< [11..11] Pn.11 interrupt flag clear */ + __OM uint32_t IC12 : 1; /*!< [12..12] Pn.12 interrupt flag clear */ + __OM uint32_t IC13 : 1; /*!< [13..13] Pn.13 interrupt flag clear */ + __OM uint32_t IC14 : 1; /*!< [14..14] Pn.14 interrupt flag clear */ + __OM uint32_t IC15 : 1; /*!< [15..15] Pn.15 interrupt flag clear */ + uint32_t : 16; + } IC_b; + } ; + + union { + __OM uint32_t BSET; /*!< (@ 0x00000024) Offset:0x24 GPIO Port n Bits Set Operation Register */ + + struct { + __OM uint32_t BSET0 : 1; /*!< [0..0] Set Pn.0 */ + __OM uint32_t BSET1 : 1; /*!< [1..1] Set Pn.1 */ + __OM uint32_t BSET2 : 1; /*!< [2..2] Set Pn.2 */ + __OM uint32_t BSET3 : 1; /*!< [3..3] Set Pn.3 */ + __OM uint32_t BSET4 : 1; /*!< [4..4] Set Pn.4 */ + __OM uint32_t BSET5 : 1; /*!< [5..5] Set Pn.5 */ + __OM uint32_t BSET6 : 1; /*!< [6..6] Set Pn.6 */ + __OM uint32_t BSET7 : 1; /*!< [7..7] Set Pn.7 */ + __OM uint32_t BSET8 : 1; /*!< [8..8] Set Pn.8 */ + __OM uint32_t BSET9 : 1; /*!< [9..9] Set Pn.9 */ + __OM uint32_t BSET10 : 1; /*!< [10..10] Set Pn.10 */ + __OM uint32_t BSET11 : 1; /*!< [11..11] Set Pn.11 */ + __OM uint32_t BSET12 : 1; /*!< [12..12] Set Pn.12 */ + __OM uint32_t BSET13 : 1; /*!< [13..13] Set Pn.13 */ + __OM uint32_t BSET14 : 1; /*!< [14..14] Set Pn.14 */ + __OM uint32_t BSET15 : 1; /*!< [15..15] Set Pn.15 */ + uint32_t : 16; + } BSET_b; + } ; + + union { + __OM uint32_t BCLR; /*!< (@ 0x00000028) Offset:0x28 GPIO Port n Bits Clear Operation + Register */ + + struct { + __OM uint32_t BCLR0 : 1; /*!< [0..0] Clear Pn.0 */ + __OM uint32_t BCLR1 : 1; /*!< [1..1] Clear Pn.1 */ + __OM uint32_t BCLR2 : 1; /*!< [2..2] Clear Pn.2 */ + __OM uint32_t BCLR3 : 1; /*!< [3..3] Clear Pn.3 */ + __OM uint32_t BCLR4 : 1; /*!< [4..4] Clear Pn.4 */ + __OM uint32_t BCLR5 : 1; /*!< [5..5] Clear Pn.5 */ + __OM uint32_t BCLR6 : 1; /*!< [6..6] Clear Pn.6 */ + __OM uint32_t BCLR7 : 1; /*!< [7..7] Clear Pn.7 */ + __OM uint32_t BCLR8 : 1; /*!< [8..8] Clear Pn.8 */ + __OM uint32_t BCLR9 : 1; /*!< [9..9] Clear Pn.9 */ + __OM uint32_t BCLR10 : 1; /*!< [10..10] Clear Pn.10 */ + __OM uint32_t BCLR11 : 1; /*!< [11..11] Clear Pn.11 */ + __OM uint32_t BCLR12 : 1; /*!< [12..12] Clear Pn.12 */ + __OM uint32_t BCLR13 : 1; /*!< [13..13] Clear Pn.13 */ + __OM uint32_t BCLR14 : 1; /*!< [14..14] Clear Pn.14 */ + __OM uint32_t BCLR15 : 1; /*!< [15..15] Clear Pn.15 */ + uint32_t : 16; + } BCLR_b; + } ; +} SN_GPIO2_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ADC (SN_ADC) + */ + +typedef struct { /*!< (@ 0x40026000) SN_ADC Structure */ + + union { + __IOM uint32_t ADM; /*!< (@ 0x00000000) Offset:0x00 ADC Management Register */ + + struct { + __IOM uint32_t CHS : 5; /*!< [4..0] ADC input channel */ + __IOM uint32_t GCHS : 1; /*!< [5..5] ADC global channel enable */ + __IOM uint32_t EOC : 1; /*!< [6..6] ADC status */ + __IOM uint32_t ADS : 1; /*!< [7..7] ADC start control */ + __IOM uint32_t ADLEN : 1; /*!< [8..8] ADC resolution */ + __IOM uint32_t ADCKS : 3; /*!< [11..9] ADC clock source divider */ + __IOM uint32_t ADENB : 1; /*!< [12..12] ADC enable */ + __IOM uint32_t AVREFHSEL : 1; /*!< [13..13] ADC high reference voltage source */ + __IOM uint32_t VHS : 3; /*!< [16..14] Internal Ref. voltage source */ + uint32_t : 15; + } ADM_b; + } ; + + union { + __IM uint32_t ADB; /*!< (@ 0x00000004) Offset:0x04 ADC Data Register */ + + struct { + __IM uint32_t ADB : 12; /*!< [11..0] ADB11~ADB4 bits for 8-bit ADC, ADB11~ADB0 bits for 12-bit + ADC */ + uint32_t : 20; + } ADB_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t IE; /*!< (@ 0x0000000C) Offset:0x0C ADC Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] AIN0 interrupt enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] AIN1 interrupt enable */ + __IOM uint32_t IE2 : 1; /*!< [2..2] AIN2 interrupt enable */ + __IOM uint32_t IE3 : 1; /*!< [3..3] AIN3 interrupt enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] AIN4 interrupt enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] AIN5 interrupt enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] AIN6 interrupt enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] AIN7 interrupt enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] AIN8 interrupt enable */ + __IOM uint32_t IE9 : 1; /*!< [9..9] AIN9 interrupt enable */ + __IOM uint32_t IE10 : 1; /*!< [10..10] AIN10 interrupt enable */ + __IOM uint32_t IE11 : 1; /*!< [11..11] AIN11 interrupt enable */ + __IOM uint32_t IE12 : 1; /*!< [12..12] AIN12 interrupt enable */ + __IOM uint32_t IE13 : 1; /*!< [13..13] AIN13 interrupt enable */ + __IOM uint32_t IE14 : 1; /*!< [14..14] AIN14 interrupt enable */ + __IOM uint32_t IE15 : 1; /*!< [15..15] AIN15 interrupt enable */ + __IOM uint32_t IE16 : 1; /*!< [16..16] AIN16 interrupt enable */ + __IOM uint32_t IE17 : 1; /*!< [17..17] AIN17 interrupt enable */ + __IOM uint32_t IE18 : 1; /*!< [18..18] AIN18 interrupt enable */ + uint32_t : 13; + } IE_b; + } ; + + union { + __IOM uint32_t RIS; /*!< (@ 0x00000010) Offset:0x10 ADC Raw Interrupt Status Register */ + + struct { + __IOM uint32_t EOCIF0 : 1; /*!< [0..0] AIN0 interrupt flag */ + __IOM uint32_t EOCIF1 : 1; /*!< [1..1] AIN1 interrupt flag */ + __IOM uint32_t EOCIF2 : 1; /*!< [2..2] AIN2 interrupt flag */ + __IOM uint32_t EOCIF3 : 1; /*!< [3..3] AIN0 interrupt flag */ + __IOM uint32_t EOCIF4 : 1; /*!< [4..4] AIN4 interrupt flag */ + __IOM uint32_t EOCIF5 : 1; /*!< [5..5] AIN5 interrupt flag */ + __IOM uint32_t EOCIF6 : 1; /*!< [6..6] AIN6 interrupt flag */ + __IOM uint32_t EOCIF7 : 1; /*!< [7..7] AIN7 interrupt flag */ + __IOM uint32_t EOCIF8 : 1; /*!< [8..8] AIN8 interrupt flag */ + __IOM uint32_t EOCIF9 : 1; /*!< [9..9] AIN9 interrupt flag */ + __IOM uint32_t EOCIF10 : 1; /*!< [10..10] AIN10 interrupt flag */ + __IOM uint32_t EOCIF11 : 1; /*!< [11..11] AIN11 interrupt flag */ + __IOM uint32_t EOCIF12 : 1; /*!< [12..12] AIN12 interrupt flag */ + __IOM uint32_t EOCIF13 : 1; /*!< [13..13] AIN13 interrupt flag */ + __IOM uint32_t EOCIF14 : 1; /*!< [14..14] AIN14 interrupt flag */ + __IOM uint32_t EOCIF15 : 1; /*!< [15..15] AIN15 interrupt flag */ + __IOM uint32_t EOCIF16 : 1; /*!< [16..16] AIN16 interrupt flag */ + __IOM uint32_t EOCIF17 : 1; /*!< [17..17] AIN17 interrupt flag */ + __IOM uint32_t EOCIF18 : 1; /*!< [18..18] AIN18 interrupt flag */ + uint32_t : 13; + } RIS_b; + } ; + __IOM uint32_t CALI; /*!< (@ 0x00000014) Offset:0x14 ADC Calibration Register */ +} SN_ADC_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Comparator (SN_CMP) + */ + +typedef struct { /*!< (@ 0x40028000) SN_CMP Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 CMP Control Register */ + + struct { + __IOM uint32_t CM0EN : 1; /*!< [0..0] CMP0 Enable bit */ + __IOM uint32_t CM0PS : 2; /*!< [2..1] CMP0 Positive input selection bits */ + __IOM uint32_t CM0NS : 2; /*!< [4..3] CMP0 Negative input pin */ + __IOM uint32_t CM0RS : 5; /*!< [9..5] CMP0 internal reference voltage (VIREF0) selection bits */ + __IOM uint32_t CM0OEN : 2; /*!< [11..10] CMP0 Output pin control bits */ + __IOM uint32_t CM0G : 1; /*!< [12..12] CMP0 interrupt trigger direction control bit */ + uint32_t : 3; + __IOM uint32_t CM1EN : 1; /*!< [16..16] CMP1 Enable bit */ + __IOM uint32_t CM1PS : 2; /*!< [18..17] CMP1 Positive input selection bits */ + __IOM uint32_t CM1NS : 2; /*!< [20..19] CMP1 Negative input pin */ + __IOM uint32_t CM1RS : 5; /*!< [25..21] CMP1 internal reference voltage (VIREF1) selection + bits */ + __IOM uint32_t CM1OEN : 2; /*!< [27..26] CMP1 Output pin control bits */ + __IOM uint32_t CM1G : 1; /*!< [28..28] CMP1 interrupt trigger direction control bit */ + uint32_t : 3; + } CTRL_b; + } ; + + union { + __IOM uint32_t CTRL1; /*!< (@ 0x00000004) Offset:0x04 CMP Control Register 1 */ + + struct { + __IOM uint32_t CM2EN : 1; /*!< [0..0] CMP2 Enable bit */ + __IOM uint32_t CM2PS : 2; /*!< [2..1] CMP2 Positive input selection bits */ + __IOM uint32_t CM2NS : 2; /*!< [4..3] CMP2 Negative input pin */ + __IOM uint32_t CM2RS : 5; /*!< [9..5] CMP2 internal reference voltage (VIREF2) selection bits */ + __IOM uint32_t CM2OEN : 2; /*!< [11..10] CMP2 Output pin control bits */ + __IOM uint32_t CM2G : 1; /*!< [12..12] CMP2 interrupt trigger direction control bit */ + uint32_t : 19; + } CTRL1_b; + } ; + + union { + __IOM uint32_t VIREF; /*!< (@ 0x00000008) Offset:0x08 CMP Internal Reference Voltage register */ + + struct { + __IOM uint32_t CMPIREFEN : 1; /*!< [0..0] CMP internal reference voltage (VIREF) enable */ + __IOM uint32_t CMPIREF : 2; /*!< [2..1] CMP internal reference voltage (VIREF) source */ + uint32_t : 29; + } VIREF_b; + } ; + + union { + __IM uint32_t OS; /*!< (@ 0x0000000C) Offset:0xC CMP Output Status Register */ + + struct { + __IM uint32_t CM0OUT : 1; /*!< [0..0] CMP0 Output flag bit */ + __IM uint32_t CM1OUT : 1; /*!< [1..1] CMP1 Output flag bit */ + __IM uint32_t CM2OUT : 1; /*!< [2..2] CMP2 Output flag bit */ + uint32_t : 29; + } OS_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000010) Offset:0x10 CMP Interrupt Enable Register */ + + struct { + __IOM uint32_t CM0IE : 1; /*!< [0..0] CMP0 interrupt enable */ + __IOM uint32_t CM1IE : 1; /*!< [1..1] CMP1 interrupt enable */ + __IOM uint32_t CM2IE : 1; /*!< [2..2] CMP2 interrupt enable */ + __IOM uint32_t CSIE : 1; /*!< [3..3] Cap-sensing interrupt enable */ + uint32_t : 28; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x00000014) Offset:0x14 CMP n Raw Interrupt Status Register */ + + struct { + __IM uint32_t CM0IF : 1; /*!< [0..0] CMP0 raw interrupt flag */ + __IM uint32_t CM1IF : 1; /*!< [1..1] CMP1 raw interrupt flag */ + __IM uint32_t CM2IF : 1; /*!< [2..2] CMP2 raw interrupt flag */ + __IM uint32_t CSIF : 1; /*!< [3..3] Cap-sensing raw interrupt flag */ + uint32_t : 28; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000018) Offset:0x18 CMP Interrupt Clear Register */ + + struct { + __OM uint32_t CM0IC : 1; /*!< [0..0] CMP0 interrupt flag clear bit */ + __OM uint32_t CM1IC : 1; /*!< [1..1] CMP1 interrupt flag clear bit */ + __OM uint32_t CM2IC : 1; /*!< [2..2] CMP2 interrupt flag clear bit */ + __OM uint32_t CSIC : 1; /*!< [3..3] Cap-sensing interrupt flag clear bit */ + uint32_t : 28; + } IC_b; + } ; + + union { + __IOM uint32_t DB; /*!< (@ 0x0000001C) Offset:0x1C CMP Interrupt Clear Register */ + + struct { + __IOM uint32_t CM0DB : 3; /*!< [2..0] Count for CMP0 output debounce time */ + uint32_t : 1; + __IOM uint32_t CM1DB : 3; /*!< [6..4] Count for CMP1 output debounce time */ + uint32_t : 1; + __IOM uint32_t CM2DB : 3; /*!< [10..8] Count for CMP2 output debounce time */ + uint32_t : 1; + __IOM uint32_t CSDB : 5; /*!< [16..12] Count for Cap-sensing output debounce time */ + uint32_t : 15; + } DB_b; + } ; + + union { + __IOM uint32_t CSCTRL; /*!< (@ 0x00000020) Offset:0x20 CMP Cap-sensing Control Register */ + + struct { + __IOM uint32_t CSEN : 1; /*!< [0..0] Cap-sensing module enable bit */ + __IOM uint32_t CSS : 1; /*!< [1..1] Cap-sensing operation start bit */ + __IOM uint32_t CS1ST : 1; /*!< [2..2] Cap-sensing channel scan group start bit */ + __IOM uint32_t CSH : 5; /*!< [7..3] Cap-sensing channel */ + uint32_t : 3; + __IOM uint32_t CMP : 3; /*!< [13..11] Comparator reference control bits */ + __IOM uint32_t VDSEL : 1; /*!< [14..14] Cap-sensing voltage detects select bit */ + __IOM uint32_t CHG : 3; /*!< [17..15] Cap-sensing charging time */ + __IOM uint32_t TNON : 2; /*!< [19..18] Non-overlap time */ + __IOM uint32_t CCAL : 4; /*!< [23..20] Cap Calibration parameter */ + __IOM uint32_t CCAL4 : 1; /*!< [24..24] Cap Calibration select bit */ + __IOM uint32_t CSOUTEN : 1; /*!< [25..25] Cap-sening output pin enable bit */ + __IOM uint32_t CSDIS : 1; /*!< [26..26] Channel discharge signl (CK_TCH) controll bit */ + uint32_t : 3; + __IOM uint32_t CSFAPC : 1; /*!< [30..30] CSF active controll */ + __IM uint32_t CSRDY : 1; /*!< [31..31] Cap-sensing module ready flag */ + } CSCTRL_b; + } ; + + union { + __IOM uint32_t CSCTRL1; /*!< (@ 0x00000024) Offset:0x24 CMP Cap-sensing Control Register + 1 */ + + struct { + __IOM uint32_t SGFRQ : 2; /*!< [1..0] Spread Spectrum frequency */ + uint32_t : 4; + __IOM uint32_t SGSEL : 2; /*!< [7..6] Cap-sensing 4MHz clock source and SSCG select bit */ + __IOM uint32_t OSCR : 5; /*!< [12..8] Ring OSC.4MHz clock range */ + __IOM uint32_t CSVCOV : 1; /*!< [13..13] CSV 16-bit event counter overflow indicator (Clock + source is Cap-sensing 4MHz) */ + __IOM uint32_t CSCOV : 1; /*!< [14..14] CSC 16-bit timer counter overflow indicator (Clock + source is CS_PCLK) */ + uint32_t : 17; + } CSCTRL1_b; + } ; + + union { + __IM uint32_t CSCNT; /*!< (@ 0x00000028) Offset:0x28 CMP CapSensing Counter Register */ + + struct { + __IM uint32_t CSV : 16; /*!< [15..0] CSV 16-bit event counter (CSV counter clock source is + CS_4MHz) */ + __IM uint32_t CSC : 16; /*!< [31..16] CSC 16-bit timer counter (CSC counter clock source + is CS_PCLK) */ + } CSCNT_b; + } ; +} SN_CMP_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CT16B0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 16-bit Timer 0 with Capture function (SN_CT16B0) + */ + +typedef struct { /*!< (@ 0x40000000) SN_CT16B0 Structure */ + + union { + __IOM uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT16Bn Timer Control Register */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] Counter enable */ + __IOM uint32_t CRST : 1; /*!< [1..1] Counter Reset */ + __IOM uint32_t CLKSEL : 1; /*!< [2..2] PCLK source */ + uint32_t : 1; + __IOM uint32_t CM : 3; /*!< [6..4] Counting mode selection */ + uint32_t : 25; + } TMRCTRL_b; + } ; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT16Bn Timer Counter Register */ + + struct { + __IOM uint32_t TC : 16; /*!< [15..0] Timer Counter */ + uint32_t : 16; + } TC_b; + } ; + + union { + __IOM uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT16Bn Prescale Register */ + + struct { + __IOM uint32_t PRE : 8; /*!< [7..0] Prescaler */ + uint32_t : 24; + } PRE_b; + } ; + + union { + __IOM uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT16Bn Prescale Counter Register */ + + struct { + __IOM uint32_t PC : 8; /*!< [7..0] Prescaler Counter */ + uint32_t : 24; + } PC_b; + } ; + + union { + __IOM uint32_t CNTCTRL; /*!< (@ 0x00000010) Offset:0x10 CT16Bn Counter Control Register */ + + struct { + __IOM uint32_t CTM : 2; /*!< [1..0] Counter/Timer Mode */ + uint32_t : 30; + } CNTCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT16Bn Match Control Register */ + + struct { + __IOM uint32_t MR0IE : 1; /*!< [0..0] Enable generating an interrupt when MR0 matches TC */ + __IOM uint32_t MR0RST : 1; /*!< [1..1] Enable reset TC when MR0 matches TC */ + __IOM uint32_t MR0STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR0 matches TC */ + __IOM uint32_t MR1IE : 1; /*!< [3..3] Enable generating an interrupt when MR1 matches TC */ + __IOM uint32_t MR1RST : 1; /*!< [4..4] Enable reset TC when MR1 matches TC */ + __IOM uint32_t MR1STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR1 matches TC */ + __IOM uint32_t MR2IE : 1; /*!< [6..6] Enable generating an interrupt when MR2 matches TC */ + __IOM uint32_t MR2RST : 1; /*!< [7..7] Enable reset TC when MR2 matches TC */ + __IOM uint32_t MR2STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR2 matches TC */ + __IOM uint32_t MR3IE : 1; /*!< [9..9] Enable generating an interrupt when MR3 matches TC */ + __IOM uint32_t MR3RST : 1; /*!< [10..10] Enable reset TC when MR3 matches TC */ + __IOM uint32_t MR3STOP : 1; /*!< [11..11] Stop TC and PC and clear CEN bit when MR3 matches TC */ + uint32_t : 9; + __IOM uint32_t MR9IE : 1; /*!< [21..21] Enable generating an interrupt based on CM[2:0] when + MR9 matches the value in the TC */ + __IOM uint32_t MR9RST : 1; /*!< [22..22] Enable reset TC when MR9 matches TC */ + __IOM uint32_t MR9STOP : 1; /*!< [23..23] Stop TC and PC and clear CEN bit when MR9 matches TC */ + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MCTRL_b; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t MR0; /*!< (@ 0x00000020) Offset:0x20 CT16Bn MR0 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key */ + } MR0_b; + } ; + + union { + __IOM uint32_t MR1; /*!< (@ 0x00000024) Offset:0x24 CT16Bn MR1 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key */ + } MR1_b; + } ; + + union { + __IOM uint32_t MR2; /*!< (@ 0x00000028) Offset:0x28 CT16Bn MR2 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key */ + } MR2_b; + } ; + + union { + __IOM uint32_t MR3; /*!< (@ 0x0000002C) Offset:0x2C CT16Bn MR3 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key */ + } MR3_b; + } ; + __IM uint32_t RESERVED1[5]; + + union { + __IOM uint32_t MR9; /*!< (@ 0x00000044) Offset:0x44 CT16Bn MR9 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key */ + } MR9_b; + } ; + __IM uint32_t RESERVED2[15]; + + union { + __IOM uint32_t CAPCTRL; /*!< (@ 0x00000084) Offset:0x84 CT16Bn Capture Control Register */ + + struct { + __IOM uint32_t CAP0RE : 1; /*!< [0..0] Capture/Reset on CT16Bn_CAP0 signal rising edge */ + __IOM uint32_t CAP0FE : 1; /*!< [1..1] Capture/Reset on CT16Bn_CAP0 signal falling edge */ + __IOM uint32_t CAP0IE : 1; /*!< [2..2] Interrupt on CT16Bn_CAP0 event */ + __IOM uint32_t CAP0EN : 1; /*!< [3..3] CAP0 function enable */ + uint32_t : 28; + } CAPCTRL_b; + } ; + + union { + __IM uint32_t CAP0; /*!< (@ 0x00000088) Offset:0x88 CT16Bn CAP0 Register */ + + struct { + __IM uint32_t CAP0 : 16; /*!< [15..0] Timer counter capture value */ + uint32_t : 16; + } CAP0_b; + } ; + + union { + __IOM uint32_t EM; /*!< (@ 0x0000008C) Offset:0x8C CT16Bn External Match Register */ + + struct { + __IOM uint32_t EM0 : 1; /*!< [0..0] When the TC doesn't match MR0 and EMC0 is not 0, this + bit will drive the state of CT16Bn_PWM0 output. */ + __IOM uint32_t EM1 : 1; /*!< [1..1] When the TC doesn't match MR1 and EMC1 is not 0, this + bit will drive the state of CT16Bn_PWM1 output. */ + __IOM uint32_t EM2 : 1; /*!< [2..2] When the TC doesn't match MR2 and EMC2 is not 0, this + bit will drive the state of CT16Bn_PWM2 output. */ + __IOM uint32_t EM3 : 1; /*!< [3..3] When the TC doesn't match MR3 and EMC3 is not 0, this + bit will drive the state of CT16Bn_PWM3 output. */ + __IOM uint32_t EMC0 : 2; /*!< [5..4] CT16Bn_PWM0 functionality when MR0=TC */ + __IOM uint32_t EMC1 : 2; /*!< [7..6] CT16Bn_PWM1 functionality when MR1=TC */ + __IOM uint32_t EMC2 : 2; /*!< [9..8] CT16Bn_PWM2 functionality when MR2=TC */ + __IOM uint32_t EMC3 : 2; /*!< [11..10] CT16Bn_PWM3 functionality when MR3=TC */ + uint32_t : 12; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } EM_b; + } ; + __IM uint32_t RESERVED3[2]; + + union { + __IOM uint32_t PWMCTRL; /*!< (@ 0x00000098) Offset:0x98 CT16Bn PWM Control Register */ + + struct { + __IOM uint32_t PWM0EN : 1; /*!< [0..0] PWM0 enable */ + __IOM uint32_t PWM1EN : 1; /*!< [1..1] PWM1 enable */ + __IOM uint32_t PWM2EN : 1; /*!< [2..2] PWM2 enable */ + __IOM uint32_t PWM3EN : 1; /*!< [3..3] PWM2 enable */ + __IOM uint32_t PWM0MODE : 2; /*!< [5..4] PWM0 output mode */ + __IOM uint32_t PWM1MODE : 2; /*!< [7..6] PWM1 output mode */ + __IOM uint32_t PWM2MODE : 2; /*!< [9..8] PWM2 output mode */ + __IOM uint32_t PWM3MODE : 2; /*!< [11..10] PWM3 output mode */ + uint32_t : 8; + __IOM uint32_t PWM0IOEN : 1; /*!< [20..20] CT16Bn_PWM0/GPIO selection */ + __IOM uint32_t PWM1IOEN : 1; /*!< [21..21] CT16Bn_PWM1/GPIO selection */ + __IOM uint32_t PWM2IOEN : 1; /*!< [22..22] CT16Bn_PWM2/GPIO selection */ + __IOM uint32_t PWM3IOEN : 1; /*!< [23..23] CT16Bn_PWM3/GPIO selection */ + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWMCTRL_b; + } ; + __IM uint32_t RESERVED4[3]; + + union { + __IM uint32_t RIS; /*!< (@ 0x000000A8) Offset:0xA8 CT16Bn Raw Interrupt Status Register */ + + struct { + __IM uint32_t MR0IF : 1; /*!< [0..0] Match channel 0 interrupt flag */ + __IM uint32_t MR1IF : 1; /*!< [1..1] Match channel 1 interrupt flag */ + __IM uint32_t MR2IF : 1; /*!< [2..2] Match channel 2 interrupt flag */ + __IM uint32_t MR3IF : 1; /*!< [3..3] Match channel 3 interrupt flag */ + __IM uint32_t CAP0IF : 1; /*!< [4..4] Capture channel 0 interrupt flag */ + __IM uint32_t MR9IF : 1; /*!< [5..5] Match channel 9 interrupt flag */ + uint32_t : 26; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x000000AC) Offset:0xAC CT16Bn Interrupt Clear Register */ + + struct { + __OM uint32_t MR0IC : 1; /*!< [0..0] MR0IF clear bit */ + __OM uint32_t MR1IC : 1; /*!< [1..1] MR1IF clear bit */ + __OM uint32_t MR2IC : 1; /*!< [2..2] MR2IF clear bit */ + __OM uint32_t MR3IC : 1; /*!< [3..3] MR3IF clear bit */ + __OM uint32_t CAP0IC : 1; /*!< [4..4] CAP0IF clear bit */ + __OM uint32_t MR9IC : 1; /*!< [5..5] MR9IF clear bit */ + uint32_t : 26; + } IC_b; + } ; + + union { + __IOM uint32_t PWMmNIOCTRL; /*!< (@ 0x000000B0) Offset:0xB0 CT16Bn PWMmN IO Control register */ + + struct { + __IOM uint32_t PWM0NIOEN : 2; /*!< [1..0] CT16Bn_PWM0N/GPIO selection bit */ + __IOM uint32_t PWM1NIOEN : 2; /*!< [3..2] CT16Bn_PWM0N/GPIO selection bit */ + __IOM uint32_t PWM2NIOEN : 2; /*!< [5..4] CT16Bn_PWM0N/GPIO selection bit */ + __IOM uint32_t PWM3NIOEN : 2; /*!< [7..6] CT16Bn_PWM3N/GPIO selection bit */ + uint32_t : 16; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWMmNIOCTRL_b; + } ; + + union { + __IOM uint32_t PWM0NDB; /*!< (@ 0x000000B4) Offset:0xB4 CT16Bn PWM0N Dead-band Period Register */ + + struct { + __IOM uint32_t DB : 10; /*!< [9..0] PWM0N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) + cycle */ + uint32_t : 14; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWM0NDB_b; + } ; + + union { + __IOM uint32_t PWM1NDB; /*!< (@ 0x000000B8) Offset:0xB8 CT16Bn PWM1N Dead-band Period Register */ + + struct { + __IOM uint32_t DB : 10; /*!< [9..0] PWM1N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) + cycle */ + uint32_t : 14; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWM1NDB_b; + } ; + + union { + __IOM uint32_t PWM2NDB; /*!< (@ 0x000000BC) Offset:0xBC CT16Bn PWM2N Dead-band Period Register */ + + struct { + __IOM uint32_t DB : 10; /*!< [9..0] PWM2N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) + cycle */ + uint32_t : 14; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWM2NDB_b; + } ; + + union { + __IOM uint32_t PWM3NDB; /*!< (@ 0x000000C0) Offset:0xC0 CT16Bn PWM3N Dead-band Period Register */ + + struct { + __IOM uint32_t DB : 10; /*!< [9..0] PWM3N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) + cycle */ + uint32_t : 14; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWM3NDB_b; + } ; +} SN_CT16B0_Type; /*!< Size = 196 (0xc4) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CT16B1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 16-bit Timer 1 with Capture function (SN_CT16B1) + */ + +typedef struct { /*!< (@ 0x40002000) SN_CT16B1 Structure */ + + union { + __IOM uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT16Bn Timer Control Register */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] Counter enable */ + __IOM uint32_t CRST : 1; /*!< [1..1] Counter Reset */ + __IOM uint32_t CLKSEL : 1; /*!< [2..2] PCLK source */ + uint32_t : 29; + } TMRCTRL_b; + } ; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT16Bn Timer Counter Register */ + + struct { + __IOM uint32_t TC : 16; /*!< [15..0] Timer Counter */ + uint32_t : 16; + } TC_b; + } ; + + union { + __IOM uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT16Bn Prescale Register */ + + struct { + __IOM uint32_t PRE : 8; /*!< [7..0] Prescaler */ + uint32_t : 24; + } PRE_b; + } ; + + union { + __IOM uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT16Bn Prescale Counter Register */ + + struct { + __IOM uint32_t PC : 8; /*!< [7..0] Prescaler Counter */ + uint32_t : 24; + } PC_b; + } ; + + union { + __IOM uint32_t CNTCTRL; /*!< (@ 0x00000010) Offset:0x10 CT16Bn Counter Control Register */ + + struct { + __IOM uint32_t CTM : 2; /*!< [1..0] Counter/Timer Mode */ + uint32_t : 30; + } CNTCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT16Bn Match Control Register */ + + struct { + __IOM uint32_t MR0IE : 1; /*!< [0..0] Enable generating an interrupt when MR0 matches TC */ + __IOM uint32_t MR0RST : 1; /*!< [1..1] Enable reset TC when MR0 matches TC */ + __IOM uint32_t MR0STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR0 matches TC */ + __IOM uint32_t MR1IE : 1; /*!< [3..3] Enable generating an interrupt when MR1 matches TC */ + __IOM uint32_t MR1RST : 1; /*!< [4..4] Enable reset TC when MR1 matches TC */ + __IOM uint32_t MR1STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR1 matches TC */ + __IOM uint32_t MR2IE : 1; /*!< [6..6] Enable generating an interrupt when MR2 matches TC */ + __IOM uint32_t MR2RST : 1; /*!< [7..7] Enable reset TC when MR2 matches TC */ + __IOM uint32_t MR2STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR2 matches TC */ + __IOM uint32_t MR3IE : 1; /*!< [9..9] Enable generating an interrupt when MR3 matches TC */ + __IOM uint32_t MR3RST : 1; /*!< [10..10] Enable reset TC when MR3 matches TC */ + __IOM uint32_t MR3STOP : 1; /*!< [11..11] Stop TC and PC and clear CEN bit when MR3 matches TC */ + __IOM uint32_t MR4IE : 1; /*!< [12..12] Enable generating an interrupt when MR4 matches TC */ + __IOM uint32_t MR4RST : 1; /*!< [13..13] Enable reset TC when MR4 matches TC */ + __IOM uint32_t MR4STOP : 1; /*!< [14..14] Stop TC and PC and clear CEN bit when MR4 matches TC */ + __IOM uint32_t MR5IE : 1; /*!< [15..15] Enable generating an interrupt when MR5 matches TC */ + __IOM uint32_t MR5RST : 1; /*!< [16..16] Enable reset TC when MR5 matches TC */ + __IOM uint32_t MR5STOP : 1; /*!< [17..17] Stop TC and PC and clear CEN bit when MR5 matches TC */ + __IOM uint32_t MR6IE : 1; /*!< [18..18] Enable generating an interrupt when MR6 matches TC */ + __IOM uint32_t MR6RST : 1; /*!< [19..19] Enable reset TC when MR6 matches TC */ + __IOM uint32_t MR6STOP : 1; /*!< [20..20] Stop TC and PC and clear CEN bit when MR6 matches TC */ + __IOM uint32_t MR7IE : 1; /*!< [21..21] Enable generating an interrupt when MR7 matches TC */ + __IOM uint32_t MR7RST : 1; /*!< [22..22] Enable reset TC when MR7 matches TC */ + __IOM uint32_t MR7STOP : 1; /*!< [23..23] Stop TC and PC and clear CEN bit when MR7 matches TC */ + __IOM uint32_t MR8IE : 1; /*!< [24..24] Enable generating an interrupt when MR8 matches TC */ + __IOM uint32_t MR8RST : 1; /*!< [25..25] Enable reset TC when MR8 matches TC */ + __IOM uint32_t MR8STOP : 1; /*!< [26..26] Stop TC and PC and clear CEN bit when MR8 matches TC */ + __IOM uint32_t MR9IE : 1; /*!< [27..27] Enable generating an interrupt when MR9 matches TC */ + __IOM uint32_t MR9RST : 1; /*!< [28..28] Enable reset TC when MR9 matches TC */ + __IOM uint32_t MR9STOP : 1; /*!< [29..29] Stop TC and PC and clear CEN bit when MR9 matches TC */ + uint32_t : 2; + } MCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL2; /*!< (@ 0x00000018) Offset:0x18 CT16Bn Match Control Register 2 */ + + struct { + __IOM uint32_t MR10IE : 1; /*!< [0..0] Enable generating an interrupt when MR10 matches TC */ + __IOM uint32_t MR10RST : 1; /*!< [1..1] Enable reset TC when MR10 matches TC */ + __IOM uint32_t MR10STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR10 matches TC */ + __IOM uint32_t MR11IE : 1; /*!< [3..3] Enable generating an interrupt when MR11 matches TC */ + __IOM uint32_t MR11RST : 1; /*!< [4..4] Enable reset TC when MR11 matches TC */ + __IOM uint32_t MR11STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR11 matches TC */ + __IOM uint32_t MR12IE : 1; /*!< [6..6] Enable generating an interrupt when MR12 matches TC */ + __IOM uint32_t MR12RST : 1; /*!< [7..7] Enable reset TC when MR12 matches TC */ + __IOM uint32_t MR12STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR12 matches TC */ + uint32_t : 23; + } MCTRL2_b; + } ; + __IM uint32_t RESERVED; + __IOM uint32_t MR0; /*!< (@ 0x00000020) Offset:0x20 CT16Bn MR0 Register */ + __IOM uint32_t MR1; /*!< (@ 0x00000024) Offset:0x24 CT16Bn MR1 Register */ + __IOM uint32_t MR2; /*!< (@ 0x00000028) Offset:0x28 CT16Bn MR2 Register */ + __IOM uint32_t MR3; /*!< (@ 0x0000002C) Offset:0x2C CT16Bn MR3 Register */ + __IOM uint32_t MR4; /*!< (@ 0x00000030) Offset:0x30 CT16Bn MR4 Register */ + __IOM uint32_t MR5; /*!< (@ 0x00000034) Offset:0x34 CT16Bn MR5 Register */ + __IOM uint32_t MR6; /*!< (@ 0x00000038) Offset:0x38 CT16Bn MR6 Register */ + __IOM uint32_t MR7; /*!< (@ 0x0000003C) Offset:0x3C CT16Bn MR7 Register */ + __IOM uint32_t MR8; /*!< (@ 0x00000040) Offset:0x40 CT16Bn MR8 Register */ + __IOM uint32_t MR9; /*!< (@ 0x00000044) Offset:0x44 CT16Bn MR9 Register */ + __IOM uint32_t MR10; /*!< (@ 0x00000048) Offset:0x48 CT16Bn MR10 Register */ + __IOM uint32_t MR11; /*!< (@ 0x0000004C) Offset:0x4C CT16Bn MR11 Register */ + __IOM uint32_t MR12; /*!< (@ 0x00000050) Offset:0x50 CT16Bn MR12 Register */ + __IM uint32_t RESERVED1[12]; + + union { + __IOM uint32_t CAPCTRL; /*!< (@ 0x00000084) Offset:0x84 CT16Bn Capture Control Register */ + + struct { + __IOM uint32_t CAP0RE : 1; /*!< [0..0] Capture/Reset on CT16Bn_CAP0 signal rising edge */ + __IOM uint32_t CAP0FE : 1; /*!< [1..1] Capture/Reset on CT16Bn_CAP0 signal falling edge */ + __IOM uint32_t CAP0IE : 1; /*!< [2..2] Interrupt on CT16Bn_CAP0 event */ + __IOM uint32_t CAP0EN : 1; /*!< [3..3] CAP0 function enable */ + uint32_t : 28; + } CAPCTRL_b; + } ; + + union { + __IM uint32_t CAP0; /*!< (@ 0x00000088) Offset:0x88 CT16Bn CAP0 Register */ + + struct { + __IM uint32_t CAP0 : 16; /*!< [15..0] Timer counter capture value */ + uint32_t : 16; + } CAP0_b; + } ; + + union { + __IOM uint32_t EM; /*!< (@ 0x0000008C) Offset:0x8C CT16Bn External Match Register */ + + struct { + __IOM uint32_t EM0 : 1; /*!< [0..0] When the TC matches MR0, this bit will act according + to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output. */ + __IOM uint32_t EM1 : 1; /*!< [1..1] When the TC matches MR1, this bit will act according + to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output. */ + __IOM uint32_t EM2 : 1; /*!< [2..2] When the TC matches MR2, this bit will act according + to EMC2[1:0], and also drive the state of CT16Bn_PWM2 output. */ + __IOM uint32_t EM3 : 1; /*!< [3..3] When the TC matches MR3, this bit will act according + to EMC3[1:0], and also drive the state of CT16Bn_PWM3 output. */ + __IOM uint32_t EM4 : 1; /*!< [4..4] When the TC matches MR4, this bit will act according + to EMC4[1:0], and also drive the state of CT16Bn_PWM0 output. */ + __IOM uint32_t EM5 : 1; /*!< [5..5] When the TC matches MR5, this bit will act according + to EMC5[1:0], and also drive the state of CT16Bn_PWM1 output. */ + __IOM uint32_t EM6 : 1; /*!< [6..6] When the TC matches MR6, this bit will act according + to EMC6[1:0], and also drive the state of CT16Bn_PWM2 output. */ + __IOM uint32_t EM7 : 1; /*!< [7..7] When the TC matches MR7, this bit will act according + to EMC7[1:0], and also drive the state of CT16Bn_PWM3 output. */ + __IOM uint32_t EM8 : 1; /*!< [8..8] When the TC matches MR8, this bit will act according + to EMC8[1:0], and also drive the state of CT16Bn_PWM0 output. */ + __IOM uint32_t EM9 : 1; /*!< [9..9] When the TC matches MR9, this bit will act according + to EMC9[1:0], and also drive the state of CT16Bn_PWM1 output. */ + __IOM uint32_t EM10 : 1; /*!< [10..10] When the TC matches MR10, this bit will act according + to EMC10[1:0], and also drive the state of CT16Bn_PWM2 + output. */ + __IOM uint32_t EM11 : 1; /*!< [11..11] When the TC matches MR11, this bit will act according + to EMC11[1:0], and also drive the state of CT16Bn_PWM3 + output. */ + uint32_t : 20; + } EM_b; + } ; + + union { + __IOM uint32_t EMC; /*!< (@ 0x00000090) Offset:0x90 CT16Bn External Match Control register */ + + struct { + __IOM uint32_t EMC0 : 2; /*!< [1..0] CT16Bn_PWM0 functionality */ + __IOM uint32_t EMC1 : 2; /*!< [3..2] CT16Bn_PWM1 functionality */ + __IOM uint32_t EMC2 : 2; /*!< [5..4] CT16Bn_PWM2 functionality */ + __IOM uint32_t EMC3 : 2; /*!< [7..6] CT16Bn_PWM3 functionality */ + __IOM uint32_t EMC4 : 2; /*!< [9..8] CT16Bn_PWM4 functionality */ + __IOM uint32_t EMC5 : 2; /*!< [11..10] CT16Bn_PWM5 functionality */ + __IOM uint32_t EMC6 : 2; /*!< [13..12] CT16Bn_PWM6 functionality */ + __IOM uint32_t EMC7 : 2; /*!< [15..14] CT16Bn_PWM7 functionality */ + __IOM uint32_t EMC8 : 2; /*!< [17..16] CT16Bn_PWM8 functionality */ + __IOM uint32_t EMC9 : 2; /*!< [19..18] CT16Bn_PWM9 functionality */ + __IOM uint32_t EMC10 : 2; /*!< [21..20] CT16Bn_PWM10 functionality */ + __IOM uint32_t EMC11 : 2; /*!< [23..22] CT16Bn_PWM11 functionality */ + uint32_t : 8; + } EMC_b; + } ; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t PWMCTRL; /*!< (@ 0x00000098) Offset:0x98 CT16Bn PWM Control Register */ + + struct { + __IOM uint32_t PWM0MODE : 2; /*!< [1..0] PWM0 output mode */ + __IOM uint32_t PWM1MODE : 2; /*!< [3..2] PWM1 output mode */ + __IOM uint32_t PWM2MODE : 2; /*!< [5..4] PWM2 output mode */ + __IOM uint32_t PWM3MODE : 2; /*!< [7..6] PWM3 output mode */ + __IOM uint32_t PWM4MODE : 2; /*!< [9..8] PWM4 output mode */ + __IOM uint32_t PWM5MODE : 2; /*!< [11..10] PWM5 output mode */ + __IOM uint32_t PWM6MODE : 2; /*!< [13..12] PWM6 output mode */ + __IOM uint32_t PWM7MODE : 2; /*!< [15..14] PWM7 output mode */ + __IOM uint32_t PWM8MODE : 2; /*!< [17..16] PWM8 output mode */ + __IOM uint32_t PWM9MODE : 2; /*!< [19..18] PWM9 output mode */ + __IOM uint32_t PWM10MODE : 2; /*!< [21..20] PWM10 output mode */ + __IOM uint32_t PWM11MODE : 2; /*!< [23..22] PWM11 output mode */ + uint32_t : 8; + } PWMCTRL_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t PWMENB; /*!< (@ 0x000000A0) Offset:0xA0 CT16Bn PWM Enable register */ + + struct { + __IOM uint32_t PWM0EN : 1; /*!< [0..0] PWM0 enable */ + __IOM uint32_t PWM1EN : 1; /*!< [1..1] PWM1 enable */ + __IOM uint32_t PWM2EN : 1; /*!< [2..2] PWM2 enable */ + __IOM uint32_t PWM3EN : 1; /*!< [3..3] PWM3 enable */ + __IOM uint32_t PWM4EN : 1; /*!< [4..4] PWM4 enable */ + __IOM uint32_t PWM5EN : 1; /*!< [5..5] PWM5 enable */ + __IOM uint32_t PWM6EN : 1; /*!< [6..6] PWM6 enable */ + __IOM uint32_t PWM7EN : 1; /*!< [7..7] PWM7 enable */ + __IOM uint32_t PWM8EN : 1; /*!< [8..8] PWM8 enable */ + __IOM uint32_t PWM9EN : 1; /*!< [9..9] PWM9 enable */ + __IOM uint32_t PWM10EN : 1; /*!< [10..10] PWM10 enable */ + __IOM uint32_t PWM11EN : 1; /*!< [11..11] PWM11 enable */ + uint32_t : 20; + } PWMENB_b; + } ; + + union { + __IOM uint32_t PWMIOENB; /*!< (@ 0x000000A4) Offset:0xA4 CT16Bn PWM IO Enable register */ + + struct { + __IOM uint32_t PWM0IOEN : 1; /*!< [0..0] CT16Bn_PWM0/GPIO selection */ + __IOM uint32_t PWM1IOEN : 1; /*!< [1..1] CT16Bn_PWM1/GPIO selection */ + __IOM uint32_t PWM2IOEN : 1; /*!< [2..2] CT16Bn_PWM2/GPIO selection */ + __IOM uint32_t PWM3IOEN : 1; /*!< [3..3] CT16Bn_PWM3/GPIO selection */ + __IOM uint32_t PWM4IOEN : 1; /*!< [4..4] CT16Bn_PWM4/GPIO selection */ + __IOM uint32_t PWM5IOEN : 1; /*!< [5..5] CT16Bn_PWM5/GPIO selection */ + __IOM uint32_t PWM6IOEN : 1; /*!< [6..6] CT16Bn_PWM6/GPIO selection */ + __IOM uint32_t PWM7IOEN : 1; /*!< [7..7] CT16Bn_PWM7/GPIO selection */ + __IOM uint32_t PWM8IOEN : 1; /*!< [8..8] CT16Bn_PWM8/GPIO selection */ + __IOM uint32_t PWM9IOEN : 1; /*!< [9..9] CT16Bn_PWM9/GPIO selection */ + __IOM uint32_t PWM10IOEN : 1; /*!< [10..10] CT16Bn_PWM10/GPIO selection */ + __IOM uint32_t PWM11IOEN : 1; /*!< [11..11] CT16Bn_PWM11/GPIO selection */ + uint32_t : 20; + } PWMIOENB_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x000000A8) Offset:0xA8 CT16Bn Raw Interrupt Status Register */ + + struct { + __IM uint32_t MR0IF : 1; /*!< [0..0] Match channel 0 interrupt flag */ + __IM uint32_t MR1IF : 1; /*!< [1..1] Match channel 1 interrupt flag */ + __IM uint32_t MR2IF : 1; /*!< [2..2] Match channel 2 interrupt flag */ + __IM uint32_t MR3IF : 1; /*!< [3..3] Match channel 3 interrupt flag */ + __IM uint32_t MR4IF : 1; /*!< [4..4] Match channel 4 interrupt flag */ + __IM uint32_t MR5IF : 1; /*!< [5..5] Match channel 5 interrupt flag */ + __IM uint32_t MR6IF : 1; /*!< [6..6] Match channel 6 interrupt flag */ + __IM uint32_t MR7IF : 1; /*!< [7..7] Match channel 7 interrupt flag */ + __IM uint32_t MR8IF : 1; /*!< [8..8] Match channel 8 interrupt flag */ + __IM uint32_t MR9IF : 1; /*!< [9..9] Match channel 9 interrupt flag */ + __IM uint32_t MR10IF : 1; /*!< [10..10] Match channel 10 interrupt flag */ + __IM uint32_t MR11IF : 1; /*!< [11..11] Match channel 11 interrupt flag */ + __IM uint32_t MR12IF : 1; /*!< [12..12] Match channel 12 interrupt flag */ + __IM uint32_t CAP0IF : 1; /*!< [13..13] Capture channel 0 interrupt flag */ + uint32_t : 18; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x000000AC) Offset:0xAC CT16Bn Interrupt Clear Register */ + + struct { + __OM uint32_t MR0IC : 1; /*!< [0..0] MR0IF clear bit */ + __OM uint32_t MR1IC : 1; /*!< [1..1] MR1IF clear bit */ + __OM uint32_t MR2IC : 1; /*!< [2..2] MR2IF clear bit */ + __OM uint32_t MR3IC : 1; /*!< [3..3] MR3IF clear bit */ + __OM uint32_t MR4IC : 1; /*!< [4..4] MR4IF clear bit */ + __OM uint32_t MR5IC : 1; /*!< [5..5] MR5IF clear bit */ + __OM uint32_t MR6IC : 1; /*!< [6..6] MR6IF clear bit */ + __OM uint32_t MR7IC : 1; /*!< [7..7] MR7IF clear bit */ + __OM uint32_t MR8IC : 1; /*!< [8..8] MR8IF clear bit */ + __OM uint32_t MR9IC : 1; /*!< [9..9] MR9IF clear bit */ + __OM uint32_t MR10IC : 1; /*!< [10..10] MR10IF clear bit */ + __OM uint32_t MR11IC : 1; /*!< [11..11] MR11IF clear bit */ + __OM uint32_t MR12IC : 1; /*!< [12..12] MR12IF clear bit */ + __OM uint32_t CAP0IC : 1; /*!< [13..13] CAP0IF clear bit */ + uint32_t : 18; + } IC_b; + } ; +} SN_CT16B1_Type; /*!< Size = 176 (0xb0) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CT16B2 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 16-bit Timer 2 with Capture function (SN_CT16B2) + */ + +typedef struct { /*!< (@ 0x40004000) SN_CT16B2 Structure */ + + union { + __IOM uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT16Bn Timer Control Register */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] Counter enable */ + __IOM uint32_t CRST : 1; /*!< [1..1] Counter Reset */ + __IOM uint32_t CLKSEL : 1; /*!< [2..2] PCLK source */ + uint32_t : 1; + __IOM uint32_t CM : 3; /*!< [6..4] Counting mode selection */ + uint32_t : 25; + } TMRCTRL_b; + } ; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT16Bn Timer Counter Register */ + + struct { + __IOM uint32_t TC : 16; /*!< [15..0] Timer Counter */ + uint32_t : 16; + } TC_b; + } ; + + union { + __IOM uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT16Bn Prescale Register */ + + struct { + __IOM uint32_t PRE : 8; /*!< [7..0] Prescalzer */ + uint32_t : 24; + } PRE_b; + } ; + + union { + __IOM uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT16Bn Prescale Counter Register */ + + struct { + __IOM uint32_t PC : 8; /*!< [7..0] Prescaler Counter */ + uint32_t : 24; + } PC_b; + } ; + + union { + __IOM uint32_t CNTCTRL; /*!< (@ 0x00000010) Offset:0x10 CT16Bn Counter Control Register */ + + struct { + __IOM uint32_t CTM : 2; /*!< [1..0] Counter/Timer Mode */ + uint32_t : 30; + } CNTCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT16Bn Match Control Register */ + + struct { + __IOM uint32_t MR0IE : 1; /*!< [0..0] Enable generating an interrupt when MR0 matches TC */ + __IOM uint32_t MR0RST : 1; /*!< [1..1] Enable reset TC when MR0 matches TC */ + __IOM uint32_t MR0STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR0 matches TC */ + __IOM uint32_t MR1IE : 1; /*!< [3..3] Enable generating an interrupt when MR1 matches TC */ + __IOM uint32_t MR1RST : 1; /*!< [4..4] Enable reset TC when MR1 matches TC */ + __IOM uint32_t MR1STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR1 matches TC */ + __IOM uint32_t MR2IE : 1; /*!< [6..6] Enable generating an interrupt when MR2 matches TC */ + __IOM uint32_t MR2RST : 1; /*!< [7..7] Enable reset TC when MR2 matches TC */ + __IOM uint32_t MR2STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR2 matches TC */ + __IOM uint32_t MR3IE : 1; /*!< [9..9] Enable generating an interrupt when MR3 matches TC */ + __IOM uint32_t MR3RST : 1; /*!< [10..10] Enable reset TC when MR3 matches TC */ + __IOM uint32_t MR3STOP : 1; /*!< [11..11] Stop TC and PC and clear CEN bit when MR3 matches TC */ + uint32_t : 9; + __IOM uint32_t MR9IE : 1; /*!< [21..21] Enable generating an interrupt when MR9 matches TC */ + __IOM uint32_t MR9RST : 1; /*!< [22..22] Enable reset TC when MR9 matches TC */ + __IOM uint32_t MR9STOP : 1; /*!< [23..23] Stop TC and PC and clear CEN bit when MR9 matches TC */ + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MCTRL_b; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t MR0; /*!< (@ 0x00000020) Offset:0x20 CT16Bn MR0 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MR0_b; + } ; + + union { + __IOM uint32_t MR1; /*!< (@ 0x00000024) Offset:0x24 CT16Bn MR1 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MR1_b; + } ; + + union { + __IOM uint32_t MR2; /*!< (@ 0x00000028) Offset:0x28 CT16Bn MR2 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MR2_b; + } ; + + union { + __IOM uint32_t MR3; /*!< (@ 0x0000002C) Offset:0x2C CT16Bn MR3 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MR3_b; + } ; + __IM uint32_t RESERVED1[5]; + + union { + __IOM uint32_t MR9; /*!< (@ 0x00000044) Offset:0x44 CT16Bn MR9 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MR9_b; + } ; + __IM uint32_t RESERVED2[15]; + + union { + __IOM uint32_t CAPCTRL; /*!< (@ 0x00000084) Offset:0x84 CT16Bn Capture Control Register */ + + struct { + __IOM uint32_t CAP0RE : 1; /*!< [0..0] Capture/Reset on CT16Bn_CAP0 signal rising edge */ + __IOM uint32_t CAP0FE : 1; /*!< [1..1] Capture/Reset on CT16Bn_CAP0 signal falling edge */ + __IOM uint32_t CAP0IE : 1; /*!< [2..2] Interrupt on CT16Bn_CAP0 event */ + __IOM uint32_t CAP0EN : 1; /*!< [3..3] CAP0 function enable */ + uint32_t : 28; + } CAPCTRL_b; + } ; + + union { + __IM uint32_t CAP0; /*!< (@ 0x00000088) Offset:0x88 CT16Bn CAP0 Register */ + + struct { + __IM uint32_t CAP0 : 16; /*!< [15..0] Timer counter capture value */ + uint32_t : 16; + } CAP0_b; + } ; + + union { + __IOM uint32_t EM; /*!< (@ 0x0000008C) Offset:0x8C CT16Bn External Match Register */ + + struct { + __IOM uint32_t EM0 : 1; /*!< [0..0] When the TC matches MR0, this bit will act according + to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output. */ + __IOM uint32_t EM1 : 1; /*!< [1..1] When the TC matches MR1, this bit will act according + to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output. */ + __IOM uint32_t EM2 : 1; /*!< [2..2] When the TC matches MR2, this bit will act according + to EMC2[1:0], and also drive the state of CT16Bn_PWM2 output. */ + __IOM uint32_t EM3 : 1; /*!< [3..3] When the TC matches MR3, this bit will act according + to EMC3[1:0], and also drive the state of CT16Bn_PWM3 output. */ + __IOM uint32_t EMC0 : 2; /*!< [5..4] CT16Bn_PWM0 functionality */ + __IOM uint32_t EMC1 : 2; /*!< [7..6] CT16Bn_PWM1 functionality */ + __IOM uint32_t EMC2 : 2; /*!< [9..8] CT16Bn_PWM2 functionality */ + __IOM uint32_t EMC3 : 2; /*!< [11..10] CT16Bn_PWM3 functionality */ + uint32_t : 12; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } EM_b; + } ; + __IM uint32_t RESERVED3[2]; + + union { + __IOM uint32_t PWMCTRL; /*!< (@ 0x00000098) Offset:0x98 CT16Bn PWM Control Register */ + + struct { + __IOM uint32_t PWM0EN : 1; /*!< [0..0] PWM0 enable */ + __IOM uint32_t PWM1EN : 1; /*!< [1..1] PWM1 enable */ + __IOM uint32_t PWM2EN : 1; /*!< [2..2] PWM2 enable */ + __IOM uint32_t PWM3EN : 1; /*!< [3..3] PWM2 enable */ + __IOM uint32_t PWM0MODE : 2; /*!< [5..4] PWM0 output mode */ + __IOM uint32_t PWM1MODE : 2; /*!< [7..6] PWM1 output mode */ + __IOM uint32_t PWM2MODE : 2; /*!< [9..8] PWM2 output mode */ + __IOM uint32_t PWM3MODE : 2; /*!< [11..10] PWM3 output mode */ + uint32_t : 8; + __IOM uint32_t PWM0IOEN : 1; /*!< [20..20] CT16Bn_PWM0/GPIO selection */ + __IOM uint32_t PWM1IOEN : 1; /*!< [21..21] CT16Bn_PWM1/GPIO selection */ + __IOM uint32_t PWM2IOEN : 1; /*!< [22..22] CT16Bn_PWM2/GPIO selection */ + __IOM uint32_t PWM3IOEN : 1; /*!< [23..23] CT16Bn_PWM3/GPIO selection */ + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWMCTRL_b; + } ; + __IM uint32_t RESERVED4[3]; + + union { + __IM uint32_t RIS; /*!< (@ 0x000000A8) Offset:0xA8 CT16Bn Raw Interrupt Status Register */ + + struct { + __IM uint32_t MR0IF : 1; /*!< [0..0] Match channel 0 interrupt flag */ + __IM uint32_t MR1IF : 1; /*!< [1..1] Match channel 1 interrupt flag */ + __IM uint32_t MR2IF : 1; /*!< [2..2] Match channel 2 interrupt flag */ + __IM uint32_t MR3IF : 1; /*!< [3..3] Match channel 3 interrupt flag */ + __IM uint32_t CAP0IF : 1; /*!< [4..4] Capture channel 0 interrupt flag */ + __IM uint32_t MR9IF : 1; /*!< [5..5] Match channel 9 interrupt flag */ + uint32_t : 26; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x000000AC) Offset:0xAC CT16Bn Interrupt Clear Register */ + + struct { + __OM uint32_t MR0IC : 1; /*!< [0..0] MR0IF clear bit */ + __OM uint32_t MR1IC : 1; /*!< [1..1] MR1IF clear bit */ + __OM uint32_t MR2IC : 1; /*!< [2..2] MR2IF clear bit */ + __OM uint32_t MR3IC : 1; /*!< [3..3] MR3IF clear bit */ + __OM uint32_t CAP0IC : 1; /*!< [4..4] CAP0IF clear bit */ + __OM uint32_t MR9IC : 1; /*!< [5..5] MR9IF clear bit */ + uint32_t : 26; + } IC_b; + } ; +} SN_CT16B2_Type; /*!< Size = 176 (0xb0) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CT16B3 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 16-bit Timer 3 with Capture function (SN_CT16B3) + */ + +typedef struct { /*!< (@ 0x40006000) SN_CT16B3 Structure */ + + union { + __IOM uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT16Bn Timer Control Register */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] Counter enable */ + __IOM uint32_t CRST : 1; /*!< [1..1] Counter Reset */ + __IOM uint32_t CLKSEL : 1; /*!< [2..2] PCLK source */ + uint32_t : 29; + } TMRCTRL_b; + } ; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT16Bn Timer Counter Register */ + + struct { + __IOM uint32_t TC : 16; /*!< [15..0] Timer Counter */ + uint32_t : 16; + } TC_b; + } ; + + union { + __IOM uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT16Bn Prescale Register */ + + struct { + __IOM uint32_t PRE : 8; /*!< [7..0] Prescalzer */ + uint32_t : 24; + } PRE_b; + } ; + + union { + __IOM uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT16Bn Prescale Counter Register */ + + struct { + __IOM uint32_t PC : 8; /*!< [7..0] Prescaler Counter */ + uint32_t : 24; + } PC_b; + } ; + + union { + __IOM uint32_t CNTCTRL; /*!< (@ 0x00000010) Offset:0x10 CT16Bn Counter Control Register */ + + struct { + __IOM uint32_t CTM : 2; /*!< [1..0] Counter/Timer Mode */ + uint32_t : 30; + } CNTCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT16Bn Match Control Register */ + + struct { + __IOM uint32_t MR0IE : 1; /*!< [0..0] Enable generating an interrupt when MR0 matches TC */ + __IOM uint32_t MR0RST : 1; /*!< [1..1] Enable reset TC when MR0 matches TC */ + __IOM uint32_t MR0STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR0 matches TC */ + __IOM uint32_t MR1IE : 1; /*!< [3..3] Enable generating an interrupt when MR1 matches TC */ + __IOM uint32_t MR1RST : 1; /*!< [4..4] Enable reset TC when MR1 matches TC */ + __IOM uint32_t MR1STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR1 matches TC */ + uint32_t : 15; + __IOM uint32_t MR9IE : 1; /*!< [21..21] Enable generating an interrupt based on CM[2:0] when + MR9 matches the value in the TC */ + __IOM uint32_t MR9RST : 1; /*!< [22..22] Enable reset TC when MR9 matches TC */ + __IOM uint32_t MR9STOP : 1; /*!< [23..23] Stop TC and PC and clear CEN bit when MR9 matches TC */ + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MCTRL_b; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t MR0; /*!< (@ 0x00000020) Offset:0x20 CT16Bn MR0 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MR0_b; + } ; + + union { + __IOM uint32_t MR1; /*!< (@ 0x00000024) Offset:0x24 CT16Bn MR1 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MR1_b; + } ; + __IM uint32_t RESERVED1[7]; + + union { + __IOM uint32_t MR9; /*!< (@ 0x00000044) Offset:0x44 CT16Bn MR9 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MR9_b; + } ; + __IM uint32_t RESERVED2[15]; + + union { + __IOM uint32_t CAPCTRL; /*!< (@ 0x00000084) Offset:0x84 CT16Bn Capture Control Register */ + + struct { + __IOM uint32_t CAP0RE : 1; /*!< [0..0] Capture/Reset on CT16Bn_CAP0 signal rising edge */ + __IOM uint32_t CAP0FE : 1; /*!< [1..1] Capture/Reset on CT16Bn_CAP0 signal falling edge */ + __IOM uint32_t CAP0IE : 1; /*!< [2..2] Interrupt on CT16Bn_CAP0 event */ + __IOM uint32_t CAP0EN : 1; /*!< [3..3] CAP0 function enable */ + uint32_t : 28; + } CAPCTRL_b; + } ; + + union { + __IM uint32_t CAP0; /*!< (@ 0x00000088) Offset:0x88 CT16Bn CAP0 Register */ + + struct { + __IM uint32_t CAP0 : 16; /*!< [15..0] Timer counter capture value */ + uint32_t : 16; + } CAP0_b; + } ; + + union { + __IOM uint32_t EM; /*!< (@ 0x0000008C) Offset:0x8C CT16Bn External Match Register */ + + struct { + __IOM uint32_t EM0 : 1; /*!< [0..0] When the TC matches MR0, this bit will act according + to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output. */ + __IOM uint32_t EM1 : 1; /*!< [1..1] When the TC matches MR1, this bit will act according + to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output. */ + uint32_t : 2; + __IOM uint32_t EMC0 : 2; /*!< [5..4] CT16Bn_PWM0 functionality */ + __IOM uint32_t EMC1 : 2; /*!< [7..6] CT16Bn_PWM1 functionality */ + uint32_t : 24; + } EM_b; + } ; + __IM uint32_t RESERVED3[2]; + + union { + __IOM uint32_t PWMCTRL; /*!< (@ 0x00000098) Offset:0x98 CT16Bn PWM Control Register */ + + struct { + __IOM uint32_t PWM0EN : 1; /*!< [0..0] PWM0 enable */ + __IOM uint32_t PWM1EN : 1; /*!< [1..1] PWM1 enable */ + uint32_t : 2; + __IOM uint32_t PWM0MODE : 2; /*!< [5..4] PWM0 output mode */ + __IOM uint32_t PWM1MODE : 2; /*!< [7..6] PWM1 output mode */ + uint32_t : 12; + __IOM uint32_t PWM0IOEN : 1; /*!< [20..20] CT16Bn_PWM0/GPIO selection */ + __IOM uint32_t PWM1IOEN : 1; /*!< [21..21] CT16Bn_PWM1/GPIO selection */ + uint32_t : 2; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWMCTRL_b; + } ; + __IM uint32_t RESERVED4[3]; + + union { + __IM uint32_t RIS; /*!< (@ 0x000000A8) Offset:0xA8 CT16Bn Raw Interrupt Status Register */ + + struct { + __IM uint32_t MR0IF : 1; /*!< [0..0] Match channel 0 interrupt flag */ + __IM uint32_t MR1IF : 1; /*!< [1..1] Match channel 1 interrupt flag */ + uint32_t : 2; + __IM uint32_t CAP0IF : 1; /*!< [4..4] Capture channel 0 interrupt flag */ + __IM uint32_t MR9IF : 1; /*!< [5..5] Match channel 9 interrupt flag */ + uint32_t : 26; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x000000AC) Offset:0xAC CT16Bn Interrupt Clear Register */ + + struct { + __OM uint32_t MR0IC : 1; /*!< [0..0] MR0IF clear bit */ + __OM uint32_t MR1IC : 1; /*!< [1..1] MR1IF clear bit */ + uint32_t : 2; + __OM uint32_t CAP0IC : 1; /*!< [4..4] CAP0IF clear bit */ + __OM uint32_t MR9IC : 1; /*!< [5..5] MR9IF clear bit */ + uint32_t : 26; + } IC_b; + } ; + + union { + __IOM uint32_t PWMmNIOCTRL; /*!< (@ 0x000000B0) Offset:0xB0 CT16Bn PWMmN IO Control register */ + + struct { + __IOM uint32_t PWM0NIOEN : 2; /*!< [1..0] CT16Bn_PWM0N/GPIO selection bit */ + __IOM uint32_t PWM1NIOEN : 2; /*!< [3..2] CT16Bn_PWM0N/GPIO selection bit */ + uint32_t : 20; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWMmNIOCTRL_b; + } ; + + union { + __IOM uint32_t PWM0NDB; /*!< (@ 0x000000B4) Offset:0xB4 CT16Bn PWM0N Dead-band Period Register */ + + struct { + __IOM uint32_t DB : 10; /*!< [9..0] PWM0N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) + cycle */ + uint32_t : 14; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWM0NDB_b; + } ; + + union { + __IOM uint32_t PWM1NDB; /*!< (@ 0x000000B8) Offset:0xB8 CT16Bn PWM1N Dead-band Period Register */ + + struct { + __IOM uint32_t DB : 10; /*!< [9..0] PWM1N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) + cycle */ + uint32_t : 14; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWM1NDB_b; + } ; +} SN_CT16B3_Type; /*!< Size = 188 (0xbc) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CT16B5 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 16-bit Timer 5 with Capture function (SN_CT16B5) + */ + +typedef struct { /*!< (@ 0x4000A000) SN_CT16B5 Structure */ + + union { + __IOM uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT16Bn Timer Control Register */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] Counter enable */ + __IOM uint32_t CRST : 1; /*!< [1..1] Counter Reset */ + __IOM uint32_t CLKSEL : 2; /*!< [3..2] PCLK source */ + __IOM uint32_t CM : 3; /*!< [6..4] Counting mode selection */ + uint32_t : 25; + } TMRCTRL_b; + } ; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT16Bn Timer Counter Register */ + + struct { + __IOM uint32_t TC : 16; /*!< [15..0] Timer Counter */ + uint32_t : 16; + } TC_b; + } ; + + union { + __IOM uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT16Bn Prescale Register */ + + struct { + __IOM uint32_t PRE : 8; /*!< [7..0] Prescalzer */ + uint32_t : 24; + } PRE_b; + } ; + + union { + __IOM uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT16Bn Prescale Counter Register */ + + struct { + __IOM uint32_t PC : 8; /*!< [7..0] Prescaler Counter */ + uint32_t : 24; + } PC_b; + } ; + + union { + __IOM uint32_t CNTCTRL; /*!< (@ 0x00000010) Offset:0x10 CT16Bn Counter Control Register */ + + struct { + __IOM uint32_t CTM : 2; /*!< [1..0] Counter/Timer Mode */ + uint32_t : 30; + } CNTCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT16Bn Match Control Register */ + + struct { + __IOM uint32_t MR0IE : 1; /*!< [0..0] Enable generating an interrupt when MR0 matches TC */ + __IOM uint32_t MR0RST : 1; /*!< [1..1] Enable reset TC when MR0 matches TC */ + __IOM uint32_t MR0STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR0 matches TC */ + __IOM uint32_t MR1IE : 1; /*!< [3..3] Enable generating an interrupt when MR1 matches TC */ + __IOM uint32_t MR1RST : 1; /*!< [4..4] Enable reset TC when MR1 matches TC */ + __IOM uint32_t MR1STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR1 matches TC */ + __IOM uint32_t MR2IE : 1; /*!< [6..6] Enable generating an interrupt when MR2 matches TC */ + __IOM uint32_t MR2RST : 1; /*!< [7..7] Enable reset TC when MR2 matches TC */ + __IOM uint32_t MR2STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR2 matches TC */ + __IOM uint32_t MR3IE : 1; /*!< [9..9] Enable generating an interrupt when MR3 matches TC */ + __IOM uint32_t MR3RST : 1; /*!< [10..10] Enable reset TC when MR3 matches TC */ + __IOM uint32_t MR3STOP : 1; /*!< [11..11] Stop TC and PC and clear CEN bit when MR3 matches TC */ + uint32_t : 9; + __IOM uint32_t MR9IE : 1; /*!< [21..21] Enable generating an interrupt based on CM[2:0] when + MR9 matches the value in the TC */ + __IOM uint32_t MR9RST : 1; /*!< [22..22] Enable reset TC when MR9 matches TC */ + __IOM uint32_t MR9STOP : 1; /*!< [23..23] Stop TC and PC and clear CEN bit when MR9 matches TC */ + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MCTRL_b; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t MR0; /*!< (@ 0x00000020) Offset:0x20 CT16Bn MR0 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MR0_b; + } ; + + union { + __IOM uint32_t MR1; /*!< (@ 0x00000024) Offset:0x24 CT16Bn MR1 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key */ + } MR1_b; + } ; + + union { + __IOM uint32_t MR2; /*!< (@ 0x00000028) Offset:0x28 CT16Bn MR2 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key */ + } MR2_b; + } ; + + union { + __IOM uint32_t MR3; /*!< (@ 0x0000002C) Offset:0x2C CT16Bn MR3 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key */ + } MR3_b; + } ; + __IM uint32_t RESERVED1[5]; + + union { + __IOM uint32_t MR9; /*!< (@ 0x00000044) Offset:0x44 CT16Bn MR9 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key */ + } MR9_b; + } ; + __IM uint32_t RESERVED2[15]; + + union { + __IOM uint32_t CAPCTRL; /*!< (@ 0x00000084) Offset:0x84 CT16Bn Capture Control Register */ + + struct { + __IOM uint32_t CAP0RE : 1; /*!< [0..0] Capture/Reset on CT16Bn_CAP0 signal rising edge */ + __IOM uint32_t CAP0FE : 1; /*!< [1..1] Capture/Reset on CT16Bn_CAP0 signal falling edge */ + __IOM uint32_t CAP0IE : 1; /*!< [2..2] Interrupt on CT16Bn_CAP0 event */ + __IOM uint32_t CAP0EN : 1; /*!< [3..3] CAP0 function enable */ + uint32_t : 28; + } CAPCTRL_b; + } ; + + union { + __IM uint32_t CAP0; /*!< (@ 0x00000088) Offset:0x88 CT16Bn CAP0 Register */ + + struct { + __IM uint32_t CAP0 : 16; /*!< [15..0] Timer counter capture value */ + uint32_t : 16; + } CAP0_b; + } ; + + union { + __IOM uint32_t EM; /*!< (@ 0x0000008C) Offset:0x8C CT16Bn External Match Register */ + + struct { + __IOM uint32_t EM0 : 1; /*!< [0..0] When the TC matches MR0, this bit will act according + to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output. */ + __IOM uint32_t EM1 : 1; /*!< [1..1] When the TC matches MR1, this bit will act according + to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output. */ + __IOM uint32_t EM2 : 1; /*!< [2..2] When the TC matches MR2, this bit will act according + to EMC2[1:0], and also drive the state of CT16Bn_PWM2 output. */ + __IOM uint32_t EM3 : 1; /*!< [3..3] When the TC matches MR3, this bit will act according + to EMC3[1:0], and also drive the state of CT16Bn_PWM3 output. */ + __IOM uint32_t EMC0 : 2; /*!< [5..4] CT16Bn_PWM0 functionality */ + __IOM uint32_t EMC1 : 2; /*!< [7..6] CT16Bn_PWM1 functionality */ + __IOM uint32_t EMC2 : 2; /*!< [9..8] CT16Bn_PWM2 functionality */ + __IOM uint32_t EMC3 : 2; /*!< [11..10] CT16Bn_PWM3 functionality */ + uint32_t : 12; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } EM_b; + } ; + __IM uint32_t RESERVED3[2]; + + union { + __IOM uint32_t PWMCTRL; /*!< (@ 0x00000098) Offset:0x98 CT16Bn PWM Control Register */ + + struct { + __IOM uint32_t PWM0EN : 1; /*!< [0..0] PWM0 enable */ + __IOM uint32_t PWM1EN : 1; /*!< [1..1] PWM1 enable */ + __IOM uint32_t PWM2EN : 1; /*!< [2..2] PWM2 enable */ + __IOM uint32_t PWM3EN : 1; /*!< [3..3] PWM2 enable */ + __IOM uint32_t PWM0MODE : 2; /*!< [5..4] PWM0 output mode */ + __IOM uint32_t PWM1MODE : 2; /*!< [7..6] PWM1 output mode */ + __IOM uint32_t PWM2MODE : 2; /*!< [9..8] PWM2 output mode */ + __IOM uint32_t PWM3MODE : 2; /*!< [11..10] PWM3 output mode */ + uint32_t : 8; + __IOM uint32_t PWM0IOEN : 1; /*!< [20..20] CT16Bn_PWM0/GPIO selection */ + __IOM uint32_t PWM1IOEN : 1; /*!< [21..21] CT16Bn_PWM1/GPIO selection */ + __IOM uint32_t PWM2IOEN : 1; /*!< [22..22] CT16Bn_PWM2/GPIO selection */ + __IOM uint32_t PWM3IOEN : 1; /*!< [23..23] CT16Bn_PWM3/GPIO selection */ + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWMCTRL_b; + } ; + __IM uint32_t RESERVED4[3]; + + union { + __IM uint32_t RIS; /*!< (@ 0x000000A8) Offset:0xA8 CT16Bn Raw Interrupt Status Register */ + + struct { + __IM uint32_t MR0IF : 1; /*!< [0..0] Match channel 0 interrupt flag */ + __IM uint32_t MR1IF : 1; /*!< [1..1] Match channel 1 interrupt flag */ + __IM uint32_t MR2IF : 1; /*!< [2..2] Match channel 2 interrupt flag */ + __IM uint32_t MR3IF : 1; /*!< [3..3] Match channel 3 interrupt flag */ + __IM uint32_t CAP0IF : 1; /*!< [4..4] Capture channel 0 interrupt flag */ + __IM uint32_t MR9IF : 1; /*!< [5..5] Match channel 9 interrupt flag */ + uint32_t : 26; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x000000AC) Offset:0xAC CT16Bn Interrupt Clear Register */ + + struct { + __OM uint32_t MR0IC : 1; /*!< [0..0] MR0IF clear bit */ + __OM uint32_t MR1IC : 1; /*!< [1..1] MR1IF clear bit */ + __OM uint32_t MR2IC : 1; /*!< [2..2] MR2IF clear bit */ + __OM uint32_t MR3IC : 1; /*!< [3..3] MR3IF clear bit */ + __OM uint32_t CAP0IC : 1; /*!< [4..4] CAP0IF clear bit */ + __OM uint32_t MR9IC : 1; /*!< [5..5] MR9IF clear bit */ + uint32_t : 26; + } IC_b; + } ; +} SN_CT16B5_Type; /*!< Size = 176 (0xb0) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (SN_WDT) + */ + +typedef struct { /*!< (@ 0x40010000) SN_WDT Structure */ + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000000) Offset:0x00 WDT Configuration Register */ + + struct { + __IOM uint32_t WDTEN : 1; /*!< [0..0] WDT enable */ + __IOM uint32_t WDTIE : 1; /*!< [1..1] WDT interrupt enable */ + __IOM uint32_t WDTINT : 1; /*!< [2..2] WDT interrupt flag */ + uint32_t : 13; + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } CFG_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000008) Offset:0x08 WDT Timer Constant Register */ + + struct { + __IOM uint32_t TC : 8; /*!< [7..0] Watchdog timer constant reload value */ + uint32_t : 8; + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } TC_b; + } ; + + union { + __OM uint32_t FEED; /*!< (@ 0x0000000C) Offset:0x0C WDT Feed Register */ + + struct { + __OM uint32_t FV : 16; /*!< [15..0] Watchdog feed value */ + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } FEED_b; + } ; +} SN_WDT_Type; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real-time Clock (SN_RTC) + */ + +typedef struct { /*!< (@ 0x40012000) SN_RTC Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 RTC Control Register */ + + struct { + __IOM uint32_t RTCEN : 1; /*!< [0..0] RTC enable */ + uint32_t : 31; + } CTRL_b; + } ; + + union { + __IOM uint32_t CLKS; /*!< (@ 0x00000004) Offset:0x04 RTC Clock Source Register */ + + struct { + __IOM uint32_t CLKSEL : 1; /*!< [0..0] RTC clock source */ + uint32_t : 31; + } CLKS_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000008) Offset:0x08 RTC Interrupt Enable Register */ + + struct { + __IOM uint32_t SECIE : 1; /*!< [0..0] Second interrupt enable */ + uint32_t : 31; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x0000000C) Offset:0x0C RTC Raw Interrupt Status Register */ + + struct { + __IM uint32_t SECIF : 1; /*!< [0..0] Second interrupt flag */ + uint32_t : 31; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000010) Offset:0x10 RTC Interrupt Clear Register */ + + struct { + __OM uint32_t SECIC : 1; /*!< [0..0] Second interrupt flag clear */ + uint32_t : 31; + } IC_b; + } ; + __IOM uint32_t SECCNTV; /*!< (@ 0x00000014) Offset:0x14 RTC Second Counter Reload Value Register */ + __IM uint32_t SECCNT; /*!< (@ 0x00000018) Offset:0x18 RTC Second Counter Register */ +} SN_RTC_Type; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI0 (SN_SPI0) + */ + +typedef struct { /*!< (@ 0x4001C000) SN_SPI0 Structure */ + + union { + __IOM uint32_t CTRL0; /*!< (@ 0x00000000) Offset:0x00 SPI0 Control Register 0 */ + + struct { + __IOM uint32_t SPIEN : 1; /*!< [0..0] SPI enable */ + __IOM uint32_t LOOPBACK : 1; /*!< [1..1] Loopback mode enable */ + __IOM uint32_t SDODIS : 1; /*!< [2..2] Slave data out disable */ + __IOM uint32_t MS : 1; /*!< [3..3] Master/Slave selection */ + __IOM uint32_t FORMAT : 1; /*!< [4..4] Interface format */ + uint32_t : 1; + __OM uint32_t FRESET : 2; /*!< [7..6] SPI FSM and FIFO Reset */ + __IOM uint32_t DL : 4; /*!< [11..8] Data length = DL[3:0]+1 */ + __IOM uint32_t TXFIFOTH : 3; /*!< [14..12] TX FIFO Threshold level */ + __IOM uint32_t RXFIFOTH : 3; /*!< [17..15] RX FIFO Threshold level */ + __IOM uint32_t SELDIS : 1; /*!< [18..18] Auto-SEL disable bit */ + uint32_t : 13; + } CTRL0_b; + } ; + + union { + __IOM uint32_t CTRL1; /*!< (@ 0x00000004) Offset:0x04 SPI0 Control Register 1 */ + + struct { + __IOM uint32_t MLSB : 1; /*!< [0..0] MSB/LSB seletion */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock priority selection */ + __IOM uint32_t CPHA : 1; /*!< [2..2] Clock phase of edge sampling */ + uint32_t : 29; + } CTRL1_b; + } ; + + union { + __IOM uint32_t CLKDIV; /*!< (@ 0x00000008) Offset:0x08 SPI0 Clock Divider Register */ + + struct { + __IOM uint32_t DIV : 8; /*!< [7..0] SPI0 SCK */ + uint32_t : 24; + } CLKDIV_b; + } ; + + union { + __IM uint32_t STAT; /*!< (@ 0x0000000C) Offset:0x0C SPI0 Status Register */ + + struct { + __IM uint32_t TX_EMPTY : 1; /*!< [0..0] TX FIFO empty flag */ + __IM uint32_t TX_FULL : 1; /*!< [1..1] TX FIFO full flag */ + __IM uint32_t RX_EMPTY : 1; /*!< [2..2] RX FIFO empty flag */ + __IM uint32_t RX_FULL : 1; /*!< [3..3] RX FIFO full flag */ + __IM uint32_t BUSY : 1; /*!< [4..4] Busy flag */ + __IM uint32_t TXFIFOTHF : 1; /*!< [5..5] TX FIFO threshold flag */ + __IM uint32_t RXFIFOTHF : 1; /*!< [6..6] RX FIFO threshold flag */ + uint32_t : 25; + } STAT_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000010) Offset:0x10 SPI0 Interrupt Enable Register */ + + struct { + __IOM uint32_t RXOVFIE : 1; /*!< [0..0] RX FIFO overflow interrupt enable */ + __IOM uint32_t RXTOIE : 1; /*!< [1..1] RX time-out interrupt enable */ + __IOM uint32_t RXFIFOTHIE : 1; /*!< [2..2] RX FIFO threshold interrupt enable */ + __IOM uint32_t TXFIFOTHIE : 1; /*!< [3..3] TX FIFO threshold interrupt enable */ + __IOM uint32_t DMAHTIE : 1; /*!< [4..4] DMA half transfer interrupt enable bit */ + __IOM uint32_t DMATCIE : 1; /*!< [5..5] DMA transfer complete interrupt enable bit */ + uint32_t : 26; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x00000014) Offset:0x14 SPI0 Raw Interrupt Status Register */ + + struct { + __IM uint32_t RXOVFIF : 1; /*!< [0..0] RX FIFO overflow interrupt flag */ + __IM uint32_t RXTOIF : 1; /*!< [1..1] RX time-out interrupt flag */ + __IM uint32_t RXFIFOTHIF : 1; /*!< [2..2] RX FIFO threshold interrupt flag */ + __IM uint32_t TXFIFOTHIF : 1; /*!< [3..3] TX FIFO threshold interrupt flag */ + __IM uint32_t DMAHTIF : 1; /*!< [4..4] RX FIFO threshold interrupt flag */ + __IM uint32_t DMATCIF : 1; /*!< [5..5] DMA transfer complete flag */ + uint32_t : 26; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000018) Offset:0x18 SPI0 Interrupt Clear Register */ + + struct { + __OM uint32_t RXOVFIC : 1; /*!< [0..0] RX FIFO overflow flag clear */ + __OM uint32_t RXTOIC : 1; /*!< [1..1] RX time-out interrupt flag clear */ + __OM uint32_t RXFIFOTHIC : 1; /*!< [2..2] RX Interrupt flag Clear */ + __OM uint32_t TXFIFOTHIC : 1; /*!< [3..3] TX Interrupt flag Clear */ + __OM uint32_t DMAHTIC : 1; /*!< [4..4] Select the DMAHTIF flag to be cleared */ + __OM uint32_t DMATCIC : 1; /*!< [5..5] Select the DMATCIF flag to be cleared */ + uint32_t : 26; + } IC_b; + } ; + + union { + __IOM uint32_t DATA; /*!< (@ 0x0000001C) Offset:0x1C SPI0 Data Register */ + + struct { + __IOM uint32_t Data : 16; /*!< [15..0] Data */ + uint32_t : 16; + } DATA_b; + } ; + + union { + __IOM uint32_t DFDLY; /*!< (@ 0x00000020) Offset:0x20 SPI0 Data Fetch Register */ + + struct { + __IOM uint32_t DFETCH_EN : 1; /*!< [0..0] SPI0 data fetch control bit */ + uint32_t : 31; + } DFDLY_b; + } ; + + union { + __IOM uint32_t DMACTRL; /*!< (@ 0x00000024) Offset:0x24 SPI0 DMA Control register */ + + struct { + __IOM uint32_t DMAEN : 1; /*!< [0..0] SPI to SPI DMA enable bit */ + __IOM uint32_t DIR : 1; /*!< [1..1] SPI data transfer direction */ + uint32_t : 30; + } DMACTRL_b; + } ; + + union { + __IOM uint32_t DMACNT; /*!< (@ 0x00000028) Offset:0x28 SPI0 DMA Control register */ + + struct { + __IOM uint32_t CNT : 28; /*!< [27..0] Number of data to DMA RX count transfer */ + uint32_t : 4; + } DMACNT_b; + } ; + + union { + __IOM uint32_t DMAHTCNT; /*!< (@ 0x0000002C) Offset:0x2C SPI0 DMA Control register */ + + struct { + __IOM uint32_t HTCNT : 28; /*!< [27..0] Number of data to DMA RX half count transfer */ + uint32_t : 4; + } DMAHTCNT_b; + } ; + + union { + __IM uint32_t CURCNT; /*!< (@ 0x00000030) Offset:0x30 SPI0 DMA Control register */ + + struct { + __IM uint32_t CURCNT : 28; /*!< [27..0] This field indicates DMA current transfer data counter + pointer. */ + uint32_t : 4; + } CURCNT_b; + } ; +} SN_SPI0_Type; /*!< Size = 52 (0x34) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SPI1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI1 (SN_SPI1) + */ + +typedef struct { /*!< (@ 0x40058000) SN_SPI1 Structure */ + + union { + __IOM uint32_t CTRL0; /*!< (@ 0x00000000) Offset:0x00 SPI1 Control Register 0 */ + + struct { + __IOM uint32_t SPIEN : 1; /*!< [0..0] SPI enable */ + __IOM uint32_t LOOPBACK : 1; /*!< [1..1] Loopback mode enable */ + __IOM uint32_t SDODIS : 1; /*!< [2..2] Slave data out disable */ + __IOM uint32_t MS : 1; /*!< [3..3] Master/Slave selection */ + __IOM uint32_t FORMAT : 1; /*!< [4..4] Interface format */ + uint32_t : 1; + __OM uint32_t FRESET : 2; /*!< [7..6] SPI FSM and FIFO Reset */ + __IOM uint32_t DL : 4; /*!< [11..8] Data length = DL[3:0]+1 */ + __IOM uint32_t TXFIFOTH : 3; /*!< [14..12] TX FIFO Threshold level */ + __IOM uint32_t RXFIFOTH : 3; /*!< [17..15] RX FIFO Threshold level */ + __IOM uint32_t SELDIS : 1; /*!< [18..18] Auto-SEL disable bit */ + uint32_t : 13; + } CTRL0_b; + } ; + + union { + __IOM uint32_t CTRL1; /*!< (@ 0x00000004) Offset:0x04 SPI1 Control Register 1 */ + + struct { + __IOM uint32_t MLSB : 1; /*!< [0..0] MSB/LSB seletion */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock priority selection */ + __IOM uint32_t CPHA : 1; /*!< [2..2] Clock phase of edge sampling */ + uint32_t : 29; + } CTRL1_b; + } ; + + union { + __IOM uint32_t CLKDIV; /*!< (@ 0x00000008) Offset:0x08 SPI1 Clock Divider Register */ + + struct { + __IOM uint32_t DIV : 8; /*!< [7..0] SPI1 SCK */ + uint32_t : 24; + } CLKDIV_b; + } ; + + union { + __IM uint32_t STAT; /*!< (@ 0x0000000C) Offset:0x0C SPI1 Status Register */ + + struct { + __IM uint32_t TX_EMPTY : 1; /*!< [0..0] TX FIFO empty flag */ + __IM uint32_t TX_FULL : 1; /*!< [1..1] TX FIFO full flag */ + __IM uint32_t RX_EMPTY : 1; /*!< [2..2] RX FIFO empty flag */ + __IM uint32_t RX_FULL : 1; /*!< [3..3] RX FIFO full flag */ + __IM uint32_t BUSY : 1; /*!< [4..4] Busy flag */ + __IM uint32_t TXFIFOTHF : 1; /*!< [5..5] TX FIFO threshold flag */ + __IM uint32_t RXFIFOTHF : 1; /*!< [6..6] RX FIFO threshold flag */ + uint32_t : 25; + } STAT_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000010) Offset:0x10 SPI1 Interrupt Enable Register */ + + struct { + __IOM uint32_t RXOVFIE : 1; /*!< [0..0] RX FIFO overflow interrupt enable */ + __IOM uint32_t RXTOIE : 1; /*!< [1..1] RX time-out interrupt enable */ + __IOM uint32_t RXFIFOTHIE : 1; /*!< [2..2] RX FIFO threshold interrupt enable */ + __IOM uint32_t TXFIFOTHIE : 1; /*!< [3..3] TX FIFO threshold interrupt enable */ + uint32_t : 28; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x00000014) Offset:0x14 SPI1 Raw Interrupt Status Register */ + + struct { + __IM uint32_t RXOVFIF : 1; /*!< [0..0] RX FIFO overflow interrupt flag */ + __IM uint32_t RXTOIF : 1; /*!< [1..1] RX time-out interrupt flag */ + __IM uint32_t RXFIFOTHIF : 1; /*!< [2..2] RX FIFO threshold interrupt flag */ + __IM uint32_t TXFIFOTHIF : 1; /*!< [3..3] TX FIFO threshold interrupt flag */ + uint32_t : 28; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000018) Offset:0x18 SPI1 Interrupt Clear Register */ + + struct { + __OM uint32_t RXOVFIC : 1; /*!< [0..0] RX FIFO overflow flag clear */ + __OM uint32_t RXTOIC : 1; /*!< [1..1] RX time-out interrupt flag clear */ + __OM uint32_t RXFIFOTHIC : 1; /*!< [2..2] RX Interrupt flag Clear */ + __OM uint32_t TXFIFOTHIC : 1; /*!< [3..3] TX Interrupt flag Clear */ + uint32_t : 28; + } IC_b; + } ; + + union { + __IOM uint32_t DATA; /*!< (@ 0x0000001C) Offset:0x1C SPI1 Data Register */ + + struct { + __IOM uint32_t Data : 16; /*!< [15..0] Data */ + uint32_t : 16; + } DATA_b; + } ; + + union { + __IOM uint32_t DFDLY; /*!< (@ 0x00000020) Offset:0x20 SPI1 Data Fetch Register */ + + struct { + __IOM uint32_t DFETCH_EN : 1; /*!< [0..0] SPI1 data fetch control bit */ + uint32_t : 31; + } DFDLY_b; + } ; +} SN_SPI1_Type; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_I2C0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C0 (SN_I2C0) + */ + +typedef struct { /*!< (@ 0x40018000) SN_I2C0 Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 I2Cn Control Register */ + + struct { + uint32_t : 1; + __IOM uint32_t NACK : 1; /*!< [1..1] NACK assert flag */ + __IOM uint32_t ACK : 1; /*!< [2..2] ACK assert flag */ + uint32_t : 1; + __IOM uint32_t STO : 1; /*!< [4..4] STOP assert flag */ + __IOM uint32_t STA : 1; /*!< [5..5] START assert flag */ + uint32_t : 1; + __IOM uint32_t I2CMODE : 1; /*!< [7..7] I2C mode */ + __IOM uint32_t I2CEN : 1; /*!< [8..8] I2Cn interface enable */ + uint32_t : 23; + } CTRL_b; + } ; + + union { + __IOM uint32_t STAT; /*!< (@ 0x00000004) Offset:0x04 I2Cn Status Register */ + + struct { + __IM uint32_t RX_DN : 1; /*!< [0..0] RX done status */ + __IM uint32_t ACK_STAT : 1; /*!< [1..1] ACK done status */ + __IM uint32_t NACK_STAT : 1; /*!< [2..2] NACK done status */ + __IM uint32_t STOP_DN : 1; /*!< [3..3] STOP done status */ + __IM uint32_t START_DN : 1; /*!< [4..4] START done status */ + __IM uint32_t MST : 1; /*!< [5..5] I2C master/slave status */ + __IM uint32_t SLV_RX_HIT : 1; /*!< [6..6] Slave RX address hit flag */ + __IM uint32_t SLV_TX_HIT : 1; /*!< [7..7] Slave TX address hit flag */ + __IM uint32_t LOST_ARB : 1; /*!< [8..8] Lost arbitration status */ + __IM uint32_t TIMEOUT : 1; /*!< [9..9] Time-out status */ + uint32_t : 5; + __IOM uint32_t I2CIF : 1; /*!< [15..15] I2C interrupt flag */ + uint32_t : 16; + } STAT_b; + } ; + + union { + __IOM uint32_t TXDATA; /*!< (@ 0x00000008) Offset:0x08 I2Cn TX Data Register */ + + struct { + __IOM uint32_t Data : 8; /*!< [7..0] TX Data */ + uint32_t : 24; + } TXDATA_b; + } ; + + union { + __IM uint32_t RXDATA; /*!< (@ 0x0000000C) Offset:0x0C I2Cn RX Data Register */ + + struct { + __IM uint32_t Data : 8; /*!< [7..0] RX Data received when RX_DN=1 */ + uint32_t : 24; + } RXDATA_b; + } ; + + union { + __IOM uint32_t SLVADDR0; /*!< (@ 0x00000010) Offset:0x10 I2Cn Slave Address 0 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 0 */ + uint32_t : 20; + __IOM uint32_t GCEN : 1; /*!< [30..30] General call address enable */ + __IOM uint32_t ADD_MODE : 1; /*!< [31..31] Slave address mode */ + } SLVADDR0_b; + } ; + + union { + __IOM uint32_t SLVADDR1; /*!< (@ 0x00000014) Offset:0x14 I2Cn Slave Address 1 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 1 */ + uint32_t : 22; + } SLVADDR1_b; + } ; + + union { + __IOM uint32_t SLVADDR2; /*!< (@ 0x00000018) Offset:0x18 I2Cn Slave Address 2 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 2 */ + uint32_t : 22; + } SLVADDR2_b; + } ; + + union { + __IOM uint32_t SLVADDR3; /*!< (@ 0x0000001C) Offset:0x1C I2Cn Slave Address 3 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 3 */ + uint32_t : 22; + } SLVADDR3_b; + } ; + + union { + __IOM uint32_t SCLHT; /*!< (@ 0x00000020) Offset:0x20 I2Cn SCL High Time Register */ + + struct { + __IOM uint32_t SCLH : 8; /*!< [7..0] SCLn High period time=(SCLHT+1)*I2Cn_PCLK cycle */ + uint32_t : 24; + } SCLHT_b; + } ; + + union { + __IOM uint32_t SCLLT; /*!< (@ 0x00000024) Offset:0x24 I2Cn SCL Low Time Register */ + + struct { + __IOM uint32_t SCLL : 8; /*!< [7..0] SCLn Low period time=(SCLLT+1)*I2Cn_PCLK cycle */ + uint32_t : 24; + } SCLLT_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t TOCTRL; /*!< (@ 0x0000002C) Offset:0x2C I2Cn Timeout Control Register */ + + struct { + __IOM uint32_t TO : 16; /*!< [15..0] Timeout period time = TO*32*I2Cn_PCLK cycle */ + uint32_t : 16; + } TOCTRL_b; + } ; +} SN_I2C0_Type; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART0 (SN_UART0) + */ + +typedef struct { /*!< (@ 0x40016000) SN_UART0 Structure */ + + union { + union { + __IM uint32_t RB; /*!< (@ 0x00000000) Offset:0x00 UARTn Receiver Buffer Register */ + + struct { + __IM uint32_t RB : 8; /*!< [7..0] The received byte in UART RX FIFO */ + uint32_t : 24; + } RB_b; + } ; + + union { + __OM uint32_t TH; /*!< (@ 0x00000000) Offset:0x00 UARTn Transmit Holding Register */ + + struct { + __OM uint32_t TH : 8; /*!< [7..0] The byte to be transmitted in UART TX FIFO when transmitter + is available */ + uint32_t : 24; + } TH_b; + } ; + + union { + __IOM uint32_t DLL; /*!< (@ 0x00000000) Offset:0x00 UARTn Divisor Latch LSB Register */ + + struct { + __IOM uint32_t DLL : 8; /*!< [7..0] DLL and DLM register determines the baud rate of UARTn */ + uint32_t : 24; + } DLL_b; + } ; + }; + + union { + union { + __IOM uint32_t DLM; /*!< (@ 0x00000004) Offset:0x04 UARTn Divisor Latch MSB Register */ + + struct { + __IOM uint32_t DLM : 8; /*!< [7..0] DLL and DLM register determines the baud rate of USARTn */ + uint32_t : 24; + } DLM_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000004) Offset:0x04 UARTn Interrupt Enable Register */ + + struct { + __IOM uint32_t RDAIE : 1; /*!< [0..0] RDA interrupt enable */ + __IOM uint32_t THREIE : 1; /*!< [1..1] THRE interrupt enable */ + __IOM uint32_t RLSIE : 1; /*!< [2..2] RLS interrupt enable */ + uint32_t : 1; + __IOM uint32_t TEMTIE : 1; /*!< [4..4] TEMT interrupt enable */ + uint32_t : 3; + __IOM uint32_t ABEOIE : 1; /*!< [8..8] ABE0 interrupt enable */ + __IOM uint32_t ABTOIE : 1; /*!< [9..9] ABT0 interrupt enable */ + uint32_t : 22; + } IE_b; + } ; + }; + + union { + union { + __IM uint32_t II; /*!< (@ 0x00000008) Offset:0x08 UARTn Interrupt Identification Register */ + + struct { + __IM uint32_t INTSTATUS : 1; /*!< [0..0] Interrupt status */ + __IM uint32_t INTID : 3; /*!< [3..1] Interrupt ID of RX FIFO */ + uint32_t : 2; + __IM uint32_t FIFOEN : 2; /*!< [7..6] Equal to FIFOEN bits in USARTn_FIFOCTRL register */ + __IM uint32_t ABEOIF : 1; /*!< [8..8] ABEO interrupt flag */ + __IM uint32_t ABTOIF : 1; /*!< [9..9] ABTO interrupt flag */ + uint32_t : 22; + } II_b; + } ; + + union { + __OM uint32_t FIFOCTRL; /*!< (@ 0x00000008) Offset:0x08 UARTn FIFO Control Register */ + + struct { + __OM uint32_t FIFOEN : 1; /*!< [0..0] FIFO enable */ + uint32_t : 5; + __OM uint32_t RXTL : 2; /*!< [7..6] RX trigger level */ + uint32_t : 24; + } FIFOCTRL_b; + } ; + }; + + union { + __IOM uint32_t LC; /*!< (@ 0x0000000C) Offset:0x0C UARTn Line Control Register */ + + struct { + __IOM uint32_t WLS : 2; /*!< [1..0] Word length selection */ + __IOM uint32_t SBS : 1; /*!< [2..2] Stop bit selection */ + __IOM uint32_t PE : 1; /*!< [3..3] Parity enable */ + __IOM uint32_t PS : 2; /*!< [5..4] Parity selection */ + __IOM uint32_t BC : 1; /*!< [6..6] Break control */ + __IOM uint32_t DLAB : 1; /*!< [7..7] Divisor Latch access */ + uint32_t : 24; + } LC_b; + } ; + __IM uint32_t RESERVED; + + union { + __IM uint32_t LS; /*!< (@ 0x00000014) Offset:0x14 UARTn Line Status Register */ + + struct { + __IM uint32_t RDR : 1; /*!< [0..0] Receiver data ready flag */ + __IM uint32_t OE : 1; /*!< [1..1] Overrun error flag */ + __IM uint32_t PE : 1; /*!< [2..2] Parity error flag */ + __IM uint32_t FE : 1; /*!< [3..3] Framing error flag */ + __IM uint32_t BI : 1; /*!< [4..4] Break interrupt flag */ + __IM uint32_t THRE : 1; /*!< [5..5] THR empty flag */ + __IM uint32_t TEMT : 1; /*!< [6..6] Transmitter empty flag */ + __IM uint32_t RXFE : 1; /*!< [7..7] Receiver FIFO error flag */ + uint32_t : 24; + } LS_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t SP; /*!< (@ 0x0000001C) Offset:0x1C UARTn Scratch Pad Register */ + + struct { + __IOM uint32_t PAD : 8; /*!< [7..0] Pad informaton */ + uint32_t : 24; + } SP_b; + } ; + + union { + __IOM uint32_t ABCTRL; /*!< (@ 0x00000020) Offset:0x20 UARTn Auto-baud Control Register */ + + struct { + __IOM uint32_t START : 1; /*!< [0..0] Auto-baud run bit */ + __IOM uint32_t MODE : 1; /*!< [1..1] Auto-baud mode selection */ + __IOM uint32_t AUTORESTART : 1; /*!< [2..2] Restart mode selection */ + uint32_t : 5; + __OM uint32_t ABEOIFC : 1; /*!< [8..8] Clear ABEOIF flag */ + __OM uint32_t ABTOIFC : 1; /*!< [9..9] Clear ABTOIF flag */ + uint32_t : 22; + } ABCTRL_b; + } ; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t FD; /*!< (@ 0x00000028) Offset:0x28 UARTn Fractional Divider Register */ + + struct { + __IOM uint32_t DIVADDVAL : 4; /*!< [3..0] Baud rate generation prescaler divisor value */ + __IOM uint32_t MULVAL : 4; /*!< [7..4] Baud rate generation prescaler multiplier value */ + __IOM uint32_t OVER8 : 1; /*!< [8..8] Oversampling value */ + uint32_t : 23; + } FD_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000030) Offset:0x30 UARTn Control Register */ + + struct { + __IOM uint32_t UARTEN : 1; /*!< [0..0] USART enable */ + __IOM uint32_t MODE : 3; /*!< [3..1] UART mode */ + uint32_t : 2; + __IOM uint32_t RXEN : 1; /*!< [6..6] RX enable */ + __IOM uint32_t TXEN : 1; /*!< [7..7] TX enable */ + uint32_t : 24; + } CTRL_b; + } ; + + union { + __IOM uint32_t HDEN; /*!< (@ 0x00000034) Offset:0x34 UARTn Control Register */ + + struct { + __IOM uint32_t HDEN : 1; /*!< [0..0] Half-duplex mode enable */ + uint32_t : 31; + } HDEN_b; + } ; +} SN_UART0_Type; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_I2S0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2S (SN_I2S0) + */ + +typedef struct { /*!< (@ 0x4001A000) SN_I2S0 Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 I2Sn Control Register */ + + struct { + __IOM uint32_t START : 1; /*!< [0..0] Start Transmit/Receive */ + __IOM uint32_t MUTE : 1; /*!< [1..1] Mute enable */ + __IOM uint32_t MONO : 1; /*!< [2..2] Mono/stereo selection */ + __IOM uint32_t MS : 1; /*!< [3..3] Master/Slave selection bit */ + __IOM uint32_t FORMAT : 2; /*!< [5..4] I2S operation format */ + __IOM uint32_t TXEN : 1; /*!< [6..6] Transmit enable bit */ + __IOM uint32_t RXEN : 1; /*!< [7..7] Receiver enable bit */ + __OM uint32_t CLRTXFIFO : 1; /*!< [8..8] Clear I2S TX FIFO */ + __OM uint32_t CLRRXFIFO : 1; /*!< [9..9] Clear I2S RX FIFO */ + __IOM uint32_t DL : 2; /*!< [11..10] Data length */ + __IOM uint32_t TXFIFOTH : 3; /*!< [14..12] TX FIFO threshold level */ + uint32_t : 1; + __IOM uint32_t RXFIFOTH : 3; /*!< [18..16] RX FIFO threshold level */ + uint32_t : 1; + __IOM uint32_t CHLENGTH : 5; /*!< [24..20] Bit number of single channel */ + uint32_t : 6; + __IOM uint32_t I2SEN : 1; /*!< [31..31] I2S enable */ + } CTRL_b; + } ; + + union { + __IOM uint32_t CLK; /*!< (@ 0x00000004) Offset:0x04 I2Sn Clock Register */ + + struct { + __IOM uint32_t MCLKDIV : 3; /*!< [2..0] MCLK divider */ + __IOM uint32_t MCLKOEN : 1; /*!< [3..3] MLCK output enable */ + __IOM uint32_t MCLKSEL : 1; /*!< [4..4] MLCK source selection */ + uint32_t : 3; + __IOM uint32_t BCLKDIV : 8; /*!< [15..8] BCLK divider */ + __IOM uint32_t CLKSEL : 1; /*!< [16..16] I2S clock source */ + uint32_t : 15; + } CLK_b; + } ; + + union { + __IM uint32_t STATUS; /*!< (@ 0x00000008) Offset:0x08 I2Sn Status Register */ + + struct { + __IM uint32_t I2SINT : 1; /*!< [0..0] I2S interrupt flag */ + __IM uint32_t RIGHTCH : 1; /*!< [1..1] Current channel status */ + uint32_t : 4; + __IM uint32_t TXFIFOTHF : 1; /*!< [6..6] TX FIFO threshold flag */ + __IM uint32_t RXFIFOTHF : 1; /*!< [7..7] RX FIFO threshold flag */ + __IM uint32_t TXFIFOFULL : 1; /*!< [8..8] TX FIFO full flag */ + __IM uint32_t RXFIFOFULL : 1; /*!< [9..9] RX FIFO full flag */ + __IM uint32_t TXFIFOEMPTY : 1; /*!< [10..10] TX FIFO empty flag */ + __IM uint32_t RXFIFOEMPTY : 1; /*!< [11..11] RX FIFO empty flag */ + __IM uint32_t TXFIFOLV : 4; /*!< [15..12] TX FIFO used level */ + uint32_t : 1; + __IM uint32_t RXFIFOLV : 4; /*!< [20..17] RX FIFO used level */ + uint32_t : 11; + } STATUS_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x0000000C) Offset:0x0C I2Sn Interrupt Enable Register */ + + struct { + uint32_t : 4; + __IOM uint32_t TXFIFOOVFIEN : 1; /*!< [4..4] TX FIFO overflow interrupt enable */ + __IOM uint32_t RXFIFOUDFIEN : 1; /*!< [5..5] RX FIFO underflow interrupt enable */ + __IOM uint32_t TXFIFOTHIEN : 1; /*!< [6..6] TX FIFO threshold interrupt enable */ + __IOM uint32_t RXFIFOTHIEN : 1; /*!< [7..7] RX FIFO threshold interrupt enable */ + uint32_t : 24; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x00000010) Offset:0x10 I2Sn Raw Interrupt Status Register */ + + struct { + uint32_t : 4; + __IM uint32_t TXFIFOOVIF : 1; /*!< [4..4] TX FIFO overflow interrupt flag */ + __IM uint32_t RXFIFOUDIF : 1; /*!< [5..5] RX FIFO underflow interrupt flag */ + __IM uint32_t TXFIFOTHIF : 1; /*!< [6..6] TX FIFO threshold interrupt flag */ + __IM uint32_t RXFIFOTHIF : 1; /*!< [7..7] RX FIFO threshold interrupt flag */ + uint32_t : 24; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000014) Offset:0x14 I2Sn Interrupt Clear Register */ + + struct { + uint32_t : 4; + __OM uint32_t TXFIFOOVIC : 1; /*!< [4..4] TX FIFO overflow interrupt clear */ + __OM uint32_t RXFIFOUDIC : 1; /*!< [5..5] RX FIFO underflow interrupt clear */ + __OM uint32_t TXFIFOTHIC : 1; /*!< [6..6] TX FIFO threshold interrupt clear */ + __OM uint32_t RXFIFOTHIC : 1; /*!< [7..7] RX FIFO threshold interrupt clear */ + uint32_t : 24; + } IC_b; + } ; + __IM uint32_t RXFIFO; /*!< (@ 0x00000018) Offset:0x18 I2Sn RX FIFO Register */ + __OM uint32_t TXFIFO; /*!< (@ 0x0000001C) Offset:0x1C I2Sn TX FIFO Register */ +} SN_I2S0_Type; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_FLASH ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FLASH Memory Control Registers (SN_FLASH) + */ + +typedef struct { /*!< (@ 0x40062000) SN_FLASH Structure */ + + union { + __IOM uint32_t LPCTRL; /*!< (@ 0x00000000) Offset:0x00 Flash Low Power Control Register */ + + struct { + __IOM uint32_t LPMODE : 6; /*!< [5..0] Flash Low Power mode selection bit */ + uint32_t : 10; + __OM uint32_t FMCKEY : 16; /*!< [31..16] FMC verify key */ + } LPCTRL_b; + } ; + + union { + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Offset:0x04 Flash Status Register */ + + struct { + __IM uint32_t BUSY : 1; /*!< [0..0] Busy flag */ + uint32_t : 1; + __IOM uint32_t ERR : 1; /*!< [2..2] Erase/Error flag */ + uint32_t : 29; + } STATUS_b; + } ; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000008) Offset:0x08 Flash Control Register */ + + struct { + __IOM uint32_t PG : 1; /*!< [0..0] Flash program mode chosen bit */ + __IOM uint32_t PER : 1; /*!< [1..1] Page erase mode chosen bit */ + __IOM uint32_t MER : 1; /*!< [2..2] Mass erase mode chosen bit */ + uint32_t : 3; + __IOM uint32_t START : 1; /*!< [6..6] Start erase/program operation */ + __IOM uint32_t CHK : 1; /*!< [7..7] Checksum calculation chosen */ + uint32_t : 24; + } CTRL_b; + } ; + __IOM uint32_t DATA; /*!< (@ 0x0000000C) Offset:0x0C Flash Data Register */ + __IOM uint32_t ADDR; /*!< (@ 0x00000010) Offset:0x10 Flash Address Register */ + + union { + __IM uint32_t CHKSUM; /*!< (@ 0x00000014) Offset:0x14 Flash Checksum Register */ + + struct { + __IM uint32_t UserROM : 16; /*!< [15..0] Checksum of User ROM */ + __IM uint32_t BootROM : 16; /*!< [31..16] Checksum of Boot ROM */ + } CHKSUM_b; + } ; + + union { + __IM uint32_t CHKSUM1; /*!< (@ 0x00000018) Offset:0x18 Flash Checksum Register 1 */ + + struct { + __IM uint32_t UserROM1 : 16; /*!< [15..0] Checksum of User ROM 1 */ + __IM uint32_t UserROM2 : 16; /*!< [31..16] Checksum of User ROM 2 */ + } CHKSUM1_b; + } ; + + union { + __IM uint32_t CHKSUM2; /*!< (@ 0x0000001C) Offset:0x1C Flash Checksum Register 2 */ + + struct { + __IM uint32_t UserROM3 : 16; /*!< [15..0] Checksum of User ROM 3 */ + __IM uint32_t UserROM4 : 16; /*!< [31..16] Checksum of User ROM 4 */ + } CHKSUM2_b; + } ; +} SN_FLASH_Type; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_LCD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief LCD Driver (SN_LCD) + */ + +typedef struct { /*!< (@ 0x40034000) SN_LCD Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 LCD Control register */ + + struct { + __IOM uint32_t LCDENB : 1; /*!< [0..0] LCD driver enable bit */ + __IOM uint32_t VLCD : 4; /*!< [4..1] VLCD voltage adjustment */ + __IOM uint32_t LCDIDLE : 1; /*!< [5..5] LCD idle state enable bit */ + __IOM uint32_t LCDSFM : 1; /*!< [6..6] LCD single frame function enable bit */ + __IOM uint32_t LSTC : 1; /*!< [7..7] LCD static mode control bit */ + __IOM uint32_t LCDCOM : 2; /*!< [9..8] Duty selection */ + __IOM uint32_t LCDCKS : 1; /*!< [10..10] LCD clock source selection */ + __IOM uint32_t LCDBNK : 1; /*!< [11..11] LCD blank control bit */ + __IOM uint32_t LCDRATE : 2; /*!< [13..12] LCD clock rate */ + __IOM uint32_t LCDBIA : 3; /*!< [16..14] LCD bias resistance selection bit */ + __IOM uint32_t LCDOUT : 1; /*!< [17..17] LCD VLCD/C2/V1 debug pins output control bit */ + uint32_t : 14; + } CTRL_b; + } ; + + union { + __IOM uint32_t FCC; /*!< (@ 0x00000004) Offset:0x04 LCD Frame Counter Control register */ + + struct { + __IOM uint32_t FCENB : 1; /*!< [0..0] LCD frame counter enable bit */ + __IOM uint32_t FCT : 6; /*!< [6..1] LCD frame counter threshold value */ + __IOM uint32_t FCIE : 1; /*!< [7..7] LCD frame interrupt enable bit */ + uint32_t : 24; + } FCC_b; + } ; + + union { + __IOM uint32_t RIS; /*!< (@ 0x00000008) Offset:0x08 LCD Raw Interrupt Status register */ + + struct { + __IOM uint32_t FCIF : 1; /*!< [0..0] LCD frame interrupt flag */ + uint32_t : 31; + } RIS_b; + } ; + + union { + __IOM uint32_t SEGSEL1; /*!< (@ 0x0000000C) Offset:0x0C LCD SEG Select register 1 */ + + struct { + __IOM uint32_t SEG0EN : 1; /*!< [0..0] SEG0 Enable bit */ + __IOM uint32_t SEG1EN : 1; /*!< [1..1] SEG1 Enable bit */ + __IOM uint32_t SEG2EN : 1; /*!< [2..2] SEG2 Enable bit */ + __IOM uint32_t SEG3EN : 1; /*!< [3..3] SEG3 Enable bit */ + __IOM uint32_t SEG4EN : 1; /*!< [4..4] SEG4 Enable bit */ + __IOM uint32_t SEG5EN : 1; /*!< [5..5] SEG5 Enable bit */ + __IOM uint32_t SEG6EN : 1; /*!< [6..6] SEG6 Enable bit */ + __IOM uint32_t SEG7EN : 1; /*!< [7..7] SEG7 Enable bit */ + __IOM uint32_t SEG8EN : 1; /*!< [8..8] SEG8 Enable bit */ + __IOM uint32_t SEG9EN : 1; /*!< [9..9] SEG9 Enable bit */ + __IOM uint32_t SEG10EN : 1; /*!< [10..10] SEG10 Enable bit */ + __IOM uint32_t SEG11EN : 1; /*!< [11..11] SEG11 Enable bit */ + __IOM uint32_t SEG12EN : 1; /*!< [12..12] SEG12 Enable bit */ + __IOM uint32_t SEG13EN : 1; /*!< [13..13] SEG13 Enable bit */ + __IOM uint32_t SEG14EN : 1; /*!< [14..14] SEG14 Enable bit */ + __IOM uint32_t SEG15EN : 1; /*!< [15..15] SEG15 Enable bit */ + __IOM uint32_t SEG16EN : 1; /*!< [16..16] SEG16 Enable bit */ + __IOM uint32_t SEG17EN : 1; /*!< [17..17] SEG17 Enable bit */ + __IOM uint32_t SEG18EN : 1; /*!< [18..18] SEG18 Enable bit */ + __IOM uint32_t SEG19EN : 1; /*!< [19..19] SEG19 Enable bit */ + __IOM uint32_t SEG20EN : 1; /*!< [20..20] SEG20 Enable bit */ + __IOM uint32_t SEG21EN : 1; /*!< [21..21] SEG21 Enable bit */ + __IOM uint32_t SEG22EN : 1; /*!< [22..22] SEG22 Enable bit */ + __IOM uint32_t SEG23EN : 1; /*!< [23..23] SEG23 Enable bit */ + __IOM uint32_t SEG24EN : 1; /*!< [24..24] SEG24 Enable bit */ + __IOM uint32_t SEG25EN : 1; /*!< [25..25] SEG25 Enable bit */ + __IOM uint32_t SEG26EN : 1; /*!< [26..26] SEG26 Enable bit */ + __IOM uint32_t SEG27EN : 1; /*!< [27..27] SEG27 Enable bit */ + __IOM uint32_t SEG28EN : 1; /*!< [28..28] SEG28 Enable bit */ + __IOM uint32_t SEG29EN : 1; /*!< [29..29] SEG29 Enable bit */ + __IOM uint32_t SEG30EN : 1; /*!< [30..30] SEG30 Enable bit */ + __IOM uint32_t SEG31EN : 1; /*!< [31..31] SEG31 Enable bit */ + } SEGSEL1_b; + } ; + + union { + __IOM uint32_t SEGSEL2; /*!< (@ 0x00000010) Offset:0x10 LCD SEG Select register 2 */ + + struct { + __IOM uint32_t SEG32EN : 1; /*!< [0..0] SEG32 Enable bit */ + __IOM uint32_t SEG33EN : 1; /*!< [1..1] SEG33 Enable bit */ + __IOM uint32_t SEG34EN : 1; /*!< [2..2] SEG34 Enable bit */ + __IOM uint32_t SEG35EN : 1; /*!< [3..3] SEG35 Enable bit */ + __IOM uint32_t SEG36EN : 1; /*!< [4..4] SEG36 Enable bit */ + __IOM uint32_t SEG37EN : 1; /*!< [5..5] SEG37 Enable bit */ + __IOM uint32_t SEG38EN : 1; /*!< [6..6] SEG38 Enable bit */ + __IOM uint32_t SEG39EN : 1; /*!< [7..7] SEG39 Enable bit */ + uint32_t : 24; + } SEGSEL2_b; + } ; + + union { + __IOM uint32_t SEGM0; /*!< (@ 0x00000014) Offset:0x14 LCD SEG Memory register 0 */ + + struct { + __IOM uint32_t SEG0 : 8; /*!< [7..0] SEG0 data for COM0~COM7 */ + __IOM uint32_t SEG1 : 8; /*!< [15..8] SEG1 data for COM0~COM7 */ + __IOM uint32_t SEG2 : 8; /*!< [23..16] SEG2 data for COM0~COM7 */ + __IOM uint32_t SEG3 : 8; /*!< [31..24] SEG3 data for COM0~COM7 */ + } SEGM0_b; + } ; + + union { + __IOM uint32_t SEGM1; /*!< (@ 0x00000018) Offset:0x18 LCD SEG Memory register 1 */ + + struct { + __IOM uint32_t SEG4 : 8; /*!< [7..0] SEG4 data for COM0~COM7 */ + __IOM uint32_t SEG5 : 8; /*!< [15..8] SEG5 data for COM0~COM7 */ + __IOM uint32_t SEG6 : 8; /*!< [23..16] SEG6 data for COM0~COM7 */ + __IOM uint32_t SEG7 : 8; /*!< [31..24] SEG7 data for COM0~COM7 */ + } SEGM1_b; + } ; + + union { + __IOM uint32_t SEGM2; /*!< (@ 0x0000001C) Offset:0x1C LCD SEG Memory register 2 */ + + struct { + __IOM uint32_t SEG8 : 8; /*!< [7..0] SEG8 data for COM0~COM7 */ + __IOM uint32_t SEG9 : 8; /*!< [15..8] SEG9 data for COM0~COM7 */ + __IOM uint32_t SEG10 : 8; /*!< [23..16] SEG10 data for COM0~COM7 */ + __IOM uint32_t SEG11 : 8; /*!< [31..24] SEG11 data for COM0~COM7 */ + } SEGM2_b; + } ; + + union { + __IOM uint32_t SEGM3; /*!< (@ 0x00000020) Offset:0x20 LCD SEG Memory register 3 */ + + struct { + __IOM uint32_t SEG12 : 8; /*!< [7..0] SEG12 data for COM0~COM7 */ + __IOM uint32_t SEG13 : 8; /*!< [15..8] SEG13 data for COM0~COM7 */ + __IOM uint32_t SEG14 : 8; /*!< [23..16] SEG14 data for COM0~COM7 */ + __IOM uint32_t SEG15 : 8; /*!< [31..24] SEG15 data for COM0~COM7 */ + } SEGM3_b; + } ; + + union { + __IOM uint32_t SEGM4; /*!< (@ 0x00000024) Offset:0x24 LCD SEG Memory register 4 */ + + struct { + __IOM uint32_t SEG16 : 8; /*!< [7..0] SEG16 data for COM0~COM7 */ + __IOM uint32_t SEG17 : 8; /*!< [15..8] SEG17 data for COM0~COM7 */ + __IOM uint32_t SEG18 : 8; /*!< [23..16] SEG18 data for COM0~COM7 */ + __IOM uint32_t SEG19 : 8; /*!< [31..24] SEG19 data for COM0~COM7 */ + } SEGM4_b; + } ; + + union { + __IOM uint32_t SEGM5; /*!< (@ 0x00000028) Offset:0x28 LCD SEG Memory register 5 */ + + struct { + __IOM uint32_t SEG20 : 8; /*!< [7..0] SEG20 data for COM0~COM7 */ + __IOM uint32_t SEG21 : 8; /*!< [15..8] SEG21 data for COM0~COM7 */ + __IOM uint32_t SEG22 : 8; /*!< [23..16] SEG22 data for COM0~COM7 */ + __IOM uint32_t SEG23 : 8; /*!< [31..24] SEG23 data for COM0~COM7 */ + } SEGM5_b; + } ; + + union { + __IOM uint32_t SEGM6; /*!< (@ 0x0000002C) Offset:0x2C LCD SEG Memory register 6 */ + + struct { + __IOM uint32_t SEG24 : 8; /*!< [7..0] SEG24 data for COM0~COM7 */ + __IOM uint32_t SEG25 : 8; /*!< [15..8] SEG25 data for COM0~COM7 */ + __IOM uint32_t SEG26 : 8; /*!< [23..16] SEG26 data for COM0~COM7 */ + __IOM uint32_t SEG27 : 8; /*!< [31..24] SEG27 data for COM0~COM7 */ + } SEGM6_b; + } ; + + union { + __IOM uint32_t SEGM7; /*!< (@ 0x00000030) Offset:0x30 LCD SEG Memory register 7 */ + + struct { + __IOM uint32_t SEG28 : 8; /*!< [7..0] SEG28 data for COM0~COM7 */ + __IOM uint32_t SEG29 : 8; /*!< [15..8] SEG29 data for COM0~COM7 */ + __IOM uint32_t SEG30 : 8; /*!< [23..16] SEG30 data for COM0~COM7 */ + __IOM uint32_t SEG31 : 8; /*!< [31..24] SEG31 data for COM0~COM7 */ + } SEGM7_b; + } ; + + union { + __IOM uint32_t SEGM8; /*!< (@ 0x00000034) Offset:0x34 LCD SEG Memory register 8 */ + + struct { + __IOM uint32_t SEG32 : 8; /*!< [7..0] SEG32 data for COM0~COM7 */ + __IOM uint32_t SEG33 : 8; /*!< [15..8] SEG33 data for COM0~COM7 */ + __IOM uint32_t SEG34 : 8; /*!< [23..16] SEG34 data for COM0~COM7 */ + __IOM uint32_t SEG35 : 8; /*!< [31..24] SEG35 data for COM0~COM7 */ + } SEGM8_b; + } ; + + union { + __IOM uint32_t SEGM9; /*!< (@ 0x00000038) Offset:0x38 LCD SEG Memory register 9 */ + + struct { + __IOM uint32_t SEG36 : 8; /*!< [7..0] SEG36 data for COM0~COM7 */ + __IOM uint32_t SEG37 : 8; /*!< [15..8] SEG37 data for COM0~COM7 */ + __IOM uint32_t SEG38 : 8; /*!< [23..16] SEG38 data for COM0~COM7 */ + __IOM uint32_t SEG39 : 8; /*!< [31..24] SEG39 data for COM0~COM7 */ + } SEGM9_b; + } ; +} SN_LCD_Type; /*!< Size = 60 (0x3c) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CRC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Cyclic Redundancy Check (SN_CRC) + */ + +typedef struct { /*!< (@ 0x40038000) SN_CRC Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x0 CRC Control Register */ + + struct { + __IOM uint32_t CRC : 2; /*!< [1..0] CRC Polynomial */ + __IOM uint32_t RESET : 1; /*!< [2..2] CRC Reset bit */ + __IOM uint32_t URCRCEN : 1; /*!< [3..3] CRC calculation for the User ROM enable bit */ + __IM uint32_t BUSY : 1; /*!< [4..4] CRC calculation busy flag */ + uint32_t : 27; + } CTRL_b; + } ; + + union { + __IOM uint32_t DATA; /*!< (@ 0x00000004) Offset:0x4 CRC Data Register */ + + struct { + __IOM uint32_t DATA : 32; /*!< [31..0] CRC Data */ + } DATA_b; + } ; +} SN_CRC_Type; /*!< Size = 8 (0x8) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_OPA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief OP Amplifier (SN_OPA) + */ + +typedef struct { /*!< (@ 0x4002A000) SN_OPA Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x0 OPA Control Register */ + + struct { + __IOM uint32_t OP0EN : 1; /*!< [0..0] OP-Amp 0 enable bit */ + uint32_t : 2; + __IOM uint32_t OP0PS : 1; /*!< [3..3] OP-Amp 0 Positive input selection bit */ + __IOM uint32_t OP0NS : 1; /*!< [4..4] OP-Amp 0 Negatiove input selection bit */ + uint32_t : 3; + __IOM uint32_t OP1EN : 1; /*!< [8..8] OP-Amp 1 enable bit */ + uint32_t : 2; + __IOM uint32_t OP1PS : 1; /*!< [11..11] OP-Amp 1 Positive input selection bit */ + __IOM uint32_t OP1NS : 1; /*!< [12..12] OP-Amp 1 Negatiove input selection bit */ + uint32_t : 19; + } CTRL_b; + } ; +} SN_OPA_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_EBI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief External Bus Interface (SN_EBI) + */ + +typedef struct { /*!< (@ 0x40036000) SN_EBI Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x0 EBI Control Register */ + + struct { + __IOM uint32_t MODE0 : 2; /*!< [1..0] EBI bank 0 access mode */ + __IOM uint32_t MODE1 : 2; /*!< [3..2] EBI bank 1 access mode */ + __IOM uint32_t MODE2 : 2; /*!< [5..4] EBI bank 2 access mode */ + __IOM uint32_t MODE3 : 2; /*!< [7..6] EBI bank 3 access mode */ + __IOM uint32_t BANK0EN : 1; /*!< [8..8] EBI bank 0 enable bit */ + __IOM uint32_t BANK1EN : 1; /*!< [9..9] EBI bank 1 enable bit */ + __IOM uint32_t BANK2EN : 1; /*!< [10..10] EBI bank 2 enable bit */ + __IOM uint32_t BANK3EN : 1; /*!< [11..11] EBI bank 3 enable bit */ + __IOM uint32_t BC0EN : 1; /*!< [12..12] Byte control of bank 0 enable bit */ + __IOM uint32_t BC1EN : 1; /*!< [13..13] Byte control of bank 1 enable bit */ + __IOM uint32_t BC2EN : 1; /*!< [14..14] Byte control of bank 2 enable bit */ + __IOM uint32_t BC3EN : 1; /*!< [15..15] Byte control of bank 3 enable bit */ + __IOM uint32_t ARDY0EN : 1; /*!< [16..16] ARDY of bank 0 enable bit */ + __IOM uint32_t ARDY1EN : 1; /*!< [17..17] ARDY of bank 1 enable bit */ + __IOM uint32_t ARDY2EN : 1; /*!< [18..18] ARDY of bank 2 enable bit */ + __IOM uint32_t ARDY3EN : 1; /*!< [19..19] ARDY of bank 3 enable bit */ + __IOM uint32_t IDLETIME : 4; /*!< [23..20] Bus idle time */ + __IOM uint32_t BK8080MODE0 : 1; /*!< [24..24] Bank0 8080 Mode */ + __IOM uint32_t BK8080MODE1 : 1; /*!< [25..25] Bank1 8080 Mode */ + __IOM uint32_t BK8080MODE2 : 1; /*!< [26..26] Bank2 8080 Mode */ + __IOM uint32_t BK8080MODE3 : 1; /*!< [27..27] Bank3 8080 Mode */ + uint32_t : 4; + } CTRL_b; + } ; + + union { + __IOM uint32_t ALCTRL; /*!< (@ 0x00000004) Offset:0x4 EBI Address Latch Control Register */ + + struct { + __IOM uint32_t AL0 : 4; /*!< [3..0] Bank 0 address length=AL0+16 */ + __IOM uint32_t AL1 : 4; /*!< [7..4] Bank 1 address length=AL1+16 */ + __IOM uint32_t AL2 : 4; /*!< [11..8] Bank 2 address length=AL2+16 */ + __IOM uint32_t AL3 : 4; /*!< [15..12] Bank 3 address length=AL3+16 */ + uint32_t : 16; + } ALCTRL_b; + } ; + + union { + __IOM uint32_t STATUS; /*!< (@ 0x00000008) Offset:0x8 EBI Status Register */ + + struct { + __IM uint32_t EBIBUSY : 1; /*!< [0..0] EBI Busy */ + uint32_t : 3; + __IM uint32_t EBIARDY : 1; /*!< [4..4] EBI Asynchronous Ready status */ + uint32_t : 3; + __IOM uint32_t EBINSRST : 1; /*!< [8..8] EBI State machine reset */ + uint32_t : 23; + } STATUS_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t TADDR0; /*!< (@ 0x00000010) Offset:0x10 EBI Address Timing Register 0 */ + + struct { + __IOM uint32_t ADDRSETUP : 4; /*!< [3..0] Address Setup time */ + uint32_t : 4; + __IOM uint32_t ADDRHOLD : 4; /*!< [11..8] Address Hold time */ + uint32_t : 20; + } TADDR0_b; + } ; + + union { + __IOM uint32_t TADDR1; /*!< (@ 0x00000014) Offset:0x14 EBI Address Timing Register 1 */ + + struct { + __IOM uint32_t ADDRSETUP : 4; /*!< [3..0] Address Setup time */ + uint32_t : 4; + __IOM uint32_t ADDRHOLD : 4; /*!< [11..8] Address Hold time */ + uint32_t : 20; + } TADDR1_b; + } ; + + union { + __IOM uint32_t TADDR2; /*!< (@ 0x00000018) Offset:0x18 EBI Address Timing Register 2 */ + + struct { + __IOM uint32_t ADDRSETUP : 4; /*!< [3..0] Address Setup time */ + uint32_t : 4; + __IOM uint32_t ADDRHOLD : 4; /*!< [11..8] Address Hold time */ + uint32_t : 20; + } TADDR2_b; + } ; + + union { + __IOM uint32_t TADDR3; /*!< (@ 0x0000001C) Offset:0x1C EBI Address Timing Register 3 */ + + struct { + __IOM uint32_t ADDRSETUP : 4; /*!< [3..0] Address Setup time */ + uint32_t : 4; + __IOM uint32_t ADDRHOLD : 4; /*!< [11..8] Address Hold time */ + uint32_t : 20; + } TADDR3_b; + } ; + + union { + __IOM uint32_t TREAD0; /*!< (@ 0x00000020) Offset:0x20 EBI Read Timing Register 0 */ + + struct { + __IOM uint32_t RDSETUP : 4; /*!< [3..0] Read Setup time */ + uint32_t : 4; + __IOM uint32_t RDSTRB : 6; /*!< [13..8] Read Strobe time */ + uint32_t : 2; + __IOM uint32_t RDHOLD : 4; /*!< [19..16] Read Hold time */ + uint32_t : 12; + } TREAD0_b; + } ; + + union { + __IOM uint32_t TREAD1; /*!< (@ 0x00000024) Offset:0x24 EBI Read Timing Register 1 */ + + struct { + __IOM uint32_t RDSETUP : 4; /*!< [3..0] Read Setup time */ + uint32_t : 4; + __IOM uint32_t RDSTRB : 6; /*!< [13..8] Read Strobe time */ + uint32_t : 2; + __IOM uint32_t RDHOLD : 4; /*!< [19..16] Read Hold time */ + uint32_t : 12; + } TREAD1_b; + } ; + + union { + __IOM uint32_t TREAD2; /*!< (@ 0x00000028) Offset:0x28 EBI Read Timing Register 2 */ + + struct { + __IOM uint32_t RDSETUP : 4; /*!< [3..0] Read Setup time */ + uint32_t : 4; + __IOM uint32_t RDSTRB : 6; /*!< [13..8] Read Strobe time */ + uint32_t : 2; + __IOM uint32_t RDHOLD : 4; /*!< [19..16] Read Hold time */ + uint32_t : 12; + } TREAD2_b; + } ; + + union { + __IOM uint32_t TREAD3; /*!< (@ 0x0000002C) Offset:0x2C EBI Read Timing Register 3 */ + + struct { + __IOM uint32_t RDSETUP : 4; /*!< [3..0] Read Setup time */ + uint32_t : 4; + __IOM uint32_t RDSTRB : 6; /*!< [13..8] Read Strobe time */ + uint32_t : 2; + __IOM uint32_t RDHOLD : 4; /*!< [19..16] Read Hold time */ + uint32_t : 12; + } TREAD3_b; + } ; + + union { + __IOM uint32_t TWRITE0; /*!< (@ 0x00000030) Offset:0x30 EBI Write Timing Register 0 */ + + struct { + __IOM uint32_t WESETUP : 4; /*!< [3..0] Write Setup time */ + uint32_t : 4; + __IOM uint32_t WESTRB : 6; /*!< [13..8] Write Strobe time */ + uint32_t : 2; + __IOM uint32_t WEHOLD : 4; /*!< [19..16] Write Hold time */ + uint32_t : 12; + } TWRITE0_b; + } ; + + union { + __IOM uint32_t TWRITE1; /*!< (@ 0x00000034) Offset:0x34 EBI Write Timing Register 1 */ + + struct { + __IOM uint32_t WESETUP : 4; /*!< [3..0] Write Setup time */ + uint32_t : 4; + __IOM uint32_t WESTRB : 6; /*!< [13..8] Write Strobe time */ + uint32_t : 2; + __IOM uint32_t WEHOLD : 4; /*!< [19..16] Write Hold time */ + uint32_t : 12; + } TWRITE1_b; + } ; + + union { + __IOM uint32_t TWRITE2; /*!< (@ 0x00000038) Offset:0x38 EBI Write Timing Register 2 */ + + struct { + __IOM uint32_t WESETUP : 4; /*!< [3..0] Write Setup time */ + uint32_t : 4; + __IOM uint32_t WESTRB : 6; /*!< [13..8] Write Strobe time */ + uint32_t : 2; + __IOM uint32_t WEHOLD : 4; /*!< [19..16] Write Hold time */ + uint32_t : 12; + } TWRITE2_b; + } ; + + union { + __IOM uint32_t TWRITE3; /*!< (@ 0x0000003C) Offset:0x3C EBI Write Timing Register 3 */ + + struct { + __IOM uint32_t WESETUP : 4; /*!< [3..0] Write Setup time */ + uint32_t : 4; + __IOM uint32_t WESTRB : 6; /*!< [13..8] Write Strobe time */ + uint32_t : 2; + __IOM uint32_t WEHOLD : 4; /*!< [19..16] Write Hold time */ + uint32_t : 12; + } TWRITE3_b; + } ; + + union { + __IOM uint32_t PR0; /*!< (@ 0x00000040) Offset:0x40 EBI Polarity Register 0 */ + + struct { + __IM uint32_t CSPOL : 1; /*!< [0..0] Chip Select polarity */ + __IM uint32_t OEPOL : 1; /*!< [1..1] Output Enable polarity */ + __IM uint32_t WEPOL : 1; /*!< [2..2] Write Enable polarity */ + __IM uint32_t ALEPOL : 1; /*!< [3..3] Address Latch polarity */ + __IOM uint32_t ARDYPOL : 1; /*!< [4..4] Asynchronous Ready polarity */ + __IM uint32_t UBLBPOL : 1; /*!< [5..5] Upper Byte and Lower Byte polarity */ + uint32_t : 26; + } PR0_b; + } ; + + union { + __IOM uint32_t PR1; /*!< (@ 0x00000044) Offset:0x44 EBI Polarity Register 1 */ + + struct { + __IM uint32_t CSPOL : 1; /*!< [0..0] Chip Select polarity */ + __IM uint32_t OEPOL : 1; /*!< [1..1] Output Enable polarity */ + __IM uint32_t WEPOL : 1; /*!< [2..2] Write Enable polarity */ + __IM uint32_t ALEPOL : 1; /*!< [3..3] Address Latch polarity */ + __IOM uint32_t ARDYPOL : 1; /*!< [4..4] Asynchronous Ready polarity */ + __IM uint32_t UBLBPOL : 1; /*!< [5..5] Upper Byte and Lower Byte polarity */ + uint32_t : 26; + } PR1_b; + } ; + + union { + __IOM uint32_t PR2; /*!< (@ 0x00000048) Offset:0x48 EBI Polarity Register 2 */ + + struct { + __IM uint32_t CSPOL : 1; /*!< [0..0] Chip Select polarity */ + __IM uint32_t OEPOL : 1; /*!< [1..1] Output Enable polarity */ + __IM uint32_t WEPOL : 1; /*!< [2..2] Write Enable polarity */ + __IM uint32_t ALEPOL : 1; /*!< [3..3] Address Latch polarity */ + __IOM uint32_t ARDYPOL : 1; /*!< [4..4] Asynchronous Ready polarity */ + __IM uint32_t UBLBPOL : 1; /*!< [5..5] Upper Byte and Lower Byte polarity */ + uint32_t : 26; + } PR2_b; + } ; + + union { + __IOM uint32_t PR3; /*!< (@ 0x0000004C) Offset:0x4C EBI Polarity Register 3 */ + + struct { + __IM uint32_t CSPOL : 1; /*!< [0..0] Chip Select polarity */ + __IM uint32_t OEPOL : 1; /*!< [1..1] Output Enable polarity */ + __IM uint32_t WEPOL : 1; /*!< [2..2] Write Enable polarity */ + __IM uint32_t ALEPOL : 1; /*!< [3..3] Address Latch polarity */ + __IOM uint32_t ARDYPOL : 1; /*!< [4..4] Asynchronous Ready polarity */ + __IM uint32_t UBLBPOL : 1; /*!< [5..5] Upper Byte and Lower Byte polarity */ + uint32_t : 26; + } PR3_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000050) Offset:0x50 EBI Interrupt Enable Register */ + + struct { + __IOM uint32_t ARDYTOEN : 1; /*!< [0..0] EBI asynchronous ready time-out interrupt enable bit */ + __IOM uint32_t ACCDISEN : 1; /*!< [1..1] Interrupt for accessing the disabled bank enable bit */ + __IOM uint32_t SMRSTEN : 1; /*!< [2..2] Interrupt for issuing a transaction during EBI state + machine reset period enable bit */ + __IOM uint32_t RWERREN : 1; /*!< [3..3] Interrupt for read/writer error enable bit */ + __IOM uint32_t DMAHTIE : 1; /*!< [4..4] DMA half-transfer interrupt enable bit */ + __IOM uint32_t DMATCIE : 1; /*!< [5..5] DMA transfer complete interrupt enable bit */ + uint32_t : 26; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x00000054) Offset:0x54 EBI Interrupt Flag Register */ + + struct { + __IM uint32_t ARDYTOIF : 1; /*!< [0..0] EBI asynchronous ready time-out flag */ + __IM uint32_t ACCDISIF : 1; /*!< [1..1] EBI accessing the disabled bank flag */ + __IM uint32_t SMRSTIF : 1; /*!< [2..2] EBI state machine reset flag */ + __IM uint32_t RWERRIF : 1; /*!< [3..3] EBI read/write error flag */ + __IM uint32_t DMAHTIF : 1; /*!< [4..4] DMA half-transfer flag */ + __IM uint32_t DMATCIF : 1; /*!< [5..5] DMA transfer complete flag */ + uint32_t : 26; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000058) Offset:0x58 EBI Interrupt Clear Register */ + + struct { + __OM uint32_t ARDYTOIC : 1; /*!< [0..0] Select ARDYTOIF flag to be cleared */ + __OM uint32_t ACCDISIC : 1; /*!< [1..1] Select ACCDISIF flag to be cleared */ + __OM uint32_t SMRSTIC : 1; /*!< [2..2] Select SMRSTIF flag to be cleared */ + __OM uint32_t RWERRIC : 1; /*!< [3..3] Select RWERRIF flag to be cleared */ + __OM uint32_t DMAHTIC : 1; /*!< [4..4] Select DMA half-transfer flag to be cleared */ + __OM uint32_t DMATCIC : 1; /*!< [5..5] Select DMA transfer complete flag to be cleared */ + uint32_t : 26; + } IC_b; + } ; + + union { + __IOM uint32_t DMACTRL; /*!< (@ 0x0000005C) Offset:0x5C EBI DMA Control Register */ + + struct { + __IOM uint32_t DMAEN : 1; /*!< [0..0] EBI DMA enable bit */ + __IOM uint32_t SPISELECT : 1; /*!< [1..1] SPIn select bit */ + __IOM uint32_t BANKSELECT : 2; /*!< [3..2] EBI Bank n select bits */ + uint32_t : 28; + } DMACTRL_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t DMACNT; /*!< (@ 0x00000064) Offset:0x64 DMA Number of data transfer register */ + + struct { + __IOM uint32_t CNT : 28; /*!< [27..0] Number of data to DMA RX count transfer */ + uint32_t : 4; + } DMACNT_b; + } ; + + union { + __IOM uint32_t DMAHTCNT; /*!< (@ 0x00000068) Offset:0x68 EBI DMA Half-transfer Register */ + + struct { + __IOM uint32_t HTCNT : 28; /*!< [27..0] Number of data to DMA RX half count transfer */ + uint32_t : 4; + } DMAHTCNT_b; + } ; + + union { + __IM uint32_t CURCNT; /*!< (@ 0x0000006C) Offset:0x6C EBI DMA Current Transfer Data Counter + Register */ + + struct { + __IM uint32_t CURCNT : 28; /*!< [27..0] Number of data to DMA RX half count transfer */ + uint32_t : 4; + } CURCNT_b; + } ; +} SN_EBI_Type; /*!< Size = 112 (0x70) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_USB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal Serial Bus Full Speed Device Interface (USB) (SN_USB) + */ + +typedef struct { /*!< (@ 0x4005C000) SN_USB Structure */ + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000000) Offset:0x00 USB Interrupt Enable Register */ + + struct { + __IOM uint32_t EP1_NAK_EN : 1; /*!< [0..0] EP1 NAK Interrupt Enable */ + __IOM uint32_t EP2_NAK_EN : 1; /*!< [1..1] EP2 NAK Interrupt Enable */ + __IOM uint32_t EP3_NAK_EN : 1; /*!< [2..2] EP3 NAK Interrupt Enable */ + __IOM uint32_t EP4_NAK_EN : 1; /*!< [3..3] EP4 NAK Interrupt Enable */ + __IOM uint32_t EP5_NAK_EN : 1; /*!< [4..4] EP5 NAK Interrupt Enable */ + __IOM uint32_t EP6_NAK_EN : 1; /*!< [5..5] EP6 NAK Interrupt Enable */ + __IOM uint32_t EPN_ACK_EN : 1; /*!< [6..6] EPN ACK Interrupt Enable */ + uint32_t : 21; + __IOM uint32_t BUSWK_IE : 1; /*!< [28..28] USB Bus Wake Up Interrupt Enable */ + __IOM uint32_t USB_IE : 1; /*!< [29..29] USB Event Interrupt Enable */ + __IOM uint32_t USB_SOF_IE : 1; /*!< [30..30] USB SOF Interrupt Enable */ + __IOM uint32_t BUS_IE : 1; /*!< [31..31] Bus Event Interrupt Enable */ + } INTEN_b; + } ; + + union { + __IM uint32_t INSTS; /*!< (@ 0x00000004) Offset:0x04 USB Interrupt Event Status Register */ + + struct { + __IM uint32_t EP1_NAK : 1; /*!< [0..0] Endpoint 1 NAK transaction flag */ + __IM uint32_t EP2_NAK : 1; /*!< [1..1] Endpoint 2 NAK transaction flag */ + __IM uint32_t EP3_NAK : 1; /*!< [2..2] Endpoint 3 NAK transaction flag */ + __IM uint32_t EP4_NAK : 1; /*!< [3..3] Endpoint 4 NAK transaction flag */ + __IM uint32_t EP5_NAK : 1; /*!< [4..4] Endpoint 5 NAK transaction flag */ + __IM uint32_t EP6_NAK : 1; /*!< [5..5] Endpoint 6 NAK transaction flag */ + uint32_t : 2; + __IM uint32_t EP1_ACK : 1; /*!< [8..8] Endpoint 1 ACK transaction flag */ + __IM uint32_t EP2_ACK : 1; /*!< [9..9] Endpoint 2 ACK transaction flag */ + __IM uint32_t EP3_ACK : 1; /*!< [10..10] Endpoint 3 ACK transaction flag */ + __IM uint32_t EP4_ACK : 1; /*!< [11..11] Endpoint 4 ACK transaction flag */ + __IM uint32_t EP5_ACK : 1; /*!< [12..12] Endpoint 5 ACK transaction flag */ + __IM uint32_t EP6_ACK : 1; /*!< [13..13] Endpoint 6 ACK transaction flag */ + uint32_t : 3; + __IM uint32_t ERR_TIMEOUT : 1; /*!< [17..17] Timeout Status */ + __IM uint32_t ERR_SETUP : 1; /*!< [18..18] Wrong Setup data received */ + __IM uint32_t EP0_OUT_STALL : 1; /*!< [19..19] EP0 OUT STALL transaction */ + __IM uint32_t EP0_IN_STALL : 1; /*!< [20..20] EP0 IN STALL Transaction is completed */ + __IM uint32_t EP0_OUT : 1; /*!< [21..21] EP0 OUT ACK Transaction Flag */ + __IM uint32_t EP0_IN : 1; /*!< [22..22] EP0 IN ACK Transaction Flag */ + __IM uint32_t EP0_SETUP : 1; /*!< [23..23] EP0 Setup Transaction Flag */ + __IM uint32_t EP0_PRESETUP : 1; /*!< [24..24] EP0 Setup Token Packet Flag */ + __IM uint32_t BUS_WAKEUP : 1; /*!< [25..25] Bus Wakeup Flag */ + __IM uint32_t USB_SOF : 1; /*!< [26..26] USB SOF packet received flag */ + uint32_t : 2; + __IM uint32_t BUS_RESUME : 1; /*!< [29..29] USB Bus Resume signal flag */ + __IM uint32_t BUS_SUSPEND : 1; /*!< [30..30] USB Bus Suspend signal flag */ + __IM uint32_t BUS_RESET : 1; /*!< [31..31] USB Bus Reset signal flag */ + } INSTS_b; + } ; + + union { + __OM uint32_t INSTSC; /*!< (@ 0x00000008) Offset:0x08 USB Interrupt Event Status Clear + Register */ + + struct { + __OM uint32_t EP1_NAKC : 1; /*!< [0..0] EP1 NAK clear bit */ + __OM uint32_t EP2_NAKC : 1; /*!< [1..1] EP2 NAK clear bit */ + __OM uint32_t EP3_NAKC : 1; /*!< [2..2] EP3 NAK clear bit */ + __OM uint32_t EP4_NAKC : 1; /*!< [3..3] EP4 NAK clear bit */ + __OM uint32_t EP5_NAKC : 1; /*!< [4..4] EP5 NAK clear bit */ + __OM uint32_t EP6_NAKC : 1; /*!< [5..5] EP6 NAK clear bit */ + uint32_t : 2; + __OM uint32_t EP1_ACKC : 1; /*!< [8..8] EP1 ACK clear bit */ + __OM uint32_t EP2_ACKC : 1; /*!< [9..9] EP2 ACK clear bit */ + __OM uint32_t EP3_ACKC : 1; /*!< [10..10] EP3 ACK clear bit */ + __OM uint32_t EP4_ACKC : 1; /*!< [11..11] EP4 ACK clear bit */ + __OM uint32_t EP5_ACKC : 1; /*!< [12..12] EP5 ACK clear bit */ + __OM uint32_t EP6_ACKC : 1; /*!< [13..13] EP6 ACK clear bit */ + uint32_t : 3; + __OM uint32_t ERR_TIMEOUTC : 1; /*!< [17..17] Timeout Error clear bit */ + __OM uint32_t ERR_SETUPC : 1; /*!< [18..18] Error Setup clear bit */ + __OM uint32_t EP0_OUT_STALLC : 1; /*!< [19..19] EP0 OUT STALL clear bit */ + __OM uint32_t EP0_IN_STALLC : 1; /*!< [20..20] EP0 IN STALL clear bit */ + __OM uint32_t EP0_OUTC : 1; /*!< [21..21] EP0 OUT clear bit */ + __OM uint32_t EP0_INC : 1; /*!< [22..22] EP0 IN clear bit */ + __OM uint32_t EP0_SETUPC : 1; /*!< [23..23] EP0 SETUP clear bit */ + __OM uint32_t EP0_PRESETUPC : 1; /*!< [24..24] EP0 PRESETUP clear bit */ + __OM uint32_t BUS_WAKEUPC : 1; /*!< [25..25] Bus Wakeup clear bit */ + __OM uint32_t USB_SOFC : 1; /*!< [26..26] USB SOF clear bit */ + uint32_t : 2; + __OM uint32_t BUS_RESUMEC : 1; /*!< [29..29] USB Bus Resume clear bit */ + uint32_t : 1; + __OM uint32_t BUS_RESETC : 1; /*!< [31..31] USB Bus Reset clear bit */ + } INSTSC_b; + } ; + + union { + __IOM uint32_t ADDR; /*!< (@ 0x0000000C) Offset:0x0C USB Device Address Register */ + + struct { + __IOM uint32_t UADDR : 7; /*!< [6..0] USB device's address */ + uint32_t : 25; + } ADDR_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000010) Offset:0x10 USB Configuration Register */ + + struct { + __IOM uint32_t EP1_DIR : 1; /*!< [0..0] Endpoint 1 IN/OUT direction setting */ + __IOM uint32_t EP2_DIR : 1; /*!< [1..1] Endpoint 2 IN/OUT direction setting */ + __IOM uint32_t EP3_DIR : 1; /*!< [2..2] Endpoint 3 IN/OUT direction setting */ + __IOM uint32_t EP4_DIR : 1; /*!< [3..3] Endpoint 4 IN/OUT direction setting */ + __IOM uint32_t EP5_DIR : 1; /*!< [4..4] Endpoint 5 IN/OUT direction setting */ + __IOM uint32_t EP6_DIR : 1; /*!< [5..5] Endpoint 6 IN/OUT direction setting */ + uint32_t : 20; + __IOM uint32_t DIS_PDEN : 1; /*!< [26..26] Enable internal D+ and D- 175k pull-down resistor */ + __IOM uint32_t ESD_EN : 1; /*!< [27..27] Enable USB anti-ESD protection */ + __IOM uint32_t SIE_EN : 1; /*!< [28..28] USB Serial Interface Engine Enable */ + __IOM uint32_t DPPU_EN : 1; /*!< [29..29] Enable internal D+ 1.5k pull-up resistor */ + __IOM uint32_t PHY_EN : 1; /*!< [30..30] PHY Transceiver Function Enable */ + __IOM uint32_t VREG33_EN : 1; /*!< [31..31] Enable the internal VREG33 ouput */ + } CFG_b; + } ; + + union { + __IOM uint32_t SGCTL; /*!< (@ 0x00000014) Offset:0x14 USB Signal Control Register */ + + struct { + __IOM uint32_t BUS_DN : 1; /*!< [0..0] USB D- state */ + __IOM uint32_t BUS_DP : 1; /*!< [1..1] USB DP state */ + __IOM uint32_t BUS_DRVEN : 1; /*!< [2..2] Enable to drive USB bus */ + uint32_t : 29; + } SGCTL_b; + } ; + + union { + __IOM uint32_t EP0CTL; /*!< (@ 0x00000018) Offset:0x18 USB Endpoint 0 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 20; + __IOM uint32_t OUT_STALL_EN : 1; /*!< [27..27] Enable EP0 OUT STALL handshake */ + __IOM uint32_t IN_STALL_EN : 1; /*!< [28..28] Enable EP0 IN STALL handshake */ + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Enable Endpoint 0 Function */ + } EP0CTL_b; + } ; + + union { + __IOM uint32_t EP1CTL; /*!< (@ 0x0000001C) Offset:0x1C USB Endpoint 1 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 1 Function enable bit */ + } EP1CTL_b; + } ; + + union { + __IOM uint32_t EP2CTL; /*!< (@ 0x00000020) Offset:0x20 USB Endpoint 2 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 2 Function enable bit */ + } EP2CTL_b; + } ; + + union { + __IOM uint32_t EP3CTL; /*!< (@ 0x00000024) Offset:0x24 USB Endpoint 3 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 3 Function enable bit */ + } EP3CTL_b; + } ; + + union { + __IOM uint32_t EP4CTL; /*!< (@ 0x00000028) Offset:0x28 USB Endpoint 4 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 4 Function enable bit */ + } EP4CTL_b; + } ; + + union { + __IOM uint32_t EP5CTL; /*!< (@ 0x0000002C) Offset:0x2C USB Endpoint 5 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 5 Function enable bit */ + } EP5CTL_b; + } ; + + union { + __IOM uint32_t EP6CTL; /*!< (@ 0x00000030) Offset:0x30 USB Endpoint 6 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 6 Function enable bit */ + } EP6CTL_b; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t EPTOGGLE; /*!< (@ 0x0000003C) Offset:0x3C USB Endpoint Data Toggle Register */ + + struct { + __IOM uint32_t ENDP1_DATA01 : 1; /*!< [0..0] Endpoint 1 data toggle bit */ + __IOM uint32_t ENDP2_DATA01 : 1; /*!< [1..1] Endpoint 2 data toggle bit */ + __IOM uint32_t ENDP3_DATA01 : 1; /*!< [2..2] Endpoint 3 data toggle bit */ + __IOM uint32_t ENDP4_DATA01 : 1; /*!< [3..3] Endpoint 4 data toggle bit */ + __IOM uint32_t ENDP5_DATA01 : 1; /*!< [4..4] Endpoint 5 data toggle bit */ + __IOM uint32_t ENDP6_DATA01 : 1; /*!< [5..5] Endpoint 6 data toggle bit */ + uint32_t : 26; + } EPTOGGLE_b; + } ; + __IM uint32_t RESERVED1[2]; + + union { + __IOM uint32_t EP1BUFOS; /*!< (@ 0x00000048) Offset:0x48 USB Endpoint 1 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP1BUFOS_b; + } ; + + union { + __IOM uint32_t EP2BUFOS; /*!< (@ 0x0000004C) Offset:0x4C USB Endpoint 2 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP2BUFOS_b; + } ; + + union { + __IOM uint32_t EP3BUFOS; /*!< (@ 0x00000050) Offset:0x50 USB Endpoint 3 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP3BUFOS_b; + } ; + + union { + __IOM uint32_t EP4BUFOS; /*!< (@ 0x00000054) Offset:0x54 USB Endpoint 4 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP4BUFOS_b; + } ; + + union { + __IOM uint32_t EP5BUFOS; /*!< (@ 0x00000058) Offset:0x58 USB Endpoint 5 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP5BUFOS_b; + } ; + + union { + __IOM uint32_t EP6BUFOS; /*!< (@ 0x0000005C) Offset:0x5C USB Endpoint 6 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP6BUFOS_b; + } ; + + union { + __IM uint32_t FRMNO; /*!< (@ 0x00000060) Offset:0x60 USB Frame Number Register */ + + struct { + __IM uint32_t FRAME_NO : 11; /*!< [10..0] The 11-bit frame number of the SOF packet */ + uint32_t : 21; + } FRMNO_b; + } ; + + union { + __IOM uint32_t PHYPRM; /*!< (@ 0x00000064) Offset:0x64 USB PHY Parameter Register */ + + struct { + __IOM uint32_t PHY_PARAM : 6; /*!< [5..0] USB PHY parameter */ + uint32_t : 26; + } PHYPRM_b; + } ; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t PHYPRM2; /*!< (@ 0x0000006C) Offset:0x6C USB PHY Parameter Register 2 */ + + struct { + __IOM uint32_t PHY_PS : 15; /*!< [14..0] USB PHY parameter 2 */ + uint32_t : 17; + } PHYPRM2_b; + } ; + + union { + __IOM uint32_t PS2CTL; /*!< (@ 0x00000070) Offset:0x70 PS/2 Control Register */ + + struct { + __IOM uint32_t SCKM : 1; /*!< [0..0] PS/2 SCK mode control bit */ + __IOM uint32_t SDAM : 1; /*!< [1..1] PS/2 SDA mode control bit */ + __IOM uint32_t SCK : 1; /*!< [2..2] PS/2 SCK data buffer */ + __IOM uint32_t SDA : 1; /*!< [3..3] PS/2 SDA data buffer */ + uint32_t : 27; + __IOM uint32_t PS2ENB : 1; /*!< [31..31] PS/2 internal 5k ohm pull-up resistor control bit */ + } PS2CTL_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t RWADDR; /*!< (@ 0x00000078) Offset:0x78 USB Read/Write Address Register */ + + struct { + uint32_t : 2; + __IOM uint32_t RWADDR : 6; /*!< [7..2] USB FIFO address to be read or written from/to USB FIFO */ + uint32_t : 24; + } RWADDR_b; + } ; + + union { + __IOM uint32_t RWDATA; /*!< (@ 0x0000007C) Offset:0x7C USB Read/Write Data Register */ + + struct { + __IOM uint32_t RWDATA : 32; /*!< [31..0] Data to be read or written from/to USB FIFO */ + } RWDATA_b; + } ; + + union { + __IOM uint32_t RWSTATUS; /*!< (@ 0x00000080) Offset:0x80 USB Read/Write Status Register */ + + struct { + __IOM uint32_t W_STATUS : 1; /*!< [0..0] Write status of USB FIFO */ + __IOM uint32_t R_STATUS : 1; /*!< [1..1] WRead status of USB FIFO */ + uint32_t : 30; + } RWSTATUS_b; + } ; + + union { + __IOM uint32_t RWADDR2; /*!< (@ 0x00000084) Offset:0x84 USB Read/Write Address Register 2 */ + + struct { + uint32_t : 2; + __IOM uint32_t RWADDR : 6; /*!< [7..2] USB FIFO address to be read or written from/to USB FIFO */ + uint32_t : 24; + } RWADDR2_b; + } ; + + union { + __IOM uint32_t RWDATA2; /*!< (@ 0x00000088) Offset:0x88 USB Read/Write Data Register 2 */ + + struct { + __IOM uint32_t RWDATA : 32; /*!< [31..0] Data to be read or written from/to USB FIFO */ + } RWDATA2_b; + } ; + + union { + __IOM uint32_t RWSTATUS2; /*!< (@ 0x0000008C) Offset:0x8C USB Read/Write Status Register 2 */ + + struct { + __IOM uint32_t W_STATUS : 1; /*!< [0..0] Write status of USB FIFO */ + __IOM uint32_t R_STATUS : 1; /*!< [1..1] WRead status of USB FIFO */ + uint32_t : 30; + } RWSTATUS2_b; + } ; +} SN_USB_Type; /*!< Size = 144 (0x90) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_UC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UC Registers (SN_UC) + */ + +typedef struct { /*!< (@ 0x1FFF2450) SN_UC Structure */ + __IM uint32_t L4BYTE; /*!< (@ 0x00000000) Offset:0x00 UC Low 4 Byte Register */ + __IM uint32_t RESERVED; + __IM uint32_t H4BYTE; /*!< (@ 0x00000008) Offset:0x08 UC High 4 Byte Register */ +} SN_UC_Type; /*!< Size = 12 (0xc) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define SN_SYS0_BASE 0x40060000UL +#define SN_SYS1_BASE 0x4005E000UL +#define SN_PMU_BASE 0x40032000UL +#define SN_PFPA_BASE 0x40042000UL +#define SN_GPIO1_BASE 0x40046000UL +#define SN_GPIO2_BASE 0x40048000UL +#define SN_GPIO3_BASE 0x4004A000UL +#define SN_GPIO0_BASE 0x40044000UL +#define SN_ADC_BASE 0x40026000UL +#define SN_CMP_BASE 0x40028000UL +#define SN_CT16B0_BASE 0x40000000UL +#define SN_CT16B1_BASE 0x40002000UL +#define SN_CT16B2_BASE 0x40004000UL +#define SN_CT16B3_BASE 0x40006000UL +#define SN_CT16B4_BASE 0x40008000UL +#define SN_CT16B5_BASE 0x4000A000UL +#define SN_WDT_BASE 0x40010000UL +#define SN_RTC_BASE 0x40012000UL +#define SN_SPI0_BASE 0x4001C000UL +#define SN_SPI1_BASE 0x40058000UL +#define SN_I2C0_BASE 0x40018000UL +#define SN_I2C1_BASE 0x4005A000UL +#define SN_UART0_BASE 0x40016000UL +#define SN_UART1_BASE 0x40056000UL +#define SN_UART2_BASE 0x40054000UL +#define SN_UART3_BASE 0x40052000UL +#define SN_I2S0_BASE 0x4001A000UL +#define SN_I2S1_BASE 0x40014000UL +#define SN_FLASH_BASE 0x40062000UL +#define SN_LCD_BASE 0x40034000UL +#define SN_CRC_BASE 0x40038000UL +#define SN_OPA_BASE 0x4002A000UL +#define SN_EBI_BASE 0x40036000UL +#define SN_USB_BASE 0x4005C000UL +#define SN_UC_BASE 0x1FFF2450UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define SN_SYS0 ((SN_SYS0_Type*) SN_SYS0_BASE) +#define SN_SYS1 ((SN_SYS1_Type*) SN_SYS1_BASE) +#define SN_PMU ((SN_PMU_Type*) SN_PMU_BASE) +#define SN_PFPA ((SN_PFPA_Type*) SN_PFPA_BASE) +#define SN_GPIO1 ((SN_GPIO1_Type*) SN_GPIO1_BASE) +#define SN_GPIO2 ((SN_GPIO2_Type*) SN_GPIO2_BASE) +#define SN_GPIO3 ((SN_GPIO1_Type*) SN_GPIO3_BASE) +#define SN_GPIO0 ((SN_GPIO1_Type*) SN_GPIO0_BASE) +#define SN_ADC ((SN_ADC_Type*) SN_ADC_BASE) +#define SN_CMP ((SN_CMP_Type*) SN_CMP_BASE) +#define SN_CT16B0 ((SN_CT16B0_Type*) SN_CT16B0_BASE) +#define SN_CT16B1 ((SN_CT16B1_Type*) SN_CT16B1_BASE) +#define SN_CT16B2 ((SN_CT16B2_Type*) SN_CT16B2_BASE) +#define SN_CT16B3 ((SN_CT16B3_Type*) SN_CT16B3_BASE) +#define SN_CT16B4 ((SN_CT16B3_Type*) SN_CT16B4_BASE) +#define SN_CT16B5 ((SN_CT16B5_Type*) SN_CT16B5_BASE) +#define SN_WDT ((SN_WDT_Type*) SN_WDT_BASE) +#define SN_RTC ((SN_RTC_Type*) SN_RTC_BASE) +#define SN_SPI0 ((SN_SPI0_Type*) SN_SPI0_BASE) +#define SN_SPI1 ((SN_SPI1_Type*) SN_SPI1_BASE) +#define SN_I2C0 ((SN_I2C0_Type*) SN_I2C0_BASE) +#define SN_I2C1 ((SN_I2C0_Type*) SN_I2C1_BASE) +#define SN_UART0 ((SN_UART0_Type*) SN_UART0_BASE) +#define SN_UART1 ((SN_UART0_Type*) SN_UART1_BASE) +#define SN_UART2 ((SN_UART0_Type*) SN_UART2_BASE) +#define SN_UART3 ((SN_UART0_Type*) SN_UART3_BASE) +#define SN_I2S0 ((SN_I2S0_Type*) SN_I2S0_BASE) +#define SN_I2S1 ((SN_I2S0_Type*) SN_I2S1_BASE) +#define SN_FLASH ((SN_FLASH_Type*) SN_FLASH_BASE) +#define SN_LCD ((SN_LCD_Type*) SN_LCD_BASE) +#define SN_CRC ((SN_CRC_Type*) SN_CRC_BASE) +#define SN_OPA ((SN_OPA_Type*) SN_OPA_BASE) +#define SN_EBI ((SN_EBI_Type*) SN_EBI_BASE) +#define SN_USB ((SN_USB_Type*) SN_USB_BASE) +#define SN_UC ((SN_UC_Type*) SN_UC_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* SN32F280_H */ + + +/** @} */ /* End of group SN32F280 */ + +/** @} */ /* End of group SONiX Technology Co., Ltd. */ diff --git a/os/common/ext/SONiX/SN32F2xx/SN32F290.h b/os/common/ext/SONiX/SN32F2xx/SN32F290.h new file mode 100644 index 00000000..6a441af4 --- /dev/null +++ b/os/common/ext/SONiX/SN32F2xx/SN32F290.h @@ -0,0 +1,4896 @@ +/* + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontroller, but can be equally used for other + * suitable processor architectures. This file can be freely distributed. + * Modifications to this file shall be clearly marked. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * @file SN32F290.h + * @brief CMSIS HeaderFile + * @version 0.65 + * @date 09. January 2022 + * @note Generated by SVDConv V3.3.35 on Sunday, 09.01.2022 18:50:24 + * from File 'SN32F290.svd', + * last modified on Tuesday, 01.09.2020 10:52:27 + */ + + + +/** @addtogroup SONiX Technology Co., Ltd. + * @{ + */ + + +/** @addtogroup SN32F290 + * @{ + */ + + +#ifndef SN32F290_H +#define SN32F290_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M0 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== SN32F290 Specific Interrupt Numbers ========================================== */ + NDT_IRQn = 0, /*!< 0 Noise Detection */ + USB_IRQn = 1, /*!< 1 USB */ + LCD_IRQn = 2, /*!< 2 LCD Driver */ + I2S0_IRQn = 3, /*!< 3 I2S0 */ + I2S1_IRQn = 4, /*!< 4 I2S1 */ + CMP3_IRQn = 5, /*!< 5 CMP3 */ + SPI0_IRQn = 6, /*!< 6 SPI0 */ + SPI1_IRQn = 7, /*!< 7 SPI1 */ + UART2_IRQn = 8, /*!< 8 UART2 */ + UART3_IRQn = 9, /*!< 9 UART3 */ + I2C0_IRQn = 10, /*!< 10 I2C0 */ + I2C1_IRQn = 11, /*!< 11 I2C1 */ + CMP2_IRQn = 12, /*!< 12 CMP2 */ + UART0_IRQn = 13, /*!< 13 UART0 */ + UART1_IRQn = 14, /*!< 14 UART1 */ + CT16B0_IRQn = 15, /*!< 15 16-bit Timer 0 */ + CT16B1_IRQn = 16, /*!< 16 CT16B1 */ + CT16B2_IRQn = 17, /*!< 17 16-bit Timer 2 */ + CMP1_IRQn = 18, /*!< 18 CMP1 */ + CT16B3_IRQn = 19, /*!< 19 16-bit Timer 3 */ + CT16B4_IRQn = 20, /*!< 20 16-bit Timer 4 */ + CT16B5_IRQn = 21, /*!< 21 16-bit Timer 5 */ + EBI_IRQn = 22, /*!< 22 External Bus Interface */ + RTC_IRQn = 23, /*!< 23 Real-time Clock */ + ADC_IRQn = 24, /*!< 24 ADC */ + WDT_IRQn = 25, /*!< 25 Watchdog Timer */ + LVD_IRQn = 26, /*!< 26 Low Voltage Detection */ + CMP0_IRQn = 27, /*!< 27 CMP0 */ + P3_IRQn = 28, /*!< 28 GPIO3 */ + P2_IRQn = 29, /*!< 29 GPIO2 */ + P1_IRQn = 30, /*!< 30 GPIO1 */ + P0_IRQn = 31 /*!< 31 GPIO0 */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M0 Processor and Core Peripherals =========================== */ +#define __CM0_REV 0x0000U /*!< CM0 Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 0 /*!< MPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0.h" /*!< ARM Cortex-M0 processor and core peripherals */ +#include "system_SN32F2xx.h" /*!< SN32F290 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SYS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System Control Registers 0 (SN_SYS0) + */ + +typedef struct { /*!< (@ 0x40060000) SN_SYS0 Structure */ + + union { + __IOM uint32_t ANBCTRL; /*!< (@ 0x00000000) Offset:0x00 Analog Block Control Register */ + + struct { + __IOM uint32_t IHRCEN : 1; /*!< [0..0] IHRC enable */ + uint32_t : 1; + __IOM uint32_t ELSEN : 1; /*!< [2..2] ELS XTAL enable */ + uint32_t : 1; + __IOM uint32_t EHSEN : 1; /*!< [4..4] EHS XTAL enable */ + __IOM uint32_t EHSFREQ : 1; /*!< [5..5] EHS XTAL frequency range */ + uint32_t : 26; + } ANBCTRL_b; + } ; + + union { + __IOM uint32_t PLLCTRL; /*!< (@ 0x00000004) Offset:0x04 PLL Control Register */ + + struct { + __IOM uint32_t MSEL : 3; /*!< [2..0] M value */ + uint32_t : 2; + __IOM uint32_t PSEL : 1; /*!< [5..5] P value */ + uint32_t : 6; + __IOM uint32_t PLLCLKSEL : 1; /*!< [12..12] PLL clock source */ + uint32_t : 2; + __IOM uint32_t PLLEN : 1; /*!< [15..15] PLL enable */ + uint32_t : 16; + } PLLCTRL_b; + } ; + + union { + __IM uint32_t CSST; /*!< (@ 0x00000008) Offset:0x08 Clock Source Status Register */ + + struct { + __IM uint32_t IHRCRDY : 1; /*!< [0..0] IHRC ready flag */ + uint32_t : 1; + __IM uint32_t ELSRDY : 1; /*!< [2..2] ELS XTAL ready flag */ + uint32_t : 1; + __IM uint32_t EHSRDY : 1; /*!< [4..4] EHS XTAL ready flag */ + uint32_t : 1; + __IM uint32_t PLLRDY : 1; /*!< [6..6] PLL ready flag */ + uint32_t : 25; + } CSST_b; + } ; + + union { + __IOM uint32_t CLKCFG; /*!< (@ 0x0000000C) Offset:0x0C System Clock Configuration Register */ + + struct { + __IOM uint32_t SYSCLKSEL : 3; /*!< [2..0] System clock source selection */ + uint32_t : 1; + __IM uint32_t SYSCLKST : 3; /*!< [6..4] System clock switch status */ + uint32_t : 25; + } CLKCFG_b; + } ; + + union { + __IOM uint32_t AHBCP; /*!< (@ 0x00000010) Offset:0x10 AHB Clock Prescale Register */ + + struct { + __IOM uint32_t AHBPRE : 3; /*!< [2..0] AHB clock source prescaler */ + __IOM uint32_t DIV1P5 : 1; /*!< [3..3] SYSCLK prescaler */ + uint32_t : 28; + } AHBCP_b; + } ; + + union { + __IOM uint32_t RSTST; /*!< (@ 0x00000014) Offset:0x14 System Reset Status Register */ + + struct { + __IOM uint32_t SWRSTF : 1; /*!< [0..0] Software reset flag */ + __IOM uint32_t WDTRSTF : 1; /*!< [1..1] WDT reset flag */ + __IOM uint32_t LVDRSTF : 1; /*!< [2..2] LVD reset flag */ + __IOM uint32_t EXTRSTF : 1; /*!< [3..3] External reset flag */ + __IOM uint32_t PORRSTF : 1; /*!< [4..4] POR reset flag */ + uint32_t : 27; + } RSTST_b; + } ; + + union { + __IOM uint32_t LVDCTRL; /*!< (@ 0x00000018) Offset:0x18 LVD Control Register */ + + struct { + __IOM uint32_t LVDRSTLVL : 3; /*!< [2..0] LVD reset level */ + uint32_t : 1; + __IOM uint32_t LVDINTLVL : 3; /*!< [6..4] LVD interrupt level */ + uint32_t : 7; + __IOM uint32_t LVDRSTEN : 1; /*!< [14..14] LVD Reset enable */ + __IOM uint32_t LVDEN : 1; /*!< [15..15] LVD enable */ + uint32_t : 16; + } LVDCTRL_b; + } ; + + union { + __IOM uint32_t EXRSTCTRL; /*!< (@ 0x0000001C) Offset:0x1C External Reset Pin Control Register */ + + struct { + __IOM uint32_t RESETDIS : 1; /*!< [0..0] External reset pin disable */ + uint32_t : 31; + } EXRSTCTRL_b; + } ; + + union { + __IOM uint32_t SWDCTRL; /*!< (@ 0x00000020) Offset:0x20 SWD Pin Control Register */ + + struct { + __IOM uint32_t SWDDIS : 1; /*!< [0..0] SWD pin disable */ + uint32_t : 31; + } SWDCTRL_b; + } ; + + union { + __IOM uint32_t IVTM; /*!< (@ 0x00000024) Offset:0x24 Interrupt Vector Table Mapping register */ + + struct { + __IOM uint32_t IVTM : 3; /*!< [2..0] Interrupt table mapping selection */ + uint32_t : 13; + __OM uint32_t IVTMKEY : 16; /*!< [31..16] IVTM register key */ + } IVTM_b; + } ; + + union { + __IOM uint32_t NDTCTRL; /*!< (@ 0x00000028) Offset:0x28 Noise Detect Control Register */ + + struct { + uint32_t : 1; + __IOM uint32_t NDT5V_IE : 1; /*!< [1..1] NDT for VDD 5V interrupt enable bit */ + uint32_t : 30; + } NDTCTRL_b; + } ; + + union { + __IOM uint32_t NDTSTS; /*!< (@ 0x0000002C) Offset:0x2C Noise Detect Status Register */ + + struct { + uint32_t : 1; + __IOM uint32_t NDT5V_DET : 1; /*!< [1..1] Power noise status of NDT5V */ + uint32_t : 30; + } NDTSTS_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t IHRCADJ; /*!< (@ 0x00000034) Offset:0x34 IHRC Frequency Adjustment register */ + + struct { + __IOM uint32_t ADJEN : 1; /*!< [0..0] IHRC frequency adjustment enable bit */ + __IOM uint32_t DIR : 1; /*!< [1..1] IHRC frequency adjusting direction bit */ + uint32_t : 2; + __IOM uint32_t ADJ : 8; /*!< [11..4] IHRC frequency adjusting bits */ + uint32_t : 4; + __OM uint32_t SYSKEY : 16; /*!< [31..16] System register key */ + } IHRCADJ_b; + } ; +} SN_SYS0_Type; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SYS1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System Control Registers 1 (SN_SYS1) + */ + +typedef struct { /*!< (@ 0x4005E000) SN_SYS1 Structure */ + + union { + __IOM uint32_t AHBCLKEN; /*!< (@ 0x00000000) Offset:0x00 AHB Clock Enable Register */ + + struct { + uint32_t : 3; + __IOM uint32_t OPACLKEN : 1; /*!< [3..3] Enable AHB clock for OPA */ + __IOM uint32_t USBCLKEN : 1; /*!< [4..4] Enable AHB clock for USB */ + __IOM uint32_t CT16B0CLKEN : 1; /*!< [5..5] Enable AHB clock for CT16B0 */ + __IOM uint32_t CT16B1CLKEN : 1; /*!< [6..6] Enable AHB clock for CT16B1 */ + __IOM uint32_t CT16B2CLKEN : 1; /*!< [7..7] Enable AHB clock for CT16B2 */ + __IOM uint32_t CT16B3CLKEN : 1; /*!< [8..8] Enable AHB clock for CT16B3 */ + __IOM uint32_t CT16B4CLKEN : 1; /*!< [9..9] Enable AHB clock for CT16B4 */ + __IOM uint32_t CT16B5CLKEN : 1; /*!< [10..10] Enable AHB clock for CT16B5 */ + __IOM uint32_t ADCCLKEN : 1; /*!< [11..11] Enable AHB clock for ADC */ + __IOM uint32_t SPI0CLKEN : 1; /*!< [12..12] Enable AHB clock for SPI0 */ + __IOM uint32_t SPI1CLKEN : 1; /*!< [13..13] Enable AHB clock for SPI1 */ + __IOM uint32_t CMPCLKEN : 1; /*!< [14..14] Enable AHB clock for CMP */ + __IOM uint32_t EBICLKEN : 1; /*!< [15..15] Enable AHB clock for EBI */ + __IOM uint32_t UART0CLKEN : 1; /*!< [16..16] Enable AHB clock for UART0 */ + __IOM uint32_t UART1CLKEN : 1; /*!< [17..17] Enable AHB clock for UART1 */ + __IOM uint32_t UART2CLKEN : 1; /*!< [18..18] Enable AHB clock for UART2 */ + __IOM uint32_t UART3CLKEN : 1; /*!< [19..19] Enable AHB clock for UART3 */ + __IOM uint32_t I2C1CLKEN : 1; /*!< [20..20] Enable AHB clock for I2C1 */ + __IOM uint32_t I2C0CLKEN : 1; /*!< [21..21] Enable AHB clock for I2C0 */ + __IOM uint32_t I2S0CLKEN : 1; /*!< [22..22] Enable AHB clock for I2S0 */ + __IOM uint32_t RTCCLKEN : 1; /*!< [23..23] Enable AHB clock for RTC */ + __IOM uint32_t WDTCLKEN : 1; /*!< [24..24] Enable AHB clock for WDT */ + __IOM uint32_t I2S1CLKEN : 1; /*!< [25..25] Enable AHB clock for I2S1 */ + __IOM uint32_t LCDCLKEN : 1; /*!< [26..26] Enable AHB clock for LCD */ + __IOM uint32_t CRCCLKEN : 1; /*!< [27..27] Enable AHB clock for CRC */ + __IOM uint32_t CLKOUTSEL : 3; /*!< [30..28] Clock output source selection */ + uint32_t : 1; + } AHBCLKEN_b; + } ; + + union { + __IOM uint32_t APBCP0; /*!< (@ 0x00000004) Offset:0x04 APB Clock Prescale Register 0 */ + + struct { + uint32_t : 16; + __IOM uint32_t ADCPRE : 3; /*!< [18..16] ADC APB clock source prescaler */ + uint32_t : 13; + } APBCP0_b; + } ; + + union { + __IOM uint32_t APBCP1; /*!< (@ 0x00000008) Offset:0x08 APB Clock Prescale Register 1 */ + + struct { + uint32_t : 8; + __OM uint32_t I2C0PRE : 3; /*!< [10..8] I2C0 APB clock source prescaler */ + uint32_t : 1; + __IOM uint32_t I2S0PRE : 3; /*!< [14..12] I2S0 APB clock source prescaler */ + __IOM uint32_t I2S1PRE : 3; /*!< [17..15] I2S1 APB clock source prescaler */ + uint32_t : 2; + __IOM uint32_t WDTPRE : 3; /*!< [22..20] WDT APB clock source prescaler */ + uint32_t : 1; + __OM uint32_t I2C1PRE : 3; /*!< [26..24] I2C1 APB clock source prescaler */ + uint32_t : 1; + __IOM uint32_t CLKOUTPRE : 3; /*!< [30..28] CLKOUT APB clock source prescaler */ + uint32_t : 1; + } APBCP1_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t PRST; /*!< (@ 0x00000010) Offset:0x10 Peripheral Reset Register */ + + struct { + __IOM uint32_t GPIO0RST : 1; /*!< [0..0] GPIO0 Reset */ + __IOM uint32_t GPIO1RST : 1; /*!< [1..1] GPIO1 Reset */ + __IOM uint32_t GPIO2RST : 1; /*!< [2..2] GPIO2 Reset */ + __IOM uint32_t GPIO3RST : 1; /*!< [3..3] GPIO3 Reset */ + __IOM uint32_t EBIRST : 1; /*!< [4..4] EBI Reset */ + __IOM uint32_t CT16B0RST : 1; /*!< [5..5] CT16B0 Reset */ + __IOM uint32_t CT16B1RST : 1; /*!< [6..6] CT16B1 Reset */ + __IOM uint32_t CT16B2RST : 1; /*!< [7..7] CT16B2 Reset */ + __IOM uint32_t CT16B3RST : 1; /*!< [8..8] CT16B3 Reset */ + __IOM uint32_t CT16B4RST : 1; /*!< [9..9] CT16B4 Reset */ + __IOM uint32_t CT16B5RST : 1; /*!< [10..10] CT16B5 Reset */ + __IOM uint32_t ADCRST : 1; /*!< [11..11] ADC Reset */ + __IOM uint32_t SPI0RST : 1; /*!< [12..12] SPI0 Reset */ + __IOM uint32_t SPI1RST : 1; /*!< [13..13] SPI1 Reset */ + __IOM uint32_t CMPRST : 1; /*!< [14..14] CMP Reset */ + __IOM uint32_t LCDRST : 1; /*!< [15..15] LCD Reset */ + __IOM uint32_t UART0RST : 1; /*!< [16..16] UART0 Reset */ + __IOM uint32_t UART1RST : 1; /*!< [17..17] UART1 Reset */ + __IOM uint32_t UART2RST : 1; /*!< [18..18] UART2 Reset */ + __IOM uint32_t UART3RST : 1; /*!< [19..19] UART1 Reset */ + __IOM uint32_t I2C1RST : 1; /*!< [20..20] I2C1 Reset */ + __IOM uint32_t I2C0RST : 1; /*!< [21..21] I2C0 Reset */ + __IOM uint32_t I2S0RST : 1; /*!< [22..22] I2S0 Reset */ + __IOM uint32_t RTCRST : 1; /*!< [23..23] RTC Reset */ + __IOM uint32_t WDTRST : 1; /*!< [24..24] WDT Reset */ + __IOM uint32_t I2S1RST : 1; /*!< [25..25] I2S1 Reset */ + __IOM uint32_t CRCRST : 1; /*!< [26..26] CRC Reset */ + __IOM uint32_t USBRST : 1; /*!< [27..27] USB Reset */ + __IOM uint32_t OPARST : 1; /*!< [28..28] USB Reset */ + uint32_t : 3; + } PRST_b; + } ; +} SN_SYS1_Type; /*!< Size = 20 (0x14) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_PMU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power Management Unit (SN_PMU) + */ + +typedef struct { /*!< (@ 0x40032000) SN_PMU Structure */ + __IM uint32_t RESERVED[16]; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000040) Offset:0x40 PMU Control Register */ + + struct { + __IOM uint32_t MODE : 3; /*!< [2..0] Low Power mode selection */ + uint32_t : 29; + } CTRL_b; + } ; +} SN_PMU_Type; /*!< Size = 68 (0x44) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_PFPA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Peripheral Function Pin Assignment (SN_PFPA) + */ + +typedef struct { /*!< (@ 0x40042000) SN_PFPA Structure */ + + union { + __IOM uint32_t CT16B0; /*!< (@ 0x00000000) Offset:0x00 PFPA for CT16B0 Register */ + + struct { + __IOM uint32_t PWM0 : 2; /*!< [1..0] CT16B0_PWM0 assigned pin */ + __IOM uint32_t PWM0N : 2; /*!< [3..2] CT16B0_PWM0N assigned pin */ + __IOM uint32_t PWM1 : 2; /*!< [5..4] CT16B0_PWM1 assigned pin */ + __IOM uint32_t PWM1N : 2; /*!< [7..6] CT16B0_PWM1N assigned pin */ + __IOM uint32_t PWM2 : 2; /*!< [9..8] CT16B0_PWM2 assigned pin */ + __IOM uint32_t PWM2N : 2; /*!< [11..10] CT16B0_PWM2N assigned pin */ + __IOM uint32_t PWM3 : 2; /*!< [13..12] CT16B0_PWM3 assigned pin */ + __IOM uint32_t PWM3N : 2; /*!< [15..14] CT16B0_PWM3N assigned pin */ + uint32_t : 16; + } CT16B0_b; + } ; + + union { + __IOM uint32_t CT16B1; /*!< (@ 0x00000004) Offset:0x04 PFPA for CT16B1 Register */ + + struct { + __IOM uint32_t PWM00 : 1; /*!< [0..0] CT16B1_PWM00 assigned pin */ + __IOM uint32_t PWM01 : 1; /*!< [1..1] CT16B1_PWM01 assigned pin */ + __IOM uint32_t PWM02 : 1; /*!< [2..2] CT16B1_PWM02 assigned pin */ + __IOM uint32_t PWM03 : 1; /*!< [3..3] CT16B1_PWM03 assigned pin */ + __IOM uint32_t PWM04 : 1; /*!< [4..4] CT16B1_PWM04 assigned pin */ + __IOM uint32_t PWM05 : 1; /*!< [5..5] CT16B1_PWM05 assigned pin */ + __IOM uint32_t PWM06 : 1; /*!< [6..6] CT16B1_PWM06 assigned pin */ + __IOM uint32_t PWM07 : 1; /*!< [7..7] CT16B1_PWM07 assigned pin */ + __IOM uint32_t PWM08 : 1; /*!< [8..8] CT16B1_PWM08 assigned pin */ + __IOM uint32_t PWM09 : 1; /*!< [9..9] CT16B1_PWM09 assigned pin */ + __IOM uint32_t PWM10 : 1; /*!< [10..10] CT16B1_PWM10 assigned pin */ + __IOM uint32_t PWM11 : 1; /*!< [11..11] CT16B1_PWM11 assigned pin */ + uint32_t : 20; + } CT16B1_b; + } ; + + union { + __IOM uint32_t UART; /*!< (@ 0x00000008) Offset:0x08 PFPA for UART Register */ + + struct { + __IOM uint32_t UTXD0 : 2; /*!< [1..0] UTXD0 assigned pin */ + __IOM uint32_t URXD0 : 2; /*!< [3..2] URXD0 assigned pin */ + __IOM uint32_t UTXD1 : 2; /*!< [5..4] UTXD1 assigned pin */ + __IOM uint32_t URXD1 : 2; /*!< [7..6] URXD1 assigned pin */ + __IOM uint32_t UTXD2 : 2; /*!< [9..8] UTXD2 assigned pin */ + __IOM uint32_t URXD2 : 2; /*!< [11..10] URXD2 assigned pin */ + __IOM uint32_t UTXD3 : 2; /*!< [13..12] UTXD3 assigned pin */ + __IOM uint32_t URXD3 : 2; /*!< [15..14] URXD3 assigned pin */ + uint32_t : 16; + } UART_b; + } ; + + union { + __IOM uint32_t I2C; /*!< (@ 0x0000000C) Offset:0x0C PFPA for I2C Register */ + + struct { + __IOM uint32_t SDA0 : 2; /*!< [1..0] SDA0 assigned pin */ + __IOM uint32_t SCL0 : 2; /*!< [3..2] SCL0 assigned pin */ + __IOM uint32_t SDA1 : 2; /*!< [5..4] SDA1 assigned pin */ + __IOM uint32_t SCL1 : 2; /*!< [7..6] SCL1 assigned pin */ + uint32_t : 24; + } I2C_b; + } ; + + union { + __IOM uint32_t SPI; /*!< (@ 0x00000010) Offset:0x10 PFPA for SPI Register */ + + struct { + __IOM uint32_t MISO0 : 2; /*!< [1..0] MISO0 assigned pin */ + __IOM uint32_t MOSI0 : 2; /*!< [3..2] MOSI0 assigned pin */ + __IOM uint32_t SCK0 : 2; /*!< [5..4] SCK0 assigned pin */ + __IOM uint32_t SEL0 : 2; /*!< [7..6] SEL0 assigned pin */ + __IOM uint32_t MISO1 : 2; /*!< [9..8] MISO1 assigned pin */ + __IOM uint32_t MOSI1 : 2; /*!< [11..10] MOSI1 assigned pin */ + __IOM uint32_t SCK1 : 2; /*!< [13..12] SCK1 assigned pin */ + __IOM uint32_t SEL1 : 2; /*!< [15..14] SEL1 assigned pin */ + uint32_t : 16; + } SPI_b; + } ; + + union { + __IOM uint32_t I2S; /*!< (@ 0x00000014) Offset:0x14 PFPA for I2S Register */ + + struct { + __IOM uint32_t MCLK0 : 2; /*!< [1..0] MCLK0 assigned pin */ + __IOM uint32_t BCLK0 : 2; /*!< [3..2] BCLK0 assigned pin */ + __IOM uint32_t WS0 : 2; /*!< [5..4] WS0 assigned pin */ + __IOM uint32_t DOUT0 : 2; /*!< [7..6] DOUT0 assigned pin */ + __IOM uint32_t DIN0 : 2; /*!< [9..8] DIN0 assigned pin */ + __IOM uint32_t MCLK1 : 2; /*!< [11..10] MCLK1 assigned pin */ + __IOM uint32_t BCLK1 : 2; /*!< [13..12] BCLK1 assigned pin */ + __IOM uint32_t WS1 : 2; /*!< [15..14] WS1 assigned pin */ + __IOM uint32_t DOUT1 : 2; /*!< [17..16] DOUT1 assigned pin */ + __IOM uint32_t DIN1 : 2; /*!< [19..18] DIN1 assigned pin */ + uint32_t : 12; + } I2S_b; + } ; + + union { + __IOM uint32_t CT16B2; /*!< (@ 0x00000018) Offset:0x18 PFPA for CT16B2 Register */ + + struct { + __IOM uint32_t PWM0 : 2; /*!< [1..0] CT16B2_PWM0 assigned pin */ + __IOM uint32_t PWM1 : 2; /*!< [3..2] CT16B2_PWM1 assigned pin */ + __IOM uint32_t PWM2 : 2; /*!< [5..4] CT16B2_PWM2 assigned pin */ + __IOM uint32_t PWM3 : 2; /*!< [7..6] CT16B2_PWM3 assigned pin */ + uint32_t : 24; + } CT16B2_b; + } ; + + union { + __IOM uint32_t CT16B3; /*!< (@ 0x0000001C) Offset:0x1C PFPA for CT16B3 Register */ + + struct { + __IOM uint32_t PWM0 : 2; /*!< [1..0] CT16B3_PWM0 assigned pin */ + __IOM uint32_t PWM0N : 2; /*!< [3..2] CT16B3_PWM0N assigned pin */ + __IOM uint32_t PWM1 : 2; /*!< [5..4] CT16B3_PWM1 assigned pin */ + __IOM uint32_t PWM1N : 2; /*!< [7..6] CT16B0_PWM1N assigned pin */ + uint32_t : 24; + } CT16B3_b; + } ; + + union { + __IOM uint32_t CT16B4; /*!< (@ 0x00000020) Offset:0x20 PFPA for CT16B4 Register */ + + struct { + __IOM uint32_t PWM0 : 2; /*!< [1..0] CT16B4_PWM0 assigned pin */ + __IOM uint32_t PWM0N : 2; /*!< [3..2] CT16B4_PWM0N assigned pin */ + __IOM uint32_t PWM1 : 2; /*!< [5..4] CT16B4_PWM1 assigned pin */ + __IOM uint32_t PWM1N : 2; /*!< [7..6] CT16B4_PWM1N assigned pin */ + uint32_t : 24; + } CT16B4_b; + } ; + + union { + __IOM uint32_t CT16B5; /*!< (@ 0x00000024) Offset:0x24 PFPA for CT16B5 Register */ + + struct { + __IOM uint32_t PWM0 : 2; /*!< [1..0] CT16B5_PWM0 assigned pin */ + __IOM uint32_t PWM1 : 2; /*!< [3..2] CT16B5_PWM1 assigned pin */ + __IOM uint32_t PWM2 : 2; /*!< [5..4] CT16B5_PWM2 assigned pin */ + __IOM uint32_t PWM3 : 2; /*!< [7..6] CT16B5_PWM3 assigned pin */ + uint32_t : 24; + } CT16B5_b; + } ; +} SN_PFPA_Type; /*!< Size = 40 (0x28) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose I/O (SN_GPIO1) + */ + +typedef struct { /*!< (@ 0x40046000) SN_GPIO1 Structure */ + + union { + __IOM uint32_t DATA; /*!< (@ 0x00000000) Offset:0x00 GPIO Port n Data Register */ + + struct { + __IOM uint32_t DATA0 : 1; /*!< [0..0] Data of Pn.0 */ + __IOM uint32_t DATA1 : 1; /*!< [1..1] Data of Pn.1 */ + __IOM uint32_t DATA2 : 1; /*!< [2..2] Data of Pn.2 */ + __IOM uint32_t DATA3 : 1; /*!< [3..3] Data of Pn.3 */ + __IOM uint32_t DATA4 : 1; /*!< [4..4] Data of Pn.4 */ + __IOM uint32_t DATA5 : 1; /*!< [5..5] Data of Pn.5 */ + __IOM uint32_t DATA6 : 1; /*!< [6..6] Data of Pn.6 */ + __IOM uint32_t DATA7 : 1; /*!< [7..7] Data of Pn.7 */ + __IOM uint32_t DATA8 : 1; /*!< [8..8] Data of Pn.8 */ + __IOM uint32_t DATA9 : 1; /*!< [9..9] Data of Pn.9 */ + __IOM uint32_t DATA10 : 1; /*!< [10..10] Data of Pn.10 */ + __IOM uint32_t DATA11 : 1; /*!< [11..11] Data of Pn.11 */ + __IOM uint32_t DATA12 : 1; /*!< [12..12] Data of Pn.12 */ + __IOM uint32_t DATA13 : 1; /*!< [13..13] Data of Pn.13 */ + __IOM uint32_t DATA14 : 1; /*!< [14..14] Data of Pn.14 */ + __IOM uint32_t DATA15 : 1; /*!< [15..15] Data of Pn.15 */ + __IOM uint32_t DATA16 : 1; /*!< [16..16] Data of Pn.16 */ + __IOM uint32_t DATA17 : 1; /*!< [17..17] Data of Pn.17 */ + __IOM uint32_t DATA18 : 1; /*!< [18..18] Data of Pn.18 */ + __IOM uint32_t DATA19 : 1; /*!< [19..19] Data of Pn.19 */ + uint32_t : 12; + } DATA_b; + } ; + + union { + __IOM uint32_t MODE; /*!< (@ 0x00000004) Offset:0x04 GPIO Port n Mode Register */ + + struct { + __IOM uint32_t MODE0 : 1; /*!< [0..0] Mode of Pn.0 */ + __IOM uint32_t MODE1 : 1; /*!< [1..1] Mode of Pn.1 */ + __IOM uint32_t MODE2 : 1; /*!< [2..2] Mode of Pn.2 */ + __IOM uint32_t MODE3 : 1; /*!< [3..3] Mode of Pn.3 */ + __IOM uint32_t MODE4 : 1; /*!< [4..4] Mode of Pn.4 */ + __IOM uint32_t MODE5 : 1; /*!< [5..5] Mode of Pn.5 */ + __IOM uint32_t MODE6 : 1; /*!< [6..6] Mode of Pn.6 */ + __IOM uint32_t MODE7 : 1; /*!< [7..7] Mode of Pn.7 */ + __IOM uint32_t MODE8 : 1; /*!< [8..8] Mode of Pn.8 */ + __IOM uint32_t MODE9 : 1; /*!< [9..9] Mode of Pn.9 */ + __IOM uint32_t MODE10 : 1; /*!< [10..10] Mode of Pn.10 */ + __IOM uint32_t MODE11 : 1; /*!< [11..11] Mode of Pn.11 */ + __IOM uint32_t MODE12 : 1; /*!< [12..12] Mode of Pn.12 */ + __IOM uint32_t MODE13 : 1; /*!< [13..13] Mode of Pn.13 */ + __IOM uint32_t MODE14 : 1; /*!< [14..14] Mode of Pn.14 */ + __IOM uint32_t MODE15 : 1; /*!< [15..15] Mode of Pn.15 */ + __IOM uint32_t MODE16 : 1; /*!< [16..16] Mode of Pn.16 */ + __IOM uint32_t MODE17 : 1; /*!< [17..17] Mode of Pn.17 */ + __IOM uint32_t MODE18 : 1; /*!< [18..18] Mode of Pn.18 */ + __IOM uint32_t MODE19 : 1; /*!< [19..19] Mode of Pn.19 */ + uint32_t : 12; + } MODE_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000008) Offset:0x08 GPIO Port n Configuration Register */ + + struct { + __IOM uint32_t CFG0 : 2; /*!< [1..0] Configuration of Pn.0 */ + __IOM uint32_t CFG1 : 2; /*!< [3..2] Configuration of Pn.1 */ + __IOM uint32_t CFG2 : 2; /*!< [5..4] Configuration of Pn.2 */ + __IOM uint32_t CFG3 : 2; /*!< [7..6] Configuration of Pn.3 */ + __IOM uint32_t CFG4 : 2; /*!< [9..8] Configuration of Pn.4 */ + __IOM uint32_t CFG5 : 2; /*!< [11..10] Configuration of Pn.5 */ + __IOM uint32_t CFG6 : 2; /*!< [13..12] Configuration of Pn.6 */ + __IOM uint32_t CFG7 : 2; /*!< [15..14] Configuration of Pn.7 */ + __IOM uint32_t CFG8 : 2; /*!< [17..16] Configuration of Pn.8 */ + __IOM uint32_t CFG9 : 2; /*!< [19..18] Configuration of Pn.9 */ + __IOM uint32_t CFG10 : 2; /*!< [21..20] Configuration of Pn.10 */ + __IOM uint32_t CFG11 : 2; /*!< [23..22] Configuration of Pn.11 */ + __IOM uint32_t CFG12 : 2; /*!< [25..24] Configuration of Pn.12 */ + __IOM uint32_t CFG13 : 2; /*!< [27..26] Configuration of Pn.13 */ + __IOM uint32_t CFG14 : 2; /*!< [29..28] Configuration of Pn.14 */ + __IOM uint32_t CFG15 : 2; /*!< [31..30] Configuration of Pn.15 */ + } CFG_b; + } ; + + union { + __IOM uint32_t IS; /*!< (@ 0x0000000C) Offset:0x0C GPIO Port n Interrupt Sense Register */ + + struct { + __IOM uint32_t IS0 : 1; /*!< [0..0] Interrupt on Pn.0 is event or edge sensitive */ + __IOM uint32_t IS1 : 1; /*!< [1..1] Interrupt on Pn.1 is event or edge sensitive */ + __IOM uint32_t IS2 : 1; /*!< [2..2] Interrupt on Pn.2 is event or edge sensitive */ + __IOM uint32_t IS3 : 1; /*!< [3..3] Interrupt on Pn.3 is event or edge sensitive */ + __IOM uint32_t IS4 : 1; /*!< [4..4] Interrupt on Pn.4 is event or edge sensitive */ + __IOM uint32_t IS5 : 1; /*!< [5..5] Interrupt on Pn.5 is event or edge sensitive */ + __IOM uint32_t IS6 : 1; /*!< [6..6] Interrupt on Pn.6 is event or edge sensitive */ + __IOM uint32_t IS7 : 1; /*!< [7..7] Interrupt on Pn.7 is event or edge sensitive */ + __IOM uint32_t IS8 : 1; /*!< [8..8] Interrupt on Pn.8 is event or edge sensitive */ + __IOM uint32_t IS9 : 1; /*!< [9..9] Interrupt on Pn.9 is event or edge sensitive */ + __IOM uint32_t IS10 : 1; /*!< [10..10] Interrupt on Pn.10 is event or edge sensitive */ + __IOM uint32_t IS11 : 1; /*!< [11..11] Interrupt on Pn.11 is event or edge sensitive */ + __IOM uint32_t IS12 : 1; /*!< [12..12] Interrupt on Pn.12 is event or edge sensitive */ + __IOM uint32_t IS13 : 1; /*!< [13..13] Interrupt on Pn.13 is event or edge sensitive */ + __IOM uint32_t IS14 : 1; /*!< [14..14] Interrupt on Pn.14 is event or edge sensitive */ + __IOM uint32_t IS15 : 1; /*!< [15..15] Interrupt on Pn.15 is event or edge sensitive */ + __IOM uint32_t IS16 : 1; /*!< [16..16] Interrupt on Pn.16 is event or edge sensitive */ + __IOM uint32_t IS17 : 1; /*!< [17..17] Interrupt on Pn.17 is event or edge sensitive */ + __IOM uint32_t IS18 : 1; /*!< [18..18] Interrupt on Pn.18 is event or edge sensitive */ + __IOM uint32_t IS19 : 1; /*!< [19..19] Interrupt on Pn.19 is event or edge sensitive */ + uint32_t : 12; + } IS_b; + } ; + + union { + __IOM uint32_t IBS; /*!< (@ 0x00000010) Offset:0x10 GPIO Port n Interrupt Both-edge Sense + Register */ + + struct { + __IOM uint32_t IBS0 : 1; /*!< [0..0] Interrupt on Pn.0 is triggered ob both edges */ + __IOM uint32_t IBS1 : 1; /*!< [1..1] Interrupt on Pn.1 is triggered ob both edges */ + __IOM uint32_t IBS2 : 1; /*!< [2..2] Interrupt on Pn.2 is triggered ob both edges */ + __IOM uint32_t IBS3 : 1; /*!< [3..3] Interrupt on Pn.3 is triggered ob both edges */ + __IOM uint32_t IBS4 : 1; /*!< [4..4] Interrupt on Pn.4 is triggered ob both edges */ + __IOM uint32_t IBS5 : 1; /*!< [5..5] Interrupt on Pn.5 is triggered ob both edges */ + __IOM uint32_t IBS6 : 1; /*!< [6..6] Interrupt on Pn.6 is triggered ob both edges */ + __IOM uint32_t IBS7 : 1; /*!< [7..7] Interrupt on Pn.7 is triggered ob both edges */ + __IOM uint32_t IBS8 : 1; /*!< [8..8] Interrupt on Pn.8 is triggered ob both edges */ + __IOM uint32_t IBS9 : 1; /*!< [9..9] Interrupt on Pn.9 is triggered ob both edges */ + __IOM uint32_t IBS10 : 1; /*!< [10..10] Interrupt on Pn.10 is triggered ob both edges */ + __IOM uint32_t IBS11 : 1; /*!< [11..11] Interrupt on Pn.11 is triggered ob both edges */ + __IOM uint32_t IBS12 : 1; /*!< [12..12] Interrupt on Pn.12 is triggered ob both edges */ + __IOM uint32_t IBS13 : 1; /*!< [13..13] Interrupt on Pn.13 is triggered ob both edges */ + __IOM uint32_t IBS14 : 1; /*!< [14..14] Interrupt on Pn.14 is triggered ob both edges */ + __IOM uint32_t IBS15 : 1; /*!< [15..15] Interrupt on Pn.15 is triggered ob both edges */ + __IOM uint32_t IBS16 : 1; /*!< [16..16] Interrupt on Pn.16 is triggered ob both edges */ + __IOM uint32_t IBS17 : 1; /*!< [17..17] Interrupt on Pn.17 is triggered ob both edges */ + __IOM uint32_t IBS18 : 1; /*!< [18..18] Interrupt on Pn.18 is triggered ob both edges */ + __IOM uint32_t IBS19 : 1; /*!< [19..19] Interrupt on Pn.19 is triggered ob both edges */ + uint32_t : 12; + } IBS_b; + } ; + + union { + __IOM uint32_t IEV; /*!< (@ 0x00000014) Offset:0x14 GPIO Port n Interrupt Event Register */ + + struct { + __IOM uint32_t IEV0 : 1; /*!< [0..0] Interrupt trigged evnet on Pn.0 */ + __IOM uint32_t IEV1 : 1; /*!< [1..1] Interrupt trigged evnet on Pn.1 */ + __IOM uint32_t IEV2 : 1; /*!< [2..2] Interrupt trigged evnet on Pn.2 */ + __IOM uint32_t IEV3 : 1; /*!< [3..3] Interrupt trigged evnet on Pn.3 */ + __IOM uint32_t IEV4 : 1; /*!< [4..4] Interrupt trigged evnet on Pn.4 */ + __IOM uint32_t IEV5 : 1; /*!< [5..5] Interrupt trigged evnet on Pn.5 */ + __IOM uint32_t IEV6 : 1; /*!< [6..6] Interrupt trigged evnet on Pn.6 */ + __IOM uint32_t IEV7 : 1; /*!< [7..7] Interrupt trigged evnet on Pn.7 */ + __IOM uint32_t IEV8 : 1; /*!< [8..8] Interrupt trigged evnet on Pn.8 */ + __IOM uint32_t IEV9 : 1; /*!< [9..9] Interrupt trigged evnet on Pn.9 */ + __IOM uint32_t IEV10 : 1; /*!< [10..10] Interrupt trigged evnet on Pn.10 */ + __IOM uint32_t IEV11 : 1; /*!< [11..11] Interrupt trigged evnet on Pn.11 */ + __IOM uint32_t IEV12 : 1; /*!< [12..12] Interrupt trigged evnet on Pn.12 */ + __IOM uint32_t IEV13 : 1; /*!< [13..13] Interrupt trigged evnet on Pn.13 */ + __IOM uint32_t IEV14 : 1; /*!< [14..14] Interrupt trigged evnet on Pn.14 */ + __IOM uint32_t IEV15 : 1; /*!< [15..15] Interrupt trigged evnet on Pn.15 */ + __IOM uint32_t IEV16 : 1; /*!< [16..16] Interrupt trigged evnet on Pn.16 */ + __IOM uint32_t IEV17 : 1; /*!< [17..17] Interrupt trigged evnet on Pn.17 */ + __IOM uint32_t IEV18 : 1; /*!< [18..18] Interrupt trigged evnet on Pn.18 */ + __IOM uint32_t IEV19 : 1; /*!< [19..19] Interrupt trigged evnet on Pn.19 */ + uint32_t : 12; + } IEV_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000018) Offset:0x18 GPIO Port n Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] Interrupt on Pn.0 enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] Interrupt on Pn.1 enable */ + __IOM uint32_t IE2 : 1; /*!< [2..2] Interrupt on Pn.2 enable */ + __IOM uint32_t IE3 : 1; /*!< [3..3] Interrupt on Pn.3 enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] Interrupt on Pn.4 enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] Interrupt on Pn.5 enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] Interrupt on Pn.6 enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] Interrupt on Pn.7 enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] Interrupt on Pn.8 enable */ + __IOM uint32_t IE9 : 1; /*!< [9..9] Interrupt on Pn.9 enable */ + __IOM uint32_t IE10 : 1; /*!< [10..10] Interrupt on Pn.10 enable */ + __IOM uint32_t IE11 : 1; /*!< [11..11] Interrupt on Pn.11 enable */ + __IOM uint32_t IE12 : 1; /*!< [12..12] Interrupt on Pn.11 enable */ + __IOM uint32_t IE13 : 1; /*!< [13..13] Interrupt on Pn.13 enable */ + __IOM uint32_t IE14 : 1; /*!< [14..14] Interrupt on Pn.14 enable */ + __IOM uint32_t IE15 : 1; /*!< [15..15] Interrupt on Pn.15 enable */ + __IOM uint32_t IE16 : 1; /*!< [16..16] Interrupt on Pn.16 enable */ + __IOM uint32_t IE17 : 1; /*!< [17..17] Interrupt on Pn.17 enable */ + __IOM uint32_t IE18 : 1; /*!< [18..18] Interrupt on Pn.18 enable */ + __IOM uint32_t IE19 : 1; /*!< [19..19] Interrupt on Pn.19 enable */ + uint32_t : 12; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x0000001C) Offset:0x1C GPIO Port n Raw Interrupt Status + Register */ + + struct { + __IM uint32_t IF0 : 1; /*!< [0..0] Pn.0 raw interrupt flag */ + __IM uint32_t IF1 : 1; /*!< [1..1] Pn.1 raw interrupt flag */ + __IM uint32_t IF2 : 1; /*!< [2..2] Pn.2 raw interrupt flag */ + __IM uint32_t IF3 : 1; /*!< [3..3] Pn.3 raw interrupt flag */ + __IM uint32_t IF4 : 1; /*!< [4..4] Pn.4 raw interrupt flag */ + __IM uint32_t IF5 : 1; /*!< [5..5] Pn.5 raw interrupt flag */ + __IM uint32_t IF6 : 1; /*!< [6..6] Pn.6 raw interrupt flag */ + __IM uint32_t IF7 : 1; /*!< [7..7] Pn.7 raw interrupt flag */ + __IM uint32_t IF8 : 1; /*!< [8..8] Pn.8 raw interrupt flag */ + __IM uint32_t IF9 : 1; /*!< [9..9] Pn.9 raw interrupt flag */ + __IM uint32_t IF10 : 1; /*!< [10..10] Pn.10 raw interrupt flag */ + __IM uint32_t IF11 : 1; /*!< [11..11] Pn.11 raw interrupt flag */ + __IM uint32_t IF12 : 1; /*!< [12..12] Pn.12 raw interrupt flag */ + __IM uint32_t IF13 : 1; /*!< [13..13] Pn.13 raw interrupt flag */ + __IM uint32_t IF14 : 1; /*!< [14..14] Pn.14 raw interrupt flag */ + __IM uint32_t IF15 : 1; /*!< [15..15] Pn.15 raw interrupt flag */ + __IM uint32_t IF16 : 1; /*!< [16..16] Pn.16 raw interrupt flag */ + __IM uint32_t IF17 : 1; /*!< [17..17] Pn.17 raw interrupt flag */ + __IM uint32_t IF18 : 1; /*!< [18..18] Pn.18 raw interrupt flag */ + __IM uint32_t IF19 : 1; /*!< [19..19] Pn.19 raw interrupt flag */ + uint32_t : 12; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000020) Offset:0x20 GPIO Port n Interrupt Clear Register */ + + struct { + __OM uint32_t IC0 : 1; /*!< [0..0] Pn.0 interrupt flag clear */ + __OM uint32_t IC1 : 1; /*!< [1..1] Pn.1 interrupt flag clear */ + __OM uint32_t IC2 : 1; /*!< [2..2] Pn.2 interrupt flag clear */ + __OM uint32_t IC3 : 1; /*!< [3..3] Pn.3 interrupt flag clear */ + __OM uint32_t IC4 : 1; /*!< [4..4] Pn.4 interrupt flag clear */ + __OM uint32_t IC5 : 1; /*!< [5..5] Pn.5 interrupt flag clear */ + __OM uint32_t IC6 : 1; /*!< [6..6] Pn.6 interrupt flag clear */ + __OM uint32_t IC7 : 1; /*!< [7..7] Pn.7 interrupt flag clear */ + __OM uint32_t IC8 : 1; /*!< [8..8] Pn.8 interrupt flag clear */ + __OM uint32_t IC9 : 1; /*!< [9..9] Pn.9 interrupt flag clear */ + __OM uint32_t IC10 : 1; /*!< [10..10] Pn.10 interrupt flag clear */ + __OM uint32_t IC11 : 1; /*!< [11..11] Pn.11 interrupt flag clear */ + __OM uint32_t IC12 : 1; /*!< [12..12] Pn.12 interrupt flag clear */ + __OM uint32_t IC13 : 1; /*!< [13..13] Pn.13 interrupt flag clear */ + __OM uint32_t IC14 : 1; /*!< [14..14] Pn.14 interrupt flag clear */ + __OM uint32_t IC15 : 1; /*!< [15..15] Pn.15 interrupt flag clear */ + __OM uint32_t IC16 : 1; /*!< [16..16] Pn.16 interrupt flag clear */ + __OM uint32_t IC17 : 1; /*!< [17..17] Pn.17 interrupt flag clear */ + __OM uint32_t IC18 : 1; /*!< [18..18] Pn.18 interrupt flag clear */ + __OM uint32_t IC19 : 1; /*!< [19..19] Pn.19 interrupt flag clear */ + uint32_t : 12; + } IC_b; + } ; + + union { + __OM uint32_t BSET; /*!< (@ 0x00000024) Offset:0x24 GPIO Port n Bits Set Operation Register */ + + struct { + __OM uint32_t BSET0 : 1; /*!< [0..0] Set Pn.0 */ + __OM uint32_t BSET1 : 1; /*!< [1..1] Set Pn.1 */ + __OM uint32_t BSET2 : 1; /*!< [2..2] Set Pn.2 */ + __OM uint32_t BSET3 : 1; /*!< [3..3] Set Pn.3 */ + __OM uint32_t BSET4 : 1; /*!< [4..4] Set Pn.4 */ + __OM uint32_t BSET5 : 1; /*!< [5..5] Set Pn.5 */ + __OM uint32_t BSET6 : 1; /*!< [6..6] Set Pn.6 */ + __OM uint32_t BSET7 : 1; /*!< [7..7] Set Pn.7 */ + __OM uint32_t BSET8 : 1; /*!< [8..8] Set Pn.8 */ + __OM uint32_t BSET9 : 1; /*!< [9..9] Set Pn.9 */ + __OM uint32_t BSET10 : 1; /*!< [10..10] Set Pn.10 */ + __OM uint32_t BSET11 : 1; /*!< [11..11] Set Pn.11 */ + __OM uint32_t BSET12 : 1; /*!< [12..12] Set Pn.12 */ + __OM uint32_t BSET13 : 1; /*!< [13..13] Set Pn.13 */ + __OM uint32_t BSET14 : 1; /*!< [14..14] Set Pn.14 */ + __OM uint32_t BSET15 : 1; /*!< [15..15] Set Pn.15 */ + __OM uint32_t BSET16 : 1; /*!< [16..16] Set Pn.16 */ + __OM uint32_t BSET17 : 1; /*!< [17..17] Set Pn.17 */ + __OM uint32_t BSET18 : 1; /*!< [18..18] Set Pn.18 */ + __OM uint32_t BSET19 : 1; /*!< [19..19] Set Pn.19 */ + uint32_t : 12; + } BSET_b; + } ; + + union { + __OM uint32_t BCLR; /*!< (@ 0x00000028) Offset:0x28 GPIO Port n Bits Clear Operation + Register */ + + struct { + __OM uint32_t BCLR0 : 1; /*!< [0..0] Clear Pn.0 */ + __OM uint32_t BCLR1 : 1; /*!< [1..1] Clear Pn.1 */ + __OM uint32_t BCLR2 : 1; /*!< [2..2] Clear Pn.2 */ + __OM uint32_t BCLR3 : 1; /*!< [3..3] Clear Pn.3 */ + __OM uint32_t BCLR4 : 1; /*!< [4..4] Clear Pn.4 */ + __OM uint32_t BCLR5 : 1; /*!< [5..5] Clear Pn.5 */ + __OM uint32_t BCLR6 : 1; /*!< [6..6] Clear Pn.6 */ + __OM uint32_t BCLR7 : 1; /*!< [7..7] Clear Pn.7 */ + __OM uint32_t BCLR8 : 1; /*!< [8..8] Clear Pn.8 */ + __OM uint32_t BCLR9 : 1; /*!< [9..9] Clear Pn.9 */ + __OM uint32_t BCLR10 : 1; /*!< [10..10] Clear Pn.10 */ + __OM uint32_t BCLR11 : 1; /*!< [11..11] Clear Pn.11 */ + __OM uint32_t BCLR12 : 1; /*!< [12..12] Clear Pn.12 */ + __OM uint32_t BCLR13 : 1; /*!< [13..13] Clear Pn.13 */ + __OM uint32_t BCLR14 : 1; /*!< [14..14] Clear Pn.14 */ + __OM uint32_t BCLR15 : 1; /*!< [15..15] Clear Pn.15 */ + __OM uint32_t BCLR16 : 1; /*!< [16..16] Clear Pn.16 */ + __OM uint32_t BCLR17 : 1; /*!< [17..17] Clear Pn.17 */ + __OM uint32_t BCLR18 : 1; /*!< [18..18] Clear Pn.18 */ + __OM uint32_t BCLR19 : 1; /*!< [19..19] Clear Pn.19 */ + uint32_t : 12; + } BCLR_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t CFG1; /*!< (@ 0x00000030) Offset:0x30 GPIO Port n Configuration Register + 1 */ + + struct { + __IOM uint32_t CFG16 : 2; /*!< [1..0] Configuration of Pn.16 */ + __IOM uint32_t CFG17 : 2; /*!< [3..2] Configuration of Pn.17 */ + __IOM uint32_t CFG18 : 2; /*!< [5..4] Configuration of Pn.18 */ + __IOM uint32_t CFG19 : 2; /*!< [7..6] Configuration of Pn.19 */ + uint32_t : 24; + } CFG1_b; + } ; +} SN_GPIO1_Type; /*!< Size = 52 (0x34) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_GPIO2 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose I/O (SN_GPIO2) + */ + +typedef struct { /*!< (@ 0x40048000) SN_GPIO2 Structure */ + + union { + __IOM uint32_t DATA; /*!< (@ 0x00000000) Offset:0x00 GPIO Port n Data Register */ + + struct { + __IOM uint32_t DATA0 : 1; /*!< [0..0] Data of Pn.0 */ + __IOM uint32_t DATA1 : 1; /*!< [1..1] Data of Pn.1 */ + __IOM uint32_t DATA2 : 1; /*!< [2..2] Data of Pn.2 */ + __IOM uint32_t DATA3 : 1; /*!< [3..3] Data of Pn.3 */ + __IOM uint32_t DATA4 : 1; /*!< [4..4] Data of Pn.4 */ + __IOM uint32_t DATA5 : 1; /*!< [5..5] Data of Pn.5 */ + __IOM uint32_t DATA6 : 1; /*!< [6..6] Data of Pn.6 */ + __IOM uint32_t DATA7 : 1; /*!< [7..7] Data of Pn.7 */ + __IOM uint32_t DATA8 : 1; /*!< [8..8] Data of Pn.8 */ + __IOM uint32_t DATA9 : 1; /*!< [9..9] Data of Pn.9 */ + __IOM uint32_t DATA10 : 1; /*!< [10..10] Data of Pn.10 */ + __IOM uint32_t DATA11 : 1; /*!< [11..11] Data of Pn.11 */ + __IOM uint32_t DATA12 : 1; /*!< [12..12] Data of Pn.12 */ + __IOM uint32_t DATA13 : 1; /*!< [13..13] Data of Pn.13 */ + __IOM uint32_t DATA14 : 1; /*!< [14..14] Data of Pn.14 */ + __IOM uint32_t DATA15 : 1; /*!< [15..15] Data of Pn.15 */ + uint32_t : 16; + } DATA_b; + } ; + + union { + __IOM uint32_t MODE; /*!< (@ 0x00000004) Offset:0x04 GPIO Port n Mode Register */ + + struct { + __IOM uint32_t MODE0 : 1; /*!< [0..0] Mode of Pn.0 */ + __IOM uint32_t MODE1 : 1; /*!< [1..1] Mode of Pn.1 */ + __IOM uint32_t MODE2 : 1; /*!< [2..2] Mode of Pn.2 */ + __IOM uint32_t MODE3 : 1; /*!< [3..3] Mode of Pn.3 */ + __IOM uint32_t MODE4 : 1; /*!< [4..4] Mode of Pn.4 */ + __IOM uint32_t MODE5 : 1; /*!< [5..5] Mode of Pn.5 */ + __IOM uint32_t MODE6 : 1; /*!< [6..6] Mode of Pn.6 */ + __IOM uint32_t MODE7 : 1; /*!< [7..7] Mode of Pn.7 */ + __IOM uint32_t MODE8 : 1; /*!< [8..8] Mode of Pn.8 */ + __IOM uint32_t MODE9 : 1; /*!< [9..9] Mode of Pn.9 */ + __IOM uint32_t MODE10 : 1; /*!< [10..10] Mode of Pn.10 */ + __IOM uint32_t MODE11 : 1; /*!< [11..11] Mode of Pn.11 */ + __IOM uint32_t MODE12 : 1; /*!< [12..12] Mode of Pn.12 */ + __IOM uint32_t MODE13 : 1; /*!< [13..13] Mode of Pn.13 */ + __IOM uint32_t MODE14 : 1; /*!< [14..14] Mode of Pn.14 */ + __IOM uint32_t MODE15 : 1; /*!< [15..15] Mode of Pn.15 */ + uint32_t : 16; + } MODE_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000008) Offset:0x08 GPIO Port n Configuration Register */ + + struct { + __IOM uint32_t CFG0 : 2; /*!< [1..0] Configuration of Pn.0 */ + __IOM uint32_t CFG1 : 2; /*!< [3..2] Configuration of Pn.1 */ + __IOM uint32_t CFG2 : 2; /*!< [5..4] Configuration of Pn.2 */ + __IOM uint32_t CFG3 : 2; /*!< [7..6] Configuration of Pn.3 */ + __IOM uint32_t CFG4 : 2; /*!< [9..8] Configuration of Pn.4 */ + __IOM uint32_t CFG5 : 2; /*!< [11..10] Configuration of Pn.5 */ + __IOM uint32_t CFG6 : 2; /*!< [13..12] Configuration of Pn.6 */ + __IOM uint32_t CFG7 : 2; /*!< [15..14] Configuration of Pn.7 */ + __IOM uint32_t CFG8 : 2; /*!< [17..16] Configuration of Pn.8 */ + __IOM uint32_t CFG9 : 2; /*!< [19..18] Configuration of Pn.9 */ + __IOM uint32_t CFG10 : 2; /*!< [21..20] Configuration of Pn.10 */ + __IOM uint32_t CFG11 : 2; /*!< [23..22] Configuration of Pn.11 */ + __IOM uint32_t CFG12 : 2; /*!< [25..24] Configuration of Pn.12 */ + __IOM uint32_t CFG13 : 2; /*!< [27..26] Configuration of Pn.13 */ + __IOM uint32_t CFG14 : 2; /*!< [29..28] Configuration of Pn.14 */ + __IOM uint32_t CFG15 : 2; /*!< [31..30] Configuration of Pn.15 */ + } CFG_b; + } ; + + union { + __IOM uint32_t IS; /*!< (@ 0x0000000C) Offset:0x0C GPIO Port n Interrupt Sense Register */ + + struct { + __IOM uint32_t IS0 : 1; /*!< [0..0] Interrupt on Pn.0 is event or edge sensitive */ + __IOM uint32_t IS1 : 1; /*!< [1..1] Interrupt on Pn.1 is event or edge sensitive */ + __IOM uint32_t IS2 : 1; /*!< [2..2] Interrupt on Pn.2 is event or edge sensitive */ + __IOM uint32_t IS3 : 1; /*!< [3..3] Interrupt on Pn.3 is event or edge sensitive */ + __IOM uint32_t IS4 : 1; /*!< [4..4] Interrupt on Pn.4 is event or edge sensitive */ + __IOM uint32_t IS5 : 1; /*!< [5..5] Interrupt on Pn.5 is event or edge sensitive */ + __IOM uint32_t IS6 : 1; /*!< [6..6] Interrupt on Pn.6 is event or edge sensitive */ + __IOM uint32_t IS7 : 1; /*!< [7..7] Interrupt on Pn.7 is event or edge sensitive */ + __IOM uint32_t IS8 : 1; /*!< [8..8] Interrupt on Pn.8 is event or edge sensitive */ + __IOM uint32_t IS9 : 1; /*!< [9..9] Interrupt on Pn.9 is event or edge sensitive */ + __IOM uint32_t IS10 : 1; /*!< [10..10] Interrupt on Pn.10 is event or edge sensitive */ + __IOM uint32_t IS11 : 1; /*!< [11..11] Interrupt on Pn.11 is event or edge sensitive */ + __IOM uint32_t IS12 : 1; /*!< [12..12] Interrupt on Pn.12 is event or edge sensitive */ + __IOM uint32_t IS13 : 1; /*!< [13..13] Interrupt on Pn.13 is event or edge sensitive */ + __IOM uint32_t IS14 : 1; /*!< [14..14] Interrupt on Pn.14 is event or edge sensitive */ + __IOM uint32_t IS15 : 1; /*!< [15..15] Interrupt on Pn.15 is event or edge sensitive */ + uint32_t : 16; + } IS_b; + } ; + + union { + __IOM uint32_t IBS; /*!< (@ 0x00000010) Offset:0x10 GPIO Port n Interrupt Both-edge Sense + Register */ + + struct { + __IOM uint32_t IBS0 : 1; /*!< [0..0] Interrupt on Pn.0 is triggered ob both edges */ + __IOM uint32_t IBS1 : 1; /*!< [1..1] Interrupt on Pn.1 is triggered ob both edges */ + __IOM uint32_t IBS2 : 1; /*!< [2..2] Interrupt on Pn.2 is triggered ob both edges */ + __IOM uint32_t IBS3 : 1; /*!< [3..3] Interrupt on Pn.3 is triggered ob both edges */ + __IOM uint32_t IBS4 : 1; /*!< [4..4] Interrupt on Pn.4 is triggered ob both edges */ + __IOM uint32_t IBS5 : 1; /*!< [5..5] Interrupt on Pn.5 is triggered ob both edges */ + __IOM uint32_t IBS6 : 1; /*!< [6..6] Interrupt on Pn.6 is triggered ob both edges */ + __IOM uint32_t IBS7 : 1; /*!< [7..7] Interrupt on Pn.7 is triggered ob both edges */ + __IOM uint32_t IBS8 : 1; /*!< [8..8] Interrupt on Pn.8 is triggered ob both edges */ + __IOM uint32_t IBS9 : 1; /*!< [9..9] Interrupt on Pn.9 is triggered ob both edges */ + __IOM uint32_t IBS10 : 1; /*!< [10..10] Interrupt on Pn.10 is triggered ob both edges */ + __IOM uint32_t IBS11 : 1; /*!< [11..11] Interrupt on Pn.11 is triggered ob both edges */ + __IOM uint32_t IBS12 : 1; /*!< [12..12] Interrupt on Pn.12 is triggered ob both edges */ + __IOM uint32_t IBS13 : 1; /*!< [13..13] Interrupt on Pn.13 is triggered ob both edges */ + __IOM uint32_t IBS14 : 1; /*!< [14..14] Interrupt on Pn.14 is triggered ob both edges */ + __IOM uint32_t IBS15 : 1; /*!< [15..15] Interrupt on Pn.15 is triggered ob both edges */ + uint32_t : 16; + } IBS_b; + } ; + + union { + __IOM uint32_t IEV; /*!< (@ 0x00000014) Offset:0x14 GPIO Port n Interrupt Event Register */ + + struct { + __IOM uint32_t IEV0 : 1; /*!< [0..0] Interrupt trigged evnet on Pn.0 */ + __IOM uint32_t IEV1 : 1; /*!< [1..1] Interrupt trigged evnet on Pn.1 */ + __IOM uint32_t IEV2 : 1; /*!< [2..2] Interrupt trigged evnet on Pn.2 */ + __IOM uint32_t IEV3 : 1; /*!< [3..3] Interrupt trigged evnet on Pn.3 */ + __IOM uint32_t IEV4 : 1; /*!< [4..4] Interrupt trigged evnet on Pn.4 */ + __IOM uint32_t IEV5 : 1; /*!< [5..5] Interrupt trigged evnet on Pn.5 */ + __IOM uint32_t IEV6 : 1; /*!< [6..6] Interrupt trigged evnet on Pn.6 */ + __IOM uint32_t IEV7 : 1; /*!< [7..7] Interrupt trigged evnet on Pn.7 */ + __IOM uint32_t IEV8 : 1; /*!< [8..8] Interrupt trigged evnet on Pn.8 */ + __IOM uint32_t IEV9 : 1; /*!< [9..9] Interrupt trigged evnet on Pn.9 */ + __IOM uint32_t IEV10 : 1; /*!< [10..10] Interrupt trigged evnet on Pn.10 */ + __IOM uint32_t IEV11 : 1; /*!< [11..11] Interrupt trigged evnet on Pn.11 */ + __IOM uint32_t IEV12 : 1; /*!< [12..12] Interrupt trigged evnet on Pn.12 */ + __IOM uint32_t IEV13 : 1; /*!< [13..13] Interrupt trigged evnet on Pn.13 */ + __IOM uint32_t IEV14 : 1; /*!< [14..14] Interrupt trigged evnet on Pn.14 */ + __IOM uint32_t IEV15 : 1; /*!< [15..15] Interrupt trigged evnet on Pn.15 */ + uint32_t : 16; + } IEV_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000018) Offset:0x18 GPIO Port n Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] Interrupt on Pn.0 enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] Interrupt on Pn.1 enable */ + __IOM uint32_t IE2 : 1; /*!< [2..2] Interrupt on Pn.2 enable */ + __IOM uint32_t IE3 : 1; /*!< [3..3] Interrupt on Pn.3 enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] Interrupt on Pn.4 enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] Interrupt on Pn.5 enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] Interrupt on Pn.6 enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] Interrupt on Pn.7 enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] Interrupt on Pn.8 enable */ + __IOM uint32_t IE9 : 1; /*!< [9..9] Interrupt on Pn.9 enable */ + __IOM uint32_t IE10 : 1; /*!< [10..10] Interrupt on Pn.10 enable */ + __IOM uint32_t IE11 : 1; /*!< [11..11] Interrupt on Pn.11 enable */ + __IOM uint32_t IE12 : 1; /*!< [12..12] Interrupt on Pn.11 enable */ + __IOM uint32_t IE13 : 1; /*!< [13..13] Interrupt on Pn.13 enable */ + __IOM uint32_t IE14 : 1; /*!< [14..14] Interrupt on Pn.14 enable */ + __IOM uint32_t IE15 : 1; /*!< [15..15] Interrupt on Pn.15 enable */ + uint32_t : 16; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x0000001C) Offset:0x1C GPIO Port n Raw Interrupt Status + Register */ + + struct { + __IM uint32_t IF0 : 1; /*!< [0..0] Pn.0 raw interrupt flag */ + __IM uint32_t IF1 : 1; /*!< [1..1] Pn.1 raw interrupt flag */ + __IM uint32_t IF2 : 1; /*!< [2..2] Pn.2 raw interrupt flag */ + __IM uint32_t IF3 : 1; /*!< [3..3] Pn.3 raw interrupt flag */ + __IM uint32_t IF4 : 1; /*!< [4..4] Pn.4 raw interrupt flag */ + __IM uint32_t IF5 : 1; /*!< [5..5] Pn.5 raw interrupt flag */ + __IM uint32_t IF6 : 1; /*!< [6..6] Pn.6 raw interrupt flag */ + __IM uint32_t IF7 : 1; /*!< [7..7] Pn.7 raw interrupt flag */ + __IM uint32_t IF8 : 1; /*!< [8..8] Pn.8 raw interrupt flag */ + __IM uint32_t IF9 : 1; /*!< [9..9] Pn.9 raw interrupt flag */ + __IM uint32_t IF10 : 1; /*!< [10..10] Pn.10 raw interrupt flag */ + __IM uint32_t IF11 : 1; /*!< [11..11] Pn.11 raw interrupt flag */ + __IM uint32_t IF12 : 1; /*!< [12..12] Pn.12 raw interrupt flag */ + __IM uint32_t IF13 : 1; /*!< [13..13] Pn.13 raw interrupt flag */ + __IM uint32_t IF14 : 1; /*!< [14..14] Pn.14 raw interrupt flag */ + __IM uint32_t IF15 : 1; /*!< [15..15] Pn.15 raw interrupt flag */ + uint32_t : 16; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000020) Offset:0x20 GPIO Port n Interrupt Clear Register */ + + struct { + __OM uint32_t IC0 : 1; /*!< [0..0] Pn.0 interrupt flag clear */ + __OM uint32_t IC1 : 1; /*!< [1..1] Pn.1 interrupt flag clear */ + __OM uint32_t IC2 : 1; /*!< [2..2] Pn.2 interrupt flag clear */ + __OM uint32_t IC3 : 1; /*!< [3..3] Pn.3 interrupt flag clear */ + __OM uint32_t IC4 : 1; /*!< [4..4] Pn.4 interrupt flag clear */ + __OM uint32_t IC5 : 1; /*!< [5..5] Pn.5 interrupt flag clear */ + __OM uint32_t IC6 : 1; /*!< [6..6] Pn.6 interrupt flag clear */ + __OM uint32_t IC7 : 1; /*!< [7..7] Pn.7 interrupt flag clear */ + __OM uint32_t IC8 : 1; /*!< [8..8] Pn.8 interrupt flag clear */ + __OM uint32_t IC9 : 1; /*!< [9..9] Pn.9 interrupt flag clear */ + __OM uint32_t IC10 : 1; /*!< [10..10] Pn.10 interrupt flag clear */ + __OM uint32_t IC11 : 1; /*!< [11..11] Pn.11 interrupt flag clear */ + __OM uint32_t IC12 : 1; /*!< [12..12] Pn.12 interrupt flag clear */ + __OM uint32_t IC13 : 1; /*!< [13..13] Pn.13 interrupt flag clear */ + __OM uint32_t IC14 : 1; /*!< [14..14] Pn.14 interrupt flag clear */ + __OM uint32_t IC15 : 1; /*!< [15..15] Pn.15 interrupt flag clear */ + uint32_t : 16; + } IC_b; + } ; + + union { + __OM uint32_t BSET; /*!< (@ 0x00000024) Offset:0x24 GPIO Port n Bits Set Operation Register */ + + struct { + __OM uint32_t BSET0 : 1; /*!< [0..0] Set Pn.0 */ + __OM uint32_t BSET1 : 1; /*!< [1..1] Set Pn.1 */ + __OM uint32_t BSET2 : 1; /*!< [2..2] Set Pn.2 */ + __OM uint32_t BSET3 : 1; /*!< [3..3] Set Pn.3 */ + __OM uint32_t BSET4 : 1; /*!< [4..4] Set Pn.4 */ + __OM uint32_t BSET5 : 1; /*!< [5..5] Set Pn.5 */ + __OM uint32_t BSET6 : 1; /*!< [6..6] Set Pn.6 */ + __OM uint32_t BSET7 : 1; /*!< [7..7] Set Pn.7 */ + __OM uint32_t BSET8 : 1; /*!< [8..8] Set Pn.8 */ + __OM uint32_t BSET9 : 1; /*!< [9..9] Set Pn.9 */ + __OM uint32_t BSET10 : 1; /*!< [10..10] Set Pn.10 */ + __OM uint32_t BSET11 : 1; /*!< [11..11] Set Pn.11 */ + __OM uint32_t BSET12 : 1; /*!< [12..12] Set Pn.12 */ + __OM uint32_t BSET13 : 1; /*!< [13..13] Set Pn.13 */ + __OM uint32_t BSET14 : 1; /*!< [14..14] Set Pn.14 */ + __OM uint32_t BSET15 : 1; /*!< [15..15] Set Pn.15 */ + uint32_t : 16; + } BSET_b; + } ; + + union { + __OM uint32_t BCLR; /*!< (@ 0x00000028) Offset:0x28 GPIO Port n Bits Clear Operation + Register */ + + struct { + __OM uint32_t BCLR0 : 1; /*!< [0..0] Clear Pn.0 */ + __OM uint32_t BCLR1 : 1; /*!< [1..1] Clear Pn.1 */ + __OM uint32_t BCLR2 : 1; /*!< [2..2] Clear Pn.2 */ + __OM uint32_t BCLR3 : 1; /*!< [3..3] Clear Pn.3 */ + __OM uint32_t BCLR4 : 1; /*!< [4..4] Clear Pn.4 */ + __OM uint32_t BCLR5 : 1; /*!< [5..5] Clear Pn.5 */ + __OM uint32_t BCLR6 : 1; /*!< [6..6] Clear Pn.6 */ + __OM uint32_t BCLR7 : 1; /*!< [7..7] Clear Pn.7 */ + __OM uint32_t BCLR8 : 1; /*!< [8..8] Clear Pn.8 */ + __OM uint32_t BCLR9 : 1; /*!< [9..9] Clear Pn.9 */ + __OM uint32_t BCLR10 : 1; /*!< [10..10] Clear Pn.10 */ + __OM uint32_t BCLR11 : 1; /*!< [11..11] Clear Pn.11 */ + __OM uint32_t BCLR12 : 1; /*!< [12..12] Clear Pn.12 */ + __OM uint32_t BCLR13 : 1; /*!< [13..13] Clear Pn.13 */ + __OM uint32_t BCLR14 : 1; /*!< [14..14] Clear Pn.14 */ + __OM uint32_t BCLR15 : 1; /*!< [15..15] Clear Pn.15 */ + uint32_t : 16; + } BCLR_b; + } ; +} SN_GPIO2_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ADC (SN_ADC) + */ + +typedef struct { /*!< (@ 0x40026000) SN_ADC Structure */ + + union { + __IOM uint32_t ADM; /*!< (@ 0x00000000) Offset:0x00 ADC Management Register */ + + struct { + __IOM uint32_t CHS : 5; /*!< [4..0] ADC input channel */ + __IOM uint32_t GCHS : 1; /*!< [5..5] ADC global channel enable */ + __IOM uint32_t EOC : 1; /*!< [6..6] ADC status */ + __IOM uint32_t ADS : 1; /*!< [7..7] ADC start control */ + __IOM uint32_t ADLEN : 1; /*!< [8..8] ADC resolution */ + __IOM uint32_t ADCKS : 3; /*!< [11..9] ADC clock source divider */ + __IOM uint32_t ADENB : 1; /*!< [12..12] ADC enable */ + __IOM uint32_t AVREFHSEL : 1; /*!< [13..13] ADC high reference voltage source */ + __IOM uint32_t VHS : 3; /*!< [16..14] Internal Ref. voltage source */ + uint32_t : 15; + } ADM_b; + } ; + + union { + __IM uint32_t ADB; /*!< (@ 0x00000004) Offset:0x04 ADC Data Register */ + + struct { + __IM uint32_t ADB : 12; /*!< [11..0] ADB11~ADB4 bits for 8-bit ADC, ADB11~ADB0 bits for 12-bit + ADC */ + uint32_t : 20; + } ADB_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t IE; /*!< (@ 0x0000000C) Offset:0x0C ADC Interrupt Enable Register */ + + struct { + __IOM uint32_t IE0 : 1; /*!< [0..0] AIN0 interrupt enable */ + __IOM uint32_t IE1 : 1; /*!< [1..1] AIN1 interrupt enable */ + __IOM uint32_t IE2 : 1; /*!< [2..2] AIN2 interrupt enable */ + __IOM uint32_t IE3 : 1; /*!< [3..3] AIN3 interrupt enable */ + __IOM uint32_t IE4 : 1; /*!< [4..4] AIN4 interrupt enable */ + __IOM uint32_t IE5 : 1; /*!< [5..5] AIN5 interrupt enable */ + __IOM uint32_t IE6 : 1; /*!< [6..6] AIN6 interrupt enable */ + __IOM uint32_t IE7 : 1; /*!< [7..7] AIN7 interrupt enable */ + __IOM uint32_t IE8 : 1; /*!< [8..8] AIN8 interrupt enable */ + __IOM uint32_t IE9 : 1; /*!< [9..9] AIN9 interrupt enable */ + __IOM uint32_t IE10 : 1; /*!< [10..10] AIN10 interrupt enable */ + __IOM uint32_t IE11 : 1; /*!< [11..11] AIN11 interrupt enable */ + __IOM uint32_t IE12 : 1; /*!< [12..12] AIN12 interrupt enable */ + __IOM uint32_t IE13 : 1; /*!< [13..13] AIN13 interrupt enable */ + __IOM uint32_t IE14 : 1; /*!< [14..14] AIN14 interrupt enable */ + __IOM uint32_t IE15 : 1; /*!< [15..15] AIN15 interrupt enable */ + __IOM uint32_t IE16 : 1; /*!< [16..16] AIN16 interrupt enable */ + __IOM uint32_t IE17 : 1; /*!< [17..17] AIN17 interrupt enable */ + __IOM uint32_t IE18 : 1; /*!< [18..18] AIN18 interrupt enable */ + uint32_t : 13; + } IE_b; + } ; + + union { + __IOM uint32_t RIS; /*!< (@ 0x00000010) Offset:0x10 ADC Raw Interrupt Status Register */ + + struct { + __IOM uint32_t EOCIF0 : 1; /*!< [0..0] AIN0 interrupt flag */ + __IOM uint32_t EOCIF1 : 1; /*!< [1..1] AIN1 interrupt flag */ + __IOM uint32_t EOCIF2 : 1; /*!< [2..2] AIN2 interrupt flag */ + __IOM uint32_t EOCIF3 : 1; /*!< [3..3] AIN0 interrupt flag */ + __IOM uint32_t EOCIF4 : 1; /*!< [4..4] AIN4 interrupt flag */ + __IOM uint32_t EOCIF5 : 1; /*!< [5..5] AIN5 interrupt flag */ + __IOM uint32_t EOCIF6 : 1; /*!< [6..6] AIN6 interrupt flag */ + __IOM uint32_t EOCIF7 : 1; /*!< [7..7] AIN7 interrupt flag */ + __IOM uint32_t EOCIF8 : 1; /*!< [8..8] AIN8 interrupt flag */ + __IOM uint32_t EOCIF9 : 1; /*!< [9..9] AIN9 interrupt flag */ + __IOM uint32_t EOCIF10 : 1; /*!< [10..10] AIN10 interrupt flag */ + __IOM uint32_t EOCIF11 : 1; /*!< [11..11] AIN11 interrupt flag */ + __IOM uint32_t EOCIF12 : 1; /*!< [12..12] AIN12 interrupt flag */ + __IOM uint32_t EOCIF13 : 1; /*!< [13..13] AIN13 interrupt flag */ + __IOM uint32_t EOCIF14 : 1; /*!< [14..14] AIN14 interrupt flag */ + __IOM uint32_t EOCIF15 : 1; /*!< [15..15] AIN15 interrupt flag */ + __IOM uint32_t EOCIF16 : 1; /*!< [16..16] AIN16 interrupt flag */ + __IOM uint32_t EOCIF17 : 1; /*!< [17..17] AIN17 interrupt flag */ + __IOM uint32_t EOCIF18 : 1; /*!< [18..18] AIN18 interrupt flag */ + uint32_t : 13; + } RIS_b; + } ; + __IOM uint32_t CALI; /*!< (@ 0x00000014) Offset:0x14 ADC Calibration Register */ +} SN_ADC_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Comparator (SN_CMP) + */ + +typedef struct { /*!< (@ 0x40028000) SN_CMP Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 CMP Control Register */ + + struct { + __IOM uint32_t CM0EN : 1; /*!< [0..0] CMP0 Enable bit */ + __IOM uint32_t CM0PS : 2; /*!< [2..1] CMP0 Positive input selection bits */ + __IOM uint32_t CM0NS : 2; /*!< [4..3] CMP0 Negative input pin */ + __IOM uint32_t CM0RS : 5; /*!< [9..5] CMP0 internal reference voltage (VIREF0) selection bits */ + __IOM uint32_t CM0OEN : 2; /*!< [11..10] CMP0 Output pin control bits */ + __IOM uint32_t CM0G : 1; /*!< [12..12] CMP0 interrupt trigger direction control bit */ + uint32_t : 3; + __IOM uint32_t CM1EN : 1; /*!< [16..16] CMP1 Enable bit */ + __IOM uint32_t CM1PS : 2; /*!< [18..17] CMP1 Positive input selection bits */ + __IOM uint32_t CM1NS : 2; /*!< [20..19] CMP1 Negative input pin */ + __IOM uint32_t CM1RS : 5; /*!< [25..21] CMP1 internal reference voltage (VIREF1) selection + bits */ + __IOM uint32_t CM1OEN : 2; /*!< [27..26] CMP1 Output pin control bits */ + __IOM uint32_t CM1G : 1; /*!< [28..28] CMP1 interrupt trigger direction control bit */ + uint32_t : 3; + } CTRL_b; + } ; + + union { + __IOM uint32_t CTRL1; /*!< (@ 0x00000004) Offset:0x04 CMP Control Register 1 */ + + struct { + __IOM uint32_t CM2EN : 1; /*!< [0..0] CMP2 Enable bit */ + __IOM uint32_t CM2PS : 2; /*!< [2..1] CMP2 Positive input selection bits */ + __IOM uint32_t CM2NS : 2; /*!< [4..3] CMP2 Negative input pin */ + __IOM uint32_t CM2RS : 5; /*!< [9..5] CMP2 internal reference voltage (VIREF2) selection bits */ + __IOM uint32_t CM2OEN : 2; /*!< [11..10] CMP2 Output pin control bits */ + __IOM uint32_t CM2G : 1; /*!< [12..12] CMP2 interrupt trigger direction control bit */ + uint32_t : 19; + } CTRL1_b; + } ; + + union { + __IOM uint32_t VIREF; /*!< (@ 0x00000008) Offset:0x08 CMP Internal Reference Voltage register */ + + struct { + __IOM uint32_t CMPIREFEN : 1; /*!< [0..0] CMP internal reference voltage (VIREF) enable */ + __IOM uint32_t CMPIREF : 2; /*!< [2..1] CMP internal reference voltage (VIREF) source */ + uint32_t : 29; + } VIREF_b; + } ; + + union { + __IM uint32_t OS; /*!< (@ 0x0000000C) Offset:0xC CMP Output Status Register */ + + struct { + __IM uint32_t CM0OUT : 1; /*!< [0..0] CMP0 Output flag bit */ + __IM uint32_t CM1OUT : 1; /*!< [1..1] CMP1 Output flag bit */ + __IM uint32_t CM2OUT : 1; /*!< [2..2] CMP2 Output flag bit */ + uint32_t : 29; + } OS_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000010) Offset:0x10 CMP Interrupt Enable Register */ + + struct { + __IOM uint32_t CM0IE : 1; /*!< [0..0] CMP0 interrupt enable */ + __IOM uint32_t CM1IE : 1; /*!< [1..1] CMP1 interrupt enable */ + __IOM uint32_t CM2IE : 1; /*!< [2..2] CMP2 interrupt enable */ + __IOM uint32_t CSIE : 1; /*!< [3..3] Cap-sensing interrupt enable */ + uint32_t : 28; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x00000014) Offset:0x14 CMP n Raw Interrupt Status Register */ + + struct { + __IM uint32_t CM0IF : 1; /*!< [0..0] CMP0 raw interrupt flag */ + __IM uint32_t CM1IF : 1; /*!< [1..1] CMP1 raw interrupt flag */ + __IM uint32_t CM2IF : 1; /*!< [2..2] CMP2 raw interrupt flag */ + __IM uint32_t CSIF : 1; /*!< [3..3] Cap-sensing raw interrupt flag */ + uint32_t : 28; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000018) Offset:0x18 CMP Interrupt Clear Register */ + + struct { + __OM uint32_t CM0IC : 1; /*!< [0..0] CMP0 interrupt flag clear bit */ + __OM uint32_t CM1IC : 1; /*!< [1..1] CMP1 interrupt flag clear bit */ + __OM uint32_t CM2IC : 1; /*!< [2..2] CMP2 interrupt flag clear bit */ + __OM uint32_t CSIC : 1; /*!< [3..3] Cap-sensing interrupt flag clear bit */ + uint32_t : 28; + } IC_b; + } ; + + union { + __IOM uint32_t DB; /*!< (@ 0x0000001C) Offset:0x1C CMP Interrupt Clear Register */ + + struct { + __IOM uint32_t CM0DB : 3; /*!< [2..0] Count for CMP0 output debounce time */ + uint32_t : 1; + __IOM uint32_t CM1DB : 3; /*!< [6..4] Count for CMP1 output debounce time */ + uint32_t : 1; + __IOM uint32_t CM2DB : 3; /*!< [10..8] Count for CMP2 output debounce time */ + uint32_t : 1; + __IOM uint32_t CSDB : 5; /*!< [16..12] Count for Cap-sensing output debounce time */ + uint32_t : 15; + } DB_b; + } ; + + union { + __IOM uint32_t CSCTRL; /*!< (@ 0x00000020) Offset:0x20 CMP Cap-sensing Control Register */ + + struct { + __IOM uint32_t CSEN : 1; /*!< [0..0] Cap-sensing module enable bit */ + __IOM uint32_t CSS : 1; /*!< [1..1] Cap-sensing operation start bit */ + __IOM uint32_t CS1ST : 1; /*!< [2..2] Cap-sensing channel scan group start bit */ + __IOM uint32_t CSH : 5; /*!< [7..3] Cap-sensing channel */ + uint32_t : 3; + __IOM uint32_t CMP : 3; /*!< [13..11] Comparator reference control bits */ + __IOM uint32_t VDSEL : 1; /*!< [14..14] Cap-sensing voltage detects select bit */ + __IOM uint32_t CHG : 3; /*!< [17..15] Cap-sensing charging time */ + __IOM uint32_t TNON : 2; /*!< [19..18] Non-overlap time */ + __IOM uint32_t CCAL : 4; /*!< [23..20] Cap Calibration parameter */ + __IOM uint32_t CCAL4 : 1; /*!< [24..24] Cap Calibration select bit */ + __IOM uint32_t CSOUTEN : 1; /*!< [25..25] Cap-sening output pin enable bit */ + __IOM uint32_t CSDIS : 1; /*!< [26..26] Channel discharge signl (CK_TCH) controll bit */ + uint32_t : 3; + __IOM uint32_t CSFAPC : 1; /*!< [30..30] CSF active controll */ + __IM uint32_t CSRDY : 1; /*!< [31..31] Cap-sensing module ready flag */ + } CSCTRL_b; + } ; + + union { + __IOM uint32_t CSCTRL1; /*!< (@ 0x00000024) Offset:0x24 CMP Cap-sensing Control Register + 1 */ + + struct { + __IOM uint32_t SGFRQ : 2; /*!< [1..0] Spread Spectrum frequency */ + uint32_t : 4; + __IOM uint32_t SGSEL : 2; /*!< [7..6] Cap-sensing 4MHz clock source and SSCG select bit */ + __IOM uint32_t OSCR : 5; /*!< [12..8] Ring OSC.4MHz clock range */ + __IOM uint32_t CSVCOV : 1; /*!< [13..13] CSV 16-bit event counter overflow indicator (Clock + source is Cap-sensing 4MHz) */ + __IOM uint32_t CSCOV : 1; /*!< [14..14] CSC 16-bit timer counter overflow indicator (Clock + source is CS_PCLK) */ + uint32_t : 17; + } CSCTRL1_b; + } ; + + union { + __IM uint32_t CSCNT; /*!< (@ 0x00000028) Offset:0x28 CMP CapSensing Counter Register */ + + struct { + __IM uint32_t CSV : 16; /*!< [15..0] CSV 16-bit event counter (CSV counter clock source is + CS_4MHz) */ + __IM uint32_t CSC : 16; /*!< [31..16] CSC 16-bit timer counter (CSC counter clock source + is CS_PCLK) */ + } CSCNT_b; + } ; +} SN_CMP_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CT16B0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 16-bit Timer 0 with Capture function (SN_CT16B0) + */ + +typedef struct { /*!< (@ 0x40000000) SN_CT16B0 Structure */ + + union { + __IOM uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT16Bn Timer Control Register */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] Counter enable */ + __IOM uint32_t CRST : 1; /*!< [1..1] Counter Reset */ + __IOM uint32_t CLKSEL : 1; /*!< [2..2] PCLK source */ + uint32_t : 1; + __IOM uint32_t CM : 3; /*!< [6..4] Counting mode selection */ + uint32_t : 25; + } TMRCTRL_b; + } ; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT16Bn Timer Counter Register */ + + struct { + __IOM uint32_t TC : 16; /*!< [15..0] Timer Counter */ + uint32_t : 16; + } TC_b; + } ; + + union { + __IOM uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT16Bn Prescale Register */ + + struct { + __IOM uint32_t PRE : 8; /*!< [7..0] Prescaler */ + uint32_t : 24; + } PRE_b; + } ; + + union { + __IOM uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT16Bn Prescale Counter Register */ + + struct { + __IOM uint32_t PC : 8; /*!< [7..0] Prescaler Counter */ + uint32_t : 24; + } PC_b; + } ; + + union { + __IOM uint32_t CNTCTRL; /*!< (@ 0x00000010) Offset:0x10 CT16Bn Counter Control Register */ + + struct { + __IOM uint32_t CTM : 2; /*!< [1..0] Counter/Timer Mode */ + uint32_t : 30; + } CNTCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT16Bn Match Control Register */ + + struct { + __IOM uint32_t MR0IE : 1; /*!< [0..0] Enable generating an interrupt when MR0 matches TC */ + __IOM uint32_t MR0RST : 1; /*!< [1..1] Enable reset TC when MR0 matches TC */ + __IOM uint32_t MR0STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR0 matches TC */ + __IOM uint32_t MR1IE : 1; /*!< [3..3] Enable generating an interrupt when MR1 matches TC */ + __IOM uint32_t MR1RST : 1; /*!< [4..4] Enable reset TC when MR1 matches TC */ + __IOM uint32_t MR1STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR1 matches TC */ + __IOM uint32_t MR2IE : 1; /*!< [6..6] Enable generating an interrupt when MR2 matches TC */ + __IOM uint32_t MR2RST : 1; /*!< [7..7] Enable reset TC when MR2 matches TC */ + __IOM uint32_t MR2STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR2 matches TC */ + __IOM uint32_t MR3IE : 1; /*!< [9..9] Enable generating an interrupt when MR3 matches TC */ + __IOM uint32_t MR3RST : 1; /*!< [10..10] Enable reset TC when MR3 matches TC */ + __IOM uint32_t MR3STOP : 1; /*!< [11..11] Stop TC and PC and clear CEN bit when MR3 matches TC */ + uint32_t : 9; + __IOM uint32_t MR9IE : 1; /*!< [21..21] Enable generating an interrupt based on CM[2:0] when + MR9 matches the value in the TC */ + __IOM uint32_t MR9RST : 1; /*!< [22..22] Enable reset TC when MR9 matches TC */ + __IOM uint32_t MR9STOP : 1; /*!< [23..23] Stop TC and PC and clear CEN bit when MR9 matches TC */ + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MCTRL_b; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t MR0; /*!< (@ 0x00000020) Offset:0x20 CT16Bn MR0 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key */ + } MR0_b; + } ; + + union { + __IOM uint32_t MR1; /*!< (@ 0x00000024) Offset:0x24 CT16Bn MR1 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key */ + } MR1_b; + } ; + + union { + __IOM uint32_t MR2; /*!< (@ 0x00000028) Offset:0x28 CT16Bn MR2 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key */ + } MR2_b; + } ; + + union { + __IOM uint32_t MR3; /*!< (@ 0x0000002C) Offset:0x2C CT16Bn MR3 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key */ + } MR3_b; + } ; + __IM uint32_t RESERVED1[5]; + + union { + __IOM uint32_t MR9; /*!< (@ 0x00000044) Offset:0x44 CT16Bn MR9 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key */ + } MR9_b; + } ; + __IM uint32_t RESERVED2[15]; + + union { + __IOM uint32_t CAPCTRL; /*!< (@ 0x00000084) Offset:0x84 CT16Bn Capture Control Register */ + + struct { + __IOM uint32_t CAP0RE : 1; /*!< [0..0] Capture/Reset on CT16Bn_CAP0 signal rising edge */ + __IOM uint32_t CAP0FE : 1; /*!< [1..1] Capture/Reset on CT16Bn_CAP0 signal falling edge */ + __IOM uint32_t CAP0IE : 1; /*!< [2..2] Interrupt on CT16Bn_CAP0 event */ + __IOM uint32_t CAP0EN : 1; /*!< [3..3] CAP0 function enable */ + uint32_t : 28; + } CAPCTRL_b; + } ; + + union { + __IM uint32_t CAP0; /*!< (@ 0x00000088) Offset:0x88 CT16Bn CAP0 Register */ + + struct { + __IM uint32_t CAP0 : 16; /*!< [15..0] Timer counter capture value */ + uint32_t : 16; + } CAP0_b; + } ; + + union { + __IOM uint32_t EM; /*!< (@ 0x0000008C) Offset:0x8C CT16Bn External Match Register */ + + struct { + __IOM uint32_t EM0 : 1; /*!< [0..0] When the TC doesn't match MR0 and EMC0 is not 0, this + bit will drive the state of CT16Bn_PWM0 output. */ + __IOM uint32_t EM1 : 1; /*!< [1..1] When the TC doesn't match MR1 and EMC1 is not 0, this + bit will drive the state of CT16Bn_PWM1 output. */ + __IOM uint32_t EM2 : 1; /*!< [2..2] When the TC doesn't match MR2 and EMC2 is not 0, this + bit will drive the state of CT16Bn_PWM2 output. */ + __IOM uint32_t EM3 : 1; /*!< [3..3] When the TC doesn't match MR3 and EMC3 is not 0, this + bit will drive the state of CT16Bn_PWM3 output. */ + __IOM uint32_t EMC0 : 2; /*!< [5..4] CT16Bn_PWM0 functionality when MR0=TC */ + __IOM uint32_t EMC1 : 2; /*!< [7..6] CT16Bn_PWM1 functionality when MR1=TC */ + __IOM uint32_t EMC2 : 2; /*!< [9..8] CT16Bn_PWM2 functionality when MR2=TC */ + __IOM uint32_t EMC3 : 2; /*!< [11..10] CT16Bn_PWM3 functionality when MR3=TC */ + uint32_t : 12; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } EM_b; + } ; + __IM uint32_t RESERVED3[2]; + + union { + __IOM uint32_t PWMCTRL; /*!< (@ 0x00000098) Offset:0x98 CT16Bn PWM Control Register */ + + struct { + __IOM uint32_t PWM0EN : 1; /*!< [0..0] PWM0 enable */ + __IOM uint32_t PWM1EN : 1; /*!< [1..1] PWM1 enable */ + __IOM uint32_t PWM2EN : 1; /*!< [2..2] PWM2 enable */ + __IOM uint32_t PWM3EN : 1; /*!< [3..3] PWM2 enable */ + __IOM uint32_t PWM0MODE : 2; /*!< [5..4] PWM0 output mode */ + __IOM uint32_t PWM1MODE : 2; /*!< [7..6] PWM1 output mode */ + __IOM uint32_t PWM2MODE : 2; /*!< [9..8] PWM2 output mode */ + __IOM uint32_t PWM3MODE : 2; /*!< [11..10] PWM3 output mode */ + uint32_t : 8; + __IOM uint32_t PWM0IOEN : 1; /*!< [20..20] CT16Bn_PWM0/GPIO selection */ + __IOM uint32_t PWM1IOEN : 1; /*!< [21..21] CT16Bn_PWM1/GPIO selection */ + __IOM uint32_t PWM2IOEN : 1; /*!< [22..22] CT16Bn_PWM2/GPIO selection */ + __IOM uint32_t PWM3IOEN : 1; /*!< [23..23] CT16Bn_PWM3/GPIO selection */ + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWMCTRL_b; + } ; + __IM uint32_t RESERVED4[3]; + + union { + __IM uint32_t RIS; /*!< (@ 0x000000A8) Offset:0xA8 CT16Bn Raw Interrupt Status Register */ + + struct { + __IM uint32_t MR0IF : 1; /*!< [0..0] Match channel 0 interrupt flag */ + __IM uint32_t MR1IF : 1; /*!< [1..1] Match channel 1 interrupt flag */ + __IM uint32_t MR2IF : 1; /*!< [2..2] Match channel 2 interrupt flag */ + __IM uint32_t MR3IF : 1; /*!< [3..3] Match channel 3 interrupt flag */ + __IM uint32_t CAP0IF : 1; /*!< [4..4] Capture channel 0 interrupt flag */ + __IM uint32_t MR9IF : 1; /*!< [5..5] Match channel 9 interrupt flag */ + uint32_t : 26; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x000000AC) Offset:0xAC CT16Bn Interrupt Clear Register */ + + struct { + __OM uint32_t MR0IC : 1; /*!< [0..0] MR0IF clear bit */ + __OM uint32_t MR1IC : 1; /*!< [1..1] MR1IF clear bit */ + __OM uint32_t MR2IC : 1; /*!< [2..2] MR2IF clear bit */ + __OM uint32_t MR3IC : 1; /*!< [3..3] MR3IF clear bit */ + __OM uint32_t CAP0IC : 1; /*!< [4..4] CAP0IF clear bit */ + __OM uint32_t MR9IC : 1; /*!< [5..5] MR9IF clear bit */ + uint32_t : 26; + } IC_b; + } ; + + union { + __IOM uint32_t PWMmNIOCTRL; /*!< (@ 0x000000B0) Offset:0xB0 CT16Bn PWMmN IO Control register */ + + struct { + __IOM uint32_t PWM0NIOEN : 2; /*!< [1..0] CT16Bn_PWM0N/GPIO selection bit */ + __IOM uint32_t PWM1NIOEN : 2; /*!< [3..2] CT16Bn_PWM0N/GPIO selection bit */ + __IOM uint32_t PWM2NIOEN : 2; /*!< [5..4] CT16Bn_PWM0N/GPIO selection bit */ + __IOM uint32_t PWM3NIOEN : 2; /*!< [7..6] CT16Bn_PWM3N/GPIO selection bit */ + uint32_t : 16; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWMmNIOCTRL_b; + } ; + + union { + __IOM uint32_t PWM0NDB; /*!< (@ 0x000000B4) Offset:0xB4 CT16Bn PWM0N Dead-band Period Register */ + + struct { + __IOM uint32_t DB : 10; /*!< [9..0] PWM0N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) + cycle */ + uint32_t : 14; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWM0NDB_b; + } ; + + union { + __IOM uint32_t PWM1NDB; /*!< (@ 0x000000B8) Offset:0xB8 CT16Bn PWM1N Dead-band Period Register */ + + struct { + __IOM uint32_t DB : 10; /*!< [9..0] PWM1N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) + cycle */ + uint32_t : 14; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWM1NDB_b; + } ; + + union { + __IOM uint32_t PWM2NDB; /*!< (@ 0x000000BC) Offset:0xBC CT16Bn PWM2N Dead-band Period Register */ + + struct { + __IOM uint32_t DB : 10; /*!< [9..0] PWM2N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) + cycle */ + uint32_t : 14; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWM2NDB_b; + } ; + + union { + __IOM uint32_t PWM3NDB; /*!< (@ 0x000000C0) Offset:0xC0 CT16Bn PWM3N Dead-band Period Register */ + + struct { + __IOM uint32_t DB : 10; /*!< [9..0] PWM3N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) + cycle */ + uint32_t : 14; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWM3NDB_b; + } ; +} SN_CT16B0_Type; /*!< Size = 196 (0xc4) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CT16B1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 16-bit Timer 1 with Capture function (SN_CT16B1) + */ + +typedef struct { /*!< (@ 0x40002000) SN_CT16B1 Structure */ + + union { + __IOM uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT16Bn Timer Control Register */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] Counter enable */ + __IOM uint32_t CRST : 1; /*!< [1..1] Counter Reset */ + __IOM uint32_t CLKSEL : 1; /*!< [2..2] PCLK source */ + uint32_t : 29; + } TMRCTRL_b; + } ; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT16Bn Timer Counter Register */ + + struct { + __IOM uint32_t TC : 16; /*!< [15..0] Timer Counter */ + uint32_t : 16; + } TC_b; + } ; + + union { + __IOM uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT16Bn Prescale Register */ + + struct { + __IOM uint32_t PRE : 8; /*!< [7..0] Prescaler */ + uint32_t : 24; + } PRE_b; + } ; + + union { + __IOM uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT16Bn Prescale Counter Register */ + + struct { + __IOM uint32_t PC : 8; /*!< [7..0] Prescaler Counter */ + uint32_t : 24; + } PC_b; + } ; + + union { + __IOM uint32_t CNTCTRL; /*!< (@ 0x00000010) Offset:0x10 CT16Bn Counter Control Register */ + + struct { + __IOM uint32_t CTM : 2; /*!< [1..0] Counter/Timer Mode */ + uint32_t : 30; + } CNTCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT16Bn Match Control Register */ + + struct { + __IOM uint32_t MR0IE : 1; /*!< [0..0] Enable generating an interrupt when MR0 matches TC */ + __IOM uint32_t MR0RST : 1; /*!< [1..1] Enable reset TC when MR0 matches TC */ + __IOM uint32_t MR0STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR0 matches TC */ + __IOM uint32_t MR1IE : 1; /*!< [3..3] Enable generating an interrupt when MR1 matches TC */ + __IOM uint32_t MR1RST : 1; /*!< [4..4] Enable reset TC when MR1 matches TC */ + __IOM uint32_t MR1STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR1 matches TC */ + __IOM uint32_t MR2IE : 1; /*!< [6..6] Enable generating an interrupt when MR2 matches TC */ + __IOM uint32_t MR2RST : 1; /*!< [7..7] Enable reset TC when MR2 matches TC */ + __IOM uint32_t MR2STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR2 matches TC */ + __IOM uint32_t MR3IE : 1; /*!< [9..9] Enable generating an interrupt when MR3 matches TC */ + __IOM uint32_t MR3RST : 1; /*!< [10..10] Enable reset TC when MR3 matches TC */ + __IOM uint32_t MR3STOP : 1; /*!< [11..11] Stop TC and PC and clear CEN bit when MR3 matches TC */ + __IOM uint32_t MR4IE : 1; /*!< [12..12] Enable generating an interrupt when MR4 matches TC */ + __IOM uint32_t MR4RST : 1; /*!< [13..13] Enable reset TC when MR4 matches TC */ + __IOM uint32_t MR4STOP : 1; /*!< [14..14] Stop TC and PC and clear CEN bit when MR4 matches TC */ + __IOM uint32_t MR5IE : 1; /*!< [15..15] Enable generating an interrupt when MR5 matches TC */ + __IOM uint32_t MR5RST : 1; /*!< [16..16] Enable reset TC when MR5 matches TC */ + __IOM uint32_t MR5STOP : 1; /*!< [17..17] Stop TC and PC and clear CEN bit when MR5 matches TC */ + __IOM uint32_t MR6IE : 1; /*!< [18..18] Enable generating an interrupt when MR6 matches TC */ + __IOM uint32_t MR6RST : 1; /*!< [19..19] Enable reset TC when MR6 matches TC */ + __IOM uint32_t MR6STOP : 1; /*!< [20..20] Stop TC and PC and clear CEN bit when MR6 matches TC */ + __IOM uint32_t MR7IE : 1; /*!< [21..21] Enable generating an interrupt when MR7 matches TC */ + __IOM uint32_t MR7RST : 1; /*!< [22..22] Enable reset TC when MR7 matches TC */ + __IOM uint32_t MR7STOP : 1; /*!< [23..23] Stop TC and PC and clear CEN bit when MR7 matches TC */ + __IOM uint32_t MR8IE : 1; /*!< [24..24] Enable generating an interrupt when MR8 matches TC */ + __IOM uint32_t MR8RST : 1; /*!< [25..25] Enable reset TC when MR8 matches TC */ + __IOM uint32_t MR8STOP : 1; /*!< [26..26] Stop TC and PC and clear CEN bit when MR8 matches TC */ + __IOM uint32_t MR9IE : 1; /*!< [27..27] Enable generating an interrupt when MR9 matches TC */ + __IOM uint32_t MR9RST : 1; /*!< [28..28] Enable reset TC when MR9 matches TC */ + __IOM uint32_t MR9STOP : 1; /*!< [29..29] Stop TC and PC and clear CEN bit when MR9 matches TC */ + uint32_t : 2; + } MCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL2; /*!< (@ 0x00000018) Offset:0x18 CT16Bn Match Control Register 2 */ + + struct { + __IOM uint32_t MR10IE : 1; /*!< [0..0] Enable generating an interrupt when MR10 matches TC */ + __IOM uint32_t MR10RST : 1; /*!< [1..1] Enable reset TC when MR10 matches TC */ + __IOM uint32_t MR10STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR10 matches TC */ + __IOM uint32_t MR11IE : 1; /*!< [3..3] Enable generating an interrupt when MR11 matches TC */ + __IOM uint32_t MR11RST : 1; /*!< [4..4] Enable reset TC when MR11 matches TC */ + __IOM uint32_t MR11STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR11 matches TC */ + __IOM uint32_t MR12IE : 1; /*!< [6..6] Enable generating an interrupt when MR12 matches TC */ + __IOM uint32_t MR12RST : 1; /*!< [7..7] Enable reset TC when MR12 matches TC */ + __IOM uint32_t MR12STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR12 matches TC */ + uint32_t : 23; + } MCTRL2_b; + } ; + __IM uint32_t RESERVED; + __IOM uint32_t MR0; /*!< (@ 0x00000020) Offset:0x20 CT16Bn MR0 Register */ + __IOM uint32_t MR1; /*!< (@ 0x00000024) Offset:0x24 CT16Bn MR1 Register */ + __IOM uint32_t MR2; /*!< (@ 0x00000028) Offset:0x28 CT16Bn MR2 Register */ + __IOM uint32_t MR3; /*!< (@ 0x0000002C) Offset:0x2C CT16Bn MR3 Register */ + __IOM uint32_t MR4; /*!< (@ 0x00000030) Offset:0x30 CT16Bn MR4 Register */ + __IOM uint32_t MR5; /*!< (@ 0x00000034) Offset:0x34 CT16Bn MR5 Register */ + __IOM uint32_t MR6; /*!< (@ 0x00000038) Offset:0x38 CT16Bn MR6 Register */ + __IOM uint32_t MR7; /*!< (@ 0x0000003C) Offset:0x3C CT16Bn MR7 Register */ + __IOM uint32_t MR8; /*!< (@ 0x00000040) Offset:0x40 CT16Bn MR8 Register */ + __IOM uint32_t MR9; /*!< (@ 0x00000044) Offset:0x44 CT16Bn MR9 Register */ + __IOM uint32_t MR10; /*!< (@ 0x00000048) Offset:0x48 CT16Bn MR10 Register */ + __IOM uint32_t MR11; /*!< (@ 0x0000004C) Offset:0x4C CT16Bn MR11 Register */ + __IOM uint32_t MR12; /*!< (@ 0x00000050) Offset:0x50 CT16Bn MR12 Register */ + __IM uint32_t RESERVED1[12]; + + union { + __IOM uint32_t CAPCTRL; /*!< (@ 0x00000084) Offset:0x84 CT16Bn Capture Control Register */ + + struct { + __IOM uint32_t CAP0RE : 1; /*!< [0..0] Capture/Reset on CT16Bn_CAP0 signal rising edge */ + __IOM uint32_t CAP0FE : 1; /*!< [1..1] Capture/Reset on CT16Bn_CAP0 signal falling edge */ + __IOM uint32_t CAP0IE : 1; /*!< [2..2] Interrupt on CT16Bn_CAP0 event */ + __IOM uint32_t CAP0EN : 1; /*!< [3..3] CAP0 function enable */ + uint32_t : 28; + } CAPCTRL_b; + } ; + + union { + __IM uint32_t CAP0; /*!< (@ 0x00000088) Offset:0x88 CT16Bn CAP0 Register */ + + struct { + __IM uint32_t CAP0 : 16; /*!< [15..0] Timer counter capture value */ + uint32_t : 16; + } CAP0_b; + } ; + + union { + __IOM uint32_t EM; /*!< (@ 0x0000008C) Offset:0x8C CT16Bn External Match Register */ + + struct { + __IOM uint32_t EM0 : 1; /*!< [0..0] When the TC matches MR0, this bit will act according + to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output. */ + __IOM uint32_t EM1 : 1; /*!< [1..1] When the TC matches MR1, this bit will act according + to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output. */ + __IOM uint32_t EM2 : 1; /*!< [2..2] When the TC matches MR2, this bit will act according + to EMC2[1:0], and also drive the state of CT16Bn_PWM2 output. */ + __IOM uint32_t EM3 : 1; /*!< [3..3] When the TC matches MR3, this bit will act according + to EMC3[1:0], and also drive the state of CT16Bn_PWM3 output. */ + __IOM uint32_t EM4 : 1; /*!< [4..4] When the TC matches MR4, this bit will act according + to EMC4[1:0], and also drive the state of CT16Bn_PWM0 output. */ + __IOM uint32_t EM5 : 1; /*!< [5..5] When the TC matches MR5, this bit will act according + to EMC5[1:0], and also drive the state of CT16Bn_PWM1 output. */ + __IOM uint32_t EM6 : 1; /*!< [6..6] When the TC matches MR6, this bit will act according + to EMC6[1:0], and also drive the state of CT16Bn_PWM2 output. */ + __IOM uint32_t EM7 : 1; /*!< [7..7] When the TC matches MR7, this bit will act according + to EMC7[1:0], and also drive the state of CT16Bn_PWM3 output. */ + __IOM uint32_t EM8 : 1; /*!< [8..8] When the TC matches MR8, this bit will act according + to EMC8[1:0], and also drive the state of CT16Bn_PWM0 output. */ + __IOM uint32_t EM9 : 1; /*!< [9..9] When the TC matches MR9, this bit will act according + to EMC9[1:0], and also drive the state of CT16Bn_PWM1 output. */ + __IOM uint32_t EM10 : 1; /*!< [10..10] When the TC matches MR10, this bit will act according + to EMC10[1:0], and also drive the state of CT16Bn_PWM2 + output. */ + __IOM uint32_t EM11 : 1; /*!< [11..11] When the TC matches MR11, this bit will act according + to EMC11[1:0], and also drive the state of CT16Bn_PWM3 + output. */ + uint32_t : 20; + } EM_b; + } ; + + union { + __IOM uint32_t EMC; /*!< (@ 0x00000090) Offset:0x90 CT16Bn External Match Control register */ + + struct { + __IOM uint32_t EMC0 : 2; /*!< [1..0] CT16Bn_PWM0 functionality */ + __IOM uint32_t EMC1 : 2; /*!< [3..2] CT16Bn_PWM1 functionality */ + __IOM uint32_t EMC2 : 2; /*!< [5..4] CT16Bn_PWM2 functionality */ + __IOM uint32_t EMC3 : 2; /*!< [7..6] CT16Bn_PWM3 functionality */ + __IOM uint32_t EMC4 : 2; /*!< [9..8] CT16Bn_PWM4 functionality */ + __IOM uint32_t EMC5 : 2; /*!< [11..10] CT16Bn_PWM5 functionality */ + __IOM uint32_t EMC6 : 2; /*!< [13..12] CT16Bn_PWM6 functionality */ + __IOM uint32_t EMC7 : 2; /*!< [15..14] CT16Bn_PWM7 functionality */ + __IOM uint32_t EMC8 : 2; /*!< [17..16] CT16Bn_PWM8 functionality */ + __IOM uint32_t EMC9 : 2; /*!< [19..18] CT16Bn_PWM9 functionality */ + __IOM uint32_t EMC10 : 2; /*!< [21..20] CT16Bn_PWM10 functionality */ + __IOM uint32_t EMC11 : 2; /*!< [23..22] CT16Bn_PWM11 functionality */ + uint32_t : 8; + } EMC_b; + } ; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t PWMCTRL; /*!< (@ 0x00000098) Offset:0x98 CT16Bn PWM Control Register */ + + struct { + __IOM uint32_t PWM0MODE : 2; /*!< [1..0] PWM0 output mode */ + __IOM uint32_t PWM1MODE : 2; /*!< [3..2] PWM1 output mode */ + __IOM uint32_t PWM2MODE : 2; /*!< [5..4] PWM2 output mode */ + __IOM uint32_t PWM3MODE : 2; /*!< [7..6] PWM3 output mode */ + __IOM uint32_t PWM4MODE : 2; /*!< [9..8] PWM4 output mode */ + __IOM uint32_t PWM5MODE : 2; /*!< [11..10] PWM5 output mode */ + __IOM uint32_t PWM6MODE : 2; /*!< [13..12] PWM6 output mode */ + __IOM uint32_t PWM7MODE : 2; /*!< [15..14] PWM7 output mode */ + __IOM uint32_t PWM8MODE : 2; /*!< [17..16] PWM8 output mode */ + __IOM uint32_t PWM9MODE : 2; /*!< [19..18] PWM9 output mode */ + __IOM uint32_t PWM10MODE : 2; /*!< [21..20] PWM10 output mode */ + __IOM uint32_t PWM11MODE : 2; /*!< [23..22] PWM11 output mode */ + uint32_t : 8; + } PWMCTRL_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t PWMENB; /*!< (@ 0x000000A0) Offset:0xA0 CT16Bn PWM Enable register */ + + struct { + __IOM uint32_t PWM0EN : 1; /*!< [0..0] PWM0 enable */ + __IOM uint32_t PWM1EN : 1; /*!< [1..1] PWM1 enable */ + __IOM uint32_t PWM2EN : 1; /*!< [2..2] PWM2 enable */ + __IOM uint32_t PWM3EN : 1; /*!< [3..3] PWM3 enable */ + __IOM uint32_t PWM4EN : 1; /*!< [4..4] PWM4 enable */ + __IOM uint32_t PWM5EN : 1; /*!< [5..5] PWM5 enable */ + __IOM uint32_t PWM6EN : 1; /*!< [6..6] PWM6 enable */ + __IOM uint32_t PWM7EN : 1; /*!< [7..7] PWM7 enable */ + __IOM uint32_t PWM8EN : 1; /*!< [8..8] PWM8 enable */ + __IOM uint32_t PWM9EN : 1; /*!< [9..9] PWM9 enable */ + __IOM uint32_t PWM10EN : 1; /*!< [10..10] PWM10 enable */ + __IOM uint32_t PWM11EN : 1; /*!< [11..11] PWM11 enable */ + uint32_t : 20; + } PWMENB_b; + } ; + + union { + __IOM uint32_t PWMIOENB; /*!< (@ 0x000000A4) Offset:0xA4 CT16Bn PWM IO Enable register */ + + struct { + __IOM uint32_t PWM0IOEN : 1; /*!< [0..0] CT16Bn_PWM0/GPIO selection */ + __IOM uint32_t PWM1IOEN : 1; /*!< [1..1] CT16Bn_PWM1/GPIO selection */ + __IOM uint32_t PWM2IOEN : 1; /*!< [2..2] CT16Bn_PWM2/GPIO selection */ + __IOM uint32_t PWM3IOEN : 1; /*!< [3..3] CT16Bn_PWM3/GPIO selection */ + __IOM uint32_t PWM4IOEN : 1; /*!< [4..4] CT16Bn_PWM4/GPIO selection */ + __IOM uint32_t PWM5IOEN : 1; /*!< [5..5] CT16Bn_PWM5/GPIO selection */ + __IOM uint32_t PWM6IOEN : 1; /*!< [6..6] CT16Bn_PWM6/GPIO selection */ + __IOM uint32_t PWM7IOEN : 1; /*!< [7..7] CT16Bn_PWM7/GPIO selection */ + __IOM uint32_t PWM8IOEN : 1; /*!< [8..8] CT16Bn_PWM8/GPIO selection */ + __IOM uint32_t PWM9IOEN : 1; /*!< [9..9] CT16Bn_PWM9/GPIO selection */ + __IOM uint32_t PWM10IOEN : 1; /*!< [10..10] CT16Bn_PWM10/GPIO selection */ + __IOM uint32_t PWM11IOEN : 1; /*!< [11..11] CT16Bn_PWM11/GPIO selection */ + uint32_t : 20; + } PWMIOENB_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x000000A8) Offset:0xA8 CT16Bn Raw Interrupt Status Register */ + + struct { + __IM uint32_t MR0IF : 1; /*!< [0..0] Match channel 0 interrupt flag */ + __IM uint32_t MR1IF : 1; /*!< [1..1] Match channel 1 interrupt flag */ + __IM uint32_t MR2IF : 1; /*!< [2..2] Match channel 2 interrupt flag */ + __IM uint32_t MR3IF : 1; /*!< [3..3] Match channel 3 interrupt flag */ + __IM uint32_t MR4IF : 1; /*!< [4..4] Match channel 4 interrupt flag */ + __IM uint32_t MR5IF : 1; /*!< [5..5] Match channel 5 interrupt flag */ + __IM uint32_t MR6IF : 1; /*!< [6..6] Match channel 6 interrupt flag */ + __IM uint32_t MR7IF : 1; /*!< [7..7] Match channel 7 interrupt flag */ + __IM uint32_t MR8IF : 1; /*!< [8..8] Match channel 8 interrupt flag */ + __IM uint32_t MR9IF : 1; /*!< [9..9] Match channel 9 interrupt flag */ + __IM uint32_t MR10IF : 1; /*!< [10..10] Match channel 10 interrupt flag */ + __IM uint32_t MR11IF : 1; /*!< [11..11] Match channel 11 interrupt flag */ + __IM uint32_t MR12IF : 1; /*!< [12..12] Match channel 12 interrupt flag */ + __IM uint32_t CAP0IF : 1; /*!< [13..13] Capture channel 0 interrupt flag */ + uint32_t : 18; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x000000AC) Offset:0xAC CT16Bn Interrupt Clear Register */ + + struct { + __OM uint32_t MR0IC : 1; /*!< [0..0] MR0IF clear bit */ + __OM uint32_t MR1IC : 1; /*!< [1..1] MR1IF clear bit */ + __OM uint32_t MR2IC : 1; /*!< [2..2] MR2IF clear bit */ + __OM uint32_t MR3IC : 1; /*!< [3..3] MR3IF clear bit */ + __OM uint32_t MR4IC : 1; /*!< [4..4] MR4IF clear bit */ + __OM uint32_t MR5IC : 1; /*!< [5..5] MR5IF clear bit */ + __OM uint32_t MR6IC : 1; /*!< [6..6] MR6IF clear bit */ + __OM uint32_t MR7IC : 1; /*!< [7..7] MR7IF clear bit */ + __OM uint32_t MR8IC : 1; /*!< [8..8] MR8IF clear bit */ + __OM uint32_t MR9IC : 1; /*!< [9..9] MR9IF clear bit */ + __OM uint32_t MR10IC : 1; /*!< [10..10] MR10IF clear bit */ + __OM uint32_t MR11IC : 1; /*!< [11..11] MR11IF clear bit */ + __OM uint32_t MR12IC : 1; /*!< [12..12] MR12IF clear bit */ + __OM uint32_t CAP0IC : 1; /*!< [13..13] CAP0IF clear bit */ + uint32_t : 18; + } IC_b; + } ; +} SN_CT16B1_Type; /*!< Size = 176 (0xb0) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CT16B2 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 16-bit Timer 2 with Capture function (SN_CT16B2) + */ + +typedef struct { /*!< (@ 0x40004000) SN_CT16B2 Structure */ + + union { + __IOM uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT16Bn Timer Control Register */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] Counter enable */ + __IOM uint32_t CRST : 1; /*!< [1..1] Counter Reset */ + __IOM uint32_t CLKSEL : 1; /*!< [2..2] PCLK source */ + uint32_t : 1; + __IOM uint32_t CM : 3; /*!< [6..4] Counting mode selection */ + uint32_t : 25; + } TMRCTRL_b; + } ; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT16Bn Timer Counter Register */ + + struct { + __IOM uint32_t TC : 16; /*!< [15..0] Timer Counter */ + uint32_t : 16; + } TC_b; + } ; + + union { + __IOM uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT16Bn Prescale Register */ + + struct { + __IOM uint32_t PRE : 8; /*!< [7..0] Prescalzer */ + uint32_t : 24; + } PRE_b; + } ; + + union { + __IOM uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT16Bn Prescale Counter Register */ + + struct { + __IOM uint32_t PC : 8; /*!< [7..0] Prescaler Counter */ + uint32_t : 24; + } PC_b; + } ; + + union { + __IOM uint32_t CNTCTRL; /*!< (@ 0x00000010) Offset:0x10 CT16Bn Counter Control Register */ + + struct { + __IOM uint32_t CTM : 2; /*!< [1..0] Counter/Timer Mode */ + uint32_t : 30; + } CNTCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT16Bn Match Control Register */ + + struct { + __IOM uint32_t MR0IE : 1; /*!< [0..0] Enable generating an interrupt when MR0 matches TC */ + __IOM uint32_t MR0RST : 1; /*!< [1..1] Enable reset TC when MR0 matches TC */ + __IOM uint32_t MR0STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR0 matches TC */ + __IOM uint32_t MR1IE : 1; /*!< [3..3] Enable generating an interrupt when MR1 matches TC */ + __IOM uint32_t MR1RST : 1; /*!< [4..4] Enable reset TC when MR1 matches TC */ + __IOM uint32_t MR1STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR1 matches TC */ + __IOM uint32_t MR2IE : 1; /*!< [6..6] Enable generating an interrupt when MR2 matches TC */ + __IOM uint32_t MR2RST : 1; /*!< [7..7] Enable reset TC when MR2 matches TC */ + __IOM uint32_t MR2STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR2 matches TC */ + __IOM uint32_t MR3IE : 1; /*!< [9..9] Enable generating an interrupt when MR3 matches TC */ + __IOM uint32_t MR3RST : 1; /*!< [10..10] Enable reset TC when MR3 matches TC */ + __IOM uint32_t MR3STOP : 1; /*!< [11..11] Stop TC and PC and clear CEN bit when MR3 matches TC */ + uint32_t : 9; + __IOM uint32_t MR9IE : 1; /*!< [21..21] Enable generating an interrupt when MR9 matches TC */ + __IOM uint32_t MR9RST : 1; /*!< [22..22] Enable reset TC when MR9 matches TC */ + __IOM uint32_t MR9STOP : 1; /*!< [23..23] Stop TC and PC and clear CEN bit when MR9 matches TC */ + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MCTRL_b; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t MR0; /*!< (@ 0x00000020) Offset:0x20 CT16Bn MR0 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MR0_b; + } ; + + union { + __IOM uint32_t MR1; /*!< (@ 0x00000024) Offset:0x24 CT16Bn MR1 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MR1_b; + } ; + + union { + __IOM uint32_t MR2; /*!< (@ 0x00000028) Offset:0x28 CT16Bn MR2 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MR2_b; + } ; + + union { + __IOM uint32_t MR3; /*!< (@ 0x0000002C) Offset:0x2C CT16Bn MR3 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MR3_b; + } ; + __IM uint32_t RESERVED1[5]; + + union { + __IOM uint32_t MR9; /*!< (@ 0x00000044) Offset:0x44 CT16Bn MR9 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MR9_b; + } ; + __IM uint32_t RESERVED2[15]; + + union { + __IOM uint32_t CAPCTRL; /*!< (@ 0x00000084) Offset:0x84 CT16Bn Capture Control Register */ + + struct { + __IOM uint32_t CAP0RE : 1; /*!< [0..0] Capture/Reset on CT16Bn_CAP0 signal rising edge */ + __IOM uint32_t CAP0FE : 1; /*!< [1..1] Capture/Reset on CT16Bn_CAP0 signal falling edge */ + __IOM uint32_t CAP0IE : 1; /*!< [2..2] Interrupt on CT16Bn_CAP0 event */ + __IOM uint32_t CAP0EN : 1; /*!< [3..3] CAP0 function enable */ + uint32_t : 28; + } CAPCTRL_b; + } ; + + union { + __IM uint32_t CAP0; /*!< (@ 0x00000088) Offset:0x88 CT16Bn CAP0 Register */ + + struct { + __IM uint32_t CAP0 : 16; /*!< [15..0] Timer counter capture value */ + uint32_t : 16; + } CAP0_b; + } ; + + union { + __IOM uint32_t EM; /*!< (@ 0x0000008C) Offset:0x8C CT16Bn External Match Register */ + + struct { + __IOM uint32_t EM0 : 1; /*!< [0..0] When the TC matches MR0, this bit will act according + to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output. */ + __IOM uint32_t EM1 : 1; /*!< [1..1] When the TC matches MR1, this bit will act according + to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output. */ + __IOM uint32_t EM2 : 1; /*!< [2..2] When the TC matches MR2, this bit will act according + to EMC2[1:0], and also drive the state of CT16Bn_PWM2 output. */ + __IOM uint32_t EM3 : 1; /*!< [3..3] When the TC matches MR3, this bit will act according + to EMC3[1:0], and also drive the state of CT16Bn_PWM3 output. */ + __IOM uint32_t EMC0 : 2; /*!< [5..4] CT16Bn_PWM0 functionality */ + __IOM uint32_t EMC1 : 2; /*!< [7..6] CT16Bn_PWM1 functionality */ + __IOM uint32_t EMC2 : 2; /*!< [9..8] CT16Bn_PWM2 functionality */ + __IOM uint32_t EMC3 : 2; /*!< [11..10] CT16Bn_PWM3 functionality */ + uint32_t : 12; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } EM_b; + } ; + __IM uint32_t RESERVED3[2]; + + union { + __IOM uint32_t PWMCTRL; /*!< (@ 0x00000098) Offset:0x98 CT16Bn PWM Control Register */ + + struct { + __IOM uint32_t PWM0EN : 1; /*!< [0..0] PWM0 enable */ + __IOM uint32_t PWM1EN : 1; /*!< [1..1] PWM1 enable */ + __IOM uint32_t PWM2EN : 1; /*!< [2..2] PWM2 enable */ + __IOM uint32_t PWM3EN : 1; /*!< [3..3] PWM2 enable */ + __IOM uint32_t PWM0MODE : 2; /*!< [5..4] PWM0 output mode */ + __IOM uint32_t PWM1MODE : 2; /*!< [7..6] PWM1 output mode */ + __IOM uint32_t PWM2MODE : 2; /*!< [9..8] PWM2 output mode */ + __IOM uint32_t PWM3MODE : 2; /*!< [11..10] PWM3 output mode */ + uint32_t : 8; + __IOM uint32_t PWM0IOEN : 1; /*!< [20..20] CT16Bn_PWM0/GPIO selection */ + __IOM uint32_t PWM1IOEN : 1; /*!< [21..21] CT16Bn_PWM1/GPIO selection */ + __IOM uint32_t PWM2IOEN : 1; /*!< [22..22] CT16Bn_PWM2/GPIO selection */ + __IOM uint32_t PWM3IOEN : 1; /*!< [23..23] CT16Bn_PWM3/GPIO selection */ + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWMCTRL_b; + } ; + __IM uint32_t RESERVED4[3]; + + union { + __IM uint32_t RIS; /*!< (@ 0x000000A8) Offset:0xA8 CT16Bn Raw Interrupt Status Register */ + + struct { + __IM uint32_t MR0IF : 1; /*!< [0..0] Match channel 0 interrupt flag */ + __IM uint32_t MR1IF : 1; /*!< [1..1] Match channel 1 interrupt flag */ + __IM uint32_t MR2IF : 1; /*!< [2..2] Match channel 2 interrupt flag */ + __IM uint32_t MR3IF : 1; /*!< [3..3] Match channel 3 interrupt flag */ + __IM uint32_t CAP0IF : 1; /*!< [4..4] Capture channel 0 interrupt flag */ + __IM uint32_t MR9IF : 1; /*!< [5..5] Match channel 9 interrupt flag */ + uint32_t : 26; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x000000AC) Offset:0xAC CT16Bn Interrupt Clear Register */ + + struct { + __OM uint32_t MR0IC : 1; /*!< [0..0] MR0IF clear bit */ + __OM uint32_t MR1IC : 1; /*!< [1..1] MR1IF clear bit */ + __OM uint32_t MR2IC : 1; /*!< [2..2] MR2IF clear bit */ + __OM uint32_t MR3IC : 1; /*!< [3..3] MR3IF clear bit */ + __OM uint32_t CAP0IC : 1; /*!< [4..4] CAP0IF clear bit */ + __OM uint32_t MR9IC : 1; /*!< [5..5] MR9IF clear bit */ + uint32_t : 26; + } IC_b; + } ; +} SN_CT16B2_Type; /*!< Size = 176 (0xb0) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CT16B3 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 16-bit Timer 3 with Capture function (SN_CT16B3) + */ + +typedef struct { /*!< (@ 0x40006000) SN_CT16B3 Structure */ + + union { + __IOM uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT16Bn Timer Control Register */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] Counter enable */ + __IOM uint32_t CRST : 1; /*!< [1..1] Counter Reset */ + __IOM uint32_t CLKSEL : 1; /*!< [2..2] PCLK source */ + uint32_t : 29; + } TMRCTRL_b; + } ; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT16Bn Timer Counter Register */ + + struct { + __IOM uint32_t TC : 16; /*!< [15..0] Timer Counter */ + uint32_t : 16; + } TC_b; + } ; + + union { + __IOM uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT16Bn Prescale Register */ + + struct { + __IOM uint32_t PRE : 8; /*!< [7..0] Prescalzer */ + uint32_t : 24; + } PRE_b; + } ; + + union { + __IOM uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT16Bn Prescale Counter Register */ + + struct { + __IOM uint32_t PC : 8; /*!< [7..0] Prescaler Counter */ + uint32_t : 24; + } PC_b; + } ; + + union { + __IOM uint32_t CNTCTRL; /*!< (@ 0x00000010) Offset:0x10 CT16Bn Counter Control Register */ + + struct { + __IOM uint32_t CTM : 2; /*!< [1..0] Counter/Timer Mode */ + uint32_t : 30; + } CNTCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT16Bn Match Control Register */ + + struct { + __IOM uint32_t MR0IE : 1; /*!< [0..0] Enable generating an interrupt when MR0 matches TC */ + __IOM uint32_t MR0RST : 1; /*!< [1..1] Enable reset TC when MR0 matches TC */ + __IOM uint32_t MR0STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR0 matches TC */ + __IOM uint32_t MR1IE : 1; /*!< [3..3] Enable generating an interrupt when MR1 matches TC */ + __IOM uint32_t MR1RST : 1; /*!< [4..4] Enable reset TC when MR1 matches TC */ + __IOM uint32_t MR1STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR1 matches TC */ + uint32_t : 15; + __IOM uint32_t MR9IE : 1; /*!< [21..21] Enable generating an interrupt based on CM[2:0] when + MR9 matches the value in the TC */ + __IOM uint32_t MR9RST : 1; /*!< [22..22] Enable reset TC when MR9 matches TC */ + __IOM uint32_t MR9STOP : 1; /*!< [23..23] Stop TC and PC and clear CEN bit when MR9 matches TC */ + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MCTRL_b; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t MR0; /*!< (@ 0x00000020) Offset:0x20 CT16Bn MR0 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MR0_b; + } ; + + union { + __IOM uint32_t MR1; /*!< (@ 0x00000024) Offset:0x24 CT16Bn MR1 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MR1_b; + } ; + __IM uint32_t RESERVED1[7]; + + union { + __IOM uint32_t MR9; /*!< (@ 0x00000044) Offset:0x44 CT16Bn MR9 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MR9_b; + } ; + __IM uint32_t RESERVED2[15]; + + union { + __IOM uint32_t CAPCTRL; /*!< (@ 0x00000084) Offset:0x84 CT16Bn Capture Control Register */ + + struct { + __IOM uint32_t CAP0RE : 1; /*!< [0..0] Capture/Reset on CT16Bn_CAP0 signal rising edge */ + __IOM uint32_t CAP0FE : 1; /*!< [1..1] Capture/Reset on CT16Bn_CAP0 signal falling edge */ + __IOM uint32_t CAP0IE : 1; /*!< [2..2] Interrupt on CT16Bn_CAP0 event */ + __IOM uint32_t CAP0EN : 1; /*!< [3..3] CAP0 function enable */ + uint32_t : 28; + } CAPCTRL_b; + } ; + + union { + __IM uint32_t CAP0; /*!< (@ 0x00000088) Offset:0x88 CT16Bn CAP0 Register */ + + struct { + __IM uint32_t CAP0 : 16; /*!< [15..0] Timer counter capture value */ + uint32_t : 16; + } CAP0_b; + } ; + + union { + __IOM uint32_t EM; /*!< (@ 0x0000008C) Offset:0x8C CT16Bn External Match Register */ + + struct { + __IOM uint32_t EM0 : 1; /*!< [0..0] When the TC matches MR0, this bit will act according + to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output. */ + __IOM uint32_t EM1 : 1; /*!< [1..1] When the TC matches MR1, this bit will act according + to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output. */ + uint32_t : 2; + __IOM uint32_t EMC0 : 2; /*!< [5..4] CT16Bn_PWM0 functionality */ + __IOM uint32_t EMC1 : 2; /*!< [7..6] CT16Bn_PWM1 functionality */ + uint32_t : 24; + } EM_b; + } ; + __IM uint32_t RESERVED3[2]; + + union { + __IOM uint32_t PWMCTRL; /*!< (@ 0x00000098) Offset:0x98 CT16Bn PWM Control Register */ + + struct { + __IOM uint32_t PWM0EN : 1; /*!< [0..0] PWM0 enable */ + __IOM uint32_t PWM1EN : 1; /*!< [1..1] PWM1 enable */ + uint32_t : 2; + __IOM uint32_t PWM0MODE : 2; /*!< [5..4] PWM0 output mode */ + __IOM uint32_t PWM1MODE : 2; /*!< [7..6] PWM1 output mode */ + uint32_t : 12; + __IOM uint32_t PWM0IOEN : 1; /*!< [20..20] CT16Bn_PWM0/GPIO selection */ + __IOM uint32_t PWM1IOEN : 1; /*!< [21..21] CT16Bn_PWM1/GPIO selection */ + uint32_t : 2; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWMCTRL_b; + } ; + __IM uint32_t RESERVED4[3]; + + union { + __IM uint32_t RIS; /*!< (@ 0x000000A8) Offset:0xA8 CT16Bn Raw Interrupt Status Register */ + + struct { + __IM uint32_t MR0IF : 1; /*!< [0..0] Match channel 0 interrupt flag */ + __IM uint32_t MR1IF : 1; /*!< [1..1] Match channel 1 interrupt flag */ + uint32_t : 2; + __IM uint32_t CAP0IF : 1; /*!< [4..4] Capture channel 0 interrupt flag */ + __IM uint32_t MR9IF : 1; /*!< [5..5] Match channel 9 interrupt flag */ + uint32_t : 26; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x000000AC) Offset:0xAC CT16Bn Interrupt Clear Register */ + + struct { + __OM uint32_t MR0IC : 1; /*!< [0..0] MR0IF clear bit */ + __OM uint32_t MR1IC : 1; /*!< [1..1] MR1IF clear bit */ + uint32_t : 2; + __OM uint32_t CAP0IC : 1; /*!< [4..4] CAP0IF clear bit */ + __OM uint32_t MR9IC : 1; /*!< [5..5] MR9IF clear bit */ + uint32_t : 26; + } IC_b; + } ; + + union { + __IOM uint32_t PWMmNIOCTRL; /*!< (@ 0x000000B0) Offset:0xB0 CT16Bn PWMmN IO Control register */ + + struct { + __IOM uint32_t PWM0NIOEN : 2; /*!< [1..0] CT16Bn_PWM0N/GPIO selection bit */ + __IOM uint32_t PWM1NIOEN : 2; /*!< [3..2] CT16Bn_PWM0N/GPIO selection bit */ + uint32_t : 20; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWMmNIOCTRL_b; + } ; + + union { + __IOM uint32_t PWM0NDB; /*!< (@ 0x000000B4) Offset:0xB4 CT16Bn PWM0N Dead-band Period Register */ + + struct { + __IOM uint32_t DB : 10; /*!< [9..0] PWM0N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) + cycle */ + uint32_t : 14; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWM0NDB_b; + } ; + + union { + __IOM uint32_t PWM1NDB; /*!< (@ 0x000000B8) Offset:0xB8 CT16Bn PWM1N Dead-band Period Register */ + + struct { + __IOM uint32_t DB : 10; /*!< [9..0] PWM1N output dead-band period time=DB*CT16Bn_PCLK*(PR+1) + cycle */ + uint32_t : 14; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWM1NDB_b; + } ; +} SN_CT16B3_Type; /*!< Size = 188 (0xbc) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CT16B5 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 16-bit Timer 5 with Capture function (SN_CT16B5) + */ + +typedef struct { /*!< (@ 0x4000A000) SN_CT16B5 Structure */ + + union { + __IOM uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT16Bn Timer Control Register */ + + struct { + __IOM uint32_t CEN : 1; /*!< [0..0] Counter enable */ + __IOM uint32_t CRST : 1; /*!< [1..1] Counter Reset */ + __IOM uint32_t CLKSEL : 2; /*!< [3..2] PCLK source */ + __IOM uint32_t CM : 3; /*!< [6..4] Counting mode selection */ + uint32_t : 25; + } TMRCTRL_b; + } ; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT16Bn Timer Counter Register */ + + struct { + __IOM uint32_t TC : 16; /*!< [15..0] Timer Counter */ + uint32_t : 16; + } TC_b; + } ; + + union { + __IOM uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT16Bn Prescale Register */ + + struct { + __IOM uint32_t PRE : 8; /*!< [7..0] Prescalzer */ + uint32_t : 24; + } PRE_b; + } ; + + union { + __IOM uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT16Bn Prescale Counter Register */ + + struct { + __IOM uint32_t PC : 8; /*!< [7..0] Prescaler Counter */ + uint32_t : 24; + } PC_b; + } ; + + union { + __IOM uint32_t CNTCTRL; /*!< (@ 0x00000010) Offset:0x10 CT16Bn Counter Control Register */ + + struct { + __IOM uint32_t CTM : 2; /*!< [1..0] Counter/Timer Mode */ + uint32_t : 30; + } CNTCTRL_b; + } ; + + union { + __IOM uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT16Bn Match Control Register */ + + struct { + __IOM uint32_t MR0IE : 1; /*!< [0..0] Enable generating an interrupt when MR0 matches TC */ + __IOM uint32_t MR0RST : 1; /*!< [1..1] Enable reset TC when MR0 matches TC */ + __IOM uint32_t MR0STOP : 1; /*!< [2..2] Stop TC and PC and clear CEN bit when MR0 matches TC */ + __IOM uint32_t MR1IE : 1; /*!< [3..3] Enable generating an interrupt when MR1 matches TC */ + __IOM uint32_t MR1RST : 1; /*!< [4..4] Enable reset TC when MR1 matches TC */ + __IOM uint32_t MR1STOP : 1; /*!< [5..5] Stop TC and PC and clear CEN bit when MR1 matches TC */ + __IOM uint32_t MR2IE : 1; /*!< [6..6] Enable generating an interrupt when MR2 matches TC */ + __IOM uint32_t MR2RST : 1; /*!< [7..7] Enable reset TC when MR2 matches TC */ + __IOM uint32_t MR2STOP : 1; /*!< [8..8] Stop TC and PC and clear CEN bit when MR2 matches TC */ + __IOM uint32_t MR3IE : 1; /*!< [9..9] Enable generating an interrupt when MR3 matches TC */ + __IOM uint32_t MR3RST : 1; /*!< [10..10] Enable reset TC when MR3 matches TC */ + __IOM uint32_t MR3STOP : 1; /*!< [11..11] Stop TC and PC and clear CEN bit when MR3 matches TC */ + uint32_t : 9; + __IOM uint32_t MR9IE : 1; /*!< [21..21] Enable generating an interrupt based on CM[2:0] when + MR9 matches the value in the TC */ + __IOM uint32_t MR9RST : 1; /*!< [22..22] Enable reset TC when MR9 matches TC */ + __IOM uint32_t MR9STOP : 1; /*!< [23..23] Stop TC and PC and clear CEN bit when MR9 matches TC */ + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MCTRL_b; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t MR0; /*!< (@ 0x00000020) Offset:0x20 CT16Bn MR0 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } MR0_b; + } ; + + union { + __IOM uint32_t MR1; /*!< (@ 0x00000024) Offset:0x24 CT16Bn MR1 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key */ + } MR1_b; + } ; + + union { + __IOM uint32_t MR2; /*!< (@ 0x00000028) Offset:0x28 CT16Bn MR2 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key */ + } MR2_b; + } ; + + union { + __IOM uint32_t MR3; /*!< (@ 0x0000002C) Offset:0x2C CT16Bn MR3 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key */ + } MR3_b; + } ; + __IM uint32_t RESERVED1[5]; + + union { + __IOM uint32_t MR9; /*!< (@ 0x00000044) Offset:0x44 CT16Bn MR9 Register */ + + struct { + __IOM uint32_t MR : 16; /*!< [15..0] Timer counter match value */ + uint32_t : 8; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key */ + } MR9_b; + } ; + __IM uint32_t RESERVED2[15]; + + union { + __IOM uint32_t CAPCTRL; /*!< (@ 0x00000084) Offset:0x84 CT16Bn Capture Control Register */ + + struct { + __IOM uint32_t CAP0RE : 1; /*!< [0..0] Capture/Reset on CT16Bn_CAP0 signal rising edge */ + __IOM uint32_t CAP0FE : 1; /*!< [1..1] Capture/Reset on CT16Bn_CAP0 signal falling edge */ + __IOM uint32_t CAP0IE : 1; /*!< [2..2] Interrupt on CT16Bn_CAP0 event */ + __IOM uint32_t CAP0EN : 1; /*!< [3..3] CAP0 function enable */ + uint32_t : 28; + } CAPCTRL_b; + } ; + + union { + __IM uint32_t CAP0; /*!< (@ 0x00000088) Offset:0x88 CT16Bn CAP0 Register */ + + struct { + __IM uint32_t CAP0 : 16; /*!< [15..0] Timer counter capture value */ + uint32_t : 16; + } CAP0_b; + } ; + + union { + __IOM uint32_t EM; /*!< (@ 0x0000008C) Offset:0x8C CT16Bn External Match Register */ + + struct { + __IOM uint32_t EM0 : 1; /*!< [0..0] When the TC matches MR0, this bit will act according + to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output. */ + __IOM uint32_t EM1 : 1; /*!< [1..1] When the TC matches MR1, this bit will act according + to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output. */ + __IOM uint32_t EM2 : 1; /*!< [2..2] When the TC matches MR2, this bit will act according + to EMC2[1:0], and also drive the state of CT16Bn_PWM2 output. */ + __IOM uint32_t EM3 : 1; /*!< [3..3] When the TC matches MR3, this bit will act according + to EMC3[1:0], and also drive the state of CT16Bn_PWM3 output. */ + __IOM uint32_t EMC0 : 2; /*!< [5..4] CT16Bn_PWM0 functionality */ + __IOM uint32_t EMC1 : 2; /*!< [7..6] CT16Bn_PWM1 functionality */ + __IOM uint32_t EMC2 : 2; /*!< [9..8] CT16Bn_PWM2 functionality */ + __IOM uint32_t EMC3 : 2; /*!< [11..10] CT16Bn_PWM3 functionality */ + uint32_t : 12; + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } EM_b; + } ; + __IM uint32_t RESERVED3[2]; + + union { + __IOM uint32_t PWMCTRL; /*!< (@ 0x00000098) Offset:0x98 CT16Bn PWM Control Register */ + + struct { + __IOM uint32_t PWM0EN : 1; /*!< [0..0] PWM0 enable */ + __IOM uint32_t PWM1EN : 1; /*!< [1..1] PWM1 enable */ + __IOM uint32_t PWM2EN : 1; /*!< [2..2] PWM2 enable */ + __IOM uint32_t PWM3EN : 1; /*!< [3..3] PWM2 enable */ + __IOM uint32_t PWM0MODE : 2; /*!< [5..4] PWM0 output mode */ + __IOM uint32_t PWM1MODE : 2; /*!< [7..6] PWM1 output mode */ + __IOM uint32_t PWM2MODE : 2; /*!< [9..8] PWM2 output mode */ + __IOM uint32_t PWM3MODE : 2; /*!< [11..10] PWM3 output mode */ + uint32_t : 8; + __IOM uint32_t PWM0IOEN : 1; /*!< [20..20] CT16Bn_PWM0/GPIO selection */ + __IOM uint32_t PWM1IOEN : 1; /*!< [21..21] CT16Bn_PWM1/GPIO selection */ + __IOM uint32_t PWM2IOEN : 1; /*!< [22..22] CT16Bn_PWM2/GPIO selection */ + __IOM uint32_t PWM3IOEN : 1; /*!< [23..23] CT16Bn_PWM3/GPIO selection */ + __OM uint32_t PWMKEY : 8; /*!< [31..24] PWM register key. */ + } PWMCTRL_b; + } ; + __IM uint32_t RESERVED4[3]; + + union { + __IM uint32_t RIS; /*!< (@ 0x000000A8) Offset:0xA8 CT16Bn Raw Interrupt Status Register */ + + struct { + __IM uint32_t MR0IF : 1; /*!< [0..0] Match channel 0 interrupt flag */ + __IM uint32_t MR1IF : 1; /*!< [1..1] Match channel 1 interrupt flag */ + __IM uint32_t MR2IF : 1; /*!< [2..2] Match channel 2 interrupt flag */ + __IM uint32_t MR3IF : 1; /*!< [3..3] Match channel 3 interrupt flag */ + __IM uint32_t CAP0IF : 1; /*!< [4..4] Capture channel 0 interrupt flag */ + __IM uint32_t MR9IF : 1; /*!< [5..5] Match channel 9 interrupt flag */ + uint32_t : 26; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x000000AC) Offset:0xAC CT16Bn Interrupt Clear Register */ + + struct { + __OM uint32_t MR0IC : 1; /*!< [0..0] MR0IF clear bit */ + __OM uint32_t MR1IC : 1; /*!< [1..1] MR1IF clear bit */ + __OM uint32_t MR2IC : 1; /*!< [2..2] MR2IF clear bit */ + __OM uint32_t MR3IC : 1; /*!< [3..3] MR3IF clear bit */ + __OM uint32_t CAP0IC : 1; /*!< [4..4] CAP0IF clear bit */ + __OM uint32_t MR9IC : 1; /*!< [5..5] MR9IF clear bit */ + uint32_t : 26; + } IC_b; + } ; +} SN_CT16B5_Type; /*!< Size = 176 (0xb0) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (SN_WDT) + */ + +typedef struct { /*!< (@ 0x40010000) SN_WDT Structure */ + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000000) Offset:0x00 WDT Configuration Register */ + + struct { + __IOM uint32_t WDTEN : 1; /*!< [0..0] WDT enable */ + __IOM uint32_t WDTIE : 1; /*!< [1..1] WDT interrupt enable */ + __IOM uint32_t WDTINT : 1; /*!< [2..2] WDT interrupt flag */ + uint32_t : 13; + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } CFG_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t TC; /*!< (@ 0x00000008) Offset:0x08 WDT Timer Constant Register */ + + struct { + __IOM uint32_t TC : 8; /*!< [7..0] Watchdog timer constant reload value */ + uint32_t : 8; + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } TC_b; + } ; + + union { + __OM uint32_t FEED; /*!< (@ 0x0000000C) Offset:0x0C WDT Feed Register */ + + struct { + __OM uint32_t FV : 16; /*!< [15..0] Watchdog feed value */ + __OM uint32_t WDKEY : 16; /*!< [31..16] WDT register key */ + } FEED_b; + } ; +} SN_WDT_Type; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real-time Clock (SN_RTC) + */ + +typedef struct { /*!< (@ 0x40012000) SN_RTC Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 RTC Control Register */ + + struct { + __IOM uint32_t RTCEN : 1; /*!< [0..0] RTC enable */ + uint32_t : 31; + } CTRL_b; + } ; + + union { + __IOM uint32_t CLKS; /*!< (@ 0x00000004) Offset:0x04 RTC Clock Source Register */ + + struct { + __IOM uint32_t CLKSEL : 1; /*!< [0..0] RTC clock source */ + uint32_t : 31; + } CLKS_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000008) Offset:0x08 RTC Interrupt Enable Register */ + + struct { + __IOM uint32_t SECIE : 1; /*!< [0..0] Second interrupt enable */ + uint32_t : 31; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x0000000C) Offset:0x0C RTC Raw Interrupt Status Register */ + + struct { + __IM uint32_t SECIF : 1; /*!< [0..0] Second interrupt flag */ + uint32_t : 31; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000010) Offset:0x10 RTC Interrupt Clear Register */ + + struct { + __OM uint32_t SECIC : 1; /*!< [0..0] Second interrupt flag clear */ + uint32_t : 31; + } IC_b; + } ; + __IOM uint32_t SECCNTV; /*!< (@ 0x00000014) Offset:0x14 RTC Second Counter Reload Value Register */ + __IM uint32_t SECCNT; /*!< (@ 0x00000018) Offset:0x18 RTC Second Counter Register */ +} SN_RTC_Type; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI0 (SN_SPI0) + */ + +typedef struct { /*!< (@ 0x4001C000) SN_SPI0 Structure */ + + union { + __IOM uint32_t CTRL0; /*!< (@ 0x00000000) Offset:0x00 SPI0 Control Register 0 */ + + struct { + __IOM uint32_t SPIEN : 1; /*!< [0..0] SPI enable */ + __IOM uint32_t LOOPBACK : 1; /*!< [1..1] Loopback mode enable */ + __IOM uint32_t SDODIS : 1; /*!< [2..2] Slave data out disable */ + __IOM uint32_t MS : 1; /*!< [3..3] Master/Slave selection */ + __IOM uint32_t FORMAT : 1; /*!< [4..4] Interface format */ + uint32_t : 1; + __OM uint32_t FRESET : 2; /*!< [7..6] SPI FSM and FIFO Reset */ + __IOM uint32_t DL : 4; /*!< [11..8] Data length = DL[3:0]+1 */ + __IOM uint32_t TXFIFOTH : 3; /*!< [14..12] TX FIFO Threshold level */ + __IOM uint32_t RXFIFOTH : 3; /*!< [17..15] RX FIFO Threshold level */ + __IOM uint32_t SELDIS : 1; /*!< [18..18] Auto-SEL disable bit */ + uint32_t : 13; + } CTRL0_b; + } ; + + union { + __IOM uint32_t CTRL1; /*!< (@ 0x00000004) Offset:0x04 SPI0 Control Register 1 */ + + struct { + __IOM uint32_t MLSB : 1; /*!< [0..0] MSB/LSB seletion */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock priority selection */ + __IOM uint32_t CPHA : 1; /*!< [2..2] Clock phase of edge sampling */ + uint32_t : 29; + } CTRL1_b; + } ; + + union { + __IOM uint32_t CLKDIV; /*!< (@ 0x00000008) Offset:0x08 SPI0 Clock Divider Register */ + + struct { + __IOM uint32_t DIV : 8; /*!< [7..0] SPI0 SCK */ + uint32_t : 24; + } CLKDIV_b; + } ; + + union { + __IM uint32_t STAT; /*!< (@ 0x0000000C) Offset:0x0C SPI0 Status Register */ + + struct { + __IM uint32_t TX_EMPTY : 1; /*!< [0..0] TX FIFO empty flag */ + __IM uint32_t TX_FULL : 1; /*!< [1..1] TX FIFO full flag */ + __IM uint32_t RX_EMPTY : 1; /*!< [2..2] RX FIFO empty flag */ + __IM uint32_t RX_FULL : 1; /*!< [3..3] RX FIFO full flag */ + __IM uint32_t BUSY : 1; /*!< [4..4] Busy flag */ + __IM uint32_t TXFIFOTHF : 1; /*!< [5..5] TX FIFO threshold flag */ + __IM uint32_t RXFIFOTHF : 1; /*!< [6..6] RX FIFO threshold flag */ + uint32_t : 25; + } STAT_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000010) Offset:0x10 SPI0 Interrupt Enable Register */ + + struct { + __IOM uint32_t RXOVFIE : 1; /*!< [0..0] RX FIFO overflow interrupt enable */ + __IOM uint32_t RXTOIE : 1; /*!< [1..1] RX time-out interrupt enable */ + __IOM uint32_t RXFIFOTHIE : 1; /*!< [2..2] RX FIFO threshold interrupt enable */ + __IOM uint32_t TXFIFOTHIE : 1; /*!< [3..3] TX FIFO threshold interrupt enable */ + __IOM uint32_t DMAHTIE : 1; /*!< [4..4] DMA half transfer interrupt enable bit */ + __IOM uint32_t DMATCIE : 1; /*!< [5..5] DMA transfer complete interrupt enable bit */ + uint32_t : 26; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x00000014) Offset:0x14 SPI0 Raw Interrupt Status Register */ + + struct { + __IM uint32_t RXOVFIF : 1; /*!< [0..0] RX FIFO overflow interrupt flag */ + __IM uint32_t RXTOIF : 1; /*!< [1..1] RX time-out interrupt flag */ + __IM uint32_t RXFIFOTHIF : 1; /*!< [2..2] RX FIFO threshold interrupt flag */ + __IM uint32_t TXFIFOTHIF : 1; /*!< [3..3] TX FIFO threshold interrupt flag */ + __IM uint32_t DMAHTIF : 1; /*!< [4..4] RX FIFO threshold interrupt flag */ + __IM uint32_t DMATCIF : 1; /*!< [5..5] DMA transfer complete flag */ + uint32_t : 26; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000018) Offset:0x18 SPI0 Interrupt Clear Register */ + + struct { + __OM uint32_t RXOVFIC : 1; /*!< [0..0] RX FIFO overflow flag clear */ + __OM uint32_t RXTOIC : 1; /*!< [1..1] RX time-out interrupt flag clear */ + __OM uint32_t RXFIFOTHIC : 1; /*!< [2..2] RX Interrupt flag Clear */ + __OM uint32_t TXFIFOTHIC : 1; /*!< [3..3] TX Interrupt flag Clear */ + __OM uint32_t DMAHTIC : 1; /*!< [4..4] Select the DMAHTIF flag to be cleared */ + __OM uint32_t DMATCIC : 1; /*!< [5..5] Select the DMATCIF flag to be cleared */ + uint32_t : 26; + } IC_b; + } ; + + union { + __IOM uint32_t DATA; /*!< (@ 0x0000001C) Offset:0x1C SPI0 Data Register */ + + struct { + __IOM uint32_t Data : 16; /*!< [15..0] Data */ + uint32_t : 16; + } DATA_b; + } ; + + union { + __IOM uint32_t DFDLY; /*!< (@ 0x00000020) Offset:0x20 SPI0 Data Fetch Register */ + + struct { + __IOM uint32_t DFETCH_EN : 1; /*!< [0..0] SPI0 data fetch control bit */ + uint32_t : 31; + } DFDLY_b; + } ; + + union { + __IOM uint32_t DMACTRL; /*!< (@ 0x00000024) Offset:0x24 SPI0 DMA Control register */ + + struct { + __IOM uint32_t DMAEN : 1; /*!< [0..0] SPI to SPI DMA enable bit */ + __IOM uint32_t DIR : 1; /*!< [1..1] SPI data transfer direction */ + uint32_t : 30; + } DMACTRL_b; + } ; + + union { + __IOM uint32_t DMACNT; /*!< (@ 0x00000028) Offset:0x28 SPI0 DMA Control register */ + + struct { + __IOM uint32_t CNT : 28; /*!< [27..0] Number of data to DMA RX count transfer */ + uint32_t : 4; + } DMACNT_b; + } ; + + union { + __IOM uint32_t DMAHTCNT; /*!< (@ 0x0000002C) Offset:0x2C SPI0 DMA Control register */ + + struct { + __IOM uint32_t HTCNT : 28; /*!< [27..0] Number of data to DMA RX half count transfer */ + uint32_t : 4; + } DMAHTCNT_b; + } ; + + union { + __IM uint32_t CURCNT; /*!< (@ 0x00000030) Offset:0x30 SPI0 DMA Control register */ + + struct { + __IM uint32_t CURCNT : 28; /*!< [27..0] This field indicates DMA current transfer data counter + pointer. */ + uint32_t : 4; + } CURCNT_b; + } ; +} SN_SPI0_Type; /*!< Size = 52 (0x34) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_SPI1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI1 (SN_SPI1) + */ + +typedef struct { /*!< (@ 0x40058000) SN_SPI1 Structure */ + + union { + __IOM uint32_t CTRL0; /*!< (@ 0x00000000) Offset:0x00 SPI1 Control Register 0 */ + + struct { + __IOM uint32_t SPIEN : 1; /*!< [0..0] SPI enable */ + __IOM uint32_t LOOPBACK : 1; /*!< [1..1] Loopback mode enable */ + __IOM uint32_t SDODIS : 1; /*!< [2..2] Slave data out disable */ + __IOM uint32_t MS : 1; /*!< [3..3] Master/Slave selection */ + __IOM uint32_t FORMAT : 1; /*!< [4..4] Interface format */ + uint32_t : 1; + __OM uint32_t FRESET : 2; /*!< [7..6] SPI FSM and FIFO Reset */ + __IOM uint32_t DL : 4; /*!< [11..8] Data length = DL[3:0]+1 */ + __IOM uint32_t TXFIFOTH : 3; /*!< [14..12] TX FIFO Threshold level */ + __IOM uint32_t RXFIFOTH : 3; /*!< [17..15] RX FIFO Threshold level */ + __IOM uint32_t SELDIS : 1; /*!< [18..18] Auto-SEL disable bit */ + uint32_t : 13; + } CTRL0_b; + } ; + + union { + __IOM uint32_t CTRL1; /*!< (@ 0x00000004) Offset:0x04 SPI1 Control Register 1 */ + + struct { + __IOM uint32_t MLSB : 1; /*!< [0..0] MSB/LSB seletion */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock priority selection */ + __IOM uint32_t CPHA : 1; /*!< [2..2] Clock phase of edge sampling */ + uint32_t : 29; + } CTRL1_b; + } ; + + union { + __IOM uint32_t CLKDIV; /*!< (@ 0x00000008) Offset:0x08 SPI1 Clock Divider Register */ + + struct { + __IOM uint32_t DIV : 8; /*!< [7..0] SPI1 SCK */ + uint32_t : 24; + } CLKDIV_b; + } ; + + union { + __IM uint32_t STAT; /*!< (@ 0x0000000C) Offset:0x0C SPI1 Status Register */ + + struct { + __IM uint32_t TX_EMPTY : 1; /*!< [0..0] TX FIFO empty flag */ + __IM uint32_t TX_FULL : 1; /*!< [1..1] TX FIFO full flag */ + __IM uint32_t RX_EMPTY : 1; /*!< [2..2] RX FIFO empty flag */ + __IM uint32_t RX_FULL : 1; /*!< [3..3] RX FIFO full flag */ + __IM uint32_t BUSY : 1; /*!< [4..4] Busy flag */ + __IM uint32_t TXFIFOTHF : 1; /*!< [5..5] TX FIFO threshold flag */ + __IM uint32_t RXFIFOTHF : 1; /*!< [6..6] RX FIFO threshold flag */ + uint32_t : 25; + } STAT_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000010) Offset:0x10 SPI1 Interrupt Enable Register */ + + struct { + __IOM uint32_t RXOVFIE : 1; /*!< [0..0] RX FIFO overflow interrupt enable */ + __IOM uint32_t RXTOIE : 1; /*!< [1..1] RX time-out interrupt enable */ + __IOM uint32_t RXFIFOTHIE : 1; /*!< [2..2] RX FIFO threshold interrupt enable */ + __IOM uint32_t TXFIFOTHIE : 1; /*!< [3..3] TX FIFO threshold interrupt enable */ + uint32_t : 28; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x00000014) Offset:0x14 SPI1 Raw Interrupt Status Register */ + + struct { + __IM uint32_t RXOVFIF : 1; /*!< [0..0] RX FIFO overflow interrupt flag */ + __IM uint32_t RXTOIF : 1; /*!< [1..1] RX time-out interrupt flag */ + __IM uint32_t RXFIFOTHIF : 1; /*!< [2..2] RX FIFO threshold interrupt flag */ + __IM uint32_t TXFIFOTHIF : 1; /*!< [3..3] TX FIFO threshold interrupt flag */ + uint32_t : 28; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000018) Offset:0x18 SPI1 Interrupt Clear Register */ + + struct { + __OM uint32_t RXOVFIC : 1; /*!< [0..0] RX FIFO overflow flag clear */ + __OM uint32_t RXTOIC : 1; /*!< [1..1] RX time-out interrupt flag clear */ + __OM uint32_t RXFIFOTHIC : 1; /*!< [2..2] RX Interrupt flag Clear */ + __OM uint32_t TXFIFOTHIC : 1; /*!< [3..3] TX Interrupt flag Clear */ + uint32_t : 28; + } IC_b; + } ; + + union { + __IOM uint32_t DATA; /*!< (@ 0x0000001C) Offset:0x1C SPI1 Data Register */ + + struct { + __IOM uint32_t Data : 16; /*!< [15..0] Data */ + uint32_t : 16; + } DATA_b; + } ; + + union { + __IOM uint32_t DFDLY; /*!< (@ 0x00000020) Offset:0x20 SPI1 Data Fetch Register */ + + struct { + __IOM uint32_t DFETCH_EN : 1; /*!< [0..0] SPI1 data fetch control bit */ + uint32_t : 31; + } DFDLY_b; + } ; +} SN_SPI1_Type; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_I2C0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C0 (SN_I2C0) + */ + +typedef struct { /*!< (@ 0x40018000) SN_I2C0 Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 I2Cn Control Register */ + + struct { + uint32_t : 1; + __IOM uint32_t NACK : 1; /*!< [1..1] NACK assert flag */ + __IOM uint32_t ACK : 1; /*!< [2..2] ACK assert flag */ + uint32_t : 1; + __IOM uint32_t STO : 1; /*!< [4..4] STOP assert flag */ + __IOM uint32_t STA : 1; /*!< [5..5] START assert flag */ + uint32_t : 1; + __IOM uint32_t I2CMODE : 1; /*!< [7..7] I2C mode */ + __IOM uint32_t I2CEN : 1; /*!< [8..8] I2Cn interface enable */ + uint32_t : 23; + } CTRL_b; + } ; + + union { + __IOM uint32_t STAT; /*!< (@ 0x00000004) Offset:0x04 I2Cn Status Register */ + + struct { + __IM uint32_t RX_DN : 1; /*!< [0..0] RX done status */ + __IM uint32_t ACK_STAT : 1; /*!< [1..1] ACK done status */ + __IM uint32_t NACK_STAT : 1; /*!< [2..2] NACK done status */ + __IM uint32_t STOP_DN : 1; /*!< [3..3] STOP done status */ + __IM uint32_t START_DN : 1; /*!< [4..4] START done status */ + __IM uint32_t MST : 1; /*!< [5..5] I2C master/slave status */ + __IM uint32_t SLV_RX_HIT : 1; /*!< [6..6] Slave RX address hit flag */ + __IM uint32_t SLV_TX_HIT : 1; /*!< [7..7] Slave TX address hit flag */ + __IM uint32_t LOST_ARB : 1; /*!< [8..8] Lost arbitration status */ + __IM uint32_t TIMEOUT : 1; /*!< [9..9] Time-out status */ + uint32_t : 5; + __IOM uint32_t I2CIF : 1; /*!< [15..15] I2C interrupt flag */ + uint32_t : 16; + } STAT_b; + } ; + + union { + __IOM uint32_t TXDATA; /*!< (@ 0x00000008) Offset:0x08 I2Cn TX Data Register */ + + struct { + __IOM uint32_t Data : 8; /*!< [7..0] TX Data */ + uint32_t : 24; + } TXDATA_b; + } ; + + union { + __IM uint32_t RXDATA; /*!< (@ 0x0000000C) Offset:0x0C I2Cn RX Data Register */ + + struct { + __IM uint32_t Data : 8; /*!< [7..0] RX Data received when RX_DN=1 */ + uint32_t : 24; + } RXDATA_b; + } ; + + union { + __IOM uint32_t SLVADDR0; /*!< (@ 0x00000010) Offset:0x10 I2Cn Slave Address 0 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 0 */ + uint32_t : 20; + __IOM uint32_t GCEN : 1; /*!< [30..30] General call address enable */ + __IOM uint32_t ADD_MODE : 1; /*!< [31..31] Slave address mode */ + } SLVADDR0_b; + } ; + + union { + __IOM uint32_t SLVADDR1; /*!< (@ 0x00000014) Offset:0x14 I2Cn Slave Address 1 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 1 */ + uint32_t : 22; + } SLVADDR1_b; + } ; + + union { + __IOM uint32_t SLVADDR2; /*!< (@ 0x00000018) Offset:0x18 I2Cn Slave Address 2 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 2 */ + uint32_t : 22; + } SLVADDR2_b; + } ; + + union { + __IOM uint32_t SLVADDR3; /*!< (@ 0x0000001C) Offset:0x1C I2Cn Slave Address 3 Register */ + + struct { + __IOM uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 3 */ + uint32_t : 22; + } SLVADDR3_b; + } ; + + union { + __IOM uint32_t SCLHT; /*!< (@ 0x00000020) Offset:0x20 I2Cn SCL High Time Register */ + + struct { + __IOM uint32_t SCLH : 8; /*!< [7..0] SCLn High period time=(SCLHT+1)*I2Cn_PCLK cycle */ + uint32_t : 24; + } SCLHT_b; + } ; + + union { + __IOM uint32_t SCLLT; /*!< (@ 0x00000024) Offset:0x24 I2Cn SCL Low Time Register */ + + struct { + __IOM uint32_t SCLL : 8; /*!< [7..0] SCLn Low period time=(SCLLT+1)*I2Cn_PCLK cycle */ + uint32_t : 24; + } SCLLT_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t TOCTRL; /*!< (@ 0x0000002C) Offset:0x2C I2Cn Timeout Control Register */ + + struct { + __IOM uint32_t TO : 16; /*!< [15..0] Timeout period time = TO*32*I2Cn_PCLK cycle */ + uint32_t : 16; + } TOCTRL_b; + } ; +} SN_I2C0_Type; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART0 (SN_UART0) + */ + +typedef struct { /*!< (@ 0x40016000) SN_UART0 Structure */ + + union { + union { + __IM uint32_t RB; /*!< (@ 0x00000000) Offset:0x00 UARTn Receiver Buffer Register */ + + struct { + __IM uint32_t RB : 8; /*!< [7..0] The received byte in UART RX FIFO */ + uint32_t : 24; + } RB_b; + } ; + + union { + __OM uint32_t TH; /*!< (@ 0x00000000) Offset:0x00 UARTn Transmit Holding Register */ + + struct { + __OM uint32_t TH : 8; /*!< [7..0] The byte to be transmitted in UART TX FIFO when transmitter + is available */ + uint32_t : 24; + } TH_b; + } ; + + union { + __IOM uint32_t DLL; /*!< (@ 0x00000000) Offset:0x00 UARTn Divisor Latch LSB Register */ + + struct { + __IOM uint32_t DLL : 8; /*!< [7..0] DLL and DLM register determines the baud rate of UARTn */ + uint32_t : 24; + } DLL_b; + } ; + }; + + union { + union { + __IOM uint32_t DLM; /*!< (@ 0x00000004) Offset:0x04 UARTn Divisor Latch MSB Register */ + + struct { + __IOM uint32_t DLM : 8; /*!< [7..0] DLL and DLM register determines the baud rate of USARTn */ + uint32_t : 24; + } DLM_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000004) Offset:0x04 UARTn Interrupt Enable Register */ + + struct { + __IOM uint32_t RDAIE : 1; /*!< [0..0] RDA interrupt enable */ + __IOM uint32_t THREIE : 1; /*!< [1..1] THRE interrupt enable */ + __IOM uint32_t RLSIE : 1; /*!< [2..2] RLS interrupt enable */ + uint32_t : 1; + __IOM uint32_t TEMTIE : 1; /*!< [4..4] TEMT interrupt enable */ + uint32_t : 3; + __IOM uint32_t ABEOIE : 1; /*!< [8..8] ABE0 interrupt enable */ + __IOM uint32_t ABTOIE : 1; /*!< [9..9] ABT0 interrupt enable */ + uint32_t : 22; + } IE_b; + } ; + }; + + union { + union { + __IM uint32_t II; /*!< (@ 0x00000008) Offset:0x08 UARTn Interrupt Identification Register */ + + struct { + __IM uint32_t INTSTATUS : 1; /*!< [0..0] Interrupt status */ + __IM uint32_t INTID : 3; /*!< [3..1] Interrupt ID of RX FIFO */ + uint32_t : 2; + __IM uint32_t FIFOEN : 2; /*!< [7..6] Equal to FIFOEN bits in USARTn_FIFOCTRL register */ + __IM uint32_t ABEOIF : 1; /*!< [8..8] ABEO interrupt flag */ + __IM uint32_t ABTOIF : 1; /*!< [9..9] ABTO interrupt flag */ + uint32_t : 22; + } II_b; + } ; + + union { + __OM uint32_t FIFOCTRL; /*!< (@ 0x00000008) Offset:0x08 UARTn FIFO Control Register */ + + struct { + __OM uint32_t FIFOEN : 1; /*!< [0..0] FIFO enable */ + uint32_t : 5; + __OM uint32_t RXTL : 2; /*!< [7..6] RX trigger level */ + uint32_t : 24; + } FIFOCTRL_b; + } ; + }; + + union { + __IOM uint32_t LC; /*!< (@ 0x0000000C) Offset:0x0C UARTn Line Control Register */ + + struct { + __IOM uint32_t WLS : 2; /*!< [1..0] Word length selection */ + __IOM uint32_t SBS : 1; /*!< [2..2] Stop bit selection */ + __IOM uint32_t PE : 1; /*!< [3..3] Parity enable */ + __IOM uint32_t PS : 2; /*!< [5..4] Parity selection */ + __IOM uint32_t BC : 1; /*!< [6..6] Break control */ + __IOM uint32_t DLAB : 1; /*!< [7..7] Divisor Latch access */ + uint32_t : 24; + } LC_b; + } ; + __IM uint32_t RESERVED; + + union { + __IM uint32_t LS; /*!< (@ 0x00000014) Offset:0x14 UARTn Line Status Register */ + + struct { + __IM uint32_t RDR : 1; /*!< [0..0] Receiver data ready flag */ + __IM uint32_t OE : 1; /*!< [1..1] Overrun error flag */ + __IM uint32_t PE : 1; /*!< [2..2] Parity error flag */ + __IM uint32_t FE : 1; /*!< [3..3] Framing error flag */ + __IM uint32_t BI : 1; /*!< [4..4] Break interrupt flag */ + __IM uint32_t THRE : 1; /*!< [5..5] THR empty flag */ + __IM uint32_t TEMT : 1; /*!< [6..6] Transmitter empty flag */ + __IM uint32_t RXFE : 1; /*!< [7..7] Receiver FIFO error flag */ + uint32_t : 24; + } LS_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t SP; /*!< (@ 0x0000001C) Offset:0x1C UARTn Scratch Pad Register */ + + struct { + __IOM uint32_t PAD : 8; /*!< [7..0] Pad informaton */ + uint32_t : 24; + } SP_b; + } ; + + union { + __IOM uint32_t ABCTRL; /*!< (@ 0x00000020) Offset:0x20 UARTn Auto-baud Control Register */ + + struct { + __IOM uint32_t START : 1; /*!< [0..0] Auto-baud run bit */ + __IOM uint32_t MODE : 1; /*!< [1..1] Auto-baud mode selection */ + __IOM uint32_t AUTORESTART : 1; /*!< [2..2] Restart mode selection */ + uint32_t : 5; + __OM uint32_t ABEOIFC : 1; /*!< [8..8] Clear ABEOIF flag */ + __OM uint32_t ABTOIFC : 1; /*!< [9..9] Clear ABTOIF flag */ + uint32_t : 22; + } ABCTRL_b; + } ; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t FD; /*!< (@ 0x00000028) Offset:0x28 UARTn Fractional Divider Register */ + + struct { + __IOM uint32_t DIVADDVAL : 4; /*!< [3..0] Baud rate generation prescaler divisor value */ + __IOM uint32_t MULVAL : 4; /*!< [7..4] Baud rate generation prescaler multiplier value */ + __IOM uint32_t OVER8 : 1; /*!< [8..8] Oversampling value */ + uint32_t : 23; + } FD_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000030) Offset:0x30 UARTn Control Register */ + + struct { + __IOM uint32_t UARTEN : 1; /*!< [0..0] USART enable */ + __IOM uint32_t MODE : 3; /*!< [3..1] UART mode */ + uint32_t : 2; + __IOM uint32_t RXEN : 1; /*!< [6..6] RX enable */ + __IOM uint32_t TXEN : 1; /*!< [7..7] TX enable */ + uint32_t : 24; + } CTRL_b; + } ; + + union { + __IOM uint32_t HDEN; /*!< (@ 0x00000034) Offset:0x34 UARTn Control Register */ + + struct { + __IOM uint32_t HDEN : 1; /*!< [0..0] Half-duplex mode enable */ + uint32_t : 31; + } HDEN_b; + } ; +} SN_UART0_Type; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_I2S0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2S (SN_I2S0) + */ + +typedef struct { /*!< (@ 0x4001A000) SN_I2S0 Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 I2Sn Control Register */ + + struct { + __IOM uint32_t START : 1; /*!< [0..0] Start Transmit/Receive */ + __IOM uint32_t MUTE : 1; /*!< [1..1] Mute enable */ + __IOM uint32_t MONO : 1; /*!< [2..2] Mono/stereo selection */ + __IOM uint32_t MS : 1; /*!< [3..3] Master/Slave selection bit */ + __IOM uint32_t FORMAT : 2; /*!< [5..4] I2S operation format */ + __IOM uint32_t TXEN : 1; /*!< [6..6] Transmit enable bit */ + __IOM uint32_t RXEN : 1; /*!< [7..7] Receiver enable bit */ + __OM uint32_t CLRTXFIFO : 1; /*!< [8..8] Clear I2S TX FIFO */ + __OM uint32_t CLRRXFIFO : 1; /*!< [9..9] Clear I2S RX FIFO */ + __IOM uint32_t DL : 2; /*!< [11..10] Data length */ + __IOM uint32_t TXFIFOTH : 3; /*!< [14..12] TX FIFO threshold level */ + uint32_t : 1; + __IOM uint32_t RXFIFOTH : 3; /*!< [18..16] RX FIFO threshold level */ + uint32_t : 1; + __IOM uint32_t CHLENGTH : 5; /*!< [24..20] Bit number of single channel */ + uint32_t : 6; + __IOM uint32_t I2SEN : 1; /*!< [31..31] I2S enable */ + } CTRL_b; + } ; + + union { + __IOM uint32_t CLK; /*!< (@ 0x00000004) Offset:0x04 I2Sn Clock Register */ + + struct { + __IOM uint32_t MCLKDIV : 3; /*!< [2..0] MCLK divider */ + __IOM uint32_t MCLKOEN : 1; /*!< [3..3] MLCK output enable */ + __IOM uint32_t MCLKSEL : 1; /*!< [4..4] MLCK source selection */ + uint32_t : 3; + __IOM uint32_t BCLKDIV : 8; /*!< [15..8] BCLK divider */ + __IOM uint32_t CLKSEL : 1; /*!< [16..16] I2S clock source */ + uint32_t : 15; + } CLK_b; + } ; + + union { + __IM uint32_t STATUS; /*!< (@ 0x00000008) Offset:0x08 I2Sn Status Register */ + + struct { + __IM uint32_t I2SINT : 1; /*!< [0..0] I2S interrupt flag */ + __IM uint32_t RIGHTCH : 1; /*!< [1..1] Current channel status */ + uint32_t : 4; + __IM uint32_t TXFIFOTHF : 1; /*!< [6..6] TX FIFO threshold flag */ + __IM uint32_t RXFIFOTHF : 1; /*!< [7..7] RX FIFO threshold flag */ + __IM uint32_t TXFIFOFULL : 1; /*!< [8..8] TX FIFO full flag */ + __IM uint32_t RXFIFOFULL : 1; /*!< [9..9] RX FIFO full flag */ + __IM uint32_t TXFIFOEMPTY : 1; /*!< [10..10] TX FIFO empty flag */ + __IM uint32_t RXFIFOEMPTY : 1; /*!< [11..11] RX FIFO empty flag */ + __IM uint32_t TXFIFOLV : 4; /*!< [15..12] TX FIFO used level */ + uint32_t : 1; + __IM uint32_t RXFIFOLV : 4; /*!< [20..17] RX FIFO used level */ + uint32_t : 11; + } STATUS_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x0000000C) Offset:0x0C I2Sn Interrupt Enable Register */ + + struct { + uint32_t : 4; + __IOM uint32_t TXFIFOOVFIEN : 1; /*!< [4..4] TX FIFO overflow interrupt enable */ + __IOM uint32_t RXFIFOUDFIEN : 1; /*!< [5..5] RX FIFO underflow interrupt enable */ + __IOM uint32_t TXFIFOTHIEN : 1; /*!< [6..6] TX FIFO threshold interrupt enable */ + __IOM uint32_t RXFIFOTHIEN : 1; /*!< [7..7] RX FIFO threshold interrupt enable */ + uint32_t : 24; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x00000010) Offset:0x10 I2Sn Raw Interrupt Status Register */ + + struct { + uint32_t : 4; + __IM uint32_t TXFIFOOVIF : 1; /*!< [4..4] TX FIFO overflow interrupt flag */ + __IM uint32_t RXFIFOUDIF : 1; /*!< [5..5] RX FIFO underflow interrupt flag */ + __IM uint32_t TXFIFOTHIF : 1; /*!< [6..6] TX FIFO threshold interrupt flag */ + __IM uint32_t RXFIFOTHIF : 1; /*!< [7..7] RX FIFO threshold interrupt flag */ + uint32_t : 24; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000014) Offset:0x14 I2Sn Interrupt Clear Register */ + + struct { + uint32_t : 4; + __OM uint32_t TXFIFOOVIC : 1; /*!< [4..4] TX FIFO overflow interrupt clear */ + __OM uint32_t RXFIFOUDIC : 1; /*!< [5..5] RX FIFO underflow interrupt clear */ + __OM uint32_t TXFIFOTHIC : 1; /*!< [6..6] TX FIFO threshold interrupt clear */ + __OM uint32_t RXFIFOTHIC : 1; /*!< [7..7] RX FIFO threshold interrupt clear */ + uint32_t : 24; + } IC_b; + } ; + __IM uint32_t RXFIFO; /*!< (@ 0x00000018) Offset:0x18 I2Sn RX FIFO Register */ + __OM uint32_t TXFIFO; /*!< (@ 0x0000001C) Offset:0x1C I2Sn TX FIFO Register */ +} SN_I2S0_Type; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_FLASH ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FLASH Memory Control Registers (SN_FLASH) + */ + +typedef struct { /*!< (@ 0x40062000) SN_FLASH Structure */ + + union { + __IOM uint32_t LPCTRL; /*!< (@ 0x00000000) Offset:0x00 Flash Low Power Control Register */ + + struct { + __IOM uint32_t LPMODE : 6; /*!< [5..0] Flash Low Power mode selection bit */ + uint32_t : 10; + __OM uint32_t FMCKEY : 16; /*!< [31..16] FMC verify key */ + } LPCTRL_b; + } ; + + union { + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Offset:0x04 Flash Status Register */ + + struct { + __IM uint32_t BUSY : 1; /*!< [0..0] Busy flag */ + uint32_t : 1; + __IOM uint32_t ERR : 1; /*!< [2..2] Erase/Error flag */ + uint32_t : 29; + } STATUS_b; + } ; + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000008) Offset:0x08 Flash Control Register */ + + struct { + __IOM uint32_t PG : 1; /*!< [0..0] Flash program mode chosen bit */ + __IOM uint32_t PER : 1; /*!< [1..1] Page erase mode chosen bit */ + __IOM uint32_t MER : 1; /*!< [2..2] Mass erase mode chosen bit */ + uint32_t : 3; + __IOM uint32_t START : 1; /*!< [6..6] Start erase/program operation */ + __IOM uint32_t CHK : 1; /*!< [7..7] Checksum calculation chosen */ + uint32_t : 24; + } CTRL_b; + } ; + __IOM uint32_t DATA; /*!< (@ 0x0000000C) Offset:0x0C Flash Data Register */ + __IOM uint32_t ADDR; /*!< (@ 0x00000010) Offset:0x10 Flash Address Register */ + + union { + __IM uint32_t CHKSUM; /*!< (@ 0x00000014) Offset:0x14 Flash Checksum Register */ + + struct { + __IM uint32_t UserROM : 16; /*!< [15..0] Checksum of User ROM */ + __IM uint32_t BootROM : 16; /*!< [31..16] Checksum of Boot ROM */ + } CHKSUM_b; + } ; + + union { + __IM uint32_t CHKSUM1; /*!< (@ 0x00000018) Offset:0x18 Flash Checksum Register 1 */ + + struct { + __IM uint32_t UserROM1 : 16; /*!< [15..0] Checksum of User ROM 1 */ + __IM uint32_t UserROM2 : 16; /*!< [31..16] Checksum of User ROM 2 */ + } CHKSUM1_b; + } ; + + union { + __IM uint32_t CHKSUM2; /*!< (@ 0x0000001C) Offset:0x1C Flash Checksum Register 2 */ + + struct { + __IM uint32_t UserROM3 : 16; /*!< [15..0] Checksum of User ROM 3 */ + __IM uint32_t UserROM4 : 16; /*!< [31..16] Checksum of User ROM 4 */ + } CHKSUM2_b; + } ; +} SN_FLASH_Type; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_LCD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief LCD Driver (SN_LCD) + */ + +typedef struct { /*!< (@ 0x40034000) SN_LCD Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 LCD Control register */ + + struct { + __IOM uint32_t LCDENB : 1; /*!< [0..0] LCD driver enable bit */ + __IOM uint32_t VLCD : 4; /*!< [4..1] VLCD voltage adjustment */ + __IOM uint32_t LCDIDLE : 1; /*!< [5..5] LCD idle state enable bit */ + __IOM uint32_t LCDSFM : 1; /*!< [6..6] LCD single frame function enable bit */ + __IOM uint32_t LSTC : 1; /*!< [7..7] LCD static mode control bit */ + __IOM uint32_t LCDCOM : 2; /*!< [9..8] Duty selection */ + __IOM uint32_t LCDCKS : 1; /*!< [10..10] LCD clock source selection */ + __IOM uint32_t LCDBNK : 1; /*!< [11..11] LCD blank control bit */ + __IOM uint32_t LCDRATE : 2; /*!< [13..12] LCD clock rate */ + __IOM uint32_t LCDBIA : 3; /*!< [16..14] LCD bias resistance selection bit */ + __IOM uint32_t LCDOUT : 1; /*!< [17..17] LCD VLCD/C2/V1 debug pins output control bit */ + uint32_t : 14; + } CTRL_b; + } ; + + union { + __IOM uint32_t FCC; /*!< (@ 0x00000004) Offset:0x04 LCD Frame Counter Control register */ + + struct { + __IOM uint32_t FCENB : 1; /*!< [0..0] LCD frame counter enable bit */ + __IOM uint32_t FCT : 6; /*!< [6..1] LCD frame counter threshold value */ + __IOM uint32_t FCIE : 1; /*!< [7..7] LCD frame interrupt enable bit */ + uint32_t : 24; + } FCC_b; + } ; + + union { + __IOM uint32_t RIS; /*!< (@ 0x00000008) Offset:0x08 LCD Raw Interrupt Status register */ + + struct { + __IOM uint32_t FCIF : 1; /*!< [0..0] LCD frame interrupt flag */ + uint32_t : 31; + } RIS_b; + } ; + + union { + __IOM uint32_t SEGSEL1; /*!< (@ 0x0000000C) Offset:0x0C LCD SEG Select register 1 */ + + struct { + __IOM uint32_t SEG0EN : 1; /*!< [0..0] SEG0 Enable bit */ + __IOM uint32_t SEG1EN : 1; /*!< [1..1] SEG1 Enable bit */ + __IOM uint32_t SEG2EN : 1; /*!< [2..2] SEG2 Enable bit */ + __IOM uint32_t SEG3EN : 1; /*!< [3..3] SEG3 Enable bit */ + __IOM uint32_t SEG4EN : 1; /*!< [4..4] SEG4 Enable bit */ + __IOM uint32_t SEG5EN : 1; /*!< [5..5] SEG5 Enable bit */ + __IOM uint32_t SEG6EN : 1; /*!< [6..6] SEG6 Enable bit */ + __IOM uint32_t SEG7EN : 1; /*!< [7..7] SEG7 Enable bit */ + __IOM uint32_t SEG8EN : 1; /*!< [8..8] SEG8 Enable bit */ + __IOM uint32_t SEG9EN : 1; /*!< [9..9] SEG9 Enable bit */ + __IOM uint32_t SEG10EN : 1; /*!< [10..10] SEG10 Enable bit */ + __IOM uint32_t SEG11EN : 1; /*!< [11..11] SEG11 Enable bit */ + __IOM uint32_t SEG12EN : 1; /*!< [12..12] SEG12 Enable bit */ + __IOM uint32_t SEG13EN : 1; /*!< [13..13] SEG13 Enable bit */ + __IOM uint32_t SEG14EN : 1; /*!< [14..14] SEG14 Enable bit */ + __IOM uint32_t SEG15EN : 1; /*!< [15..15] SEG15 Enable bit */ + __IOM uint32_t SEG16EN : 1; /*!< [16..16] SEG16 Enable bit */ + __IOM uint32_t SEG17EN : 1; /*!< [17..17] SEG17 Enable bit */ + __IOM uint32_t SEG18EN : 1; /*!< [18..18] SEG18 Enable bit */ + __IOM uint32_t SEG19EN : 1; /*!< [19..19] SEG19 Enable bit */ + __IOM uint32_t SEG20EN : 1; /*!< [20..20] SEG20 Enable bit */ + __IOM uint32_t SEG21EN : 1; /*!< [21..21] SEG21 Enable bit */ + __IOM uint32_t SEG22EN : 1; /*!< [22..22] SEG22 Enable bit */ + __IOM uint32_t SEG23EN : 1; /*!< [23..23] SEG23 Enable bit */ + __IOM uint32_t SEG24EN : 1; /*!< [24..24] SEG24 Enable bit */ + __IOM uint32_t SEG25EN : 1; /*!< [25..25] SEG25 Enable bit */ + __IOM uint32_t SEG26EN : 1; /*!< [26..26] SEG26 Enable bit */ + __IOM uint32_t SEG27EN : 1; /*!< [27..27] SEG27 Enable bit */ + __IOM uint32_t SEG28EN : 1; /*!< [28..28] SEG28 Enable bit */ + __IOM uint32_t SEG29EN : 1; /*!< [29..29] SEG29 Enable bit */ + __IOM uint32_t SEG30EN : 1; /*!< [30..30] SEG30 Enable bit */ + __IOM uint32_t SEG31EN : 1; /*!< [31..31] SEG31 Enable bit */ + } SEGSEL1_b; + } ; + + union { + __IOM uint32_t SEGSEL2; /*!< (@ 0x00000010) Offset:0x10 LCD SEG Select register 2 */ + + struct { + __IOM uint32_t SEG32EN : 1; /*!< [0..0] SEG32 Enable bit */ + __IOM uint32_t SEG33EN : 1; /*!< [1..1] SEG33 Enable bit */ + __IOM uint32_t SEG34EN : 1; /*!< [2..2] SEG34 Enable bit */ + __IOM uint32_t SEG35EN : 1; /*!< [3..3] SEG35 Enable bit */ + __IOM uint32_t SEG36EN : 1; /*!< [4..4] SEG36 Enable bit */ + __IOM uint32_t SEG37EN : 1; /*!< [5..5] SEG37 Enable bit */ + __IOM uint32_t SEG38EN : 1; /*!< [6..6] SEG38 Enable bit */ + __IOM uint32_t SEG39EN : 1; /*!< [7..7] SEG39 Enable bit */ + uint32_t : 24; + } SEGSEL2_b; + } ; + + union { + __IOM uint32_t SEGM0; /*!< (@ 0x00000014) Offset:0x14 LCD SEG Memory register 0 */ + + struct { + __IOM uint32_t SEG0 : 8; /*!< [7..0] SEG0 data for COM0~COM7 */ + __IOM uint32_t SEG1 : 8; /*!< [15..8] SEG1 data for COM0~COM7 */ + __IOM uint32_t SEG2 : 8; /*!< [23..16] SEG2 data for COM0~COM7 */ + __IOM uint32_t SEG3 : 8; /*!< [31..24] SEG3 data for COM0~COM7 */ + } SEGM0_b; + } ; + + union { + __IOM uint32_t SEGM1; /*!< (@ 0x00000018) Offset:0x18 LCD SEG Memory register 1 */ + + struct { + __IOM uint32_t SEG4 : 8; /*!< [7..0] SEG4 data for COM0~COM7 */ + __IOM uint32_t SEG5 : 8; /*!< [15..8] SEG5 data for COM0~COM7 */ + __IOM uint32_t SEG6 : 8; /*!< [23..16] SEG6 data for COM0~COM7 */ + __IOM uint32_t SEG7 : 8; /*!< [31..24] SEG7 data for COM0~COM7 */ + } SEGM1_b; + } ; + + union { + __IOM uint32_t SEGM2; /*!< (@ 0x0000001C) Offset:0x1C LCD SEG Memory register 2 */ + + struct { + __IOM uint32_t SEG8 : 8; /*!< [7..0] SEG8 data for COM0~COM7 */ + __IOM uint32_t SEG9 : 8; /*!< [15..8] SEG9 data for COM0~COM7 */ + __IOM uint32_t SEG10 : 8; /*!< [23..16] SEG10 data for COM0~COM7 */ + __IOM uint32_t SEG11 : 8; /*!< [31..24] SEG11 data for COM0~COM7 */ + } SEGM2_b; + } ; + + union { + __IOM uint32_t SEGM3; /*!< (@ 0x00000020) Offset:0x20 LCD SEG Memory register 3 */ + + struct { + __IOM uint32_t SEG12 : 8; /*!< [7..0] SEG12 data for COM0~COM7 */ + __IOM uint32_t SEG13 : 8; /*!< [15..8] SEG13 data for COM0~COM7 */ + __IOM uint32_t SEG14 : 8; /*!< [23..16] SEG14 data for COM0~COM7 */ + __IOM uint32_t SEG15 : 8; /*!< [31..24] SEG15 data for COM0~COM7 */ + } SEGM3_b; + } ; + + union { + __IOM uint32_t SEGM4; /*!< (@ 0x00000024) Offset:0x24 LCD SEG Memory register 4 */ + + struct { + __IOM uint32_t SEG16 : 8; /*!< [7..0] SEG16 data for COM0~COM7 */ + __IOM uint32_t SEG17 : 8; /*!< [15..8] SEG17 data for COM0~COM7 */ + __IOM uint32_t SEG18 : 8; /*!< [23..16] SEG18 data for COM0~COM7 */ + __IOM uint32_t SEG19 : 8; /*!< [31..24] SEG19 data for COM0~COM7 */ + } SEGM4_b; + } ; + + union { + __IOM uint32_t SEGM5; /*!< (@ 0x00000028) Offset:0x28 LCD SEG Memory register 5 */ + + struct { + __IOM uint32_t SEG20 : 8; /*!< [7..0] SEG20 data for COM0~COM7 */ + __IOM uint32_t SEG21 : 8; /*!< [15..8] SEG21 data for COM0~COM7 */ + __IOM uint32_t SEG22 : 8; /*!< [23..16] SEG22 data for COM0~COM7 */ + __IOM uint32_t SEG23 : 8; /*!< [31..24] SEG23 data for COM0~COM7 */ + } SEGM5_b; + } ; + + union { + __IOM uint32_t SEGM6; /*!< (@ 0x0000002C) Offset:0x2C LCD SEG Memory register 6 */ + + struct { + __IOM uint32_t SEG24 : 8; /*!< [7..0] SEG24 data for COM0~COM7 */ + __IOM uint32_t SEG25 : 8; /*!< [15..8] SEG25 data for COM0~COM7 */ + __IOM uint32_t SEG26 : 8; /*!< [23..16] SEG26 data for COM0~COM7 */ + __IOM uint32_t SEG27 : 8; /*!< [31..24] SEG27 data for COM0~COM7 */ + } SEGM6_b; + } ; + + union { + __IOM uint32_t SEGM7; /*!< (@ 0x00000030) Offset:0x30 LCD SEG Memory register 7 */ + + struct { + __IOM uint32_t SEG28 : 8; /*!< [7..0] SEG28 data for COM0~COM7 */ + __IOM uint32_t SEG29 : 8; /*!< [15..8] SEG29 data for COM0~COM7 */ + __IOM uint32_t SEG30 : 8; /*!< [23..16] SEG30 data for COM0~COM7 */ + __IOM uint32_t SEG31 : 8; /*!< [31..24] SEG31 data for COM0~COM7 */ + } SEGM7_b; + } ; + + union { + __IOM uint32_t SEGM8; /*!< (@ 0x00000034) Offset:0x34 LCD SEG Memory register 8 */ + + struct { + __IOM uint32_t SEG32 : 8; /*!< [7..0] SEG32 data for COM0~COM7 */ + __IOM uint32_t SEG33 : 8; /*!< [15..8] SEG33 data for COM0~COM7 */ + __IOM uint32_t SEG34 : 8; /*!< [23..16] SEG34 data for COM0~COM7 */ + __IOM uint32_t SEG35 : 8; /*!< [31..24] SEG35 data for COM0~COM7 */ + } SEGM8_b; + } ; + + union { + __IOM uint32_t SEGM9; /*!< (@ 0x00000038) Offset:0x38 LCD SEG Memory register 9 */ + + struct { + __IOM uint32_t SEG36 : 8; /*!< [7..0] SEG36 data for COM0~COM7 */ + __IOM uint32_t SEG37 : 8; /*!< [15..8] SEG37 data for COM0~COM7 */ + __IOM uint32_t SEG38 : 8; /*!< [23..16] SEG38 data for COM0~COM7 */ + __IOM uint32_t SEG39 : 8; /*!< [31..24] SEG39 data for COM0~COM7 */ + } SEGM9_b; + } ; +} SN_LCD_Type; /*!< Size = 60 (0x3c) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_CRC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Cyclic Redundancy Check (SN_CRC) + */ + +typedef struct { /*!< (@ 0x40038000) SN_CRC Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x0 CRC Control Register */ + + struct { + __IOM uint32_t CRC : 2; /*!< [1..0] CRC Polynomial */ + __IOM uint32_t RESET : 1; /*!< [2..2] CRC Reset bit */ + __IOM uint32_t URCRCEN : 1; /*!< [3..3] CRC calculation for the User ROM enable bit */ + __IM uint32_t BUSY : 1; /*!< [4..4] CRC calculation busy flag */ + uint32_t : 27; + } CTRL_b; + } ; + + union { + __IOM uint32_t DATA; /*!< (@ 0x00000004) Offset:0x4 CRC Data Register */ + + struct { + __IOM uint32_t DATA : 32; /*!< [31..0] CRC Data */ + } DATA_b; + } ; +} SN_CRC_Type; /*!< Size = 8 (0x8) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_OPA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief OP Amplifier (SN_OPA) + */ + +typedef struct { /*!< (@ 0x4002A000) SN_OPA Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x0 OPA Control Register */ + + struct { + __IOM uint32_t OP0EN : 1; /*!< [0..0] OP-Amp 0 enable bit */ + uint32_t : 2; + __IOM uint32_t OP0PS : 1; /*!< [3..3] OP-Amp 0 Positive input selection bit */ + __IOM uint32_t OP0NS : 1; /*!< [4..4] OP-Amp 0 Negatiove input selection bit */ + uint32_t : 3; + __IOM uint32_t OP1EN : 1; /*!< [8..8] OP-Amp 1 enable bit */ + uint32_t : 2; + __IOM uint32_t OP1PS : 1; /*!< [11..11] OP-Amp 1 Positive input selection bit */ + __IOM uint32_t OP1NS : 1; /*!< [12..12] OP-Amp 1 Negatiove input selection bit */ + uint32_t : 19; + } CTRL_b; + } ; +} SN_OPA_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_EBI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief External Bus Interface (SN_EBI) + */ + +typedef struct { /*!< (@ 0x40036000) SN_EBI Structure */ + + union { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x0 EBI Control Register */ + + struct { + __IOM uint32_t MODE0 : 2; /*!< [1..0] EBI bank 0 access mode */ + __IOM uint32_t MODE1 : 2; /*!< [3..2] EBI bank 1 access mode */ + __IOM uint32_t MODE2 : 2; /*!< [5..4] EBI bank 2 access mode */ + __IOM uint32_t MODE3 : 2; /*!< [7..6] EBI bank 3 access mode */ + __IOM uint32_t BANK0EN : 1; /*!< [8..8] EBI bank 0 enable bit */ + __IOM uint32_t BANK1EN : 1; /*!< [9..9] EBI bank 1 enable bit */ + __IOM uint32_t BANK2EN : 1; /*!< [10..10] EBI bank 2 enable bit */ + __IOM uint32_t BANK3EN : 1; /*!< [11..11] EBI bank 3 enable bit */ + __IOM uint32_t BC0EN : 1; /*!< [12..12] Byte control of bank 0 enable bit */ + __IOM uint32_t BC1EN : 1; /*!< [13..13] Byte control of bank 1 enable bit */ + __IOM uint32_t BC2EN : 1; /*!< [14..14] Byte control of bank 2 enable bit */ + __IOM uint32_t BC3EN : 1; /*!< [15..15] Byte control of bank 3 enable bit */ + __IOM uint32_t ARDY0EN : 1; /*!< [16..16] ARDY of bank 0 enable bit */ + __IOM uint32_t ARDY1EN : 1; /*!< [17..17] ARDY of bank 1 enable bit */ + __IOM uint32_t ARDY2EN : 1; /*!< [18..18] ARDY of bank 2 enable bit */ + __IOM uint32_t ARDY3EN : 1; /*!< [19..19] ARDY of bank 3 enable bit */ + __IOM uint32_t IDLETIME : 4; /*!< [23..20] Bus idle time */ + __IOM uint32_t BK8080MODE0 : 1; /*!< [24..24] Bank0 8080 Mode */ + __IOM uint32_t BK8080MODE1 : 1; /*!< [25..25] Bank1 8080 Mode */ + __IOM uint32_t BK8080MODE2 : 1; /*!< [26..26] Bank2 8080 Mode */ + __IOM uint32_t BK8080MODE3 : 1; /*!< [27..27] Bank3 8080 Mode */ + uint32_t : 4; + } CTRL_b; + } ; + + union { + __IOM uint32_t ALCTRL; /*!< (@ 0x00000004) Offset:0x4 EBI Address Latch Control Register */ + + struct { + __IOM uint32_t AL0 : 4; /*!< [3..0] Bank 0 address length=AL0+16 */ + __IOM uint32_t AL1 : 4; /*!< [7..4] Bank 1 address length=AL1+16 */ + __IOM uint32_t AL2 : 4; /*!< [11..8] Bank 2 address length=AL2+16 */ + __IOM uint32_t AL3 : 4; /*!< [15..12] Bank 3 address length=AL3+16 */ + uint32_t : 16; + } ALCTRL_b; + } ; + + union { + __IOM uint32_t STATUS; /*!< (@ 0x00000008) Offset:0x8 EBI Status Register */ + + struct { + __IM uint32_t EBIBUSY : 1; /*!< [0..0] EBI Busy */ + uint32_t : 3; + __IM uint32_t EBIARDY : 1; /*!< [4..4] EBI Asynchronous Ready status */ + uint32_t : 3; + __IOM uint32_t EBINSRST : 1; /*!< [8..8] EBI State machine reset */ + uint32_t : 23; + } STATUS_b; + } ; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t TADDR0; /*!< (@ 0x00000010) Offset:0x10 EBI Address Timing Register 0 */ + + struct { + __IOM uint32_t ADDRSETUP : 4; /*!< [3..0] Address Setup time */ + uint32_t : 4; + __IOM uint32_t ADDRHOLD : 4; /*!< [11..8] Address Hold time */ + uint32_t : 20; + } TADDR0_b; + } ; + + union { + __IOM uint32_t TADDR1; /*!< (@ 0x00000014) Offset:0x14 EBI Address Timing Register 1 */ + + struct { + __IOM uint32_t ADDRSETUP : 4; /*!< [3..0] Address Setup time */ + uint32_t : 4; + __IOM uint32_t ADDRHOLD : 4; /*!< [11..8] Address Hold time */ + uint32_t : 20; + } TADDR1_b; + } ; + + union { + __IOM uint32_t TADDR2; /*!< (@ 0x00000018) Offset:0x18 EBI Address Timing Register 2 */ + + struct { + __IOM uint32_t ADDRSETUP : 4; /*!< [3..0] Address Setup time */ + uint32_t : 4; + __IOM uint32_t ADDRHOLD : 4; /*!< [11..8] Address Hold time */ + uint32_t : 20; + } TADDR2_b; + } ; + + union { + __IOM uint32_t TADDR3; /*!< (@ 0x0000001C) Offset:0x1C EBI Address Timing Register 3 */ + + struct { + __IOM uint32_t ADDRSETUP : 4; /*!< [3..0] Address Setup time */ + uint32_t : 4; + __IOM uint32_t ADDRHOLD : 4; /*!< [11..8] Address Hold time */ + uint32_t : 20; + } TADDR3_b; + } ; + + union { + __IOM uint32_t TREAD0; /*!< (@ 0x00000020) Offset:0x20 EBI Read Timing Register 0 */ + + struct { + __IOM uint32_t RDSETUP : 4; /*!< [3..0] Read Setup time */ + uint32_t : 4; + __IOM uint32_t RDSTRB : 6; /*!< [13..8] Read Strobe time */ + uint32_t : 2; + __IOM uint32_t RDHOLD : 4; /*!< [19..16] Read Hold time */ + uint32_t : 12; + } TREAD0_b; + } ; + + union { + __IOM uint32_t TREAD1; /*!< (@ 0x00000024) Offset:0x24 EBI Read Timing Register 1 */ + + struct { + __IOM uint32_t RDSETUP : 4; /*!< [3..0] Read Setup time */ + uint32_t : 4; + __IOM uint32_t RDSTRB : 6; /*!< [13..8] Read Strobe time */ + uint32_t : 2; + __IOM uint32_t RDHOLD : 4; /*!< [19..16] Read Hold time */ + uint32_t : 12; + } TREAD1_b; + } ; + + union { + __IOM uint32_t TREAD2; /*!< (@ 0x00000028) Offset:0x28 EBI Read Timing Register 2 */ + + struct { + __IOM uint32_t RDSETUP : 4; /*!< [3..0] Read Setup time */ + uint32_t : 4; + __IOM uint32_t RDSTRB : 6; /*!< [13..8] Read Strobe time */ + uint32_t : 2; + __IOM uint32_t RDHOLD : 4; /*!< [19..16] Read Hold time */ + uint32_t : 12; + } TREAD2_b; + } ; + + union { + __IOM uint32_t TREAD3; /*!< (@ 0x0000002C) Offset:0x2C EBI Read Timing Register 3 */ + + struct { + __IOM uint32_t RDSETUP : 4; /*!< [3..0] Read Setup time */ + uint32_t : 4; + __IOM uint32_t RDSTRB : 6; /*!< [13..8] Read Strobe time */ + uint32_t : 2; + __IOM uint32_t RDHOLD : 4; /*!< [19..16] Read Hold time */ + uint32_t : 12; + } TREAD3_b; + } ; + + union { + __IOM uint32_t TWRITE0; /*!< (@ 0x00000030) Offset:0x30 EBI Write Timing Register 0 */ + + struct { + __IOM uint32_t WESETUP : 4; /*!< [3..0] Write Setup time */ + uint32_t : 4; + __IOM uint32_t WESTRB : 6; /*!< [13..8] Write Strobe time */ + uint32_t : 2; + __IOM uint32_t WEHOLD : 4; /*!< [19..16] Write Hold time */ + uint32_t : 12; + } TWRITE0_b; + } ; + + union { + __IOM uint32_t TWRITE1; /*!< (@ 0x00000034) Offset:0x34 EBI Write Timing Register 1 */ + + struct { + __IOM uint32_t WESETUP : 4; /*!< [3..0] Write Setup time */ + uint32_t : 4; + __IOM uint32_t WESTRB : 6; /*!< [13..8] Write Strobe time */ + uint32_t : 2; + __IOM uint32_t WEHOLD : 4; /*!< [19..16] Write Hold time */ + uint32_t : 12; + } TWRITE1_b; + } ; + + union { + __IOM uint32_t TWRITE2; /*!< (@ 0x00000038) Offset:0x38 EBI Write Timing Register 2 */ + + struct { + __IOM uint32_t WESETUP : 4; /*!< [3..0] Write Setup time */ + uint32_t : 4; + __IOM uint32_t WESTRB : 6; /*!< [13..8] Write Strobe time */ + uint32_t : 2; + __IOM uint32_t WEHOLD : 4; /*!< [19..16] Write Hold time */ + uint32_t : 12; + } TWRITE2_b; + } ; + + union { + __IOM uint32_t TWRITE3; /*!< (@ 0x0000003C) Offset:0x3C EBI Write Timing Register 3 */ + + struct { + __IOM uint32_t WESETUP : 4; /*!< [3..0] Write Setup time */ + uint32_t : 4; + __IOM uint32_t WESTRB : 6; /*!< [13..8] Write Strobe time */ + uint32_t : 2; + __IOM uint32_t WEHOLD : 4; /*!< [19..16] Write Hold time */ + uint32_t : 12; + } TWRITE3_b; + } ; + + union { + __IOM uint32_t PR0; /*!< (@ 0x00000040) Offset:0x40 EBI Polarity Register 0 */ + + struct { + __IM uint32_t CSPOL : 1; /*!< [0..0] Chip Select polarity */ + __IM uint32_t OEPOL : 1; /*!< [1..1] Output Enable polarity */ + __IM uint32_t WEPOL : 1; /*!< [2..2] Write Enable polarity */ + __IM uint32_t ALEPOL : 1; /*!< [3..3] Address Latch polarity */ + __IOM uint32_t ARDYPOL : 1; /*!< [4..4] Asynchronous Ready polarity */ + __IM uint32_t UBLBPOL : 1; /*!< [5..5] Upper Byte and Lower Byte polarity */ + uint32_t : 26; + } PR0_b; + } ; + + union { + __IOM uint32_t PR1; /*!< (@ 0x00000044) Offset:0x44 EBI Polarity Register 1 */ + + struct { + __IM uint32_t CSPOL : 1; /*!< [0..0] Chip Select polarity */ + __IM uint32_t OEPOL : 1; /*!< [1..1] Output Enable polarity */ + __IM uint32_t WEPOL : 1; /*!< [2..2] Write Enable polarity */ + __IM uint32_t ALEPOL : 1; /*!< [3..3] Address Latch polarity */ + __IOM uint32_t ARDYPOL : 1; /*!< [4..4] Asynchronous Ready polarity */ + __IM uint32_t UBLBPOL : 1; /*!< [5..5] Upper Byte and Lower Byte polarity */ + uint32_t : 26; + } PR1_b; + } ; + + union { + __IOM uint32_t PR2; /*!< (@ 0x00000048) Offset:0x48 EBI Polarity Register 2 */ + + struct { + __IM uint32_t CSPOL : 1; /*!< [0..0] Chip Select polarity */ + __IM uint32_t OEPOL : 1; /*!< [1..1] Output Enable polarity */ + __IM uint32_t WEPOL : 1; /*!< [2..2] Write Enable polarity */ + __IM uint32_t ALEPOL : 1; /*!< [3..3] Address Latch polarity */ + __IOM uint32_t ARDYPOL : 1; /*!< [4..4] Asynchronous Ready polarity */ + __IM uint32_t UBLBPOL : 1; /*!< [5..5] Upper Byte and Lower Byte polarity */ + uint32_t : 26; + } PR2_b; + } ; + + union { + __IOM uint32_t PR3; /*!< (@ 0x0000004C) Offset:0x4C EBI Polarity Register 3 */ + + struct { + __IM uint32_t CSPOL : 1; /*!< [0..0] Chip Select polarity */ + __IM uint32_t OEPOL : 1; /*!< [1..1] Output Enable polarity */ + __IM uint32_t WEPOL : 1; /*!< [2..2] Write Enable polarity */ + __IM uint32_t ALEPOL : 1; /*!< [3..3] Address Latch polarity */ + __IOM uint32_t ARDYPOL : 1; /*!< [4..4] Asynchronous Ready polarity */ + __IM uint32_t UBLBPOL : 1; /*!< [5..5] Upper Byte and Lower Byte polarity */ + uint32_t : 26; + } PR3_b; + } ; + + union { + __IOM uint32_t IE; /*!< (@ 0x00000050) Offset:0x50 EBI Interrupt Enable Register */ + + struct { + __IOM uint32_t ARDYTOEN : 1; /*!< [0..0] EBI asynchronous ready time-out interrupt enable bit */ + __IOM uint32_t ACCDISEN : 1; /*!< [1..1] Interrupt for accessing the disabled bank enable bit */ + __IOM uint32_t SMRSTEN : 1; /*!< [2..2] Interrupt for issuing a transaction during EBI state + machine reset period enable bit */ + __IOM uint32_t RWERREN : 1; /*!< [3..3] Interrupt for read/writer error enable bit */ + __IOM uint32_t DMAHTIE : 1; /*!< [4..4] DMA half-transfer interrupt enable bit */ + __IOM uint32_t DMATCIE : 1; /*!< [5..5] DMA transfer complete interrupt enable bit */ + uint32_t : 26; + } IE_b; + } ; + + union { + __IM uint32_t RIS; /*!< (@ 0x00000054) Offset:0x54 EBI Interrupt Flag Register */ + + struct { + __IM uint32_t ARDYTOIF : 1; /*!< [0..0] EBI asynchronous ready time-out flag */ + __IM uint32_t ACCDISIF : 1; /*!< [1..1] EBI accessing the disabled bank flag */ + __IM uint32_t SMRSTIF : 1; /*!< [2..2] EBI state machine reset flag */ + __IM uint32_t RWERRIF : 1; /*!< [3..3] EBI read/write error flag */ + __IM uint32_t DMAHTIF : 1; /*!< [4..4] DMA half-transfer flag */ + __IM uint32_t DMATCIF : 1; /*!< [5..5] DMA transfer complete flag */ + uint32_t : 26; + } RIS_b; + } ; + + union { + __OM uint32_t IC; /*!< (@ 0x00000058) Offset:0x58 EBI Interrupt Clear Register */ + + struct { + __OM uint32_t ARDYTOIC : 1; /*!< [0..0] Select ARDYTOIF flag to be cleared */ + __OM uint32_t ACCDISIC : 1; /*!< [1..1] Select ACCDISIF flag to be cleared */ + __OM uint32_t SMRSTIC : 1; /*!< [2..2] Select SMRSTIF flag to be cleared */ + __OM uint32_t RWERRIC : 1; /*!< [3..3] Select RWERRIF flag to be cleared */ + __OM uint32_t DMAHTIC : 1; /*!< [4..4] Select DMA half-transfer flag to be cleared */ + __OM uint32_t DMATCIC : 1; /*!< [5..5] Select DMA transfer complete flag to be cleared */ + uint32_t : 26; + } IC_b; + } ; + + union { + __IOM uint32_t DMACTRL; /*!< (@ 0x0000005C) Offset:0x5C EBI DMA Control Register */ + + struct { + __IOM uint32_t DMAEN : 1; /*!< [0..0] EBI DMA enable bit */ + __IOM uint32_t SPISELECT : 1; /*!< [1..1] SPIn select bit */ + __IOM uint32_t BANKSELECT : 2; /*!< [3..2] EBI Bank n select bits */ + uint32_t : 28; + } DMACTRL_b; + } ; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t DMACNT; /*!< (@ 0x00000064) Offset:0x64 DMA Number of data transfer register */ + + struct { + __IOM uint32_t CNT : 28; /*!< [27..0] Number of data to DMA RX count transfer */ + uint32_t : 4; + } DMACNT_b; + } ; + + union { + __IOM uint32_t DMAHTCNT; /*!< (@ 0x00000068) Offset:0x68 EBI DMA Half-transfer Register */ + + struct { + __IOM uint32_t HTCNT : 28; /*!< [27..0] Number of data to DMA RX half count transfer */ + uint32_t : 4; + } DMAHTCNT_b; + } ; + + union { + __IM uint32_t CURCNT; /*!< (@ 0x0000006C) Offset:0x6C EBI DMA Current Transfer Data Counter + Register */ + + struct { + __IM uint32_t CURCNT : 28; /*!< [27..0] Number of data to DMA RX half count transfer */ + uint32_t : 4; + } CURCNT_b; + } ; +} SN_EBI_Type; /*!< Size = 112 (0x70) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_USB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal Serial Bus Full Speed Device Interface (USB) (SN_USB) + */ + +typedef struct { /*!< (@ 0x4005C000) SN_USB Structure */ + + union { + __IOM uint32_t INTEN; /*!< (@ 0x00000000) Offset:0x00 USB Interrupt Enable Register */ + + struct { + __IOM uint32_t EP1_NAK_EN : 1; /*!< [0..0] EP1 NAK Interrupt Enable */ + __IOM uint32_t EP2_NAK_EN : 1; /*!< [1..1] EP2 NAK Interrupt Enable */ + __IOM uint32_t EP3_NAK_EN : 1; /*!< [2..2] EP3 NAK Interrupt Enable */ + __IOM uint32_t EP4_NAK_EN : 1; /*!< [3..3] EP4 NAK Interrupt Enable */ + __IOM uint32_t EP5_NAK_EN : 1; /*!< [4..4] EP5 NAK Interrupt Enable */ + __IOM uint32_t EP6_NAK_EN : 1; /*!< [5..5] EP6 NAK Interrupt Enable */ + __IOM uint32_t EPN_ACK_EN : 1; /*!< [6..6] EPN ACK Interrupt Enable */ + uint32_t : 21; + __IOM uint32_t BUSWK_IE : 1; /*!< [28..28] USB Bus Wake Up Interrupt Enable */ + __IOM uint32_t USB_IE : 1; /*!< [29..29] USB Event Interrupt Enable */ + __IOM uint32_t USB_SOF_IE : 1; /*!< [30..30] USB SOF Interrupt Enable */ + __IOM uint32_t BUS_IE : 1; /*!< [31..31] Bus Event Interrupt Enable */ + } INTEN_b; + } ; + + union { + __IM uint32_t INSTS; /*!< (@ 0x00000004) Offset:0x04 USB Interrupt Event Status Register */ + + struct { + __IM uint32_t EP1_NAK : 1; /*!< [0..0] Endpoint 1 NAK transaction flag */ + __IM uint32_t EP2_NAK : 1; /*!< [1..1] Endpoint 2 NAK transaction flag */ + __IM uint32_t EP3_NAK : 1; /*!< [2..2] Endpoint 3 NAK transaction flag */ + __IM uint32_t EP4_NAK : 1; /*!< [3..3] Endpoint 4 NAK transaction flag */ + __IM uint32_t EP5_NAK : 1; /*!< [4..4] Endpoint 5 NAK transaction flag */ + __IM uint32_t EP6_NAK : 1; /*!< [5..5] Endpoint 6 NAK transaction flag */ + uint32_t : 2; + __IM uint32_t EP1_ACK : 1; /*!< [8..8] Endpoint 1 ACK transaction flag */ + __IM uint32_t EP2_ACK : 1; /*!< [9..9] Endpoint 2 ACK transaction flag */ + __IM uint32_t EP3_ACK : 1; /*!< [10..10] Endpoint 3 ACK transaction flag */ + __IM uint32_t EP4_ACK : 1; /*!< [11..11] Endpoint 4 ACK transaction flag */ + __IM uint32_t EP5_ACK : 1; /*!< [12..12] Endpoint 5 ACK transaction flag */ + __IM uint32_t EP6_ACK : 1; /*!< [13..13] Endpoint 6 ACK transaction flag */ + uint32_t : 3; + __IM uint32_t ERR_TIMEOUT : 1; /*!< [17..17] Timeout Status */ + __IM uint32_t ERR_SETUP : 1; /*!< [18..18] Wrong Setup data received */ + __IM uint32_t EP0_OUT_STALL : 1; /*!< [19..19] EP0 OUT STALL transaction */ + __IM uint32_t EP0_IN_STALL : 1; /*!< [20..20] EP0 IN STALL Transaction is completed */ + __IM uint32_t EP0_OUT : 1; /*!< [21..21] EP0 OUT ACK Transaction Flag */ + __IM uint32_t EP0_IN : 1; /*!< [22..22] EP0 IN ACK Transaction Flag */ + __IM uint32_t EP0_SETUP : 1; /*!< [23..23] EP0 Setup Transaction Flag */ + __IM uint32_t EP0_PRESETUP : 1; /*!< [24..24] EP0 Setup Token Packet Flag */ + __IM uint32_t BUS_WAKEUP : 1; /*!< [25..25] Bus Wakeup Flag */ + __IM uint32_t USB_SOF : 1; /*!< [26..26] USB SOF packet received flag */ + uint32_t : 2; + __IM uint32_t BUS_RESUME : 1; /*!< [29..29] USB Bus Resume signal flag */ + __IM uint32_t BUS_SUSPEND : 1; /*!< [30..30] USB Bus Suspend signal flag */ + __IM uint32_t BUS_RESET : 1; /*!< [31..31] USB Bus Reset signal flag */ + } INSTS_b; + } ; + + union { + __OM uint32_t INSTSC; /*!< (@ 0x00000008) Offset:0x08 USB Interrupt Event Status Clear + Register */ + + struct { + __OM uint32_t EP1_NAKC : 1; /*!< [0..0] EP1 NAK clear bit */ + __OM uint32_t EP2_NAKC : 1; /*!< [1..1] EP2 NAK clear bit */ + __OM uint32_t EP3_NAKC : 1; /*!< [2..2] EP3 NAK clear bit */ + __OM uint32_t EP4_NAKC : 1; /*!< [3..3] EP4 NAK clear bit */ + __OM uint32_t EP5_NAKC : 1; /*!< [4..4] EP5 NAK clear bit */ + __OM uint32_t EP6_NAKC : 1; /*!< [5..5] EP6 NAK clear bit */ + uint32_t : 2; + __OM uint32_t EP1_ACKC : 1; /*!< [8..8] EP1 ACK clear bit */ + __OM uint32_t EP2_ACKC : 1; /*!< [9..9] EP2 ACK clear bit */ + __OM uint32_t EP3_ACKC : 1; /*!< [10..10] EP3 ACK clear bit */ + __OM uint32_t EP4_ACKC : 1; /*!< [11..11] EP4 ACK clear bit */ + __OM uint32_t EP5_ACKC : 1; /*!< [12..12] EP5 ACK clear bit */ + __OM uint32_t EP6_ACKC : 1; /*!< [13..13] EP6 ACK clear bit */ + uint32_t : 3; + __OM uint32_t ERR_TIMEOUTC : 1; /*!< [17..17] Timeout Error clear bit */ + __OM uint32_t ERR_SETUPC : 1; /*!< [18..18] Error Setup clear bit */ + __OM uint32_t EP0_OUT_STALLC : 1; /*!< [19..19] EP0 OUT STALL clear bit */ + __OM uint32_t EP0_IN_STALLC : 1; /*!< [20..20] EP0 IN STALL clear bit */ + __OM uint32_t EP0_OUTC : 1; /*!< [21..21] EP0 OUT clear bit */ + __OM uint32_t EP0_INC : 1; /*!< [22..22] EP0 IN clear bit */ + __OM uint32_t EP0_SETUPC : 1; /*!< [23..23] EP0 SETUP clear bit */ + __OM uint32_t EP0_PRESETUPC : 1; /*!< [24..24] EP0 PRESETUP clear bit */ + __OM uint32_t BUS_WAKEUPC : 1; /*!< [25..25] Bus Wakeup clear bit */ + __OM uint32_t USB_SOFC : 1; /*!< [26..26] USB SOF clear bit */ + uint32_t : 2; + __OM uint32_t BUS_RESUMEC : 1; /*!< [29..29] USB Bus Resume clear bit */ + uint32_t : 1; + __OM uint32_t BUS_RESETC : 1; /*!< [31..31] USB Bus Reset clear bit */ + } INSTSC_b; + } ; + + union { + __IOM uint32_t ADDR; /*!< (@ 0x0000000C) Offset:0x0C USB Device Address Register */ + + struct { + __IOM uint32_t UADDR : 7; /*!< [6..0] USB device's address */ + uint32_t : 25; + } ADDR_b; + } ; + + union { + __IOM uint32_t CFG; /*!< (@ 0x00000010) Offset:0x10 USB Configuration Register */ + + struct { + __IOM uint32_t EP1_DIR : 1; /*!< [0..0] Endpoint 1 IN/OUT direction setting */ + __IOM uint32_t EP2_DIR : 1; /*!< [1..1] Endpoint 2 IN/OUT direction setting */ + __IOM uint32_t EP3_DIR : 1; /*!< [2..2] Endpoint 3 IN/OUT direction setting */ + __IOM uint32_t EP4_DIR : 1; /*!< [3..3] Endpoint 4 IN/OUT direction setting */ + __IOM uint32_t EP5_DIR : 1; /*!< [4..4] Endpoint 5 IN/OUT direction setting */ + __IOM uint32_t EP6_DIR : 1; /*!< [5..5] Endpoint 6 IN/OUT direction setting */ + uint32_t : 20; + __IOM uint32_t DIS_PDEN : 1; /*!< [26..26] Enable internal D+ and D- 175k pull-down resistor */ + __IOM uint32_t ESD_EN : 1; /*!< [27..27] Enable USB anti-ESD protection */ + __IOM uint32_t SIE_EN : 1; /*!< [28..28] USB Serial Interface Engine Enable */ + __IOM uint32_t DPPU_EN : 1; /*!< [29..29] Enable internal D+ 1.5k pull-up resistor */ + __IOM uint32_t PHY_EN : 1; /*!< [30..30] PHY Transceiver Function Enable */ + __IOM uint32_t VREG33_EN : 1; /*!< [31..31] Enable the internal VREG33 ouput */ + } CFG_b; + } ; + + union { + __IOM uint32_t SGCTL; /*!< (@ 0x00000014) Offset:0x14 USB Signal Control Register */ + + struct { + __IOM uint32_t BUS_DN : 1; /*!< [0..0] USB D- state */ + __IOM uint32_t BUS_DP : 1; /*!< [1..1] USB DP state */ + __IOM uint32_t BUS_DRVEN : 1; /*!< [2..2] Enable to drive USB bus */ + uint32_t : 29; + } SGCTL_b; + } ; + + union { + __IOM uint32_t EP0CTL; /*!< (@ 0x00000018) Offset:0x18 USB Endpoint 0 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 20; + __IOM uint32_t OUT_STALL_EN : 1; /*!< [27..27] Enable EP0 OUT STALL handshake */ + __IOM uint32_t IN_STALL_EN : 1; /*!< [28..28] Enable EP0 IN STALL handshake */ + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Enable Endpoint 0 Function */ + } EP0CTL_b; + } ; + + union { + __IOM uint32_t EP1CTL; /*!< (@ 0x0000001C) Offset:0x1C USB Endpoint 1 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 1 Function enable bit */ + } EP1CTL_b; + } ; + + union { + __IOM uint32_t EP2CTL; /*!< (@ 0x00000020) Offset:0x20 USB Endpoint 2 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 2 Function enable bit */ + } EP2CTL_b; + } ; + + union { + __IOM uint32_t EP3CTL; /*!< (@ 0x00000024) Offset:0x24 USB Endpoint 3 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 3 Function enable bit */ + } EP3CTL_b; + } ; + + union { + __IOM uint32_t EP4CTL; /*!< (@ 0x00000028) Offset:0x28 USB Endpoint 4 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 4 Function enable bit */ + } EP4CTL_b; + } ; + + union { + __IOM uint32_t EP5CTL; /*!< (@ 0x0000002C) Offset:0x2C USB Endpoint 5 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 5 Function enable bit */ + } EP5CTL_b; + } ; + + union { + __IOM uint32_t EP6CTL; /*!< (@ 0x00000030) Offset:0x30 USB Endpoint 6 Control Register */ + + struct { + __IOM uint32_t ENDP_CNT : 7; /*!< [6..0] Endpoint byte count */ + uint32_t : 22; + __IOM uint32_t ENDP_STATE : 2; /*!< [30..29] Endpoint Handshake State */ + __IOM uint32_t ENDP_EN : 1; /*!< [31..31] Endpoint 6 Function enable bit */ + } EP6CTL_b; + } ; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t EPTOGGLE; /*!< (@ 0x0000003C) Offset:0x3C USB Endpoint Data Toggle Register */ + + struct { + __IOM uint32_t ENDP1_DATA01 : 1; /*!< [0..0] Endpoint 1 data toggle bit */ + __IOM uint32_t ENDP2_DATA01 : 1; /*!< [1..1] Endpoint 2 data toggle bit */ + __IOM uint32_t ENDP3_DATA01 : 1; /*!< [2..2] Endpoint 3 data toggle bit */ + __IOM uint32_t ENDP4_DATA01 : 1; /*!< [3..3] Endpoint 4 data toggle bit */ + __IOM uint32_t ENDP5_DATA01 : 1; /*!< [4..4] Endpoint 5 data toggle bit */ + __IOM uint32_t ENDP6_DATA01 : 1; /*!< [5..5] Endpoint 6 data toggle bit */ + uint32_t : 26; + } EPTOGGLE_b; + } ; + __IM uint32_t RESERVED1[2]; + + union { + __IOM uint32_t EP1BUFOS; /*!< (@ 0x00000048) Offset:0x48 USB Endpoint 1 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP1BUFOS_b; + } ; + + union { + __IOM uint32_t EP2BUFOS; /*!< (@ 0x0000004C) Offset:0x4C USB Endpoint 2 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP2BUFOS_b; + } ; + + union { + __IOM uint32_t EP3BUFOS; /*!< (@ 0x00000050) Offset:0x50 USB Endpoint 3 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP3BUFOS_b; + } ; + + union { + __IOM uint32_t EP4BUFOS; /*!< (@ 0x00000054) Offset:0x54 USB Endpoint 4 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP4BUFOS_b; + } ; + + union { + __IOM uint32_t EP5BUFOS; /*!< (@ 0x00000058) Offset:0x58 USB Endpoint 5 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP5BUFOS_b; + } ; + + union { + __IOM uint32_t EP6BUFOS; /*!< (@ 0x0000005C) Offset:0x5C USB Endpoint 6 Buffer Offset Register */ + + struct { + uint32_t : 2; + __IOM uint32_t OFFSET : 7; /*!< [8..2] The offset address for endpoint data buffer */ + uint32_t : 23; + } EP6BUFOS_b; + } ; + + union { + __IM uint32_t FRMNO; /*!< (@ 0x00000060) Offset:0x60 USB Frame Number Register */ + + struct { + __IM uint32_t FRAME_NO : 11; /*!< [10..0] The 11-bit frame number of the SOF packet */ + uint32_t : 21; + } FRMNO_b; + } ; + + union { + __IOM uint32_t PHYPRM; /*!< (@ 0x00000064) Offset:0x64 USB PHY Parameter Register */ + + struct { + __IOM uint32_t PHY_PARAM : 6; /*!< [5..0] USB PHY parameter */ + uint32_t : 26; + } PHYPRM_b; + } ; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t PHYPRM2; /*!< (@ 0x0000006C) Offset:0x6C USB PHY Parameter Register 2 */ + + struct { + __IOM uint32_t PHY_PS : 15; /*!< [14..0] USB PHY parameter 2 */ + uint32_t : 17; + } PHYPRM2_b; + } ; + + union { + __IOM uint32_t PS2CTL; /*!< (@ 0x00000070) Offset:0x70 PS/2 Control Register */ + + struct { + __IOM uint32_t SCKM : 1; /*!< [0..0] PS/2 SCK mode control bit */ + __IOM uint32_t SDAM : 1; /*!< [1..1] PS/2 SDA mode control bit */ + __IOM uint32_t SCK : 1; /*!< [2..2] PS/2 SCK data buffer */ + __IOM uint32_t SDA : 1; /*!< [3..3] PS/2 SDA data buffer */ + uint32_t : 27; + __IOM uint32_t PS2ENB : 1; /*!< [31..31] PS/2 internal 5k ohm pull-up resistor control bit */ + } PS2CTL_b; + } ; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t RWADDR; /*!< (@ 0x00000078) Offset:0x78 USB Read/Write Address Register */ + + struct { + uint32_t : 2; + __IOM uint32_t RWADDR : 6; /*!< [7..2] USB FIFO address to be read or written from/to USB FIFO */ + uint32_t : 24; + } RWADDR_b; + } ; + + union { + __IOM uint32_t RWDATA; /*!< (@ 0x0000007C) Offset:0x7C USB Read/Write Data Register */ + + struct { + __IOM uint32_t RWDATA : 32; /*!< [31..0] Data to be read or written from/to USB FIFO */ + } RWDATA_b; + } ; + + union { + __IOM uint32_t RWSTATUS; /*!< (@ 0x00000080) Offset:0x80 USB Read/Write Status Register */ + + struct { + __IOM uint32_t W_STATUS : 1; /*!< [0..0] Write status of USB FIFO */ + __IOM uint32_t R_STATUS : 1; /*!< [1..1] WRead status of USB FIFO */ + uint32_t : 30; + } RWSTATUS_b; + } ; + + union { + __IOM uint32_t RWADDR2; /*!< (@ 0x00000084) Offset:0x84 USB Read/Write Address Register 2 */ + + struct { + uint32_t : 2; + __IOM uint32_t RWADDR : 6; /*!< [7..2] USB FIFO address to be read or written from/to USB FIFO */ + uint32_t : 24; + } RWADDR2_b; + } ; + + union { + __IOM uint32_t RWDATA2; /*!< (@ 0x00000088) Offset:0x88 USB Read/Write Data Register 2 */ + + struct { + __IOM uint32_t RWDATA : 32; /*!< [31..0] Data to be read or written from/to USB FIFO */ + } RWDATA2_b; + } ; + + union { + __IOM uint32_t RWSTATUS2; /*!< (@ 0x0000008C) Offset:0x8C USB Read/Write Status Register 2 */ + + struct { + __IOM uint32_t W_STATUS : 1; /*!< [0..0] Write status of USB FIFO */ + __IOM uint32_t R_STATUS : 1; /*!< [1..1] WRead status of USB FIFO */ + uint32_t : 30; + } RWSTATUS2_b; + } ; +} SN_USB_Type; /*!< Size = 144 (0x90) */ + + + +/* =========================================================================================================================== */ +/* ================ SN_UC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UC Registers (SN_UC) + */ + +typedef struct { /*!< (@ 0x1FFF2450) SN_UC Structure */ + __IM uint32_t L4BYTE; /*!< (@ 0x00000000) Offset:0x00 UC Low 4 Byte Register */ + __IM uint32_t RESERVED; + __IM uint32_t H4BYTE; /*!< (@ 0x00000008) Offset:0x08 UC High 4 Byte Register */ +} SN_UC_Type; /*!< Size = 12 (0xc) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define SN_SYS0_BASE 0x40060000UL +#define SN_SYS1_BASE 0x4005E000UL +#define SN_PMU_BASE 0x40032000UL +#define SN_PFPA_BASE 0x40042000UL +#define SN_GPIO1_BASE 0x40046000UL +#define SN_GPIO2_BASE 0x40048000UL +#define SN_GPIO3_BASE 0x4004A000UL +#define SN_GPIO0_BASE 0x40044000UL +#define SN_ADC_BASE 0x40026000UL +#define SN_CMP_BASE 0x40028000UL +#define SN_CT16B0_BASE 0x40000000UL +#define SN_CT16B1_BASE 0x40002000UL +#define SN_CT16B2_BASE 0x40004000UL +#define SN_CT16B3_BASE 0x40006000UL +#define SN_CT16B4_BASE 0x40008000UL +#define SN_CT16B5_BASE 0x4000A000UL +#define SN_WDT_BASE 0x40010000UL +#define SN_RTC_BASE 0x40012000UL +#define SN_SPI0_BASE 0x4001C000UL +#define SN_SPI1_BASE 0x40058000UL +#define SN_I2C0_BASE 0x40018000UL +#define SN_I2C1_BASE 0x4005A000UL +#define SN_UART0_BASE 0x40016000UL +#define SN_UART1_BASE 0x40056000UL +#define SN_UART2_BASE 0x40054000UL +#define SN_UART3_BASE 0x40052000UL +#define SN_I2S0_BASE 0x4001A000UL +#define SN_I2S1_BASE 0x40014000UL +#define SN_FLASH_BASE 0x40062000UL +#define SN_LCD_BASE 0x40034000UL +#define SN_CRC_BASE 0x40038000UL +#define SN_OPA_BASE 0x4002A000UL +#define SN_EBI_BASE 0x40036000UL +#define SN_USB_BASE 0x4005C000UL +#define SN_UC_BASE 0x1FFF2450UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define SN_SYS0 ((SN_SYS0_Type*) SN_SYS0_BASE) +#define SN_SYS1 ((SN_SYS1_Type*) SN_SYS1_BASE) +#define SN_PMU ((SN_PMU_Type*) SN_PMU_BASE) +#define SN_PFPA ((SN_PFPA_Type*) SN_PFPA_BASE) +#define SN_GPIO1 ((SN_GPIO1_Type*) SN_GPIO1_BASE) +#define SN_GPIO2 ((SN_GPIO2_Type*) SN_GPIO2_BASE) +#define SN_GPIO3 ((SN_GPIO1_Type*) SN_GPIO3_BASE) +#define SN_GPIO0 ((SN_GPIO1_Type*) SN_GPIO0_BASE) +#define SN_ADC ((SN_ADC_Type*) SN_ADC_BASE) +#define SN_CMP ((SN_CMP_Type*) SN_CMP_BASE) +#define SN_CT16B0 ((SN_CT16B0_Type*) SN_CT16B0_BASE) +#define SN_CT16B1 ((SN_CT16B1_Type*) SN_CT16B1_BASE) +#define SN_CT16B2 ((SN_CT16B2_Type*) SN_CT16B2_BASE) +#define SN_CT16B3 ((SN_CT16B3_Type*) SN_CT16B3_BASE) +#define SN_CT16B4 ((SN_CT16B3_Type*) SN_CT16B4_BASE) +#define SN_CT16B5 ((SN_CT16B5_Type*) SN_CT16B5_BASE) +#define SN_WDT ((SN_WDT_Type*) SN_WDT_BASE) +#define SN_RTC ((SN_RTC_Type*) SN_RTC_BASE) +#define SN_SPI0 ((SN_SPI0_Type*) SN_SPI0_BASE) +#define SN_SPI1 ((SN_SPI1_Type*) SN_SPI1_BASE) +#define SN_I2C0 ((SN_I2C0_Type*) SN_I2C0_BASE) +#define SN_I2C1 ((SN_I2C0_Type*) SN_I2C1_BASE) +#define SN_UART0 ((SN_UART0_Type*) SN_UART0_BASE) +#define SN_UART1 ((SN_UART0_Type*) SN_UART1_BASE) +#define SN_UART2 ((SN_UART0_Type*) SN_UART2_BASE) +#define SN_UART3 ((SN_UART0_Type*) SN_UART3_BASE) +#define SN_I2S0 ((SN_I2S0_Type*) SN_I2S0_BASE) +#define SN_I2S1 ((SN_I2S0_Type*) SN_I2S1_BASE) +#define SN_FLASH ((SN_FLASH_Type*) SN_FLASH_BASE) +#define SN_LCD ((SN_LCD_Type*) SN_LCD_BASE) +#define SN_CRC ((SN_CRC_Type*) SN_CRC_BASE) +#define SN_OPA ((SN_OPA_Type*) SN_OPA_BASE) +#define SN_EBI ((SN_EBI_Type*) SN_EBI_BASE) +#define SN_USB ((SN_USB_Type*) SN_USB_BASE) +#define SN_UC ((SN_UC_Type*) SN_UC_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* SN32F290_H */ + + +/** @} */ /* End of group SN32F290 */ + +/** @} */ /* End of group SONiX Technology Co., Ltd. */ diff --git a/os/common/ext/SONiX/SN32F2xx/SN32F2xx.h b/os/common/ext/SONiX/SN32F2xx/SN32F2xx.h new file mode 100644 index 00000000..402a2eca --- /dev/null +++ b/os/common/ext/SONiX/SN32F2xx/SN32F2xx.h @@ -0,0 +1,57 @@ +#ifndef __SN32F2xx_H +#define __SN32F2xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief SN32 Family + */ +#if !defined (SN32F2) +#define SN32F2 +#endif /* SN32F2 */ + +/* Uncomment the line below according to the target SN32 device used in your + application + */ + +#if !defined (SN32F240) && !defined (SN32F240B) && !defined (SN32F260) \ + && !defined (SN32F280) && !defined (SN32F290) + /* #define SN32F230 */ /*!< SN32F239, SN32F238, SN32F237, SN32F236,and SN32F235 Devices */ + /* #define SN32F240 */ /*!< SN32F249, SN32F248, SN32F247, SN32F246 and SN32F245 Devices */ + /* #define SN32F240B */ /*!< SN32F248B, SN32F247B, SN32F246B and SN32F2451B Devices */ + /* #define SN32F260 */ /*!< SN32F268, SN32F267, SN32F265, SN32F2641, + SN32F264 and SN32F263 Devices */ + /* #define SN32F280 */ /*!< SN32F289, SN32F288 and SN32F287 Devices */ + /* #define SN32F290 */ /*!< SN32F299. SN32F298 and SN32F297 Devices */ +#include "board.h" +#endif + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(SN32F240) + #include "SN32F240.h" +#elif defined(SN32F240B) + #include "SN32F240B.h" +#elif defined(SN32F260) + #include "SN32F260.h" +#elif defined(SN32F280) + #include "SN32F280.h" +#elif defined(SN32F290) + #include "SN32F290.h" +#else + #error "Please select first the target SN32F2xx device used in your application (in SN32F2xx.h file)" +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /*__SN32F2xx_H*/ diff --git a/os/common/ext/SONiX/SN32F2xx/system_SN32F240.c b/os/common/ext/SONiX/SN32F2xx/system_SN32F240.c new file mode 100644 index 00000000..e2bc8a1d --- /dev/null +++ b/os/common/ext/SONiX/SN32F2xx/system_SN32F240.c @@ -0,0 +1,300 @@ +/****************************************************************************** + * @file system_SN32F240.c + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File + * for the SONIX SN32F240 Devices + * @version V1.1.1 + * @date 2015/08/21 + * + * @note + * Copyright (C) 2009-2013 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#include +#include +#include + + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// System Clock Configuration +// SYSCLKSEL (SYS0_CLKCFG) +// <0=> IHRC +// <1=> ILRC +// <2=> EHS X'TAL +// <3=> ELS X'TAL +// <4=> PLL +// +// EHS Source Frequency (MHz) +// <10-25> +// +// PLL Control Register (SYS0_PLLCTRL) +// F_CLKOUT = F_VCO / P = (F_CLKIN / F * M) / P +// 10 MHz <= F_CLKIN <= 25 MHz +// 156 MHz <= (F_CLKIN / F * M) <= 320 MHz +// MSEL +// <3-31> +// PSEL +// <3=> P = 6 +// <4=> P = 8 +// <5=> P = 10 +// <6=> P = 12 +// <7=> P = 14 +// FSEL +// <0=> F = 1 +// <1=> F = 2 +// PLL CLKIN Source selection +// <0=> IHRC +// <1=> EHS X'TAL +// PLL Enable selection +// <0=> Disable +// <1=> Enable +// +// +// AHB Clock Prescaler Register (SYS0_AHBCP) +// <0=> SYSCLK/1 +// <1=> SYSCLK/2 +// <2=> SYSCLK/4 +// <3=> SYSCLK/8 +// <4=> SYSCLK/16 +// <5=> SYSCLK/32 +// <6=> SYSCLK/64 +// <7=> SYSCLK/128 +// <8=> SYSCLK/256 +// <9=> SYSCLK/512 +// +// CLKOUT selection +// <0=> Disable +// <1=> ILRC +// <2=> ELS X'TAL +// <4=> HCLK +// <5=> IHRC +// <6=> EHS X'TAL +// <7=> PLL +// +*/ + +#ifndef SYS_CLOCK_SETUP +#define SYS_CLOCK_SETUP 1 +#endif +#ifndef SYS0_CLKCFG_VAL +#define SYS0_CLKCFG_VAL 0 +#endif +#ifndef EHS_FREQ +#define EHS_FREQ 10 +#endif +#ifndef PLL_MSEL +#define PLL_MSEL 12 +#endif +#ifndef PLL_PSEL +#define PLL_PSEL 3 +#endif +#ifndef PLL_FSEL +#define PLL_FSEL 0 +#endif +#ifndef PLL_CLKIN +#define PLL_CLKIN 1 +#endif +#ifndef PLL_ENABLE +#define PLL_ENABLE 0 +#endif +#ifndef AHB_PRESCALAR +#define AHB_PRESCALAR 0x0 +#endif +#ifndef CLKOUT_SEL_VAL +#define CLKOUT_SEL_VAL 0x0 +#endif + +/* +//-------- <<< end of configuration section >>> ------------------------------ +*/ + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ +#ifndef IHRC +#define IHRC 0 +#endif +#ifndef ILRC +#define ILRC 1 +#endif +#ifndef EHSXTAL +#define EHSXTAL 2 +#endif +#ifndef ELSXTAL +#define ELSXTAL 3 +#endif +#ifndef PLL +#define PLL 4 +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __IHRC_FREQ (12000000UL) +#define __ILRC_FREQ (32000UL) +#define __ELS_XTAL_FREQ (32768UL) + +#if (SYS_CLOCK_SETUP) +#define SYS0_PLLCTRL_VAL (PLL_ENABLE<<15) | (PLL_CLKIN<<12) | (PLL_FSEL<<8) | (PLL_PSEL<<5) | PLL_MSEL +#endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + uint32_t AHB_prescaler = 0; + uint32_t F; + + switch (SN_SYS0->CLKCFG_b.SYSCLKST) + { + case 0: //IHRC + SystemCoreClock = __IHRC_FREQ; + break; + case 1: //ILRC + SystemCoreClock = __ILRC_FREQ; + break; + case 2: //EHS X'TAL +#if (SYS_CLOCK_SETUP) + SystemCoreClock = EHS_FREQ * 1000000; +#else + //TODO: User had to assign EHS X'TAL frequency. + SystemCoreClock = 10000000UL / AHB_prescaler; +#endif + break; + case 3: //ELS X'TAL + SystemCoreClock = __ELS_XTAL_FREQ; + break; + case 4: //PLL +#if (SYS_CLOCK_SETUP) + if (PLL_FSEL == 0) + F = 1; + else + F = 2; + if (PLL_CLKIN == 0x0) //IHRC as F_CLKIN + SystemCoreClock = __IHRC_FREQ / F * PLL_MSEL / PLL_PSEL /2; + else + SystemCoreClock = EHS_FREQ * 1000000 / F * PLL_MSEL / PLL_PSEL /2; +#else + //TODO: User had to assign PLL output frequency. + SystemCoreClock = 50000000UL; +#endif + break; + default: + break; + } + + switch (SN_SYS0->AHBCP) + { + case 0: AHB_prescaler = 1; break; + case 1: AHB_prescaler = 2; break; + case 2: AHB_prescaler = 4; break; + case 3: AHB_prescaler = 8; break; + case 4: AHB_prescaler = 16; break; + case 5: AHB_prescaler = 32; break; + case 6: AHB_prescaler = 64; break; + case 7: AHB_prescaler = 128;break; + case 8: AHB_prescaler = 256;break; + case 9: AHB_prescaler = 512;break; + default: break; + } + + SystemCoreClock /= AHB_prescaler; + + return; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + +#if (SYS_CLOCK_SETUP) + +#if SYS0_CLKCFG_VAL == IHRC //IHRC + +#endif + +#if SYS0_CLKCFG_VAL == ILRC //ILRC + SN_SYS0->CLKCFG = 0x1; + while ((SN_SYS0->CLKCFG & 0x70) != 0x10); +#endif + +#if (SYS0_CLKCFG_VAL == EHSXTAL) //EHS XTAL + #if (EHS_FREQ > 12) + SN_SYS0->ANBCTRL |= (1<<5); + #else + SN_SYS0->ANBCTRL &=~(1<<5); + #endif + SN_SYS0->ANBCTRL |= (1<<4); + while ((SN_SYS0->CSST & 0x10) != 0x10); + SN_SYS0->CLKCFG = 0x2; + while ((SN_SYS0->CLKCFG & 0x70) != 0x20); +#endif + +#if (SYS0_CLKCFG_VAL == ELSXTAL) //ELS XTAL + SN_SYS0->ANBCTRL |=0x04; + while((SN_SYS0->CSST & 0x4) != 0x4); + SN_SYS0->CLKCFG = 0x3; + while ((SN_SYS0->CLKCFG & 0x70) != 0x30); +#endif + +#if (SYS0_CLKCFG_VAL == PLL) //PLL + SN_SYS0->PLLCTRL = SYS0_PLLCTRL_VAL; + if (PLL_CLKIN == 0x1) //EHS XTAL as F_CLKIN + { + //Enable EHS + #if (EHS_FREQ > 12) + SN_SYS0->ANBCTRL |= (1<<5); + #else + SN_SYS0->ANBCTRL &=~(1<<5); + #endif + SN_SYS0->ANBCTRL |= (1<<4); + while ((SN_SYS0->CSST & 0x10) != 0x10); + } + + while ((SN_SYS0->CSST & 0x40) != 0x40); + SN_SYS0->CLKCFG = 0x4; + while ((SN_SYS0->CLKCFG & 0x70) != 0x40); +#endif + + SN_SYS0->AHBCP = AHB_PRESCALAR; + +#if (CLKOUT_SEL_VAL > 0) //CLKOUT + SN_SYS1->AHBCLKEN_b.CLKOUTSEL = CLKOUT_SEL_VAL; +#endif +#endif //(SYS_CLOCK_SETUP) + +} \ No newline at end of file diff --git a/os/common/ext/SONiX/SN32F2xx/system_SN32F240B.c b/os/common/ext/SONiX/SN32F2xx/system_SN32F240B.c new file mode 100644 index 00000000..30f63aea --- /dev/null +++ b/os/common/ext/SONiX/SN32F2xx/system_SN32F240B.c @@ -0,0 +1,220 @@ +/****************************************************************************** + * @file system_SN32F240B.c + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File + * for the SONIX SN32F240B Devices + * @version V1.0.3 + * @date 2018/09/18 + * + * @note + * Copyright (C) 2014-2018 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#include +#include +#include +#include + + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// System Clock Configuration +// SYSCLKSEL (SYS0_CLKCFG) +// <0=> IHRC=48MHz +// <1=> ILRC +// +// AHB Clock Prescaler Register (SYS0_AHBCP) +// <0=> SYSCLK/1 +// <1=> SYSCLK/2 +// <2=> SYSCLK/4 +// <3=> SYSCLK/8 +// <4=> SYSCLK/16 +// <5=> SYSCLK/32 +// <6=> SYSCLK/64 +// <7=> SYSCLK/128 +// +// CLKOUT selection +// <0=> Disable +// <1=> ILRC +// <4=> HCLK +// <5=> IHRC +// +// CLKOUT Prescaler Register (SYS1_APBCP1) +// <0=> CLKOUT/1 +// <1=> CLKOUT/2 +// <2=> CLKOUT/4 +// <3=> CLKOUT/8 +// <4=> CLKOUT/16 +// <5=> CLKOUT/32 +// <6=> CLKOUT/64 +// <7=> CLKOUT/128 +// +*/ +#ifndef SYS_CLOCK_SETUP +#define SYS_CLOCK_SETUP 1 +#endif +#ifndef SYS0_CLKCFG_VAL +#define SYS0_CLKCFG_VAL 0 +#endif +#ifndef AHB_PRESCALAR +#define AHB_PRESCALAR 0x0 +#endif +#ifndef CLKOUT_SEL_VAL +#define CLKOUT_SEL_VAL 0x0 +#endif +#ifndef CLKOUT_PRESCALAR +#define CLKOUT_PRESCALAR 0x0 +#endif + +/* +//-------- <<< end of configuration section >>> ------------------------------ +*/ + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ +#ifndef IHRC48 +#define IHRC48 0 +#endif +#ifndef ILRC +#define ILRC 1 +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __IHRC48_FREQ (48000000UL) +#define __ILRC_FREQ (32000UL) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + uint32_t AHB_prescaler = 0; + + switch (SN_SYS0->CLKCFG_b.SYSCLKST) + { + case 0: //IHRC + if(SN_SYS0->ANBCTRL == 1) + SystemCoreClock = __IHRC48_FREQ; + break; + case 1: //ILRC + SystemCoreClock = __ILRC_FREQ; + break; + + default: + break; + } + + switch (SN_SYS0->AHBCP_b.AHBPRE) + { + case 0: AHB_prescaler = 1; break; + case 1: AHB_prescaler = 2; break; + case 2: AHB_prescaler = 4; break; + case 3: AHB_prescaler = 8; break; + case 4: AHB_prescaler = 16; break; + case 5: AHB_prescaler = 32; break; + case 6: AHB_prescaler = 64; break; + case 7: AHB_prescaler = 128;break; + default: break; + } + + SystemCoreClock /= AHB_prescaler; +} +/** + * Initialize the Flash controller + * + * @param none + * @return none + * + * @brief Update the Flash power control. + */ +void FlashClockUpdate (void) +{ + //;;;;;;;;; Need for SN32F240B Begin + if (SystemCoreClock > 24000000) + SN_FLASH->LPCTRL = 0x5AFA0005; + else if (SystemCoreClock > 12000000) + SN_FLASH->LPCTRL = 0x5AFA0003; + else if (SystemCoreClock > 8000) + SN_FLASH->LPCTRL = 0x5AFA0000; + else //Slow mode required for SystemCoreClock <= 8000 + SlowModeSwitch(); + //;;;;;;;;; Need for SN32F240B End +} +/** + * Switch System to Slow Mode + * @param none + * @return none + * + * @brief Special init required for SystemCoreClock <= 8000 + */ +void SlowModeSwitch (void) +{ + SN_SYS0->CLKCFG_b.SYSCLKSEL = 1; //Switch to ILRC + SN_SYS0->AHBCP_b.AHBPRE =0x2; //8kHz only for now + SystemCoreClockUpdate(); + SN_FLASH->LPCTRL = 0x5AFA0002; +} +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ +#if (SYS_CLOCK_SETUP) + + #if SYS0_CLKCFG_VAL == IHRC48 //IHRC=48MHz + + SN_FLASH->LPCTRL = 0x5AFA0005; + + SN_SYS0->ANBCTRL = 0x1; + while ((SN_SYS0->CSST & 0x1) != 0x1); + SN_SYS0->CLKCFG = 0x0; + while ((SN_SYS0->CLKCFG & 0x70) != 0x0); + #endif + + #if SYS0_CLKCFG_VAL == ILRC //ILRC ON + SN_FLASH->LPCTRL = 0x5AFA0000; + SN_SYS0->CLKCFG = 0x1; + while ((SN_SYS0->CLKCFG & 0x70) != 0x10); + #endif + + SN_SYS0->AHBCP_b.AHBPRE = AHB_PRESCALAR; + + sys1EnableCLKOUT(CLKOUT_SEL_VAL); + sys1SelectCLKOUTPRE(CLKOUT_PRESCALAR); +#endif //(SYS_CLOCK_SETUP) + +} diff --git a/os/common/ext/SONiX/SN32F2xx/system_SN32F260.c b/os/common/ext/SONiX/SN32F2xx/system_SN32F260.c new file mode 100644 index 00000000..453da394 --- /dev/null +++ b/os/common/ext/SONiX/SN32F2xx/system_SN32F260.c @@ -0,0 +1,172 @@ +/****************************************************************************** + * @file system_SN32F260.c + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File + * for the SONIX SN32F260 Devices + * @version V1.0.3 + * @date 2016/01/21 + * + * @note + * Copyright (C) 2014-2015 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#include +#include +#include +#include + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// System Clock Configuration +// SYSCLKSEL (SYS0_CLKCFG) +// <0=> IHRC +// <1=> ILRC +// +// AHB Clock Prescaler Register (SYS0_AHBCP) +// <0=> SYSCLK/1 +// <1=> SYSCLK/2 +// <2=> SYSCLK/4 +// <3=> SYSCLK/8 +// <4=> SYSCLK/16 +// <5=> SYSCLK/32 +// <6=> SYSCLK/64 +// <7=> SYSCLK/128 +// +// CLKOUT selection +// <0=> Disable +// <1=> ILRC +// <4=> HCLK +// <5=> IHRC +// +*/ +#ifndef SYS_CLOCK_SETUP +#define SYS_CLOCK_SETUP 1 +#endif +#ifndef SYS0_CLKCFG_VAL +#define SYS0_CLKCFG_VAL 0 +#endif +#ifndef AHB_PRESCALAR +#define AHB_PRESCALAR 0x0 +#endif +#ifndef CLKOUT_SEL_VAL +#define CLKOUT_SEL_VAL 0x0 +#endif + +/* +//-------- <<< end of configuration section >>> ------------------------------ +*/ + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ +#ifndef IHRC +#define IHRC 0 +#endif +#ifndef ILRC +#define ILRC 1 +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __IHRC_FREQ (48000000UL) +#define __ILRC_FREQ (32000UL) + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + uint32_t AHB_prescaler; + + switch ((SN_SYS0->CLKCFG >> 4) & 0x07) + { + case 0: //IHRC + SystemCoreClock = __IHRC_FREQ; + break; + case 1: //ILRC + SystemCoreClock = __ILRC_FREQ; + break; + + default: + break; + } + + switch (AHB_PRESCALAR) + { + case 0: AHB_prescaler = 1; break; + case 1: AHB_prescaler = 2; break; + case 2: AHB_prescaler = 4; break; + case 3: AHB_prescaler = 8; break; + case 4: AHB_prescaler = 16; break; + case 5: AHB_prescaler = 32; break; + case 6: AHB_prescaler = 64; break; + case 7: AHB_prescaler = 128;break; + default: break; + } + + SystemCoreClock /= AHB_prescaler; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ +#if (SYS_CLOCK_SETUP) + + #if SYS0_CLKCFG_VAL == IHRC //IHRC + + #if (AHB_PRESCALAR == 0 | AHB_PRESCALAR == 1) + SN_FLASH->LPCTRL = 0x5AFA0005; + #else + SN_FLASH->LPCTRL = 0x5AFA0000; + #endif + + SN_SYS0->AHBCP = AHB_PRESCALAR; + SN_SYS0->CLKCFG = 0x0; + while ((SN_SYS0->CLKCFG & 0x70) != 0x0); + #endif + + #if SYS0_CLKCFG_VAL == ILRC //ILRC + SN_FLASH->LPCTRL = 0x5AFA0000; + SN_SYS0->CLKCFG = 0x1; + while ((SN_SYS0->CLKCFG & 0x70) != 0x10); + SN_SYS0->AHBCP = AHB_PRESCALAR; + #endif + + + + sys1EnableCLKOUT(CLKOUT_SEL_VAL); +#endif //(SYS_CLOCK_SETUP) + +} \ No newline at end of file diff --git a/os/common/ext/SONiX/SN32F2xx/system_SN32F280.c b/os/common/ext/SONiX/SN32F2xx/system_SN32F280.c new file mode 100644 index 00000000..d68c4881 --- /dev/null +++ b/os/common/ext/SONiX/SN32F2xx/system_SN32F280.c @@ -0,0 +1,299 @@ +/****************************************************************************** + * @file system_SN32F280.c + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File + * for the SONIX SN32F790 Devices + * @version V0.0.5 + * @date 2018/06/14 + * + * @note + * Copyright (C) 2016-2017 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#include +#include +#include + + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// SYSCLKSEL (SYS0_CLKCFG) +// <0=> IHRC +// <1=> ILRC +// <2=> EHS X'TAL +// <3=> ELS X'TAL +// <4=> PLL +// +// EHS Source Frequency (MHz) +// <10-25> +// +// PLL ENABLE +// PLL Control Register (SYS0_PLLCTRL) +// F_CLKOUT = F_VCO / P = (F_CLKIN * M) / P +// 10 MHz <= F_CLKIN <= 25 MHz +// 96 MHz <= (F_CLKIN * M) <= 144 MHz +// MSEL +// <0=> M = 4 +// <1=> M = 6 +// <2=> M = 8 +// <3=> M = 10 +// <4=> M = 12 +// PSEL +// <0=> P = 2 +// <1=> P = 4 +// PLL CLKIN Source selection +// <0=> IHRC +// <1=> EHS X'TAL +// +// +// AHB Clock Prescaler Register (SYS0_AHBCP) +// <0=> SYSCLK/1 +// <1=> SYSCLK/2 +// <2=> SYSCLK/4 +// <3=> SYSCLK/8 +// <4=> SYSCLK/16 +// <5=> SYSCLK/32 +// <6=> SYSCLK/64 +// <7=> SYSCLK/128 +// SYSCLK prescaler Register (SYS0_AHBCP) +// <0=> SYSCLK/1 +// <1=> SYSCLK/1.5 +// CLKOUT selection +// <0=> Disable +// <1=> ILRC +// <2=> ELS X'TAL +// <4=> HCLK +// <5=> IHRC +// <6=> EHS X'TAL +// <7=> PLL +// CLKOUT Prescaler Register (SYS1_APBCP1) +// <0=> CLKOUT selection/1 +// <1=> CLKOUT selection/2 +// <2=> CLKOUT selection/4 +// <3=> CLKOUT selection/8 +// <4=> CLKOUT selection/16 +// <5=> CLKOUT selection/32 +// <6=> CLKOUT selection/64 +// <7=> CLKOUT selection/128 +*/ + + +#ifndef SYS0_CLKCFG_VAL +#define SYS0_CLKCFG_VAL 0 +#endif +#ifndef EHS_FREQ +#define EHS_FREQ 16 +#endif +#ifndef PLL_ENABLE +#define PLL_ENABLE 0 +#endif +#ifndef PLL_MSEL +#define PLL_MSEL 1 +#endif +#ifndef PLL_PSEL +#define PLL_PSEL 0 +#endif +#ifndef PLL_CLKIN +#define PLL_CLKIN 0 +#endif +#ifndef AHB_PRESCALAR +#define AHB_PRESCALAR 0x0 +#endif +#ifndef AHB_1P5PRESCALAR +#define AHB_1P5PRESCALAR 0x0 +#endif +#ifndef CLKOUT_SEL_VAL +#define CLKOUT_SEL_VAL 0x0 +#endif +#ifndef CLKOUT_PRESCALAR +#define CLKOUT_PRESCALAR 0x0 +#endif + +/* +//-------- <<< end of configuration section >>> ------------------------------ +*/ + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ +#ifndef IHRC +#define IHRC 0 +#endif +#ifndef ILRC +#define ILRC 1 +#endif +#ifndef EHSXTAL +#define EHSXTAL 2 +#endif +#ifndef ELSXTAL +#define ELSXTAL 3 +#endif +#ifndef PLL +#define PLL 4 +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __IHRC_FREQ (12000000UL) +#define __ILRC_FREQ (32000UL) +#define __ELS_XTAL_FREQ (32768UL) + +#define SYS0_PLLCTRL_VAL (PLL_ENABLE<<15) | (PLL_CLKIN<<12) | (PLL_PSEL<<5) | PLL_MSEL + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + uint32_t AHB_prescaler; + + switch (SN_SYS0->CLKCFG_b.SYSCLKST) + { + case 0: //IHRC + SystemCoreClock = __IHRC_FREQ; + break; + case 1: //ILRC + SystemCoreClock = __ILRC_FREQ; + break; + case 2: //EHS X'TAL + SystemCoreClock = EHS_FREQ * 1000000; + break; + case 3: //ELS X'TAL + SystemCoreClock = __ELS_XTAL_FREQ; + break; + case 4: //PLL + if (PLL_CLKIN == 0x0) //IHRC as F_CLKIN + SystemCoreClock = __IHRC_FREQ * (PLL_MSEL+2) / (PLL_PSEL+1); + else + SystemCoreClock = EHS_FREQ * 1000000 * (PLL_MSEL+2) / (PLL_PSEL+1); + break; + default: + break; + } + + switch (SN_SYS0->AHBCP) + { + case 0: AHB_prescaler = 1; break; + case 1: AHB_prescaler = 2; break; + case 2: AHB_prescaler = 4; break; + case 3: AHB_prescaler = 8; break; + case 4: AHB_prescaler = 16; break; + case 5: AHB_prescaler = 32; break; + case 6: AHB_prescaler = 64; break; + case 7: AHB_prescaler = 128;break; + default: break; + } + + SystemCoreClock /= AHB_prescaler; + + if (SN_SYS0->AHBCP_b.DIV1P5 == 1) + SystemCoreClock = SystemCoreClock*2/3; + + //;;;;;;;;; Need for SN32F780 Begin ;;;;;;;;; + if (SystemCoreClock > 48000000) + SN_FLASH->LPCTRL = 0x5AFA0031; + else if (SystemCoreClock > 24000000) + SN_FLASH->LPCTRL = 0x5AFA0011; + else + SN_FLASH->LPCTRL = 0x5AFA0000; + //;;;;;;;;; Need for SN32F780 End ;;;;;;;;; + + return; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + #if SYS0_CLKCFG_VAL == IHRC //IHRC + SN_SYS0->CLKCFG = 0x0; + while ((SN_SYS0->CLKCFG & 0x70) != 0x0); + #endif + + #if SYS0_CLKCFG_VAL == ILRC //ILRC + SN_SYS0->CLKCFG = 0x1; + while ((SN_SYS0->CLKCFG & 0x70) != 0x10); + #endif + + #if (SYS0_CLKCFG_VAL == EHSXTAL) //EHS XTAL + #if (EHS_FREQ > 12) + SN_SYS0->ANBCTRL_b.EHSFREQ = 1; + SN_FLASH->LPCTRL = 0x5AFA0011; + #else + SN_SYS0->ANBCTRL_b.EHSFREQ = 0; + #endif + SN_SYS0->ANBCTRL_b.EHSEN = 1; + while ((SN_SYS0->CSST & 0x10) != 0x10); + SN_SYS0->CLKCFG = 0x2; + while ((SN_SYS0->CLKCFG & 0x70) != 0x20); + #endif + + #if (SYS0_CLKCFG_VAL == ELSXTAL) //ELS XTAL + SN_SYS0->ANBCTRL_b.ELSEN = 1; + while((SN_SYS0->CSST & 0x4) != 0x4); + SN_SYS0->CLKCFG = 0x3; + while ((SN_SYS0->CLKCFG & 0x70) != 0x30); + #endif + + #if (PLL_ENABLE == 1) + SN_SYS0->PLLCTRL = SYS0_PLLCTRL_VAL; + if (PLL_CLKIN == 0x1) //EHS XTAL as F_CLKIN + { + //Enable EHS + #if (EHS_FREQ > 12) + SN_SYS0->ANBCTRL_b.EHSFREQ = 1; + #else + SN_SYS0->ANBCTRL_b.EHSFREQ = 0; + #endif + SN_SYS0->ANBCTRL_b.EHSEN = 1; + while ((SN_SYS0->CSST & 0x10) != 0x10); + } + while ((SN_SYS0->CSST & 0x40) != 0x40); + #if (SYS0_CLKCFG_VAL == PLL) //PLL + SN_FLASH->LPCTRL = 0x5AFA0031; + SN_SYS0->CLKCFG = 0x4; + while ((SN_SYS0->CLKCFG & 0x70) != 0x40); + #endif + #endif + + SN_SYS0->AHBCP = AHB_PRESCALAR; + SN_SYS0->AHBCP_b.DIV1P5 = AHB_1P5PRESCALAR; + + #if (CLKOUT_SEL_VAL > 0) //CLKOUT + SN_SYS1->AHBCLKEN_b.CLKOUTSEL = CLKOUT_SEL_VAL; + SN_SYS1->APBCP1_b.CLKOUTPRE = CLKOUT_PRESCALAR; + #endif +} diff --git a/os/common/ext/SONiX/SN32F2xx/system_SN32F290.c b/os/common/ext/SONiX/SN32F2xx/system_SN32F290.c new file mode 100644 index 00000000..5b91a1ac --- /dev/null +++ b/os/common/ext/SONiX/SN32F2xx/system_SN32F290.c @@ -0,0 +1,298 @@ +/****************************************************************************** + * @file system_SN32F290.c + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File + * for the SONIX SN32F790 Devices + * @version V0.0.5 + * @date 2018/06/14 + * + * @note + * Copyright (C) 2016-2017 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#include +#include +#include + + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// SYSCLKSEL (SYS0_CLKCFG) +// <0=> IHRC +// <1=> ILRC +// <2=> EHS X'TAL +// <3=> ELS X'TAL +// <4=> PLL +// +// EHS Source Frequency (MHz) +// <10-25> +// +// PLL ENABLE +// PLL Control Register (SYS0_PLLCTRL) +// F_CLKOUT = F_VCO / P = (F_CLKIN * M) / P +// 10 MHz <= F_CLKIN <= 25 MHz +// 96 MHz <= (F_CLKIN * M) <= 144 MHz +// MSEL +// <0=> M = 4 +// <1=> M = 6 +// <2=> M = 8 +// <3=> M = 10 +// <4=> M = 12 +// PSEL +// <0=> P = 2 +// <1=> P = 4 +// PLL CLKIN Source selection +// <0=> IHRC +// <1=> EHS X'TAL +// +// +// AHB Clock Prescaler Register (SYS0_AHBCP) +// <0=> SYSCLK/1 +// <1=> SYSCLK/2 +// <2=> SYSCLK/4 +// <3=> SYSCLK/8 +// <4=> SYSCLK/16 +// <5=> SYSCLK/32 +// <6=> SYSCLK/64 +// <7=> SYSCLK/128 +// SYSCLK prescaler Register (SYS0_AHBCP) +// <0=> SYSCLK/1 +// <1=> SYSCLK/1.5 +// CLKOUT selection +// <0=> Disable +// <1=> ILRC +// <2=> ELS X'TAL +// <4=> HCLK +// <5=> IHRC +// <6=> EHS X'TAL +// <7=> PLL +// CLKOUT Prescaler Register (SYS1_APBCP1) +// <0=> CLKOUT selection/1 +// <1=> CLKOUT selection/2 +// <2=> CLKOUT selection/4 +// <3=> CLKOUT selection/8 +// <4=> CLKOUT selection/16 +// <5=> CLKOUT selection/32 +// <6=> CLKOUT selection/64 +// <7=> CLKOUT selection/128 +*/ + +#ifndef SYS0_CLKCFG_VAL +#define SYS0_CLKCFG_VAL 0 +#endif +#ifndef EHS_FREQ +#define EHS_FREQ 16 +#endif +#ifndef PLL_ENABLE +#define PLL_ENABLE 0 +#endif +#ifndef PLL_MSEL +#define PLL_MSEL 1 +#endif +#ifndef PLL_PSEL +#define PLL_PSEL 0 +#endif +#ifndef PLL_CLKIN +#define PLL_CLKIN 0 +#endif +#ifndef AHB_PRESCALAR +#define AHB_PRESCALAR 0x0 +#endif +#ifndef AHB_1P5PRESCALAR +#define AHB_1P5PRESCALAR 0x0 +#endif +#ifndef CLKOUT_SEL_VAL +#define CLKOUT_SEL_VAL 0x0 +#endif +#ifndef CLKOUT_PRESCALAR +#define CLKOUT_PRESCALAR 0x0 +#endif + +/* +//-------- <<< end of configuration section >>> ------------------------------ +*/ + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ +#ifndef IHRC +#define IHRC 0 +#endif +#ifndef ILRC +#define ILRC 1 +#endif +#ifndef EHSXTAL +#define EHSXTAL 2 +#endif +#ifndef ELSXTAL +#define ELSXTAL 3 +#endif +#ifndef PLL +#define PLL 4 +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __IHRC_FREQ (12000000UL) +#define __ILRC_FREQ (32000UL) +#define __ELS_XTAL_FREQ (32768UL) + +#define SYS0_PLLCTRL_VAL (PLL_ENABLE<<15) | (PLL_CLKIN<<12) | (PLL_PSEL<<5) | PLL_MSEL + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + uint32_t AHB_prescaler; + + switch (SN_SYS0->CLKCFG_b.SYSCLKST) + { + case 0: //IHRC + SystemCoreClock = __IHRC_FREQ; + break; + case 1: //ILRC + SystemCoreClock = __ILRC_FREQ; + break; + case 2: //EHS X'TAL + SystemCoreClock = EHS_FREQ * 1000000; + break; + case 3: //ELS X'TAL + SystemCoreClock = __ELS_XTAL_FREQ; + break; + case 4: //PLL + if (PLL_CLKIN == 0x0) //IHRC as F_CLKIN + SystemCoreClock = __IHRC_FREQ * (PLL_MSEL+2) / (PLL_PSEL+1); + else + SystemCoreClock = EHS_FREQ * 1000000 * (PLL_MSEL+2) / (PLL_PSEL+1); + break; + default: + break; + } + + switch (SN_SYS0->AHBCP) + { + case 0: AHB_prescaler = 1; break; + case 1: AHB_prescaler = 2; break; + case 2: AHB_prescaler = 4; break; + case 3: AHB_prescaler = 8; break; + case 4: AHB_prescaler = 16; break; + case 5: AHB_prescaler = 32; break; + case 6: AHB_prescaler = 64; break; + case 7: AHB_prescaler = 128;break; + default: break; + } + + SystemCoreClock /= AHB_prescaler; + + if (SN_SYS0->AHBCP_b.DIV1P5 == 1) + SystemCoreClock = SystemCoreClock*2/3; + + //;;;;;;;;; Need for SN32F780 Begin ;;;;;;;;; + if (SystemCoreClock > 48000000) + SN_FLASH->LPCTRL = 0x5AFA0031; + else if (SystemCoreClock > 24000000) + SN_FLASH->LPCTRL = 0x5AFA0011; + else + SN_FLASH->LPCTRL = 0x5AFA0000; + //;;;;;;;;; Need for SN32F780 End ;;;;;;;;; + + return; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + #if SYS0_CLKCFG_VAL == IHRC //IHRC + SN_SYS0->CLKCFG = 0x0; + while ((SN_SYS0->CLKCFG & 0x70) != 0x0); + #endif + + #if SYS0_CLKCFG_VAL == ILRC //ILRC + SN_SYS0->CLKCFG = 0x1; + while ((SN_SYS0->CLKCFG & 0x70) != 0x10); + #endif + + #if (SYS0_CLKCFG_VAL == EHSXTAL) //EHS XTAL + #if (EHS_FREQ > 12) + SN_SYS0->ANBCTRL_b.EHSFREQ = 1; + SN_FLASH->LPCTRL = 0x5AFA0011; + #else + SN_SYS0->ANBCTRL_b.EHSFREQ = 0; + #endif + SN_SYS0->ANBCTRL_b.EHSEN = 1; + while ((SN_SYS0->CSST & 0x10) != 0x10); + SN_SYS0->CLKCFG = 0x2; + while ((SN_SYS0->CLKCFG & 0x70) != 0x20); + #endif + + #if (SYS0_CLKCFG_VAL == ELSXTAL) //ELS XTAL + SN_SYS0->ANBCTRL_b.ELSEN = 1; + while((SN_SYS0->CSST & 0x4) != 0x4); + SN_SYS0->CLKCFG = 0x3; + while ((SN_SYS0->CLKCFG & 0x70) != 0x30); + #endif + + #if (PLL_ENABLE == 1) + SN_SYS0->PLLCTRL = SYS0_PLLCTRL_VAL; + if (PLL_CLKIN == 0x1) //EHS XTAL as F_CLKIN + { + //Enable EHS + #if (EHS_FREQ > 12) + SN_SYS0->ANBCTRL_b.EHSFREQ = 1; + #else + SN_SYS0->ANBCTRL_b.EHSFREQ = 0; + #endif + SN_SYS0->ANBCTRL_b.EHSEN = 1; + while ((SN_SYS0->CSST & 0x10) != 0x10); + } + while ((SN_SYS0->CSST & 0x40) != 0x40); + #if (SYS0_CLKCFG_VAL == PLL) //PLL + SN_FLASH->LPCTRL = 0x5AFA0031; + SN_SYS0->CLKCFG = 0x4; + while ((SN_SYS0->CLKCFG & 0x70) != 0x40); + #endif + #endif + + SN_SYS0->AHBCP = AHB_PRESCALAR; + SN_SYS0->AHBCP_b.DIV1P5 = AHB_1P5PRESCALAR; + + #if (CLKOUT_SEL_VAL > 0) //CLKOUT + SN_SYS1->AHBCLKEN_b.CLKOUTSEL = CLKOUT_SEL_VAL; + SN_SYS1->APBCP1_b.CLKOUTPRE = CLKOUT_PRESCALAR; + #endif +} diff --git a/os/common/ext/SONiX/SN32F2xx/system_SN32F2xx.h b/os/common/ext/SONiX/SN32F2xx/system_SN32F2xx.h new file mode 100644 index 00000000..30c27350 --- /dev/null +++ b/os/common/ext/SONiX/SN32F2xx/system_SN32F2xx.h @@ -0,0 +1,84 @@ +/**************************************************************************//** + * @file system_SN32F240B.h + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File + * for the SONIX SN32F240B Device + * @version V1.1 + * @date Jul 2017 + * + * @note + * Copyright (C) 2009-2017 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __SYSTEM_SN32F2xx_H +#define __SYSTEM_SN32F2xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "SN32F2xx.h" +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); +#if defined(SN32F240B) +/** + * Initialize the Flash controller + * + * @param none + * @return none + * + * @brief Update the Flash power control. + */ +extern void FlashClockUpdate (void); + +/** + * Switch System to Slow Mode + * @param none + * @return none + * + * @brief Special init required for SystemCoreClock <= 8000 + */ +extern void SlowModeSwitch (void); +#endif /* defined(SN32F240B) */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_SN32F2xx_H */ diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F240.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F240.ld new file mode 100644 index 00000000..addcbfa7 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F240.ld @@ -0,0 +1,96 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SN32F240 memory setup. + */ +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 64k + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 8k + ram1 (wx) : org = 0x00000000, len = 0 + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x00000000, len = 0 + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld + + +_flag_start = 0xFFFC; + +SECTIONS +{ + .flag _flag_start : + { + KEEP(*(.flag)) ; + } > flash0 +} \ No newline at end of file diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F240B.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F240B.ld new file mode 100644 index 00000000..754c31b3 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F240B.ld @@ -0,0 +1,96 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SN32F240B memory setup. + */ +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 64k + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 8k + ram1 (wx) : org = 0x00000000, len = 0 + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x00000000, len = 0 + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld + + +_flag_start = 0xFFFC; + +SECTIONS +{ + .flag _flag_start : + { + KEEP(*(.flag)) ; + } > flash0 +} \ No newline at end of file diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F260.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F260.ld new file mode 100644 index 00000000..1ee9f91d --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F260.ld @@ -0,0 +1,105 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SN32F240B memory setup. + * 0x200 entry point bootloader + */ +MEMORY +{ + flash0 (rx) : org = 0x00000200, len = 30208 + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 2k + ram1 (wx) : org = 0x00000000, len = 0 + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x00000000, len = 0 + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Custom vectors section with 512 byte alignment. + + The default ChibiOS linker script aligns to 1024 bytes, because that is the worse + case alignment requirement for STM32 chips. + See https://forum.chibios.org/viewtopic.php?t=5554 + + However the sonix-keyboard-bootloader expects the ISR vector table to be at 0x200. + This is not possible if the alignment is 1024 bytes. + + By adding this custom section with 512 byte alignment before the inclusion of + the rules.ld defaults, the linker will use this section for .vectors objects. */ +SECTIONS +{ + .vectors_512_aligned : ALIGN(512) + { + KEEP(*(.vectors)) + } > VECTORS_FLASH AT > VECTORS_FLASH_LMA +} + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F280.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F280.ld new file mode 100644 index 00000000..60142cfd --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F280.ld @@ -0,0 +1,96 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SN32F280 memory setup. + */ +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 128k + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 32k + ram1 (wx) : org = 0x00000000, len = 0 + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x00000000, len = 0 + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld + + +_flag_start = 0xFFFC; + +SECTIONS +{ + .flag _flag_start : + { + KEEP(*(.flag)) ; + } > flash0 +} diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F290.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F290.ld new file mode 100644 index 00000000..17f7517e --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/SN32F290.ld @@ -0,0 +1,96 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SN32F290 memory setup. + */ +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 256k + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 32k + ram1 (wx) : org = 0x00000000, len = 0 + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x00000000, len = 0 + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld + + +_flag_start = 0xFFFC; + +SECTIONS +{ + .flag _flag_start : + { + KEEP(*(.flag)) ; + } > flash0 +} diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f24x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f24x.mk new file mode 100644 index 00000000..fb25fff1 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f24x.mk @@ -0,0 +1,20 @@ +# List of the ChibiOS generic SN32F24x startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx/system_SN32F240.c + +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S + +STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \ + $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/SN32F24x \ + $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \ + $(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx + +STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld +STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld + +# Shared variables +ALLXASMSRC += $(STARTUPASM) +ALLCSRC += $(STARTUPSRC) +ALLINC += $(STARTUPINC) \ No newline at end of file diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f24xb.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f24xb.mk new file mode 100644 index 00000000..07243240 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f24xb.mk @@ -0,0 +1,20 @@ +# List of the ChibiOS generic SN32F24xB startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx/system_SN32F240B.c + +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S + +STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \ + $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/SN32F24xB \ + $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \ + $(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx + +STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld +STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld + +# Shared variables +ALLXASMSRC += $(STARTUPASM) +ALLCSRC += $(STARTUPSRC) +ALLINC += $(STARTUPINC) \ No newline at end of file diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f26x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f26x.mk new file mode 100644 index 00000000..da7e265a --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f26x.mk @@ -0,0 +1,20 @@ +# List of the ChibiOS generic SN32F26x startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx/system_SN32F260.c + +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S + +STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \ + $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/SN32F26x \ + $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \ + $(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx + +STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld +STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld + +# Shared variables +ALLXASMSRC += $(STARTUPASM) +ALLCSRC += $(STARTUPSRC) +ALLINC += $(STARTUPINC) \ No newline at end of file diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f28x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f28x.mk new file mode 100644 index 00000000..80172a93 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f28x.mk @@ -0,0 +1,20 @@ +# List of the ChibiOS generic SN32F28x startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx/system_SN32F280.c + +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S + +STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \ + $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/SN32F28x \ + $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \ + $(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx + +STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld +STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld + +# Shared variables +ALLXASMSRC += $(STARTUPASM) +ALLCSRC += $(STARTUPSRC) +ALLINC += $(STARTUPINC) \ No newline at end of file diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f29x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f29x.mk new file mode 100644 index 00000000..58519a11 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f29x.mk @@ -0,0 +1,20 @@ +# List of the ChibiOS generic SN32F29x startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx/system_SN32F290.c + +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S + +STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \ + $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/SN32F29x \ + $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \ + $(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx + +STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld +STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld + +# Shared variables +ALLXASMSRC += $(STARTUPASM) +ALLCSRC += $(STARTUPSRC) +ALLINC += $(STARTUPINC) \ No newline at end of file diff --git a/os/common/startup/ARMCMx/devices/SN32F24x/cmparams.h b/os/common/startup/ARMCMx/devices/SN32F24x/cmparams.h new file mode 100644 index 00000000..bdd5d383 --- /dev/null +++ b/os/common/startup/ARMCMx/devices/SN32F24x/cmparams.h @@ -0,0 +1,79 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SN32F24x/cmparams.h + * @brief ARM Cortex-M0 parameters for the SN32F24x. + * + * @defgroup ARMCMx_SN32F24x SN32F24x Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M0 specific parameters for the + * SN32F24x platform. + * @{ + */ + +#ifndef CMPARAMS_H +#define CMPARAMS_H + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 0 + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU 0 + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 2 + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 32 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +#include "board.h" + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "SN32F240.h" + +/*lint -save -e9029 [10.4] Signedness comes from external files, it is + unpredictable but gives no problems.*/ +#if CORTEX_MODEL != __CORTEX_M +#error "CMSIS __CORTEX_M mismatch" +#endif + +#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS +#error "CMSIS __NVIC_PRIO_BITS mismatch" +#endif +/*lint -restore*/ + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* CMPARAMS_H */ + +/** @} */ diff --git a/os/common/startup/ARMCMx/devices/SN32F24xB/cmparams.h b/os/common/startup/ARMCMx/devices/SN32F24xB/cmparams.h new file mode 100644 index 00000000..1a435b39 --- /dev/null +++ b/os/common/startup/ARMCMx/devices/SN32F24xB/cmparams.h @@ -0,0 +1,79 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SN32F24x/cmparams.h + * @brief ARM Cortex-M0 parameters for the SN32F24x. + * + * @defgroup ARMCMx_SN32F24x SN32F24x Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M0 specific parameters for the + * SN32F24x platform. + * @{ + */ + +#ifndef CMPARAMS_H +#define CMPARAMS_H + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 0 + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU 0 + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 2 + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 32 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +#include "board.h" + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "SN32F240B.h" + +/*lint -save -e9029 [10.4] Signedness comes from external files, it is + unpredictable but gives no problems.*/ +#if CORTEX_MODEL != __CORTEX_M +#error "CMSIS __CORTEX_M mismatch" +#endif + +#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS +#error "CMSIS __NVIC_PRIO_BITS mismatch" +#endif +/*lint -restore*/ + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* CMPARAMS_H */ + +/** @} */ diff --git a/os/common/startup/ARMCMx/devices/SN32F26x/cmparams.h b/os/common/startup/ARMCMx/devices/SN32F26x/cmparams.h new file mode 100644 index 00000000..de8b5cc1 --- /dev/null +++ b/os/common/startup/ARMCMx/devices/SN32F26x/cmparams.h @@ -0,0 +1,79 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SN32F26x/cmparams.h + * @brief ARM Cortex-M0 parameters for the SN32F26x. + * + * @defgroup ARMCMx_SN32F26x SN32F26x Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M0 specific parameters for the + * SN32F26x platform. + * @{ + */ + +#ifndef CMPARAMS_H +#define CMPARAMS_H + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 0 + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU 0 + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 2 + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 32 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +#include "board.h" + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "SN32F260.h" + +/*lint -save -e9029 [10.4] Signedness comes from external files, it is + unpredictable but gives no problems.*/ +#if CORTEX_MODEL != __CORTEX_M +#error "CMSIS __CORTEX_M mismatch" +#endif + +#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS +#error "CMSIS __NVIC_PRIO_BITS mismatch" +#endif +/*lint -restore*/ + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* CMPARAMS_H */ + +/** @} */ diff --git a/os/common/startup/ARMCMx/devices/SN32F28x/cmparams.h b/os/common/startup/ARMCMx/devices/SN32F28x/cmparams.h new file mode 100644 index 00000000..b37d6892 --- /dev/null +++ b/os/common/startup/ARMCMx/devices/SN32F28x/cmparams.h @@ -0,0 +1,79 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SN32F28x/cmparams.h + * @brief ARM Cortex-M0 parameters for the SN32F28x. + * + * @defgroup ARMCMx_SN32F28x SN32F28x Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M0 specific parameters for the + * SN32F28x platform. + * @{ + */ + +#ifndef CMPARAMS_H +#define CMPARAMS_H + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 0 + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU 0 + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 2 + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 32 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +#include "board.h" + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "SN32F280.h" + +/*lint -save -e9029 [10.4] Signedness comes from external files, it is + unpredictable but gives no problems.*/ +#if CORTEX_MODEL != __CORTEX_M +#error "CMSIS __CORTEX_M mismatch" +#endif + +#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS +#error "CMSIS __NVIC_PRIO_BITS mismatch" +#endif +/*lint -restore*/ + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* CMPARAMS_H */ + +/** @} */ diff --git a/os/common/startup/ARMCMx/devices/SN32F29x/cmparams.h b/os/common/startup/ARMCMx/devices/SN32F29x/cmparams.h new file mode 100644 index 00000000..69e883e9 --- /dev/null +++ b/os/common/startup/ARMCMx/devices/SN32F29x/cmparams.h @@ -0,0 +1,79 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SN32F29x/cmparams.h + * @brief ARM Cortex-M0 parameters for the SN32F29x. + * + * @defgroup ARMCMx_SN32F29x SN32F29x Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M0 specific parameters for the + * SN32F29x platform. + * @{ + */ + +#ifndef CMPARAMS_H +#define CMPARAMS_H + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 0 + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU 0 + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 2 + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 32 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +#include "board.h" + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "SN32F290.h" + +/*lint -save -e9029 [10.4] Signedness comes from external files, it is + unpredictable but gives no problems.*/ +#if CORTEX_MODEL != __CORTEX_M +#error "CMSIS __CORTEX_M mismatch" +#endif + +#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS +#error "CMSIS __NVIC_PRIO_BITS mismatch" +#endif +/*lint -restore*/ + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* CMPARAMS_H */ + +/** @} */ diff --git a/os/hal/boards/SN_SN32F240/board.c b/os/hal/boards/SN_SN32F240/board.c new file mode 100644 index 00000000..655a9b04 --- /dev/null +++ b/os/hal/boards/SN_SN32F240/board.c @@ -0,0 +1,71 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = { + #if SN32_HAS_GPIOA + {.mode = VAL_GPIOA_MODE, .cfg = VAL_GPIOA_CFG}, + #endif + #if SN32_HAS_GPIOB + {.mode = VAL_GPIOB_MODE, .cfg = VAL_GPIOB_CFG}, + #endif + #if SN32_HAS_GPIOC + {.mode = VAL_GPIOC_MODE, .cfg = VAL_GPIOC_CFG}, + #endif + #if SN32_HAS_GPIOD + {.mode = VAL_GPIOD_MODE, .cfg = VAL_GPIOD_CFG}, + #endif +}; +#endif + +static int flag __attribute__((section(".flag"))) __attribute__((__used__)) = 0xAAAA5555; +extern void enter_bootloader_mode_if_requested(void); + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + enter_bootloader_mode_if_requested(); + sn32_clock_init(); +} + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { + + SN_SYS0->EXRSTCTRL_b.RESETDIS = 1; // Disable RESET + SN_SYS0->SWDCTRL_b.SWDDIS = 1; // Disable SWD +} + +void restart_usb_driver(USBDriver *usbp) { + // Do nothing. Restarting the USB driver on these boards breaks it. +} diff --git a/os/hal/boards/SN_SN32F240/board.h b/os/hal/boards/SN_SN32F240/board.h new file mode 100644 index 00000000..27f6f5e2 --- /dev/null +++ b/os/hal/boards/SN_SN32F240/board.h @@ -0,0 +1,262 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for Generic SN32F240 Board + */ + +/* + * Board identifier. + */ +#define BOARD_GENERIC_SN32_F240 +#define BOARD_NAME "SN32F240" + +/* + * MCU type as defined in the SN32 header. + */ +#define SN32F240 + +/* + * IO pins assignments. + */ +#define GPIOA_PIN0 0U +#define GPIOA_PIN1 1U +#define GPIOA_PIN2 2U +#define GPIOA_PIN3 3U +#define GPIOA_PIN4 4U +#define GPIOA_PIN5 5U +#define GPIOA_PIN6 6U +#define GPIOA_PIN7 7U +#define GPIOA_PIN8 8U +#define GPIOA_PIN9 9U +#define GPIOA_PIN10 10U +#define GPIOA_PIN11 11U +#define GPIOA_PIN12 12U +#define GPIOA_PIN13 13U +#define GPIOA_PIN14 14U +#define GPIOA_PIN15 15U + +#define GPIOB_PIN0 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_PIN3 3U +#define GPIOB_PIN4 4U +#define GPIOB_PIN5 5U +#define GPIOB_PIN6 6U +#define GPIOB_PIN7 7U +#define GPIOB_PIN8 8U +#define GPIOB_PIN9 9U +#define GPIOB_PIN10 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_PIN13 13U +#define GPIOB_PIN14 14U +#define GPIOB_PIN15 15U + +#define GPIOC_PIN0 0U +#define GPIOC_PIN1 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_PIN7 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_PIN13 13U +#define GPIOC_PIN14 14U +#define GPIOC_PIN15 15U + +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_PIN12 12U +#define GPIOD_PIN13 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the SN32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n))) +#define PIN_MODE_OUTPUT(n) (1U << ((n))) + +#define PIN_CFG_PULLUP(n) (0U << ((n*2))) // Pull-up +#define PIN_CFG_SCHMITT_EN(n) (2U << ((n*2))) // Floating +#define PIN_CFG_SCHMITT_DIS(n) (3U << ((n*2))) // Input buffer disconnected, alway read as zero. + +// Define GPIO register values used by pal_default_config. +// The following values match the chip reset values, all GPIO pins as floating inputs. + +#define VAL_GPIOA_MODE \ + ( PIN_MODE_INPUT(GPIOA_PIN0) \ + | PIN_MODE_INPUT(GPIOA_PIN1) \ + | PIN_MODE_INPUT(GPIOA_PIN2) \ + | PIN_MODE_INPUT(GPIOA_PIN3) \ + | PIN_MODE_INPUT(GPIOA_PIN4) \ + | PIN_MODE_INPUT(GPIOA_PIN5) \ + | PIN_MODE_INPUT(GPIOA_PIN6) \ + | PIN_MODE_INPUT(GPIOA_PIN7) \ + | PIN_MODE_INPUT(GPIOA_PIN8) \ + | PIN_MODE_INPUT(GPIOA_PIN9) \ + | PIN_MODE_INPUT(GPIOA_PIN10) \ + | PIN_MODE_INPUT(GPIOA_PIN11) \ + | PIN_MODE_INPUT(GPIOA_PIN12) \ + | PIN_MODE_INPUT(GPIOA_PIN13) \ + | PIN_MODE_INPUT(GPIOA_PIN14) \ + | PIN_MODE_INPUT(GPIOA_PIN15) ) +#define VAL_GPIOA_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOA_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN2) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN11) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN12) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN13) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN14) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN15) ) + +#define VAL_GPIOB_MODE \ + ( PIN_MODE_INPUT(GPIOB_PIN0) \ + | PIN_MODE_INPUT(GPIOB_PIN1) \ + | PIN_MODE_INPUT(GPIOB_PIN2) \ + | PIN_MODE_INPUT(GPIOB_PIN3) \ + | PIN_MODE_INPUT(GPIOB_PIN4) \ + | PIN_MODE_INPUT(GPIOB_PIN5) \ + | PIN_MODE_INPUT(GPIOB_PIN6) \ + | PIN_MODE_INPUT(GPIOB_PIN7) \ + | PIN_MODE_INPUT(GPIOB_PIN8) \ + | PIN_MODE_INPUT(GPIOB_PIN9) \ + | PIN_MODE_INPUT(GPIOB_PIN10) \ + | PIN_MODE_INPUT(GPIOB_PIN11) \ + | PIN_MODE_INPUT(GPIOB_PIN12) \ + | PIN_MODE_INPUT(GPIOB_PIN13) \ + | PIN_MODE_INPUT(GPIOB_PIN14) \ + | PIN_MODE_INPUT(GPIOB_PIN15) ) +#define VAL_GPIOB_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOB_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN2) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN11) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN12) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN13) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN14) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN15) ) + +#define VAL_GPIOC_MODE \ + ( PIN_MODE_INPUT(GPIOC_PIN0) \ + | PIN_MODE_INPUT(GPIOC_PIN1) \ + | PIN_MODE_INPUT(GPIOC_PIN2) \ + | PIN_MODE_INPUT(GPIOC_PIN3) \ + | PIN_MODE_INPUT(GPIOC_PIN4) \ + | PIN_MODE_INPUT(GPIOC_PIN5) \ + | PIN_MODE_INPUT(GPIOC_PIN6) \ + | PIN_MODE_INPUT(GPIOC_PIN7) \ + | PIN_MODE_INPUT(GPIOC_PIN8) \ + | PIN_MODE_INPUT(GPIOC_PIN9) \ + | PIN_MODE_INPUT(GPIOC_PIN10) \ + | PIN_MODE_INPUT(GPIOC_PIN11) \ + | PIN_MODE_INPUT(GPIOC_PIN12) \ + | PIN_MODE_INPUT(GPIOC_PIN13) \ + | PIN_MODE_INPUT(GPIOC_PIN14) \ + | PIN_MODE_INPUT(GPIOC_PIN15) ) +#define VAL_GPIOC_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOC_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN2) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN11) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN12) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN13) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN14) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN15) ) + +#define VAL_GPIOD_MODE \ + ( PIN_MODE_INPUT(GPIOD_PIN3) \ + | PIN_MODE_INPUT(GPIOD_PIN4) \ + | PIN_MODE_INPUT(GPIOD_PIN5) \ + | PIN_MODE_INPUT(GPIOD_PIN6) \ + | PIN_MODE_INPUT(GPIOD_PIN7) \ + | PIN_MODE_INPUT(GPIOD_PIN8) \ + | PIN_MODE_INPUT(GPIOD_PIN9) \ + | PIN_MODE_INPUT(GPIOD_PIN10) \ + | PIN_MODE_INPUT(GPIOD_PIN11) \ + | PIN_MODE_INPUT(GPIOD_PIN12) \ + | PIN_MODE_INPUT(GPIOD_PIN13) \ + | PIN_MODE_INPUT(GPIOD_PIN14) \ + | PIN_MODE_INPUT(GPIOD_PIN15) ) +#define VAL_GPIOD_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOD_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN11) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN12) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN13) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN14) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN15) ) + +#if !defined(_FROM_ASM_) +# ifdef __cplusplus +extern "C" { +# endif +void boardInit(void); +# ifdef __cplusplus +} +# endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/SN_SN32F240/board.mk b/os/hal/boards/SN_SN32F240/board.mk new file mode 100644 index 00000000..7b974dda --- /dev/null +++ b/os/hal/boards/SN_SN32F240/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F240B/board.c + +# Required include directories +BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F240B + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) \ No newline at end of file diff --git a/os/hal/boards/SN_SN32F240B/board.c b/os/hal/boards/SN_SN32F240B/board.c new file mode 100644 index 00000000..ccaf913c --- /dev/null +++ b/os/hal/boards/SN_SN32F240B/board.c @@ -0,0 +1,67 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = { + #if SN32_HAS_GPIOA + {.mode = VAL_GPIOA_MODE, .cfg = VAL_GPIOA_CFG}, + #endif + #if SN32_HAS_GPIOB + {.mode = VAL_GPIOB_MODE, .cfg = VAL_GPIOB_CFG}, + #endif + #if SN32_HAS_GPIOC + {.mode = VAL_GPIOC_MODE, .cfg = VAL_GPIOC_CFG}, + #endif + #if SN32_HAS_GPIOD + {.mode = VAL_GPIOD_MODE, .cfg = VAL_GPIOD_CFG}, + #endif +}; +#endif + +static int flag __attribute__((section(".flag"))) __attribute__((__used__)) = 0xAAAA5555; +extern void enter_bootloader_mode_if_requested(void); + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + enter_bootloader_mode_if_requested(); + sn32_clock_init(); +} + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { + + SN_SYS0->EXRSTCTRL_b.RESETDIS = 1; // Disable RESET + SN_SYS0->SWDCTRL_b.SWDDIS = 1; // Disable SWD +} diff --git a/os/hal/boards/SN_SN32F240B/board.h b/os/hal/boards/SN_SN32F240B/board.h new file mode 100644 index 00000000..5904811f --- /dev/null +++ b/os/hal/boards/SN_SN32F240B/board.h @@ -0,0 +1,250 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for Generic SN32F240B Board + */ + +/* + * Board identifier. + */ +#define BOARD_GENERIC_SN32_F240B +#define BOARD_NAME "SN32F240B" + +/* + * MCU type as defined in the SN32 header. + */ +#define SN32F240B + +/* + * IO pins assignments. + */ +#define GPIOA_PIN0 0U +#define GPIOA_PIN1 1U +#define GPIOA_PIN2 2U +#define GPIOA_PIN3 3U +#define GPIOA_PIN4 4U +#define GPIOA_PIN5 5U +#define GPIOA_PIN6 6U +#define GPIOA_PIN7 7U +#define GPIOA_PIN8 8U +#define GPIOA_PIN9 9U +#define GPIOA_PIN10 10U +#define GPIOA_PIN11 11U +#define GPIOA_PIN12 12U +#define GPIOA_PIN13 13U +#define GPIOA_PIN14 14U +#define GPIOA_PIN15 15U + +#define GPIOB_PIN0 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_PIN3 3U +#define GPIOB_PIN4 4U +#define GPIOB_PIN5 5U +#define GPIOB_PIN6 6U +#define GPIOB_PIN7 7U +#define GPIOB_PIN8 8U +#define GPIOB_PIN9 9U +#define GPIOB_PIN10 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_PIN13 13U +#define GPIOB_PIN14 14U +#define GPIOB_PIN15 15U + +#define GPIOC_PIN0 0U +#define GPIOC_PIN1 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_PIN7 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_PIN13 13U +#define GPIOC_PIN14 14U +#define GPIOC_PIN15 15U + +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the SN32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n))) +#define PIN_MODE_OUTPUT(n) (1U << ((n))) + +#define PIN_CFG_PULLUP(n) (0U << ((n*2))) // Pull-up +#define PIN_CFG_SCHMITT_EN(n) (2U << ((n*2))) // Floating +#define PIN_CFG_SCHMITT_DIS(n) (3U << ((n*2))) // Input buffer disconnected, alway read as zero. + +// Define GPIO register values used by pal_default_config. +// The following values match the chip reset values, all GPIO pins as floating inputs. + +#define VAL_GPIOA_MODE \ + ( PIN_MODE_INPUT(GPIOA_PIN0) \ + | PIN_MODE_INPUT(GPIOA_PIN1) \ + | PIN_MODE_INPUT(GPIOA_PIN2) \ + | PIN_MODE_INPUT(GPIOA_PIN3) \ + | PIN_MODE_INPUT(GPIOA_PIN4) \ + | PIN_MODE_INPUT(GPIOA_PIN5) \ + | PIN_MODE_INPUT(GPIOA_PIN6) \ + | PIN_MODE_INPUT(GPIOA_PIN7) \ + | PIN_MODE_INPUT(GPIOA_PIN8) \ + | PIN_MODE_INPUT(GPIOA_PIN9) \ + | PIN_MODE_INPUT(GPIOA_PIN10) \ + | PIN_MODE_INPUT(GPIOA_PIN11) \ + | PIN_MODE_INPUT(GPIOA_PIN12) \ + | PIN_MODE_INPUT(GPIOA_PIN13) \ + | PIN_MODE_INPUT(GPIOA_PIN14) \ + | PIN_MODE_INPUT(GPIOA_PIN15) ) +#define VAL_GPIOA_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOA_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN2) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN11) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN12) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN13) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN14) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN15) ) + +#define VAL_GPIOB_MODE \ + ( PIN_MODE_INPUT(GPIOB_PIN0) \ + | PIN_MODE_INPUT(GPIOB_PIN1) \ + | PIN_MODE_INPUT(GPIOB_PIN2) \ + | PIN_MODE_INPUT(GPIOB_PIN3) \ + | PIN_MODE_INPUT(GPIOB_PIN4) \ + | PIN_MODE_INPUT(GPIOB_PIN5) \ + | PIN_MODE_INPUT(GPIOB_PIN6) \ + | PIN_MODE_INPUT(GPIOB_PIN7) \ + | PIN_MODE_INPUT(GPIOB_PIN8) \ + | PIN_MODE_INPUT(GPIOB_PIN9) \ + | PIN_MODE_INPUT(GPIOB_PIN10) \ + | PIN_MODE_INPUT(GPIOB_PIN11) \ + | PIN_MODE_INPUT(GPIOB_PIN12) \ + | PIN_MODE_INPUT(GPIOB_PIN13) \ + | PIN_MODE_INPUT(GPIOB_PIN14) \ + | PIN_MODE_INPUT(GPIOB_PIN15) ) +#define VAL_GPIOB_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOB_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN2) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN11) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN12) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN13) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN14) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN15) ) + +#define VAL_GPIOC_MODE \ + ( PIN_MODE_INPUT(GPIOC_PIN0) \ + | PIN_MODE_INPUT(GPIOC_PIN1) \ + | PIN_MODE_INPUT(GPIOC_PIN2) \ + | PIN_MODE_INPUT(GPIOC_PIN3) \ + | PIN_MODE_INPUT(GPIOC_PIN4) \ + | PIN_MODE_INPUT(GPIOC_PIN5) \ + | PIN_MODE_INPUT(GPIOC_PIN6) \ + | PIN_MODE_INPUT(GPIOC_PIN7) \ + | PIN_MODE_INPUT(GPIOC_PIN8) \ + | PIN_MODE_INPUT(GPIOC_PIN9) \ + | PIN_MODE_INPUT(GPIOC_PIN10) \ + | PIN_MODE_INPUT(GPIOC_PIN11) \ + | PIN_MODE_INPUT(GPIOC_PIN12) \ + | PIN_MODE_INPUT(GPIOC_PIN13) \ + | PIN_MODE_INPUT(GPIOC_PIN14) \ + | PIN_MODE_INPUT(GPIOC_PIN15) ) +#define VAL_GPIOC_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOC_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN2) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN11) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN12) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN13) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN14) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN15) ) + +#define VAL_GPIOD_MODE \ + ( PIN_MODE_INPUT(GPIOD_PIN3) \ + | PIN_MODE_INPUT(GPIOD_PIN4) \ + | PIN_MODE_INPUT(GPIOD_PIN5) \ + | PIN_MODE_INPUT(GPIOD_PIN6) \ + | PIN_MODE_INPUT(GPIOD_PIN7) \ + | PIN_MODE_INPUT(GPIOD_PIN8) \ + | PIN_MODE_INPUT(GPIOD_PIN9) \ + | PIN_MODE_INPUT(GPIOD_PIN10) \ + | PIN_MODE_INPUT(GPIOD_PIN11) ) +#define VAL_GPIOD_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOD_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN11) ) + +#if !defined(_FROM_ASM_) +# ifdef __cplusplus +extern "C" { +# endif +void boardInit(void); +# ifdef __cplusplus +} +# endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/SN_SN32F240B/board.mk b/os/hal/boards/SN_SN32F240B/board.mk new file mode 100644 index 00000000..7b974dda --- /dev/null +++ b/os/hal/boards/SN_SN32F240B/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F240B/board.c + +# Required include directories +BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F240B + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) \ No newline at end of file diff --git a/os/hal/boards/SN_SN32F260/board.c b/os/hal/boards/SN_SN32F260/board.c new file mode 100644 index 00000000..72ad880c --- /dev/null +++ b/os/hal/boards/SN_SN32F260/board.c @@ -0,0 +1,60 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = { + #if SN32_HAS_GPIOA + {.mode = VAL_GPIOA_MODE, .cfg = VAL_GPIOA_CFG}, + #endif + #if SN32_HAS_GPIOB + {.mode = VAL_GPIOB_MODE, .cfg = VAL_GPIOB_CFG}, + #endif + #if SN32_HAS_GPIOC + {.mode = VAL_GPIOC_MODE, .cfg = VAL_GPIOC_CFG}, + #endif + #if SN32_HAS_GPIOD + {.mode = VAL_GPIOD_MODE, .cfg = VAL_GPIOD_CFG}, + #endif +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + sn32_clock_init(); +} + +/** + * @brief Board-specific initialization code. + */ +void boardInit(void) { + SN_SYS0->SWDCTRL_b.SWDDIS = 1; // Disable SWD +} diff --git a/os/hal/boards/SN_SN32F260/board.h b/os/hal/boards/SN_SN32F260/board.h new file mode 100644 index 00000000..cb347349 --- /dev/null +++ b/os/hal/boards/SN_SN32F260/board.h @@ -0,0 +1,205 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for Generic SN32F260 Board + */ + +/* + * Board identifier. + */ +#define BOARD_GENERIC_SN32_F260 +#define BOARD_NAME "SN32F260" + +/* + * MCU type as defined in the SN32 header. + */ +#define SN32F260 + +/* + * IO pins assignments. + */ +#define GPIOA_PIN0 0U +#define GPIOA_PIN1 1U +#define GPIOA_PIN2 2U +#define GPIOA_PIN3 3U +#define GPIOA_PIN4 4U +#define GPIOA_PIN5 5U +#define GPIOA_PIN6 6U +#define GPIOA_PIN7 7U +#define GPIOA_PIN8 8U +#define GPIOA_PIN9 9U +#define GPIOA_PIN10 10U +#define GPIOA_PIN11 11U +#define GPIOA_PIN12 12U +#define GPIOA_PIN13 13U +#define GPIOA_PIN14 14U +#define GPIOA_PIN15 15U + +#define GPIOB_PIN0 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_PIN3 3U +#define GPIOB_PIN4 4U +#define GPIOB_PIN5 5U + +#define GPIOC_PIN0 0U +#define GPIOC_PIN1 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_PIN7 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U + +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_PIN2 2U +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the SN32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n))) +#define PIN_MODE_OUTPUT(n) (1U << ((n))) + +#define PIN_CFG_PULLUP(n) (0U << ((n*2))) // Pull-up +#define PIN_CFG_SCHMITT_EN(n) (2U << ((n*2))) // Floating +#define PIN_CFG_SCHMITT_DIS(n) (3U << ((n*2))) // Input buffer disconnected, alway read as zero. + +// Define GPIO register values used by pal_default_config. +// The following values match the chip reset values, all GPIO pins as floating inputs. + +#define VAL_GPIOA_MODE \ + ( PIN_MODE_INPUT(GPIOA_PIN0) \ + | PIN_MODE_INPUT(GPIOA_PIN1) \ + | PIN_MODE_INPUT(GPIOA_PIN2) \ + | PIN_MODE_INPUT(GPIOA_PIN3) \ + | PIN_MODE_INPUT(GPIOA_PIN4) \ + | PIN_MODE_INPUT(GPIOA_PIN5) \ + | PIN_MODE_INPUT(GPIOA_PIN6) \ + | PIN_MODE_INPUT(GPIOA_PIN7) \ + | PIN_MODE_INPUT(GPIOA_PIN8) \ + | PIN_MODE_INPUT(GPIOA_PIN9) \ + | PIN_MODE_INPUT(GPIOA_PIN10) \ + | PIN_MODE_INPUT(GPIOA_PIN11) \ + | PIN_MODE_INPUT(GPIOA_PIN12) \ + | PIN_MODE_INPUT(GPIOA_PIN13) \ + | PIN_MODE_INPUT(GPIOA_PIN14) \ + | PIN_MODE_INPUT(GPIOA_PIN15) ) +#define VAL_GPIOA_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOA_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN2) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN11) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN12) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN13) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN14) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN15) ) + +#define VAL_GPIOB_MODE \ + ( PIN_MODE_INPUT(GPIOB_PIN0) \ + | PIN_MODE_INPUT(GPIOB_PIN1) \ + | PIN_MODE_INPUT(GPIOB_PIN2) \ + | PIN_MODE_INPUT(GPIOB_PIN3) \ + | PIN_MODE_INPUT(GPIOB_PIN4) \ + | PIN_MODE_INPUT(GPIOB_PIN5) ) +#define VAL_GPIOB_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOB_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN2) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN5) ) + +#define VAL_GPIOC_MODE \ + ( PIN_MODE_INPUT(GPIOC_PIN0) \ + | PIN_MODE_INPUT(GPIOC_PIN1) \ + | PIN_MODE_INPUT(GPIOC_PIN2) \ + | PIN_MODE_INPUT(GPIOC_PIN3) \ + | PIN_MODE_INPUT(GPIOC_PIN4) \ + | PIN_MODE_INPUT(GPIOC_PIN5) \ + | PIN_MODE_INPUT(GPIOC_PIN6) \ + | PIN_MODE_INPUT(GPIOC_PIN7) \ + | PIN_MODE_INPUT(GPIOC_PIN8) \ + | PIN_MODE_INPUT(GPIOC_PIN9) \ + | PIN_MODE_INPUT(GPIOC_PIN10) ) +#define VAL_GPIOC_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOC_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN2) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN10) ) + +#define VAL_GPIOD_MODE \ + ( PIN_MODE_INPUT(GPIOD_PIN0) \ + | PIN_MODE_INPUT(GPIOD_PIN1) \ + | PIN_MODE_INPUT(GPIOD_PIN2) \ + | PIN_MODE_INPUT(GPIOD_PIN3) \ + | PIN_MODE_INPUT(GPIOD_PIN4) \ + | PIN_MODE_INPUT(GPIOD_PIN5) \ + | PIN_MODE_INPUT(GPIOD_PIN6) \ + | PIN_MODE_INPUT(GPIOD_PIN7) \ + | PIN_MODE_INPUT(GPIOD_PIN8) ) +#define VAL_GPIOD_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOD_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN2) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN8) ) + +#if !defined(_FROM_ASM_) +# ifdef __cplusplus +extern "C" { +# endif +void boardInit(void); +# ifdef __cplusplus +} +# endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/SN_SN32F260/board.mk b/os/hal/boards/SN_SN32F260/board.mk new file mode 100644 index 00000000..6fae75f1 --- /dev/null +++ b/os/hal/boards/SN_SN32F260/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F260/board.c + +# Required include directories +BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F260 + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) \ No newline at end of file diff --git a/os/hal/boards/SN_SN32F280/board.c b/os/hal/boards/SN_SN32F280/board.c new file mode 100644 index 00000000..ccaf913c --- /dev/null +++ b/os/hal/boards/SN_SN32F280/board.c @@ -0,0 +1,67 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = { + #if SN32_HAS_GPIOA + {.mode = VAL_GPIOA_MODE, .cfg = VAL_GPIOA_CFG}, + #endif + #if SN32_HAS_GPIOB + {.mode = VAL_GPIOB_MODE, .cfg = VAL_GPIOB_CFG}, + #endif + #if SN32_HAS_GPIOC + {.mode = VAL_GPIOC_MODE, .cfg = VAL_GPIOC_CFG}, + #endif + #if SN32_HAS_GPIOD + {.mode = VAL_GPIOD_MODE, .cfg = VAL_GPIOD_CFG}, + #endif +}; +#endif + +static int flag __attribute__((section(".flag"))) __attribute__((__used__)) = 0xAAAA5555; +extern void enter_bootloader_mode_if_requested(void); + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + enter_bootloader_mode_if_requested(); + sn32_clock_init(); +} + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { + + SN_SYS0->EXRSTCTRL_b.RESETDIS = 1; // Disable RESET + SN_SYS0->SWDCTRL_b.SWDDIS = 1; // Disable SWD +} diff --git a/os/hal/boards/SN_SN32F280/board.h b/os/hal/boards/SN_SN32F280/board.h new file mode 100644 index 00000000..57eb0ab8 --- /dev/null +++ b/os/hal/boards/SN_SN32F280/board.h @@ -0,0 +1,296 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for Generic SN32F280 Board + */ + +/* + * Board identifier. + */ +#define BOARD_GENERIC_SN32_F240 +#define BOARD_NAME "SN32F280" + +/* + * MCU type as defined in the SN32 header. + */ +#define SN32F280 + +/* + * IO pins assignments. + */ +#define GPIOA_PIN0 0U +#define GPIOA_PIN1 1U +#define GPIOA_PIN2 2U +#define GPIOA_PIN3 3U +#define GPIOA_PIN4 4U +#define GPIOA_PIN5 5U +#define GPIOA_PIN6 6U +#define GPIOA_PIN7 7U +#define GPIOA_PIN8 8U +#define GPIOA_PIN9 9U +#define GPIOA_PIN10 10U +#define GPIOA_PIN11 11U +#define GPIOA_PIN12 12U +#define GPIOA_PIN13 13U +#define GPIOA_PIN14 14U +#define GPIOA_PIN15 15U +#define GPIOA_PIN16 16U +#define GPIOA_PIN17 17U +#define GPIOA_PIN18 18U +#define GPIOA_PIN19 19U + +#define GPIOB_PIN0 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_PIN3 3U +#define GPIOB_PIN4 4U +#define GPIOB_PIN5 5U +#define GPIOB_PIN6 6U +#define GPIOB_PIN7 7U +#define GPIOB_PIN8 8U +#define GPIOB_PIN9 9U +#define GPIOB_PIN10 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_PIN13 13U +#define GPIOB_PIN14 14U +#define GPIOB_PIN15 15U +#define GPIOB_PIN16 16U +#define GPIOB_PIN17 17U +#define GPIOB_PIN18 18U +#define GPIOB_PIN19 19U + +#define GPIOC_PIN0 0U +#define GPIOC_PIN1 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_PIN7 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_PIN13 13U +#define GPIOC_PIN14 14U +#define GPIOC_PIN15 15U + +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_PIN12 12U +#define GPIOD_PIN13 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U +#define GPIOD_PIN16 16U +#define GPIOD_PIN17 17U +#define GPIOD_PIN18 18U +#define GPIOD_PIN19 19U + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the SN32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n))) +#define PIN_MODE_OUTPUT(n) (1U << ((n))) + +#define PIN_CFG_PULLUP(n) (0U << ((n*2))) // Pull-up +#define PIN_CFG_SCHMITT_EN(n) (2U << ((n*2))) // Floating +#define PIN_CFG_SCHMITT_DIS(n) (3U << ((n*2))) // Input buffer disconnected, alway read as zero. + +// Define GPIO register values used by pal_default_config. +// The following values match the chip reset values, all GPIO pins as floating inputs. + +#define VAL_GPIOA_MODE \ + ( PIN_MODE_INPUT(GPIOA_PIN0) \ + | PIN_MODE_INPUT(GPIOA_PIN1) \ + | PIN_MODE_INPUT(GPIOA_PIN2) \ + | PIN_MODE_INPUT(GPIOA_PIN3) \ + | PIN_MODE_INPUT(GPIOA_PIN4) \ + | PIN_MODE_INPUT(GPIOA_PIN5) \ + | PIN_MODE_INPUT(GPIOA_PIN6) \ + | PIN_MODE_INPUT(GPIOA_PIN7) \ + | PIN_MODE_INPUT(GPIOA_PIN8) \ + | PIN_MODE_INPUT(GPIOA_PIN9) \ + | PIN_MODE_INPUT(GPIOA_PIN10) \ + | PIN_MODE_INPUT(GPIOA_PIN11) \ + | PIN_MODE_INPUT(GPIOA_PIN12) \ + | PIN_MODE_INPUT(GPIOA_PIN13) \ + | PIN_MODE_INPUT(GPIOA_PIN14) \ + | PIN_MODE_INPUT(GPIOA_PIN15) \ + | PIN_MODE_INPUT(GPIOA_PIN16) \ + | PIN_MODE_INPUT(GPIOA_PIN17) \ + | PIN_MODE_INPUT(GPIOA_PIN18) \ + | PIN_MODE_INPUT(GPIOA_PIN19) ) +#define VAL_GPIOA_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOA_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN2) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN11) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN12) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN13) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN14) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN15) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN16) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN17) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN18) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN19) ) + +#define VAL_GPIOB_MODE \ + ( PIN_MODE_INPUT(GPIOB_PIN0) \ + | PIN_MODE_INPUT(GPIOB_PIN1) \ + | PIN_MODE_INPUT(GPIOB_PIN2) \ + | PIN_MODE_INPUT(GPIOB_PIN3) \ + | PIN_MODE_INPUT(GPIOB_PIN4) \ + | PIN_MODE_INPUT(GPIOB_PIN5) \ + | PIN_MODE_INPUT(GPIOB_PIN6) \ + | PIN_MODE_INPUT(GPIOB_PIN7) \ + | PIN_MODE_INPUT(GPIOB_PIN8) \ + | PIN_MODE_INPUT(GPIOB_PIN9) \ + | PIN_MODE_INPUT(GPIOB_PIN10) \ + | PIN_MODE_INPUT(GPIOB_PIN11) \ + | PIN_MODE_INPUT(GPIOB_PIN12) \ + | PIN_MODE_INPUT(GPIOB_PIN13) \ + | PIN_MODE_INPUT(GPIOB_PIN14) \ + | PIN_MODE_INPUT(GPIOB_PIN15) \ + | PIN_MODE_INPUT(GPIOB_PIN16) \ + | PIN_MODE_INPUT(GPIOB_PIN17) \ + | PIN_MODE_INPUT(GPIOB_PIN18) \ + | PIN_MODE_INPUT(GPIOB_PIN19) ) +#define VAL_GPIOB_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOB_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN2) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN11) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN12) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN13) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN14) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN15) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN16) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN17) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN18) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN19) ) + +#define VAL_GPIOC_MODE \ + ( PIN_MODE_INPUT(GPIOC_PIN0) \ + | PIN_MODE_INPUT(GPIOC_PIN1) \ + | PIN_MODE_INPUT(GPIOC_PIN2) \ + | PIN_MODE_INPUT(GPIOC_PIN3) \ + | PIN_MODE_INPUT(GPIOC_PIN4) \ + | PIN_MODE_INPUT(GPIOC_PIN5) \ + | PIN_MODE_INPUT(GPIOC_PIN6) \ + | PIN_MODE_INPUT(GPIOC_PIN7) \ + | PIN_MODE_INPUT(GPIOC_PIN8) \ + | PIN_MODE_INPUT(GPIOC_PIN9) \ + | PIN_MODE_INPUT(GPIOC_PIN10) \ + | PIN_MODE_INPUT(GPIOC_PIN11) \ + | PIN_MODE_INPUT(GPIOC_PIN12) \ + | PIN_MODE_INPUT(GPIOC_PIN13) \ + | PIN_MODE_INPUT(GPIOC_PIN14) \ + | PIN_MODE_INPUT(GPIOC_PIN15) ) +#define VAL_GPIOC_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOC_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN2) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN11) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN12) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN13) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN14) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN15) ) + +#define VAL_GPIOD_MODE \ + ( PIN_MODE_INPUT(GPIOD_PIN3) \ + | PIN_MODE_INPUT(GPIOD_PIN4) \ + | PIN_MODE_INPUT(GPIOD_PIN5) \ + | PIN_MODE_INPUT(GPIOD_PIN6) \ + | PIN_MODE_INPUT(GPIOD_PIN7) \ + | PIN_MODE_INPUT(GPIOD_PIN8) \ + | PIN_MODE_INPUT(GPIOD_PIN9) \ + | PIN_MODE_INPUT(GPIOD_PIN10) \ + | PIN_MODE_INPUT(GPIOD_PIN11) \ + | PIN_MODE_INPUT(GPIOD_PIN12) \ + | PIN_MODE_INPUT(GPIOD_PIN13) \ + | PIN_MODE_INPUT(GPIOD_PIN14) \ + | PIN_MODE_INPUT(GPIOD_PIN15) \ + | PIN_MODE_INPUT(GPIOD_PIN16) \ + | PIN_MODE_INPUT(GPIOD_PIN17) \ + | PIN_MODE_INPUT(GPIOD_PIN18) \ + | PIN_MODE_INPUT(GPIOD_PIN19) ) +#define VAL_GPIOD_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOD_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN11) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN12) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN13) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN14) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN15) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN16) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN17) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN18) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN19) ) + +#if !defined(_FROM_ASM_) +# ifdef __cplusplus +extern "C" { +# endif +void boardInit(void); +# ifdef __cplusplus +} +# endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/SN_SN32F280/board.mk b/os/hal/boards/SN_SN32F280/board.mk new file mode 100644 index 00000000..67dba3f0 --- /dev/null +++ b/os/hal/boards/SN_SN32F280/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F280/board.c + +# Required include directories +BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F280 + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) \ No newline at end of file diff --git a/os/hal/boards/SN_SN32F290/board.c b/os/hal/boards/SN_SN32F290/board.c new file mode 100644 index 00000000..ccaf913c --- /dev/null +++ b/os/hal/boards/SN_SN32F290/board.c @@ -0,0 +1,67 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = { + #if SN32_HAS_GPIOA + {.mode = VAL_GPIOA_MODE, .cfg = VAL_GPIOA_CFG}, + #endif + #if SN32_HAS_GPIOB + {.mode = VAL_GPIOB_MODE, .cfg = VAL_GPIOB_CFG}, + #endif + #if SN32_HAS_GPIOC + {.mode = VAL_GPIOC_MODE, .cfg = VAL_GPIOC_CFG}, + #endif + #if SN32_HAS_GPIOD + {.mode = VAL_GPIOD_MODE, .cfg = VAL_GPIOD_CFG}, + #endif +}; +#endif + +static int flag __attribute__((section(".flag"))) __attribute__((__used__)) = 0xAAAA5555; +extern void enter_bootloader_mode_if_requested(void); + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + enter_bootloader_mode_if_requested(); + sn32_clock_init(); +} + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { + + SN_SYS0->EXRSTCTRL_b.RESETDIS = 1; // Disable RESET + SN_SYS0->SWDCTRL_b.SWDDIS = 1; // Disable SWD +} diff --git a/os/hal/boards/SN_SN32F290/board.h b/os/hal/boards/SN_SN32F290/board.h new file mode 100644 index 00000000..3a95eb7d --- /dev/null +++ b/os/hal/boards/SN_SN32F290/board.h @@ -0,0 +1,296 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for Generic SN32F290 Board + */ + +/* + * Board identifier. + */ +#define BOARD_GENERIC_SN32_F240 +#define BOARD_NAME "SN32F290" + +/* + * MCU type as defined in the SN32 header. + */ +#define SN32F290 + +/* + * IO pins assignments. + */ +#define GPIOA_PIN0 0U +#define GPIOA_PIN1 1U +#define GPIOA_PIN2 2U +#define GPIOA_PIN3 3U +#define GPIOA_PIN4 4U +#define GPIOA_PIN5 5U +#define GPIOA_PIN6 6U +#define GPIOA_PIN7 7U +#define GPIOA_PIN8 8U +#define GPIOA_PIN9 9U +#define GPIOA_PIN10 10U +#define GPIOA_PIN11 11U +#define GPIOA_PIN12 12U +#define GPIOA_PIN13 13U +#define GPIOA_PIN14 14U +#define GPIOA_PIN15 15U +#define GPIOA_PIN16 16U +#define GPIOA_PIN17 17U +#define GPIOA_PIN18 18U +#define GPIOA_PIN19 19U + +#define GPIOB_PIN0 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_PIN3 3U +#define GPIOB_PIN4 4U +#define GPIOB_PIN5 5U +#define GPIOB_PIN6 6U +#define GPIOB_PIN7 7U +#define GPIOB_PIN8 8U +#define GPIOB_PIN9 9U +#define GPIOB_PIN10 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_PIN13 13U +#define GPIOB_PIN14 14U +#define GPIOB_PIN15 15U +#define GPIOB_PIN16 16U +#define GPIOB_PIN17 17U +#define GPIOB_PIN18 18U +#define GPIOB_PIN19 19U + +#define GPIOC_PIN0 0U +#define GPIOC_PIN1 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_PIN7 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_PIN13 13U +#define GPIOC_PIN14 14U +#define GPIOC_PIN15 15U + +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_PIN12 12U +#define GPIOD_PIN13 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U +#define GPIOD_PIN16 16U +#define GPIOD_PIN17 17U +#define GPIOD_PIN18 18U +#define GPIOD_PIN19 19U + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the SN32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n))) +#define PIN_MODE_OUTPUT(n) (1U << ((n))) + +#define PIN_CFG_PULLUP(n) (0U << ((n*2))) // Pull-up +#define PIN_CFG_SCHMITT_EN(n) (2U << ((n*2))) // Floating +#define PIN_CFG_SCHMITT_DIS(n) (3U << ((n*2))) // Input buffer disconnected, alway read as zero. + +// Define GPIO register values used by pal_default_config. +// The following values match the chip reset values, all GPIO pins as floating inputs. + +#define VAL_GPIOA_MODE \ + ( PIN_MODE_INPUT(GPIOA_PIN0) \ + | PIN_MODE_INPUT(GPIOA_PIN1) \ + | PIN_MODE_INPUT(GPIOA_PIN2) \ + | PIN_MODE_INPUT(GPIOA_PIN3) \ + | PIN_MODE_INPUT(GPIOA_PIN4) \ + | PIN_MODE_INPUT(GPIOA_PIN5) \ + | PIN_MODE_INPUT(GPIOA_PIN6) \ + | PIN_MODE_INPUT(GPIOA_PIN7) \ + | PIN_MODE_INPUT(GPIOA_PIN8) \ + | PIN_MODE_INPUT(GPIOA_PIN9) \ + | PIN_MODE_INPUT(GPIOA_PIN10) \ + | PIN_MODE_INPUT(GPIOA_PIN11) \ + | PIN_MODE_INPUT(GPIOA_PIN12) \ + | PIN_MODE_INPUT(GPIOA_PIN13) \ + | PIN_MODE_INPUT(GPIOA_PIN14) \ + | PIN_MODE_INPUT(GPIOA_PIN15) \ + | PIN_MODE_INPUT(GPIOA_PIN16) \ + | PIN_MODE_INPUT(GPIOA_PIN17) \ + | PIN_MODE_INPUT(GPIOA_PIN18) \ + | PIN_MODE_INPUT(GPIOA_PIN19) ) +#define VAL_GPIOA_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOA_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN2) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN11) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN12) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN13) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN14) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN15) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN16) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN17) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN18) \ + | PIN_CFG_SCHMITT_EN(GPIOA_PIN19) ) + +#define VAL_GPIOB_MODE \ + ( PIN_MODE_INPUT(GPIOB_PIN0) \ + | PIN_MODE_INPUT(GPIOB_PIN1) \ + | PIN_MODE_INPUT(GPIOB_PIN2) \ + | PIN_MODE_INPUT(GPIOB_PIN3) \ + | PIN_MODE_INPUT(GPIOB_PIN4) \ + | PIN_MODE_INPUT(GPIOB_PIN5) \ + | PIN_MODE_INPUT(GPIOB_PIN6) \ + | PIN_MODE_INPUT(GPIOB_PIN7) \ + | PIN_MODE_INPUT(GPIOB_PIN8) \ + | PIN_MODE_INPUT(GPIOB_PIN9) \ + | PIN_MODE_INPUT(GPIOB_PIN10) \ + | PIN_MODE_INPUT(GPIOB_PIN11) \ + | PIN_MODE_INPUT(GPIOB_PIN12) \ + | PIN_MODE_INPUT(GPIOB_PIN13) \ + | PIN_MODE_INPUT(GPIOB_PIN14) \ + | PIN_MODE_INPUT(GPIOB_PIN15) \ + | PIN_MODE_INPUT(GPIOB_PIN16) \ + | PIN_MODE_INPUT(GPIOB_PIN17) \ + | PIN_MODE_INPUT(GPIOB_PIN18) \ + | PIN_MODE_INPUT(GPIOB_PIN19) ) +#define VAL_GPIOB_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOB_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN2) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN11) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN12) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN13) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN14) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN15) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN16) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN17) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN18) \ + | PIN_CFG_SCHMITT_EN(GPIOB_PIN19) ) + +#define VAL_GPIOC_MODE \ + ( PIN_MODE_INPUT(GPIOC_PIN0) \ + | PIN_MODE_INPUT(GPIOC_PIN1) \ + | PIN_MODE_INPUT(GPIOC_PIN2) \ + | PIN_MODE_INPUT(GPIOC_PIN3) \ + | PIN_MODE_INPUT(GPIOC_PIN4) \ + | PIN_MODE_INPUT(GPIOC_PIN5) \ + | PIN_MODE_INPUT(GPIOC_PIN6) \ + | PIN_MODE_INPUT(GPIOC_PIN7) \ + | PIN_MODE_INPUT(GPIOC_PIN8) \ + | PIN_MODE_INPUT(GPIOC_PIN9) \ + | PIN_MODE_INPUT(GPIOC_PIN10) \ + | PIN_MODE_INPUT(GPIOC_PIN11) \ + | PIN_MODE_INPUT(GPIOC_PIN12) \ + | PIN_MODE_INPUT(GPIOC_PIN13) \ + | PIN_MODE_INPUT(GPIOC_PIN14) \ + | PIN_MODE_INPUT(GPIOC_PIN15) ) +#define VAL_GPIOC_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOC_PIN0) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN1) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN2) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN11) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN12) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN13) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN14) \ + | PIN_CFG_SCHMITT_EN(GPIOC_PIN15) ) + +#define VAL_GPIOD_MODE \ + ( PIN_MODE_INPUT(GPIOD_PIN3) \ + | PIN_MODE_INPUT(GPIOD_PIN4) \ + | PIN_MODE_INPUT(GPIOD_PIN5) \ + | PIN_MODE_INPUT(GPIOD_PIN6) \ + | PIN_MODE_INPUT(GPIOD_PIN7) \ + | PIN_MODE_INPUT(GPIOD_PIN8) \ + | PIN_MODE_INPUT(GPIOD_PIN9) \ + | PIN_MODE_INPUT(GPIOD_PIN10) \ + | PIN_MODE_INPUT(GPIOD_PIN11) \ + | PIN_MODE_INPUT(GPIOD_PIN12) \ + | PIN_MODE_INPUT(GPIOD_PIN13) \ + | PIN_MODE_INPUT(GPIOD_PIN14) \ + | PIN_MODE_INPUT(GPIOD_PIN15) \ + | PIN_MODE_INPUT(GPIOD_PIN16) \ + | PIN_MODE_INPUT(GPIOD_PIN17) \ + | PIN_MODE_INPUT(GPIOD_PIN18) \ + | PIN_MODE_INPUT(GPIOD_PIN19) ) +#define VAL_GPIOD_CFG \ + ( PIN_CFG_SCHMITT_EN(GPIOD_PIN3) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN4) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN5) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN6) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN7) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN8) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN9) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN10) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN11) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN12) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN13) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN14) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN15) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN16) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN17) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN18) \ + | PIN_CFG_SCHMITT_EN(GPIOD_PIN19) ) + +#if !defined(_FROM_ASM_) +# ifdef __cplusplus +extern "C" { +# endif +void boardInit(void); +# ifdef __cplusplus +} +# endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/SN_SN32F290/board.mk b/os/hal/boards/SN_SN32F290/board.mk new file mode 100644 index 00000000..2dd4916b --- /dev/null +++ b/os/hal/boards/SN_SN32F290/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F290/board.c + +# Required include directories +BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F290 + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F24x/ADC/ADC.c b/os/hal/ports/SN32/LLD/SN32F24x/ADC/ADC.c new file mode 100644 index 00000000..a87f2152 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/ADC/ADC.c @@ -0,0 +1,142 @@ +/******************** (C) COPYRIGHT 2013 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2013/12 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: ADC related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include +#include "ADC.h" +#include "..\..\Utility\Utility.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +uint8_t bADC_StartConv; + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + +/***************************************************************************** +* Function : ADC_Init +* Description : Initialization of ADC +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void ADC_Init(void) +{ + SN_SYS1->AHBCLKEN |= (0x01 << 11); //Enables HCLK for ADC + + //Set ADC PCLK + SN_SYS1->APBCP0 |= (0x00 << 16); //ADC PCLK = HCLK/1 + //SN_SYS1->APBCP0 |= (0x01 << 16); //ADC PCLK = HCLK/2 + //SN_SYS1->APBCP0 |= (0x02 << 16); //ADC PCLK = HCLK/4 + //SN_SYS1->APBCP0 |= (0x03 << 16); //ADC PCLK = HCLK/8 + //SN_SYS1->APBCP0 |= (0x04 << 16); //ADC PCLK = HCLK/16 + + SN_ADC->ADM_b.ADENB = ADC_ADENB_EN; //Enable ADC + + UT_DelayNx10us(10); //Delay 100us + + SN_ADC->ADM_b.AVREFHSEL = ADC_AVREFHSEL_INTERNAL; //Set ADC high reference voltage source from internal VDD + + SN_ADC->ADM_b.GCHS = ADC_GCHS_EN; //Enable ADC global channel + + SN_ADC->ADM_b.ADLEN = ADC_ADLEN_12BIT; //Set ADC resolution = 12-bit + + SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV32; //ADC_CLK = ADC_PCLK/32 + + #if ADC_FUNCTION_TYPE == ADC_TYPE + + SN_ADC->ADM_b.CHS = ADC_CHS_AIN1; //Set P2.1 as ADC input channel + + SN_ADC->IE |= ADC_IE_AIN1; //Enable ADC channel P2.1 interrupt + + #endif + + #if ADC_FUNCTION_TYPE == TS_TYPE + + SN_ADC->ADM_b.TSENB = ADC_TSENB_EN; //Enable Temperature Sensor + SN_ADC->ADM_b.CHS = ADC_CHS_TS; //Set P2.14 as Temperature Sensor channel + SN_ADC->IE |= ADC_IE_TS; //Enable Temperature Sensor interrupt + + #endif + + ADC_NvicEnable(); //Enable ADC NVIC interrupt +} + +/***************************************************************************** +* Function : ADC_Read +* Description : Read ADC converted data +* Input : None +* Output : None +* Return : Data in ADB register +* Note : None +*****************************************************************************/ +uint16_t ADC_Read(void) +{ + return SN_ADC->ADB; +} + +/***************************************************************************** +* Function : ADC_IRQHandler +* Description : ISR of ADC interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void ADC_IRQHandler(void) +{ + bADC_StartConv = 0; + + SN_ADC->RIS = 0x0; //clear interrupt flag +} + +/***************************************************************************** +* Function : ADC_NvicEnable +* Description : Enable ADC interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void ADC_NvicEnable(void) +{ + NVIC_ClearPendingIRQ(ADC_IRQn); + NVIC_EnableIRQ(ADC_IRQn); + NVIC_SetPriority(ADC_IRQn,0); // Set interrupt priority (default) +} + +/***************************************************************************** +* Function : ADC_NvicDisable +* Description : Disable ADC interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void ADC_NvicDisable(void) +{ + NVIC_DisableIRQ(ADC_IRQn); +} diff --git a/os/hal/ports/SN32/LLD/SN32F24x/ADC/ADC.h b/os/hal/ports/SN32/LLD/SN32F24x/ADC/ADC.h new file mode 100644 index 00000000..85c71683 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/ADC/ADC.h @@ -0,0 +1,109 @@ +#ifndef __SN32F240_ADC_H +#define __SN32F240_ADC_H + +/*_____ I N C L U D E S ____________________________________________________*/ +#include + +/*_____ D E F I N I T I O N S ______________________________________________*/ +//ADC function Type +#define ADC_FUNCTION_TYPE ADC_TYPE //ADC_TYPE, TS_TYPE +#define ADC_TYPE 0 //ADC function +#define TS_TYPE 1 //Temperature Sensor function + +//Temperature sensor enable bit +#define ADC_TSENB_DIS 0x0 +#define ADC_TSENB_EN 0x1 + +//ADC high reference voltage source select bit +#define ADC_AVREFHSEL_INTERNAL 0x0 +#define ADC_AVREFHSEL_EXTERNAL 0x1 + +//ADC Enable bit +#define ADC_ADENB_DIS 0x0 +#define ADC_ADENB_EN 0x1 + +//ADC Clock source divider +#define ADC_ADCKS_DIV1 0x0 +#define ADC_ADCKS_DIV2 0x1 +#define ADC_ADCKS_DIV4 0x2 +#define ADC_ADCKS_DIV8 0x3 +#define ADC_ADCKS_DIV16 0x5 +#define ADC_ADCKS_DIV32 0x6 + +//ADC resolution control bit +#define ADC_ADLEN_8BIT 0x0 +#define ADC_ADLEN_12BIT 0x1 + +//ADC start control bit +#define ADC_ADS_STOP 0x0 +#define ADC_ADS_START 0x1 + +//ADC global channel select bit +#define ADC_GCHS_DIS 0x0 +#define ADC_GCHS_EN 0x1 + +//ADC input channels select bit +#define ADC_CHS_AIN0 0x0 //P2.0 +#define ADC_CHS_AIN1 0x1 //P2.1 +#define ADC_CHS_AIN2 0x2 //P2.2 +#define ADC_CHS_AIN3 0x3 //P2.3 +#define ADC_CHS_AIN4 0x4 //P2.4 +#define ADC_CHS_AIN5 0x5 //P2.5 +#define ADC_CHS_AIN6 0x6 //P2.6 +#define ADC_CHS_AIN7 0x7 //P2.7 +#define ADC_CHS_AIN8 0x8 //P2.8 +#define ADC_CHS_AIN9 0x9 //P2.9 +#define ADC_CHS_AIN10 0xA //P2.10 +#define ADC_CHS_AIN11 0xB //P2.11 +#define ADC_CHS_AIN12 0xC //P2.12 +#define ADC_CHS_AIN13 0xD //P2.13 +#define ADC_CHS_TS 0xE //Temperature Sensor + +//ADC Interrupt Enable register(ADC_IE) +#define ADC_IE_AIN0 0x0001 +#define ADC_IE_AIN1 0x0002 +#define ADC_IE_AIN2 0x0004 +#define ADC_IE_AIN3 0x0008 +#define ADC_IE_AIN4 0x0010 +#define ADC_IE_AIN5 0x0020 +#define ADC_IE_AIN6 0x0040 +#define ADC_IE_AIN7 0x0080 +#define ADC_IE_AIN8 0x0100 +#define ADC_IE_AIN9 0x0200 +#define ADC_IE_AIN10 0x0400 +#define ADC_IE_AIN11 0x0800 +#define ADC_IE_AIN12 0x1000 +#define ADC_IE_AIN13 0x2000 +#define ADC_IE_TS 0x4000 + + +//ADC Raw Interrupt Status register(ADC_RIS) +#define mskADC_IF_AIN0 (0x1<<0) //P2.0 +#define mskADC_IF_AIN1 (0x1<<1) //P2.1 +#define mskADC_IF_AIN2 (0x1<<2) //P2.2 +#define mskADC_IF_AIN3 (0x1<<3) //P2.3 +#define mskADC_IF_AIN4 (0x1<<4) //P2.4 +#define mskADC_IF_AIN5 (0x1<<5) //P2.5 +#define mskADC_IF_AIN6 (0x1<<6) //P2.6 +#define mskADC_IF_AIN7 (0x1<<7) //P2.7 +#define mskADC_IF_AIN8 (0x1<<8) //P2.8 +#define mskADC_IF_AIN9 (0x1<<9) //P2.9 +#define mskADC_IF_AIN10 (0x1<<10) //P2.10 +#define mskADC_IF_AIN11 (0x1<<11) //P2.11 +#define mskADC_IF_AIN12 (0x1<<12) //P2.12 +#define mskADC_IF_AIN13 (0x1<<13) //P2.13 +#define mskADC_IF_TS (0x1<<14) //Temperature Sensor + +/*_____ M A C R O S ________________________________________________________*/ + + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +extern uint8_t bADC_StartConv; + +void ADC_Init(void); +uint16_t ADC_Read(void); +void ADC_NvicEnable(void); +void ADC_NvicDisable(void); + +#endif /*__SN32F240_ADC_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16.h b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16.h new file mode 100644 index 00000000..9fc2dd48 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16.h @@ -0,0 +1,259 @@ +#ifndef __SN32F240_CT16_H +#define __SN32F240_CT16_H + + +/*_____ I N C L U D E S ____________________________________________________*/ + +/*_____ D E F I N I T I O N S ______________________________________________*/ +/* +Base Address: 0x4000 0000 (CT16B0) + 0x4000 2000 (CT16B1) + 0x4000 4000 (CT16B2) +*/ + +/* CT16Bn Timer Control register (0x00) */ +#define CT16_CEN_DIS 0 //[0:0] CT16Bn enable bit +#define CT16_CEN_EN 1 +#define mskCT16_CEN_DIS (CT16_CEN_DIS<<0) +#define mskCT16_CEN_EN (CT16_CEN_EN<<0) + +#define CT16_CRST 1 //[1:1] CT16Bn counter reset bit +#define mskCT16_CRST (CT16_CRST<<1) + + //[6:4] CT16Bn counting mode selection +#define CT16_CM_EDGE_UP 0 //Edge-aligned Up-counting mode +#define CT16_CM_EDGE_DOWN 1 //Edge-aligned Down-counting mode +#define CT16_CM_CENTER_UP 2 //Center-aligned mode 1. Match interrupt is set during up-counting period +#define CT16_CM_CENTER_DOWN 4 //Center-aligned mode 2. Match interrupt is set during down-counting period +#define CT16_CM_CENTER_BOTH 6 //Center-aligned mode 3. Match interrupt is set during both up and down period. +#define mskCT16_CM_EDGE_UP (CT16_CM_EDGE_UP<<4) +#define mskCT16_CM_EDGE_DOWN (CT16_CM_EDGE_DOWN<<4) +#define mskCT16_CM_CENTER_UP (CT16_CM_CENTER_UP<<4) +#define mskCT16_CM_CENTER_DOWN (CT16_CM_CENTER_DOWN<<4) +#define mskCT16_CM_CENTER_BOTH (CT16_CM_CENTER_BOTH<<4) + +/* CT16Bn Count Control register (0x10) */ + //[1:0] Count/Timer Mode selection. +#define CT16_CTM_TIMER 0 //Timer mode: Every rising PCLK edge. +#define CT16_CTM_CNTER_RISING 1 //Counter mode: TC increments on rising edge of CAP input. +#define CT16_CTM_CNTER_FALLING 2 //Counter mode: TC increments on falling edge of CAP input. +#define CT16_CTM_CNTER_BOTH 3 //Counter mode: TC increments on both edge of CAP input. +#define mskCT16_CTM_TIMER (CT16_CTM_TIMER<<0) +#define mskCT16_CTM_CNTER_RISING (CT16_CTM_CNTER_RISING<<0) +#define mskCT16_CTM_CNTER_FALLING (CT16_CTM_CNTER_FALLING<<0) +#define mskCT16_CTM_CNTER_BOTH (CT16_CTM_CNTER_BOTH<<0) + +#define CT16_CIS 0 //[3:2] Count Input Select +#define mskCT16_CIS (CT16_CIS<<2) + +/* CT16Bn Match Control register (0x14) */ +#define CT16_MR0IE_EN 1 //[0:0] Enable MR0 match interrupt +#define CT16_MR0IE_DIS 0 +#define mskCT16_MR0IE_EN (CT16_MR0IE_EN<<0) +#define mskCT16_MR0IE_DIS (CT16_MR0IE_DIS<<0) + +#define CT16_MR0RST_EN 1 //[1:1] Enable reset TC when MR0 matches TC. +#define CT16_MR0RST_DIS 0 +#define mskCT16_MR0RST_EN (CT16_MR0RST_EN<<1) +#define mskCT16_MR0RST_DIS (CT16_MR0RST_DIS<<1) + +#define CT16_MR0STOP_EN 1 //[2:2] Enable stop TC and clear CEN when MR0 matches TC. +#define CT16_MR0STOP_DIS 0 +#define mskCT16_MR0STOP_EN (CT16_MR0STOP_EN<<2) +#define mskCT16_MR0STOP_DIS (CT16_MR0STOP_DIS<<2) + +#define CT16_MR1IE_EN 1 //[3:3] Enable MR1 match interrupt +#define CT16_MR1IE_DIS 0 +#define mskCT16_MR1IE_EN (CT16_MR1IE_EN<<3) +#define mskCT16_MR1IE_DIS (CT16_MR1IE_DIS<<3) + +#define CT16_MR1RST_EN 1 //[4:4] Enable reset TC when MR1 matches TC. +#define CT16_MR1RST_DIS 0 +#define mskCT16_MR1RST_EN (CT16_MR1RST_EN<<4) +#define mskCT16_MR1RST_DIS (CT16_MR1RST_DIS<<4) + +#define CT16_MR1STOP_EN 1 //[5:5] Enable stop TC and clear CEN when MR1 matches TC. +#define CT16_MR1STOP_DIS 0 +#define mskCT16_MR1STOP_EN (CT16_MR1STOP_EN<<5) +#define mskCT16_MR1STOP_DIS (CT16_MR1STOP_DIS<<5) + +#define CT16_MR2IE_EN 1 //[6:6] Enable MR2 match interrupt +#define CT16_MR2IE_DIS 0 +#define mskCT16_MR2IE_EN (CT16_MR2IE_EN<<6) +#define mskCT16_MR2IE_DIS (CT16_MR2IE_DIS<<6) + +#define CT16_MR2RST_EN 1 //[7:7] Enable reset TC when MR2 matches TC. +#define CT16_MR2RST_DIS 0 +#define mskCT16_MR2RST_EN (CT16_MR2RST_EN<<7) +#define mskCT16_MR2RST_DIS (CT16_MR2RST_DIS<<7) + +#define CT16_MR2STOP_EN 1 //[8:8] Enable stop TC and clear CEN when MR2 matches TC. +#define CT16_MR2STOP_DIS 0 +#define mskCT16_MR2STOP_EN (CT16_MR2STOP_EN<<8) +#define mskCT16_MR2STOP_DIS (CT16_MR2STOP_DIS<<8) + +#define CT16_MR3IE_EN 1 //[9:9] Enable MR3 match interrupt +#define CT16_MR3IE_DIS 0 +#define mskCT16_MR3IE_EN (CT16_MR3IE_EN<<9) +#define mskCT16_MR3IE_DIS (CT16_MR3IE_DIS<<9) + +#define CT16_MR3RST_EN 1 //[10:10] Enable reset TC when MR3 matches TC. +#define CT16_MR3RST_DIS 0 +#define mskCT16_MR3RST_EN (CT16_MR3RST_EN<<10) +#define mskCT16_MR3RST_DIS (CT16_MR3RST_DIS<<10) + +#define CT16_MR3STOP_EN 1 //[11:11] Enable stop TC and clear CEN when MR3 matches TC. +#define CT16_MR3STOP_DIS 0 +#define mskCT16_MR3STOP_EN (CT16_MR3STOP_EN<<11) +#define mskCT16_MR3STOP_DIS (CT16_MR3STOP_DIS<<11) + +/* CT16Bn Capture Control register (0x28) */ +#define CT16_CAP0RE_EN 1 //[0:0] Enable CAP0 capture on rising edge. +#define CT16_CAP0RE_DIS 0 +#define mskCT16_CAP0RE_EN (CT16_CAP0RE_EN<<0) +#define mskCT16_CAP0RE_DIS (CT16_CAP0RE_DIS<<0) + +#define CT16_CAP0FE_EN 1 //[1:1] Enable CAP0 capture on fallng edge. +#define CT16_CAP0FE_DIS 0 +#define mskCT16_CAP0FE_EN (CT16_CAP0FE_EN<<1) +#define mskCT16_CAP0FE_DIS (CT16_CAP0FE_DIS<<1) + +#define CT16_CAP0IE_EN 1 //[2:2] Enable CAP0 interrupt. +#define CT16_CAP0IE_DIS 0 +#define mskCT16_CAP0IE_EN (CT16_CAP0IE_EN<<2) +#define mskCT16_CAP0IE_DIS (CT16_CAP0IE_DIS<<2) + +#define CT16_CAP0EN_EN 1 //[3:3] Enable CAP0 function. +#define CT16_CAP0EN_DIS 0 +#define mskCT16_CAP0EN_EN (CT16_CAP0EN_EN<<3) +#define mskCT16_CAP0EN_DIS (CT16_CAP0EN_DIS<<3) + +/* CT16Bn External Match register (0x30) */ +#define CT16_EM0 1 //[0:0] CT16Bn PWM0 drive state +#define mskCT16_EM0 (CT16_EM0<<0) +#define CT16_EM1 1 //[1:1] CT16Bn PWM1 drive state +#define mskCT16_EM1 (CT16_EM1<<1) +#define CT16_EM2 1 //[2:2] CT16Bn PWM2 drive state +#define mskCT16_EM2 (CT16_EM2<<2) + + + //[5:4] CT16Bn PWM0 functionality +#define CT16_EMC0_DO_NOTHING 0 //Do nothing. +#define CT16_EMC0_LOW 1 //CT16Bn PWM0 pin is low. +#define CT16_EMC0_HIGH 2 //CT16Bn PWM0 pin is high. +#define CT16_EMC0_TOGGLE 3 //Toggle CT16Bn PWM0 pin. +#define mskCT16_EMC0_DO_NOTHING (CT16_EMC0_LOW<<4) +#define mskCT16_EMC0_LOW (CT16_EMC0_LOW<<4) +#define mskCT16_EMC0_HIGH (CT16_EMC0_HIGH<<4) +#define mskCT16_EMC0_TOGGLE (CT16_EMC0_TOGGLE<<4) + + //[7:6] CT16Bn PWM1 functionality +#define CT16_EMC1_DO_NOTHING 0 //Do nothing. +#define CT16_EMC1_LOW 1 //CT16Bn PWM1 pin is low. +#define CT16_EMC1_HIGH 2 //CT16Bn PWM1 pin is high. +#define CT16_EMC1_TOGGLE 3 //Toggle CT16Bn PWM1 pin. +#define mskCT16_EMC1_DO_NOTHING (CT16_EMC1_LOW<<6) +#define mskCT16_EMC1_LOW (CT16_EMC1_LOW<<6) +#define mskCT16_EMC1_HIGH (CT16_EMC1_HIGH<<6) +#define mskCT16_EMC1_TOGGLE (CT16_EMC1_TOGGLE<<6) + + //[9:8] CT16Bn PWM2 functionality +#define CT16_EMC2_DO_NOTHING 0 //Do nothing. +#define CT16_EMC2_LOW 1 //CT16Bn PWM2 pin is low. +#define CT16_EMC2_HIGH 2 //CT16Bn PWM2 pin is high. +#define CT16_EMC2_TOGGLE 3 //Toggle CT16Bn PWM2 pin. +#define mskCT16_EMC2_DO_NOTHING (CT16_EMC2_LOW<<8) +#define mskCT16_EMC2_LOW (CT16_EMC2_LOW<<8) +#define mskCT16_EMC2_HIGH (CT16_EMC2_HIGH<<8) +#define mskCT16_EMC2_TOGGLE (CT16_EMC2_TOGGLE<<8) + + +/* CT16Bn PWM Control register (0x34) */ + //[0:0] CT16Bn PWM0 enable. +#define CT16_PWM0EN_EN 1 // CT16Bn PWM0 is enabled for PWM mode. +#define CT16_PWM0EN_EM0 0 // CT16Bn PWM0 is controlled by EM0. +#define mskCT16_PWM0EN_EN (CT16_PWM0EN_EN<<0) +#define mskCT16_PWM0EN_EM0 (CT16_PWM0EN_EM0<<0) + + //[1:1] CT16Bn PWM1 enable. +#define CT16_PWM1EN_EN 1 // CT16Bn PWM1 is enabled for PWM mode. +#define CT16_PWM1EN_EM1 0 // CT16Bn PWM1 is controlled by EM1. +#define mskCT16_PWM1EN_EN (CT16_PWM1EN_EN<<1) +#define mskCT16_PWM1EN_EM1 (CT16_PWM1EN_EM1<<1) + + //[2:2] CT16Bn PWM2 enable. +#define CT16_PWM2EN_EN 1 // CT16Bn PWM2 is enabled for PWM mode. +#define CT16_PWM2EN_EM2 0 // CT16Bn PWM2 is controlled by EM2. +#define mskCT16_PWM2EN_EN (CT16_PWM2EN_EN<<2) +#define mskCT16_PWM2EN_EM2 (CT16_PWM2EN_EM2<<2) + + //[5:4] CT16Bn PWM0 output mode. +#define CT16_PWM0MODE_1 0 // PWM mode 1. +#define CT16_PWM0MODE_2 1 // PWM mode 2. +#define CT16_PWM0MODE_FORCE_0 2 // Force 0. +#define CT16_PWM0MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM0MODE_1 (CT16_PWM0MODE_1<<4) +#define mskCT16_PWM0MODE_2 (CT16_PWM0MODE_2<<4) +#define mskCT16_PWM0MODE_FORCE_0 (CT16_PWM0MODE_FORCE_0<<4) +#define mskCT16_PWM0MODE_FORCE_1 (CT16_PWM0MODE_FORCE_1<<4) + + //[7:6] CT16Bn PWM1 output mode. +#define CT16_PWM1MODE_1 0 // PWM mode 1. +#define CT16_PWM1MODE_2 1 // PWM mode 2. +#define CT16_PWM1MODE_FORCE_0 2 // Force 0. +#define CT16_PWM1MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM1MODE_1 (CT16_PWM1MODE_1<<6) +#define mskCT16_PWM1MODE_2 (CT16_PWM1MODE_2<<6) +#define mskCT16_PWM1MODE_FORCE_0 (CT16_PWM1MODE_FORCE_0<<6) +#define mskCT16_PWM1MODE_FORCE_1 (CT16_PWM1MODE_FORCE_1<<6) + + //[9:8] CT16Bn PWM2 output mode. +#define CT16_PWM2MODE_1 0 // PWM mode 1. +#define CT16_PWM2MODE_2 1 // PWM mode 2. +#define CT16_PWM2MODE_FORCE_0 2 // Force 0. +#define CT16_PWM2MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM2MODE_1 (CT16_PWM2MODE_1<<8) +#define mskCT16_PWM2MODE_2 (CT16_PWM2MODE_2<<8) +#define mskCT16_PWM2MODE_FORCE_0 (CT16_PWM2MODE_FORCE_0<<8) +#define mskCT16_PWM2MODE_FORCE_1 (CT16_PWM2MODE_FORCE_1<<8) + + //[20:20] CT16Bn PWM0 IO selection. +#define CT16_PWM0IOEN_EN 1 // PWM 0 pin acts as match output. +#define CT16_PWM0IOEN_DIS 0 // PWM 0 pin acts as GPIO. +#define mskCT16_PWM0IOEN_EN (CT16_PWM0IOEN_EN<<20) +#define mskCT16_PWM0IOEN_DIS (CT16_PWM0IOEN_DIS<<20) + + //[21:21] CT16Bn PWM1 IO selection. +#define CT16_PWM1IOEN_EN 1 // PWM 1 pin acts as match output. +#define CT16_PWM1IOEN_DIS 0 // PWM 1 pin acts as GPIO. +#define mskCT16_PWM1IOEN_EN (CT16_PWM1IOEN_EN<<21) +#define mskCT16_PWM1IOEN_DIS (CT16_PWM1IOEN_DIS<<21) + + //[22:22] CT16Bn PWM2 IO selection. +#define CT16_PWM2IOEN_EN 1 // PWM 2 pin acts as match output. +#define CT16_PWM2IOEN_DIS 0 // PWM 2 pin acts as GPIO. +#define mskCT16_PWM2IOEN_EN (CT16_PWM2IOEN_EN<<22) +#define mskCT16_PWM2IOEN_DIS (CT16_PWM2IOEN_DIS<<22) + + +/* CT16Bn Timer Raw Interrupt Status register (0x38) */ +/* CT16Bn Timer Interrupt Clear register (0x3C) */ +/* The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS*/ +#define mskCT16_MR0IF (0x1<<0) //[0:0] Interrupt flag for match channel 0 +#define mskCT16_MR0IC mskCT16_MR0IF +#define mskCT16_MR1IF (0x1<<1) //[1:1] Interrupt flag for match channel 1 +#define mskCT16_MR1IC mskCT16_MR1IF +#define mskCT16_MR2IF (0x1<<2) //[2:2] Interrupt flag for match channel 2 +#define mskCT16_MR2IC mskCT16_MR2IF +#define mskCT16_MR3IF (0x1<<3) //[3:3] Interrupt flag for match channel 3 +#define mskCT16_MR3IC mskCT16_MR3IF +#define mskCT16_CAP0IF (0x1<<4) //[4:4] Interrupt flag for capture channel 0 +#define mskCT16_CAP0IC mskCT16_CAP0IF + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + +#endif /*__SN32F240_CT16_H*/ + diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B0.c b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B0.c new file mode 100644 index 00000000..c91c8e87 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B0.c @@ -0,0 +1,160 @@ +/******************** (C) COPYRIGHT 2013 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2013/12 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: CT16B0 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include "CT16.h" +#include "CT16B0.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +volatile uint32_t iwCT16B0_IrqEvent = 0x00; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS + +void CT16B0_Init (void); +void CT16B0_NvicEnable (void); +void CT16B0_NvicDisable (void); + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ +/***************************************************************************** +* Function : CT16B0_Init +* Description : Initialization of CT16B0 timer +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B0_Init (void) +{ + //Enable P_CLOCK for CT16B0. + __CT16B0_ENABLE; + + //CT16B0 PCLK prescalar setting + SN_SYS1->APBCP0_b.CT16B0PRE = 0x00; //PCLK = HCLK/1 + //SN_SYS1->APBCP0_b.CT16B0PRE = 0x01; //PCLK = HCLK/2 + //SN_SYS1->APBCP0_b.CT16B0PRE = 0x02; //PCLK = HCLK/4 + //SN_SYS1->APBCP0_b.CT16B0PRE = 0x03; //PCLK = HCLK/8 + //SN_SYS1->APBCP0_b.CT16B0PRE = 0x04; //PCLK = HCLK/16 +} + +/***************************************************************************** +* Function : CT16B0_NvicEnable +* Description : Enable CT16B0 timer interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B0_NvicEnable (void) +{ + NVIC_ClearPendingIRQ(CT16B0_IRQn); + NVIC_EnableIRQ(CT16B0_IRQn); + //NVIC_SetPriority(CT16B0_IRQn,0); // Set interrupt priority (default) +} + +/***************************************************************************** +* Function : CT16B0_NvicEnable +* Description : Disable CT16B0 timer interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B0_NvicDisable (void) +{ + NVIC_DisableIRQ(CT16B0_IRQn); +} + + + +/***************************************************************************** +* Function : CT16B0_IRQHandler +* Description : ISR of CT16B0 interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B0_IRQHandler(void) +{ + uint32_t iwRisStatus; + + iwRisStatus = SN_CT16B0->RIS; //Save the interrupt status. + + //Before checking the status, always re-check the interrupt enable register first. + //In practice, user might use only one or two timer interrupt source. + //Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary. + //User can add the directive pair of "#if 0" and "#endif" pair + //to COMMENT the un-used parts to reduce ISR overheads and ROM usage. + + //Check the status in oder. + //MR0 + if (SN_CT16B0->MCTRL_b.MR0IE) //Check if MR0 IE enables? + { + if(iwRisStatus & mskCT16_MR0IF) + { + iwCT16B0_IrqEvent |= mskCT16_MR0IF; + SN_CT16B0->IC = mskCT16_MR0IC; //Clear MR0 match interrupt status + } + } + //MR1 + if (SN_CT16B0->MCTRL_b.MR1IE) //Check if MR1 IE enables? + { + if(iwRisStatus & mskCT16_MR1IF) + { + iwCT16B0_IrqEvent |= mskCT16_MR1IF; + SN_CT16B0->IC = mskCT16_MR1IC; //Clear MR1 match interrupt status + } + } + //MR2 + if (SN_CT16B0->MCTRL_b.MR2IE) //Check if MR2 IE enables? + { + if(iwRisStatus & mskCT16_MR2IF) + { + iwCT16B0_IrqEvent |= mskCT16_MR2IF; + SN_CT16B0->IC = mskCT16_MR2IC; //Clear MR2 match interrupt status + } + } + //MR3 + if (SN_CT16B0->MCTRL_b.MR3IE) //Check if MR3 IE enables? + { + if(iwRisStatus & mskCT16_MR3IF) + { + iwCT16B0_IrqEvent |= mskCT16_MR3IF; + SN_CT16B0->IC = mskCT16_MR3IC; //Clear MR3 match interrupt status + } + } + //CAP0 + if (SN_CT16B0->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables? + { + if(iwRisStatus & mskCT16_CAP0IF) //CAP0 + { + iwCT16B0_IrqEvent |= mskCT16_CAP0IF; + SN_CT16B0->IC = mskCT16_CAP0IC; //Clear CAP0 interrupt status + } + } +} + + + diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B0.h b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B0.h new file mode 100644 index 00000000..8faaa47f --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B0.h @@ -0,0 +1,26 @@ +#ifndef __SN32F240_CT16B0_H +#define __SN32F240_CT16B0_H + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +#define CT16B0_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT16B0 timer and interrupt + //POLLING_METHOD: Enable CT16B0 timer ONLY + +/*_____ M A C R O S ________________________________________________________*/ + // Enable CT16B0 PCLK +#define __CT16B0_ENABLE SN_SYS1->AHBCLKEN_b.CT16B0CLKEN = ENABLE + // Disable CT16B0 PCLK +#define __CT16B0_DISABLE SN_SYS1->AHBCLKEN_b.CT16B0CLKEN = DISABLE + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +extern volatile uint32_t iwCT16B0_IrqEvent; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS + +extern void CT16B0_Init(void); +extern void CT16B0_NvicEnable(void); +extern void CT16B0_NvicDisable(void); +extern void CT16B0_IRQHandler(void); +#endif /*__SN32F240_CT16B0_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B1.c b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B1.c new file mode 100644 index 00000000..8bba8df5 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B1.c @@ -0,0 +1,161 @@ +/******************** (C) COPYRIGHT 2013 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2013/12 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: CT16B1 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include "CT16.h" +#include "CT16B1.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +volatile uint32_t iwCT16B1_IrqEvent = 0x00; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS + +void CT16B1_Init (void); +void CT16B1_NvicEnable (void); +void CT16B1_NvicDisable (void); + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ +/***************************************************************************** +* Function : CT16B1_Init +* Description : Initialization of CT16B1 timer +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B1_Init (void) +{ + //Enable P_CLOCK for CT16B1. + __CT16B1_ENABLE; + + //CT16B1 PCLK prescalar setting + SN_SYS1->APBCP0_b.CT16B1PRE = 0x00; //PCLK = HCLK/1 + //SN_SYS1->APBCP0_b.CT16B1PRE = 0x01; //PCLK = HCLK/2 + //SN_SYS1->APBCP0_b.CT16B1PRE = 0x02; //PCLK = HCLK/4 + //SN_SYS1->APBCP0_b.CT16B1PRE = 0x03; //PCLK = HCLK/8 + //SN_SYS1->APBCP0_b.CT16B1PRE = 0x04; //PCLK = HCLK/16 +} + +/***************************************************************************** +* Function : CT16B1_NvicEnable +* Description : Enable CT16B1 timer interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B1_NvicEnable (void) +{ + NVIC_ClearPendingIRQ(CT16B1_IRQn); + NVIC_EnableIRQ(CT16B1_IRQn); + //NVIC_SetPriority(CT16B1_IRQn,0); // Set interrupt priority (default) +} + +/***************************************************************************** +* Function : CT16B1_NvicDisable +* Description : Enable CT16B1 timer interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B1_NvicDisable (void) +{ + NVIC_DisableIRQ(CT16B1_IRQn); +} + +/***************************************************************************** +* Function : CT16B1_IRQHandler +* Description : ISR of CT16B1 interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B1_IRQHandler(void) +{ + uint32_t iwRisStatus; + + iwRisStatus = SN_CT16B1->RIS; //Save the interrupt status. + + //Before checking the status, always re-check the interrupt enable register first. + //In practice, user might use only one or two timer interrupt source. + //Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary. + //User can add the directive pair of "#if 0" and "#endif" pair + //to COMMENT the un-used parts to reduce ISR overheads and ROM usage. + + //Check the status in oder. + //MR0 + if (SN_CT16B1->MCTRL_b.MR0IE) //Check if MR0 IE enables? + { + if(iwRisStatus & mskCT16_MR0IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR0IF; + SN_CT16B1->IC = mskCT16_MR0IC; //Clear MR0 match interrupt status + } + } + //MR1 + if (SN_CT16B1->MCTRL_b.MR1IE) //Check if MR1 IE enables? + { + if(iwRisStatus & mskCT16_MR1IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR1IF; + SN_CT16B1->IC = mskCT16_MR1IC; //Clear MR1 match interrupt status + } + } + + //MR2 + if (SN_CT16B1->MCTRL_b.MR2IE) //Check if MR2 IE enables? + { + if(iwRisStatus & mskCT16_MR2IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR2IF; + SN_CT16B1->IC = mskCT16_MR2IC; //Clear MR2 match interrupt status + } + } + + //MR3 + if (SN_CT16B1->MCTRL_b.MR3IE) //Check if MR3 IE enables? + { + if(iwRisStatus & mskCT16_MR3IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR3IF; + SN_CT16B1->IC = mskCT16_MR3IC; //Clear MR3 match interrupt status + } + } + + //CAP0 + if (SN_CT16B1->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables? + { + if(iwRisStatus & mskCT16_CAP0IF) //CAP0 + { + iwCT16B1_IrqEvent |= mskCT16_CAP0IF; + SN_CT16B1->IC = mskCT16_CAP0IC; //Clear CAP0 interrupt status + } + } +} + + + diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B1.h b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B1.h new file mode 100644 index 00000000..380119a2 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B1.h @@ -0,0 +1,26 @@ +#ifndef __SN32F240_CT16B1_H +#define __SN32F240_CT16B1_H + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +#define CT16B1_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT16B1 timer and interrupt + //POLLING_METHOD: Enable CT16B1 timer ONLY + +/*_____ M A C R O S ________________________________________________________*/ + // Enable CT16B1 PCLK +#define __CT16B1_ENABLE SN_SYS1->AHBCLKEN_b.CT16B1CLKEN = ENABLE + // Disable CT16B1 PCLK +#define __CT16B1_DISABLE SN_SYS1->AHBCLKEN_b.CT16B1CLKEN = DISABLE + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +extern volatile uint32_t iwCT16B1_IrqEvent; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS + +extern void CT16B1_Init(void); +extern void CT16B1_NvicEnable(void); +extern void CT16B1_NvicDisable(void); +extern void CT16B1_IRQHandler(void); +#endif /*__SN32F240_CT16B1_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B2.c b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B2.c new file mode 100644 index 00000000..846ede03 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B2.c @@ -0,0 +1,158 @@ +/******************** (C) COPYRIGHT 2013 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2013/12 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: CT16B2 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include "CT16.h" +#include "CT16B2.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +volatile uint32_t iwCT16B2_IrqEvent = 0x00; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS + +void CT16B2_Init (void); +void CT16B2_NvicEnable (void); +void CT16B2_NvicDisable (void); +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ +/***************************************************************************** +* Function : CT16B2_Init +* Description : Initialization of CT16B2 timer +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B2_Init (void) +{ + //Enable P_CLOCK for CT16B2. + __CT16B2_ENABLE; + + //CT16B2 PCLK prescalar setting + SN_SYS1->APBCP1_b.CT16B2PRE = 0x00; //PCLK = HCLK/1 + //SN_SYS1->APBCP1_b.CT16B2PRE = 0x01; //PCLK = HCLK/2 + //SN_SYS1->APBCP1_b.CT16B2PRE = 0x02; //PCLK = HCLK/4 + //SN_SYS1->APBCP1_b.CT16B2PRE = 0x03; //PCLK = HCLK/8 + //SN_SYS1->APBCP1_b.CT16B2PRE = 0x04; //PCLK = HCLK/16 +} + +/***************************************************************************** +* Function : CT16B2_NvicEnable +* Description : Enable CT16B2 timer interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B2_NvicEnable (void) +{ + NVIC_ClearPendingIRQ(CT16B2_IRQn); + NVIC_EnableIRQ(CT16B2_IRQn); + NVIC_SetPriority(CT16B2_IRQn,0); // Set interrupt priority (default) +} + +/***************************************************************************** +* Function : CT16B2_NvicDisable +* Description : Disable CT16B2 timer interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B2_NvicDisable (void) +{ + NVIC_DisableIRQ(CT16B2_IRQn); +} + + +/***************************************************************************** +* Function : CT16B2_IRQHandler +* Description : ISR of CT16B2 interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B2_IRQHandler(void) +{ + uint32_t iwRisStatus; + + iwRisStatus = SN_CT16B2->RIS; // Save the interrupt status. + + //Before checking the status, always re-check the interrupt enable register first. + //In practice, user might use only one or two timer interrupt source. + //Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary. + //User can add the directive pair of "#if 0" and "#endif" pair + //to COMMENT the un-used parts to reduce ISR overheads and ROM usage. + + //Check the status in oder. + //MR0 + if (SN_CT16B2->MCTRL_b.MR0IE) //Check if MR0 IE enables? + { + if(iwRisStatus & mskCT16_MR0IF) + { + iwCT16B2_IrqEvent |= mskCT16_MR0IF; + SN_CT16B2->IC = mskCT16_MR0IC; //Clear MR0 match interrupt status + } + } + //MR1 + if (SN_CT16B2->MCTRL_b.MR1IE) //Check if MR1 IE enables? + { + if(iwRisStatus & mskCT16_MR1IF) + { + iwCT16B2_IrqEvent |= mskCT16_MR1IF; + SN_CT16B2->IC = mskCT16_MR1IC; //Clear MR1 match interrupt status + } + } + //MR2 + if (SN_CT16B2->MCTRL_b.MR2IE) //Check if MR2 IE enables? + { + if(iwRisStatus & mskCT16_MR2IF) + { + iwCT16B2_IrqEvent |= mskCT16_MR2IF; + SN_CT16B2->IC = mskCT16_MR2IC; //Clear MR2 match interrupt status + } + } + //MR3 + if (SN_CT16B2->MCTRL_b.MR3IE) //Check if MR3 IE enables? + { + if(iwRisStatus & mskCT16_MR3IF) + { + iwCT16B2_IrqEvent |= mskCT16_MR3IF; + SN_CT16B2->IC = mskCT16_MR3IC; //Clear MR3 match interrupt status + } + } + //CAP0 + if (SN_CT16B2->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables? + { + if(iwRisStatus & mskCT16_CAP0IF) //CAP0 + { + iwCT16B2_IrqEvent |= mskCT16_CAP0IF; + SN_CT16B2->IC = mskCT16_CAP0IC; //Clear CAP0 interrupt status + } + } +} + + + diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B2.h b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B2.h new file mode 100644 index 00000000..23c4a4ed --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B2.h @@ -0,0 +1,26 @@ +#ifndef __SN32F240_CT16B2_H +#define __SN32F240_CT16B2_H + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +#define CT16B2_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT16B2 timer and interrupt + //POLLING_METHOD: Enable CT16B2 timer ONLY + +/*_____ M A C R O S ________________________________________________________*/ + // Enable CT16B2 PCLK +#define __CT16B2_ENABLE SN_SYS1->AHBCLKEN_b.CT16B2CLKEN = ENABLE + // Disable CT16B1 PCLK +#define __CT16B2_DISABLE SN_SYS1->AHBCLKEN_b.CT16B2CLKEN = DISABLE + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +extern volatile uint32_t iwCT16B2_IrqEvent; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS + +extern void CT16B2_Init(void); +extern void CT16B2_NvicEnable(void); +extern void CT16B2_NvicDisable(void); +extern void CT16B2_IRQHandler(void); +#endif /*__SN32F240_CT16B2_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32.h b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32.h new file mode 100644 index 00000000..48e2de98 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32.h @@ -0,0 +1,278 @@ +#ifndef __SN32F240_CT32_H +#define __SN32F240_CT32_H + + +/*_____ I N C L U D E S ____________________________________________________*/ + +/*_____ D E F I N I T I O N S ______________________________________________*/ +/* +Base Address: 0x4000 6000 (CT32B0) + 0x4000 8000 (CT32B1) + 0x4000 A000 (CT32B2) +*/ + +/* CT32Bn Timer Control register (0x00) */ +#define CT32_CEN_DIS 0 //[0:0] CT32Bn enable bit +#define CT32_CEN_EN 1 +#define mskCT32_CEN_DIS (CT32_CEN_DIS<<0) +#define mskCT32_CEN_EN (CT32_CEN_EN<<0) + +#define CT32_CRST 1 //[1:1] CT32Bn counter reset bit +#define mskCT32_CRST (CT32_CRST<<1) + + //[6:4] CT32Bn counting mode selection +#define CT32_CM_EDGE_UP 0 //Edge-aligned Up-counting mode +#define CT32_CM_EDGE_DOWN 1 //Edge-aligned Down-counting mode +#define CT32_CM_CENTER_UP 2 //Center-aligned mode 1. Match interrupt is set during up-counting period +#define CT32_CM_CENTER_DOWN 4 //Center-aligned mode 2. Match interrupt is set during down-counting period +#define CT32_CM_CENTER_BOTH 6 //Center-aligned mode 3. Match interrupt is set during both up and down period. +#define mskCT32_CM_EDGE_UP (CT32_CM_EDGE_UP<<4) +#define mskCT32_CM_EDGE_DOWN (CT32_CM_EDGE_DOWN<<4) +#define mskCT32_CM_CENTER_UP (CT32_CM_CENTER_UP<<4) +#define mskCT32_CM_CENTER_DOWN (CT32_CM_CENTER_DOWN<<4) +#define mskCT32_CM_CENTER_BOTH (CT32_CM_CENTER_BOTH<<4) + +/* CT32Bn Count Control register (0x10) */ + //[1:0] Count/Timer Mode selection. +#define CT32_CTM_TIMER 0 //Timer mode: Every rising PCLK edge. +#define CT32_CTM_CNTER_RISING 1 //Counter mode: TC increments on rising edge of CAP input. +#define CT32_CTM_CNTER_FALLING 2 //Counter mode: TC increments on falling edge of CAP input. +#define CT32_CTM_CNTER_BOTH 3 //Counter mode: TC increments on both edge of CAP input. +#define mskCT32_CTM_TIMER (CT32_CTM_TIMER<<0) +#define mskCT32_CTM_CNTER_RISING (CT32_CTM_CNTER_RISING<<0) +#define mskCT32_CTM_CNTER_FALLING (CT32_CTM_CNTER_FALLING<<0) +#define mskCT32_CTM_CNTER_BOTH (CT32_CTM_CNTER_BOTH<<0) + +#define CT32_CIS 0 //[3:2] Count Input Select +#define mskCT32_CIS (CT32_CIS<<2) + +/* CT32Bn Match Control register (0x14) */ +#define CT32_MR0IE_EN 1 //[0:0] Enable MR0 match interrupt +#define CT32_MR0IE_DIS 0 +#define mskCT32_MR0IE_EN (CT32_MR0IE_EN<<0) +#define mskCT32_MR0IE_DIS (CT32_MR0IE_DIS<<0) + +#define CT32_MR0RST_EN 1 //[1:1] Enable reset TC when MR0 matches TC. +#define CT32_MR0RST_DIS 0 +#define mskCT32_MR0RST_EN (CT32_MR0RST_EN<<1) +#define mskCT32_MR0RST_DIS (CT32_MR0RST_DIS<<1) + +#define CT32_MR0STOP_EN 1 //[2:2] Enable stop TC and clear CEN when MR0 matches TC. +#define CT32_MR0STOP_DIS 0 +#define mskCT32_MR0STOP_EN (CT32_MR0STOP_EN<<2) +#define mskCT32_MR0STOP_DIS (CT32_MR0STOP_DIS<<2) + +#define CT32_MR1IE_EN 1 //[3:3] Enable MR1 match interrupt +#define CT32_MR1IE_DIS 0 +#define mskCT32_MR1IE_EN (CT32_MR1IE_EN<<3) +#define mskCT32_MR1IE_DIS (CT32_MR1IE_DIS<<3) + +#define CT32_MR1RST_EN 1 //[4:4] Enable reset TC when MR1 matches TC. +#define CT32_MR1RST_DIS 0 +#define mskCT32_MR1RST_EN (CT32_MR1RST_EN<<4) +#define mskCT32_MR1RST_DIS (CT32_MR1RST_DIS<<4) + +#define CT32_MR1STOP_EN 1 //[5:5] Enable stop TC and clear CEN when MR1 matches TC. +#define CT32_MR1STOP_DIS 0 +#define mskCT32_MR1STOP_EN (CT32_MR1STOP_EN<<5) +#define mskCT32_MR1STOP_DIS (CT32_MR1STOP_DIS<<5) + +#define CT32_MR2IE_EN 1 //[6:6] Enable MR2 match interrupt +#define CT32_MR2IE_DIS 0 +#define mskCT32_MR2IE_EN (CT32_MR2IE_EN<<6) +#define mskCT32_MR2IE_DIS (CT32_MR2IE_DIS<<6) + +#define CT32_MR2RST_EN 1 //[7:7] Enable reset TC when MR2 matches TC. +#define CT32_MR2RST_DIS 0 +#define mskCT32_MR2RST_EN (CT32_MR2RST_EN<<7) +#define mskCT32_MR2RST_DIS (CT32_MR2RST_DIS<<7) + +#define CT32_MR2STOP_EN 1 //[8:8] Enable stop TC and clear CEN when MR2 matches TC. +#define CT32_MR2STOP_DIS 0 +#define mskCT32_MR2STOP_EN (CT32_MR2STOP_EN<<8) +#define mskCT32_MR2STOP_DIS (CT32_MR2STOP_DIS<<8) + +#define CT32_MR3IE_EN 1 //[9:9] Enable MR3 match interrupt +#define CT32_MR3IE_DIS 0 +#define mskCT32_MR3IE_EN (CT32_MR3IE_EN<<9) +#define mskCT32_MR3IE_DIS (CT32_MR3IE_DIS<<9) + +#define CT32_MR3RST_EN 1 //[10:10] Enable reset TC when MR3 matches TC. +#define CT32_MR3RST_DIS 0 +#define mskCT32_MR3RST_EN (CT32_MR3RST_EN<<10) +#define mskCT32_MR3RST_DIS (CT32_MR3RST_DIS<<10) + +#define CT32_MR3STOP_EN 1 //[11:11] Enable stop TC and clear CEN when MR3 matches TC. +#define CT32_MR3STOP_DIS 0 +#define mskCT32_MR3STOP_EN (CT32_MR3STOP_EN<<11) +#define mskCT32_MR3STOP_DIS (CT32_MR3STOP_DIS<<11) + +/* CT32Bn Capture Control register (0x28) */ +#define CT32_CAP0RE_EN 1 //[0:0] Enable CAP0 capture on rising edge. +#define CT32_CAP0RE_DIS 0 +#define mskCT32_CAP0RE_EN (CT32_CAP0RE_EN<<0) +#define mskCT32_CAP0RE_DIS (CT32_CAP0RE_DIS<<0) + +#define CT32_CAP0FE_EN 1 //[1:1] Enable CAP0 capture on fallng edge. +#define CT32_CAP0FE_DIS 0 +#define mskCT32_CAP0FE_EN (CT32_CAP0FE_EN<<1) +#define mskCT32_CAP0FE_DIS (CT32_CAP0FE_DIS<<1) + +#define CT32_CAP0IE_EN 1 //[2:2] Enable CAP0 interrupt. +#define CT32_CAP0IE_DIS 0 +#define mskCT32_CAP0IE_EN (CT32_CAP0IE_EN<<2) +#define mskCT32_CAP0IE_DIS (CT32_CAP0IE_DIS<<2) + +#define CT32_CAP0EN_EN 1 //[3:3] Enable CAP0 function. +#define CT32_CAP0EN_DIS 0 +#define mskCT32_CAP0EN_EN (CT32_CAP0EN_EN<<3) +#define mskCT32_CAP0EN_DIS (CT32_CAP0EN_DIS<<3) + +/* CT32Bn External Match register (0x30) */ +#define CT32_EM0 1 //[0:0] CT32Bn PWM0 drive state +#define mskCT32_EM0 (CT32_EM0<<0) +#define CT32_EM1 1 //[1:1] CT32Bn PWM1 drive state +#define mskCT32_EM1 (CT32_EM1<<1) +#define CT32_EM2 1 //[2:2] CT32Bn PWM2 drive state +#define mskCT32_EM2 (CT32_EM2<<2) +#define CT32_EM3 1 //[3:3] CT32Bn PWM3 drive state +#define mskCT32_EM3 (CT32_EM3<<3) + + //[5:4] CT32Bn PWM0 functionality +#define CT32_EMC0_DO_NOTHING 0 //Do nothing. +#define CT32_EMC0_LOW 1 //CT32Bn PWM0 pin is low. +#define CT32_EMC0_HIGH 2 //CT32Bn PWM0 pin is high. +#define CT32_EMC0_TOGGLE 3 //Toggle CT32Bn PWM0 pin. +#define mskCT32_EMC0_DO_NOTHING (CT32_EMC0_LOW<<4) +#define mskCT32_EMC0_LOW (CT32_EMC0_LOW<<4) +#define mskCT32_EMC0_HIGH (CT32_EMC0_HIGH<<4) +#define mskCT32_EMC0_TOGGLE (CT32_EMC0_TOGGLE<<4) + + //[7:6] CT32Bn PWM1 functionality +#define CT32_EMC1_DO_NOTHING 0 //Do nothing. +#define CT32_EMC1_LOW 1 //CT32Bn PWM1 pin is low. +#define CT32_EMC1_HIGH 2 //CT32Bn PWM1 pin is high. +#define CT32_EMC1_TOGGLE 3 //Toggle CT32Bn PWM1 pin. +#define mskCT32_EMC1_DO_NOTHING (CT32_EMC1_LOW<<6) +#define mskCT32_EMC1_LOW (CT32_EMC1_LOW<<6) +#define mskCT32_EMC1_HIGH (CT32_EMC1_HIGH<<6) +#define mskCT32_EMC1_TOGGLE (CT32_EMC1_TOGGLE<<6) + + //[9:8] CT32Bn PWM2 functionality +#define CT32_EMC2_DO_NOTHING 0 //Do nothing. +#define CT32_EMC2_LOW 1 //CT32Bn PWM2 pin is low. +#define CT32_EMC2_HIGH 2 //CT32Bn PWM2 pin is high. +#define CT32_EMC2_TOGGLE 3 //Toggle CT32Bn PWM2 pin. +#define mskCT32_EMC2_DO_NOTHING (CT32_EMC2_LOW<<8) +#define mskCT32_EMC2_LOW (CT32_EMC2_LOW<<8) +#define mskCT32_EMC2_HIGH (CT32_EMC2_HIGH<<8) +#define mskCT32_EMC2_TOGGLE (CT32_EMC2_TOGGLE<<8) + + //[11:10] CT32Bn PWM3 functionality +#define CT32_EMC3_DO_NOTHING 0 //Do nothing. +#define CT32_EMC3_LOW 1 //CT32Bn PWM3 pin is low. +#define CT32_EMC3_HIGH 2 //CT32Bn PWM3 pin is high. +#define CT32_EMC3_TOGGLE 3 //Toggle CT32Bn PWM3 pin. +#define mskCT32_EMC3_DO_NOTHING (CT32_EMC2_LOW<<10) +#define mskCT32_EMC3_LOW (CT32_EMC2_LOW<<10) +#define mskCT32_EMC3_HIGH (CT32_EMC2_HIGH<<10) +#define mskCT32_EMC3_TOGGLE (CT32_EMC2_TOGGLE<<10) + +/* CT32Bn PWM Control register (0x34) */ + //[0:0] CT32Bn PWM0 enable. +#define CT32_PWM0EN_EN 1 // CT32Bn PWM0 is enabled for PWM mode. +#define CT32_PWM0EN_EM0 0 // CT32Bn PWM0 is controlled by EM0. +#define mskCT32_PWM0EN_EN (CT32_PWM0EN_EN<<0) +#define mskCT32_PWM0EN_EM0 (CT32_PWM0EN_EM0<<0) + + //[1:1] CT32Bn PWM1 enable. +#define CT32_PWM1EN_EN 1 // CT32Bn PWM1 is enabled for PWM mode. +#define CT32_PWM1EN_EM1 0 // CT32Bn PWM1 is controlled by EM1. +#define mskCT32_PWM1EN_EN (CT32_PWM1EN_EN<<1) +#define mskCT32_PWM1EN_EM1 (CT32_PWM1EN_EM1<<1) + + //[2:2] CT32Bn PWM2 enable. +#define CT32_PWM2EN_EN 1 // CT32Bn PWM2 is enabled for PWM mode. +#define CT32_PWM2EN_EM2 0 // CT32Bn PWM2 is controlled by EM2. +#define mskCT32_PWM2EN_EN (CT32_PWM2EN_EN<<2) +#define mskCT32_PWM2EN_EM2 (CT32_PWM2EN_EM2<<2) + + //[3:3] CT32Bn PWM3 enable. +#define CT32_PWM3EN_EN 1 // CT32Bn PWM3 is enabled for PWM mode. +#define CT32_PWM3EN_EM3 0 // CT32Bn PWM3 is controlled by EM3. +#define mskCT32_PWM3EN_EN (CT32_PWM3EN_EN<<3) +#define mskCT32_PWM3EN_EM3 (CT32_PWM3EN_EM3<<3) + + //[5:4] CT32Bn PWM0 output mode. +#define CT32_PWM0MODE_1 0 // PWM mode 1. +#define CT32_PWM0MODE_2 1 // PWM mode 2. +#define CT32_PWM0MODE_FORCE_0 2 // Force 0. +#define CT32_PWM0MODE_FORCE_1 3 // Force 1. +#define mskCT32_PWM0MODE_1 (CT32_PWM0MODE_1<<4) +#define mskCT32_PWM0MODE_2 (CT32_PWM0MODE_2<<4) +#define mskCT32_PWM0MODE_FORCE_0 (CT32_PWM0MODE_FORCE_0<<4) +#define mskCT32_PWM0MODE_FORCE_1 (CT32_PWM0MODE_FORCE_1<<4) + + //[7:6] CT32Bn PWM1 output mode. +#define CT32_PWM1MODE_1 0 // PWM mode 1. +#define CT32_PWM1MODE_2 1 // PWM mode 2. +#define CT32_PWM1MODE_FORCE_0 2 // Force 0. +#define CT32_PWM1MODE_FORCE_1 3 // Force 1. +#define mskCT32_PWM1MODE_1 (CT32_PWM1MODE_1<<6) +#define mskCT32_PWM1MODE_2 (CT32_PWM1MODE_2<<6) +#define mskCT32_PWM1MODE_FORCE_0 (CT32_PWM1MODE_FORCE_0<<6) +#define mskCT32_PWM1MODE_FORCE_1 (CT32_PWM1MODE_FORCE_1<<6) + + //[9:8] CT32Bn PWM2 output mode. +#define CT32_PWM2MODE_1 0 // PWM mode 1. +#define CT32_PWM2MODE_2 1 // PWM mode 2. +#define CT32_PWM2MODE_FORCE_0 2 // Force 0. +#define CT32_PWM2MODE_FORCE_1 3 // Force 1. +#define mskCT32_PWM2MODE_1 (CT32_PWM2MODE_1<<8) +#define mskCT32_PWM2MODE_2 (CT32_PWM2MODE_2<<8) +#define mskCT32_PWM2MODE_FORCE_0 (CT32_PWM2MODE_FORCE_0<<8) +#define mskCT32_PWM2MODE_FORCE_1 (CT32_PWM2MODE_FORCE_1<<8) + + //[20:20] CT32Bn PWM0 IO selection. +#define CT32_PWM0IOEN_EN 1 // PWM 0 pin acts as match output. +#define CT32_PWM0IOEN_DIS 0 // PWM 0 pin acts as GPIO. +#define mskCT32_PWM0IOEN_EN (CT32_PWM0IOEN_EN<<20) +#define mskCT32_PWM0IOEN_DIS (CT32_PWM0IOEN_DIS<<20) + + //[21:21] CT32Bn PWM1 IO selection. +#define CT32_PWM1IOEN_EN 1 // PWM 1 pin acts as match output. +#define CT32_PWM1IOEN_DIS 0 // PWM 1 pin acts as GPIO. +#define mskCT32_PWM1IOEN_EN (CT32_PWM1IOEN_EN<<21) +#define mskCT32_PWM1IOEN_DIS (CT32_PWM1IOEN_DIS<<21) + + //[22:22] CT32Bn PWM2 IO selection. +#define CT32_PWM2IOEN_EN 1 // PWM 2 pin acts as match output. +#define CT32_PWM2IOEN_DIS 0 // PWM 2 pin acts as GPIO. +#define mskCT32_PWM2IOEN_EN (CT32_PWM2IOEN_EN<<22) +#define mskCT32_PWM2IOEN_DIS (CT32_PWM2IOEN_DIS<<22) + + //[23:23] CT32Bn PWM3 IO selection. +#define CT32_PWM3IOEN_EN 1 // PWM 3 pin acts as match output. +#define CT32_PWM3IOEN_DIS 0 // PWM 3 pin acts as GPIO. +#define mskCT32_PWM3IOEN_EN (CT32_PWM3IOEN_EN<<23) +#define mskCT32_PWM3IOEN_DIS (CT32_PWM3IOEN_DIS<<23) + +/* CT32Bn Timer Raw Interrupt Status register (0x38) */ +/* CT32Bn Timer Interrupt Clear register (0x3C) */ +/* The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS*/ +#define mskCT32_MR0IF (0x1<<0) //[0:0] Interrupt flag for match channel 0 +#define mskCT32_MR0IC mskCT32_MR0IF +#define mskCT32_MR1IF (0x1<<1) //[1:1] Interrupt flag for match channel 1 +#define mskCT32_MR1IC mskCT32_MR1IF +#define mskCT32_MR2IF (0x1<<2) //[2:2] Interrupt flag for match channel 2 +#define mskCT32_MR2IC mskCT32_MR2IF +#define mskCT32_MR3IF (0x1<<3) //[3:3] Interrupt flag for match channel 3 +#define mskCT32_MR3IC mskCT32_MR3IF +#define mskCT32_CAP0IF (0x1<<4) //[4:4] Interrupt flag for capture channel 0 +#define mskCT32_CAP0IC mskCT32_CAP0IF + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +#endif /*__SN32F240_CT32_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B0.c b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B0.c new file mode 100644 index 00000000..099a1963 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B0.c @@ -0,0 +1,160 @@ +/******************** (C) COPYRIGHT 2013 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2013/12 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: CT32B0 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include "CT32.h" +#include "CT32B0.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +volatile uint32_t iwCT32B0_IrqEvent = 0x00; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS + +void CT32B0_Init (void); +void CT32B0_NvicEnable (void); +void CT32B0_NvicDisable (void); + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + +/***************************************************************************** +* Function : CT32B0_Init +* Description : Initialization of CT32B0 timer +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT32B0_Init (void) +{ + //Enable P_CLOCK for CT32B0. + __CT32B0_ENABLE; + + //CT32B0 PCLK prescalar setting + SN_SYS1->APBCP0_b.CT32B0PRE = 0x00; //PCLK = HCLK/1 + //SN_SYS1->APBCP0_b.CT32B0PRE = 0x01; //PCLK = HCLK/2 + //SN_SYS1->APBCP0_b.CT32B0PRE = 0x02; //PCLK = HCLK/4 + //SN_SYS1->APBCP0_b.CT32B0PRE = 0x03; //PCLK = HCLK/8 + //SN_SYS1->APBCP0_b.CT32B0PRE = 0x04; //PCLK = HCLK/16 +} + +/***************************************************************************** +* Function : CT32B0_NvicEnable +* Description : Enable CT32B0 timer interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT32B0_NvicEnable (void) +{ + NVIC_ClearPendingIRQ(CT32B0_IRQn); + NVIC_EnableIRQ(CT32B0_IRQn); + //NVIC_SetPriority(CT32B0_IRQn,0); //Set interrupt priority (default) +} + +/***************************************************************************** +* Function : CT32B0_NvicDisable +* Description : Disable CT32B0 timer interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT32B0_NvicDisable (void) +{ + NVIC_DisableIRQ(CT32B0_IRQn); +} + + +/***************************************************************************** +* Function : TIMER32_0_IRQHandler +* Description : ISR of CT32B0 interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT32B0_IRQHandler(void) +{ + uint32_t iwRisStatus; + + iwRisStatus = SN_CT32B0->RIS; // Save the interrupt status. + + //Before checking the status, always re-check the interrupt enable register first. + //In practice, user might use only one or two timer interrupt source. + //Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary. + //User can add the directive pair of "#if 0" and "#endif" pair + //to COMMENT the un-used parts to reduce ISR overheads and ROM usage. + + //Check the status in oder. + //MR0 + if (SN_CT32B0->MCTRL_b.MR0IE) //Check if MR0 IE enables? + { + if(iwRisStatus & mskCT32_MR0IF) + { + iwCT32B0_IrqEvent |= mskCT32_MR0IF; + SN_CT32B0->IC = mskCT32_MR0IC; //Clear MR0 match interrupt status + } + } + //MR1 + if (SN_CT32B0->MCTRL_b.MR1IE) //Check if MR1 IE enables? + { + if(iwRisStatus & mskCT32_MR1IF) + { + iwCT32B0_IrqEvent |= mskCT32_MR1IF; + SN_CT32B0->IC = mskCT32_MR1IC; //Clear MR1 match interrupt status + } + } + //MR2 + if (SN_CT32B0->MCTRL_b.MR2IE) //Check if MR2 IE enables? + { + if(iwRisStatus & mskCT32_MR2IF) + { + iwCT32B0_IrqEvent |= mskCT32_MR2IF; + SN_CT32B0->IC = mskCT32_MR2IC; //Clear MR2 match interrupt status + } + } + //MR3 + if (SN_CT32B0->MCTRL_b.MR3IE) //Check if MR3 IE enables? + { + if(iwRisStatus & mskCT32_MR3IF) + { + iwCT32B0_IrqEvent |= mskCT32_MR3IF; + SN_CT32B0->IC = mskCT32_MR3IC; //Clear MR3 match interrupt status + } + } + //CAP0 + if (SN_CT32B0->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables? + { + if(iwRisStatus & mskCT32_CAP0IF) //CAP0 + { + iwCT32B0_IrqEvent |= mskCT32_CAP0IF; + SN_CT32B0->IC = mskCT32_CAP0IC; //Clear CAP0 interrupt status + } + } +} + + + diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B0.h b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B0.h new file mode 100644 index 00000000..9973f45c --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B0.h @@ -0,0 +1,26 @@ +#ifndef __SN32F240_CT32B0_H +#define __SN32F240_CT32B0_H + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +#define CT32B0_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT32B0 timer and interrupt + //POLLING_METHOD: Enable CT32B0 timer ONLY + +/*_____ M A C R O S ________________________________________________________*/ + // Enable CT32B0 PCLK +#define __CT32B0_ENABLE SN_SYS1->AHBCLKEN_b.CT32B0CLKEN = ENABLE + // Disable CT32B0 PCLK +#define __CT32B0_DISABLE SN_SYS1->AHBCLKEN_b.CT32B0CLKEN = DISABLE + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +extern volatile uint32_t iwCT32B0_IrqEvent; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS + +extern void CT32B0_Init(void); +extern void CT32B0_NvicEnable(void); +extern void CT32B0_NvicDisable(void); +extern void CT32B0_IRQHandler(void); +#endif /*__SN32F240_CT32B0_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B1.c b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B1.c new file mode 100644 index 00000000..88b9372b --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B1.c @@ -0,0 +1,160 @@ +/******************** (C) COPYRIGHT 2013 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2013/12 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: CT32B1 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include "CT32.h" +#include "CT32B1.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +volatile uint32_t iwCT32B1_IrqEvent = 0x00; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS + +void CT32B1_Init (void); +void CT32B1_NvicEnable (void); +void CT32B1_NvicDisable (void); + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + +/***************************************************************************** +* Function : CT32B1_Init +* Description : Initialization of CT32B1 timer +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT32B1_Init (void) +{ + //Enable P_CLOCK for CT32B1. + __CT32B1_ENABLE; + + //CT32B1 PCLK prescalar setting + SN_SYS1->APBCP0_b.CT32B1PRE = 0x00; //PCLK = HCLK/1 + //SN_SYS1->APBCP0_b.CT32B1PRE = 0x01; //PCLK = HCLK/2 + //SN_SYS1->APBCP0_b.CT32B1PRE = 0x02; //PCLK = HCLK/4 + //SN_SYS1->APBCP0_b.CT32B1PRE = 0x03; //PCLK = HCLK/8 + //SN_SYS1->APBCP0_b.CT32B1PRE = 0x04; //PCLK = HCLK/16 +} + +/***************************************************************************** +* Function : CT32B1_NvicEnable +* Description : Enable CT32B1 timer interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT32B1_NvicEnable (void) +{ + NVIC_ClearPendingIRQ(CT32B1_IRQn); + NVIC_EnableIRQ(CT32B1_IRQn); + //NVIC_SetPriority(CT32B1_IRQn,0); //Set interrupt priority (default) +} + +/***************************************************************************** +* Function : CT32B1_NvicDisable +* Description : Disable CT32B1 timer interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT32B1_NvicDisable (void) +{ + NVIC_DisableIRQ(CT32B1_IRQn); +} + + +/***************************************************************************** +* Function : TIMER32_0_IRQHandler +* Description : ISR of CT32B1 interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT32B1_IRQHandler(void) +{ + uint32_t iwRisStatus; + + iwRisStatus = SN_CT32B1->RIS; // Save the interrupt status. + + //Before checking the status, always re-check the interrupt enable register first. + //In practice, user might use only one or two timer interrupt source. + //Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary. + //User can add the directive pair of "#if 0" and "#endif" pair + //to COMMENT the un-used parts to reduce ISR overheads and ROM usage. + + //Check the status in oder. + //MR0 + if (SN_CT32B1->MCTRL_b.MR0IE) //Check if MR0 IE enables? + { + if(iwRisStatus & mskCT32_MR0IF) + { + iwCT32B1_IrqEvent |= mskCT32_MR0IF; + SN_CT32B1->IC = mskCT32_MR0IC; //Clear MR0 match interrupt status + } + } + //MR1 + if (SN_CT32B1->MCTRL_b.MR1IE) //Check if MR1 IE enables? + { + if(iwRisStatus & mskCT32_MR1IF) + { + iwCT32B1_IrqEvent |= mskCT32_MR1IF; + SN_CT32B1->IC = mskCT32_MR1IC; //Clear MR1 match interrupt status + } + } + //MR2 + if (SN_CT32B1->MCTRL_b.MR2IE) //Check if MR2 IE enables? + { + if(iwRisStatus & mskCT32_MR2IF) + { + iwCT32B1_IrqEvent |= mskCT32_MR2IF; + SN_CT32B1->IC = mskCT32_MR2IC; //Clear MR2 match interrupt status + } + } + //MR3 + if (SN_CT32B1->MCTRL_b.MR3IE) //Check if MR3 IE enables? + { + if(iwRisStatus & mskCT32_MR3IF) + { + iwCT32B1_IrqEvent |= mskCT32_MR3IF; + SN_CT32B1->IC = mskCT32_MR3IC; //Clear MR3 match interrupt status + } + } + //CAP0 + if (SN_CT32B1->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables? + { + if(iwRisStatus & mskCT32_CAP0IF) //CAP0 + { + iwCT32B1_IrqEvent |= mskCT32_CAP0IF; + SN_CT32B1->IC = mskCT32_CAP0IC; //Clear CAP0 interrupt status + } + } +} + + + diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B1.h b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B1.h new file mode 100644 index 00000000..278a60e0 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B1.h @@ -0,0 +1,26 @@ +#ifndef __SN32F240_CT32B1_H +#define __SN32F240_CT32B1_H + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +#define CT32B1_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT32B1 timer and interrupt + //POLLING_METHOD: Enable CT32B1 timer ONLY + +/*_____ M A C R O S ________________________________________________________*/ + // Enable CT32B1 PCLK +#define __CT32B1_ENABLE SN_SYS1->AHBCLKEN_b.CT32B1CLKEN = ENABLE + // Disable CT32B1 PCLK +#define __CT32B1_DISABLE SN_SYS1->AHBCLKEN_b.CT32B1CLKEN = DISABLE + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +extern volatile uint32_t iwCT32B1_IrqEvent; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS + +extern void CT32B1_Init(void); +extern void CT32B1_NvicEnable(void); +extern void CT32B1_NvicDisable(void); +extern void CT32B1_IRQHandler(void); +#endif /*__SN32F240_CT32B1_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B2.c b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B2.c new file mode 100644 index 00000000..b405284c --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B2.c @@ -0,0 +1,160 @@ +/******************** (C) COPYRIGHT 2013 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2013/12 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: CT32B2 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include "CT32.h" +#include "CT32B2.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +volatile uint32_t iwCT32B2_IrqEvent = 0x00; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS + +void CT32B2_Init (void); +void CT32B2_NvicEnable (void); +void CT32B2_NvicDisable (void); + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + +/***************************************************************************** +* Function : CT32B2_Init +* Description : Initialization of CT32B2 timer +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT32B2_Init (void) +{ + //Enable P_CLOCK for CT32B2. + __CT32B2_ENABLE; + + //CT32B2 PCLK prescalar setting + SN_SYS1->APBCP0_b.CT32B2PRE = 0x00; //PCLK = HCLK/1 + //SN_SYS1->APBCP0_b.CT32B2PRE = 0x01; //PCLK = HCLK/2 + //SN_SYS1->APBCP0_b.CT32B2PRE = 0x02; //PCLK = HCLK/4 + //SN_SYS1->APBCP0_b.CT32B2PRE = 0x03; //PCLK = HCLK/8 + //SN_SYS1->APBCP0_b.CT32B2PRE = 0x04; //PCLK = HCLK/16 +} + +/***************************************************************************** +* Function : CT32B2_NvicEnable +* Description : Enable CT32B2 timer interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT32B2_NvicEnable (void) +{ + NVIC_ClearPendingIRQ(CT32B2_IRQn); + NVIC_EnableIRQ(CT32B2_IRQn); + //NVIC_SetPriority(CT32B2_IRQn,0); //Set interrupt priority (default) +} + +/***************************************************************************** +* Function : CT32B2_NvicDisable +* Description : Disable CT32B2 timer interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT32B2_NvicDisable (void) +{ + NVIC_DisableIRQ(CT32B2_IRQn); +} + + +/***************************************************************************** +* Function : TIMER32_0_IRQHandler +* Description : ISR of CT32B2 interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT32B2_IRQHandler(void) +{ + uint32_t iwRisStatus; + + iwRisStatus = SN_CT32B2->RIS; // Save the interrupt status. + + //Before checking the status, always re-check the interrupt enable register first. + //In practice, user might use only one or two timer interrupt source. + //Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary. + //User can add the directive pair of "#if 0" and "#endif" pair + //to COMMENT the un-used parts to reduce ISR overheads and ROM usage. + + //Check the status in oder. + //MR0 + if (SN_CT32B2->MCTRL_b.MR0IE) //Check if MR0 IE enables? + { + if(iwRisStatus & mskCT32_MR0IF) + { + iwCT32B2_IrqEvent |= mskCT32_MR0IF; + SN_CT32B2->IC = mskCT32_MR0IC; //Clear MR0 match interrupt status + } + } + //MR1 + if (SN_CT32B2->MCTRL_b.MR1IE) //Check if MR1 IE enables? + { + if(iwRisStatus & mskCT32_MR1IF) + { + iwCT32B2_IrqEvent |= mskCT32_MR1IF; + SN_CT32B2->IC = mskCT32_MR1IC; //Clear MR1 match interrupt status + } + } + //MR2 + if (SN_CT32B2->MCTRL_b.MR2IE) //Check if MR2 IE enables? + { + if(iwRisStatus & mskCT32_MR2IF) + { + iwCT32B2_IrqEvent |= mskCT32_MR2IF; + SN_CT32B2->IC = mskCT32_MR2IC; //Clear MR2 match interrupt status + } + } + //MR3 + if (SN_CT32B2->MCTRL_b.MR3IE) //Check if MR3 IE enables? + { + if(iwRisStatus & mskCT32_MR3IF) + { + iwCT32B2_IrqEvent |= mskCT32_MR3IF; + SN_CT32B2->IC = mskCT32_MR3IC; //Clear MR3 match interrupt status + } + } + //CAP0 + if (SN_CT32B2->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables? + { + if(iwRisStatus & mskCT32_CAP0IF) //CAP0 + { + iwCT32B2_IrqEvent |= mskCT32_CAP0IF; + SN_CT32B2->IC = mskCT32_CAP0IC; //Clear CAP0 interrupt status + } + } +} + + + diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B2.h b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B2.h new file mode 100644 index 00000000..bcbd7211 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B2.h @@ -0,0 +1,26 @@ +#ifndef __SN32F240_CT32B2_H +#define __SN32F240_CT32B2_H + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +#define CT32B2_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT32B2 timer and interrupt + //POLLING_METHOD: Enable CT32B2 timer ONLY + +/*_____ M A C R O S ________________________________________________________*/ + // Enable CT32B2 PCLK +#define __CT32B2_ENABLE SN_SYS1->AHBCLKEN_b.CT32B2CLKEN = ENABLE + // Disable CT32B2 PCLK +#define __CT32B2_DISABLE SN_SYS1->AHBCLKEN_b.CT32B2CLKEN = DISABLE + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +extern volatile uint32_t iwCT32B2_IrqEvent; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS + +extern void CT32B2_Init(void); +extern void CT32B2_NvicEnable(void); +extern void CT32B2_NvicDisable(void); +extern void CT32B2_IRQHandler(void); +#endif /*__SN32F240_CT32B2_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/driver.mk b/os/hal/ports/SN32/LLD/SN32F24x/CT/driver.mk new file mode 100644 index 00000000..bb1de87c --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/CT/driver.mk @@ -0,0 +1,16 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_CT TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.c +endif + +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B0.c +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B1.c +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B2.c +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B0.c +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B1.c +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B2.c + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.c b/os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.c new file mode 100644 index 00000000..a031d534 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.c @@ -0,0 +1,101 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_st_lld.c + * @brief PLATFORM ST subsystem low level driver source. + * + * @addtogroup ST + * @{ + */ + +#include "hal.h" +#include "CT16.h" +#include "CT16B0.h" +#include "CT16B1.h" +#include "CT16B2.h" +#include "CT32.h" +#include "CT32B0.h" +#include "CT32B1.h" +#include "CT32B2.h" +#include "SN32F240.h" + +#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define IHRC_CLOCK 12000000 +#define ILRC_CLOCK 32000 +#define ELS_XTAL_CLOCK 32768 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +OSAL_IRQ_HANDLER(SysTick_Handler) { + + OSAL_IRQ_PROLOGUE(); + + osalSysLockFromISR(); + osalOsTimerHandlerI(); + osalSysUnlockFromISR(); + + OSAL_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ST driver initialization. + * + * @notapi + */ +void st_lld_init(void) { + /* Periodic systick mode, the Cortex-Mx internal systick timer is used + in this mode.*/ + SysTick->LOAD = ((IHRC_CLOCK >> SN_SYS0->AHBCP) / OSAL_ST_FREQUENCY) - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + /* IRQ enabled.*/ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, 8); +} + +#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.h b/os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.h new file mode 100644 index 00000000..612388e0 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.h @@ -0,0 +1,147 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_st_lld.h + * @brief PLATFORM ST subsystem low level driver header. + * @details This header is designed to be include-able without having to + * include other files from the HAL. + * + * @addtogroup ST + * @{ + */ + +#ifndef HAL_ST_LLD_H +#define HAL_ST_LLD_H + +#include "CT16B0.h" +#include "CT16B1.h" +#include "CT16B2.h" +#include "CT32B0.h" +#include "CT32B1.h" +#include "CT32B2.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void st_lld_init(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Driver inline functions. */ +/*===========================================================================*/ + +/** + * @brief Returns the time counter value. + * + * @return The counter value. + * + * @notapi + */ +static inline systime_t st_lld_get_counter(void) { + return (systime_t)0; +} + +/** + * @brief Starts the alarm. + * @note Makes sure that no spurious alarms are triggered after + * this call. + * + * @param[in] abstime the time to be set for the first alarm + * + * @notapi + */ +static inline void st_lld_start_alarm(systime_t abstime) { + + (void)abstime; +} + +/** + * @brief Stops the alarm interrupt. + * + * @notapi + */ +static inline void st_lld_stop_alarm(void) { + +} + +/** + * @brief Sets the alarm time. + * + * @param[in] abstime the time to be set for the next alarm + * + * @notapi + */ +static inline void st_lld_set_alarm(systime_t abstime) { + + (void)abstime; +} + +/** + * @brief Returns the current alarm time. + * + * @return The currently set alarm time. + * + * @notapi + */ +static inline systime_t st_lld_get_alarm(void) { + + return (systime_t)0; +} + +/** + * @brief Determines if the alarm is active. + * + * @return The alarm status. + * @retval false if the alarm is not active. + * @retval true is the alarm is active + * + * @notapi + */ +static inline bool st_lld_is_alarm_active(void) { + + return false; +} + +#endif /* HAL_ST_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/FLASH/Flash.c b/os/hal/ports/SN32/LLD/SN32F24x/FLASH/Flash.c new file mode 100644 index 00000000..951dc5dd --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/FLASH/Flash.c @@ -0,0 +1,90 @@ +/******************** (C) COPYRIGHT 2013 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2013/12 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: Flash related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include "Flash.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +uint32_t wFLASH_PGRAM[2]; + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + +/***************************************************************************** +* Function : FLASH_EraseSector +* Description : Erase assigned sector address in Flash ROM +* Input : adr - Sector start address +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void FLASH_EraseSector (uint32_t adr) +{ + SN_FLASH->CTRL = FLASH_PER; // Page Erase Enabled + SN_FLASH->ADDR = adr; // Page Address + SN_FLASH->CTRL |= FLASH_STARTE; // Start Erase + + while ((SN_FLASH->STATUS & FLASH_BUSY) == FLASH_BUSY); +} + + +/***************************************************************************** +* Function : Flash_ProgramPage +* Description : Program assigned page in Flash ROM +* Input : adr - Page start address (word-alignment) of Flash +* sz - Content size to be programmed (Bytes) +* pBuf - pointer to the Source data +* Output : None +* Return : OK or FAIL +* Note : None +*****************************************************************************/ +uint32_t FLASH_ProgramPage (uint32_t adr, uint32_t sz, uint8_t *pBuf) +{ + while (sz){ + + SN_FLASH->CTRL = FLASH_PG; // Programming Enabled + SN_FLASH->ADDR = adr; + SN_FLASH->DATA = *((uint32_t *)pBuf); + + __nop();__nop();__nop();__nop();__nop();__nop(); //Must add to avoid Hard Fault!!!!!! + + while ((SN_FLASH->STATUS & FLASH_BUSY) == FLASH_BUSY); + + // Check for Errors + if ((SN_FLASH->STATUS & FLASH_PGERR) == FLASH_PGERR) { + SN_FLASH->STATUS &= ~FLASH_PGERR; + return (FAIL); + } + + // Go to next Word + adr += 4; + pBuf += 4; + sz -= 4; + } + + return (OK); +} + diff --git a/os/hal/ports/SN32/LLD/SN32F24x/FLASH/Flash.h b/os/hal/ports/SN32/LLD/SN32F24x/FLASH/Flash.h new file mode 100644 index 00000000..9b2acb4a --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/FLASH/Flash.h @@ -0,0 +1,44 @@ +#ifndef __SN32F240_FLASH_H +#define __SN32F240_FLASH_H + +/*_____ I N C L U D E S ____________________________________________________*/ +#include "SN32F240.h" +#include "SN32F200_Def.h" + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +//FLASH HW +#define FLASH_PAGE_SIZE 1024 +#define FLASH_F240_MAX_ROM_SIZE 0xFFFF +#define FLASH_F230_MAX_ROM_SIZE 0x7FFF +#define FLASH_F220_MAX_ROM_SIZE 0x3FFF + + +// Flash Control Register definitions +#define FLASH_PG 0x00000001 +#define FLASH_PER 0x00000002 +#define FLASH_STARTE 0x00000040 + +// Flash Status Register definitions +#define FLASH_BUSY 0x00000001 +#define FLASH_PGERR 0x00000004 + + +/*_____ M A C R O S ________________________________________________________*/ + +//Flash Low Power Mode +#define __FLASH_LPM_DISABLE SN_FLASH->LPCTRL = 0x5AFA0000 +#define __FLASH_LPM_SLOW_MODE SN_FLASH->LPCTRL = 0x5AFA0002 + +//Flash Status +#define __FLASH_CLEAR_ERROR_STATUS SN_FLASH->STATUS &= ~FLASH_PGERR + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +extern uint32_t wFLASH_PGRAM[2]; + +void FLASH_EraseSector (uint32_t); +uint32_t FLASH_ProgramPage (uint32_t, uint32_t, uint8_t *); + + +#endif /* __SN32F240_FLASH_H */ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/GPIO/GPIO.c b/os/hal/ports/SN32/LLD/SN32F24x/GPIO/GPIO.c new file mode 100644 index 00000000..9d415472 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/GPIO/GPIO.c @@ -0,0 +1,827 @@ +/******************** (C) COPYRIGHT 2014 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2014/02 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: GPIO related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 1. First release +* 1.1 2014/02/27 SA1 1. Fix error in GPIO_Interrupt. +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include "GPIO.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + +/***************************************************************************** +* Function : GPIO_Init +* Description : GPIO Init +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void GPIO_Init (void) +{ + //P2.0 as Input Pull-down + GPIO_Mode (GPIO_PORT2, GPIO_PIN0, GPIO_MODE_INPUT); + GPIO_Config (GPIO_PORT2, GPIO_PIN0, GPIO_CFG_PULL_DOWN); + //P2.0 as rising edge + GPIO_P2Trigger(GPIO_PIN0, GPIO_IS_EDGE, GPIO_IBS_EDGE_TRIGGER, GPIO_IEV_RISING_EDGE); + GPIO_Interrupt(GPIO_PORT2, GPIO_PIN0, GPIO_IE_EN); + + //P2.1 as Input Pull-up + GPIO_Mode (GPIO_PORT2, GPIO_PIN1, GPIO_MODE_INPUT); + GPIO_Config (GPIO_PORT2, GPIO_PIN1, GPIO_CFG_PULL_UP); + //P2.1 as falling edge + GPIO_P2Trigger(GPIO_PIN1, GPIO_IS_EDGE, GPIO_IBS_EDGE_TRIGGER, GPIO_IEV_FALLING_EDGE); + GPIO_Interrupt(GPIO_PORT2, GPIO_PIN1, GPIO_IE_EN); + + //P2.2 as Input Repeater-mode + GPIO_Mode (GPIO_PORT2, GPIO_PIN2, GPIO_MODE_INPUT); + GPIO_Config (GPIO_PORT2, GPIO_PIN2, GPIO_CFG_REPEATER_MODE); + //P2.2 as both edge + GPIO_P2Trigger(GPIO_PIN2, GPIO_IS_EDGE, GPIO_IBS_BOTH_EDGE_TRIGGER, GPIO_IEV_RISING_EDGE); + GPIO_Interrupt(GPIO_PORT2, GPIO_PIN2, GPIO_IE_EN); + + //P2.3 as Input Pull-down + GPIO_Mode (GPIO_PORT2, GPIO_PIN3, GPIO_MODE_INPUT); + GPIO_Config (GPIO_PORT2, GPIO_PIN3, GPIO_CFG_PULL_DOWN); + //P2.3 as high level + GPIO_P2Trigger(GPIO_PIN3, GPIO_IS_EVENT, GPIO_IBS_EDGE_TRIGGER, GPIO_IEV_RISING_EDGE); + GPIO_Interrupt(GPIO_PORT2, GPIO_PIN3, GPIO_IE_EN); + + //P2.4 as Input Pullup + GPIO_Mode (GPIO_PORT2, GPIO_PIN4, GPIO_MODE_INPUT); + GPIO_Config (GPIO_PORT2, GPIO_PIN4, GPIO_CFG_PULL_UP); + //P2.4 as low level trigger + GPIO_P2Trigger(GPIO_PIN4, GPIO_IS_EVENT, GPIO_IBS_EDGE_TRIGGER, GPIO_IEV_FALLING_EDGE); + GPIO_Interrupt(GPIO_PORT2, GPIO_PIN4, GPIO_IE_EN); + + //P2.5 as Output Low + GPIO_Mode (GPIO_PORT2, GPIO_PIN5, GPIO_MODE_OUTPUT); + GPIO_Clr (GPIO_PORT2, GPIO_PIN5); +} + +/***************************************************************************** +* Function : GPIO_Mode +* Description : set GPIO as input or output +* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3 + pin_number - GPIO_PIN0, 1, 2, ...,15 + mode - 0 as Input + 1 as output +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void GPIO_Mode(uint32_t port_number, uint32_t pin_number, uint32_t mode) +{ + uint32_t wGpiomode=0; + switch(port_number){ + case 0: + wGpiomode=(uint32_t)SN_GPIO0->MODE; + wGpiomode&=~(1<<(uint32_t) pin_number); + wGpiomode|=(mode<<(uint32_t) pin_number); + SN_GPIO0->MODE=wGpiomode; + wGpiomode=SN_GPIO0->MODE; //for checlk + break; + case 1: + wGpiomode=(uint32_t)SN_GPIO1->MODE; + wGpiomode&=~(1<<(uint32_t) pin_number); + wGpiomode|=(mode<<(uint32_t) pin_number); + SN_GPIO1->MODE=wGpiomode; + wGpiomode=SN_GPIO1->MODE; //for checlk + break; + case 2: + wGpiomode=(uint32_t)SN_GPIO2->MODE; + wGpiomode&=~(1<<(uint32_t) pin_number); + wGpiomode|=(mode<<(uint32_t) pin_number); + SN_GPIO2->MODE=wGpiomode; + wGpiomode=SN_GPIO2->MODE; //for checlk + break; + case 3: + wGpiomode=(uint32_t)SN_GPIO3->MODE; + wGpiomode&=~(1<<(uint32_t) pin_number); + wGpiomode|=(mode<<(uint32_t) pin_number); + SN_GPIO3->MODE=wGpiomode; + wGpiomode=SN_GPIO3->MODE; //for checlk + break; + default: + break; + } + return; +} + +/***************************************************************************** +* Function : GPIO_Set +* Description : set GPIO high +* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3 + pin_number - GPIO_PIN0, 1, 2, ...,15 +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void GPIO_Set(uint32_t port_number, uint32_t pin_number) +{ + switch(port_number){ + case 0: + SN_GPIO0->BSET|=(1<BSET|=(1<BSET|=(1<BSET|=(1<BCLR|=(1<BCLR|=(1<BCLR|=(1<BCLR|=(1<IS; + wGpiovalue&=~(1<IS=wGpiovalue; + wGpiovalue=SN_GPIO0->IBS; + wGpiovalue&=~(1<IBS=wGpiovalue; + wGpiovalue=SN_GPIO0->IEV; + wGpiovalue&=~(1<IEV=wGpiovalue; +} + +/***************************************************************************** +* Function : GPIO_P1Trigger +* Description : set GPIO as edge or level trigger +* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3 + pin_number - GPIO_PIN0, 1, 2, ...,15 + is - 0: edge sensitive + 1: event sensitive + ibs - 0: edge trigger + 1: both edge trigger + iev - 0: Rising edges or HIGH level trigger + 1: Falling edges or LOW level trigger +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void GPIO_P1Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev) +{ + uint32_t wGpiovalue=0; + + wGpiovalue=SN_GPIO1->IS; + wGpiovalue&=~(1<IS=wGpiovalue; + wGpiovalue=SN_GPIO1->IBS; + wGpiovalue&=~(1<IBS=wGpiovalue; + wGpiovalue=SN_GPIO1->IEV; + wGpiovalue&=~(1<IEV=wGpiovalue; +} + +/***************************************************************************** +* Function : GPIO_P2Trigger +* Description : set GPIO as edge or level trigger +* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3 + pin_number - GPIO_PIN0, 1, 2, ...,15 + is - 0: edge sensitive + 1: event sensitive + ibs - 0: edge trigger + 1: both edge trigger + iev - 0: Rising edges or HIGH level trigger + 1: Falling edges or LOW level trigger +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void GPIO_P2Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev) +{ + uint32_t wGpiovalue=0; + + wGpiovalue=SN_GPIO2->IS; + wGpiovalue&=~(1<IS=wGpiovalue; + wGpiovalue=SN_GPIO2->IBS; + wGpiovalue&=~(1<IBS=wGpiovalue; + wGpiovalue=SN_GPIO2->IEV; + wGpiovalue&=~(1<IEV=wGpiovalue; +} + +/***************************************************************************** +* Function : GPIO_P3Trigger +* Description : set GPIO as edge or level trigger +* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3 + pin_number - GPIO_PIN0, 1, 2, ...,15 + is - 0: edge sensitive + 1: event sensitive + ibs - 0: edge trigger + 1: both edge trigger + iev - 0: Rising edges or HIGH level trigger + 1: Falling edges or LOW level trigger +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void GPIO_P3Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev) +{ + uint32_t wGpiovalue=0; + + wGpiovalue=SN_GPIO3->IS; + wGpiovalue&=~(1<IS=wGpiovalue; + wGpiovalue=SN_GPIO3->IBS; + wGpiovalue&=~(1<IBS=wGpiovalue; + wGpiovalue=SN_GPIO3->IEV; + wGpiovalue&=~(1<IEV=wGpiovalue; +} + +/***************************************************************************** +* Function : GPIO_Interrupt +* Description : set GPIO interrupt and NVIC +* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3 + pin_number - GPIO_PIN0, 1, 2, ...,15 + enable - 0 as disable + 1 as enable +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void GPIO_Interrupt(uint32_t port_number, uint32_t pin_number, uint32_t enable) +{ + switch(port_number){ + case 0: + //check SWD pin + if ((pin_number == GPIO_PIN8) || (pin_number == GPIO_PIN9)){ + if(SN_SYS0->SWDCTRL!=0x1) return; + } + SN_GPIO0->IC=0xFFFF; + SN_GPIO0->IE&=~(1<IE|=(enable<IE&=~(1<IE|=(enable<IC=0xFFFF; + NVIC_ClearPendingIRQ(P1_IRQn); + NVIC_EnableIRQ(P1_IRQn); + break; + case 2: + SN_GPIO2->IC=0xFFFF; + SN_GPIO2->IE&=~(1<IE|=(enable<EXRSTCTRL!=1) return; + } + SN_GPIO3->IC=0xFFFF; + SN_GPIO3->IE&=~(1<IE|=(enable<IC=(1<IC=(1<IC=(1<IC=(1<CFG&=~(3<CFG|=(value<CFG&=~(3<CFG|=(value<CFG&=~(3<CFG|=(value<CFG&=~(3<CFG|=(value<ODCTRL&=~(1<ODCTRL|=(value<ODCTRL=~(1<ODCTRL|=(value<ODCTRL=~(1<ODCTRL|=(value<ODCTRL=~(1<ODCTRL|=(value<RIS >>pin_number); + break; + case 1: + wreturn_value=(SN_GPIO1->RIS >>pin_number); + break; + case 2: + wreturn_value=(SN_GPIO2->RIS >>pin_number); + break; + case 3: + wreturn_value=(SN_GPIO3->RIS >>pin_number); + break; + default: + break; + } + wreturn_value&=0x01; + return wreturn_value; +} + + +/***************************************************************************** +* Function : P0_IRQHandler +* Description : Set GPIO P0 IRQ +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void P0_IRQHandler(void) +{ + if (GPIO_IntStatus(GPIO_PORT0,GPIO_PIN0)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN0); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN1)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN1); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN2)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN2); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN3)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN3); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN4)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN4); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN5)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN5); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN6)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN6); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN7)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN7); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN8)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN8); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN9)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN9); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN10)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN10); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN11)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN11); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN12)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN12); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN13)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN13); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN14)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN14); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN15)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN15); + } +} + +/***************************************************************************** +* Function : P1_IRQHandler +* Description : Set GPIO P1 IRQ +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void P1_IRQHandler(void) +{ + if (GPIO_IntStatus(GPIO_PORT1,GPIO_PIN0)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN0); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN1)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN1); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN2)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN2); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN3)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN3); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN4)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN4); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN5)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN5); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN6)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN6); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN7)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN7); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN8)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN8); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN9)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN9); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN10)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN10); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN11)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN11); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN12)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN12); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN13)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN13); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN14)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN14); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN15)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN15); + } +} + +/***************************************************************************** +* Function : P2_IRQHandler +* Description : Set GPIO P2 IRQ +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void P2_IRQHandler(void) +{ + if (GPIO_IntStatus(GPIO_PORT2,GPIO_PIN0)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN0); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN1)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN1); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN2)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN2); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN3)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN3); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN4)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN4); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN5)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN5); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN6)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN6); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN7)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN7); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN8)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN8); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN9)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN9); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN10)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN10); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN11)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN11); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN12)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN12); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN13)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN13); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN14)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN14); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN15)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN15); + } +} + +/***************************************************************************** +* Function : P3_IRQHandler +* Description : Set GPIO P3 IRQ +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void P3_IRQHandler(void) +{ + if (GPIO_IntStatus(GPIO_PORT3,GPIO_PIN0)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN0); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN1)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN1); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN2)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN2); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN3)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN3); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN4)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN4); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN5)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN5); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN6)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN6); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN7)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN7); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN8)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN8); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN9)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN9); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN10)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN10); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN11)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN11); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN12)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN12); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN13)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN13); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN14)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN14); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN15)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN15); + } +} + diff --git a/os/hal/ports/SN32/LLD/SN32F24x/GPIO/GPIO.h b/os/hal/ports/SN32/LLD/SN32F24x/GPIO/GPIO.h new file mode 100644 index 00000000..86fb277d --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/GPIO/GPIO.h @@ -0,0 +1,114 @@ +#ifndef __SN32F240_GPIO_H +#define __SN32F240_GPIO_H + +/*_____ I N C L U D E S ____________________________________________________*/ +#include + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +/* +Base Address: 0x4004 4000 (GPIO 0) + 0x4004 6000 (GPIO 1) + 0x4004 8000 (GPIO 2) + 0x4004 A000 (GPIO 3) +*/ + +/* GPIO Port n Data register (0x00) */ + + +/* GPIO Port n Mode register (0x04) */ +#define GPIO_MODE_INPUT 0 +#define GPIO_MODE_OUTPUT 1 + +#define GPIO_CURRENT_10MA 0 +#define GPIO_CURRENT_20MA 1 + +/* GPIO Port n Configuration register (0x08) */ +#define GPIO_CFG_PULL_UP 0 +#define GPIO_CFG_PULL_DOWN 1 +#define GPIO_CFG_PULL_INACTIVE 2 +#define GPIO_CFG_REPEATER_MODE 3 + +/* GPIO Port n Interrupt Sense register (0x0C) */ +#define GPIO_IS_EDGE 0 +#define GPIO_IS_EVENT 1 + + +/* GPIO Port n Interrupt Both-edge Sense registe (0x10) */ +#define GPIO_IBS_EDGE_TRIGGER 0 +#define GPIO_IBS_BOTH_EDGE_TRIGGER 1 + + +/* GPIO Port n Interrupt Event register (0x14) */ +#define GPIO_IEV_RISING_EDGE 0 +#define GPIO_IEV_FALLING_EDGE 1 + + +/* GPIO Port n Interrupt Enable register (0x18) */ +#define GPIO_IE_DIS 0 +#define GPIO_IE_EN 1 + + +/* GPIO Port n Raw Interrupt Status register (0x1C/0x20) */ +#define mskPIN0IF (0x1<<0) +#define mskPIN1IF (0x1<<1) +#define mskPIN2IF (0x1<<2) +#define mskPIN3IF (0x1<<3) +#define mskPIN4IF (0x1<<4) +#define mskPIN5IF (0x1<<5) +#define mskPIN6IF (0x1<<6) +#define mskPIN7IF (0x1<<7) +#define mskPIN8IF (0x1<<8) +#define mskPIN9IF (0x1<<9) +#define mskPIN10IF (0x1<<10) +#define mskPIN11IF (0x1<<11) +#define mskPIN12IF (0x1<<12) +#define mskPIN13IF (0x1<<13) +#define mskPIN14IF (0x1<<14) +#define mskPIN15IF (0x1<<15) + + +/* GPIO Port Name Define */ +//GPIO name define +#define GPIO_PORT0 0 +#define GPIO_PORT1 1 +#define GPIO_PORT2 2 +#define GPIO_PORT3 3 + +/* GPIO Pin Name Define */ +#define GPIO_PIN0 0 +#define GPIO_PIN1 1 +#define GPIO_PIN2 2 +#define GPIO_PIN3 3 +#define GPIO_PIN4 4 +#define GPIO_PIN5 5 +#define GPIO_PIN6 6 +#define GPIO_PIN7 7 +#define GPIO_PIN8 8 +#define GPIO_PIN9 9 +#define GPIO_PIN10 10 +#define GPIO_PIN11 11 +#define GPIO_PIN12 12 +#define GPIO_PIN13 13 +#define GPIO_PIN14 14 +#define GPIO_PIN15 15 + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +void GPIO_Init (void); +void GPIO_Mode(uint32_t port_number, uint32_t pin_number, uint32_t mode); +void GPIO_Set(uint32_t port_number, uint32_t pin_number); +void GPIO_Clr(uint32_t port_number, uint32_t pin_number); +void GPIO_P0Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev); +void GPIO_P1Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev); +void GPIO_P2Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev); +void GPIO_P3Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev); +void GPIO_Interrupt(uint32_t port_number, uint32_t pin_number, uint32_t enable); +void GPIO_IntClr(uint32_t port_number, uint32_t pin_number); +void GPIO_Config(uint32_t port_number, uint32_t pin_number, uint32_t value); +void GPIO_OpenDrain(uint32_t port_number, uint32_t pin_number, uint32_t value); +uint32_t GPIO_IntStatus(uint32_t port_number, uint32_t pin_number); +#endif /*__SN32F240_GPIO_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/GPIO/driver.mk b/os/hal/ports/SN32/LLD/SN32F24x/GPIO/driver.mk new file mode 100644 index 00000000..24d83b08 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/GPIO/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/GPIO/hal_pal_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/GPIO/hal_pal_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/GPIO \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F24x/GPIO/hal_pal_lld.c b/os/hal/ports/SN32/LLD/SN32F24x/GPIO/hal_pal_lld.c new file mode 100644 index 00000000..5935e92d --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/GPIO/hal_pal_lld.c @@ -0,0 +1,147 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file GPIOv3/hal_pal_lld.c + * @brief SN32 PAL low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void initgpio(SN_GPIO0_Type *gpiop, const sn32_gpio_setup_t *config) { + + gpiop->DATA = config->data; + gpiop->MODE = config->mode; + gpiop->CFG = config->cfg; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief SN32 I/O ports configuration. + * @details Ports A-D clocks enabled. + * + * @param[in] config the SN32 ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + /* + * Initial GPIO setup. + */ + +#if SN32_HAS_GPIOA + initgpio(GPIOA, &config->PAData); +#endif +#if SN32_HAS_GPIOB + initgpio(GPIOB, &config->PBData); +#endif +#if SN32_HAS_GPIOC + initgpio(GPIOC, &config->PCData); +#endif +#if SN32_HAS_GPIOD + initgpio(GPIOD, &config->PDData); +#endif + +} + +/** + * @brief Pad mode setup. + * @details This function programs a pad + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum + * speed. + * + * @param[in] port the port identifier + * @param[in] pad the pad number + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setpadmode(ioportid_t port, + uint32_t pad, + iomode_t mode) { + + switch (mode) + { + + case PAL_MODE_UNCONNECTED: + break; + + case PAL_MODE_INPUT: + port->MODE &= ~(1 << pad); + break; + + case PAL_MODE_INPUT_PULLUP: + port->MODE &= ~(1 << pad); + port->CFG &= ~(3 << (pad * 2)); + // port->BSET = (1 << pad); // High 1 + break; + + case PAL_MODE_INPUT_PULLDOWN: + port->MODE &= ~(1 << pad); + port->CFG &= ~(3 << (pad * 2)); + // port->BCLR = (1 << pad); // Low 0 + break; + + case PAL_MODE_INPUT_ANALOG: + port->MODE &= ~(1 << pad); + port->CFG &= ~(3 << (pad * 2)); + break; + + case PAL_MODE_OUTPUT_PUSHPULL: + port->MODE |= (1 << pad); + break; + + case 7: + break; + + default: + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/GPIO/hal_pal_lld.h b/os/hal/ports/SN32/LLD/SN32F24x/GPIO/hal_pal_lld.h new file mode 100644 index 00000000..ba737998 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/GPIO/hal_pal_lld.h @@ -0,0 +1,423 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file GPIOv3/hal_pal_lld.h + * @brief SN32 PAL low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef HAL_PAL_LLD_H +#define HAL_PAL_LLD_H + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +// /* Specifies palInit() without parameter, required until all platforms will +// be updated to the new style.*/ +// // #define PAL_NEW_INIT + + +/* Discarded definitions from the ST headers, the PAL driver uses its own + definitions in order to have an unified handling for all devices. + Unfortunately the ST headers have no uniform definitions for the same + objects across the various sub-families.*/ +#undef GPIOA +#undef GPIOB +#undef GPIOC +#undef GPIOD + +/** + * @name GPIO ports definitions + * @{ + */ +#define GPIOA ((SN_GPIO0_Type *)SN_GPIO0_BASE)// SN_GPIO0// +#define GPIOB ((SN_GPIO0_Type *)SN_GPIO1_BASE)// SN_GPIO1// +#define GPIOC ((SN_GPIO0_Type *)SN_GPIO2_BASE)// SN_GPIO2// +#define GPIOD ((SN_GPIO0_Type *)SN_GPIO3_BASE)// SN_GPIO3// + +/** @} */ + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @name Port related definitions + * @{ + */ +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 16 + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) +/** @} */ + +// GPIO0 = 40044000 +// pad = 5 + +// line = 40044005 + +/** + * @name Line handling macros + * @{ + */ +/** + * @brief Forms a line identifier. + * @details A port/pad pair are encoded into an @p ioline_t type. The encoding + * of this type is platform-dependent. + * @note In this driver the pad number is encoded in the lower 4 bits of + * the GPIO address which are guaranteed to be zero. + */ +#define PAL_LINE(port, pad) \ + ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad))) + +/** + * @brief Decodes a port identifier from a line identifier. + */ +#define PAL_PORT(line) \ + ((SN_GPIO0_Type *)(((uint32_t)(line)) & 0xFFFFFFF0U)) + +/** + * @brief Decodes a pad identifier from a line identifier. + */ +#define PAL_PAD(line) \ + ((uint32_t)((uint32_t)(line) & 0x0000000FU)) + +/** + * @brief Value identifying an invalid line. + */ +#define PAL_NOLINE 0U +/** @} */ + +/** + * @brief GPIO port setup info. + */ +typedef struct { + /** Initial value for DATA register.*/ + uint32_t data; + /** Initial value for MODE register.*/ + uint32_t mode; + /** Initial value for CFG register.*/ + uint32_t cfg; + /** Initial value for IS register.*/ + uint32_t is; + /** Initial value for IBS register.*/ + uint32_t ibs; + /** Initial value for IEV register.*/ + uint32_t iev; + /** Initial value for IE register.*/ + uint32_t ie; + /** Initial value for RIS register.*/ + uint32_t ris; + /** Initial value for IC register.*/ + uint32_t ic; + /** Initial value for BSET register.*/ + uint32_t bset; + /** Initial value for BCLR register.*/ + uint32_t bclr; +} sn32_gpio_setup_t; + +/** + * @brief SN32 GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialize the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { +#if SN32_HAS_GPIOA || defined(__DOXYGEN__) + /** @brief Port A setup data.*/ + sn32_gpio_setup_t PAData; +#endif +#if SN32_HAS_GPIOB || defined(__DOXYGEN__) + /** @brief Port B setup data.*/ + sn32_gpio_setup_t PBData; +#endif +#if SN32_HAS_GPIOC || defined(__DOXYGEN__) + /** @brief Port C setup data.*/ + sn32_gpio_setup_t PCData; +#endif +#if SN32_HAS_GPIOD || defined(__DOXYGEN__) + /** @brief Port D setup data.*/ + sn32_gpio_setup_t PDData; +#endif +} PALConfig; + +/** + * @brief Type of digital I/O port sized unsigned integer. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Type of digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Type of an I/O line. + */ +typedef uint32_t ioline_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef SN_GPIO0_Type * ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/* The low level driver wraps the definitions already present in the SN32 */ +/* firmware library. */ +/*===========================================================================*/ + +/** + * @brief GPIO port A identifier. + */ +#if SN32_HAS_GPIOA || defined(__DOXYGEN__) +#define IOPORT1 GPIOA +#endif + +/** + * @brief GPIO port B identifier. + */ +#if SN32_HAS_GPIOB || defined(__DOXYGEN__) +#define IOPORT2 GPIOB +#endif + +/** + * @brief GPIO port C identifier. + */ +#if SN32_HAS_GPIOC || defined(__DOXYGEN__) +#define IOPORT3 GPIOC +#endif + +/** + * @brief GPIO port D identifier. + */ +#if SN32_HAS_GPIOD || defined(__DOXYGEN__) +#define IOPORT4 GPIOD +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->DATA) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +// #define pal_lld_readlatch(port) ((port)->RIS) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->DATA = (uint16_t)(bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((port)->BSET = (uint16_t)(bits)) + +/** + * @brief Clears a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((port)->BCLR = ~(uint16_t)(bits)) + +/** + * @brief Writes a group of bits. + * @details This function is implemented by writing the GPIO BSET register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset the group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group + * width are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) { \ + uint32_t w = ((~(uint32_t)(bits) & (uint32_t)(mask)) << (16U + (offset))) | \ + ((uint32_t)(bits) & (uint32_t)(mask)) << (offset); \ + (port)->DATA = w; \ +} + +/** + * @brief Reads a logical state from an I/O pad. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @return The logical state. + * @retval PAL_LOW low logical state. + * @retval PAL_HIGH high logical state. + * + * @notapi + */ +#define pal_lld_readpad(port, pad) (((port)->DATA >> pad) & 1) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) ((port)->DATA = (bit << pad)) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) ((port)->BSET = (0x1 << pad)) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) ((port)->BCLR = (0x1 << pad)) + +/** + * @brief Toggles a pad logical state. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +// #define pal_lld_togglepad(port, pad) + +/** + * @brief Pad mode setup. + * @details This function programs a pad with the specified mode. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad mode + * + * @notapi + */ +// #define pal_lld_setpadmode(port, pad, mode) ((port)->MODE |= mode << pad) + +#define pal_lld_setpadmode(port, pad, mode) \ + _pal_lld_setpadmode(port, pad, mode) + +#ifdef __cplusplus +extern "C" { +#endif + extern const PALConfig pal_default_config; + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setpadmode(ioportid_t port, + uint32_t pad, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* HAL_PAL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/driver.mk b/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/driver.mk new file mode 100644 index 00000000..74bc4b73 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/hal_pal_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/hal_pal_lld.c +endif + +PLATFORMINC += $(CHIBIOS)/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3 diff --git a/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/hal_pal_lld.c b/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/hal_pal_lld.c new file mode 100644 index 00000000..2804ef6b --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/hal_pal_lld.c @@ -0,0 +1,181 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file GPIOv3/hal_pal_lld.c + * @brief SN32 PAL low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if defined(SN32F240B) +#define AHB2_EN_MASK SN32_GPIO_EN_MASK +#define AHB2_LPEN_MASK 0 + +#else +#error "missing or unsupported platform for GPIOv3 PAL driver" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void initgpio(sn32_gpio_t *gpiop, const sn32_gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->ASCR = config->ascr; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; + gpiop->LOCKR = config->lockr; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief SN32 I/O ports configuration. + * @details Ports A-D(E, F, G, H) clocks enabled. + * + * @param[in] config the SN32 ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + /* + * Enables the GPIO related clocks. + */ +#if defined(SN32L4XX) + RCC->AHB2ENR |= AHB2_EN_MASK; +#endif + + /* + * Initial GPIO setup. + */ +#if SN32_HAS_GPIOA + initgpio(GPIOA, &config->PAData); +#endif +#if SN32_HAS_GPIOB + initgpio(GPIOB, &config->PBData); +#endif +#if SN32_HAS_GPIOC + initgpio(GPIOC, &config->PCData); +#endif +#if SN32_HAS_GPIOD + initgpio(GPIOD, &config->PDData); +#endif +#if SN32_HAS_GPIOE + initgpio(GPIOE, &config->PEData); +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum + * speed. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + uint32_t moder = (mode & PAL_SN32_MODE_MASK) >> 0; + uint32_t otyper = (mode & PAL_SN32_OTYPE_MASK) >> 2; + uint32_t ospeedr = (mode & PAL_SN32_OSPEED_MASK) >> 3; + uint32_t pupdr = (mode & PAL_SN32_PUPDR_MASK) >> 5; + uint32_t altr = (mode & PAL_SN32_ALTERNATE_MASK) >> 7; + uint32_t ascr = (mode & PAL_SN32_ASCR_MASK) >> 11; + uint32_t lockr = (mode & PAL_SN32_LOCKR_MASK) >> 12; + uint32_t bit = 0; + while (true) { + if ((mask & 1) != 0) { + uint32_t altrmask, m1, m2, m4; + + altrmask = altr << ((bit & 7) * 4); + m1 = 1 << bit; + m2 = 3 << (bit * 2); + m4 = 15 << ((bit & 7) * 4); + port->OTYPER = (port->OTYPER & ~m1) | otyper; + port->ASCR = (port->ASCR & ~m1) | ascr; + port->OSPEEDR = (port->OSPEEDR & ~m2) | ospeedr; + port->PUPDR = (port->PUPDR & ~m2) | pupdr; + if ((mode & PAL_SN32_MODE_MASK) == PAL_SN32_MODE_ALTERNATE) { + /* If going in alternate mode then the alternate number is set + before switching mode in order to avoid glitches.*/ + if (bit < 8) + port->AFRL = (port->AFRL & ~m4) | altrmask; + else + port->AFRH = (port->AFRH & ~m4) | altrmask; + port->MODER = (port->MODER & ~m2) | moder; + } + else { + /* If going into a non-alternate mode then the mode is switched + before setting the alternate mode in order to avoid glitches.*/ + port->MODER = (port->MODER & ~m2) | moder; + if (bit < 8) + port->AFRL = (port->AFRL & ~m4) | altrmask; + else + port->AFRH = (port->AFRH & ~m4) | altrmask; + } + port->LOCKR = (port->LOCKR & ~m1) | lockr; + } + mask >>= 1; + if (!mask) + return; + otyper <<= 1; + ospeedr <<= 2; + pupdr <<= 2; + moder <<= 2; + bit++; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/hal_pal_lld.h b/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/hal_pal_lld.h new file mode 100644 index 00000000..9e118a6d --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/hal_pal_lld.h @@ -0,0 +1,480 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file GPIOv3/hal_pal_lld.h + * @brief SN32 PAL low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef HAL_PAL_LLD_H +#define HAL_PAL_LLD_H + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_RESET +#undef PAL_MODE_UNCONNECTED +#undef PAL_MODE_INPUT +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_PUSHPULL +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/** + * @name SN32-specific I/O mode flags + * @{ + */ +#define PAL_SN32_MODE_MASK (3U << 0U) +#define PAL_SN32_MODE_INPUT (0U << 0U) +#define PAL_SN32_MODE_OUTPUT (1U << 0U) +#define PAL_SN32_MODE_ALTERNATE (2U << 0U) +#define PAL_SN32_MODE_ANALOG (3U << 0U) + +#define PAL_SN32_OTYPE_MASK (1U << 2U) +#define PAL_SN32_OTYPE_PUSHPULL (0U << 2U) +#define PAL_SN32_OTYPE_OPENDRAIN (1U << 2U) + +#define PAL_SN32_OSPEED_MASK (3U << 3U) +#define PAL_SN32_OSPEED_LOW (0U << 3U) +#define PAL_SN32_OSPEED_MEDIUM (1U << 3U) +#define PAL_SN32_OSPEED_FAST (2U << 3U) +#define PAL_SN32_OSPEED_HIGH (3U << 3U) + +#define PAL_SN32_PUPDR_MASK (3U << 5U) +#define PAL_SN32_PUPDR_FLOATING (0U << 5U) +#define PAL_SN32_PUPDR_PULLUP (1U << 5U) +#define PAL_SN32_PUPDR_PULLDOWN (2U << 5U) + +#define PAL_SN32_ALTERNATE_MASK (15U << 7U) +#define PAL_SN32_ALTERNATE(n) ((n) << 7U) + +#define PAL_SN32_ASCR_MASK (1U << 11U) +#define PAL_SN32_ASCR_OFF (0U << 11U) +#define PAL_SN32_ASCR_ON (1U << 11U) + +#define PAL_SN32_LOCKR_MASK (1U << 12U) +#define PAL_SN32_LOCKR_OFF (0U << 12U) +#define PAL_SN32_LOCKR_ON (1U << 12U) + +/** + * @brief Alternate function. + * + * @param[in] n alternate function selector + */ +#define PAL_MODE_ALTERNATE(n) (PAL_SN32_MODE_ALTERNATE | \ + PAL_SN32_ALTERNATE(n)) +/** @} */ + +/** + * @name Standard I/O mode flags + * @{ + */ +/** + * @brief Implemented as input. + */ +#define PAL_MODE_RESET PAL_SN32_MODE_INPUT + +/** + * @brief Implemented as analog with analog switch disabled and lock. + */ +#define PAL_MODE_UNCONNECTED (PAL_SN32_MODE_ANALOG | \ + PAL_SN32_ASCR_OFF | \ + PAL_SN32_LOCKR_ON) + +/** + * @brief Regular input high-Z pad. + */ +#define PAL_MODE_INPUT PAL_SN32_MODE_INPUT + +/** + * @brief Input pad with weak pull up resistor. + */ +#define PAL_MODE_INPUT_PULLUP (PAL_SN32_MODE_INPUT | \ + PAL_SN32_PUPDR_PULLUP) + +/** + * @brief Input pad with weak pull down resistor. + */ +#define PAL_MODE_INPUT_PULLDOWN (PAL_SN32_MODE_INPUT | \ + PAL_SN32_PUPDR_PULLDOWN) + +/** + * @brief Analog input mode. + */ +#define PAL_MODE_INPUT_ANALOG (PAL_SN32_MODE_ANALOG | \ + PAL_SN32_ASCR_ON) + +/** + * @brief Push-pull output pad. + */ +#define PAL_MODE_OUTPUT_PUSHPULL (PAL_SN32_MODE_OUTPUT | \ + PAL_SN32_OTYPE_PUSHPULL) + +/** + * @brief Open-drain output pad. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_SN32_MODE_OUTPUT | \ + PAL_SN32_OTYPE_OPENDRAIN) +/** @} */ + +/* Discarded definitions from the ST headers, the PAL driver uses its own + definitions in order to have an unified handling for all devices. + Unfortunately the ST headers have no uniform definitions for the same + objects across the various sub-families.*/ +#undef GPIOA +#undef GPIOB +#undef GPIOC +#undef GPIOD + +/** + * @name GPIO ports definitions + * @{ + */ +#define GPIOA ((sn32_gpio_t *)GPIOA_BASE) +#define GPIOB ((sn32_gpio_t *)GPIOB_BASE) +#define GPIOC ((sn32_gpio_t *)GPIOC_BASE) +#define GPIOD ((sn32_gpio_t *)GPIOD_BASE) +/** @} */ + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @name Port related definitions + * @{ + */ +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 16 + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) +/** @} */ + +/** + * @name Line handling macros + * @{ + */ +/** + * @brief Forms a line identifier. + * @details A port/pad pair are encoded into an @p ioline_t type. The encoding + * of this type is platform-dependent. + * @note In this driver the pad number is encoded in the lower 4 bits of + * the GPIO address which are guaranteed to be zero. + */ +#define PAL_LINE(port, pad) \ + ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad))) + +/** + * @brief Decodes a port identifier from a line identifier. + */ +#define PAL_PORT(line) \ + ((sn32_gpio_t *)(((uint32_t)(line)) & 0xFFFFFFF0U)) + +/** + * @brief Decodes a pad identifier from a line identifier. + */ +#define PAL_PAD(line) \ + ((uint32_t)((uint32_t)(line) & 0x0000000FU)) + +/** + * @brief Value identifying an invalid line. + */ +#define PAL_NOLINE 0U +/** @} */ + +/** + * @brief SN32 GPIO registers block. + */ +typedef struct { + + volatile uint32_t MODER; + volatile uint32_t OTYPER; + volatile uint32_t OSPEEDR; + volatile uint32_t PUPDR; + volatile uint32_t IDR; + volatile uint32_t ODR; + volatile union { + uint32_t W; + struct { + uint16_t set; + uint16_t clear; + } H; + } BSRR; + volatile uint32_t LOCKR; + volatile uint32_t AFRL; + volatile uint32_t AFRH; + volatile uint32_t BRR; + volatile uint32_t ASCR; +} sn32_gpio_t; + +/** + * @brief GPIO port setup info. + */ +typedef struct { + /** Initial value for MODER register.*/ + uint32_t moder; + /** Initial value for OTYPER register.*/ + uint32_t otyper; + /** Initial value for OSPEEDR register.*/ + uint32_t ospeedr; + /** Initial value for PUPDR register.*/ + uint32_t pupdr; + /** Initial value for ODR register.*/ + uint32_t odr; + /** Initial value for AFRL register.*/ + uint32_t afrl; + /** Initial value for AFRH register.*/ + uint32_t afrh; + /** Initial value for ASCR register.*/ + uint32_t ascr; + /** Initial value for LOCKR register.*/ + uint32_t lockr; +} sn32_gpio_setup_t; + +/** + * @brief SN32 GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialize the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { +#if SN32_HAS_GPIOA || defined(__DOXYGEN__) + /** @brief Port A setup data.*/ + sn32_gpio_setup_t PAData; +#endif +#if SN32_HAS_GPIOB || defined(__DOXYGEN__) + /** @brief Port B setup data.*/ + sn32_gpio_setup_t PBData; +#endif +#if SN32_HAS_GPIOC || defined(__DOXYGEN__) + /** @brief Port C setup data.*/ + sn32_gpio_setup_t PCData; +#endif +#if SN32_HAS_GPIOD || defined(__DOXYGEN__) + /** @brief Port D setup data.*/ + sn32_gpio_setup_t PDData; +#endif +} PALConfig; + +/** + * @brief Type of digital I/O port sized unsigned integer. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Type of digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Type of an I/O line. + */ +typedef uint32_t ioline_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef sn32_gpio_t * ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/* The low level driver wraps the definitions already present in the SN32 */ +/* firmware library. */ +/*===========================================================================*/ + +/** + * @brief GPIO port A identifier. + */ +#if SN32_HAS_GPIOA || defined(__DOXYGEN__) +#define IOPORT1 GPIOA +#endif + +/** + * @brief GPIO port B identifier. + */ +#if SN32_HAS_GPIOB || defined(__DOXYGEN__) +#define IOPORT2 GPIOB +#endif + +/** + * @brief GPIO port C identifier. + */ +#if SN32_HAS_GPIOC || defined(__DOXYGEN__) +#define IOPORT3 GPIOC +#endif + +/** + * @brief GPIO port D identifier. + */ +#if SN32_HAS_GPIOD || defined(__DOXYGEN__) +#define IOPORT4 GPIOD +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief GPIO ports subsystem initialization. + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads an I/O port. + * @details This function is implemented by reading the GPIO IDR register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->IDR) + +/** + * @brief Reads the output latch. + * @details This function is implemented by reading the GPIO ODR register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->ODR) + +/** + * @brief Writes on a I/O port. + * @details This function is implemented by writing the GPIO ODR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->ODR = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((port)->BSRR.H.set = (uint16_t)(bits)) + +/** + * @brief Clears a bits mask on a I/O port. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((port)->BSRR.H.clear = (uint16_t)(bits)) + +/** + * @brief Writes a group of bits. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset the group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group + * width are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + ((port)->BSRR.W = ((~(bits) & (mask)) << (16U + (offset))) | \ + (((bits) & (mask)) << (offset))) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) + +extern const PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* HAL_PAL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/I2C/I2C.h b/os/hal/ports/SN32/LLD/SN32F24x/I2C/I2C.h new file mode 100644 index 00000000..8bcf6dae --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/I2C/I2C.h @@ -0,0 +1,274 @@ +#ifndef __SN32F240_I2C_H +#define __SN32F240_I2C_H + +/*_____ I N C L U D E S ____________________________________________________*/ + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +/* +Base Address: 0x4001 8000 (I2C0) + 0x4005 A000 (I2C1) +*/ + +/* I2C n Control register (0x00) */ + //[1:1]Assert NACK (HIGH level to SDA) flag +#define I2C_NACK_NOFUNCTION 0 //No function +#define I2C_NACK 1 //An NACK will be returned during the acknowledge clock pulse on SCLn +#define mskI2C_NACK_NOFUNCTION (I2C_NACK_NOFUNCTION<<1) +#define mskI2C_NACK (I2C_NACK<<1) + + //[2:2]Assert ACK (Low level to SDA) flag +#define I2C_ACK_NOFUNCTION 0 //No function +#define I2C_ACK 1 //An ACK will be returned during the acknowledge clock pulse on SCLn +#define mskI2C_ACK_NOFUNCTION (I2C_ACK_NOFUNCTION<<2) +#define mskI2C_ACK (I2C_ACK<<2) + + //[4:4]STOP flag +#define I2C_STO_IDLE 0 //Stop condition idle +#define I2C_STO_STOP 1 //Transmit a STOP condition in master mode, or recover from an error condition in slave mode. +#define mskI2C_STO_IDLE (I2C_STO_IDLE<<4) +#define mskI2C_STO_STOP (I2C_STO_STOP<<4) + + //[5:5]START bit +#define I2C_STA_IDLE 0 //No START condition or Repeated START condition will be generated +#define I2C_STA_START 1 //transmit a START or a Repeated START condition +#define mskI2C_STA_IDLE (I2C_STA_IDLE<<5) +#define mskI2C_STA_START (I2C_STA_START<<5) + +#define I2C_I2CEN_DIS 0 //[8:8]I2C Interface enable bit +#define I2C_I2CEN_EN 1 +#define mskI2C_I2CEN_DIS (I2C_I2CEN_DIS<<8) +#define mskI2C_I2CEN_EN (I2C_I2CEN_EN<<8) + + +/* I2C n Status register (0x04) */ + //[0:0]RX done status +#define I2C_RX_DN_NO_HANDSHAKE 0 //No RX with ACK/NACK transfer +#define I2C_RX_DN_HANDSHAKE 1 //8-bit RX with ACK/NACK transfer is done +#define mskI2C_RX_DN_NO_HANDSHAKE (I2C_RX_DN_NO_HANDSHAKE<<0) +#define mskI2C_RX_DN_HANDSHAKE (I2C_RX_DN_HANDSHAKE<<0) + + //[1:1]ACK done status +#define I2C_ACK_STAT_NO_RECEIVED_ACK 0 //Not received an ACK +#define I2C_ACK_STAT_RECEIVED_ACK 1 //Received an ACK +#define mskI2C_ACK_STAT_NO_RECEIVED_ACK (I2C_ACK_STAT_NO_RECEIVED_ACK<<1) +#define mskI2C_ACK_STAT_RECEIVED_ACK (I2C_ACK_STAT_RECEIVED_ACK<<1) + + + //[2:2]NACK done status +#define I2C_NACK_STAT_NO_RECEIVED_NACK 0 //Not received a NACK +#define I2C_NACK_STAT_RECEIVED_NACK 1 //Received a NACK +#define mskI2C_NACK_STAT_NO_RECEIVED_NACK (I2C_NACK_STAT_NO_RECEIVED_NACK<<2) +#define mskI2C_NACK_STAT_RECEIVED_NACK (I2C_NACK_STAT_RECEIVED_NACK<<2) + + //[3:3]Stop done status +#define I2C_STOP_DN_NO_STOP 0 //No STOP bit +#define I2C_STOP_DN_STOP 1 //MASTER mode, a STOP condition was issued + //SLAVE mode, a STOP condition was received +#define mskI2C_STOP_DN_NO_STOP (I2C_STOP_DN_NO_STOP<<3) +#define mskI2C_STOP_DN_STOP (I2C_STOP_DN_STOP<<3) + + //[4:4]Start done status +#define I2C_START_DN_NO_START 0 //No START bit +#define I2C_START_DN_START 1 //MASTER mode, a START bit was issued + //SLAVE mode, a START bit was received +#define mskI2C_START_DN_NO_START (I2C_START_DN_NO_START<<4) +#define mskI2C_START_DN_START (I2C_START_DN_START<<4) + + +#define I2C_MST_SLAVE 0 //[5:5]Master/Slave status +#define I2C_MST_MASTER 1 +#define mskI2C_MST_SLAVE (I2C_MST_SLAVE<<5) +#define mskI2C_MST_MASTER (I2C_MST_MASTER<<5) + +#define mskI2C_STA_STA_STO ((I2C_START_DN_START<<4)|(I2C_STOP_DN_STOP<<3)) +#define mskI2C_STA_MASTER_STA_STO ((I2C_MST_MASTER<<5)|(I2C_START_DN_START<<4)|(I2C_STOP_DN_STOP<<3)) + + + //[6:6]Slave address check +#define I2C_SLV_RX_NO_MATCH_ADDR 0 //No matched slave address +#define I2C_SLV_RX_MATCH_ADDR 1 //Slave address hit, and is called for RX in slave mode +#define mskI2C_SLV_RX_NO_MATCH_ADDR (I2C_SLV_RX_NO_MATCH_ADDR<<6) +#define mskI2C_SLV_RX_MATCH_ADDR (I2C_SLV_RX_MATCH_ADDR<<6) + + //[7:7]Slave address check +#define I2C_SLV_TX_NO_MATCH_ADDR 0 //No matched slave address +#define I2C_SLV_TX_MATCH_ADDR 1 //Slave address hit, and is called for TX in slave mode. +#define mskI2C_SLV_TX_NO_MATCH_ADDR (I2C_SLV_TX_NO_MATCH_ADDR<<7) +#define mskI2C_SLV_TX_MATCH_ADDR (I2C_SLV_TX_MATCH_ADDR<<7) + + //[8:8]Lost arbitration +#define I2C_LOST_ARB_NO_LOST 0 //Not lost arbitration +#define I2C_LOST_ARB_LOST_ARBITRATION 1 //Lost arbitration +#define mskI2C_LOST_ARB_NO_LOST (I2C_LOST_ARB_NO_LOST<<8) +#define mskI2C_LOST_ARB_LOST_ARBITRATION (I2C_LOST_ARB_LOST_ARBITRATION<<8) + + //[9:9]Time-out status +#define I2C_TIMEOUT_NO_TIMEOUT 0 //No Timeout +#define I2C_TIMEOUT_TIMEOUT 1 //Timeout +#define mskI2C_TIMEOUT_TIMEOUT (I2C_TIMEOUT_TIMEOUT<<9) +#define mskI2C_TIMEOUT_NO_TIMEOUT (I2C_TIMEOUT_NO_TIMEOUT<<9) + + //[15:15]I2C Interrupt flag +#define I2C_I2CIF_STAUS_NO_CHANGE 0 //I2C status doesn’t change +#define I2C_I2CIF_INTERRUPT 1 //Read, I2C status changes + //Write, Clear this flag +#define mskI2C_I2CIF_STAUS_NO_CHANGE (I2C_I2CIF_STAUS_NO_CHANGE<<15) +#define mskI2C_I2CIF_INTERRUPT (I2C_I2CIF_INTERRUPT<<15) + + +/* I2C n TX Data register (0x08) */ + + +/* I2C n RX Data register (0x0C) */ + + +/* I2C n Slave Address 0 register (0x10) */ + //[9:0]The I2C slave address +#define I2C_ADDR_SLAVE_ADDR0 0x07 //ADD[9:0] is valid when ADD_MODE = 1 + //ADD[7:1] is valid when ADD_MODE = 0 + + //[30:30]General call address enable bit +#define I2C_GCEN_DIS 0 //Disable +#define I2C_GCEN_EN 1 //Enable general call address (0x0) +#define mskI2C_GCEN_DIS (I2C_GCEN_DIS<<30) +#define mskI2C_GCEN_EN (I2C_GCEN_EN<<30) + + //[31:31]Slave address mode +#define I2C_ADD_MODE_7BIT 0 //7-bit address mode +#define I2C_ADD_MODE_10BIT 1 //10-bit address mode +#define mskI2C_ADD_MODE_7BIT (I2C_ADD_MODE_7BIT<<31) +#define mskI2C_ADD_MODE_10BIT (I2C_ADD_MODE_10BIT<<31) + + +/* I2C n Slave Address 1~3 register (0x14/0x18/0x1C) */ + //The I2C slave address 1~3 + //ADD[9:0] is valid when ADD_MODE = 1 + //ADD[7:1] is valid when ADD_MODE = 0 +#define I2C_ADDR_SLAVE_ADDR1 0x0A //The I2C slave address 1 +#define I2C_ADDR_SLAVE_ADDR2 0 //The I2C slave address 2 +#define I2C_ADDR_SLAVE_ADDR3 0 //The I2C slave address 3 + +#define I2C_SLAVE0 0 //Slave Number 0 +#define I2C_SLAVE1 1 //Slave Number 1 +#define I2C_SLAVE2 2 //Slave Number 2 +#define I2C_SLAVE3 3 //Slave Number 3 + +/* I2C n SCL High Time register <(I2Cn_SCLHT> (0x20) */ +#define I2C0_SCLHT 14 //[7:0], Count for SCL High Period time +#define I2C1_SCLHT 4 //SCL High Period Time = (SCLH+1) * I2C0_PCLK cycle + + +/* I2C n SCL Low Time register <(I2Cn_SCLLT> (0x24) */ +#define I2C0_SCLLT 14 //[7:0], Count for SCL Low Period time +#define I2C1_SCLLT 4 //SCL Loq Period Time = (SCLH+1) * I2C0_PCLK cycle + + +/* I2C n Timeout Control register (0x2C) */ +#define I2C_TO_DIS 0 //[15:0], Count for checking Timeout +#define I2C_TO_PERIOD_TIME 0 //N: Timeout period time = N*I2Cn_PCLK cycle + + +/* I2C n Monitor Mode Control register (0x30) */ +#define I2C_MMEN_MONITOR_DIS 0 //[0:0]Monitor mode enable bit +#define I2C_MMEN_MONITOR_EN 1 +#define mskI2C_MMEN_MONITOR_DIS (I2C_MMEN_MONITOR_DIS<<0) //Monitor mode enable bit +#define mskI2C_MMEN_MONITOR_EN (I2C_MMEN_MONITOR_EN<<0) + + //[1:1]SCL output enable bit +#define I2C_SCLOEN_DIS 0 //SCL output will be forced high +#define I2C_SCLOEN_EN 1 //I2C holds the clock line low until it has had time to respond to an I2C interrupt +#define mskI2C_SCLOEN_DIS (I2C_SCLOEN_DIS<<1) //SCL output enable bit +#define mskI2C_SCLOEN_EN (I2C_SCLOEN_EN<<1) + + //[2:2]Match address selection +#define I2C_MATCH_ALL_ADDR0_3 0 //Interrupt will only be generated when the address matches +#define I2C_MATCH_ALL_ANY_ADDR 1 //In monitor mode, an interrupt will be generated on ANY address received +#define mskI2C_MATCH_ALL_ADDR0_3 (I2C_MATCH_ALL_ADDR0_3<<2) +#define mskI2C_MATCH_ALL_ANY_ADDR (I2C_MATCH_ALL_ANY_ADDR<<2) + + +#define I2C_ERROR 0x00001 + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + +//------------------I2C------------------------- +//Address +extern uint16_t hwI2C_Device_Addr_I2C0; +extern uint16_t hwI2C_Device_Addr_I2C1; + +//Check Flag +extern uint32_t wI2C_TimeoutFlag; +extern uint32_t wI2C_ArbitrationFlag; + +//Error Flag +extern uint32_t wI2C_RegisterCheckError; +extern uint32_t wI2C_TotalError; + +//------------------Master Tx------------------------- +//TX FIFO +extern uint8_t bI2C_MasTxData[10]; + +//Control Flag +extern uint8_t bI2C_MasTxPointer; +extern uint32_t wI2C_MasTxCtr; + +//------------------Master Rx------------------------- +//RX FIFO +extern uint8_t bI2C_MasRxData[10]; + +//Rx Control Flag +extern uint8_t bI2C_MasRxPointer; +extern uint32_t wI2C_ReturnNackFlag; +extern uint32_t wI2C_RxControlFlag; + +//------------------Slave Rx------------------------- +//RX FIFO +extern uint8_t bI2C_SlaRxData[10]; +//Rx Control Flag +extern uint8_t bI2C_SlaRxPointer; +//extern volatile uint8_t bEndSRxFlagI2C; + +//------------------Slave Tx------------------------- +//TX FIFO +extern uint8_t bI2C_SlaTxData[10]; +//Tx Control Flag +extern uint8_t bI2C_SlaTxPointer; +//extern volatile uint8_t bEndSTxFlagI2C; + +void I2C0_Init(void); +void I2C1_Init(void); +void I2C0_Timeout_Ctrl(uint32_t wI2CTo); +void I2C1_Timeout_Ctrl(uint32_t wI2CTo); +void I2C0_Monitor_Mode_Ctrl(uint32_t wI2CmatchAll, uint32_t wI2Cscloen, uint32_t wI2Cmmen); +void I2C1_Monitor_Mode_Ctrl(uint32_t wI2CmatchAll, uint32_t wI2Cscloen, uint32_t wI2Cmmen); +void Set_I2C0_Address(uint8_t bI2CaddMode, uint8_t bSlaveNo, uint32_t bSlaveAddr, uint8_t bGCEnable); +void Set_I2C1_Address(uint8_t bI2CaddMode, uint8_t bSlaveNo, uint32_t bSlaveAddr, uint8_t bGCEnable); + +extern void I2C0_Enable(void); +extern void I2C0_Disable(void); +extern void I2C1_Enable(void); +extern void I2C1_Disable(void); + +void I2C0_Master_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wTxNum, volatile uint32_t wRepeatTX, volatile uint32_t wReTxNum); +void I2C0_Master_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wRxNum, volatile uint32_t wRepeatRX, volatile uint32_t wReRxNum); +void I2C1_Master_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wTxNum, volatile uint32_t wRepeatTX, volatile uint32_t wReTxNum); +void I2C1_Master_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wRxNum, volatile uint32_t wRepeatRX, volatile uint32_t wReRxNum); + + + +void I2C1_Slave_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint32_t wNumForNack); +void I2C1_Slave_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop); + +void I2C1_Mointer_Mode(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop); + +void I2C0_Slave_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint32_t wNumForNack); +void I2C0_Slave_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop); + +void I2C0_Mointer_Mode(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop); + + +#endif /*__SN32F240_I2C_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/I2C/I2C0.c b/os/hal/ports/SN32/LLD/SN32F24x/I2C/I2C0.c new file mode 100644 index 00000000..882418a3 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/I2C/I2C0.c @@ -0,0 +1,720 @@ +/******************** (C) COPYRIGHT 2013 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2013/12 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: I2C0 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 1. First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include "I2C.h" +#include "..\..\Utility\Utility.h" + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +//------------------I2C------------------------- +//Address +uint16_t hwI2C_Device_Addr_I2C0 = 0x00; +uint16_t hwI2C_Device_Addr_I2C1 = 0x00; + +//Check Flag +uint32_t wI2C_TimeoutFlag = 0; +uint32_t wI2C_ArbitrationFlag = 0; + +//Error Flag +uint32_t wI2C_RegisterCheckError = 0; +uint32_t wI2C_TotalError = 0; + +//------------------Master Tx------------------------- +//TX FIFO +uint8_t bI2C_MasTxData[10]; + +//Tx Control Flag +uint8_t bI2C_MasTxPointer=0; +uint32_t wI2C_MasTxCtr=0; + +//------------------Master Rx------------------------- +//RX FIFO +uint8_t bI2C_MasRxData[10]; +//Rx Control Flag +uint8_t bI2C_MasRxPointer=0; +uint32_t wI2C_ReturnNackFlag=0; +uint32_t wI2C_RxControlFlag=0; + +//------------------Slave Rx------------------------- +//RX FIFO +uint8_t bI2C_SlaRxData[10]; +//Rx Control Flag +uint8_t bI2C_SlaRxPointer=0; + +//------------------Slave Tx------------------------- +//TX FIFO +uint8_t bI2C_SlaTxData[10]; +//Tx Control Flag +uint8_t bI2C_SlaTxPointer=0; + +//Mointer Mode +uint8_t bI2C0_MointerAddress = 0x00; + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + +/***************************************************************************** +* Function : I2C0_Init +* Description : Set specified value to specified bits of assigned register +* Input : wI2C0SCLH - SCL High Time +* wI2C0SCLL - SCL Low Time +* wI2C0Mode - 0: Standard/Fast mode.1: Fast-mode Plus +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C0_Init(void) +{ + //I2C0 interrupt enable + NVIC_ClearPendingIRQ(I2C0_IRQn); + NVIC_EnableIRQ(I2C0_IRQn); + NVIC_SetPriority(I2C0_IRQn,0); + + //Enable HCLK for I2C0 + SN_SYS1->AHBCLKEN |= (0x1 << 21); //Enable clock for I2C0 + + //I2C speed + SN_I2C0->SCLHT = I2C0_SCLHT; + SN_I2C0->SCLLT = I2C0_SCLLT; + + //Mointer mode + //SN_I2C0->MMCTRL = 0x00; + SN_I2C0->MMCTRL = mskI2C_MATCH_ALL_ADDR0_3| + mskI2C_SCLOEN_DIS| + mskI2C_MMEN_MONITOR_DIS; + + //I2C enable + SN_I2C0->CTRL_b.I2CEN = I2C_I2CEN_EN; +} + +/***************************************************************************** +* Function : I2C0_Timeout_Ctrl +* Description : Set specified value to specified bits of assigned register +* Input : wI2CTo - TimeOut Value: wI2CTo * 32 * I2C_PCLK cycle +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C0_Timeout_Ctrl(uint32_t wI2CTo) +{ + SN_I2C0->TOCTRL = wI2CTo; +} + +/***************************************************************************** +* Function : I2C0_Monitor_Mode_Ctrl +* Description : Set specified value to specified bits of assigned register +* Input : wI2CmatchAll - 0: No use. 1: Interrupt will be generated on ANY address received. +* wI2Cscloen - 0: No use. 1: Let I2C holds the clock line low to get data. +* wI2Cmmen - 0: No use. 1: Monitor mode enable bit. +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C0_Monitor_Mode_Ctrl(uint32_t wI2CmatchAll, uint32_t wI2Cscloen, uint32_t wI2Cmmen) +{ + SN_I2C0->TOCTRL = (wI2CmatchAll << 2) | (wI2Cscloen << 1) | (wI2Cmmen << 0); +} + +/***************************************************************************** +* Function : Set_I2C0_Address +* Description : Set specified value to specified bits of assigned register +* Input : bI2CaddMode - 7 bits address is 0, 10 bits address is 1 +* bSlaveNo - Slave address number 0, 1, 2, 3 +* bSlaveAddr - Slave value +* bGCEnable - Genral call enable is 1 +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void Set_I2C0_Address(uint8_t bI2CaddMode, uint8_t bSlaveNo, uint32_t bSlaveAddr, uint8_t bGCEnable) +{ + volatile uint16_t hwAddressCom=0; + + + if(bI2CaddMode == 0) + { + hwAddressCom = bSlaveAddr << 1; + } + else + { + hwAddressCom = bSlaveAddr; + } + + if(bGCEnable == 1) + { + SN_I2C0->SLVADDR0_b.GCEN = I2C_GCEN_EN; + } + else + { + SN_I2C0->SLVADDR0_b.GCEN = I2C_GCEN_DIS; + } + + if(bI2CaddMode == 1) + { + SN_I2C0->SLVADDR0_b.ADD_MODE = I2C_ADD_MODE_10BIT; + } + else + { + SN_I2C0->SLVADDR0_b.ADD_MODE = I2C_ADD_MODE_7BIT; + } + + switch (bSlaveNo) + { + case 0: + SN_I2C0->SLVADDR0 = hwAddressCom; + break; + + case 1: + SN_I2C0->SLVADDR1 = hwAddressCom; + break; + + case 2: + SN_I2C0->SLVADDR2 = hwAddressCom; + break; + + case 3: + SN_I2C0->SLVADDR3 = hwAddressCom; + break; + + default: + break; + } +} + +/***************************************************************************** +* Function : I2C0_Enable +* Description : I2C0 enable setting +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C0_Enable(void) +{ + //Enable HCLK for I2C0 + SN_SYS1->AHBCLKEN |= (0x1 << 21); //Enable clock for I2C0 + + SN_I2C0->CTRL_b.I2CEN = I2C_I2CEN_EN; //I2C enable +} + +/***************************************************************************** +* Function : I2C0_Disable +* Description : I2C0 disable setting +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C0_Disable(void) +{ + SN_I2C0->CTRL_b.I2CEN = I2C_I2CEN_DIS; //I2C disable + + //Disable HCLK for I2C0 + SN_SYS1->AHBCLKEN &=~ (0x1 << 21); //Disable clock for I2C0 +} + +/***************************************************************************** +* Function : I2C0_Master_Tx +* Description : Set specified value to specified bits of assigned register +* Input : *bDataFIFO - Declare TX FIFO Register +* *bPointerFIFO - Declare TX FIFO Pointer Register +* *bCommStop - Declare the Register when get the STOP information +* bSlaveAddress - Set the Slave adress +* wTxNum - Set the Number of sending Data +* wRepeatTX - 0 : No use. 1: Next transfer with a Repated Start condition. 2: Work next transfer. +* wReTxNum - Send (wReTxNum + 1) Data when wRepeatTX is 1. +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C0_Master_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wTxNum, volatile uint32_t wRepeatTX, volatile uint32_t wReTxNum) +{ + + //wReTxNum = 0, Repeat once; wReTxNum = 1, Repeat twice + + //if(((I2C_STAT) & (mskI2C_TIMEOUT_TIMEOUT)) != 0x00) //Timeout State + if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_TimeoutFlag = 1; + } + else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_ArbitrationFlag = 1; + } + else if(((SN_I2C0->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STOP_DN_STOP)) //Stop Down + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + *bPointerFIFO = 0x00; + wI2C_MasTxCtr = 0x00; + *bCommStop = 1; + } + else if(((SN_I2C0->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STA_MASTER_STA_STO)) //Start and Stop Down + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + SN_I2C0->TXDATA = (bSlaveAddress << 0x01); + } + else + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + + switch (SN_I2C0->STAT) + { + /* START has been transmitted and prepare SLA+W */ + case (mskI2C_MST_MASTER|mskI2C_START_DN_START): + SN_I2C0->TXDATA = (bSlaveAddress << 0x01); + break; + + /* SLA+W or Data has been transmitted and ACK has been received */ + case (mskI2C_MST_MASTER|mskI2C_ACK_STAT_RECEIVED_ACK): + if ((*bPointerFIFO < wTxNum)&&(wI2C_MasTxCtr == 0x00)) + { + SN_I2C0->TXDATA = *bDataFIFO; + *bPointerFIFO = *bPointerFIFO + 1; + } + else if ((*bPointerFIFO == wTxNum)&&(wI2C_MasTxCtr == 0x00)) + { + if(wRepeatTX == 0) //No Repeat + { + SN_I2C0->CTRL |= mskI2C_STO_STOP; + } + else if(wRepeatTX == 1) //Repeat Start + { + SN_I2C0->CTRL |= mskI2C_STA_START; + wI2C_MasTxCtr++; + } + else if(wRepeatTX == 2) //Repeat Both + { + SN_I2C0->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START); + wI2C_MasTxCtr++; + } + else + { + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + } + } + else if ((*bPointerFIFO < (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01)) + { + SN_I2C0->TXDATA = *bDataFIFO; + *bPointerFIFO = *bPointerFIFO + 1; + } + else if ((*bPointerFIFO == (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01)) + { + SN_I2C0->CTRL |= mskI2C_STO_STOP; + } + else + { + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + } + break; + + /* SLA+W or Data has been transmitted and NACK has been received */ + case (mskI2C_MST_MASTER|mskI2C_NACK_STAT_RECEIVED_NACK): + if ((*bPointerFIFO == wTxNum)&&(wI2C_MasTxCtr == 0x00)) + { + if(wRepeatTX == 0) //No Repeat + { + SN_I2C0->CTRL |= mskI2C_STO_STOP; + } + else if(wRepeatTX == 1) //Repeat Start + { + SN_I2C0->CTRL |= mskI2C_STA_START; + wI2C_MasTxCtr++; + } + else if(wRepeatTX == 2) //Repeat Both + { + SN_I2C0->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START); + wI2C_MasTxCtr++; + } + else + { + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + } + } + else if ((*bPointerFIFO == (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01)) + { + SN_I2C0->CTRL |= mskI2C_STO_STOP; + } + else + { + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + } + break; + + /*Error State Check*/ + default: + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + break; + } + } +} + +/***************************************************************************** +* Function : I2C0_Master_Rx +* Description : Set specified value to specified bits of assigned register +* Input : *bDataFIFO - Declare RX FIFO Register +* *bPointerFIFO - Declare RX FIFO Pointer Register +* *bCommStop - Declare the Register when get the STOP information +* bSlaveAddress - Set the Slave adress +* wRxNum - Set the Number of getting Data +* wRepeatRX - 0 : No use. 1: Next transfer with a Repated Start condition 2: Work next transfer. +* wReRxNum - Get (wReRxNum + 1) data when wRepeatRX is 1. +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C0_Master_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wRxNum, volatile uint32_t wRepeatRX, volatile uint32_t wReRxNum) +{ + uint32_t wDeboundNum = 0; + + //if(((I2C_STAT) & (mskI2C_TIMEOUT_TIMEOUT)) != 0x00) //Timeout State + if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_TimeoutFlag = 1; + } + else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_ArbitrationFlag = 1; + } + else if(((SN_I2C0->STAT) & (mskI2C_STA_STA_STO)) == (mskI2C_STOP_DN_STOP)) //Stop Down + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + *bPointerFIFO = 0x00; + wI2C_MasTxCtr = 0x00; + *bCommStop = 1; + wI2C_RxControlFlag = 0x00; + wI2C_ReturnNackFlag = 0x00; + } + else if(((SN_I2C0->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STA_MASTER_STA_STO)) //Start and Stop Down + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + SN_I2C0->TXDATA = (bSlaveAddress << 0x01) | 0x01; + } + else + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + + switch (SN_I2C0->STAT) + { + /* START has been transmitted and prepare to send address */ + case (mskI2C_MST_MASTER|mskI2C_START_DN_START): + SN_I2C0->TXDATA = (bSlaveAddress << 0x01) | 0x01; + break; + + /* Received an ACK */ + case (mskI2C_MST_MASTER|mskI2C_ACK_STAT_RECEIVED_ACK): + if((wRxNum == 1) && (wI2C_ReturnNackFlag == 0)) + { + SN_I2C0->CTRL |= mskI2C_NACK; //NACK + wI2C_ReturnNackFlag++; + } + else if((wReRxNum == 0) && (wI2C_ReturnNackFlag == 1)) + { + SN_I2C0->CTRL |= mskI2C_NACK; //NACK + wI2C_ReturnNackFlag++; + } + else + { + SN_I2C0->CTRL |= mskI2C_ACK; //ACK + } + break; + + /* RX with ACK/NACK transfer is down */ + case (mskI2C_MST_MASTER|mskI2C_RX_DN_HANDSHAKE): + *bDataFIFO = SN_I2C0->RXDATA; + *bPointerFIFO = *bPointerFIFO + 1; + + if(wI2C_ReturnNackFlag == 0x00) + { + wDeboundNum = wRxNum-1; + } + else if(wI2C_ReturnNackFlag == 0x01) + { + wDeboundNum = wRxNum+wReRxNum; + } + + if(wI2C_ReturnNackFlag == 0x02) + { + SN_I2C0->CTRL |= mskI2C_STO_STOP; + } + else if((wI2C_ReturnNackFlag == 0x01) && (wI2C_RxControlFlag == 0x00)) + { + + if(wRepeatRX == 0) //No Repeat + { + SN_I2C0->CTRL |= mskI2C_STO_STOP; + } + else if(wRepeatRX == 1) //Repeat Start + { + SN_I2C0->CTRL |= mskI2C_STA_START; + } + else if(wRepeatRX == 2) //Repeat Both + { + SN_I2C0->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START); + } + else + { + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + } + wI2C_RxControlFlag = 1; + } + else if((*bPointerFIFO < (wDeboundNum))) + { + //Return ACK + SN_I2C0->CTRL |= mskI2C_ACK; //ACK + } + else if((*bPointerFIFO >= (wDeboundNum))) + { + //Return NACK + SN_I2C0->CTRL |= mskI2C_NACK; //NACK + wI2C_ReturnNackFlag++; + } + else + { + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + } + break; + + /*Error State Check*/ + default: + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + break; + } + } +} + + +/***************************************************************************** +* Function : I2C0_Slave_Rx +* Description : Set specified value to specified bits of assigned register +* Input : *bDataFIFO - Declare RX FIFO Register +* *bPointerFIFO - Declare RX FIFO Pointer Register +* *bCommStop - Declare the Register when get the STOP information +* wNumForNack - Return NACK when getting the number of data is wNumForNack. +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C0_Slave_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint32_t wNumForNack) +{ + + if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_TimeoutFlag = 1; + } + else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_ArbitrationFlag = 1; + } + else if( SN_I2C0->STAT & mskI2C_STOP_DN_STOP) //Stop Down + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + *bCommStop = 0x01; + } + else + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + + switch (SN_I2C0->STAT) + { + /* Slave addess hit for Rx */ + case mskI2C_SLV_RX_MATCH_ADDR: + if(wNumForNack == 0) + { + SN_I2C0->CTRL |= mskI2C_ACK;; //ACK + } + else if(wNumForNack == 1) + { + SN_I2C0->CTRL |= mskI2C_NACK; //NACK + } + else + { + SN_I2C0->CTRL |= mskI2C_ACK; //ACK + } + break; + + /* DATA has been received and ACK/NACK has been returned */ + case mskI2C_RX_DN_HANDSHAKE: + *bDataFIFO = SN_I2C0->RXDATA ; + *bPointerFIFO = *bPointerFIFO + 1; + + if(wNumForNack == 0) + { + SN_I2C0->CTRL |= mskI2C_ACK; //ACK + } + else if(*bPointerFIFO == (wNumForNack-1)) + { + SN_I2C0->CTRL |= mskI2C_NACK; //NACK + } + else + { + SN_I2C0->CTRL |= mskI2C_ACK; //ACK + } + break; + + /*Error State Check*/ + default: + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + break; + } + } +} + +/***************************************************************************** +* Function : I2C0_Slave_Tx +* Description : Set specified value to specified bits of assigned register +* Input : *bDataFIFO - Declare TX FIFO Register +* *bPointerFIFO - Declare TX FIFO Pointer Register +* *bCommStop - Declare the Register when get the STOP information +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C0_Slave_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop) +{ + if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_TimeoutFlag = 1; + } + else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_ArbitrationFlag = 1; + } + else if( SN_I2C0->STAT & mskI2C_STOP_DN_STOP) //Stop Down + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + *bCommStop = 0x01; + } + else + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + + switch (SN_I2C0->STAT) + { + /* Slave addess hit for Tx */ + case mskI2C_SLV_TX_MATCH_ADDR: + SN_I2C0->TXDATA = *bDataFIFO; + *bPointerFIFO = *bPointerFIFO + 1; + break; + + /* Received ACK */ + case mskI2C_ACK_STAT_RECEIVED_ACK: + SN_I2C0->TXDATA = *bDataFIFO; + *bPointerFIFO = *bPointerFIFO + 1; + break; + + /* Received NACK */ + case mskI2C_NACK_STAT_RECEIVED_NACK: + SN_I2C0->CTRL |= mskI2C_ACK; //For release SCL and SDA + break; + + /*Error State Check*/ + default: + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + break; + } + } +} + +/***************************************************************************** +* Function : I2C0_Mointer_Mode +* Description : Set specified value to specified bits of assigned register +* Input : *bDataFIFO - Declare RX FIFO Register +* *bPointerFIFO - Declare RX FIFO Pointer Register +* *bCommStop - Declare the Register when get the STOP information +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C0_Mointer_Mode(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop) +{ + if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_TimeoutFlag = 1; + } + else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_ArbitrationFlag = 1; + } + else if( SN_I2C0->STAT & mskI2C_STOP_DN_STOP) //Stop Down + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + *bCommStop = 0x01; + } + else + { + SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + + switch (SN_I2C0->STAT) + { + /* Slave addess hit for Rx */ + case mskI2C_SLV_RX_MATCH_ADDR: + bI2C0_MointerAddress = SN_I2C0->RXDATA; + bI2C0_MointerAddress = bI2C0_MointerAddress >> 1; + SN_I2C0->CTRL |= mskI2C_ACK; //ACK + + break; + + /* Slave addess hit for Tx */ + case mskI2C_SLV_TX_MATCH_ADDR: + bI2C0_MointerAddress = SN_I2C0->RXDATA; + bI2C0_MointerAddress = bI2C0_MointerAddress >> 1; + SN_I2C0->CTRL |= mskI2C_ACK; //ACK + + break; + /* DATA has been received*/ + case I2C_RX_DN_HANDSHAKE: + *bDataFIFO = SN_I2C0->RXDATA; + *bPointerFIFO = *bPointerFIFO + 1; + SN_I2C0->CTRL |= mskI2C_ACK; //ACK + + break; + + /*Error State Check*/ + default: + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + break; + } + } +} diff --git a/os/hal/ports/SN32/LLD/SN32F24x/I2C/I2C1.c b/os/hal/ports/SN32/LLD/SN32F24x/I2C/I2C1.c new file mode 100644 index 00000000..583cce98 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/I2C/I2C1.c @@ -0,0 +1,675 @@ +/******************** (C) COPYRIGHT 2013 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2013/12 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: I2C1 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 1. First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include "I2C.h" +#include "..\..\Utility\Utility.h" +/*_____ D E C L A R A T I O N S ____________________________________________*/ +//Mointer Mode +uint8_t bI2C1_MointerAddress = 0x00; + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + + +/***************************************************************************** +* Function : I2C1_Init +* Description : Set specified value to specified bits of assigned register +* Input : wI2C1SCLH - SCL High Time +* wI2C1SCLL - SCL Low Time +* wI2C1Mode - 0: Standard/Fast mode.1: Fast-mode Plus +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C1_Init(void) +{ + //I2C1 interrupt enable + NVIC_ClearPendingIRQ(I2C1_IRQn); + NVIC_EnableIRQ(I2C1_IRQn); + NVIC_SetPriority(I2C1_IRQn,0); + + //Enable HCLK for I2C1 + SN_SYS1->AHBCLKEN |= (0x1 << 20); //Enable clock for I2C1 + + //I2C speed + SN_I2C1->SCLHT = I2C1_SCLHT; + SN_I2C1->SCLLT = I2C1_SCLLT; + + + //I2C enable + SN_I2C1->CTRL_b.I2CEN = I2C_I2CEN_EN; + + //I2C1 address set + Set_I2C1_Address(I2C_ADD_MODE_7BIT, I2C_SLAVE0, I2C_ADDR_SLAVE_ADDR0, I2C_GCEN_DIS); + Set_I2C1_Address(I2C_ADD_MODE_7BIT, I2C_SLAVE1, I2C_ADDR_SLAVE_ADDR1, I2C_GCEN_DIS); +} + +/***************************************************************************** +* Function : I2C1_Timeout_Ctrl +* Description : Set specified value to specified bits of assigned register +* Input : wI2CTo - TimeOut Value: wI2CTo * 32 * I2C_PCLK cycle +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C01_Timeout_Ctrl(uint32_t wI2CTo) +{ + SN_I2C1->TOCTRL = wI2CTo; +} + +/***************************************************************************** +* Function : I2C1_Monitor_Mode_Ctrl +* Description : Set specified value to specified bits of assigned register +* Input : wI2CmatchAll - 0: No use. 1: Interrupt will be generated on ANY address received. +* wI2Cscloen - 0: No use. 1: Let I2C holds the clock line low to get data. +* wI2Cmmen - 0: No use. 1: Monitor mode enable bit. +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C1_Monitor_Mode_Ctrl(uint32_t wI2CmatchAll, uint32_t wI2Cscloen, uint32_t wI2Cmmen) +{ + SN_I2C1->TOCTRL = (wI2CmatchAll << 2) | (wI2Cscloen << 1) | (wI2Cmmen << 0); +} + +/***************************************************************************** +* Function : Set_I2C1_Address +* Description : Set specified value to specified bits of assigned register +* Input : bI2CaddMode - 7 bits address is 0, 10 bits address is 1 +* bSlaveNo - Slave address number 0, 1, 2, 3 +* bSlaveAddr - Slave value +* bGCEnable - Genral call enable is 1 +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void Set_I2C1_Address(uint8_t bI2CaddMode, uint8_t bSlaveNo, uint32_t bSlaveAddr, uint8_t bGCEnable) +{ + volatile uint16_t hwAddressCom=0; + + + if(bI2CaddMode == 0) + { + hwAddressCom = bSlaveAddr << 1; + } + else + { + hwAddressCom = bSlaveAddr; + } + + if(bGCEnable == 1) + { + SN_I2C1->SLVADDR0_b.GCEN = I2C_GCEN_EN; + } + else + { + SN_I2C1->SLVADDR0_b.GCEN = I2C_GCEN_DIS; + } + + if(bI2CaddMode == 1) + { + SN_I2C1->SLVADDR0_b.ADD_MODE = I2C_ADD_MODE_10BIT; + } + else + { + SN_I2C1->SLVADDR0_b.ADD_MODE = I2C_ADD_MODE_7BIT; + } + + switch (bSlaveNo) + { + case 0: + SN_I2C1->SLVADDR0 = hwAddressCom; + break; + + case 1: + SN_I2C1->SLVADDR1 = hwAddressCom; + break; + + case 2: + SN_I2C1->SLVADDR2 = hwAddressCom; + break; + + case 3: + SN_I2C1->SLVADDR3 = hwAddressCom; + break; + + default: + break; + } +} + +/***************************************************************************** +* Function : I2C1_Enable +* Description : I2C1 enable setting +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C1_Enable(void) +{ + //Enable HCLK for I2C1 + SN_SYS1->AHBCLKEN |= (0x1 << 20); //Enable clock for I2C1 + + SN_I2C1->CTRL_b.I2CEN = I2C_I2CEN_EN; //I2C1 enable +} + +/***************************************************************************** +* Function : I2C1_Disable +* Description : I2C1 disable setting +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C1_Disable(void) +{ + SN_I2C1->CTRL_b.I2CEN = I2C_I2CEN_DIS; //I2C1 disable + + //Disable HCLK for I2C1 + SN_SYS1->AHBCLKEN &=~ (0x1 << 20); //Disable clock for I2C1 +} + +/***************************************************************************** +* Function : I2C1_Master_Tx +* Description : Set specified value to specified bits of assigned register +* Input : *bDataFIFO - Declare TX FIFO Register +* *bPointerFIFO - Declare TX FIFO Pointer Register +* *bCommStop - Declare the Register when get the STOP information +* bSlaveAddress - Set the Slave adress +* wTxNum - Set the Number of sending Data +* wRepeatTX - 0 : No use. 1: Next transfer with a Repated Start condition. 2: Work next transfer. +* wReTxNum - Send (wReTxNum + 1) Data when wRepeatTX is 1. +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C1_Master_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wTxNum, volatile uint32_t wRepeatTX, volatile uint32_t wReTxNum) +{ + + //wReTxNum = 0, Repeat once; wReTxNum = 1, Repeat twice + + if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_TimeoutFlag = 1; + } + else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_ArbitrationFlag = 1; + } + else if(((SN_I2C1->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STOP_DN_STOP)) //Stop Down + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + *bPointerFIFO = 0x00; + wI2C_MasTxCtr = 0x00; + *bCommStop = 1; + } + else if(((SN_I2C1->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STA_MASTER_STA_STO)) //Start and Stop Down + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + SN_I2C1->TXDATA = (bSlaveAddress << 0x01); + } + else + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + + switch (SN_I2C1->STAT) + { + /* START has been transmitted and prepare SLA+W */ + case (mskI2C_MST_MASTER|mskI2C_START_DN_START): + SN_I2C1->TXDATA = (bSlaveAddress << 0x01); + break; + + /* SLA+W or Data has been transmitted and ACK has been received */ + case (mskI2C_MST_MASTER|mskI2C_ACK_STAT_RECEIVED_ACK): + if ((*bPointerFIFO < wTxNum)&&(wI2C_MasTxCtr == 0x00)) + { + SN_I2C1->TXDATA = *bDataFIFO; + *bPointerFIFO = *bPointerFIFO + 1; + } + else if ((*bPointerFIFO == wTxNum)&&(wI2C_MasTxCtr == 0x00)) + { + if(wRepeatTX == 0) //No Repeat + { + SN_I2C1->CTRL |= mskI2C_STO_STOP; + } + else if(wRepeatTX == 1) //Repeat Start + { + SN_I2C1->CTRL |= mskI2C_STA_START; + wI2C_MasTxCtr++; + } + else if(wRepeatTX == 2) //Repeat Both + { + SN_I2C1->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START); + wI2C_MasTxCtr++; + } + else + { + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + } + } + else if ((*bPointerFIFO < (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01)) + { + SN_I2C1->TXDATA = *bDataFIFO; + *bPointerFIFO = *bPointerFIFO + 1; + } + else if ((*bPointerFIFO == (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01)) + { + SN_I2C1->CTRL |= mskI2C_STO_STOP; + } + else + { + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + } + break; + + /* SLA+W or Data has been transmitted and NACK has been received */ + case (mskI2C_MST_MASTER|mskI2C_NACK_STAT_RECEIVED_NACK): + if ((*bPointerFIFO == wTxNum)&&(wI2C_MasTxCtr == 0x00)) + { + if(wRepeatTX == 0) //No Repeat + { + SN_I2C1->CTRL |= mskI2C_STO_STOP; + } + else if(wRepeatTX == 1) //Repeat Start + { + SN_I2C1->CTRL |= mskI2C_STA_START; + wI2C_MasTxCtr++; + } + else if(wRepeatTX == 2) //Repeat Both + { + SN_I2C1->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START); + wI2C_MasTxCtr++; + } + else + { + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + } + } + else if ((*bPointerFIFO == (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01)) + { + SN_I2C1->CTRL |= mskI2C_STO_STOP; + } + else + { + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + } + break; + + /*Error State Check*/ + default: + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + break; + } + } +} + +/***************************************************************************** +* Function : I2C1_Master_Rx +* Description : Set specified value to specified bits of assigned register +* Input : *bDataFIFO - Declare RX FIFO Register +* *bPointerFIFO - Declare RX FIFO Pointer Register +* *bCommStop - Declare the Register when get the STOP information +* bSlaveAddress - Set the Slave adress +* wRxNum - Set the Number of getting Data +* wRepeatRX - 0 : No use. 1: Next transfer with a Repated Start condition 2: Work next transfer. +* wReRxNum - Get (wReRxNum + 1) data when wRepeatRX is 1. +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C1_Master_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wRxNum, volatile uint32_t wRepeatRX, volatile uint32_t wReRxNum) +{ + uint32_t wDeboundNum = 0; + + if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_TimeoutFlag = 1; + } + else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_ArbitrationFlag = 1; + } + else if(((SN_I2C1->STAT) & (mskI2C_STA_STA_STO)) == (mskI2C_STOP_DN_STOP)) //Stop Down + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + *bPointerFIFO = 0x00; + wI2C_MasTxCtr = 0x00; + *bCommStop = 1; + wI2C_RxControlFlag = 0x00; + wI2C_ReturnNackFlag = 0x00; + } + else if(((SN_I2C1->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STA_MASTER_STA_STO)) //Start and Stop Down + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + SN_I2C1->TXDATA = (bSlaveAddress << 0x01) | 0x01; + } + else + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + + switch (SN_I2C1->STAT) + { + /* START has been transmitted and prepare to send address */ + case (mskI2C_MST_MASTER|mskI2C_START_DN_START): + SN_I2C1->TXDATA = (bSlaveAddress << 0x01) | 0x01; + break; + + /* Received an ACK */ + case (mskI2C_MST_MASTER|mskI2C_ACK_STAT_RECEIVED_ACK): + if((wRxNum == 1) && (wI2C_ReturnNackFlag == 0)) + { + SN_I2C1->CTRL |= mskI2C_NACK; //NACK + wI2C_ReturnNackFlag++; + } + else if((wReRxNum == 0) && (wI2C_ReturnNackFlag == 1)) + { + SN_I2C1->CTRL |= mskI2C_NACK; //NACK + wI2C_ReturnNackFlag++; + } + else + { + SN_I2C1->CTRL |= mskI2C_ACK; //ACK + } + break; + + /* RX with ACK/NACK transfer is down */ + case (mskI2C_MST_MASTER|mskI2C_RX_DN_HANDSHAKE): + *bDataFIFO = SN_I2C1->RXDATA; + *bPointerFIFO = *bPointerFIFO + 1; + + if(wI2C_ReturnNackFlag == 0x00) + { + wDeboundNum = wRxNum-1; + } + else if(wI2C_ReturnNackFlag == 0x01) + { + wDeboundNum = wRxNum+wReRxNum; + } + + if(wI2C_ReturnNackFlag == 0x02) + { + SN_I2C1->CTRL |= mskI2C_STO_STOP; + } + else if((wI2C_ReturnNackFlag == 0x01) && (wI2C_RxControlFlag == 0x00)) + { + + if(wRepeatRX == 0) //No Repeat + { + SN_I2C1->CTRL |= mskI2C_STO_STOP; + } + else if(wRepeatRX == 1) //Repeat Start + { + SN_I2C1->CTRL |= mskI2C_STA_START; + } + else if(wRepeatRX == 2) //Repeat Both + { + SN_I2C1->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START); + } + else + { + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + } + wI2C_RxControlFlag = 1; + } + else if((*bPointerFIFO < (wDeboundNum))) + { + //Return ACK + SN_I2C1->CTRL |= mskI2C_ACK; //ACK + } + else if((*bPointerFIFO >= (wDeboundNum))) + { + //Return NACK + SN_I2C1->CTRL |= mskI2C_NACK; //NACK + wI2C_ReturnNackFlag++; + } + else + { + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + } + break; + + /*Error State Check*/ + default: + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + break; + } + } +} + +/***************************************************************************** +* Function : I2C1_Slave_Rx +* Description : Set specified value to specified bits of assigned register +* Input : *bDataFIFO - Declare RX FIFO Register +* *bPointerFIFO - Declare RX FIFO Pointer Register +* *bCommStop - Declare the Register when get the STOP information +* wNumForNack - Return NACK when getting the number of data is wNumForNack. +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C1_Slave_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint32_t wNumForNack) +{ + + if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_TimeoutFlag = 1; + } + else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_ArbitrationFlag = 1; + } + else if( SN_I2C1->STAT & mskI2C_STOP_DN_STOP) //Stop Down + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + *bCommStop = 0x01; + } + else + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + + switch (SN_I2C1->STAT) + { + /* Slave addess hit for Rx */ + case mskI2C_SLV_RX_MATCH_ADDR: + if(wNumForNack == 0) + { + SN_I2C1->CTRL |= mskI2C_ACK;; //ACK + } + else if(wNumForNack == 1) + { + SN_I2C1->CTRL |= mskI2C_NACK; //NACK + } + else + { + SN_I2C1->CTRL |= mskI2C_ACK; //ACK + } + break; + + /* DATA has been received and ACK/NACK has been returned */ + case mskI2C_RX_DN_HANDSHAKE: + *bDataFIFO = SN_I2C1->RXDATA ; + *bPointerFIFO = *bPointerFIFO + 1; + + if(wNumForNack == 0) + { + SN_I2C1->CTRL |= mskI2C_ACK; //ACK + } + else if(*bPointerFIFO == (wNumForNack-1)) + { + SN_I2C1->CTRL |= mskI2C_NACK; //NACK + } + else + { + SN_I2C1->CTRL |= mskI2C_ACK; //ACK + } + break; + + /*Error State Check*/ + default: + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + break; + } + } +} + +/***************************************************************************** +* Function : I2C1_Slave_Tx +* Description : Set specified value to specified bits of assigned register +* Input : *bDataFIFO - Declare TX FIFO Register +* *bPointerFIFO - Declare TX FIFO Pointer Register +* *bCommStop - Declare the Register when get the STOP information +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C1_Slave_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop) +{ + if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_TimeoutFlag = 1; + } + else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_ArbitrationFlag = 1; + } + else if( SN_I2C1->STAT & mskI2C_STOP_DN_STOP) //Stop Down + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + *bCommStop = 0x01; + } + else + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + + switch (SN_I2C1->STAT) + { + /* Slave addess hit for Tx */ + case mskI2C_SLV_TX_MATCH_ADDR: + SN_I2C1->TXDATA = *bDataFIFO; + *bPointerFIFO = *bPointerFIFO + 1; + break; + + /* Received ACK */ + case mskI2C_ACK_STAT_RECEIVED_ACK: + SN_I2C1->TXDATA = *bDataFIFO; + *bPointerFIFO = *bPointerFIFO + 1; + break; + + /* Received NACK */ + case mskI2C_NACK_STAT_RECEIVED_NACK: + SN_I2C1->CTRL |= mskI2C_ACK; //For release SCL and SDA + break; + + /*Error State Check*/ + default: + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + break; + } + } +} + +/***************************************************************************** +* Function : I2C1_Mointer_Mode +* Description : Set specified value to specified bits of assigned register +* Input : *bDataFIFO - Declare RX FIFO Register +* *bPointerFIFO - Declare RX FIFO Pointer Register +* *bCommStop - Declare the Register when get the STOP information +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C1_Mointer_Mode(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop) +{ + if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_TimeoutFlag = 1; + } + else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + wI2C_ArbitrationFlag = 1; + } + else if( SN_I2C1->STAT & mskI2C_STOP_DN_STOP) //Stop Down + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + *bCommStop = 0x01; + } + else + { + SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag + + switch (SN_I2C1->STAT) + { + /* Slave addess hit for Rx */ + case mskI2C_SLV_RX_MATCH_ADDR: + bI2C1_MointerAddress = SN_I2C1->RXDATA; + bI2C1_MointerAddress = bI2C1_MointerAddress >> 1; + SN_I2C1->CTRL |= mskI2C_ACK; //ACK + + break; + + /* Slave addess hit for Tx */ + case mskI2C_SLV_TX_MATCH_ADDR: + bI2C1_MointerAddress = SN_I2C1->RXDATA; + bI2C1_MointerAddress = bI2C1_MointerAddress >> 1; + SN_I2C1->CTRL |= mskI2C_ACK; //ACK + + break; + /* DATA has been received*/ + case I2C_RX_DN_HANDSHAKE: + *bDataFIFO = SN_I2C1->RXDATA; + *bPointerFIFO = *bPointerFIFO + 1; + SN_I2C1->CTRL |= mskI2C_ACK; //ACK + + break; + + /*Error State Check*/ + default: + wI2C_RegisterCheckError |= I2C_ERROR; + wI2C_TotalError++; + break; + } + } +} diff --git a/os/hal/ports/SN32/LLD/SN32F24x/I2S/I2S.c b/os/hal/ports/SN32/LLD/SN32F24x/I2S/I2S.c new file mode 100644 index 00000000..0c5bd877 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/I2S/I2S.c @@ -0,0 +1,153 @@ +/******************** (C) COPYRIGHT 2014 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2014/02 +* AUTHOR: SA1 +* IC: SN32F240/730/220 +* DESCRIPTION: I2S related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 1. First release +* 2.0 2014/02/27 SA1 1. Update I2S functions. +* 3.2 2019/05/31 SA1 1. Fix I2S_Master_Init and I2S_Slave_Init. +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include "I2S.h" +#include "..\..\Utility\Utility.h" + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ +/************************************************************** +* Function : I2S_Master_INIT +* Description : Set I2S as master +* Input : None +* Output : None +* Return : None +* Note : None +****************************************************************/ +void I2S_Master_Init(void) +{ + __I2S_ENABLE_I2SHCLK; //Enable HCLK for I2S + + SN_I2S->CTRL_b.I2SEN = I2S_I2SEN_EN; //I2S enable bit + SN_I2S->CTRL_b.CHLENGTH = I2S_CHLENGTH_32BITS; //Single channel[4:0] + SN_I2S->CTRL_b.RXFIFOTH = I2S_RXFIFOTH_2; //RX FIFO Threshold level + SN_I2S->CTRL_b.TXFIFOTH = I2S_TXFIFOTH_6; //TX FIFO Threshold level + + SN_I2S->CTRL_b.DL = I2S_DL_24BITS; //I2S Data Length + __I2S_RESET_RXFIFO; //Clear I2S RX FIFO + __I2S_RESET_TXFIFO; //Clear I2S TX FIFO + SN_I2S->CTRL_b.RXEN = I2S_RXEN_EN; //Receiver enable bit + SN_I2S->CTRL_b.TXEN = I2S_TXEN_EN; //Transmit enable bit + + SN_I2S->CTRL_b.FORMAT=I2S_FORMAT_STANDARD; //I2S operation format + SN_I2S->CTRL_b.MS=I2S_MS_MASTER_MODE; //Master selection bit + SN_I2S->CTRL_b.MONO=I2S_MONO_STERO; //Stereo selection bit + SN_I2S->CTRL_b.MUTE=I2S_MUTE_DIS; //Mute enable bit + + //I2S clk + SN_I2S->CLK = mskI2S_CLKSEL_HCLK| //I2S clock source selection + mskI2S_BCLKDIV_DIV| //MCLK/n, n = 2, 4, 6, 8, ...,512 + mskI2S_MCLKSEL_I2S_PCLK| //MCLK source of master is from I2S_PCLK + mskI2S_MCLKOEN_OUTPUT_DIS| //MCLK output enable bit + mskI2S_MCLKDIV_DIV3; //MCLK = MCLK source / 6 +} + +/************************************************************** +* Function : I2S_Slave_Init +* Description : Set I2S as slave +* Input : None +* Output : None +* Return : None +* Note : None +****************************************************************/ +void I2S_Slave_Init(void) +{ + __I2S_ENABLE_I2SHCLK; //Enable HCLK for I2S + + SN_I2S->CTRL_b.I2SEN = I2S_I2SEN_EN ; //I2S enable bit + SN_I2S->CTRL_b.CHLENGTH = I2S_CHLENGTH_32BITS; //Single channel[4:0] + SN_I2S->CTRL_b.RXFIFOTH = I2S_RXFIFOTH_2; //RX FIFO Threshold level + SN_I2S->CTRL_b.TXFIFOTH = I2S_TXFIFOTH_6; + + SN_I2S->CTRL_b.DL = I2S_DL_24BITS; //I2S Data Length + __I2S_RESET_RXFIFO; //Clear I2S RX FIFO + __I2S_RESET_TXFIFO; //Clear I2S TX FIFO + SN_I2S->CTRL_b.RXEN = I2S_RXEN_EN; //Receiver enable bit + SN_I2S->CTRL_b.TXEN = I2S_TXEN_EN; + + SN_I2S->CTRL_b.FORMAT=I2S_FORMAT_STANDARD; //I2S operation format + SN_I2S->CTRL_b.MS=I2S_MS_SLAVE_MODE; //Master selection bit + SN_I2S->CTRL_b.MONO=I2S_MONO_STERO; //Stereo selection bit + SN_I2S->CTRL_b.MUTE=I2S_MUTE_DIS; +} + +/***************************************************************************** +* Function : I2S_Enable +* Description : I2S enable +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2S_Enable(void) +{ + __I2S_ENABLE_I2SHCLK; //Enable HCLK for I2S + + SN_I2S->CTRL_b.I2SEN = I2S_I2SEN_EN ; //I2S enable bit + __I2S_RESET_TXFIFO; + __I2S_RESET_RXFIFO; +} + +/***************************************************************************** +* Function : I2S_Disable +* Description : I2S disable +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2S_Disable(void) +{ + SN_I2S->CTRL_b.I2SEN = I2S_I2SEN_DIS; //I2S disable bit + + __I2S_DISABLE_I2SHCLK; //Disable HCLK for I2S +} + +/********************************** +* Function : I2S_Interrupt_Enable +* Description : I2S interrupt enable +* Input : None +* Output : None +* Return : None +* Note : None +**********************************/ +void I2S_Interrupt_Enable(void) +{ + SN_I2S->IC = mskI2S_RXFIFOTHIC| //Clear RXFIFOTHIF bit + mskI2S_TXFIFOTHIC| //Clear TXFIFOTHIF bit + mskI2S_RXFIFOUDIC| //Clear RXFIFOOUDIF bit + mskI2S_TXFIFOOVIC; //Clear TXFIFOOVIF bit + + SN_I2S->IE = mskI2S_TXFIFOOVFIEN_EN| //TX FIFO overflow interrupt enable bit + mskI2S_RXFIFOUDFIEN_EN| //RX FIFO underflow interrupt enable bit + mskI2S_TXFIFOTHIEN_EN| //TX FIFO threshold interrupt enable bit + mskI2S_RXFIFOTHIEN_EN; //RX FIFO threshold interrupt enable bit +} diff --git a/os/hal/ports/SN32/LLD/SN32F24x/I2S/I2S.h b/os/hal/ports/SN32/LLD/SN32F24x/I2S/I2S.h new file mode 100644 index 00000000..8a54e443 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/I2S/I2S.h @@ -0,0 +1,216 @@ +#ifndef __SN32F240_I2S_H +#define __SN32F240_I2S_H + +/*_____ I N C L U D E S ____________________________________________________*/ + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +/* +Base Address: 0x4001 A000 +*/ + +/* I2S Control register (0x00) */ + +#define I2S_START_DIS 0 //[0:0]Start Transmit/Receive bit +#define I2S_START_EN 1 +#define mskI2S_START_DIS (mskI2S_START_DIS<<0) +#define mskI2S_START_EN (mskI2S_START_EN<<0) + +#define I2S_MUTE_DIS 0 //[1:1]Mute enable bit +#define I2S_MUTE_EN 1 +#define mskI2S_MUTE_DIS (I2S_MUTE_DIS<<1) +#define mskI2S_MUTE_EN (I2S_MUTE_EN<<1) + +#define I2S_MONO_STERO 0 //[2:2]Mono/Stereo selection bit +#define I2S_MONO_MONO 1 +#define mskI2S_MONO_STERO (I2S_MONO_STERO<<2) +#define mskI2S_MONO_MONO (I2S_MONO_MONO<<2) + +#define I2S_MS_MASTER_MODE 0 //[3:3]Master/Slave selection bit +#define I2S_MS_SLAVE_MODE 1 +#define mskI2S_MS_MASTER_MODE (I2S_MS_MASTER_MODE<<3) +#define mskI2S_MS_SLAVE_MODE (I2S_MS_SLAVE_MODE<<3) + + //[5:4]I2S operation format +#define I2S_FORMAT_STANDARD 0 //Standard I2S format +#define I2S_FORMAT_LEFTJUST 1 //Left-justified format +#define I2S_FORMAT_RIGHTJUST 2 //Right(MSB)-justified format +#define mskI2S_FORMAT_STANDARD (I2S_FORMAT_STANDARD<<4) +#define mskI2S_FORMAT_LEFTJUST (I2S_FORMAT_LEFTJUST<<4) +#define mskI2S_FORMAT_RIGHTJUST (I2S_FORMAT_RIGHTJUST<<4) + +#define I2S_TXEN_DIS 0 //[6:6]Transmit enable bit +#define I2S_TXEN_EN 1 +#define mskI2S_TXEN_DIS (I2S_TXEN_DIS<<6) +#define mskI2S_TXEN_EN (I2S_TXEN_EN<<6) + +#define I2S_RXEN_DIS 0 //[7:7]Receiver enable bit +#define I2S_RXEN_EN 1 +#define mskI2S_RXEN_DIS (I2S_RXEN_DIS<<7) +#define mskI2S_RXEN_EN (I2S_RXEN_EN<<7) + +#define I2S_CLRTXFIFO_RESET_TXFIFO 1 //[8:8]Clear I2S TX FIFO +#define I2S_CLRRXFIFO_RESET_RXFIFO 1 //[9:9]Clear I2S TX FIFO + +#define I2S_DL_8BITS 0 //[11:10]I2S Data Length +#define I2S_DL_16BITS 1 +#define I2S_DL_24BITS 2 +#define I2S_DL_32BITS 3 + +#define I2S_TXFIFOTH_0 0 //[14:12]TX FIFO Threshold level[2:0] +#define I2S_TXFIFOTH_1 1 +#define I2S_TXFIFOTH_2 2 +#define I2S_TXFIFOTH_3 3 +#define I2S_TXFIFOTH_4 4 +#define I2S_TXFIFOTH_5 5 +#define I2S_TXFIFOTH_6 6 +#define I2S_TXFIFOTH_7 7 + +#define I2S_RXFIFOTH_0 0 //[18:16]RX FIFO Threshold level[2:0] +#define I2S_RXFIFOTH_1 1 +#define I2S_RXFIFOTH_2 2 +#define I2S_RXFIFOTH_3 3 +#define I2S_RXFIFOTH_4 4 +#define I2S_RXFIFOTH_5 5 +#define I2S_RXFIFOTH_6 6 +#define I2S_RXFIFOTH_7 7 + +#define I2S_CHLENGTH_8BITS 7 //[24:20]Bit number of single channel[4:0] +#define I2S_CHLENGTH_9BITS 8 +#define I2S_CHLENGTH_10BITS 9 +#define I2S_CHLENGTH_11BITS 10 +#define I2S_CHLENGTH_12BITS 11 +#define I2S_CHLENGTH_13BITS 12 +#define I2S_CHLENGTH_14BITS 13 +#define I2S_CHLENGTH_15BITS 14 +#define I2S_CHLENGTH_16BITS 15 +#define I2S_CHLENGTH_17BITS 16 +#define I2S_CHLENGTH_18BITS 17 +#define I2S_CHLENGTH_19BITS 18 +#define I2S_CHLENGTH_20BITS 19 +#define I2S_CHLENGTH_21BITS 20 +#define I2S_CHLENGTH_22BITS 21 +#define I2S_CHLENGTH_23BITS 22 +#define I2S_CHLENGTH_24BITS 23 +#define I2S_CHLENGTH_25BITS 24 +#define I2S_CHLENGTH_26BITS 25 +#define I2S_CHLENGTH_27BITS 26 +#define I2S_CHLENGTH_28BITS 27 +#define I2S_CHLENGTH_29BITS 28 +#define I2S_CHLENGTH_30BITS 29 +#define I2S_CHLENGTH_31BITS 30 +#define I2S_CHLENGTH_32BITS 31 + +#define I2S_I2SEN_DIS 0 //[31:31]I2S enable bit +#define I2S_I2SEN_EN 1 +#define mskI2S_I2SEN_DIS (I2S_I2SEN_DIS<<31) +#define mskI2S_I2SEN_EN (I2S_I2SEN_EN<<31) + +/* I2S Clock register (0x04) */ + //[2:0]MCLK divider +#define I2S_MCLKDIV_DIV0 0 //MCLK = MCLK source +#define mskI2S_MCLKDIV_DIV0 (I2S_MCLKDIV_DIV0<<0) +#define I2S_MCLKDIV_DIV1 1 //MCLK = MCLK source / 2 +#define mskI2S_MCLKDIV_DIV1 (I2S_MCLKDIV_DIV1<<0) +#define I2S_MCLKDIV_DIV2 2 //MCLK = MCLK source / 4 +#define mskI2S_MCLKDIV_DIV2 (I2S_MCLKDIV_DIV2<<0) +#define I2S_MCLKDIV_DIV3 3 //MCLK = MCLK source / 6 +#define mskI2S_MCLKDIV_DIV3 (I2S_MCLKDIV_DIV3<<0) +#define I2S_MCLKDIV_DIV4 4 //MCLK = MCLK source / 8 +#define mskI2S_MCLKDIV_DIV4 (I2S_MCLKDIV_DIV4<<0) +#define I2S_MCLKDIV_DIV5 5 //MCLK = MCLK source / 10 +#define mskI2S_MCLKDIV_DIV5 (I2S_MCLKDIV_DIV5<<0) +#define I2S_MCLKDIV_DIV6 6 //MCLK = MCLK source / 12 +#define mskI2S_MCLKDIV_DIV6 (I2S_MCLKDIV_DIV6<<0) +#define I2S_MCLKDIV_DIV7 7 //MCLK = MCLK source / 14 +#define mskI2S_MCLKDIV_DIV7 (I2S_MCLKDIV_DIV7<<0) + + +#define I2S_MCLKOEN_OUTPUT_DIS 0 //[3:3]MCLK output enable bit +#define I2S_MCLKOEN_OUTPUT_EN 1 +#define mskI2S_MCLKOEN_OUTPUT_DIS (I2S_MCLKOEN_OUTPUT_DIS<<3) +#define mskI2S_MCLKOEN_OUTPUT_EN (I2S_MCLKOEN_OUTPUT_EN<<3) + + //[4:4]MCLK source selection bit +#define I2S_MCLKSEL_I2S_PCLK 0 //MCLK source of master is from I2S_PCLK +#define I2S_MCLKSEL_GPIO 1 //MCLK source of master is from GPIO +#define mskI2S_MCLKSEL_I2S_PCLK (I2S_MCLKSEL_I2S_PCLK<<4) +#define mskI2S_MCLKSEL_GPIO (I2S_MCLKSEL_GPIO<<4) + + //[15:8]BCLK divider +#define I2S_BCLKDIV_DIV 0 // MCLK/n, n = 2, 4, 6, 8, ...,512 +#define mskI2S_BCLKDIV_DIV (I2S_BCLKDIV_DIV<<8) + //[16:16]I2S clock source selection +#define I2S_CLKSEL_HCLK 0 //HCLK +#define I2S_CLKSEL_EHS 1 //EHS +#define mskI2S_CLKSEL_HCLK (I2S_CLKSEL_HCLK<<16) +#define mskI2S_CLKSEL_EHS (I2S_CLKSEL_EHS<<16) + + +/* I2S Status register (0x08) */ +#define mskI2S_I2SINT (0x1<<0) //I2S interrupt flag +#define mskI2S_RIGHTCH (0x1<<1) //Current channel status +#define mskI2S_TXFIFOTHF (0x1<<6) //TX FIFO threshold flag +#define mskI2S_RXFIFOTHF (0x1<<7) //RX FIFO threshold flag +#define mskI2S_TXFIFOFULL (0x1<<8) //TX FIFO full flag +#define mskI2S_RXFIFOFULL (0x1<<9) //RX FIFO full flag +#define mskI2S_TXFIFOEMPTY (0x1<<10) //TX FIFO empty flag +#define mskI2S_RXFIFOEMPTY (0x1<<11) //RX FIFO empty flag +#define mskI2S_TXFIFOLV (0xf<<12) //TX FIFO used level +#define mskI2S_RXFIFOLV (0xf<<17) //RX FIFO used level + + +/* I2S Interrupt Enable register (0x0C) */ +#define I2S_TXFIFOOVFIEN_DIS 0 //[4:4]TX FIFO overflow interrupt enable bit +#define I2S_TXFIFOOVFIEN_EN 1 +#define mskI2S_TXFIFOOVFIEN_DIS (I2S_TXFIFOOVFIEN_DIS<<4) +#define mskI2S_TXFIFOOVFIEN_EN (I2S_TXFIFOOVFIEN_EN<<4) + +#define I2S_RXFIFOUDFIEN_DIS 0 //[5:5]RX FIFO underflow interrupt enable bit +#define I2S_RXFIFOUDFIEN_EN 1 +#define mskI2S_RXFIFOUDFIEN_DIS (I2S_RXFIFOUDFIEN_DIS<<5) +#define mskI2S_RXFIFOUDFIEN_EN (I2S_RXFIFOUDFIEN_EN<<5) + +#define I2S_TXFIFOTHIEN_DIS 0 //[6:6]TX FIFO threshold interrupt enable bit +#define I2S_TXFIFOTHIEN_EN 1 +#define mskI2S_TXFIFOTHIEN_DIS (I2S_TXFIFOTHIEN_DIS<<6) +#define mskI2S_TXFIFOTHIEN_EN (I2S_TXFIFOTHIEN_EN<<6) + +#define I2S_RXFIFOTHIEN_DIS 0 //[7:7]RX FIFO threshold interrupt enable bit +#define I2S_RXFIFOTHIEN_EN 1 +#define mskI2S_RXFIFOTHIEN_DIS (I2S_RXFIFOTHIEN_DIS<<7) +#define mskI2S_RXFIFOTHIEN_EN (I2S_RXFIFOTHIEN_EN<<7) + + +/* I2S Raw Interrupt Status register (0x10) */ +/* I2S Interrupt Clear register (0x14) */ +#define mskI2S_TXFIFOOVIF (0x1<<4) //TX FIFO overflow interrupt flag +#define mskI2S_TXFIFOOVIC mskI2S_TXFIFOOVIF +#define mskI2S_RXFIFOUDIF (0x1<<5) //RX FIFO underflow interrupt flag +#define mskI2S_RXFIFOUDIC mskI2S_RXFIFOUDIF +#define mskI2S_TXFIFOTHIF (0x1<<6) //TX FIFO threshold interrupt flag +#define mskI2S_TXFIFOTHIC mskI2S_TXFIFOTHIF +#define mskI2S_RXFIFOTHIF (0x1<<7) //RX FIFO threshold interrupt flag +#define mskI2S_RXFIFOTHIC mskI2S_RXFIFOTHIF + + +/*_____ M A C R O S ________________________________________________________*/ +//I2S HCLK Enable/Disable +#define __I2S_ENABLE_I2SHCLK SN_SYS1->AHBCLKEN |= (1<<22) +#define __I2S_DISABLE_I2SHCLK SN_SYS1->AHBCLKEN &= ~(1<<22) + +//Reset I2S FIFO +#define __I2S_RESET_TXFIFO (SN_I2S->CTRL_b.CLRTXFIFO = I2S_CLRTXFIFO_RESET_TXFIFO) +#define __I2S_RESET_RXFIFO (SN_I2S->CTRL_b.CLRRXFIFO = I2S_CLRRXFIFO_RESET_RXFIFO) + +//I2S Start +#define __I2S_START (SN_I2S->CTRL_b.START = 1) + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +void I2S_Master_Init(void); +void I2S_Slave_Init(void); +void I2S_Enable(void); +void I2S_Disable(void); +void I2S_Interrupt_Enable(void); + +#endif /*__SN32F240_I2S_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/LCD/LCD.c b/os/hal/ports/SN32/LLD/SN32F24x/LCD/LCD.c new file mode 100644 index 00000000..68c47767 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/LCD/LCD.c @@ -0,0 +1,181 @@ +/******************** (C) COPYRIGHT 2013 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2013/12 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: LCD related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 1. First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include "LCD.h" +#include "..\..\System\SYS_con_drive.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ +#if LCD_TYPE == LCD_R_TYPE +/*********************************************************************************** +* Function : LCD_RtypeInit +* Description : Initialization of R-type LCD driver +* Input : None +* Output : None +* Return : None +* Note : User shall follow the notice in 16.6 R-TYPE LCD APPLICATION CIRCUIT +* to take care of the circuit. +***********************************************************************************/ +void LCD_RtypeInit(void) +{ + __LCD_ENABLE_LCDHCLK; //Enable HCLK for LCD + + //<-------------------- TODO: User modify on demand BEGIN --------------------> + //Setup LCD Driving ability, Clock rate, Duty, Bias, Type + SN_LCD->CTRL = (mskLCD_DRIVEP_LOW|mskLCD_RATE_DIV64|mskLCD_ONE_FOURTH_DUTY|mskLCD_ONE_THIRD_BIAS|mskLCD_R_TYPE); + + LCD_SelectClockSource(LCD_CLOCK_ILRC); //Setup LCD Clock source + + //Setup ITB bit, R-type resistance + SN_LCD->CTRL1 = (0|mskLCD_REF_400K); //Only value 0 is allowed for ITB bit + + __LCD_SEGMENT_GROUP1_ENABLE; //Enable SEG12~23 (P0.10~P0.15, P1.0~P1.5) as LCD pins + __LCD_SEGMENT_GROUP2_ENABLE; //Enable SEG24~31 (P0.0~P0.7) as LCD pins + //<-------------------- TODO: User modify on demand END --------------------> + + __LCD_ENABLE; //Enable LCD +} +#endif +#if LCD_TYPE == LCD_1C_TYPE +/*********************************************************************************** +* Function : LCD_1CtypeInit +* Description : Initialization of 1C-type LCD driver +* Input : None +* Output : None +* Return : None +* Note : User shall follow the notice in 16.7 C-TYPE LCD APPLICATION CIRCUIT +* to take care of the circuit. +***********************************************************************************/ +void LCD_1CtypeInit(void) +{ + __LCD_ENABLE_LCDHCLK; //Enable HCLK for LCD + + //<-------------------- TODO: User modify on demand BEGIN --------------------> + //Setup LCD Driving ability, Clock rate, Duty, Bias, Type + SN_LCD->CTRL = (mskLCD_DRIVEP_LOW|mskLCD_RATE_DIV64|mskLCD_ONE_FOURTH_DUTY| + mskLCD_ONE_THIRD_BIAS|mskLCD_1C_TYPE); + + LCD_SelectClockSource(LCD_CLOCK_ILRC); //Setup LCD Clock source + + //Setup IT1 bits, IT2 bits, VCP + SN_LCD->CCTRL1 = (0x44020000|mskLCD_1C_VCP_3P3V); + + __LCD_SEGMENT_GROUP1_ENABLE; //Enable SEG12~23 (P0.10~P0.15, P1.0~P1.5) as LCD pins + __LCD_SEGMENT_GROUP2_ENABLE; //Enable SEG24~31 (P0.0~P0.7) as LCD pins + //<-------------------- TODO: User modify on demand END --------------------> + + SN_LCD->CCTRL2 = 4; //Only value 0x4 is allowed + __LCD_ENABLE; //Enable LCD +} +#endif +#if LCD_TYPE == LCD_4C_TYPE +/*********************************************************************************** +* Function : LCD_4CtypeInit +* Description : Initialization of 4C-type LCD driver +* Input : None +* Output : None +* Return : None +* Note : User shall follow the notice in 16.7 C-TYPE LCD APPLICATION CIRCUIT +* to take care of the circuit. +***********************************************************************************/ +void LCD_4CtypeInit(void) +{ + __LCD_ENABLE_LCDHCLK; //Enable HCLK for LCD + + //<-------------------- TODO: User modify on demand BEGIN --------------------> + //Setup LCD Driving ability, Clock rate, Duty, Bias, Type + SN_LCD->CTRL = (mskLCD_DRIVEP_LOW|mskLCD_RATE_DIV64|mskLCD_ONE_FOURTH_DUTY| + mskLCD_ONE_THIRD_BIAS|mskLCD_4C_TYPE); + + LCD_SelectClockSource(LCD_CLOCK_ILRC); //Setup LCD Clock source + + //Setup IT1 bits, IT2 bits, VCP + SN_LCD->CCTRL1 = (0x44020000|mskLCD_4C_VCP_3P0V); + + __LCD_SEGMENT_GROUP1_ENABLE; //Enable SEG12~23 (P0.10~P0.15, P1.0~P1.5) as LCD pins + __LCD_SEGMENT_GROUP2_ENABLE; //Enable SEG24~31 (P0.0~P0.7) as LCD pins + //<-------------------- TODO: User modify on demand END --------------------> + + SN_LCD->CCTRL2 = 4; //Only value 0x4 is allowed + __LCD_ENABLE; //Enable LCD +} +#endif + +/*********************************************************************************** +* Function : LCD_SelectClockSource +* Description : Select LCD clcok source +* Input : LCD clock source - LCD_CLOCK_ILRC or LCD_CLOCK_ELS +* Output : None +* Return : None +* Note : None +***********************************************************************************/ +void LCD_SelectClockSource(uint32_t src) +{ + if (src == LCD_CLOCK_ELS) + SYS0_EnableELSXtal(); + + SN_LCD->CTRL_b.LCDCLK = src; +} + + +/*********************************************************************************** +* Function : LCD_FrameInterruptEnable +* Description : LCD Frame interrupt enable function +* Input : CEN - Enable/Disable counter (ENABLE or DISABLE) +* FCT - Frame counter threshold value +* IE - LCD interrupt Enable/Disable (ENABLE or DISABLE) +* Output : None +* Return : None +* Note : 0 < FCT < 32 +***********************************************************************************/ +void LCD_SetFrameCounterInterrupt(uint32_t CEN, uint32_t FCT, uint32_t IE) +{ + if (IE == ENABLE) + { + NVIC_ClearPendingIRQ(LCD_IRQn); + NVIC_EnableIRQ(LCD_IRQn); + } + + SN_LCD->FCC = (CEN | (FCT<<1) | (IE<<7)); +} + + +/***************************************************************************** +* Function : LCD_IRQHandler +* Description : ISR of LCD frame interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void LCD_IRQHandler(void) +{ + SN_LCD->RIS = 0; //Write 0 to clear LCD interurpt flag +} diff --git a/os/hal/ports/SN32/LLD/SN32F24x/LCD/LCD.h b/os/hal/ports/SN32/LLD/SN32F24x/LCD/LCD.h new file mode 100644 index 00000000..13004fef --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/LCD/LCD.h @@ -0,0 +1,140 @@ +#ifndef __SN32F240_LCD_H +#define __SN32F240_LCD_H + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +#define LCD_TYPE LCD_R_TYPE //LCD_R_TYPE, LCD_1C_TYPE, or LCD_4C_TYPE + +//LCD Panel driving ability +#define LCD_DRIVEP_STRONG 0 +#define LCD_DRIVEP_MEDIUM 1 +#define LCD_DRIVEP_LOW 3 +#define mskLCD_DRIVEP_STRONG (LCD_DRIVEP_STRONG<<28) +#define mskLCD_DRIVEP_MEDIUM (LCD_DRIVEP_MEDIUM<<28) +#define mskLCD_DRIVEP_LOW (LCD_DRIVEP_LOW<<28) + +//LCD_PCLK rate +#define LCD_RATE_DIV64 0 +#define LCD_RATE_DIV128 1 +#define mskLCD_RATE_DIV64 (LCD_RATE_DIV64<<11) +#define mskLCD_RATE_DIV128 (LCD_RATE_DIV128<<11) + +//LCD Clock source +#define LCD_CLOCK_ILRC 0 +#define LCD_CLOCK_ELS 1 +#define mskLCD_CLOCK_ILRC (LCD_CLOCK_ILRC<<10) +#define mskLCD_CLOCK_ELS (LCD_CLOCK_ELS<<10) + +//LCD Duty +#define LCD_HALF_DUTY 1 // 1/2 duty +#define LCD_ONE_THIRD_DUTY 2 // 1/3 duty +#define LCD_ONE_FOURTH_DUTY 3 // 1/4 duty +#define mskLCD_HALF_DUTY (LCD_HALF_DUTY<<8) +#define mskLCD_ONE_THIRD_DUTY (LCD_ONE_THIRD_DUTY<<8) +#define mskLCD_ONE_FOURTH_DUTY (LCD_ONE_FOURTH_DUTY<<8) + +//LCD Bias +#define LCD_ONE_THIRD_BIAS 0 // 1/3 bias +#define LCD_HALF_BIAS 1 // 1/2 bias +#define mskLCD_ONE_THIRD_BIAS (LCD_ONE_THIRD_BIAS<<4) +#define mskLCD_HALF_BIAS (LCD_HALF_BIAS<<4) + +//LCD Type +#define LCD_R_TYPE 0 +#define LCD_4C_TYPE 1 +#define LCD_1C_TYPE 2 +#define mskLCD_R_TYPE (LCD_R_TYPE<<2) +#define mskLCD_4C_TYPE (LCD_4C_TYPE<<2) +#define mskLCD_1C_TYPE (LCD_1C_TYPE<<2) + +//LCD R-type resistance +#define LCD_REF_400K 0 +#define LCD_REF_200K 1 +#define LCD_REF_100K 2 +#define LCD_REF_35K 3 +#define mskLCD_REF_400K (LCD_REF_400K<<1) +#define mskLCD_REF_200K (LCD_REF_200K<<1) +#define mskLCD_REF_100K (LCD_REF_100K<<1) +#define mskLCD_REF_35K (LCD_REF_35K<<1) + +//LCD 1C-type VCP +#define mskLCD_1C_VCP_2P7V 0 +#define mskLCD_1C_VCP_2P8V 1 +#define mskLCD_1C_VCP_2P9V 2 +#define mskLCD_1C_VCP_3P0V 3 +#define mskLCD_1C_VCP_3P1V 4 +#define mskLCD_1C_VCP_3P2V 5 +#define mskLCD_1C_VCP_3P3V 6 +#define mskLCD_1C_VCP_3P4V 7 + +//LCD 4C-type VCP +#define mskLCD_4C_VCP_2P7V 0 +#define mskLCD_4C_VCP_2P8V 1 +#define mskLCD_4C_VCP_2P9V 2 +#define mskLCD_4C_VCP_3P0V 3 +#define mskLCD_4C_VCP_3P06V 4 +#define mskLCD_4C_VCP_3P14V 5 +#define mskLCD_4C_VCP_3P2V 6 +#define mskLCD_4C_VCP_3P3V 7 +#define mskLCD_4C_VCP_3P4V 8 +#define mskLCD_4C_VCP_3P6V 9 +#define mskLCD_4C_VCP_3P8V 10 +#define mskLCD_4C_VCP_4P0V 11 +#define mskLCD_4C_VCP_4P2V 12 +#define mskLCD_4C_VCP_4P4V 13 +#define mskLCD_4C_VCP_4P7V 14 +#define mskLCD_4C_VCP_5P0V 15 + +//LCD Frame Interrupt Enable/Disable +#define LCD_FRAME_IE_ENABLE 1 +#define LCD_FRAME_IE_DISABLE 0 +#define mskLCD_FRAME_IE_ENABLE (LCD_FRAME_IE_ENABLE<<7) +#define mskLCD_FRAME_IE_DISABLE (LCD_FRAME_IE_DISABLE<<7) + +//LCD Frame Counter Enable/Disable +#define LCD_FRAME_COUNTER_ENABLE 1 +#define LCD_FRAME_COUNTER_DISABLE 0 +#define mskLCD_FRAME_COUNTER_ENABLE LCD_FRAME_COUNTER_ENABLE +#define mskLCD_FRAME_COUNTER_DISABLE LCD_FRAME_COUNTER_DISABLE + +//LCD Frame Counter Threshold +#define LCD_FRAME_COUNTER_THRESHOLD 31 //0 < LCD_FRAME_COUNTER_THRESHOLD < 32 + + +/*_____ M A C R O S ________________________________________________________*/ + +//LCD HCLK Enable/Disable +#define __LCD_ENABLE_LCDHCLK SN_SYS1->AHBCLKEN |= (1<<2) +#define __LCD_DISABLE_LCDHCLK SN_SYS1->AHBCLKEN &= ~(1<<2) + +//LCD Driver Enable/Disable +#define __LCD_ENABLE SN_LCD->CTRL |= 0x1 +#define __LCD_DISENABLE SN_LCD->CTRL &= ~0x1 + +//LCD SEGMENT Group 2 Enable/Disable +#define __LCD_SEGMENT_GROUP2_ENABLE SN_LCD->CTRL_b.SEGSEL2 = ENABLE +#define __LCD_SEGMENT_GROUP2_DISABLE SN_LCD->CTRL_b.SEGSEL2 = DISABLE + +//LCD SEGMENT Group 1 Enable/Disable +#define __LCD_SEGMENT_GROUP1_ENABLE SN_LCD->CTRL_b.SEGSEL1 = ENABLE +#define __LCD_SEGMENT_GROUP1_DISABLE SN_LCD->CTRL_b.SEGSEL1 = DISABLE + +//LCD Blank mode Enable/Disable +#define __LCD_DISPLAY_BLANK_ENABLE SN_LCD->CTRL1_b.LCDBNK = ENABLE +#define __LCD_DISPLAY_BLANK_DISABLE SN_LCD->CTRL1_b.LCDBNK = DISABLE + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + +void LCD_RtypeInit(void); +void LCD_1CtypeInit(void); +void LCD_4CtypeInit(void); +void LCD_SelectClockSource(uint32_t src); +void LCD_SetFrameCounterInterrupt(uint32_t CEN, uint32_t FCT, uint32_t IE); + + +#endif /*__SN32F760_PMU_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/RTC/RTC.c b/os/hal/ports/SN32/LLD/SN32F24x/RTC/RTC.c new file mode 100644 index 00000000..ad0c2dc1 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/RTC/RTC.c @@ -0,0 +1,153 @@ +/******************** (C) COPYRIGHT 2013 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2013/12 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: RTC related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include "RTC.h" +#include "..\..\System\SYS_con_drive.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + +/*_____ D E F I N I T I O N S ______________________________________________*/ + +/*_____ M A C R O S ________________________________________________________*/ + +/*_____ F U N C T I O N S __________________________________________________*/ + +/***************************************************************************** +* Function : RTC_IRQHandler +* Description : None +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void RTC_IRQHandler(void) +{ + if(SN_RTC->RIS & mskRTC_SECIF) + { + SN_GPIO0->DATA_b.DATA0 = ~SN_GPIO0->DATA_b.DATA0; + + SN_RTC->IC = mskRTC_SECIC; //Clear Second interrupt status + } + + if(SN_RTC->RIS & mskRTC_ALMIF) + { + + SN_GPIO0->DATA_b.DATA1 = ~SN_GPIO0->DATA_b.DATA1; + + SN_RTC->IC = mskRTC_ALMIC; //Clear Alarm interrupt status + } + + if(SN_RTC->RIS & mskRTC_OVFIF) + { + SN_GPIO0->DATA_b.DATA2 = ~SN_GPIO0->DATA_b.DATA2; + + SN_RTC->IC = mskRTC_OVFIC; //Clear Overflow interrupt status + } +} + + +/***************************************************************************** +* Function : RTC_Initial +* Description : RTC initial set +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void RTC_Init(void) +{ + __RTC_ENABLE_RTCHCLK; //Enable HCLK for RTC + + #if RTC_MODE == SECOND //Second will occur every 1 second + RTC_SelectClockSource(RTC_CLKSEL_ELS); //Clock Source select + SN_RTC->IE = mskRTC_SECIE_ENABLE; //Enable Second Interrupt + __RTC_SECCNTV(32767); //Second counter reload value + + #endif + + #if RTC_MODE == ALARM //Alarm will occur after 10 seconds + RTC_SelectClockSource(RTC_CLKSEL_ELS); //Clock Source select + SN_RTC->IE = mskRTC_ALMIE_ENABLE; //Enable Alarm Interrupt + __RTC_SECCNTV(32767); //Second counter reload value + __RTC_ALMCNTV(9); //Alarm counter reload value + #endif + + #if RTC_MODE == OVERFLOW //Overflow will occur in 54975.58139 seconds(15.271 hours) + RTC_SelectClockSource(RTC_CLKSEL_EHS); //Clock Source select + SN_RTC->IE = + (mskRTC_OVFIE_ENABLE | mskRTC_ALMIE_ENABLE); //Enable Overflow Interrupt + __RTC_SECCNTV(1); //Second counter reload value & Second will occur in 12.8u second + __RTC_ALMCNTV(75000000); //Alarm counter reload value & Alarm will occur in 960 seconds(16 minutes) + #endif + + //Enable RTC NVIC interrupt + RTC_NvicEnable(); + + __RTC_ENABLE; //Enable RTC +} +/*********************************************************************************** +* Function : RTC_SelectClockSource +* Description : Select RTC clcok source +* Input : RTC clock source - + RTC_CLKSEL_ILRC or RTC_CLKSEL_ELS or RTC_CLKSEL_EHS +* Output : None +* Return : None +* Note : None +***********************************************************************************/ +void RTC_SelectClockSource(uint32_t src) +{ + if (src == RTC_CLKSEL_ELS) + SYS0_EnableELSXtal(); + else if (src == RTC_CLKSEL_EHS) + SYS0_EnableEHSXtal(SYS0_EHS_FREQ_DRIVE_HIGH); + + SN_RTC->CLKS = src; //clock source select +} +/***************************************************************************** +* Function : RTC_NvicEnable +* Description : Enable RTC interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void RTC_NvicEnable(void) +{ + NVIC_ClearPendingIRQ(RTC_IRQn); + NVIC_EnableIRQ(RTC_IRQn); + NVIC_SetPriority(RTC_IRQn,0); // Set interrupt priority (default) +} + +/***************************************************************************** +* Function : RTC_NvicDisable +* Description : Disable RTC interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void RTC_NvicDisable(void) +{ + NVIC_DisableIRQ(RTC_IRQn); +} + + diff --git a/os/hal/ports/SN32/LLD/SN32F24x/RTC/RTC.h b/os/hal/ports/SN32/LLD/SN32F24x/RTC/RTC.h new file mode 100644 index 00000000..05a9642e --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/RTC/RTC.h @@ -0,0 +1,66 @@ +#ifndef __SN32F240_RTC_H +#define __SN32F240_RTC_H + + +/*_____ I N C L U D E S ____________________________________________________*/ +#include + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +#define SECOND 0 +#define ALARM 1 +#define OVERFLOW 2 +#define RTC_MODE SECOND //SECOND, ALARM, OVERFLOW + +//RTC enable +#define mskRTC_RTCEN_DISABLE 0 +#define mskRTC_RTCEN_ENABLE 1 + +//RTC Clock source +#define RTC_CLKSEL_ILRC 0 +#define RTC_CLKSEL_ELS 1 +#define RTC_CLKSEL_EHS 3 + +//RTC Interrupt Enable/Disable +#define RTC_IE_ENABLE 1 +#define RTC_IE_DISABLE 0 + +#define mskRTC_SECIE_ENABLE RTC_IE_ENABLE +#define mskRTC_SECIE_DISABLE RTC_IE_DISABLE + +#define mskRTC_ALMIE_ENABLE (RTC_IE_ENABLE<<1) +#define mskRTC_ALMIE_DISABLE (RTC_IE_DISABLE<<1) + +#define mskRTC_OVFIE_ENABLE (RTC_IE_ENABLE<<2) +#define mskRTC_OVFIE_DISABLE (RTC_IE_DISABLE<<2) + +#define mskRTC_SECIF (0x1<<0) //Interrupt flag for Second +#define mskRTC_ALMIF (0x1<<1) //Interrupt flag for Alarm +#define mskRTC_OVFIF (0x1<<2) //Interrupt flag for Overflow + +#define mskRTC_SECIC mskRTC_SECIF +#define mskRTC_ALMIC mskRTC_ALMIF +#define mskRTC_OVFIC mskRTC_OVFIF + +/*_____ M A C R O S ________________________________________________________*/ +//LCD HCLK Enable/Disable +#define __RTC_ENABLE_RTCHCLK (SN_SYS1->AHBCLKEN |= (1<<23)) +#define __RTC_DISABLE_RTCHCLK (SN_SYS1->AHBCLKEN &= ~(1<<23)) + +//RTC Enable/Disable +#define __RTC_ENABLE (SN_RTC->CTRL |= mskRTC_RTCEN_ENABLE) + +#define __RTC_SECCNTV(value) (SN_RTC->SECCNTV = value) + +#define __RTC_ALMCNTV(value) (SN_RTC->ALMCNTV = value) + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +void RTC_Init(void); + +void RTC_SelectClockSource(uint32_t src); + +void RTC_NvicEnable(void); + +void RTC_NvicDisable(void); + +#endif /*__SN32F240_RTC_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/SPI/SPI.h b/os/hal/ports/SN32/LLD/SN32F24x/SPI/SPI.h new file mode 100644 index 00000000..0a081261 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/SPI/SPI.h @@ -0,0 +1,188 @@ +#ifndef __SN32F240_SSP_H +#define __SN32F240_SSP_H + + +/*_____ I N C L U D E S ____________________________________________________*/ + +/*_____ D E F I N I T I O N S ______________________________________________*/ +/* +Base Address: 0x4001 C000 (SSP0) + 0x4005 8000 (SSP1) +*/ + +/* SSP n Control register 0 (0x00) */ +#define SSP_SSPEN_DIS 0 //[0:0] SSP enable bit +#define SSP_SSPEN_EN 1 +#define mskSSP_SSPEN_DIS (SSP_SSPEN_DIS<<0) +#define mskSSP_SSPEN_EN (SSP_SSPEN_EN<<0) + + //[1:1] Loop back mode disable +#define SSP_LOOPBACK_DIS 0 //Disable +#define SSP_LOOPBACK_EN 1 //Data input from data output +#define mskSSP_LOOPBACK_DIS (SSP_LOOPBACK_DIS<<1) +#define mskSSP_LOOPBACK_EN (SSP_LOOPBACK_EN<<1) + + //[2:2] Slave data output disable bit (ONLY used in slave mode) +#define SSP_SDODIS_EN 0 //Enable slave data output +#define SSP_SDODIS_DIS 1 //Disable slave data output. (MISO=0) +#define mskSSP_SDODIS_EN (SSP_SDODIS_EN<<2) +#define mskSSP_SDODIS_DIS (SSP_SDODIS_DIS<<2) + +#define SSP_MS_MASTER_MODE 0 //[3:3] Master/Slave selection bit +#define SSP_MS_SLAVE_MODE 1 +#define mskSSP_MS_MASTER_MODE (SSP_MS_MASTER_MODE<<3) +#define mskSSP_MS_SLAVE_MODE (SSP_MS_SLAVE_MODE<<3) + +#define SSP_FORMAT_SPI_MODE 0 //[4:4] Interface format +#define SSP_FORMAT_SSP_MODE 1 +#define mskSSP_FORMAT_SPI_MODE (SSP_FORMAT_SPI_MODE<<4) +#define mskSSP_FORMAT_SSP_MODE (SSP_FORMAT_SSP_MODE<<4) + + //[7:6] SSP FSM and FIFO Reset bit +#define SSP_FRESET_DO_NOTHING 0 //Do nothing +#define SSP_FRESET_RESET_FIFO 3 //Reset finite state machine and FIFO +#define mskSSP_FRESET_DO_NOTHING (SSP_FRESET_DO_NOTHING<<6) +#define mskSSP_FRESET_RESET_FIFO (SSP_FRESET_RESET_FIFO<<6) + +#define SSP_DL_3 2 //[11:8] Data Length = DL[3:0]+1 +#define SSP_DL_4 3 +#define SSP_DL_5 4 +#define SSP_DL_6 5 +#define SSP_DL_7 6 +#define SSP_DL_8 7 +#define SSP_DL_9 8 +#define SSP_DL_10 9 +#define SSP_DL_11 10 +#define SSP_DL_12 11 +#define SSP_DL_13 12 +#define SSP_DL_14 13 +#define SSP_DL_15 14 +#define SSP_DL_16 15 + +#define SSP_TXFIFOTH_0 0 //[14:12]TX FIFO Threshold level +#define SSP_TXFIFOTH_1 1 +#define SSP_TXFIFOTH_2 2 +#define SSP_TXFIFOTH_3 3 +#define SSP_TXFIFOTH_4 4 +#define SSP_TXFIFOTH_5 5 +#define SSP_TXFIFOTH_6 6 +#define SSP_TXFIFOTH_7 7 + +#define SSP_RXFIFOTH_0 0 //[17:15]RX FIFO Threshold level +#define SSP_RXFIFOTH_1 1 +#define SSP_RXFIFOTH_2 2 +#define SSP_RXFIFOTH_3 3 +#define SSP_RXFIFOTH_4 4 +#define SSP_RXFIFOTH_5 5 +#define SSP_RXFIFOTH_6 6 +#define SSP_RXFIFOTH_7 7 + + //[18:18]Auto-SEL disable bit. For SPI mode only. +#define SSP_SELDIS_EN 0 //Enable Auto-SEL flow control +#define SSP_SELDIS_DIS 1 //Disable Auto-SEL flow control +#define mskSSP_SELDIS_EN (SSP_SELDIS_EN<<18) +#define mskSSP_SELDIS_DIS (SSP_SELDIS_DIS<<18) + + +/* SSP n Control register 1 (0x04) */ + //[0:0]MSB/LSB selection bit +#define SSP_MLSB_MSB 0 //MSB transmit first +#define SSP_MLSB_LSB 1 //LSB transmit first +#define mskSSP_MLSB_MSB (SSP_MLSB_MSB<<0) +#define mskSSP_MLSB_LSB (SSP_MLSB_LSB<<0) + + //[1:1]Clock polarity selection bit +#define SSP_CPOL_SCK_IDLE_LOW 0 //SCK idles at Low level +#define SSP_CPOL_SCK_IDLE_HIGH 1 //SCK idles at High level +#define mskSSP_CPOL_SCK_IDLE_LOW (SSP_CPOL_SCK_IDLE_LOW<<1) +#define mskSSP_CPOL_SCK_IDLE_HIGH (SSP_CPOL_SCK_IDLE_HIGH<<1) + + //[2:2]Clock phase for edge sampling +#define SSP_CPHA_FALLING_EDGE 0 //Data changes at clock falling edge +#define SSP_CPHA_RISING_EDGE 1 //Data changes at clock rising edge +#define mskSSP_CPHA_FALLING_EDGE (SSP_CPHA_FALLING_EDGE<<2) +#define mskSSP_CPHA_RISING_EDGE (SSP_CPHA_RISING_EDGE<<2) + + +/* SSP n Clock Divider register (0x08) */ + //[7:0]SSPn clock divider +#define SSP_DIV 6 //MCLK/n, n = 2, 4, 6, 8, ...,512 + + +/* SSP n Status register (0x0C) */ +#define mskSSP_TX_EMPTY (0x1<<0) //TX FIFO empty flag +#define mskSSP_TX_FULL (0x1<<1) //TX FIFO full flag +#define mskSSP_RX_EMPTY (0x1<<2) //RX FIFO empty flag +#define mskSSP_RX_FULL (0x1<<3) //RX FIFO full flag +#define mskSSP_BUSY (0x1<<4) //Busy flag +#define mskSSP_TXFIFOTHF (0x1<<5) //TX FIFO threshold flag +#define mskSSP_RXFIFOTHF (0x1<<6) //RX FIFO threshold flag + + +/* SSP n Interrupt Enable register (0x10) */ +#define SSP_RXOVFIE_DIS 0 //[0:0]RX Overflow interrupt enable +#define SSP_RXOVFIE_EN 1 +#define mskSSP_RXOVFIE_DIS (SSP_RXOVFIE_DIS<<0) +#define mskSSP_RXOVFIE_EN (SSP_RXOVFIE_EN<<0) + +#define SSP_RXTOIE_DIS 0 //[1:1]RX time-out interrupt enable +#define SSP_RXTOIE_EN 1 +#define mskSSP_RXTOIE_DIS (SSP_RXTOIE_DIS<<1) +#define mskSSP_RXTOIE_EN (SSP_RXTOIE_EN<<1) + +#define SSP_RXFIFOTHIE_DIS 0 //[2:2]RX FIFO threshold interrupt enable +#define SSP_RXFIFOTHIE_EN 1 +#define mskSSP_RXFIFOTHIE_DIS (SSP_RXFIFOTHIE_DIS<<2) +#define mskSSP_RXFIFOTHIE_EN (SSP_RXFIFOTHIE_EN <<2) + +#define SSP_TXFIFOTHIE_DIS 0 //[3:3]TX FIFO threshold interrupt enable +#define SSP_TXFIFOTHIE_EN 1 +#define mskSSP_TXFIFOTHIE_DIS (SSP_TXFIFOTHIE_DIS<<3) +#define mskSSP_TXFIFOTHIE_EN (SSP_TXFIFOTHIE_EN<<3) + + +/* SSP n Raw Interrupt Status register (0x14) */ +/* SSP n Interrupt Clear register (0x18) */ +#define mskSSP_RXOVFIF (0x1<<0) //[0:0]RX overflow interrupt flag +#define mskSSP_RXOVFIC mskSSP_RXOVFIF + +#define mskSSP_RXTOIF (0x1<<1) //[1:1]RX time-out interrupt flag +#define mskSSP_RXTOIC mskSSP_RXTOIF + +#define mskSSP_RXFIFOTHIF (0x1<<2) //[2:2]RX FIFO threshold interrupt flag +#define mskSSP_RXFIFOTHIC mskSSP_RXFIFOTHIF + +#define mskSSP_TXFIFOTHIF (0x1<<3) //[3:3]TX FIFO threshold interrupt flag +#define mskSSP_TXFIFOTHIC mskSSP_TXFIFOTHIF + + +/* SSP n Data Fetch register (0x20) */ + //[0:0]SSP data fetch control bit +#define SSP_DF_DIS 0 //Disable +#define SSP_DF_EN 1 //Enable when SCKn frequency > 6MHz +#define mskSSP_DF_DIS (SSP_DF_DIS<<0) +#define mskSSP_SSP_DF_EN (SSP_DF_EN<<0) + + +/*_____ M A C R O S ________________________________________________________*/ +#define __SPI0_FIFO_RESET (SN_SSP0->CTRL0_b.FRESET = SSP_FRESET_RESET_FIFO) +#define __SPI1_FIFO_RESET (SN_SSP1->CTRL0_b.FRESET = SSP_FRESET_RESET_FIFO) +#define __SPI0_CLR_SEL0 (SN_GPIO2->DATA_b.DATA15=0) +#define __SPI0_SET_SEL0 (SN_GPIO2->DATA_b.DATA15=1) +#define __SPI1_CLR_SEL1 (SN_GPIO2->DATA_b.DATA14=0) +#define __SPI1_SET_SEL1 (SN_GPIO2->DATA_b.DATA14=1) +//SSP Data Fetch speed (High: SCK>6MHz) +#define __SSP0_DATA_FETCH_HIGH_SPEED (SN_SSP0->DF = SSP_DF_EN) //*(volatile unsigned long *)(0x4001C020) = 1 +#define __SSP1_DATA_FETCH_HIGH_SPEED (SN_SSP1->DF = SSP_DF_EN) //*(volatile unsigned long *)(0x40058020) = 1 + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +extern void SPI0_Init(void); +extern void SPI0_Enable(void); +extern void SPI0_Disable(void); + +extern void SPI1_Init(void); +extern void SPI1_Enable(void); +extern void SPI1_Disable(void); +#endif /*__SN32F760_SSP_H*/ + diff --git a/os/hal/ports/SN32/LLD/SN32F24x/SPI/SPI0.c b/os/hal/ports/SN32/LLD/SN32F24x/SPI/SPI0.c new file mode 100644 index 00000000..b27d760d --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/SPI/SPI0.c @@ -0,0 +1,124 @@ +/******************** (C) COPYRIGHT 2014 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2014/05 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: SPI0 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 1. First release +* 1.1 2014/05/23 SA1 1. Add __SSP0_DATA_FETCH_HIGH_SPEED macro +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include "SPI.h" +#include "..\..\Utility\Utility.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + +/***************************************************************************** +* Function : SPI0_Init +* Description : Initialization of SPI0 init +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void SPI0_Init(void) +{ + //Enable HCLK for SSP0 + SN_SYS1->AHBCLKEN |= (0x1 << 12); //Enable clock for SSP0. + + //SSP0 PCLK + SN_SYS1->APBCP0 |= (0x00 << 20); //PCLK = HCLK/1 + //SN_SYS1->APBCP0 |= (0x01 << 20); //PCLK = HCLK/2 + //SN_SYS1->APBCP0 |= (0x02 << 20); //PCLK = HCLK/4 + //SN_SYS1->APBCP0 |= (0x03 << 20); //PCLK = HCLK/8 + //SN_SYS1->APBCP0 |= (0x04 << 20); //PCLK = HCLK/16 + + //SSP0 setting + SN_SSP0->CTRL0_b.DL = SSP_DL_8; //3 ~ 16 Data length + SN_SSP0->CTRL0_b.FORMAT = SSP_FORMAT_SPI_MODE; //Interface format + SN_SSP0->CTRL0_b.MS = SSP_MS_MASTER_MODE; //Master/Slave selection bit + SN_SSP0->CTRL0_b.LOOPBACK = SSP_LOOPBACK_DIS; //Loop back mode + SN_SSP0->CTRL0_b.SDODIS = SSP_SDODIS_EN; //Slave data output + //(ONLY used in slave mode) + + SN_SSP0->CLKDIV_b.DIV = (SSP_DIV/2) - 1; //SSPn clock divider + + //SSP0 SPI mode + SN_SSP0->CTRL1 = SSP_CPHA_FALLING_EDGE| //Clock phase for edge sampling + SSP_CPOL_SCK_IDLE_LOW| //Clock polarity selection bit + SSP_MLSB_MSB; //MSB/LSB selection bit + + //SSP0 SEL0 setting + SN_SSP0->CTRL0_b.SELDIS = SSP_SELDIS_DIS; //Auto-SEL disable bit + SN_GPIO2->MODE_b.MODE15=1; //SEL(P2.15) is outout high + __SPI0_SET_SEL0; + + //SSP0 Fifo reset + __SPI0_FIFO_RESET; + + //SSP0 interrupt enable + NVIC_ClearPendingIRQ(SSP0_IRQn); + NVIC_EnableIRQ(SSP0_IRQn); + //NVIC_SetPriority(SSP0_IRQn,0); + + //__SSP0_DATA_FETCH_HIGH_SPEED; //Enable if Freq. of SCK > 6MHz + + //SSP0 enable + SN_SSP0->CTRL0_b.SSPEN = SSP_SSPEN_EN; //SSP enable bit +} + +/***************************************************************************** +* Function : SPI0_Enable +* Description : SPI0 enable setting +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void SPI0_Enable(void) +{ + //Enable HCLK for SSP0 + SN_SYS1->AHBCLKEN |= (0x1 << 12); //Enable clock for SSP0. + + SN_SSP0->CTRL0_b.SSPEN = SSP_SSPEN_EN; //SSP enable bit + __SPI0_FIFO_RESET; +} + +/***************************************************************************** +* Function : SPI0_Disable +* Description : SPI0 disable setting +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void SPI0_Disable(void) +{ + SN_SSP0->CTRL0_b.SSPEN = SSP_SSPEN_DIS; //SSP disable bit + + //Disable HCLK for SSP0 + SN_SYS1->AHBCLKEN &=~ (0x1 << 12); //Disable clock for SSP0. +} + diff --git a/os/hal/ports/SN32/LLD/SN32F24x/SPI/SPI1.c b/os/hal/ports/SN32/LLD/SN32F24x/SPI/SPI1.c new file mode 100644 index 00000000..f327399a --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/SPI/SPI1.c @@ -0,0 +1,123 @@ +/******************** (C) COPYRIGHT 2014 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2014/05 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: SPI1 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 1. First release +* 1.1 2014/05/23 SA1 1. Add __SSP1_DATA_FETCH_HIGH_SPEED macro +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include "SPI.h" +#include "..\..\Utility\Utility.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + +/***************************************************************************** +* Function : SPI1_Init +* Description : Initialization of SPI1 init +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void SPI1_Init(void) +{ + //Enable HCLK for SSP1 + SN_SYS1->AHBCLKEN |= (0x1 << 13); //Enable clock for SSP1. + + //SSP1 PCLK + SN_SYS1->APBCP0 |= (0x00 << 24); //PCLK = HCLK/1 + //SN_SYS1->APBCP0 |= (0x01 << 24); //PCLK = HCLK/2 + //SN_SYS1->APBCP0 |= (0x02 << 24); //PCLK = HCLK/4 + //SN_SYS1->APBCP0 |= (0x03 << 24); //PCLK = HCLK/8 + //SN_SYS1->APBCP0 |= (0x04 << 24); //PCLK = HCLK/16 + + //SSP1 setting + SN_SSP1->CTRL0_b.DL = SSP_DL_8; //3 ~ 16 Data length + SN_SSP1->CTRL0_b.FORMAT = SSP_FORMAT_SPI_MODE; //Interface format + SN_SSP1->CTRL0_b.MS = SSP_MS_MASTER_MODE; //Master/Slave selection bit + SN_SSP1->CTRL0_b.LOOPBACK = SSP_LOOPBACK_DIS; //Loop back mode + SN_SSP1->CTRL0_b.SDODIS = SSP_SDODIS_EN; //Slave data output + + SN_SSP1->CLKDIV_b.DIV = (SSP_DIV/2) - 1; //SSPn clock divider + + //SSP1 SPI mode + SN_SSP1->CTRL1 = SSP_CPHA_FALLING_EDGE| //Clock phase for edge sampling + SSP_CPOL_SCK_IDLE_LOW| //Clock polarity selection bit + SSP_MLSB_MSB; //MSB/LSB selection bit + + //SSP1 SEL1 Setting + SN_SSP1->CTRL0_b.SELDIS = SSP_SELDIS_DIS; //Auto-SEL disable bit + SN_GPIO2->MODE_b.MODE14=1; //SEL1(P2.14) is outout high + __SPI1_SET_SEL1; + + //SSP1 Fifo reset + __SPI1_FIFO_RESET; + + //SSP1 interrupt enable + NVIC_ClearPendingIRQ(SSP1_IRQn); + NVIC_EnableIRQ(SSP1_IRQn); + //NVIC_SetPriority(SSP1_IRQn,0); + + //__SSP1_DATA_FETCH_HIGH_SPEED; //Enable if Freq. of SCK > 6MHz + + //SSP1 enable + SN_SSP1->CTRL0_b.SSPEN = SSP_SSPEN_EN; //SSP enable bit +} + +/***************************************************************************** +* Function : SPI1_Enable +* Description : SPI1 enable setting +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void SPI1_Enable(void) +{ + //Enable HCLK for SSP1 + SN_SYS1->AHBCLKEN |= (0x1 << 13); //Enable clock for SSP0. + + SN_SSP1->CTRL0_b.SSPEN = SSP_SSPEN_EN; //SSP enable bit + __SPI1_FIFO_RESET; +} + +/***************************************************************************** +* Function : SPI1_Disable +* Description : SPI1 disable setting +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void SPI1_Disable(void) +{ + SN_SSP1->CTRL0_b.SSPEN = SSP_SSPEN_DIS; //SSP disable bit + + //Disable HCLK for SSP1 + SN_SYS1->AHBCLKEN &=~ (0x1 << 13); //Disable clock for SSP0. +} + diff --git a/os/hal/ports/SN32/LLD/SN32F24x/SysTick/SysTick.c b/os/hal/ports/SN32/LLD/SN32F24x/SysTick/SysTick.c new file mode 100644 index 00000000..809651e7 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/SysTick/SysTick.c @@ -0,0 +1,71 @@ +/******************** (C) COPYRIGHT 2013 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2013/12 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: SysTick related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include "SysTick.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ +/***************************************************************************** +* Function : SysTick_Init +* Description : Initialization of SysTick timer +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void SysTick_Init (void) +{ + SystemCoreClockUpdate(); + + __SYSTICK_SET_TIMER_PERIOD(10); //RELOAD = (system tick clock frequency ¡Ñ 10 ms)/1000 -1 + + __SYSTICK_CLEAR_COUNTER_AND_FLAG; + +#if SYSTICK_IRQ == INTERRUPT_METHOD + SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt +#else + SysTick->CTRL = 0x5; //Enable SysTick timer ONLY +#endif +} + + +/***************************************************************************** +* Function : SysTick_Handler +* Description : ISR of SysTick interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void SysTick_Handler(void) +{ + __SYSTICK_CLEAR_COUNTER_AND_FLAG; +} + + diff --git a/os/hal/ports/SN32/LLD/SN32F24x/SysTick/SysTick.h b/os/hal/ports/SN32/LLD/SN32F24x/SysTick/SysTick.h new file mode 100644 index 00000000..2cc58844 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/SysTick/SysTick.h @@ -0,0 +1,23 @@ +#ifndef __SN32F240_SYSTICK_H +#define __SN32F240_SYSTICK_H + + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +#define SYSTICK_IRQ POLLING_METHOD //INTERRUPT_METHOD: Enable SysTick timer and interrupt + //POLLING_METHOD: Enable SysTick timer ONLY + +/*_____ M A C R O S ________________________________________________________*/ +#define __SYSTICK_SET_TIMER_PERIOD(ms) SysTick->LOAD = SystemCoreClock * ms /1000 - 1 +#define __SYSTICK_CLEAR_COUNTER_AND_FLAG SysTick->VAL = 0xFF + + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +void SysTick_Init(void); + +#endif /*__SN32F240_SYSTICK_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USART/USART.h b/os/hal/ports/SN32/LLD/SN32F24x/USART/USART.h new file mode 100644 index 00000000..fce22108 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/USART/USART.h @@ -0,0 +1,233 @@ +#ifndef __SN32F240_USART_H +#define __SN32F240_USART_H + + +/*_____ I N C L U D E S ____________________________________________________*/ +#include + +/*_____ D E F I N I T I O N S ______________________________________________*/ +/* +Base Address: 0x4001 6000 (USART0) + 0x4005 6000 (USART1) +*/ +#define USART0_CLK_EN (0x01<<16) +#define USART1_CLK_EN (0x01<<17) + +#define USART0_PLKSEL_DIV1 (0x00) +#define USART0_PLKSEL_DIV2 (0x01) +#define USART0_PLKSEL_DIV4 (0x02) +#define USART0_PLKSEL_DIV8 (0x03) +#define USART0_PLKSEL_DIV16 (0x04) + +#define USART1_PLKSEL_DIV1 (0x00<<4) +#define USART1_PLKSEL_DIV2 (0x01<<4) +#define USART1_PLKSEL_DIV4 (0x02<<4) +#define USART1_PLKSEL_DIV8 (0x03<<4) +#define USART1_PLKSEL_DIV16 (0x04<<4) +/**************Line Control Define******/ +#define USART_CHARACTER_LEN5BIT (0x00) +#define USART_CHARACTER_LEN6BIT (0x01) +#define USART_CHARACTER_LEN7BIT (0x02) +#define USART_CHARACTER_LEN8BIT (0x03) +/***********************/ +#define USART_STOPBIT_1BIT (0x0<<2) +#define USART_STOPBIT_2BIT (0x1<<2) +/***********************/ +#define USART_PARITY_BIT_DISEN (0x0<<3) +#define USART_PARITY_BIT_EN (0x1<<3) +/***********************/ +#define USART_PARITY_SELECTODD (0x00<<4) +#define USART_PARITY_SELECTEVEN (0x01<<4) +#define USART_PARITY_SELECTFORC1 (0x02<<4) +#define USART_PARITY_SELECTFORC0 (0x03<<4) +/***********************/ +#define USART_BREAK_DISEN (0x0<<6) +#define USART_BREAK_EN (0x1<<6) +/***********************/ +#define USART_DIVISOR_DISEN (0x0<<7) +#define USART_DIVISOR_EN (0x1<<7) + +#define USART_OVER_SAMPLE_16 (0x0<<8) +#define USART_OVER_SAMPLE_8 (0x1<<8) +/***Baud rate pre-scaler multilier = MULVAL+1***/ +#define USART_MULVAL_0 (0x0000<<4) +#define USART_MULVAL_1 (0x0001<<4) +#define USART_MULVAL_2 (0x0002<<4) +#define USART_MULVAL_3 (0x0003<<4) +#define USART_MULVAL_4 (0x0004<<4) +#define USART_MULVAL_5 (0x0005<<4) +#define USART_MULVAL_6 (0x0006<<4) +#define USART_MULVAL_7 (0x0007<<4) +#define USART_MULVAL_8 (0x0008<<4) +#define USART_MULVAL_9 (0x0009<<4) +#define USART_MULVAL_10 (0x000A<<4) +#define USART_MULVAL_11 (0x000B<<4) +#define USART_MULVAL_12 (0x000C<<4) +#define USART_MULVAL_13 (0x000D<<4) +#define USART_MULVAL_14 (0x000E<<4) +#define USART_MULVAL_15 (0x000F<<4) +/***Buad rate pre-scaler divisor value********/ +#define USART_DIVADDVAL_0 (0x000) +#define USART_DIVADDVAL_1 (0x001) +#define USART_DIVADDVAL_2 (0x002) +#define USART_DIVADDVAL_3 (0x003) +#define USART_DIVADDVAL_4 (0x004) +#define USART_DIVADDVAL_5 (0x005) +#define USART_DIVADDVAL_6 (0x006) +#define USART_DIVADDVAL_7 (0x007) +#define USART_DIVADDVAL_8 (0x008) +#define USART_DIVADDVAL_9 (0x009) +#define USART_DIVADDVAL_10 (0x00A) +#define USART_DIVADDVAL_11 (0x00B) +#define USART_DIVADDVAL_12 (0x00C) +#define USART_DIVADDVAL_13 (0x00D) +#define USART_DIVADDVAL_14 (0x00E) +#define USART_DIVADDVAL_15 (0x00F) +/***USART divisor latch MSB reg[7:0]. determines the baud rate***/ + + +/***USART divisor latch LSB reg[7:0]. determines the baud rate***/ + + +#define USART_FIFO_ENABLE (0x01) +#define USART_RXFIFO_RESET (0x01<<1) +#define USART_TXFIFO_RESET (0x01<<2) + +#define USART_RXTRIGGER_LEVEL1 (0x00<<6) +#define USART_RXTRIGGER_LEVEL4 (0x01<<6) +#define USART_RXTRIGGER_LEVEL8 (0x02<<6) +#define USART_RXTRIGGER_LEVEL14 (0x03<<6) + +/***USART Interrupt Enable register***/ +#define USART_TXERRIE_EN (0x01<<10) //Tx error flag INT +#define USART_ABTOIE_EN (0x01<<9) //auto-buad time out INT +#define USART_ABEOIE_EN (0x01<<8) //End of auto-buad INT +#define USART_TEMTIE_EN (0x01<<4) //Transmitter empty flag +#define USART_MSIE_EN (0x01<<3) //Modem status INT +#define USART_RLSIE_EN (0x01<<2) //Rx Receive line status(RLS) INT +#define USART_THREIE_EN (0x01<<1) //Transmitter holding register empty flag INT +#define USART_RDAIE_EN (0x01) //character receive(RDA) time-out INT + +/*** USARTn_CTRL************/ +#define USART_EN (0x01) +#define USART_MODE_UART (0x00<<1) +#define USART_MODE_MODEN (0x01<<1) +#define USART_MODE_SMARTCARD (0x03<<1) +#define USART_MODE_SYNCH (0x04<<1) +#define USART_MODE_RS485 (0x05<<1) +#define USART_RX_EN (0x01<<6) +#define USART_TX_EN (0x01<<7) +#define USART_CTRL_EN 1 +#define USART_CTRL_DIS 0 +#define USART_FIFOCTRL_RESET 1 + +/*** USARTn_ABCCTRL************/ +#define USART_ABCCTRL_START (0x01) //START:1(Auto-baud is running), START:0(Auto-baud is not running) +#define USART_ABCCTRL_MODE0 (0x00<<1) +#define USART_ABCCTRL_MODE1 (0x01<<1) +#define USART_ABCCTRL_RESTART (0x01<<2) +#define USART_ABEO_EN (0x01<<8) +#define USART_ABTO_EN (0x01<<9) + +/*** USARTn_MC(modem contro)************/ +#define USART_MC_RTSCTRL (0x01<<1) //Source for modem output pin RTS +#define USART_MCCTS_EN (0x01<<6) //Auto-CTS 1:enable 0:disable +#define USART_MCRTS_EN (0x01<<7) //Auto-RTS 1:enable 0:disable + +/*** USARTn_RS485(modem contro)************/ +#define USART_NMM_EN (0x01) //Normal Multidrop Mode(NMM) 1:enable 0:disable +#define USART_485RX_EN (0x01<<1) //RS-485 Receiver bit 1:enalbe 0:disable +#define USART_AAD_EN (0x01<<2) //Auto address detect(AAD) bit 1:enable 0:disable +#define USART_ADC_EN (0x01<<4) //Auto Direction control bit 1:enable 0:disable +#define USART_OINV_SEL1 (0x01<<5) +#define USART_OINV_SEL0 (0x00<<5) +#define RS485_ADDRESS 40 +#define RS485_DELAY_TIME 40 + +/*** USARTn_Synchronous Mode(modem contro)************/ +#define USART_SCLK_LOW (0x0<<1) //SCLK idle low +#define USART_SCLK_HIGH (0x1<<1) //SCLK idle high +#define USART_POLAR_RISING (0x0<<2) //sample on Rising edge +#define USART_POLAR_FALLING (0x1<<2) //sample on Falling edge + +/*** Line status register************/ +#define USART_LS_RDR (0x01) //receiver data ready flag +#define USART_LS_OE (0x01<<1) //overrun error flag +#define USART_LS_PE (0x01<<2) //parity error flag +#define USART_LS_FE (0x01<<3) //framing error flag +#define USART_LS_BI (0x01<<4) //break interrupt flag +#define USART_LS_THRE (0x01<<5) //transmitter holding register empty flag +#define USART_LS_TEMT (0x01<<6) //transmitter empty flag +#define USART_LS_RXFE (0x01<<7) //error in RX FIFO flag +#define USART_LS_THERR (0x01<<8) //TX error flag +#define mskUSART_LS_RDR (0x01) +#define mskUSART_LS_OE (0x01<<1) +#define mskUSART_LS_PE (0x01<<2) +#define mskUSART_LS_FE (0x01<<3) +#define mskUSART_LS_BI (0x01<<4) +#define mskUSART_LS_THRE (0x01<<5) +#define mskUSART_LS_TEMT (0x01<<6) +#define mskUSART_LS_RXFE (0x01<<7) +#define mskUSART_LS_TXERR (0x01<<8) + +/*** Line status register************/ +#define USART_MS_DCTS (0x01) +#define USART_MS_CTS (0x01<<4) +#define mskUSART_MS_DCTS (0x01) +#define mskUSART_MS_CTS (0x01<<4) + +/*** Interrupt Identification register************/ +#define USART_RLS 3 +#define USART_RDA 2 +#define USART_CTI 6 +#define USART_THRE 1 +#define USART_MODEM 0 +#define USART_TEMT 7 +#define USART_II_STATUS 0 //the INTstatus can be determined by USARTn_II[3:1] +#define USART_II_ABEOIF (0x01<<8) //end of auto-baud interrupt flag +#define USART_II_ABTOIF (0x01<<9) //auto-baud time-out interrupt flag +#define USART_II_TXERRIF (0x01<<10) //TXERR interrupt flag +#define mskUSART_INTID_STATUS 7 //interrupt corresponding to the USARTn RX FIFO +#define mskUSART_II_STATUS (0x01) +#define mskUSART_II_ABEOIF (0x01<<8) +#define mskUSART_II_ABTOIF (0x01<<9) +#define mskUSART_II_TXERRIF (0x01<<10) + + +/*_____ M A C R O S ________________________________________________________*/ +#define __USART0_RXFIFO_RESET (SN_USART0->FIFOCTRL_b.RXFIFORST = USART_FIFOCTRL_RESET) +#define __USART0_TXFIFO_RESET (SN_USART0->FIFOCTRL_b.TXFIFORST = USART_FIFOCTRL_RESET) +#define __USART1_RXFIFO_RESET (SN_USART1->FIFOCTRL_b.RXFIFORST = USART_FIFOCTRL_RESET) +#define __USART1_TXFIFO_RESET (SN_USART1->FIFOCTRL_b.TXFIFORST = USART_FIFOCTRL_RESET) + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +extern uint32_t GulNum; +extern uint8_t bUSART0_RecvFIFO[16]; +extern uint32_t GulNum1; +extern uint8_t bUSART1_RecvFIFO[16]; +extern volatile uint8_t bUSART0_RecvNew; +extern volatile uint8_t bUSART1_RecvNew; + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +extern void USART0_Init(void); +extern void USART0_SendByte(void); +extern void USART0_Enable(void); +extern void USART0_Disable(void); +extern void USART0_InterruptEnable(void); +extern void USART0_AutoBaudrateInit(void); + +extern void USART1_Init(void); +extern void USART1_SendByte(void); +extern void USART1_Enable(void); +extern void USART1_Disable(void); +extern void USART1_InterruptEnable(void); +extern void USART1_AutoBaudrateInit(void); + +extern void USART0_Modem_Init(void); +extern void USART0_RS485_Init(void); +extern void USART0_SyncMode_Init(void); + + +#endif /*__SN32F240_USART_H*/ + diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USART/USART0.c b/os/hal/ports/SN32/LLD/SN32F24x/USART/USART0.c new file mode 100644 index 00000000..27399c4c --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/USART/USART0.c @@ -0,0 +1,374 @@ +/******************** (C) COPYRIGHT 2015 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2015/05 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: USART0 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 First release +* 1.1 2014/01/20 SA1 1. Modify USART0_SendByte sub function +* 1.2 2014/02/27 SA1 1. Fix typing errors. +* 1.22 2014/05/23 SA1 1. Fix USART0_Init for BR=115200 +* 2.0 2015/05/29 SA1 1. Fix USART0_Init for BR=115200 & 57600 @ PCLK=12MHz +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include "USART.h" +#include "..\..\Utility\Utility.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +volatile uint8_t bUSART0_RecvNew; +uint32_t GulNum; +uint8_t bUSART0_RecvFIFO[16]; + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + +/***************************************************************************** +* Function : UART0_IRQHandler +* Description : USART0 interrupt service routine +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void USART0_IRQHandler (void) +{ + uint32_t II_Buf, LS_Buf, MS_Buf; + volatile uint32_t Null_Buf; + + II_Buf = SN_USART0->II; + while ((II_Buf & mskUSART_II_STATUS) == USART_II_STATUS) //check interrupt status, the INT can be determined by USARTn_II[3:1] + { + switch ((II_Buf>>1) & mskUSART_INTID_STATUS) + { + case USART_RLS: //Receive Line Status + LS_Buf = SN_USART0->LS; + if((LS_Buf & mskUSART_LS_OE) == USART_LS_OE) //Overrun Error + { } + if((LS_Buf & mskUSART_LS_RXFE) == USART_LS_RXFE)//RX FIFO Error + { + if((LS_Buf & mskUSART_LS_PE) == USART_LS_PE)//Parity Error + Null_Buf = SN_USART0->RB; //Clear interrupt + if((LS_Buf & mskUSART_LS_FE) == USART_LS_FE) //Framing Error + Null_Buf = SN_USART0->RB; //Clear interrupt + if((LS_Buf & mskUSART_LS_BI) == USART_LS_BI) //Break Interrupt + Null_Buf = SN_USART0->RB; //Clear interrupt + } + break; + + case USART_RDA: //Receive Data Available + case USART_CTI: //Character Time-out Indicator + LS_Buf = SN_USART0->LS; + bUSART0_RecvNew = 1; + if((LS_Buf & mskUSART_LS_RDR) == USART_LS_RDR)//Receiver Data Ready + { + bUSART0_RecvFIFO[GulNum] = SN_USART0->RB; + GulNum++; + } + if(GulNum == 16) + GulNum = 0; + break; + + case USART_THRE: //THRE interrupt + LS_Buf = SN_USART0->LS; + if((LS_Buf & mskUSART_LS_THRE) == USART_LS_THRE)//THRE empty + { //SN_USART0->TH = Null_Buf; //Clear interrupt + } + break; + + case USART_TEMT: //TEMT interrupt + LS_Buf = SN_USART0->LS; + if((LS_Buf & mskUSART_LS_TEMT) == USART_LS_TEMT) + { //SN_USART0->TH = Null_Buf; //Clear interrupt + } + break; + + case USART_MODEM: //Modem status + MS_Buf = SN_USART0->MS; + if((MS_Buf & mskUSART_MS_DCTS) == USART_MS_DCTS)//Delta CTS + { + if((MS_Buf & mskUSART_MS_CTS) == USART_MS_CTS) + { //Low to High transition + } + else + { //High to Low transition + } + } + break; + default: + break; + } //end switch ((II_Buf>>1) & mskUSART_INTID_STATUS) + + II_Buf = SN_USART0->II; + //LS_Buf = SN_USART0->LS; + } //end while ((II_Buf&0x01) == mskUSART_II_STATUS) + + if ((II_Buf & mskUSART_II_ABEOIF) == USART_II_ABEOIF) //Auto Baud interrupt + SN_USART0->ABCTRL |= USART_ABEO_EN; + else if((II_Buf & mskUSART_II_ABTOIF) == USART_II_ABTOIF) //Auto Baud time-out interrupt + SN_USART0->ABCTRL |= USART_ABTO_EN; + + if((II_Buf & mskUSART_II_TXERRIF) == USART_II_TXERRIF)//TXERR interrupt + { + LS_Buf = SN_USART0->LS; + if ((LS_Buf & mskUSART_LS_TXERR) == USART_LS_THERR)//TX Error + SN_USART0->FIFOCTRL|= USART_TXFIFO_RESET; //TX FIFO Reset + } +} + + +/***************************************************************************** +* Function : USART0_Init +* Description : Initialization of USART0 +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USART0_Init (void) +{ + SN_SYS1->AHBCLKEN |= USART0_CLK_EN; //Enables clock for USART0 + + SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV1; //USART0 PCLK = HCLK/1 = 12MHz + //SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV2; //USART0 PCLK = HCLK/2 = 6MHz + //SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV4; //USART0 PCLK = HCLK/4 = 3MHz + //SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV8; //USART0 PCLK = HCLK/8 = 1.5MHz + //SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV16; //USART0 PCLK = HCLK/16= 0.75MHz + + //===Line Control=== + //setting character Word length(5/6/7/8 bit) + SN_USART0->LC = (USART_CHARACTER_LEN8BIT //8bit character length. + | USART_STOPBIT_1BIT //stop bit of 1 bit + | USART_PARITY_BIT_DISEN //parity bit is disable + | USART_PARITY_SELECTODD //parity bit is odd + | USART_BREAK_DISEN //Break Transmission control disable + | USART_DIVISOR_EN); //Divisor Latch Access enable + + //===Baud Rate Calculation=== + //USART PCLK = 12MHz, Baud rate = 115200 + SN_USART0->FD = (USART_OVER_SAMPLE_16|USART_MULVAL_7|USART_DIVADDVAL_5); + SN_USART0->DLM = 0; + SN_USART0->DLL = 4; + /* + //USART PCLK = 12MHz, Baud rate = 57600 + SN_USART0->FD = (OVER_SAMPLE_16|USART_MULVAL_7|USART_DIVADDVAL_5); + SN_USART0->DLM = 0; + SN_USART0->DLL = 8; + */ + SN_USART0->LC &= ~(USART_DIVISOR_EN); //Disable divisor latch + + //===Auto Baud Rate=== + //USART0_Autobaudrate_Init(); //Auto buad rate initial + + //===FIFO Control=== + SN_USART0->FIFOCTRL =(USART_FIFO_ENABLE //Enable USART FIFOs + | USART_RXFIFO_RESET //RX FIFO Reset + | USART_TXFIFO_RESET //TX FIFO Reset + | USART_RXTRIGGER_LEVEL1); //RX Trigger Level(1/4/8/14 characters) + + //===Modem Control=== + //USART0_Modem_Init(); //Initialization of USART0 Modem. + + //===Smart Card Control=== + //SN_USART0->SCICTRL_b.NACKDIS = 1; //NACK response disable, T=0 only (0:NACK response is enabled, 1:NACK response is inhibited) + //SN_USART0->SCICTRL_b.PROTSEL = 1; //Protocol selection (0:T=0, 1:T=1) + //SN_USART0->SCICTRL_b.SCLKEN = 1; //SCLK out enable (0:Disable, 1:Enable) + //SN_USART0->SCICTRL_b.TXRETRY = 0; //T=0 only, the field controls the maximum number of retransmissions that the USART will attempt if the remote device signal NACK. + //SN_USART0->SCICTRL_b.XTRAGUARD = 0; //T=0 only, this field indicates the Guard time value in terms of number of bit times + //SN_USART0->SCICTRL_b.TC = 0; //TC[7:0] (Count for SCLK clock cycle when SCLKEN=1. SCLK will toggle every (TC[7:0]+1)*USARTn_PCLK cycle) + + //===Synchronous Mode Control=== + //USART0_SyncMode_Init(); //USART0_SyncMode_Init + + //===RS485 Control=== + //USART0_RS485_Init(); //USART0_RS485_Init + + //===Scratch Pad=== + //SN_USART0->SP = 0; //A readable, writable byte + + //===Oversampling=== + //SN_USART0->FD |= USART_OVER_SAMPLE_8; //OVER8(Oversampling Value), 1:Oversampling by 8. 0:Oversampling by 16 + + //===Half-duplex=== + //SN_USART0->HDEN = 1; //Half-duplex mode enable + + //===Interrupt Enable=== + USART0_InterruptEnable(); + + //===USART Control=== + SN_USART0->CTRL =(USART_EN //Enable USART0 + | USART_MODE_UART //USART Mode = USAT + | USART_RX_EN //Enable RX + | USART_TX_EN); //Enable TX + //===NVIC=== + NVIC_EnableIRQ(USART0_IRQn); //Enable USART0 INT + +} + +/***************************************************************************** +* Function : USART0_SendByte +* Description : USART0 Send data +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USART0_SendByte(void) +{ + uint32_t i; + for (i=0; i<8; i++) + { + SN_USART0->TH= ('a'+i); + while ((SN_USART0->LS & 0x40) == 0); + } +} + +/***************************************************************************** +* Function : USART0_AutoBaudrateInit +* Description : Initialization of USART0 Auto baud rate. +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USART0_AutoBaudrateInit(void) +{ + SN_USART0->ABCTRL =(USART_ABTO_EN //Clear Auto Baud Time-out interrupt + | USART_ABEO_EN //Clear Auto Baud interrupt + | USART_ABCCTRL_RESTART //Restart in case of time-out + | USART_ABCCTRL_MODE1 //Auto Baud mode, 0:mode 0, 1:mode 1 + | USART_ABCCTRL_START); //Auto Baud start, 0:stop(not running), 1:start(running) +} + +/***************************************************************************** +* Function : USART0_Modem_Init +* Description : Initialization of USART0 Modem. +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USART0_Modem_Init(void) +{ + SN_USART0->MC =(USART_MC_RTSCTRL //Source for modem output pin RTS + | USART_MCCTS_EN //CTS enable + | USART_MCRTS_EN); //RTS enable +} + +/***************************************************************************** +* Function : USART0_RS485_Init +* Description : Initialization of USART0 RS-485. +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USART0_RS485_Init(void) +{ + SN_USART0->RS485CTRL=(USART_NMM_EN //RS-485 Normal Multidrop Mode enable + | USART_485RX_EN //RS-485 Receiver enable, NMMEN=1 only + | USART_AAD_EN //Auto Address Detect enable + | USART_ADC_EN //Direction control enable + | USART_OINV_SEL1); //Polarity control + SN_USART0->RS485ADRMATCH = RS485_ADDRESS; //the address match value for RS-485mode + SN_USART0->RS485DLYV = RS485_DELAY_TIME; //The direction control (RTS or DTR) delay value,this time is in periods of the baud clock +} + +/***************************************************************************** +* Function : USART0_SyncMode_Init +* Description : Initialization of USART0 Synchronous Mode. +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USART0_SyncMode_Init(void) +{ + SN_USART0->SYNCCTRL=(USART_SCLK_HIGH //SCLK idle high + |USART_POLAR_FALLING); //sample on Falling edge +} + +/***************************************************************************** +* Function : USART0_Smartcard_Init +* Description : Initialization of USART0 Smart Card. +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USART0_Smartcard_Init(void) +{ +} + +/***************************************************************************** +* Function : USART0_Enable +* Description : Enable USART0 +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USART0_Enable(void) +{ + //Enable HCLK for USART0 + SN_SYS1->AHBCLKEN |= USART0_CLK_EN; //Enables clock for USART0 + SN_USART0->CTRL_b.USARTEN = USART_CTRL_EN; //USART enable bit + __USART0_RXFIFO_RESET; + __USART0_TXFIFO_RESET; +} + +/***************************************************************************** +* Function : USART0_Disable +* Description : Disable USART0 +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USART0_Disable(void) +{ + SN_USART0->CTRL_b.USARTEN = USART_CTRL_DIS; //USART disable + //Disable HCLK for USART0 + SN_SYS1->AHBCLKEN &= ~(USART0_CLK_EN); //Disable clock for USART0 +} + +/***************************************************************************** +* Function : USART0_InterruptEnable +* Description : Interrupt Enable +* Input : wTxhfie- TX half empty interrupt enable. 0: Disable, 1: Enable. + wRxhfie- RX half empty interrupt enable. 0: Disable, 1: Enable. + wRxtoie- RX Time-out interrupt enable. 0: Disable, 1: Enable. + wRxovfie- RXOverflow interrupt enable. 0: Disable, 1: Enable. +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USART0_InterruptEnable(void) +{ + SN_USART0->IE =(USART_RDAIE_EN //Enables the Receive Data Available(RDA) interrupt + | USART_THREIE_EN //Enable THRE interrupt + | USART_RLSIE_EN //Enable Receive Line Status(RLS) interrupt + | USART_TEMTIE_EN //Enable TEMT interrupt + | USART_ABEOIE_EN //Enable Auto Baud interrupt + | USART_ABTOIE_EN //Enable Auto Baud time-out interrupt + | USART_TXERRIE_EN);//Enable TXERR interrupt +} + diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USART/USART1.c b/os/hal/ports/SN32/LLD/SN32F24x/USART/USART1.c new file mode 100644 index 00000000..428d37fd --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/USART/USART1.c @@ -0,0 +1,284 @@ +/******************** (C) COPYRIGHT 2015 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2015/05 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: USART1 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 First release +* 1.1 2014/01/20 SA1 1. Modify USART0_SendByte sub function +* 1.2 2014/02/27 SA1 1. Fix typing errors. +* 1.22 2014/05/23 SA1 1. Fix USART1_Init for BR=115200 +* 2.0 2015/05/29 SA1 1. Fix USART1_Init for BR=115200 & 57600 @ PCLK=12MHz +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include "USART.h" +#include "..\..\Utility\Utility.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +volatile uint8_t bUSART1_RecvNew; +uint32_t GulNum1; +uint8_t bUSART1_RecvFIFO[16]; + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + +/***************************************************************************** +* Function : UART1_IRQHandler +* Description : USART1 interrupt service routine +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void USART1_IRQHandler (void) +{ + uint32_t II_Buf, LS_Buf; + volatile uint32_t Null_Buf; + + II_Buf = SN_USART1->II; + while ((II_Buf & mskUSART_II_STATUS) == USART_II_STATUS) //check interrupt status, the INT can be determined by USARTn_II[3:1] + { + switch ((II_Buf>>1) & mskUSART_INTID_STATUS) + { + case USART_RLS: //Receive Line Status + LS_Buf = SN_USART1->LS; + if((LS_Buf & mskUSART_LS_OE) == USART_LS_OE) //Overrun Error + { } + if((LS_Buf & mskUSART_LS_RXFE) == USART_LS_RXFE)//RX FIFO Error + { + if((LS_Buf & mskUSART_LS_PE) == USART_LS_PE)//Parity Error + Null_Buf = SN_USART1->RB; //Clear interrupt + if((LS_Buf & mskUSART_LS_FE) == USART_LS_FE) //Framing Error + Null_Buf = SN_USART1->RB; //Clear interrupt + if((LS_Buf & mskUSART_LS_BI) == USART_LS_BI) //Break Interrupt + Null_Buf = SN_USART1->RB; //Clear interrupt + } + break; + + case USART_RDA: //Receive Data Available + case USART_CTI: //Character Time-out Indicator + LS_Buf = SN_USART1->LS; + bUSART1_RecvNew = 1; + if((LS_Buf & mskUSART_LS_RDR) == USART_LS_RDR)//Receiver Data Ready + { + bUSART1_RecvFIFO[GulNum1] = SN_USART1->RB; + GulNum1++; + } + if(GulNum1 == 16) + GulNum1 = 0; + break; + + case USART_THRE: //THRE interrupt + LS_Buf = SN_USART1->LS; + if((LS_Buf & mskUSART_LS_THRE) == USART_LS_THRE)//THRE empty + { //SN_USART1->TH = Null_Buf; //Clear interrupt + } + break; + + case USART_TEMT: //TEMT interrupt + LS_Buf = SN_USART1->LS; + if((LS_Buf & mskUSART_LS_TEMT) == USART_LS_TEMT) + { //SN_USART1->TH = Null_Buf; //Clear interrupt + } + break; + + default: + break; + } //end switch ((II_Buf>>1) & mskUSART_INTID_STATUS) + + II_Buf = SN_USART1->II; + } //end while ((II_Buf&0x01) == mskUSART_II_STATUS) + + if ((II_Buf & mskUSART_II_ABEOIF) == USART_II_ABEOIF) //Auto Baud interrupt + SN_USART1->ABCTRL |= USART_ABEO_EN; + else if((II_Buf & mskUSART_II_ABTOIF) == USART_II_ABTOIF) //Auto Baud time-out interrupt + SN_USART1->ABCTRL |= USART_ABTO_EN; + + if((II_Buf & mskUSART_II_TXERRIF) == USART_II_TXERRIF)//TXERR interrupt + { + LS_Buf = SN_USART1->LS; + if ((LS_Buf & mskUSART_LS_TXERR) == USART_LS_THERR)//TX Error + SN_USART1->FIFOCTRL|= USART_TXFIFO_RESET; //TX FIFO Reset + } +} + + +/***************************************************************************** +* Function : USART1_Init +* Description : Initialization of USART1 +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USART1_Init (void) +{ + SN_SYS1->AHBCLKEN |= USART1_CLK_EN; //Enables clock for USART0 + + SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV1; //USART0 PCLK = HCLK/1 = 12MHz + //SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV2; //USART0 PCLK = HCLK/2 = 6MHz + //SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV4; //USART0 PCLK = HCLK/4 = 3MHz + //SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV8; //USART0 PCLK = HCLK/8 = 1.5MHz + //SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV16; //USART0 PCLK = HCLK/16= 0.75MHz + + //===Line Control=== + //setting character Word length(5/6/7/8 bit) + SN_USART1->LC = (USART_CHARACTER_LEN8BIT //8bit character length. + | USART_STOPBIT_1BIT //stop bit of 1 bit + | USART_PARITY_BIT_DISEN //parity bit is disable + | USART_PARITY_SELECTODD //parity bit is odd + | USART_BREAK_DISEN //Break Transmission control disable + | USART_DIVISOR_EN); //Divisor Latch Access enable + + //===Baud Rate Calculation=== + //USART PCLK = 12MHz, Baud rate = 115200 + SN_USART1->FD = (USART_OVER_SAMPLE_16|USART_MULVAL_7|USART_DIVADDVAL_5); + SN_USART1->DLM = 0; + SN_USART1->DLL = 4; + /* + //USART PCLK = 12MHz, Baud rate = 57600 + SN_USART1->FD = (OVER_SAMPLE_16|USART_MULVAL_7|USART_DIVADDVAL_5); + SN_USART1->DLM = 0; + SN_USART1->DLL = 8; + */ + SN_USART1->LC &= ~(USART_DIVISOR_EN); //Disable divisor latch + + //===Auto Baud Rate=== + //USART0_Autobaudrate_Init(); //Auto buad rate initial + + //===FIFO Control=== + SN_USART1->FIFOCTRL =(USART_FIFO_ENABLE //Enable USART FIFOs + | USART_RXFIFO_RESET //RX FIFO Reset + | USART_TXFIFO_RESET //TX FIFO Reset + | USART_RXTRIGGER_LEVEL1); //RX Trigger Level(1/4/8/14 characters) + + //===Scratch Pad=== + //SN_USART1->SP = 0; //A readable, writable byte + + //===Oversampling=== + //SN_USART1->FD |= USART_OVER_SAMPLE_8; //OVER8(Oversampling Value), 1:Oversampling by 8. 0:Oversampling by 16 + + //===Half-duplex=== + //SN_USART1->HDEN = 1; //Half-duplex mode enable + + //===Interrupt Enable=== + USART1_InterruptEnable(); + + //===USART Control=== + SN_USART1->CTRL =(USART_EN //Enable USART0 + | USART_MODE_UART //USART Mode = USAT + | USART_RX_EN //Enable RX + | USART_TX_EN); //Enable TX + //===NVIC=== + NVIC_EnableIRQ(USART1_IRQn); //Enable USART1 INT + +} + +/***************************************************************************** +* Function : USART1_SendByte +* Description : USART1 Send data +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USART1_SendByte(void) +{ + uint32_t i; + for (i=0; i<8; i++) + { + SN_USART1->TH= ('a'+i); + while ((SN_USART1->LS & 0x40) == 0); + } +} + +/***************************************************************************** +* Function : USART1_AutoBaudrateInit +* Description : Initialization of USART1 Auto baud rate. +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USART1_AutoBaudrateInit(void) +{ + SN_USART1->ABCTRL =(USART_ABTO_EN //Clear Auto Baud Time-out interrupt + | USART_ABEO_EN //Clear Auto Baud interrupt + | USART_ABCCTRL_RESTART //Restart in case of time-out + | USART_ABCCTRL_MODE1 //Auto Baud mode, 0:mode 0, 1:mode 1 + | USART_ABCCTRL_START); //Auto Baud start, 0:stop(not running), 1:start(running) +} + +/***************************************************************************** +* Function : USART1_Enable +* Description : Enable USART1 +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USART1_Enable(void) +{ + //Enable HCLK for USART1 + SN_SYS1->AHBCLKEN |= USART1_CLK_EN; //Enables clock for USART0 + SN_USART1->CTRL_b.USARTEN = USART_CTRL_EN; //USART enable bit + __USART1_RXFIFO_RESET; + __USART1_TXFIFO_RESET; +} + +/***************************************************************************** +* Function : USART1_Disable +* Description : Disable USART1 +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USART1_Disable(void) +{ + SN_USART1->CTRL_b.USARTEN = USART_CTRL_DIS; //USART disable + //Disable HCLK for USART1 + SN_SYS1->AHBCLKEN &= ~(USART1_CLK_EN); //Disable clock for USART0 +} + +/***************************************************************************** +* Function : USART1_InterruptEnable +* Description : Interrupt Enable +* Input : wTxhfie- TX half empty interrupt enable. 0: Disable, 1: Enable. + wRxhfie- RX half empty interrupt enable. 0: Disable, 1: Enable. + wRxtoie- RX Time-out interrupt enable. 0: Disable, 1: Enable. + wRxovfie- RXOverflow interrupt enable. 0: Disable, 1: Enable. +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USART1_InterruptEnable(void) +{ + SN_USART1->IE =(USART_RDAIE_EN //Enables the Receive Data Available(RDA) interrupt + | USART_THREIE_EN //Enable THRE interrupt + | USART_RLSIE_EN //Enable Receive Line Status(RLS) interrupt + | USART_TEMTIE_EN //Enable TEMT interrupt + | USART_ABEOIE_EN //Enable Auto Baud interrupt + | USART_ABTOIE_EN //Enable Auto Baud time-out interrupt + | USART_TXERRIE_EN);//Enable TXERR interrupt +} + diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USB/driver.mk b/os/hal/ports/SN32/LLD/SN32F24x/USB/driver.mk new file mode 100644 index 00000000..8326191b --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/USB/driver.mk @@ -0,0 +1,5 @@ +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/USB/hal_usb_lld.c +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/USB/usbhw.c +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/USB/usbsystem.c + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/USB diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USB/hal_usb_lld.c b/os/hal/ports/SN32/LLD/SN32F24x/USB/hal_usb_lld.c new file mode 100644 index 00000000..45871911 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/USB/hal_usb_lld.c @@ -0,0 +1,1005 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_usb_lld.c + * @brief PLATFORM USB subsystem low level driver source. + * + * @addtogroup USB + * @{ + */ + +#include +#include +#include "hal.h" +#include "usbhw.h" + +#if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ +#define SN32_USB_IRQ_VECTOR Vector44 +#define SN32_USB_PMA_SIZE 256 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief USB1 driver identifier. + */ +#if (PLATFORM_USB_USE_USB1 == TRUE) || defined(__DOXYGEN__) +USBDriver USBD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static int address; +static uint8_t nakcnt[USB_MAX_ENDPOINTS + 1] = {0, 0, 0, 0, 0, 0, 0}; + +/** + * @brief EP0 state. + * @note It is an union because IN and OUT endpoints are never used at the + * same time for EP0. + */ +static union { + /** + * @brief IN EP0 state. + */ + USBInEndpointState in; + /** + * @brief OUT EP0 state. + */ + USBOutEndpointState out; +} ep0_state; + +/** + * @brief EP0 initialization structure. + */ +static const USBEndpointConfig ep0config = { + USB_ENDPOINT_TYPE_CONTROL, + _usb_ep0setup, + _usb_ep0in, + _usb_ep0out, + 0x40, + 0x40, + &ep0_state.in, + &ep0_state.out +}; +void rgb_matrix_toggle(void); +void handleACK(USBDriver* usbp, usbep_t ep); +void handleNAK(USBDriver* usbp, usbep_t ep); +#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) +#define _usb_isr_invoke_tx_complete_cb(usbp, ep) { \ + (usbp)->transmitting &= ~(1 << (ep)); \ + osalSysLockFromISR(); \ + osalThreadResumeI(&(usbp)->epc[ep]->in_state->thread, MSG_OK); \ + osalSysUnlockFromISR(); \ +} +#else +#define _usb_isr_invoke_tx_complete_cb(usbp, ep) { \ + (usbp)->transmitting &= ~(1 << (ep)); \ +} +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void sn32_usb_read_fifo(usbep_t ep, uint8_t *buf, size_t sz, bool intr) { + uint32_t *pRAM = &USB_SRAM_EP0_W0; + + if (ep == 0) { + memcpy(buf, pRAM, sz); + } else { + memcpy(buf, (void *)wUSB_EPnOffset[ep - 1], sz); + } +} + +static void sn32_usb_write_fifo(usbep_t ep, const uint8_t *buf, size_t sz, bool intr) { + uint32_t *pRAM = &USB_SRAM_EP0_W0; + + if (ep == 0) { + memcpy(pRAM, buf, sz); + } else { + memcpy((void *)wUSB_EPnOffset[ep - 1], buf, sz); + } +} + +void rgb_matrix_disable_noeeprom(void); +/** + * @brief USB shared ISR. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +static void usb_lld_serve_interrupt(USBDriver *usbp) +{ + uint32_t iwIntFlag; + size_t n; + + //** Get Interrupt Status and clear immediately. + iwIntFlag = SN_USB->INSTS; + //Clear flags right away for interrupts that we dont handle, keep other untill fully handled + SN_USB->INSTSC = 0x0007C0C0; + + if(iwIntFlag == 0) + { + //@20160902 add for EMC protection + return; + } + + if (iwIntFlag & mskBUS_WAKEUP) + { /* Wakeup */ + USB_WakeupEvent(); + _usb_wakeup(usbp); + return; + } + + ///////////////////////////////////////////////// + /* Device Status Interrupt (BusReset, Suspend) */ + ///////////////////////////////////////////////// + if (iwIntFlag & (mskBUS_RESET | mskBUS_SUSPEND | mskBUS_RESUME)) + { + if (iwIntFlag & mskBUS_RESET) + { + /* BusReset */ + USB_ResetEvent(); + _usb_reset(usbp); + } + else if (iwIntFlag & mskBUS_SUSPEND) + { + /* Suspend */ + __USB_CLRINSTS(mskBUS_SUSPEND); + _usb_suspend(usbp); + } + else if(iwIntFlag & mskBUS_RESUME) + { + /* Resume */ + __USB_CLRINSTS(mskBUS_RESUME); + _usb_wakeup(usbp); + } + } + ///////////////////////////////////////////////// + /* Device Status Interrupt (SETUP, IN, OUT) */ + ///////////////////////////////////////////////// + else if (iwIntFlag & (mskEP0_SETUP|mskEP0_IN|mskEP0_OUT|mskEP0_IN_STALL|mskEP0_OUT_STALL)) + { + const USBEndpointConfig *epcp = usbp->epc[0]; + + if (iwIntFlag & mskEP0_SETUP) + { + /* SETUP */ + //** keep EP0 NAK + //USB_EPnNak(USB_EP0); //useless + + //not sure we need it here... + //TODO: clean it up when packets are properly handled + epcp->in_state->txcnt = 0; + epcp->in_state->txsize = 0; + epcp->in_state->txlast = 0; + epcp->out_state->rxcnt = 0; + epcp->out_state->rxsize = 0; + epcp->out_state->rxpkts = 0; + + _usb_isr_invoke_setup_cb(usbp, 0); + __USB_CLRINSTS((mskEP0_SETUP|mskEP0_PRESETUP|mskEP0_OUT_STALL|mskEP0_IN_STALL)); + } + else if (iwIntFlag & mskEP0_IN) + { + USBInEndpointState *isp = epcp->in_state; + + /* IN */ + + // The address + if (address) { + SN_USB->ADDR = address; + address = 0; + USB_EPnStall(USB_EP0); + } + +// USB_EPnAck(USB_EP0,0); + + isp->txcnt += isp->txlast; + n = isp->txsize - isp->txcnt; + if (n > 0) { + /* Transfer not completed, there are more packets to send.*/ + if (n > epcp->in_maxsize) + n = epcp->in_maxsize; + + /* Writes the packet from the defined buffer.*/ + isp->txbuf += isp->txlast; + isp->txlast = n; + + sn32_usb_write_fifo(0, isp->txbuf, n, true); + + USB_EPnAck(USB_EP0, n); + } + else + { + //USB_EPnNak(USB_EP0); //not needed + + _usb_isr_invoke_in_cb(usbp, 0); + } + __USB_CLRINSTS(mskEP0_IN); + + } + else if (iwIntFlag & mskEP0_OUT) + { + USBOutEndpointState *osp = epcp->out_state; + /* OUT */ + + n = SN_USB->EP0CTL & mskEPn_CNT; + if (n > epcp->out_maxsize) + n = epcp->out_maxsize; + + //Just being paranoid here. keep here while debugging EP handling issue + //TODO: clean it up when packets are properly handled + if (epcp->out_state->rxsize >= n) { + //we are ok to copy n bytes to buf + sn32_usb_read_fifo(USB_EP0, osp->rxbuf, n, true); + epcp->out_state->rxsize -= n; + } + else if (epcp->out_state->rxsize > 0) { + //we dont have enough buffer to receive n bytes + //copy only size availabe on buffer + n = epcp->out_state->rxsize; + sn32_usb_read_fifo(USB_EP0, osp->rxbuf, n, true); + epcp->out_state->rxsize -= n; + } + else { + //well buffer is 0 size. strange. do nothing. + n = 0; + } + + epcp->out_state->rxbuf += n; + epcp->out_state->rxcnt += n; + if (epcp->out_state->rxpkts > 0) { + epcp->out_state->rxpkts -= 1; + } + + if (n < epcp->out_maxsize || epcp->out_state->rxpkts == 0) + { + //done with transfer + //USB_EPnNak(USB_EP0); //useless mcu resets it anyways + _usb_isr_invoke_out_cb(usbp, 0); + } + else { + //more to receive + USB_EPnAck(USB_EP0, 0); + } + __USB_CLRINSTS(mskEP0_OUT); + + } + else if (iwIntFlag & (mskEP0_IN_STALL|mskEP0_OUT_STALL)) + { + /* EP0_IN_OUT_STALL */ + USB_EPnStall(USB_EP0); + SN_USB->INSTSC = (mskEP0_IN_STALL|mskEP0_OUT_STALL); + } + } + ///////////////////////////////////////////////// + /* Device Status Interrupt (EPnACK) */ + ///////////////////////////////////////////////// + else if (iwIntFlag & (mskEP6_ACK|mskEP5_ACK|mskEP4_ACK|mskEP3_ACK|mskEP2_ACK|mskEP1_ACK)) + { + // Determine the interrupting endpoint, direction, and clear the interrupt flag + if(iwIntFlag & mskEP1_ACK) + { + handleACK(usbp, USB_EP1); + __USB_CLRINSTS(mskEP1_ACK); + } + if(iwIntFlag & mskEP2_ACK) + { + handleACK(usbp, USB_EP2); + __USB_CLRINSTS(mskEP2_ACK); + } + if(iwIntFlag & mskEP3_ACK) + { + handleACK(usbp, USB_EP3); + __USB_CLRINSTS(mskEP3_ACK); + } + if(iwIntFlag & mskEP4_ACK) + { + handleACK(usbp, USB_EP4); + __USB_CLRINSTS(mskEP4_ACK); + } + if(iwIntFlag & mskEP5_ACK) + { + handleACK(usbp, USB_EP5); + __USB_CLRINSTS(mskEP5_ACK); + } + if(iwIntFlag & mskEP6_ACK) + { + handleACK(usbp, USB_EP6); + __USB_CLRINSTS(mskEP6_ACK); + } + } + else if (iwIntFlag & (mskEP6_NAK|mskEP5_NAK|mskEP4_NAK|mskEP3_NAK|mskEP2_NAK|mskEP1_NAK)) + { + // Determine the interrupting endpoint, direction, and clear the interrupt flag + if (iwIntFlag & mskEP1_NAK) + { + handleNAK(usbp, USB_EP1); + __USB_CLRINSTS(mskEP1_NAK); + } + if (iwIntFlag & mskEP2_NAK) + { + handleNAK(usbp, USB_EP2); + __USB_CLRINSTS(mskEP2_NAK); + } + if (iwIntFlag & mskEP3_NAK) + { + handleNAK(usbp, USB_EP3); + __USB_CLRINSTS(mskEP3_NAK); + } + if (iwIntFlag & mskEP4_NAK) + { + handleNAK(usbp, USB_EP4); + __USB_CLRINSTS(mskEP4_NAK); + } + if (iwIntFlag & mskEP5_NAK) + { + handleNAK(usbp, USB_EP5); + __USB_CLRINSTS(mskEP5_NAK); + } + if (iwIntFlag & mskEP6_NAK) + { + handleNAK(usbp, USB_EP6); + __USB_CLRINSTS(mskEP6_NAK); + } + } + + ///////////////////////////////////////////////// + /* Device Status Interrupt (SOF) */ + ///////////////////////////////////////////////// + if ((iwIntFlag & mskUSB_SOF) && (SN_USB->INTEN & mskUSB_SOF_IE)) + { + /* SOF */ + _usb_isr_invoke_sof_cb(usbp); + __USB_CLRINSTS(mskUSB_SOF); + } +} + +void handleACK(USBDriver* usbp, usbep_t ep) { + uint8_t out = 0; + uint8_t cnt = 0; + size_t n; + + if(ep == USB_EP1) + { + out = ( SN_USB->CFG & mskEP1_DIR ) == mskEP1_DIR; + cnt = SN_USB->EP1CTL & mskEPn_CNT; + } + else if(ep == USB_EP2) + { + out = ( SN_USB->CFG & mskEP2_DIR ) == mskEP2_DIR; + cnt = SN_USB->EP2CTL & mskEPn_CNT; + } + else if(ep == USB_EP3) + { + out = ( SN_USB->CFG & mskEP3_DIR ) == mskEP3_DIR; + cnt = SN_USB->EP3CTL & mskEPn_CNT; + } + else if(ep == USB_EP4) + { + out = ( SN_USB->CFG & mskEP4_DIR ) == mskEP4_DIR; + cnt = SN_USB->EP4CTL & mskEPn_CNT; + } + else if(ep == USB_EP5) + { + out = ( SN_USB->CFG & mskEP5_DIR ) == mskEP5_DIR; + cnt = SN_USB->EP5CTL & mskEPn_CNT; + } + else if(ep == USB_EP6) + { + out = ( SN_USB->CFG & mskEP6_DIR ) == mskEP6_DIR; + cnt = SN_USB->EP6CTL & mskEPn_CNT; + } + else { + return; + } + nakcnt[ep] = 0; + + // Get the endpoint config and state + const USBEndpointConfig *epcp = usbp->epc[ep]; + USBInEndpointState *isp = epcp->in_state; + USBOutEndpointState *osp = epcp->out_state; + + // Process based on endpoint direction + if(out) + { + // Read size of received data + n = cnt; + + if (n > epcp->out_maxsize) + n = epcp->out_maxsize; + + //state is NAK already + //Just being paranoid here. keep here while debugging EP handling issue + //TODO: clean it up when packets are properly handled + if (epcp->out_state->rxsize >= n) { + //we are ok to copy n bytes to buf + sn32_usb_read_fifo(ep, osp->rxbuf, n, true); + epcp->out_state->rxsize -= n; + } + else if (epcp->out_state->rxsize > 0) { + //we dont have enough buffer to receive n bytes + //copy only size availabe on buffer + n = epcp->out_state->rxsize; + sn32_usb_read_fifo(ep, osp->rxbuf, n, true); + epcp->out_state->rxsize -= n; + } + else { + //well buffer is 0 size. strange. do nothing. + n = 0; + } + osp->rxbuf += n; + + epcp->out_state->rxcnt += n; + if (epcp->out_state->rxpkts > 0) { + epcp->out_state->rxpkts -= 1; + } + + if (n < epcp->out_maxsize || epcp->out_state->rxpkts == 0) + { + _usb_isr_invoke_out_cb(usbp, ep); + } + else + { + //not done. keep on receiving + USB_EPnAck(ep, 0); + } + } + else + { + // Process transmit queue + isp->txcnt += isp->txlast; + n = isp->txsize - isp->txcnt; + + if (n > 0) + { + /* Transfer not completed, there are more packets to send.*/ + if (n > epcp->in_maxsize) + { + n = epcp->in_maxsize; + } + + /* Writes the packet from the defined buffer.*/ + isp->txbuf += isp->txlast; + isp->txlast = n; + + sn32_usb_write_fifo(ep, isp->txbuf, n, true); + + USB_EPnAck(ep, n); + } + else + { + //USB_EPnNak(ep); //not needed here it is autoreset to NAK already + + _usb_isr_invoke_in_cb(usbp, ep); + } + } +} + +void handleNAK(USBDriver *usbp, usbep_t ep) { + uint8_t out = 0; + //handle it properly + if (ep == USB_EP1) { + out = ( SN_USB->CFG & mskEP1_DIR ) == mskEP1_DIR; + } + else if (ep == USB_EP2) { + out = ( SN_USB->CFG & mskEP2_DIR ) == mskEP2_DIR; + } + else if (ep == USB_EP3) { + out = ( SN_USB->CFG & mskEP3_DIR ) == mskEP3_DIR; + } + else if (ep == USB_EP4) { + out = ( SN_USB->CFG & mskEP4_DIR ) == mskEP4_DIR; + } + else if (ep == USB_EP5) { + out = ( SN_USB->CFG & mskEP5_DIR ) == mskEP5_DIR; + } + else if (ep == USB_EP6) { + out = ( SN_USB->CFG & mskEP6_DIR ) == mskEP6_DIR; + } + else { + return; + } + + + if(out) + { + // By acking next OUT token from host we are allowing reception + // of the data from host + USB_EPnAck(ep, 0); + } + else + { + // This is not a retransmission, retransmission is transparent and happens on phy layer + // NAK happens when host polls IN EP and device has nothing to send + // It has been observed that sometimes USB phy doesn't generate ACK (unknown why) + // (count ACK interrupts didn't match count of usb_lld_start_in calls per EP) + // However while USB transmitting and qmk thread wants to send another packet qmk goes to + // infinite sleep, expecting that successfull USB transmission will wake it up + // If USB transmission never completes (no ACK) then qmk never wakes up and keyboard locks up + // To prevent this every NAK (1ms or 8ms depending on host poll interval) was calling + // callbacks and wake up function to wake up qmk thread, however packet was not delivered to host + // (for unknown reason) and thus we have seen: + // 1) stuck keypresses when usb packets to press key delivered but key release packet lost + // 2) untyped key when usb packet to press key was lost but key release packet delivered + // Because callback was called every NAK some qmk features didnt work such as CONSOLE + // since callback might release buffers and endup in deadlock via disabled interrupts + // callback for keyboard is empty thus its repated calling is harmless + #if defined(SN32_USB_ORIGINAL_NAK_HANDLING) + _usb_isr_invoke_in_cb(usbp, ep); + #else + //To fake missing ACK we can send 0 sized packet + //however (again for unknown reason) packets now being delivered to host as well! + //- value 2 has been selected to allow at least 2 NAK delivery (2ms or 16ms depending on + //host polling interval) between moment qmk called start_in and moment USB phy actually + //started transmission + //- value 10 was selected arbitrary. + //- values 3-10 we are delivering 0 sized packet trying to get at least one ack + if (nakcnt[ep] > 0) { + //qmk called start_in + if (nakcnt[ep] > 10) { + //11-.... + //consider packet undeliverable but ack it to the qmk + nakcnt[ep] = 0; + _usb_isr_invoke_in_cb(usbp, ep); + } + else if (nakcnt[ep] > 2) { + //3-10 + nakcnt[ep]++; + USB_EPnAck(ep, 0); + } + else { + //1-2 + //give it sometime to deliver the packet + nakcnt[ep]++; + } + } + #endif + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers and threads. */ +/*===========================================================================*/ + +/** + * @brief SN32 USB Interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(SN32_USB_IRQ_VECTOR) { + + OSAL_IRQ_PROLOGUE(); + usb_lld_serve_interrupt(&USBD1); + OSAL_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level USB driver initialization. + * + * @notapi + */ +void usb_lld_init(void) { + + #if PLATFORM_USB_USE_USB1 == TRUE + /* Driver initialization.*/ + usbObjectInit(&USBD1); + #endif +} + +/** + * @brief Configures and activates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_start(USBDriver *usbp) { + + if (usbp->state == USB_STOP) { + /* Enables the peripheral.*/ + #if PLATFORM_USB_USE_USB1 == TRUE + if (&USBD1 == usbp) { + USB_Init(); + nvicEnableVector(USB_IRQn, 14); + } + #endif + } + /* Configures the peripheral.*/ +} + +/** + * @brief Deactivates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_stop(USBDriver *usbp) { + if (usbp->state == USB_READY) { + /* Resets the peripheral.*/ + + /* Disables the peripheral.*/ + #if PLATFORM_USB_USE_USB1 == TRUE + if (&USBD1 == usbp) { + } + #endif + } +} + +/** + * @brief USB low level reset routine. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_reset(USBDriver *usbp) { + /* Post reset initialization.*/ + + /* EP0 initialization.*/ + usbp->epc[0] = &ep0config; + usb_lld_init_endpoint(usbp, 0); +} + +/** + * @brief Sets the USB address. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_set_address(USBDriver *usbp) { + // It seems the address must be set after an endpoint interrupt, so store it for now. + // It will be written to SN_USB->ADDR in the EP0 IN interrupt + address = usbp->address; +} + +/** + * @brief Enables an endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { + const USBEndpointConfig *epcp = usbp->epc[ep]; + + /* Set the endpoint type. */ + switch (epcp->ep_mode & USB_EP_MODE_TYPE) { + case USB_EP_MODE_TYPE_ISOC: + break; + case USB_EP_MODE_TYPE_BULK: + break; + case USB_EP_MODE_TYPE_INTR: + break; + default: + break; + } + + /* IN endpoint? */ + if (epcp->in_state != NULL) { + // Set endpoint direction flag in USB configuration register + switch (ep) + { + case 1: + SN_USB->CFG &= ~mskEP1_DIR; + break; + case 2: + SN_USB->CFG &= ~mskEP2_DIR; + break; + case 3: + SN_USB->CFG &= ~mskEP3_DIR; + break; + case 4: + SN_USB->CFG &= ~mskEP4_DIR; + break; + case 5: + SN_USB->CFG &= ~mskEP5_DIR; + break; + case 6: + SN_USB->CFG &= ~mskEP6_DIR; + break; + } + } + + /* OUT endpoint? */ + if (epcp->out_state != NULL) { + // Set endpoint direction flag in USB configuration register + // Also enable ACK state + switch (ep) + { + case 1: + SN_USB->CFG |= mskEP1_DIR; + break; + case 2: + SN_USB->CFG |= mskEP2_DIR; + break; + case 3: + SN_USB->CFG |= mskEP3_DIR; + break; + case 4: + SN_USB->CFG |= mskEP4_DIR; + break; + case 5: + SN_USB->CFG |= mskEP5_DIR; + break; + case 6: + SN_USB->CFG |= mskEP6_DIR; + break; + } + } + + /* Enable endpoint. */ + switch(ep) + { + case 1: + SN_USB->EP1CTL |= mskEPn_ENDP_EN; + break; + case 2: + SN_USB->EP2CTL |= mskEPn_ENDP_EN; + break; + case 3: + SN_USB->EP3CTL |= mskEPn_ENDP_EN; + break; + case 4: + SN_USB->EP4CTL |= mskEPn_ENDP_EN; + break; + case 5: + SN_USB->EP5CTL |= mskEPn_ENDP_EN; + break; + case 6: + SN_USB->EP6CTL |= mskEPn_ENDP_EN; + break; + } +} + +/** + * @brief Disables all the active endpoints except the endpoint zero. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_disable_endpoints(USBDriver *usbp) { + unsigned i; + + /* Disabling all endpoints.*/ + for (i = 1; i <= USB_MAX_ENDPOINTS; i++) { + USB_EPnDisable(i); + } +} + +/** + * @brief Returns the status of an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) { + if (ep > USB_MAX_ENDPOINTS) + return EP_STATUS_DISABLED; + if (!USB_EPnEnabled(ep)) + return EP_STATUS_DISABLED; + if (USB_EPnStalled(ep)) + return EP_STATUS_STALLED; + return EP_STATUS_ACTIVE; +/* + if (SN_USB->INSTS & mskEP0_OUT) { + return EP_STATUS_DISABLED; + } else if (SN_USB->INSTS & mskEP0_OUT_STALL) { + return EP_STATUS_STALLED; + } else { + return EP_STATUS_ACTIVE; + } +*/ +} + +/** + * @brief Returns the status of an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) { + if (ep > USB_MAX_ENDPOINTS) + return EP_STATUS_DISABLED; + if (!USB_EPnEnabled(ep)) + return EP_STATUS_DISABLED; + if (USB_EPnStalled(ep)) + return EP_STATUS_STALLED; + return EP_STATUS_ACTIVE; +/* + if (SN_USB->INSTS & mskEP0_IN) { + return EP_STATUS_DISABLED; + } else if (SN_USB->INSTS & mskEP0_IN_STALL) { + return EP_STATUS_STALLED; + } else { + return EP_STATUS_ACTIVE; + } +*/ +} + +/** + * @brief Reads a setup packet from the dedicated packet buffer. + * @details This function must be invoked in the context of the @p setup_cb + * callback in order to read the received setup packet. + * @pre In order to use this function the endpoint must have been + * initialized as a control endpoint. + * @post The endpoint is ready to accept another packet. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the packet data + * + * @notapi + */ + +void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { + + sn32_usb_read_fifo(ep, buf, 8, false); +} + +/** + * @brief Starts a receive operation on an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { + + USBOutEndpointState *osp = usbp->epc[ep]->out_state; + + /* Transfer initialization.*/ + if (osp->rxsize == 0) /* Special case for zero sized packets.*/ + osp->rxpkts = 1; + else + osp->rxpkts = (uint16_t)((osp->rxsize + usbp->epc[ep]->out_maxsize - 1) / + usbp->epc[ep]->out_maxsize); + osp->rxcnt = 0;//haven't received anything yet + USB_EPnAck(ep, 0); +} + +/** + * @brief Starts a transmit operation on an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_start_in(USBDriver *usbp, usbep_t ep) +{ + size_t n; + USBInEndpointState *isp = usbp->epc[ep]->in_state; + + /* Transfer initialization.*/ + //who handles 0 packet ack on setup? + n = isp->txsize; + + if((n >= 0) || (ep == 0)) + { + if (n > (size_t)usbp->epc[ep]->in_maxsize) + n = (size_t)usbp->epc[ep]->in_maxsize; + + isp->txlast = n; + + sn32_usb_write_fifo(ep, isp->txbuf, n, false); + + nakcnt[ep] = 1; + USB_EPnAck(ep, n); + } + else + { + _usb_isr_invoke_in_cb(usbp, ep); + } + +} + +/** + * @brief Brings an OUT endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) { + + USB_EPnStall(ep); + +} + +/** + * @brief Brings an IN endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) { + + USB_EPnStall(ep); + +} + +/** + * @brief Brings an OUT endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) { + if (ep > USB_MAX_ENDPOINTS) + return; + USB_EPnNak(ep); + //__USB_CLRINSTS(mskEP0_OUT); +} + +/** + * @brief Brings an IN endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) { + if (ep > USB_MAX_ENDPOINTS) + return; + USB_EPnNak(ep); + //__USB_CLRINSTS(mskEP0_IN); +} + +#endif /* HAL_USE_USB == TRUE */ + +/** @} */ \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USB/hal_usb_lld.h b/os/hal/ports/SN32/LLD/SN32F24x/USB/hal_usb_lld.h new file mode 100644 index 00000000..72ea3ee4 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/USB/hal_usb_lld.h @@ -0,0 +1,425 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_usb_lld.h + * @brief PLATFORM USB subsystem low level driver header. + * + * @addtogroup USB + * @{ + */ + +#ifndef HAL_USB_LLD_H +#define HAL_USB_LLD_H + +#if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__) + +#include "sn32_usb.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Status stage handling method. + */ +#define USB_EP0_STATUS_STAGE USB_EP0_STATUS_STAGE_SW + +/** + * @brief The address can be changed immediately upon packet reception. + */ +#define USB_SET_ADDRESS_MODE USB_EARLY_SET_ADDRESS // FixMe: USB_LATE_SET_ADDRESS ? + +/** + * @brief Method for set address acknowledge. + */ +#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_SW + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ +/** + * @brief USB driver enable switch. + * @details If set to @p TRUE the support for USB1 is included. + * @note The default is @p FALSE. + */ +#if !defined(PLATFORM_USB_USE_USB1) || defined(__DOXYGEN__) +#define PLATFORM_USB_USE_USB1 TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an IN endpoint state structure. + */ +typedef struct { + /** + * @brief Requested transmit transfer size. + */ + size_t txsize; + /** + * @brief Transmitted bytes so far. + */ + size_t txcnt; + /** + * @brief Pointer to the transmission linear buffer. + */ + const uint8_t *txbuf; +#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + thread_reference_t thread; +#endif + /* End of the mandatory fields.*/ + /** + * @brief Size of the last transmitted packet. + */ + size_t txlast; +} USBInEndpointState; + +/** + * @brief Type of an OUT endpoint state structure. + */ +typedef struct { + /** + * @brief Requested receive transfer size. + */ + size_t rxsize; + /** + * @brief Received bytes so far. + */ + size_t rxcnt; + /** + * @brief Pointer to the receive linear buffer. + */ + uint8_t *rxbuf; +#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + thread_reference_t thread; +#endif + /* End of the mandatory fields.*/ + /** + * @brief Number of packets to receive. + */ + uint16_t rxpkts; +} USBOutEndpointState; + +/** + * @brief Type of an USB endpoint configuration structure. + * @note Platform specific restrictions may apply to endpoints. + */ +typedef struct { + /** + * @brief Type and mode of the endpoint. + */ + uint32_t ep_mode; + /** + * @brief Setup packet notification callback. + * @details This callback is invoked when a setup packet has been + * received. + * @post The application must immediately call @p usbReadPacket() in + * order to access the received packet. + * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL + * endpoints, it should be set to @p NULL for other endpoint + * types. + */ + usbepcallback_t setup_cb; + /** + * @brief IN endpoint notification callback. + * @details This field must be set to @p NULL if the IN endpoint is not + * used. + */ + usbepcallback_t in_cb; + /** + * @brief OUT endpoint notification callback. + * @details This field must be set to @p NULL if the OUT endpoint is not + * used. + */ + usbepcallback_t out_cb; + /** + * @brief IN endpoint maximum packet size. + * @details This field must be set to zero if the IN endpoint is not + * used. + */ + uint16_t in_maxsize; + /** + * @brief OUT endpoint maximum packet size. + * @details This field must be set to zero if the OUT endpoint is not + * used. + */ + uint16_t out_maxsize; + /** + * @brief @p USBEndpointState associated to the IN endpoint. + * @details This structure maintains the state of the IN endpoint. + */ + USBInEndpointState *in_state; + /** + * @brief @p USBEndpointState associated to the OUT endpoint. + * @details This structure maintains the state of the OUT endpoint. + */ + USBOutEndpointState *out_state; + /* End of the mandatory fields.*/ + /* End of the mandatory fields.*/ + /** + * @brief Reserved field, not currently used. + * @note Initialize this field to 1 in order to be forward compatible. + */ + uint16_t ep_buffers; + /** + * @brief Pointer to a buffer for setup packets. + * @details Setup packets require a dedicated 8-bytes buffer, set this + * field to @p NULL for non-control endpoints. + */ + uint8_t *setup_buf; +} USBEndpointConfig; + +/** + * @brief Type of an USB driver configuration structure. + */ +typedef struct { + /** + * @brief USB events callback. + * @details This callback is invoked when an USB driver event is registered. + */ + usbeventcb_t event_cb; + /** + * @brief Device GET_DESCRIPTOR request callback. + * @note This callback is mandatory and cannot be set to @p NULL. + */ + usbgetdescriptor_t get_descriptor_cb; + /** + * @brief Requests hook callback. + * @details This hook allows to be notified of standard requests or to + * handle non standard requests. + */ + usbreqhandler_t requests_hook_cb; + /** + * @brief Start Of Frame callback. + */ + usbcallback_t sof_cb; + /* End of the mandatory fields.*/ +} USBConfig; + +/** + * @brief Structure representing an USB driver. + */ +struct USBDriver { + /** + * @brief Driver state. + */ + usbstate_t state; + /** + * @brief Current configuration data. + */ + const USBConfig *config; + /** + * @brief Bit map of the transmitting IN endpoints. + */ + uint16_t transmitting; + /** + * @brief Bit map of the receiving OUT endpoints. + */ + uint16_t receiving; + /** + * @brief Active endpoints configurations. + */ + const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1]; + /** + * @brief Fields available to user, it can be used to associate an + * application-defined handler to an IN endpoint. + * @note The base index is one, the endpoint zero does not have a + * reserved element in this array. + */ + void *in_params[USB_MAX_ENDPOINTS]; + /** + * @brief Fields available to user, it can be used to associate an + * application-defined handler to an OUT endpoint. + * @note The base index is one, the endpoint zero does not have a + * reserved element in this array. + */ + void *out_params[USB_MAX_ENDPOINTS]; + /** + * @brief Endpoint 0 state. + */ + usbep0state_t ep0state; + /** + * @brief Next position in the buffer to be transferred through endpoint 0. + */ + uint8_t *ep0next; + /** + * @brief Number of bytes yet to be transferred through endpoint 0. + */ + size_t ep0n; + /** + * @brief Endpoint 0 end transaction callback. + */ + usbcallback_t ep0endcb; + /** + * @brief Setup packet buffer. + */ + uint8_t setup[8]; + /** + * @brief Current USB device status. + */ + uint16_t status; + /** + * @brief Assigned USB address. + */ + uint8_t address; + /** + * @brief Current USB device configuration. + */ + uint8_t configuration; + /** + * @brief State of the driver when a suspend happened. + */ + usbstate_t saved_state; +#if defined(USB_DRIVER_EXT_FIELDS) + USB_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the next address in the packet memory. + */ + uint32_t pmnext; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the current frame number. + * + * @param[in] usbp pointer to the @p USBDriver object + * @return The current frame number. + * + * @notapi + */ +#define usb_lld_get_frame_number(usbp) 0 + +/** + * @brief Returns the exact size of a receive transaction. + * @details The received size can be different from the size specified in + * @p usbStartReceiveI() because the last packet could have a size + * different from the expected one. + * @pre The OUT endpoint must have been configured in transaction mode + * in order to use this function. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return Received data size. + * + * @notapi + */ +#define usb_lld_get_transaction_size(usbp, ep) \ + ((usbp)->epc[ep]->out_state->rxcnt) + +/** + * @brief Connects the USB device. + * + * @api + */ +#define usb_lld_connect_bus(usbp) + +/** + * @brief Disconnect the USB device. + * + * @api + */ +#define usb_lld_disconnect_bus(usbp) + +/** + * @brief Start of host wake-up procedure. + * + * @notapi + */ +#define usb_lld_wakeup_host(usbp) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* Descriptor related */ +/* bmAttributes in Endpoint Descriptor */ +#define USB_ENDPOINT_TYPE_MASK 0x03 +#define USB_ENDPOINT_TYPE_CONTROL 0x00 +#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01 +#define USB_ENDPOINT_TYPE_BULK 0x02 +#define USB_ENDPOINT_TYPE_INTERRUPT 0x03 +#define USB_ENDPOINT_SYNC_MASK 0x0C +#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION 0x00 +#define USB_ENDPOINT_SYNC_ASYNCHRONOUS 0x04 +#define USB_ENDPOINT_SYNC_ADAPTIVE 0x08 +#define USB_ENDPOINT_SYNC_SYNCHRONOUS 0x0C +#define USB_ENDPOINT_USAGE_MASK 0x30 +#define USB_ENDPOINT_USAGE_DATA 0x00 +#define USB_ENDPOINT_USAGE_FEEDBACK 0x10 +#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK 0x20 +#define USB_ENDPOINT_USAGE_RESERVED 0x30 + +/* bEndpointAddress in Endpoint Descriptor */ +#define USB_ENDPOINT_DIRECTION_MASK 0x80 + +#if (PLATFORM_USB_USE_USB1 == TRUE) && !defined(__DOXYGEN__) +extern USBDriver USBD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void usb_lld_init(void); + void usb_lld_start(USBDriver *usbp); + void usb_lld_stop(USBDriver *usbp); + void usb_lld_reset(USBDriver *usbp); + void usb_lld_set_address(USBDriver *usbp); + void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep); + void usb_lld_disable_endpoints(USBDriver *usbp); + usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep); + usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep); + void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf); + void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep); + void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep); + void usb_lld_start_out(USBDriver *usbp, usbep_t ep); + void usb_lld_start_in(USBDriver *usbp, usbep_t ep); + void usb_lld_stall_out(USBDriver *usbp, usbep_t ep); + void usb_lld_stall_in(USBDriver *usbp, usbep_t ep); + void usb_lld_clear_out(USBDriver *usbp, usbep_t ep); + void usb_lld_clear_in(USBDriver *usbp, usbep_t ep); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_USB == TRUE */ + +#endif /* HAL_USB_LLD_H */ + +/** @} */ \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USB/sn32_usb.h b/os/hal/ports/SN32/LLD/SN32F24x/USB/sn32_usb.h new file mode 100644 index 00000000..beee10ef --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/USB/sn32_usb.h @@ -0,0 +1,59 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file USBv1/sn32_usb.h + * @brief SN32 USB registers layout header. + * @note This file requires definitions from the ST STM32 header files + * sn32f124x.h + * + * @addtogroup USB + * @{ + */ + +#ifndef SN32_USB_H +#define SN32_USB_H + +// TODO: ENDPOINTS nubmer is chip dependent and needs to be organized better +/** + * @brief Number of the available endpoints. + * @details This value does not include the endpoint 0 which is always present. + */ +#define USB_MAX_ENDPOINTS 6 + +/** + * @brief USB registers block numeric address. + */ +#define SN32_USB_BASE SN_USB_BASE + +/** + * @brief USB RAM numeric address. + */ +#define SN32_USBRAM_BASE SN_USB_BASE + 0x100 + +/** + * @brief Pointer to the USB registers block. + */ +// #define SN32_USB ((sn32_usb_t *)SN32_USB_BASE) + +/** + * @brief Pointer to the USB RAM. + */ +#define SN32_USBRAM ((sn32_usb_pma_t *)SN32_USBRAM_BASE) + +#endif /* SN32_USB_H */ + +/** @} */ \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USB/usbhw.c b/os/hal/ports/SN32/LLD/SN32F24x/USB/usbhw.c new file mode 100644 index 00000000..3eb8f967 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/USB/usbhw.c @@ -0,0 +1,323 @@ +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: usbhw.c + * Purpose: USB Custom User Module + * Version: V1.01 + * Date: 2017/07 + *------------------------------------------------------------------------------*/ +#include +#include "SN32F200_Def.h" + +#include "usbhw.h" +#include "usbsystem.h" + +volatile uint32_t wUSB_EPnOffset[7]; +volatile uint32_t wUSB_EPnMaxPacketsize[7]; + +/***************************************************************************** +* Function : USB_Init +* Description : 1. setting IDLE_TIME, REPORT_PROTOCOL, S_USB_EP0setupdata.wUSB_Status +* 2. set EP1~EP6 FIFO RAM address. +* 3. save EP1~EP6 FIFO RAM point address. +* 4. save EP1~EP6 Package Size. +* 5. Enable USB function and setting EP1~EP6 Direction. +* 6. NEVER REMOVE !! USB D+/D- Dischage +* 7. Enable USB PHY and USB interrupt. +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USB_Init (void) +{ + volatile uint32_t *pRam; + uint32_t wTmp, i; + + /* Initialize clock and Enable USB PHY. */ + USB_SystemInit(); // enable System,PLL,EHS XTAL by user setting + SN_SYS1->AHBCLKEN |= 0x02; // Enable USBCLKEN + __USB_PHY_ENABLE; // enable ESD_EN & PHY_EN + + /* Initialize USB EP1~EP6 RAM address base on 64-bytes. */ + USB_EPnBufferOffset(1,EP1_BUFFER_OFFSET_VALUE); + USB_EPnBufferOffset(2,EP2_BUFFER_OFFSET_VALUE); + USB_EPnBufferOffset(3,EP3_BUFFER_OFFSET_VALUE); + USB_EPnBufferOffset(4,EP4_BUFFER_OFFSET_VALUE); + USB_EPnBufferOffset(5,EP5_BUFFER_OFFSET_VALUE); + USB_EPnBufferOffset(6,EP6_BUFFER_OFFSET_VALUE); + + /* Initialize EP1~EP6 RAM point address to array(wUSB_EPnOffset).*/ + pRam = &wUSB_EPnOffset[0]; + *(pRam+0) = (uint32_t)(&USB_SRAM_EP0_W0) + EP1_BUFFER_OFFSET_VALUE; + *(pRam+1) = (uint32_t)(&USB_SRAM_EP0_W0) + EP2_BUFFER_OFFSET_VALUE; + *(pRam+2) = (uint32_t)(&USB_SRAM_EP0_W0) + EP3_BUFFER_OFFSET_VALUE; + *(pRam+3) = (uint32_t)(&USB_SRAM_EP0_W0) + EP4_BUFFER_OFFSET_VALUE; + *(pRam+4) = (uint32_t)(&USB_SRAM_EP0_W0) + EP5_BUFFER_OFFSET_VALUE; + *(pRam+5) = (uint32_t)(&USB_SRAM_EP0_W0) + EP6_BUFFER_OFFSET_VALUE; + + /* Initialize EP0~EP6 package size to array(wUSB_EPnPacketsize).*/ + pRam = &wUSB_EPnMaxPacketsize[0]; + *(pRam+0) = USB_EP0_PACKET_SIZE; + *(pRam+1) = USB_EP1_PACKET_SIZE; + *(pRam+2) = USB_EP2_PACKET_SIZE; + *(pRam+3) = USB_EP3_PACKET_SIZE; + *(pRam+4) = USB_EP4_PACKET_SIZE; + *(pRam+5) = USB_EP5_PACKET_SIZE; + *(pRam+6) = USB_EP6_PACKET_SIZE; + + /* Enable the USB Interrupt */ + SN_USB->INTEN = (mskBUS_IE|mskUSB_IE|mskUSB_BUSWK_IE); + SN_USB->INTEN |= mskEP1_NAK_EN; + SN_USB->INTEN |= mskEP2_NAK_EN; + SN_USB->INTEN |= mskEP3_NAK_EN; + SN_USB->INTEN |= mskEP4_NAK_EN; + SN_USB->INTEN |= mskEP5_NAK_EN; + SN_USB->INTEN |= mskEP6_NAK_EN; + SN_USB->INTEN |= mskUSB_SOF_IE; + + NVIC_ClearPendingIRQ(USB_IRQn); + NVIC_EnableIRQ(USB_IRQn); + + /* BUS_DRVEN = 0, BUS_DP = 1, BUS_DN = 0 */ + SN_USB->SGCTL = mskBUS_J_STATE; + /* VREG33_EN = 1, PHY_EN = 1, DPPU_EN = 1, SIE_EN = 1, USBRAM_EN = 1, FLTDET_PUEN = 1 */ + wTmp = (mskVREG33_EN|mskPHY_EN|mskDPPU_EN|mskSIE_EN|mskESD_EN|mskUSBRAM_EN|mskVREG33DIS_EN|mskFLTDET_PUEN_DISABLE); + + //!!NEVER REMOVE!!! + SN_USB->CFG = wTmp; + for (i = 0; i < DISCHARE_DELAY; i++); + SN_USB->CFG = (wTmp&(~mskVREG33DIS_EN))|mskDPPU_EN; + //!!NEVER REMOVE!!! + + SN_USB->PHYPRM = (0x01U<<31); + return; +} + +/***************************************************************************** +* Function : USB_ClrEPnToggle +* Description : USB Clear EP1~EP6 toggle bit to DATA0 +* write 1: toggle bit Auto. +* write 0: clear EPn toggle bit to DATA0 +* Input : hwEPNum ->EP1~EP6 +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USB_ClrEPnToggle (uint32_t hwEPNum) +{ + SN_USB->EPTOGGLE &= ~(0x1< USB_EP6) + return; + pEPn_ptr = &SN_USB->EP0CTL + wEPNum; + *pEPn_ptr = 0; //** SET DISABLE. No handshake IN/OUT token. +} + +/***************************************************************************** +* Function : USB_EPnNak +* Description : SET EP1~EP6 is NAK. +* For IN will handshake NAK to IN token. +* For OUT will handshake NAK to OUT token. +* Input : wEPNum +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USB_EPnNak (uint32_t wEPNum) +{ + volatile uint32_t *pEPn_ptr; + if(wEPNum > USB_EP6) + return; + pEPn_ptr = &SN_USB->EP0CTL + wEPNum; + *pEPn_ptr = mskEPn_ENDP_EN; //** SET NAK +} + +/***************************************************************************** +* Function : USB_EPnAck +* Description : SET EP1~EP6 is ACK. +* For IN will handshake bBytent to IN token. +* For OUT will handshake ACK to OUT token. +* Input : wEPNum:EP1~EP6. +* bBytecnt: Byte Number of Handshake. +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USB_EPnAck (uint32_t wEPNum, uint8_t bBytecnt) +{ + volatile uint32_t *pEPn_ptr; + if (wEPNum > USB_EP6) + return; + pEPn_ptr = &SN_USB->EP0CTL + wEPNum; + *pEPn_ptr = (mskEPn_ENDP_EN|mskEPn_ENDP_STATE_ACK|bBytecnt); +} + +/***************************************************************************** +* Function : USB_EPnAck +* Description : SET EP1~EP6 is STALL. For IN will handshake STALL to IN token. +* For OUT will handshake STALL to OUT token. +* Input : wEPNum:EP1~EP6. +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USB_EPnStall (uint32_t wEPNum) +{ + volatile uint32_t *pEPn_ptr; + if(wEPNum > USB_EP6) //wEPNum != EP0~EP6 + return; + pEPn_ptr = &SN_USB->EP0CTL + wEPNum; + if (wEPNum == USB_EP0) + { + if(SN_USB->INSTS & mskEP0_PRESETUP) + return; + } + *pEPn_ptr = (mskEPn_ENDP_EN|mskEPn_ENDP_STATE_STALL); +} + +/***************************************************************************** +* Function : USB_EPnEnabled +* Description : check if EP0~EP4 enabled or not +* Input : wEPNum:EP0~EP4. +* Output : None +* Return : true - enabled/false - disabled +* Note : None +*****************************************************************************/ +_Bool USB_EPnEnabled(uint32_t wEPNum) +{ + volatile uint32_t *pEPn_ptr; + if(wEPNum > USB_EP6) //** wEPNum != EP0~EP6 + return 0; + pEPn_ptr = &SN_USB->EP0CTL + wEPNum; + return (((*pEPn_ptr) & mskEPn_ENDP_EN) == mskEPn_ENDP_EN); +} + +/***************************************************************************** +* Function : USB_EPnStalled +* Description : GET EP0~EP4 state. +* Input : wEPNum:EP0~EP4. +* Output : None +* Return : mskEPn_ENDP_STATE +* Note : None +*****************************************************************************/ +_Bool USB_EPnStalled(uint32_t wEPNum) +{ + volatile uint32_t *pEPn_ptr; + if(wEPNum > USB_EP6) //** wEPNum != EP0~EP6 + return 0; + pEPn_ptr = &SN_USB->EP0CTL + wEPNum; + return (((*pEPn_ptr) & mskEPn_ENDP_STATE) == mskEPn_ENDP_STATE_STALL); +} + +/***************************************************************************** +* Function : USB_RemoteWakeUp +* Description : USB Remote wakeup: USB D+/D- siganl is J-K state. +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USB_RemoteWakeUp() +{ + __USB_JSTATE_DRIVER; //** J state ;Full speed D+ = 1, D- = 0 + USB_DelayJstate(); + __USB_KSTATE_DRIVER; //** K state ;Full speed D+ = 0, D- = 1 + USB_DelayKstate(); + SN_USB->SGCTL &= ~mskBUS_DRVEN; +} + +/***************************************************************************** + * Function : USB_DelayJstate + * Description : For J state delay. about 180us + * Input : None + * Output : None + * Return : None + * Note : None + *****************************************************************************/ +void USB_DelayJstate() +{ + uint32_t i; + for (i = 0; i < 300; i++) + ; // delay 180us +} + +/***************************************************************************** + * Function : USB_DelayKstate + * Description : For K state delay. about 14 ~ 14.5ms + * Input : None + * Output : None + * Return : None + * Note : None + *****************************************************************************/ +void USB_DelayKstate() +{ + uint32_t i; + for (i = 0; i < K_STATE_DELAY; i++) + ; // require delay 1ms ~ 15ms +} + +/***************************************************************************** +* Function : USB_EPnBufferOffset +* Description : SET EP1~EP6 RAM point address +* Input : wEPNum: EP1~EP6 +* wAddr of device address +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USB_EPnBufferOffset(uint32_t wEPNum, uint32_t wAddr) +{ + volatile uint32_t *pEPn_ptr; + if ((wEPNum > USB_EP0) && (wEPNum <= USB_EP6)) //wEPNum = EP1 ~ EP6 + { + pEPn_ptr = &SN_USB->EP1BUFOS; // Assign point to EP1 RAM address + *(pEPn_ptr+wEPNum-1) = wAddr; // SET point to EPn RAM address + } +} + +/***************************************************************************** +* Function : USB_ResetEvent +* Description : recevice USB bus reset to Initial parameter +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USB_ResetEvent (void) +{ + uint32_t wLoop; + __USB_CLRINSTS(0xFFFFFFFF); // Clear all USB Event status + __USB_SETADDRESS(0); // Set USB address = 0 + USB_EPnStall(USB_EP0); // Set EP0 enable & INOUTSTALL + + for (wLoop=USB_EP1; wLoop<=USB_EP6; wLoop++) + USB_EPnDisable(wLoop); // Set EP1~EP6 disable & NAK +} + +/***************************************************************************** +* Function : USB_WakeupEvent +* Description : Enable USB CLK and PHY +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void USB_WakeupEvent (void) +{ + USB_SystemInit(); // enable System,PLL,EHS XTAL by user setting + __USB_PHY_ENABLE; //** enable ESD_EN & PHY_EN + __USB_CLRINSTS(mskBUS_WAKEUP); //** Clear BUS_WAKEUP +} \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USB/usbhw.h b/os/hal/ports/SN32/LLD/SN32F24x/USB/usbhw.h new file mode 100644 index 00000000..4c36a252 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/USB/usbhw.h @@ -0,0 +1,264 @@ +/**************************************************************************** + **************************************************************************** +****************************************************************************/ +#ifndef __USBHW_H__ +#define __USBHW_H__ + +//** USB Remote Wakeup I/O Define +//** USB Remote Wakeup I/O Port Define, Default P1.5 +#define REMOTE_WAKEUP_IO_P0 DISABLE +#define REMOTE_WAKEUP_IO_P1 ENABLE +#define REMOTE_WAKEUP_IO_P2 DISABLE +#define REMOTE_WAKEUP_IO_P3 DISABLE + +//** USB Remote Wakeup I/O Bit Define +#define REMOTE_WAKEUP_IO_P0_BIT 0x0000 +#define REMOTE_WAKEUP_IO_P1_BIT 0x0020 +#define REMOTE_WAKEUP_IO_P2_BIT 0x0000 +#define REMOTE_WAKEUP_IO_P3_BIT 0x0000 + +//** USB EPn NAK interrupt +#define EP1_NAK_IE DISABLE +#define EP2_NAK_IE DISABLE +#define EP3_NAK_IE DISABLE +#define EP4_NAK_IE DISABLE + +//** USB SOF interrupt +#define SOF_IE DISABLE + +/* AHB Clock Enable register */ +#define mskP0CLK_EN (0x1<<0) +#define mskP1CLK_EN (0x1<<1) +#define mskP2CLK_EN (0x1<<2) +#define mskP3CLK_EN (0x1<<3) +#define mskUSBCLK_EN (0x1<<4) +#define mskCT16B0CLK_EN (0x1<<6) +#define mskCT16B1CLK_EN (0x1<<7) +#define mskADCCLK_EN (0x1<<11) +#define mskSPI0CLK_EN (0x1<<12) +#define mskUART0CLK_EN (0x1<<16) +#define mskUART1CLK_EN (0x1<<17) +#define mskUART2CLK_EN (0x1<<18) +#define mskI2C0CLK_EN (0x1<<21) +#define mskWDTCLK_EN (0x1<<24) + +/* USB Interrupt Enable Bit Definitions */ +#define mskEP1_NAK_EN (0x1<<0) +#define mskEP2_NAK_EN (0x1<<1) +#define mskEP3_NAK_EN (0x1<<2) +#define mskEP4_NAK_EN (0x1<<3) +#define mskEP5_NAK_EN (0x1<<4) +#define mskEP6_NAK_EN (0x1<<5) +#define mskUSB_BUSWK_IE (0x1<<28) +#define mskUSB_IE (0x1<<29) +#define mskUSB_SOF_IE (0x1<<30) +#define mskBUS_IE (0x1U<<31) + +/* USB Interrupt Event Status Bit Definitions */ +#define mskEP1_NAK (0x1<<0) +#define mskEP2_NAK (0x1<<1) +#define mskEP3_NAK (0x1<<2) +#define mskEP4_NAK (0x1<<3) +#define mskEP5_NAK (0x1<<4) +#define mskEP6_NAK (0x1<<5) +#define mskEP1_ACK (0x1<<8) +#define mskEP2_ACK (0x1<<9) +#define mskEP3_ACK (0x1<<10) +#define mskEP4_ACK (0x1<<11) +#define mskEP5_ACK (0x1<<12) +#define mskEP6_ACK (0x1<<13) +#define mskERR_TIMEOUT (0x1<<17) +#define mskERR_SETUP (0x1<<18) +#define mskEP0_OUT_STALL (0x1<<19) +#define mskEP0_IN_STALL (0x1<<20) +#define mskEP0_OUT (0x1<<21) +#define mskEP0_IN (0x1<<22) +#define mskEP0_SETUP (0x1<<23) +#define mskEP0_PRESETUP (0x1<<24) +#define mskBUS_WAKEUP (0x1<<25) +#define mskUSB_SOF (0x1<<26) +#define mskBUS_RESUME (0x1<<29) +#define mskBUS_SUSPEND (0x1<<30) +#define mskBUS_RESET (0x1U<<31) + +/* USB Device Address Bit Definitions */ +#define mskUADDR (0x7F<<0) + +/* USB Configuration Bit Definitions */ +#define mskEP1_DIR (0x1<<0) +#define mskEP2_DIR (0x1<<1) +#define mskEP3_DIR (0x1<<2) +#define mskEP4_DIR (0x1<<3) +#define mskEP5_DIR (0x1<<4) +#define mskEP6_DIR (0x1<<5) +#define mskEP2_ISO (0x1<<9) +#define mskEP3_ISO (0x1<<10) +#define mskEP4_ISO (0x1<<11) +#define mskEP5_ISO (0x1<<12) +#define mskEP6_ISO (0x1<<13) +#define mskVREG33DIS_EN (0x1<<31) +#define mskUSBRAM_EN (0x1<<25) +#define mskFLTDET_PUEN_DISABLE (0x1<<26) // FixMe ? // #define mskDIS_PDEN (0x1<<26) +#define mskESD_EN (0x1<<27) +#define mskSIE_EN (0x1<<28) +#define mskDPPU_EN (0x1<<29) +#define mskPHY_EN (0x1<<30) +#define mskVREG33_EN (0x1U<<31) + +/* USB Signal Control Bit Definitions */ +#define mskBUS_DRVEN (0x1<<2) +#define mskBUS_DPDN_STATE (0x3<<0) +#define mskBUS_J_STATE (0x2<<0) // D+ = 1, D- = 0 +#define mskBUS_K_STATE (0x1<<0) // D+ = 0, D- = 1 +#define mskBUS_SE0_STATE (0x0<<0) // D+ = 0, D- = 0 +#define mskBUS_SE1_STATE (0x3<<0) // D+ = 1, D- = 1 +#define mskBUS_IDLE_STATE mskBUS_J_STATE + +/* USB Configuration Bit Definitions */ +#define mskEPn_CNT (0x1FF<<0) +#define mskEP0_OUT_STALL_EN (0x1<<27) +#define mskEP0_IN_STALL_EN (0x1<<28) +#define mskEPn_ENDP_STATE (0x3<<29) +#define mskEPn_ENDP_STATE_ACK (0x1<<29) +#define mskEPn_ENDP_STATE_NAK (0x0<<29) +#define mskEPn_ENDP_STATE_STALL (0x3<<29) +#define mskEPn_ENDP_EN (0x1U<<31) + +/* USB Endpoint Data Toggle Bit Definitions */ +#define mskEP1_CLEAR_DATA0 (0x1<<0) +#define mskEP2_CLEAR_DATA0 (0x1<<1) +#define mskEP3_CLEAR_DATA0 (0x1<<2) +#define mskEP4_CLEAR_DATA0 (0x1<<3) +#define mskEP5_CLEAR_DATA0 (0x1<<4) +#define mskEP6_CLEAR_DATA0 (0x1<<5) + +/* USB Endpoint n Buffer Offset Bit Definitions */ +#define mskEPn_OFFSET (0x1FF<<0) + +/* USB Frame Number Bit Definitions */ +#define mskFRAME_NO (0x7FF<<0) + +/* Rx & Tx Packet Length Definitions */ +#define PKT_LNGTH_MASK 0x000003FF + +/* nUsb_Status Register Definitions */ +#define mskBUSRESET (0x1<<0) +#define mskBUSSUSPEND (0x1<<1) +#define mskBUSRESUME (0x1<<2) +#define mskREMOTEWAKEUP (0x1<<3) +#define mskSETCONFIGURATION0CMD (0x1<<4) +#define mskSETADDRESS (0x1<<5) +#define mskSETADDRESSCMD (0x1<<6) +#define mskREMOTE_WAKEUP (0x1<<7) +#define mskDEV_FEATURE_CMD (0x1<<8) +#define mskSET_REPORT_FLAG (0x1<<9) +#define mskPROTOCOL_GET_REPORT (0x1<<10) +#define mskPROTOCOL_SET_IDLE (0x1<<11) +#define mskPROTOCOL_ARRIVAL (0x1<<12) +#define mskSET_REPORT_DONE (0x1<<13) +#define mskNOT_8BYTE_ENDDING (0x1<<14) +#define mskSETUP_OUT (0x1<<15) +#define mskSETUP_IN (0x1<<16) +#define mskINITREPEAT (0x1<<17) +#define mskREMOTE_WAKEUP_ACT (0x1<<18) + +//ISP KERNEL MODE +#define RETURN_KERNEL_0 0x5AA555AA +#define RETURN_KERNEL_1 0xCC3300FF +/*********Marco function***************/ + +//USB device address set +#define __USB_SETADDRESS(addr) (SN_USB->ADDR = addr) +//USB INT status register clear +#define __USB_CLRINSTS(Clrflag) (SN_USB->INSTSC = Clrflag) +//USB EP0_IN token set STALL +#define __USB_EP0INSTALL_EN (SN_USB->EP0CTL |= mskEP0_IN_STALL_EN) +//USB EP0_OUT token set STALL +#define __USB_EP0OUTSTALL_EN (SN_USB->EP0CTL |= mskEP0_OUT_STALL_EN) +//USB bus driver J state +#define __USB_JSTATE_DRIVER (SN_USB->SGCTL = (mskBUS_DRVEN|mskBUS_J_STATE)) +//USB bus driver K state +#define __USB_KSTATE_DRIVER (SN_USB->SGCTL = (mskBUS_DRVEN|mskBUS_K_STATE)) +//USB PHY set enable +#define __USB_PHY_ENABLE (SN_USB->CFG |= (mskESD_EN|mskPHY_EN)) +//USB PHY set Disable +#define __USB_PHY_DISABLE (SN_USB->CFG &= ~(mskESD_EN|mskPHY_EN)) + +/***************************************/ + +/* USB SRAM */ +#define USB_SRAM_EP0_W0 *((uint32_t *)&SN_USB->SRAM+0) // EP0 SRAM Byte 0~3 +#define USB_SRAM_EP0_W1 *((uint32_t *)&SN_USB->SRAM+1) // EP0 SRAM Byte 4~7 +#define USB_SRAM_EP0_W2 *((uint32_t *)&SN_USB->SRAM+2) // EP0 SRAM Byte 8~11 +#define USB_SRAM_EP0_W3 *((uint32_t *)&SN_USB->SRAM+3) // EP0 SRAM Byte 12~15 +#define USB_SRAM_EP0_W4 *((uint32_t *)&SN_USB->SRAM+4) // EP0 SRAM Byte 16~19 +#define USB_SRAM_EP0_W5 *((uint32_t *)&SN_USB->SRAM+5) // EP0 SRAM Byte 20~23 +#define USB_SRAM_EP0_W6 *((uint32_t *)&SN_USB->SRAM+6) // EP0 SRAM Byte 24~27 +#define USB_SRAM_EP0_W7 *((uint32_t *)&SN_USB->SRAM+7) // EP0 SRAM Byte 28~31 +#define USB_SRAM_EP0_W8 *((uint32_t *)&SN_USB->SRAM+8) // EP0 SRAM Byte 32~35 +#define USB_SRAM_EP0_W9 *((uint32_t *)&SN_USB->SRAM+9) // EP0 SRAM Byte 36~39 +#define USB_SRAM_EP0_W10 *((uint32_t *)&SN_USB->SRAM+10) // EP0 SRAM Byte 40~43 +#define USB_SRAM_EP0_W11 *((uint32_t *)&SN_USB->SRAM+11) // EP0 SRAM Byte 44~47 +#define USB_SRAM_EP0_W12 *((uint32_t *)&SN_USB->SRAM+12) // EP0 SRAM Byte 48~51 +#define USB_SRAM_EP0_W13 *((uint32_t *)&SN_USB->SRAM+13) // EP0 SRAM Byte 52~55 +#define USB_SRAM_EP0_W14 *((uint32_t *)&SN_USB->SRAM+14) // EP0 SRAM Byte 56~59 +#define USB_SRAM_EP0_W15 *((uint32_t *)&SN_USB->SRAM+15) // EP0 SRAM Byte 60~63 + +/* TODO: orgaize better since this is MCU dependent: + * 240b has 1+4 EPs/256 Bytes USB SRAM + * 240 has 1+6 EPs/512 Bytes USB SRAM + * 260 has 1+4 EPs/256 Bytes USB SRAM + * */ +// USB EPn Buffer Offset Register +#define EP1_BUFFER_OFFSET_VALUE 0x40 +#define EP2_BUFFER_OFFSET_VALUE 0x80 +#define EP3_BUFFER_OFFSET_VALUE 0xC0 +#define EP4_BUFFER_OFFSET_VALUE 0x100 +#define EP5_BUFFER_OFFSET_VALUE 0x140 +#define EP6_BUFFER_OFFSET_VALUE 0x180 + +/* USB Endpoint Max Packet Size */ +#define USB_EP0_PACKET_SIZE 64 // only 8, 64 +#define USB_EP1_PACKET_SIZE 0x40 +#define USB_EP2_PACKET_SIZE 0x40 +#define USB_EP3_PACKET_SIZE 0x20 +#define USB_EP4_PACKET_SIZE 0x20 +#define USB_EP5_PACKET_SIZE 0x20 +#define USB_EP6_PACKET_SIZE 0x20 + +/* USB Endpoint Direction */ +#define USB_DIRECTION_OUT 0 +#define USB_DIRECTION_IN 1 + +/* USB Endpoint Address */ +#define USB_EP0 0x0 +#define USB_EP1 0x1 +#define USB_EP2 0x2 +#define USB_EP3 0x3 +#define USB_EP4 0x4 +#define USB_EP5 0x5 +#define USB_EP6 0x6 + +extern volatile uint32_t wUSB_EPnOffset[]; +extern volatile uint32_t wUSB_EPnMaxPacketSize[]; + +/* USB Hardware Functions */ +extern void USB_Init(void); +extern void USB_ClrEPnToggle(uint32_t wEPNum); +extern void USB_EPnDisable(uint32_t wEPNum); +extern void USB_EPnNak(uint32_t wEPNum); +extern void USB_EPnAck(uint32_t wEPNum, uint8_t bBytecnt); +extern void USB_EPnStall(uint32_t wEPNum); +extern _Bool USB_EPnEnabled(uint32_t wEPNum); +extern _Bool USB_EPnStalled(uint32_t wEPNum); + +extern void USB_RemoteWakeUp(void); +extern void USB_DelayJstate(void); +extern void USB_DelayKstate(void); +extern void USB_EPnBufferOffset(uint32_t wEPNum, uint32_t wAddr); + +/* USB IRQ Functions*/ +extern void USB_ResetEvent(void); +extern void USB_WakeupEvent(void); + +#endif /* __USBHW_H__ */ \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USB/usbsystem.c b/os/hal/ports/SN32/LLD/SN32F24x/USB/usbsystem.c new file mode 100644 index 00000000..d837576c --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/USB/usbsystem.c @@ -0,0 +1,106 @@ +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: usbsystem.c + * Purpose: USB Custom User Module + * Version: V1.01 + * Date: 2013/12 + *------------------------------------------------------------------------------*/ +#include +//#include "type.h" +//#include "..\Utility\Utility.h" + +#include "usbsystem.h" + + +void USB_SystemInit (void) +{ + + SN_FLASH->LPCTRL = 0x5AFA0000; //Disable Slow mode power saving + +//*********************************** +#if (USB_SYS_CLOCK_SETUP) + + #if (USB_SYS0_CLKCFG_VAL == USB_IHRC) //IHRC + SN_SYS0->ANBCTRL |= USB_IHRC_EN; //enable IHRC + while ((SN_SYS0->CSST & 0x01) != 0x01); //check IHRC ready + SN_SYS0->CLKCFG = 0x00; //switch IHRC + while ((SN_SYS0->CLKCFG & 0x70) != 0x00); + #endif + + #if (USB_SYS0_CLKCFG_VAL == USB_ILRC) //ILRC + SN_SYS0->CLKCFG = 0x1; + while ((SN_SYS0->CLKCFG & 0x70) != 0x10); //switch ILRC + #endif + + #if (USB_SYS0_CLKCFG_VAL == USB_EHSXTAL) //EHS XTAL + #if (USB_EHS_FREQ > 12) + SN_SYS0->ANBCTRL |= (1<<5); //Enable XTAL > 12MHz + #else + SN_SYS0->ANBCTRL &=~(1<<5); //Enable XTAL <= 12MHz + #endif + + SN_SYS0->ANBCTRL |= (1<<4); //Enable XTAL + while ((SN_SYS0->CSST & 0x10) != 0x10); + SN_SYS0->CLKCFG = 0x02; //switch XTAL + while ((SN_SYS0->CLKCFG & 0x70) != 0X20); + #endif +#endif + + #if (USB_PLL_ENABLE == 0x01) //SET PLL + SN_SYS0->PLLCTRL = USB_SYS0_PLLCTRL_EN; //ENABLE PLL + if(USB_PLL_CLKIN == 0x0) //PLL clk source is IHRC + { + SN_SYS0->ANBCTRL |= USB_IHRC_EN; //enable IHRC + SN_SYS0->PLLCTRL |= USB_PLL_CLKSOURCE_IHRC; + } + else //PLL clk source is XTAL + { + + #if (USB_EHS_FREQ > 12) + SN_SYS0->ANBCTRL |= (1<<5); //Enable XTAL > 12MHz + #else + SN_SYS0->ANBCTRL &=~(1<<5); //Enable XTAL <= 12MHz + #endif + + SN_SYS0->ANBCTRL |= (1<<4); //Enable XTAL + while ((SN_SYS0->CSST & 0x10) != 0x10); + + + + #if (USB_EHS_FREQ == 12) //XTAL = 12MHz + //SN_SYS0->ANBCTRL |= (1<<5); //Enable XTAL < 12MHz + SN_SYS0->PLLCTRL |= USB_PLL_CLKSOURCE_12MHz; + #endif + + #if (USB_EHS_FREQ == 16) //XTAL = 16MHz + SN_SYS0->ANBCTRL |=(1<<5); //Enable XTAL > 12MHz + SN_SYS0->PLLCTRL |= USB_PLL_CLKSOURCE_16MHz; + #endif + + #if (USB_EHS_FREQ == 24) //XTAL = 24MHz + SN_SYS0->ANBCTRL |=(1<<5); //Enable XTAL > 12MHz + SN_SYS0->PLLCTRL |= USB_PLL_CLKSOURCE_24MHz; + #endif + SN_SYS0->ANBCTRL |= (1<<4); //Enable EHS XTAL + while ((SN_SYS0->CSST & 0x10) != 0x10); + + #if (USB_PLL_CLKIN == 0x01 ) + SN_SYS0->PLLCTRL |= (0x01<<12); + SN_SYS0->PLLCTRL |= (0x01<<15); //ENABLE PLL + #endif + } + #endif + + #if (USB_SYS0_CLKCFG_VAL == USB_PLL) + { + while ((SN_SYS0->CSST & 0x40) != 0x40); + SN_SYS0->CLKCFG = 0x4; //CLK switch PLL + while ((SN_SYS0->CLKCFG & 0x70) != 0x40); + } + #endif + SN_SYS0->AHBCP = USB_AHB_PRESCALAR; + #if (USB_CLKOUT_SEL_VAL > 0) //CLKOUT + SN_SYS1->AHBCLKEN |= (USB_CLKOUT_SEL_VAL<<28); + #endif +} \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F24x/USB/usbsystem.h b/os/hal/ports/SN32/LLD/SN32F24x/USB/usbsystem.h new file mode 100644 index 00000000..c9aa2a8b --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/USB/usbsystem.h @@ -0,0 +1,145 @@ +/*---------------------------------------------------------------------------- + * U S B - K e r n e l + *---------------------------------------------------------------------------- + * Name: usbsystem.h + * Purpose: USB Custom User Definitions + * Version: V1.20 + *----------------------------------------------------------------------------*/ + +#ifndef __USBSYSTEM_H__ +#define __USBSYSTEM_H__ +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// System Clock Configuration +// SYSCLKSEL (SYS0_CLKCFG) +// <0=> ILRC +// <1=> IHRC +// <2=> EHS X'TAL +// <4=> PLL +// +// EHS Source Frequency (MHz) +// <10-25> +// +// PLL Control Register (SYS0_PLLCTRL) +// F_CLKOUT = F_VCO / P = (F_CLKIN / F * M) / P +// 10 MHz <= F_CLKIN <= 25 MHz +// 156 MHz <= (F_CLKIN / F * M) <= 320 MHz +// MSEL +// <24=> MSEL = 24 +// <18=> MSEL = 18 +// <12=> MSEL = 12 +// PSEL +// <3=> P = 6 +// <4=> P = 8 +// FSEL +// <0=> F = 1 +// <1=> F = 2 +// PLL CLKIN Source selection +// <0=> IHRC +// <1=> EHS X'TAL +// PLL Enable selection +// <1=> Enable +// +// +// AHB Clock Prescaler Register (SYS0_AHBCP) +// <0=> SYSCLK/1 +// <1=> SYSCLK/2 +// <2=> SYSCLK/4 +// <3=> SYSCLK/8 +// <4=> SYSCLK/16 +// <5=> SYSCLK/32 +// <6=> SYSCLK/64 +// <7=> SYSCLK/128 +// <8=> SYSCLK/256 +// <9=> SYSCLK/512 +// +// CLKOUT selection +// <0=> Disable +// <1=> ILRC +// <2=> ELS X'TAL +// <4=> HCLK +// <5=> IHRC +// <6=> EHS X'TAL +// <7=> PLL +// +*/ + +#define USB_SYS_CLOCK_SETUP 1 +#define USB_SYS0_CLKCFG_VAL USB_PLL +#define USB_EHS_FREQ 12 +#define USB_PLL_MSEL 18 +#define USB_PLL_PSEL 3 +#define USB_PLL_FSEL 0 +#define USB_PLL_CLKIN 0 +#define USB_PLL_ENABLE 1 +#define USB_AHB_PRESCALAR 0x0 +#define USB_CLKOUT_SEL_VAL 0x0 + +/* +//-------- <<< end of configuration section >>> ------------------------------ +*/ +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ +#define USB_IHRC 0 +#define USB_ILRC 1 +#define USB_EHSXTAL 2 +#define USB_ELSXTAL 3 +#define USB_PLL 4 + +#define USB_IHRC_EN 1 +#define USB_SYS0_PLLCTRL_EN 0x8000 +#define USB_PSEL_6 (0x03<<5) +#define USB_PSEL_8 (0x04<<5) +#define USB_MSEL_24 24 +#define USB_MSEL_18 18 +#define USB_MSEL_12 12 +#define USB_PLL_CLKSOURCE_IHRC (USB_PSEL_6|USB_MSEL_24) +#define USB_PLL_CLKSOURCE_12MHz (USB_PSEL_6|USB_MSEL_24) +#define USB_PLL_CLKSOURCE_16MHz (USB_PSEL_6|USB_MSEL_18) +#define USB_PLL_CLKSOURCE_24MHz (USB_PSEL_6|USB_MSEL_12) + +#define USB_PLL_DLEYA_TIME 100000 +#define USB_PLL_10US_TIME 76 + +#if (USB_SYS0_CLKCFG_VAL == USB_PLL) + #define K_STATE_DELAY USB_PLL_DLEYA_TIME*(USB_AHB_PRESCALAR+1) + #define DISCHARE_DELAY K_STATE_DELAY + #define UTILITY_10US_DELAY USB_PLL_10US_TIME*(USB_AHB_PRESCALAR+1) +#endif //end USB_SYS0_CLKCFG_VAL == PLL + +#if (USB_SYS0_CLKCFG_VAL == USB_IHRC) +#define K_STATE_DELAY (USB_PLL_DLEYA_TIME/4)*(USB_AHB_PRESCALAR+1) +#define DISCHARE_DELAY K_STATE_DELAY + #define UTILITY_10US_DELAY (USB_PLL_10US_TIME/4)*(USB_AHB_PRESCALAR+1) +#endif //end USB_SYS0_CLKCFG_VAL == USB_IHRC + +#if (USB_SYS0_CLKCFG_VAL == USB_EHSXTAL) +#if (USB_EHS_FREQ == 12) + #define K_STATE_DELAY (USB_PLL_DLEYA_TIME/4)*(USB_AHB_PRESCALAR+1) + #define DISCHARE_DELAY K_STATE_DELAY + #define UTILITY_10US_DELAY (USB_PLL_10US_TIME/4)*(USB_AHB_PRESCALAR+1) +#elif (USB_EHS_FREQ == 16) + #define K_STATE_DELAY (USB_PLL_DLEYA_TIME/3)*(USB_AHB_PRESCALAR+1) + #define DISCHARE_DELAY K_STATE_DELAY + #define UTILITY_10US_DELAY (USB_PLL_10US_TIME/3)*(USB_AHB_PRESCALAR+1) +#elif (USB_EHS_FREQ == 24) + #define K_STATE_DELAY (USB_PLL_DLEYA_TIME/2)*(USB_AHB_PRESCALAR+1) + #define DISCHARE_DELAY K_STATE_DELAY + #define UTILITY_10US_DELAY (USB_PLL_10US_TIME/2)*(USB_AHB_PRESCALAR+1) +#endif //end USB_EHS_FREQ +#endif //end USB_SYS0_CLKCFG_VAL == USB_EHSTAL + +extern void USB_SystemInit (void); +#endif /* __USBSYSTEM_H__ */ \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F24x/WDT/WDT.c b/os/hal/ports/SN32/LLD/SN32F24x/WDT/WDT.c new file mode 100644 index 00000000..a774d183 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/WDT/WDT.c @@ -0,0 +1,155 @@ +/******************** (C) COPYRIGHT 2014 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2014/01 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: WDT related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 First release +* 1.1 2014/01/20 SA1 1. Modify WDT_ReloadValue function +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include +#include "WDT.h" +#include "..\..\System\SYS_con_drive.h" + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + + +/*_____ F U N C T I O N S __________________________________________________*/ +/***************************************************************************** +* Function : WDT_IRQHandler +* Description : ISR of WDT interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void WDT_IRQHandler(void) +{ + SN_GPIO2->DATA_b.DATA0 = ~SN_GPIO2->DATA_b.DATA0; //P2.0 toggle + + __WDT_FEED_VALUE; + + __WDT_CLRINSTS; //Clear WDT interrupt flag +} + +/***************************************************************************** +* Function : WDT_Init +* Description : WDT initial +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void WDT_Init(void) +{ + uint32_t wRegBuf; + + WDT_SelectClockSource(WDT_CLKSEL_ILRC); //clock source select + + #if WDT_MODE == INTERRUPT + wRegBuf = mskWDT_WDTIE_ENABLE; //WDT as interrupt mode + #endif + + #if WDT_MODE == RESET + wRegBuf = mskWDT_WDTIE_DISABLE; //WDT as reset mode + #endif + + wRegBuf = wRegBuf & (~mskWDT_WDTINT); //Clear WDT interrupt flag + + wRegBuf = wRegBuf | mskWDT_WDKEY; + + SN_WDT->CFG = wRegBuf; + + WDT_ReloadValue(61); //Set overflow time = 250ms + + WDT_NvicEnable(); //Enable WDT NVIC interrupt + + __WDT_ENABLE; //Enable WDT +} + +/***************************************************************************** +* Function : WDT_ReloadValue +* Description : set WDT reload value +* Input : time - + 0~255: overflow time set +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void WDT_ReloadValue(uint32_t time) +{ + uint32_t wRegBuf; + + wRegBuf = time | mskWDT_WDKEY; + + SN_WDT->TC = wRegBuf; + + __WDT_FEED_VALUE; +} + +/*********************************************************************************** +* Function : WDT_SelectClockSource +* Description : Select WDT clcok source +* Input : WDT clock source - + WDT_CLKSEL_IHRC or WDT_CLKSEL_HCLK or WDT_CLKSEL_ILRC or WDT_CLKSEL_ELS +* Output : None +* Return : None +* Note : None +***********************************************************************************/ +void WDT_SelectClockSource(uint32_t src) +{ + if (src == WDT_CLKSEL_IHRC) + SYS0_EnableIHRC(); + else if (src == WDT_CLKSEL_ELS) + SYS0_EnableELSXtal(); + + SN_WDT->CLKSOURCE = mskWDT_WDKEY | src; //clock source select +} + +/***************************************************************************** +* Function : WDT_NvicEnable +* Description : Enable WDT interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void WDT_NvicEnable(void) +{ + NVIC_ClearPendingIRQ(WDT_IRQn); + NVIC_EnableIRQ(WDT_IRQn); + NVIC_SetPriority(WDT_IRQn, 0); // Set interrupt priority (default) +} + +/***************************************************************************** +* Function : WDT_NvicDisable +* Description : Disable WDT interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void WDT_NvicDisable(void) +{ + NVIC_DisableIRQ(WDT_IRQn); +} diff --git a/os/hal/ports/SN32/LLD/SN32F24x/WDT/WDT.h b/os/hal/ports/SN32/LLD/SN32F24x/WDT/WDT.h new file mode 100644 index 00000000..67e44a36 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F24x/WDT/WDT.h @@ -0,0 +1,55 @@ +#ifndef __SN32F240_WDT_H +#define __SN32F240_WDT_H + +/*_____ I N C L U D E S ____________________________________________________*/ +#include + +/*_____ D E F I N I T I O N S ______________________________________________*/ +#define RESET 0 //WDT as Reset mode +#define INTERRUPT 1 //WDT as Interrupt mode +#define WDT_MODE INTERRUPT + //RESET_MODE : WDT as Reset mode + +//Watchdog register key +#define mskWDT_WDKEY (0x5AFA<<16) + +//Watchdog interrupt flag +#define mskWDT_WDTINT (1<<2) + +//Watchdog interrupt enable +#define WDT_WDTIE_DISABLE 0 +#define WDT_WDTIE_ENABLE 1 +#define mskWDT_WDTIE_DISABLE (WDT_WDTIE_DISABLE<<1) +#define mskWDT_WDTIE_ENABLE (WDT_WDTIE_ENABLE<<1) + +//Watchdog enable +#define mskWDT_WDTEN_DISABLE 0 +#define mskWDT_WDTEN_ENABLE 1 + +//Watchdog Clock source +#define WDT_CLKSEL_IHRC 0 +#define WDT_CLKSEL_HCLK 1 +#define WDT_CLKSEL_ILRC 2 +#define WDT_CLKSEL_ELS 3 + +//Watchdog Feed value +#define mskWDT_FV 0x55AA + +/*_____ M A C R O S ________________________________________________________*/ +//Watchdog Feed Value +#define __WDT_FEED_VALUE (SN_WDT->FEED = (mskWDT_WDKEY | mskWDT_FV)) + +//WDT Enable/Disable +#define __WDT_ENABLE (SN_WDT->CFG |= (mskWDT_WDKEY | mskWDT_WDTEN_ENABLE)) +#define __WDT_DISABLE (SN_WDT->CFG = (mskWDT_WDKEY | (SN_WDT->CFG & ~mskWDT_WDTEN_ENABLE))) + +//WDT INT status register clear +#define __WDT_CLRINSTS (SN_WDT->CFG = (mskWDT_WDKEY | (SN_WDT->CFG & ~mskWDT_WDTINT))) + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +void WDT_Init(void); +void WDT_ReloadValue(uint32_t time); +void WDT_SelectClockSource(uint32_t src); +void WDT_NvicEnable(void); +void WDT_NvicDisable(void); +#endif /*__SN32F240_WDT_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/ADC/ADC.c b/os/hal/ports/SN32/LLD/SN32F2xx/ADC/ADC.c new file mode 100644 index 00000000..964a1f6c --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/ADC/ADC.c @@ -0,0 +1,128 @@ +/******************** (C) COPYRIGHT 2017 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2017/07 +* AUTHOR: SA1 +* IC: SN32F240B +* DESCRIPTION: ADC related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2017/07/07 SA1 First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include +#include "ADC.h" + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +uint8_t bADC_StartConv; + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + +/***************************************************************************** +* Function : ADC_Init +* Description : Initialization of ADC +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void ADC_Init(void) +{ + SN_SYS1->AHBCLKEN_b.ADCCLKEN = 1; //Enables HCLK for ADC + + SN_ADC->ADM_b.ADENB = ADC_ADENB_EN; //Enable ADC + + UT_DelayNx10us(10); //Delay 100us + + SN_ADC->ADM_b.AVREFHSEL = ADC_AVREFHSEL_INTERNAL; //Set ADC high reference voltage source from internal reference + + SN_ADC->ADM_b.VHS = ADC_VHS_VDD; //Set ADC high reference voltage source as VDD + + SN_ADC->ADM_b.GCHS = ADC_GCHS_EN; //Enable ADC global channel + + SN_ADC->ADM_b.ADLEN = ADC_ADLEN_12BIT; //Set ADC resolution = 12-bit + + SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV1; //ADC_CLK = ADC_PCLK/1 + //SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV2; //ADC_CLK = ADC_PCLK/2 + //SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV4; //ADC_CLK = ADC_PCLK/4 + //SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV8; //ADC_CLK = ADC_PCLK/8 + //SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV16; //ADC_CLK = ADC_PCLK/16 + //SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV32; //ADC_CLK = ADC_PCLK/32 + + SN_ADC->ADM_b.CHS = ADC_CHS_AIN1; //Set P2.1 as ADC input channel + + SN_ADC->IE |= ADC_IE_AIN1; //Enable ADC channel P2.1 interrupt + + ADC_NvicEnable(); //Enable ADC NVIC interrupt +} + +/***************************************************************************** +* Function : ADC_Read +* Description : Read ADC converted data +* Input : None +* Output : None +* Return : Data in ADB register +* Note : None +*****************************************************************************/ +uint16_t ADC_Read(void) +{ + return SN_ADC->ADB; +} + +/***************************************************************************** +* Function : ADC_IRQHandler +* Description : ISR of ADC interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void ADC_IRQHandler(void) +{ + bADC_StartConv = 0; + + SN_ADC->RIS = 0x0; //clear interrupt flag +} + +/***************************************************************************** +* Function : ADC_NvicEnable +* Description : Enable ADC interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void ADC_NvicEnable(void) +{ + NVIC_ClearPendingIRQ(ADC_IRQn); + NVIC_EnableIRQ(ADC_IRQn); + NVIC_SetPriority(ADC_IRQn,0); // Set interrupt priority (default) +} + +/***************************************************************************** +* Function : ADC_NvicDisable +* Description : Disable ADC interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void ADC_NvicDisable(void) +{ + NVIC_DisableIRQ(ADC_IRQn); +} diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/ADC/ADC.h b/os/hal/ports/SN32/LLD/SN32F2xx/ADC/ADC.h new file mode 100644 index 00000000..ef93536f --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/ADC/ADC.h @@ -0,0 +1,117 @@ +#ifndef __SN32F2XX_ADC_H +#define __SN32F2XX_ADC_H + +/*_____ I N C L U D E S ____________________________________________________*/ +#include + +/*_____ D E F I N I T I O N S ______________________________________________*/ +//ADC Internal Reference Voltage level +#define ADC_VHS_INTERNAL_2V 0 +#define ADC_VHS_INTERNAL_3V 1 +#define ADC_VHS_INTERNAL_4P5V 2 +#define ADC_VHS_VDD 7 + +//ADC high reference voltage source select bit +#define ADC_AVREFHSEL_INTERNAL 0x0 +#define ADC_AVREFHSEL_EXTERNAL 0x1 + +//ADC Enable bit +#define ADC_ADENB_DIS 0x0 +#define ADC_ADENB_EN 0x1 + +//ADC Clock source divider +#define ADC_ADCKS_DIV1 0x0 +#define ADC_ADCKS_DIV2 0x1 +#define ADC_ADCKS_DIV4 0x2 +#define ADC_ADCKS_DIV8 0x3 +#define ADC_ADCKS_DIV16 0x5 +#define ADC_ADCKS_DIV32 0x6 + +//ADC resolution control bit +#define ADC_ADLEN_8BIT 0x0 +#define ADC_ADLEN_12BIT 0x1 + +//ADC start control bit +#define ADC_ADS_STOP 0x0 +#define ADC_ADS_START 0x1 + +//ADC global channel select bit +#define ADC_GCHS_DIS 0x0 +#define ADC_GCHS_EN 0x1 + +//ADC input channels select bit +#define ADC_CHS_AIN0 0x0 //P2.0 +#define ADC_CHS_AIN1 0x1 //P2.1 +#define ADC_CHS_AIN2 0x2 //P2.2 +#define ADC_CHS_AIN3 0x3 //P2.3 +#define ADC_CHS_AIN4 0x4 //P2.4 +#define ADC_CHS_AIN5 0x5 //P2.5 +#define ADC_CHS_AIN6 0x6 //P2.6 +#define ADC_CHS_AIN7 0x7 //P2.7 +#define ADC_CHS_AIN8 0x8 //P2.8 +#define ADC_CHS_AIN9 0x9 //P2.9 +#define ADC_CHS_AIN10 0xA //P2.10 +#define ADC_CHS_AIN11 0xB //P2.11 +#define ADC_CHS_AIN12 0xC //P2.12 +#define ADC_CHS_AIN13 0xD //P2.13 +#define ADC_CHS_AIN14 0xE //P2.14 +#define ADC_CHS_AIN15 0xF //P2.15 +#define ADC_CHS_AIN16 0x10 //Internal Ref. Voltage +#define ADC_CHS_AIN17 0x11 //VDD +#define ADC_CHS_AIN18 0x12 //VSS + +//ADC Interrupt Enable register(ADC_IE) +#define ADC_IE_AIN0 0x00001 +#define ADC_IE_AIN1 0x00002 +#define ADC_IE_AIN2 0x00004 +#define ADC_IE_AIN3 0x00008 +#define ADC_IE_AIN4 0x00010 +#define ADC_IE_AIN5 0x00020 +#define ADC_IE_AIN6 0x00040 +#define ADC_IE_AIN7 0x00080 +#define ADC_IE_AIN8 0x00100 +#define ADC_IE_AIN9 0x00200 +#define ADC_IE_AIN10 0x00400 +#define ADC_IE_AIN11 0x00800 +#define ADC_IE_AIN12 0x01000 +#define ADC_IE_AIN13 0x02000 +#define ADC_IE_AIN14 0x04000 +#define ADC_IE_AIN15 0x08000 +#define ADC_IE_AIN16 0x10000 +#define ADC_IE_AIN17 0x20000 +#define ADC_IE_AIN18 0x40000 + +//ADC Raw Interrupt Status register(ADC_RIS) +#define mskADC_IF_AIN0 (0x1<<0) //P2.0 +#define mskADC_IF_AIN1 (0x1<<1) //P2.1 +#define mskADC_IF_AIN2 (0x1<<2) //P2.2 +#define mskADC_IF_AIN3 (0x1<<3) //P2.3 +#define mskADC_IF_AIN4 (0x1<<4) //P2.4 +#define mskADC_IF_AIN5 (0x1<<5) //P2.5 +#define mskADC_IF_AIN6 (0x1<<6) //P2.6 +#define mskADC_IF_AIN7 (0x1<<7) //P2.7 +#define mskADC_IF_AIN8 (0x1<<8) //P2.8 +#define mskADC_IF_AIN9 (0x1<<9) //P2.9 +#define mskADC_IF_AIN10 (0x1<<10) //P2.10 +#define mskADC_IF_AIN11 (0x1<<11) //P2.11 +#define mskADC_IF_AIN12 (0x1<<12) //P2.12 +#define mskADC_IF_AIN13 (0x1<<13) //P2.13 +#define mskADC_IF_AIN14 (0x1<<14) //P2.14 +#define mskADC_IF_AIN15 (0x1<<15) //P2.15 +#define mskADC_IF_AIN16 (0x1<<16) //Internal Ref. Voltage +#define mskADC_IF_AIN17 (0x1<<17) //VDD +#define mskADC_IF_AIN18 (0x1<<18) //VSS + +/*_____ M A C R O S ________________________________________________________*/ + + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +extern uint8_t bADC_StartConv; + +void ADC_Init(void); +uint16_t ADC_Read(void); +void ADC_NvicEnable(void); +void ADC_NvicDisable(void); + +#endif /*__SN32F2XX_ADC_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16.h b/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16.h new file mode 100644 index 00000000..4eb6f04f --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16.h @@ -0,0 +1,1331 @@ +#ifndef __SN32F2XX_CT16_H +#define __SN32F2XX_CT16_H + + +/*_____ I N C L U D E S ____________________________________________________*/ +#include + +/*_____ D E F I N I T I O N S ______________________________________________*/ +/* +Base Address: 0x4000 0000 (CT16B0) + 0x4000 2000 (CT16B1) + 0x4000 4000 (CT16B2) +*/ + +/* CT16Bn Timer Control register (0x00) */ +#define CT16_CEN_DIS 0 //[0:0] CT16Bn enable bit +#define CT16_CEN_EN 1 +#define mskCT16_CEN_DIS (CT16_CEN_DIS<<0) +#define mskCT16_CEN_EN (CT16_CEN_EN<<0) + +#define CT16_CRST 1 //[1:1] CT16Bn counter reset bit +#define mskCT16_CRST (CT16_CRST<<1) + + //[6:4] CT16Bn counting mode selection +#define CT16_CM_EDGE_UP 0 //Edge-aligned Up-counting mode +#define CT16_CM_EDGE_DOWN 1 //Edge-aligned Down-counting mode +#define CT16_CM_CENTER_UP 2 //Center-aligned mode 1. Match interrupt is set during up-counting period +#define CT16_CM_CENTER_DOWN 4 //Center-aligned mode 2. Match interrupt is set during down-counting period +#define CT16_CM_CENTER_BOTH 6 //Center-aligned mode 3. Match interrupt is set during both up and down period. +#define mskCT16_CM_EDGE_UP (CT16_CM_EDGE_UP<<4) +#define mskCT16_CM_EDGE_DOWN (CT16_CM_EDGE_DOWN<<4) +#define mskCT16_CM_CENTER_UP (CT16_CM_CENTER_UP<<4) +#define mskCT16_CM_CENTER_DOWN (CT16_CM_CENTER_DOWN<<4) +#define mskCT16_CM_CENTER_BOTH (CT16_CM_CENTER_BOTH<<4) + +/* CT16Bn Count Control register (0x10) */ + //[1:0] Count/Timer Mode selection. +#define CT16_CTM_TIMER 0 //Timer mode: Every rising PCLK edge. +#define CT16_CTM_CNTER_RISING 1 //Counter mode: TC increments on rising edge of CAP input. +#define CT16_CTM_CNTER_FALLING 2 //Counter mode: TC increments on falling edge of CAP input. +#define CT16_CTM_CNTER_BOTH 3 //Counter mode: TC increments on both edge of CAP input. +#define mskCT16_CTM_TIMER (CT16_CTM_TIMER<<0) +#define mskCT16_CTM_CNTER_RISING (CT16_CTM_CNTER_RISING<<0) +#define mskCT16_CTM_CNTER_FALLING (CT16_CTM_CNTER_FALLING<<0) +#define mskCT16_CTM_CNTER_BOTH (CT16_CTM_CNTER_BOTH<<0) + +#define CT16_CIS 0 //[3:2] Count Input Select +#define mskCT16_CIS (CT16_CIS<<2) + +/* CT16Bn Match Control register (0x14) */ +#define CT16_MR0IE_EN 1 //[0:0] Enable MR0 match interrupt +#define CT16_MR0IE_DIS 0 +#define mskCT16_MR0IE_EN (CT16_MR0IE_EN<<0) +#define mskCT16_MR0IE_DIS (CT16_MR0IE_DIS<<0) + +#define CT16_MR0RST_EN 1 //[1:1] Enable reset TC when MR0 matches TC. +#define CT16_MR0RST_DIS 0 +#define mskCT16_MR0RST_EN (CT16_MR0RST_EN<<1) +#define mskCT16_MR0RST_DIS (CT16_MR0RST_DIS<<1) + +#define CT16_MR0STOP_EN 1 //[2:2] Enable stop TC and clear CEN when MR0 matches TC. +#define CT16_MR0STOP_DIS 0 +#define mskCT16_MR0STOP_EN (CT16_MR0STOP_EN<<2) +#define mskCT16_MR0STOP_DIS (CT16_MR0STOP_DIS<<2) + +#define CT16_MR1IE_EN 1 //[3:3] Enable MR1 match interrupt +#define CT16_MR1IE_DIS 0 +#define mskCT16_MR1IE_EN (CT16_MR1IE_EN<<3) +#define mskCT16_MR1IE_DIS (CT16_MR1IE_DIS<<3) + +#define CT16_MR1RST_EN 1 //[4:4] Enable reset TC when MR1 matches TC. +#define CT16_MR1RST_DIS 0 +#define mskCT16_MR1RST_EN (CT16_MR1RST_EN<<4) +#define mskCT16_MR1RST_DIS (CT16_MR1RST_DIS<<4) + +#define CT16_MR1STOP_EN 1 //[5:5] Enable stop TC and clear CEN when MR1 matches TC. +#define CT16_MR1STOP_DIS 0 +#define mskCT16_MR1STOP_EN (CT16_MR1STOP_EN<<5) +#define mskCT16_MR1STOP_DIS (CT16_MR1STOP_DIS<<5) + +#define CT16_MR2IE_EN 1 //[6:6] Enable MR2 match interrupt +#define CT16_MR2IE_DIS 0 +#define mskCT16_MR2IE_EN (CT16_MR2IE_EN<<6) +#define mskCT16_MR2IE_DIS (CT16_MR2IE_DIS<<6) + +#define CT16_MR2RST_EN 1 //[7:7] Enable reset TC when MR2 matches TC. +#define CT16_MR2RST_DIS 0 +#define mskCT16_MR2RST_EN (CT16_MR2RST_EN<<7) +#define mskCT16_MR2RST_DIS (CT16_MR2RST_DIS<<7) + +#define CT16_MR2STOP_EN 1 //[8:8] Enable stop TC and clear CEN when MR2 matches TC. +#define CT16_MR2STOP_DIS 0 +#define mskCT16_MR2STOP_EN (CT16_MR2STOP_EN<<8) +#define mskCT16_MR2STOP_DIS (CT16_MR2STOP_DIS<<8) + +#define CT16_MR3IE_EN 1 //[9:9] Enable MR3 match interrupt +#define CT16_MR3IE_DIS 0 +#define mskCT16_MR3IE_EN (CT16_MR3IE_EN<<9) +#define mskCT16_MR3IE_DIS (CT16_MR3IE_DIS<<9) + +#define CT16_MR3RST_EN 1 //[10:10] Enable reset TC when MR3 matches TC. +#define CT16_MR3RST_DIS 0 +#define mskCT16_MR3RST_EN (CT16_MR3RST_EN<<10) +#define mskCT16_MR3RST_DIS (CT16_MR3RST_DIS<<10) + +#define CT16_MR3STOP_EN 1 //[11:11] Enable stop TC and clear CEN when MR3 matches TC. +#define CT16_MR3STOP_DIS 0 +#define mskCT16_MR3STOP_EN (CT16_MR3STOP_EN<<11) +#define mskCT16_MR3STOP_DIS (CT16_MR3STOP_DIS<<11) + +#define CT16_MR4IE_EN 1 //[12:12 Enable MR4 match interrupt +#define CT16_MR4IE_DIS 0 +#define mskCT16_MR4IE_EN (CT16_MR4IE_EN<<12) +#define mskCT16_MR4IE_DIS (CT16_MR4IE_DIS<<12) + +#define CT16_MR4RST_EN 1 //[13:13] Enable reset TC when MR4 matches TC. +#define CT16_MR4RST_DIS 0 +#define mskCT16_MR4RST_EN (CT16_MR4RST_EN<<13) +#define mskCT16_MR4RST_DIS (CT16_MR4RST_DIS<<13) + +#define CT16_MR4STOP_EN 1 //[14:14] Enable stop TC and clear CEN when MR4 matches TC. +#define CT16_MR4STOP_DIS 0 +#define mskCT16_MR4STOP_EN (CT16_MR4STOP_EN<<14) +#define mskCT16_MR4STOP_DIS (CT16_MR4STOP_DIS<<14) + +#define CT16_MR5IE_EN 1 //[15:15] Enable MR5 match interrupt +#define CT16_MR5IE_DIS 0 +#define mskCT16_MR5IE_EN (CT16_MR5IE_EN<<15) +#define mskCT16_MR5IE_DIS (CT16_MR5IE_DIS<<15) + +#define CT16_MR5RST_EN 1 //[16:16] Enable reset TC when MR5 matches TC. +#define CT16_MR5RST_DIS 0 +#define mskCT16_MR5RST_EN (CT16_MR5RST_EN<<16) +#define mskCT16_MR5RST_DIS (CT16_MR5RST_DIS<<16) + +#define CT16_MR5STOP_EN 1 //[17:17] Enable stop TC and clear CEN when MR5 matches TC. +#define CT16_MR5STOP_DIS 0 +#define mskCT16_MR5STOP_EN (CT16_MR5STOP_EN<<17) +#define mskCT16_MR5STOP_DIS (CT16_MR5STOP_DIS<<17) + +#define CT16_MR6IE_EN 1 //[18:18 Enable MR6 match interrupt +#define CT16_MR6IE_DIS 0 +#define mskCT16_MR6IE_EN (CT16_MR6IE_EN<<18) +#define mskCT16_MR6IE_DIS (CT16_MR6IE_DIS<<18) + +#define CT16_MR6RST_EN 1 //[19:19] Enable reset TC when MR6 matches TC. +#define CT16_MR6RST_DIS 0 +#define mskCT16_MR6RST_EN (CT16_MR6RST_EN<<19) +#define mskCT16_MR6RST_DIS (CT16_MR6RST_DIS<<19) + +#define CT16_MR6STOP_EN 1 //[20:20] Enable stop TC and clear CEN when MR6 matches TC. +#define CT16_MR6STOP_DIS 0 +#define mskCT16_MR6STOP_EN (CT16_MR6STOP_EN<<20) +#define mskCT16_MR6STOP_DIS (CT16_MR6STOP_DIS<<20) + +#define CT16_MR7IE_EN 1 //[21:21 Enable MR7 match interrupt +#define CT16_MR7IE_DIS 0 +#define mskCT16_MR7IE_EN (CT16_MR7IE_EN<<21) +#define mskCT16_MR7IE_DIS (CT16_MR7IE_DIS<<21) + +#define CT16_MR7RST_EN 1 //[22:22] Enable reset TC when MR7 matches TC. +#define CT16_MR7RST_DIS 0 +#define mskCT16_MR7RST_EN (CT16_MR7RST_EN<<22) +#define mskCT16_MR7RST_DIS (CT16_MR7RST_DIS<<22) + +#define CT16_MR7STOP_EN 1 //[23:23] Enable stop TC and clear CEN when MR7 matches TC. +#define CT16_MR7STOP_DIS 0 +#define mskCT16_MR7STOP_EN (CT16_MR7STOP_EN<<23) +#define mskCT16_MR7STOP_DIS (CT16_MR7STOP_DIS<<23) + +#define CT16_MR8IE_EN 1 //[24:24 Enable MR8 match interrupt +#define CT16_MR8IE_DIS 0 +#define mskCT16_MR8IE_EN (CT16_MR8IE_EN<<24) +#define mskCT16_MR8IE_DIS (CT16_MR8IE_DIS<<24) + +#define CT16_MR8RST_EN 1 //[25:25] Enable reset TC when MR8 matches TC. +#define CT16_MR8RST_DIS 0 +#define mskCT16_MR8RST_EN (CT16_MR8RST_EN<<25) +#define mskCT16_MR8RST_DIS (CT16_MR8RST_DIS<<25) + +#define CT16_MR8STOP_EN 1 //[26:26] Enable stop TC and clear CEN when MR8 matches TC. +#define CT16_MR8STOP_DIS 0 +#define mskCT16_MR8STOP_EN (CT16_MR8STOP_EN<<26) +#define mskCT16_MR8STOP_DIS (CT16_MR8STOP_DIS<<26) + +#define CT16_MR9IE_EN 1 //[27:27] Enable MR9 match interrupt +#define CT16_MR9IE_DIS 0 +#define mskCT16_MR9IE_EN (CT16_MR9IE_EN<<27) +#define mskCT16_MR9IE_DIS (CT16_MR9IE_DIS<<27) + +#define CT16_MR9RST_EN 1 //[28:28] Enable reset TC when MR9 matches TC. +#define CT16_MR9RST_DIS 0 +#define mskCT16_MR9RST_EN (CT16_MR9RST_EN<<28) +#define mskCT16_MR9RST_DIS (CT16_MR9RST_DIS<<28) + +#define CT16_MR9STOP_EN 1 //[29:29] Enable stop TC and clear CEN when MR9 matches TC. +#define CT16_MR9STOP_DIS 0 +#define mskCT16_MR9STOP_EN (CT16_MR9STOP_EN<<29) +#define mskCT16_MR9STOP_DIS (CT16_MR9STOP_DIS<<29) + +/* CT16Bn Match Control register 2 (0x18) */ +#define CT16_MR10IE_EN 1 //[0:0] Enable MR10 match interrupt +#define CT16_MR10IE_DIS 0 +#define mskCT16_MR10IE_EN (CT16_MR10IE_EN<<0) +#define mskCT16_MR10IE_DIS (CT16_MR10IE_DIS<<0) + +#define CT16_MR10RST_EN 1 //[1:1] Enable reset TC when MR10 matches TC. +#define CT16_MR10RST_DIS 0 +#define mskCT16_MR10RST_EN (CT16_MR10RST_EN<<1) +#define mskCT16_MR10RST_DIS (CT16_MR10RST_DIS<<1) + +#define CT16_MR10STOP_EN 1 //[2:2] Enable stop TC and clear CEN when MR10 matches TC. +#define CT16_MR10STOP_DIS 0 +#define mskCT16_MR10STOP_EN (CT16_MR10STOP_EN<<2) +#define mskCT16_MR10STOP_DIS (CT16_MR10STOP_DIS<<2) + +#define CT16_MR11IE_EN 1 //[3:3] Enable MR11 match interrupt +#define CT16_MR11IE_DIS 0 +#define mskCT16_MR11IE_EN (CT16_MR11IE_EN<<3) +#define mskCT16_MR11IE_DIS (CT16_MR11IE_DIS<<3) + +#define CT16_MR11RST_EN 1 //[4:4] Enable reset TC when MR11 matches TC. +#define CT16_MR11RST_DIS 0 +#define mskCT16_MR11RST_EN (CT16_MR11RST_EN<<4) +#define mskCT16_MR11RST_DIS (CT16_MR11RST_DIS<<4) + +#define CT16_MR11STOP_EN 1 //[5:5] Enable stop TC and clear CEN when MR11 matches TC. +#define CT16_MR11STOP_DIS 0 +#define mskCT16_MR11STOP_EN (CT16_MR11STOP_EN<<5) +#define mskCT16_MR11STOP_DIS (CT16_MR11STOP_DIS<<5) + +#define CT16_MR12IE_EN 1 //[6:6] Enable MR12 match interrupt +#define CT16_MR12IE_DIS 0 +#define mskCT16_MR12IE_EN (CT16_MR12IE_EN<<6) +#define mskCT16_MR12IE_DIS (CT16_MR12IE_DIS<<6) + +#define CT16_MR12RST_EN 1 //[7:7] Enable reset TC when MR12 matches TC. +#define CT16_MR12RST_DIS 0 +#define mskCT16_MR12RST_EN (CT16_MR12RST_EN<<7) +#define mskCT16_MR12RST_DIS (CT16_MR12RST_DIS<<7) + +#define CT16_MR12STOP_EN 1 //[8:8] Enable stop TC and clear CEN when MR12 matches TC. +#define CT16_MR12STOP_DIS 0 +#define mskCT16_MR12STOP_EN (CT16_MR12STOP_EN<<8) +#define mskCT16_MR12STOP_DIS (CT16_MR12STOP_DIS<<8) + +#define CT16_MR13IE_EN 1 //[9:9] Enable MR13 match interrupt +#define CT16_MR13IE_DIS 0 +#define mskCT16_MR13IE_EN (CT16_MR13IE_EN<<9) +#define mskCT16_MR13IE_DIS (CT16_MR13IE_DIS<<9) + +#define CT16_MR13RST_EN 1 //[10:10] Enable reset TC when MR13 matches TC. +#define CT16_MR13RST_DIS 0 +#define mskCT16_MR13RST_EN (CT16_MR13RST_EN<<10) +#define mskCT16_MR13RST_DIS (CT16_MR13RST_DIS<<10) + +#define CT16_MR13STOP_EN 1 //[11:11] Enable stop TC and clear CEN when MR13 matches TC. +#define CT16_MR13STOP_DIS 0 +#define mskCT16_MR13STOP_EN (CT16_MR13STOP_EN<<11) +#define mskCT16_MR13STOP_DIS (CT16_MR13STOP_DIS<<11) + +#define CT16_MR14IE_EN 1 //[12:12 Enable MR14 match interrupt +#define CT16_MR14IE_DIS 0 +#define mskCT16_MR14IE_EN (CT16_MR14IE_EN<<12) +#define mskCT16_MR14IE_DIS (CT16_MR14IE_DIS<<12) + +#define CT16_MR14RST_EN 1 //[13:13] Enable reset TC when MR14 matches TC. +#define CT16_MR14RST_DIS 0 +#define mskCT16_MR14RST_EN (CT16_MR14RST_EN<<13) +#define mskCT16_MR14RST_DIS (CT16_MR14RST_DIS<<13) + +#define CT16_MR14STOP_EN 1 //[14:14] Enable stop TC and clear CEN when MR14 matches TC. +#define CT16_MR14STOP_DIS 0 +#define mskCT16_MR14STOP_EN (CT16_MR14STOP_EN<<14) +#define mskCT16_MR14STOP_DIS (CT16_MR14STOP_DIS<<14) + +#define CT16_MR15IE_EN 1 //[15:15 Enable MR15 match interrupt +#define CT16_MR15IE_DIS 0 +#define mskCT16_MR15IE_EN (CT16_MR15IE_EN<<15) +#define mskCT16_MR15IE_DIS (CT16_MR15IE_DIS<<15) + +#define CT16_MR15RST_EN 1 //[16:16] Enable reset TC when MR15 matches TC. +#define CT16_MR15RST_DIS 0 +#define mskCT16_MR15RST_EN (CT16_MR15RST_EN<<16) +#define mskCT16_MR15RST_DIS (CT16_MR15RST_DIS<<16) + +#define CT16_MR15STOP_EN 1 //[17:17] Enable stop TC and clear CEN when MR15 matches TC. +#define CT16_MR15STOP_DIS 0 +#define mskCT16_MR15STOP_EN (CT16_MR15STOP_EN<<17) +#define mskCT16_MR15STOP_DIS (CT16_MR15STOP_DIS<<17) + +#define CT16_MR16IE_EN 1 //[18:18 Enable MR16 match interrupt +#define CT16_MR16IE_DIS 0 +#define mskCT16_MR16IE_EN (CT16_MR16IE_EN<<18) +#define mskCT16_MR16IE_DIS (CT16_MR16IE_DIS<<18) + +#define CT16_MR16RST_EN 1 //[19:19] Enable reset TC when MR16 matches TC. +#define CT16_MR16RST_DIS 0 +#define mskCT16_MR16RST_EN (CT16_MR16RST_EN<<19) +#define mskCT16_MR16RST_DIS (CT16_MR16RST_DIS<<19) + +#define CT16_MR16STOP_EN 1 //[20:20] Enable stop TC and clear CEN when MR16 matches TC. +#define CT16_MR16STOP_DIS 0 +#define mskCT16_MR16STOP_EN (CT16_MR16STOP_EN<<20) +#define mskCT16_MR16STOP_DIS (CT16_MR16STOP_DIS<<20) + +#define CT16_MR17IE_EN 1 //[21:21 Enable MR17 match interrupt +#define CT16_MR17IE_DIS 0 +#define mskCT16_MR17IE_EN (CT16_MR17IE_EN<<21) +#define mskCT16_MR17IE_DIS (CT16_MR17IE_DIS<<21) + +#define CT16_MR17RST_EN 1 //[22:22] Enable reset TC when MR17 matches TC. +#define CT16_MR17RST_DIS 0 +#define mskCT16_MR17RST_EN (CT16_MR17RST_EN<<22) +#define mskCT16_MR17RST_DIS (CT16_MR17RST_DIS<<22) + +#define CT16_MR17STOP_EN 1 //[23:23] Enable stop TC and clear CEN when MR17 matches TC. +#define CT16_MR17STOP_DIS 0 +#define mskCT16_MR17STOP_EN (CT16_MR17STOP_EN<<23) +#define mskCT16_MR17STOP_DIS (CT16_MR17STOP_DIS<<23) + +#define CT16_MR18IE_EN 1 //[24:24 Enable MR18 match interrupt +#define CT16_MR18IE_DIS 0 +#define mskCT16_MR18IE_EN (CT16_MR18IE_EN<<24) +#define mskCT16_MR18IE_DIS (CT16_MR18IE_DIS<<24) + +#define CT16_MR18RST_EN 1 //[25:25] Enable reset TC when MR18 matches TC. +#define CT16_MR18RST_DIS 0 +#define mskCT16_MR18RST_EN (CT16_MR18RST_EN<<25) +#define mskCT16_MR18RST_DIS (CT16_MR18RST_DIS<<25) + +#define CT16_MR18STOP_EN 1 //[26:26] Enable stop TC and clear CEN when MR18 matches TC. +#define CT16_MR18STOP_DIS 0 +#define mskCT16_MR18STOP_EN (CT16_MR18STOP_EN<<26) +#define mskCT16_MR18STOP_DIS (CT16_MR18STOP_DIS<<26) + +#define CT16_MR19IE_EN 1 //[27:27] Enable MR19 match interrupt +#define CT16_MR19IE_DIS 0 +#define mskCT16_MR19IE_EN (CT16_MR19IE_EN<<27) +#define mskCT16_MR19IE_DIS (CT16_MR19IE_DIS<<27) + +#define CT16_MR19RST_EN 1 //[28:28] Enable reset TC when MR19 matches TC. +#define CT16_MR19RST_DIS 0 +#define mskCT16_MR19RST_EN (CT16_MR19RST_EN<<28) +#define mskCT16_MR19RST_DIS (CT16_MR19RST_DIS<<28) + +#define CT16_MR19STOP_EN 1 //[29:29] Enable stop TC and clear CEN when MR19 matches TC. +#define CT16_MR19STOP_DIS 0 +#define mskCT16_MR19STOP_EN (CT16_MR19STOP_EN<<29) +#define mskCT16_MR19STOP_DIS (CT16_MR19STOP_DIS<<29) + +/* CT16Bn Match Control register 3 (0x1C) */ +#define CT16_MR20IE_EN 1 //[0:0] Enable MR20 match interrupt +#define CT16_MR20IE_DIS 0 +#define mskCT16_MR20IE_EN (CT16_MR20IE_EN<<0) +#define mskCT16_MR20IE_DIS (CT16_MR20IE_DIS<<0) + +#define CT16_MR20RST_EN 1 //[1:1] Enable reset TC when MR20 matches TC. +#define CT16_MR20RST_DIS 0 +#define mskCT16_MR20RST_EN (CT16_MR20RST_EN<<1) +#define mskCT16_MR20RST_DIS (CT16_MR20RST_DIS<<1) + +#define CT16_MR20STOP_EN 1 //[2:2] Enable stop TC and clear CEN when MR20 matches TC. +#define CT16_MR20STOP_DIS 0 +#define mskCT16_MR20STOP_EN (CT16_MR20STOP_EN<<2) +#define mskCT16_MR20STOP_DIS (CT16_MR20STOP_DIS<<2) + +#define CT16_MR21IE_EN 1 //[3:3] Enable MR21 match interrupt +#define CT16_MR21IE_DIS 0 +#define mskCT16_MR21IE_EN (CT16_MR21IE_EN<<3) +#define mskCT16_MR21IE_DIS (CT16_MR21IE_DIS<<3) + +#define CT16_MR21RST_EN 1 //[4:4] Enable reset TC when MR21 matches TC. +#define CT16_MR21RST_DIS 0 +#define mskCT16_MR21RST_EN (CT16_MR21RST_EN<<4) +#define mskCT16_MR21RST_DIS (CT16_MR21RST_DIS<<4) + +#define CT16_MR21STOP_EN 1 //[5:5] Enable stop TC and clear CEN when MR21 matches TC. +#define CT16_MR21STOP_DIS 0 +#define mskCT16_MR21STOP_EN (CT16_MR21STOP_EN<<5) +#define mskCT16_MR21STOP_DIS (CT16_MR21STOP_DIS<<5) + +#define CT16_MR22IE_EN 1 //[6:6] Enable MR22 match interrupt +#define CT16_MR22IE_DIS 0 +#define mskCT16_MR22IE_EN (CT16_MR22IE_EN<<6) +#define mskCT16_MR22IE_DIS (CT16_MR22IE_DIS<<6) + +#define CT16_MR22RST_EN 1 //[7:7] Enable reset TC when MR22 matches TC. +#define CT16_MR22RST_DIS 0 +#define mskCT16_MR22RST_EN (CT16_MR22RST_EN<<7) +#define mskCT16_MR22RST_DIS (CT16_MR22RST_DIS<<7) + +#define CT16_MR22STOP_EN 1 //[8:8] Enable stop TC and clear CEN when MR22 matches TC. +#define CT16_MR22STOP_DIS 0 +#define mskCT16_MR22STOP_EN (CT16_MR22STOP_EN<<8) +#define mskCT16_MR22STOP_DIS (CT16_MR22STOP_DIS<<8) + +#define CT16_MR23IE_EN 1 //[9:9] Enable MR23 match interrupt +#define CT16_MR23IE_DIS 0 +#define mskCT16_MR23IE_EN (CT16_MR23IE_EN<<9) +#define mskCT16_MR23IE_DIS (CT16_MR23IE_DIS<<9) + +#define CT16_MR23RST_EN 1 //[10:10] Enable reset TC when MR23 matches TC. +#define CT16_MR23RST_DIS 0 +#define mskCT16_MR23RST_EN (CT16_MR23RST_EN<<10) +#define mskCT16_MR23RST_DIS (CT16_MR23RST_DIS<<10) + +#define CT16_MR23STOP_EN 1 //[11:11] Enable stop TC and clear CEN when MR23 matches TC. +#define CT16_MR23STOP_DIS 0 +#define mskCT16_MR23STOP_EN (CT16_MR23STOP_EN<<11) +#define mskCT16_MR23STOP_DIS (CT16_MR23STOP_DIS<<11) + +#define CT16_MR24IE_EN 1 //[12:12] Enable MR24 match interrupt +#define CT16_MR24IE_DIS 0 +#define mskCT16_MR24IE_EN (CT16_MR24IE_EN<<12) +#define mskCT16_MR24IE_DIS (CT16_MR24IE_DIS<<12) + +#define CT16_MR24RST_EN 1 //[13:13] Enable reset TC when MR24 matches TC. +#define CT16_MR24RST_DIS 0 +#define mskCT16_MR24RST_EN (CT16_MR24RST_EN<<13) +#define mskCT16_MR24RST_DIS (CT16_MR24RST_DIS<<13) + +#define CT16_MR24STOP_EN 1 //[14:14] Enable stop TC and clear CEN when MR24 matches TC. +#define CT16_MR24STOP_DIS 0 +#define mskCT16_MR24STOP_EN (CT16_MR24STOP_EN<<14) +#define mskCT16_MR24STOP_DIS (CT16_MR24STOP_DIS<<14) + +/* CT16Bn Capture Control register (0x80) */ +#define CT16_CAP0RE_EN 1 //[0:0] Enable CAP0 capture on rising edge. +#define CT16_CAP0RE_DIS 0 +#define mskCT16_CAP0RE_EN (CT16_CAP0RE_EN<<0) +#define mskCT16_CAP0RE_DIS (CT16_CAP0RE_DIS<<0) + +#define CT16_CAP0FE_EN 1 //[1:1] Enable CAP0 capture on fallng edge. +#define CT16_CAP0FE_DIS 0 +#define mskCT16_CAP0FE_EN (CT16_CAP0FE_EN<<1) +#define mskCT16_CAP0FE_DIS (CT16_CAP0FE_DIS<<1) + +#define CT16_CAP0IE_EN 1 //[2:2] Enable CAP0 interrupt. +#define CT16_CAP0IE_DIS 0 +#define mskCT16_CAP0IE_EN (CT16_CAP0IE_EN<<2) +#define mskCT16_CAP0IE_DIS (CT16_CAP0IE_DIS<<2) + +#define CT16_CAP0EN_EN 1 //[3:3] Enable CAP0 function. +#define CT16_CAP0EN_DIS 0 +#define mskCT16_CAP0EN_EN (CT16_CAP0EN_EN<<3) +#define mskCT16_CAP0EN_DIS (CT16_CAP0EN_DIS<<3) + +/* CT16Bn External Match register (0x88) */ +#define CT16_EM0 1 //[0:0] CT16Bn PWM0 drive state +#define mskCT16_EM0 (CT16_EM0<<0) +#define CT16_EM1 1 //[1:1] CT16Bn PWM1 drive state +#define mskCT16_EM1 (CT16_EM1<<1) +#define CT16_EM2 1 //[2:2] CT16Bn PWM2 drive state +#define mskCT16_EM2 (CT16_EM2<<2) +#define CT16_EM3 1 //[3:3] CT16Bn PWM3 drive state +#define mskCT16_EM3 (CT16_EM3<<3) +#define CT16_EM4 1 //[4:4] CT16Bn PWM4 drive state +#define mskCT16_EM4 (CT16_EM4<<4) +#define CT16_EM5 1 //[5:5] CT16Bn PWM5 drive state +#define mskCT16_EM5 (CT16_EM5<<5) +#define CT16_EM6 1 //[6:6] CT16Bn PWM6 drive state +#define mskCT16_EM6 (CT16_EM6<<6) +#define CT16_EM7 1 //[7:7] CT16Bn PWM7 drive state +#define mskCT16_EM7 (CT16_EM7<<7) +#define CT16_EM8 1 //[8:8] CT16Bn PWM8 drive state +#define mskCT16_EM8 (CT16_EM8<<8) +#define CT16_EM9 1 //[9:9] CT16Bn PWM9 drive state +#define mskCT16_EM9 (CT16_EM9<<9) +#define CT16_EM10 1 //[10:10] CT16Bn PWM10 drive state +#define mskCT16_EM10 (CT16_EM0<<10) +#define CT16_EM11 1 //[11:11] CT16Bn PWM11 drive state +#define mskCT16_EM11 (CT16_EM11<<11) +#define CT16_EM12 1 //[12:12] CT16Bn PWM12 drive state +#define mskCT16_EM12 (CT16_EM12<<12) +#define CT16_EM13 1 //[13:13] CT16Bn PWM13 drive state +#define mskCT16_EM13 (CT16_EM13<<13) +#define CT16_EM14 1 //[14:14] CT16Bn PWM14 drive state +#define mskCT16_EM14 (CT16_EM14<<14) +#define CT16_EM15 1 //[15:15] CT16Bn PWM15 drive state +#define mskCT16_EM15 (CT16_EM15<<15) +#define CT16_EM16 1 //[16:16] CT16Bn PWM16 drive state +#define mskCT16_EM16 (CT16_EM16<<16) +#define CT16_EM17 1 //[17:17] CT16Bn PWM17 drive state +#define mskCT16_EM17 (CT16_EM17<<17) +#define CT16_EM18 1 //[18:18] CT16Bn PWM18 drive state +#define mskCT16_EM18 (CT16_EM18<<8) +#define CT16_EM19 1 //[19:19] CT16Bn PWM19 drive state +#define mskCT16_EM19 (CT16_EM19<<19) +#define CT16_EM20 1 //[20:20] CT16Bn PWM20 drive state +#define mskCT16_EM20 (CT16_EM20<<20) +#define CT16_EM21 1 //[21:21] CT16Bn PWM21 drive state +#define mskCT16_EM21 (CT16_EM21<<21) +#define CT16_EM22 1 //[22:22] CT16Bn PWM22 drive state +#define mskCT16_EM22 (CT16_EM22<<22) +#define CT16_EM23 1 //[23:23] CT16Bn PWM23 drive state +#define mskCT16_EM23 (CT16_EM23<<23) + +/* CT16Bn External Match Control register (0x8C) */ + //[1:0]CT16Bn PWM0 functionality +#define CT16_EMC0_DO_NOTHING 0 //Do nothing. +#define CT16_EMC0_LOW 1 //CT16Bn PWM0 pin is low. +#define CT16_EMC0_HIGH 2 //CT16Bn PWM0 pin is high. +#define CT16_EMC0_TOGGLE 3 //Toggle CT16Bn PWM0 pin. +#define mskCT16_EMC0_DO_NOTHING (CT16_EMC0_LOW<<0) +#define mskCT16_EMC0_LOW (CT16_EMC0_LOW<<0) +#define mskCT16_EMC0_HIGH (CT16_EMC0_HIGH<<0) +#define mskCT16_EMC0_TOGGLE (CT16_EMC0_TOGGLE<<0) + + //[3:2]CT16Bn PWM1 functionality +#define CT16_EMC1_DO_NOTHING 0 //Do nothing. +#define CT16_EMC1_LOW 1 //CT16Bn PWM1 pin is low. +#define CT16_EMC1_HIGH 2 //CT16Bn PWM1 pin is high. +#define CT16_EMC1_TOGGLE 3 //Toggle CT16Bn PWM1 pin. +#define mskCT16_EMC1_DO_NOTHING (CT16_EMC1_LOW<<2) +#define mskCT16_EMC1_LOW (CT16_EMC1_LOW<<2) +#define mskCT16_EMC1_HIGH (CT16_EMC1_HIGH<<2) +#define mskCT16_EMC1_TOGGLE (CT16_EMC1_TOGGLE<<2) + + //[5:4]CT16Bn PWM2 functionality +#define CT16_EMC2_DO_NOTHING 0 //Do nothing. +#define CT16_EMC2_LOW 1 //CT16Bn PWM2 pin is low. +#define CT16_EMC2_HIGH 2 //CT16Bn PWM2 pin is high. +#define CT16_EMC2_TOGGLE 3 //Toggle CT16Bn PWM2 pin. +#define mskCT16_EMC2_DO_NOTHING (CT16_EMC2_LOW<<4) +#define mskCT16_EMC2_LOW (CT16_EMC2_LOW<<4) +#define mskCT16_EMC2_HIGH (CT16_EMC2_HIGH<<4) +#define mskCT16_EMC2_TOGGLE (CT16_EMC2_TOGGLE<<4) + + //[7:6]CT16Bn PWM3 functionality +#define CT16_EMC3_DO_NOTHING 0 //Do nothing. +#define CT16_EMC3_LOW 1 //CT16Bn PWM3 pin is low. +#define CT16_EMC3_HIGH 2 //CT16Bn PWM3 pin is high. +#define CT16_EMC3_TOGGLE 3 //Toggle CT16Bn PWM3 pin. +#define mskCT16_EMC3_DO_NOTHING (CT16_EMC3_LOW<<6) +#define mskCT16_EMC3_LOW (CT16_EMC3_LOW<<6) +#define mskCT16_EMC3_HIGH (CT16_EMC3_HIGH<<6) +#define mskCT16_EMC3_TOGGLE (CT16_EMC3_TOGGLE<<6) + + //[9:8]CT16Bn PWM4 functionality +#define CT16_EMC4_DO_NOTHING 0 //Do nothing. +#define CT16_EMC4_LOW 1 //CT16Bn PWM4 pin is low. +#define CT16_EMC4_HIGH 2 //CT16Bn PWM4 pin is high. +#define CT16_EMC4_TOGGLE 3 //Toggle CT16Bn PWM4 pin. +#define mskCT16_EMC4_DO_NOTHING (CT16_EMC4_LOW<<8) +#define mskCT16_EMC4_LOW (CT16_EMC4_LOW<<8) +#define mskCT16_EMC4_HIGH (CT16_EMC4_HIGH<<8) +#define mskCT16_EMC4_TOGGLE (CT16_EMC4_TOGGLE<<8) + + //[11:10]CT16Bn PWM5 functionality +#define CT16_EMC5_DO_NOTHING 0 //Do nothing. +#define CT16_EMC5_LOW 1 //CT16Bn PWM5 pin is low. +#define CT16_EMC5_HIGH 2 //CT16Bn PWM5 pin is high. +#define CT16_EMC5_TOGGLE 3 //Toggle CT16Bn PWM5 pin. +#define mskCT16_EMC5_DO_NOTHING (CT16_EMC5_LOW<<10) +#define mskCT16_EMC5_LOW (CT16_EMC5_LOW<<10) +#define mskCT16_EMC5_HIGH (CT16_EMC5_HIGH<<10) +#define mskCT16_EMC5_TOGGLE (CT16_EMC5_TOGGLE<<10) + + //[13:12]CT16Bn PWM6 functionality +#define CT16_EMC6_DO_NOTHING 0 //Do nothing. +#define CT16_EMC6_LOW 1 //CT16Bn PWM6 pin is low. +#define CT16_EMC6_HIGH 2 //CT16Bn PWM6 pin is high. +#define CT16_EMC6_TOGGLE 3 //Toggle CT16Bn PWM6 pin. +#define mskCT16_EMC6_DO_NOTHING (CT16_EMC6_LOW<<12) +#define mskCT16_EMC6_LOW (CT16_EMC6_LOW<<12) +#define mskCT16_EMC6_HIGH (CT16_EMC6_HIGH<<12) +#define mskCT16_EMC6_TOGGLE (CT16_EMC6_TOGGLE<<12) + + //[15:14]CT16Bn PWM7 functionality +#define CT16_EMC7_DO_NOTHING 0 //Do nothing. +#define CT16_EMC7_LOW 1 //CT16Bn PWM7 pin is low. +#define CT16_EMC7_HIGH 2 //CT16Bn PWM7 pin is high. +#define CT16_EMC7_TOGGLE 3 //Toggle CT16Bn PWM7 pin. +#define mskCT16_EMC7_DO_NOTHING (CT16_EMC7_LOW<<14) +#define mskCT16_EMC7_LOW (CT16_EMC7_LOW<<14) +#define mskCT16_EMC7_HIGH (CT16_EMC7_HIGH<<14) +#define mskCT16_EMC7_TOGGLE (CT16_EMC7_TOGGLE<<14) + + //[17:16]CT16Bn PWM8 functionality +#define CT16_EMC8_DO_NOTHING 0 //Do nothing. +#define CT16_EMC8_LOW 1 //CT16Bn PWM8 pin is low. +#define CT16_EMC8_HIGH 2 //CT16Bn PWM8 pin is high. +#define CT16_EMC8_TOGGLE 3 //Toggle CT16Bn PWM8 pin. +#define mskCT16_EMC8_DO_NOTHING (CT16_EMC8_LOW<<16) +#define mskCT16_EMC8_LOW (CT16_EMC8_LOW<<16) +#define mskCT16_EMC8_HIGH (CT16_EMC8_HIGH<<16) +#define mskCT16_EMC8_TOGGLE (CT16_EMC8_TOGGLE<<16) + + //[19:18]CT16Bn PWM9 functionality +#define CT16_EMC9_DO_NOTHING 0 //Do nothing. +#define CT16_EMC9_LOW 1 //CT16Bn PWM9 pin is low. +#define CT16_EMC9_HIGH 2 //CT16Bn PWM9 pin is high. +#define CT16_EMC9_TOGGLE 3 //Toggle CT16Bn PWM9 pin. +#define mskCT16_EMC9_DO_NOTHING (CT16_EMC9_LOW<<18) +#define mskCT16_EMC9_LOW (CT16_EMC9_LOW<<18) +#define mskCT16_EMC9_HIGH (CT16_EMC9_HIGH<<18) +#define mskCT16_EMC9_TOGGLE (CT16_EMC9_TOGGLE<<18) + + //[21:20]CT16Bn PWM10 functionality +#define CT16_EMC10_DO_NOTHING 0 //Do nothing. +#define CT16_EMC10_LOW 1 //CT16Bn PWM10 pin is low. +#define CT16_EMC10_HIGH 2 //CT16Bn PWM10 pin is high. +#define CT16_EMC10_TOGGLE 3 //Toggle CT16Bn PWM10 pin. +#define mskCT16_EMC10_DO_NOTHING (CT16_EMC10_LOW<<20) +#define mskCT16_EMC10_LOW (CT16_EMC10_LOW<<20) +#define mskCT16_EMC10_HIGH (CT16_EMC10_HIGH<<20) +#define mskCT16_EMC10_TOGGLE (CT16_EMC10_TOGGLE<<20) + + //[23:22]CT16Bn PWM11 functionality +#define CT16_EMC11_DO_NOTHING 0 //Do nothing. +#define CT16_EMC11_LOW 1 //CT16Bn PWM11 pin is low. +#define CT16_EMC11_HIGH 2 //CT16Bn PWM11 pin is high. +#define CT16_EMC11_TOGGLE 3 //Toggle CT16Bn PWM11 pin. +#define mskCT16_EMC11_DO_NOTHING (CT16_EMC11_LOW<<22) +#define mskCT16_EMC11_LOW (CT16_EMC11_LOW<<22) +#define mskCT16_EMC11_HIGH (CT16_EMC11_HIGH<<22) +#define mskCT16_EMC11_TOGGLE (CT16_EMC11_TOGGLE<<22) + + //[25:24]CT16Bn PWM12 functionality +#define CT16_EMC12_DO_NOTHING 0 //Do nothing. +#define CT16_EMC12_LOW 1 //CT16Bn PWM12 pin is low. +#define CT16_EMC12_HIGH 2 //CT16Bn PWM12 pin is high. +#define CT16_EMC12_TOGGLE 3 //Toggle CT16Bn PWM12 pin. +#define mskCT16_EMC12_DO_NOTHING (CT16_EMC12_LOW<<24) +#define mskCT16_EMC12_LOW (CT16_EMC12_LOW<<24) +#define mskCT16_EMC12_HIGH (CT16_EMC12_HIGH<<24) +#define mskCT16_EMC12_TOGGLE (CT16_EMC12_TOGGLE<<24) + + //[27:26]CT16Bn PWM13 functionality +#define CT16_EMC13_DO_NOTHING 0 //Do nothing. +#define CT16_EMC13_LOW 1 //CT16Bn PWM13 pin is low. +#define CT16_EMC13_HIGH 2 //CT16Bn PWM13 pin is high. +#define CT16_EMC13_TOGGLE 3 //Toggle CT16Bn PWM13 pin. +#define mskCT16_EMC13_DO_NOTHING (CT16_EMC13_LOW<<26) +#define mskCT16_EMC13_LOW (CT16_EMC13_LOW<<26) +#define mskCT16_EMC13_HIGH (CT16_EMC13_HIGH<<26) +#define mskCT16_EMC13_TOGGLE (CT16_EMC13_TOGGLE<<26) + + //[29:28]CT16Bn PWM14 functionality +#define CT16_EMC14_DO_NOTHING 0 //Do nothing. +#define CT16_EMC14_LOW 1 //CT16Bn PWM14 pin is low. +#define CT16_EMC14_HIGH 2 //CT16Bn PWM14 pin is high. +#define CT16_EMC14_TOGGLE 3 //Toggle CT16Bn PWM14 pin. +#define mskCT16_EMC14_DO_NOTHING (CT16_EMC14_LOW<<28) +#define mskCT16_EMC14_LOW (CT16_EMC14_LOW<<28) +#define mskCT16_EMC14_HIGH (CT16_EMC14_HIGH<<28) +#define mskCT16_EMC14_TOGGLE (CT16_EMC14_TOGGLE<<28) + + //[31:30]CT16Bn PWM15 functionality +#define CT16_EMC15_DO_NOTHING 0 //Do nothing. +#define CT16_EMC15_LOW 1 //CT16Bn PWM15 pin is low. +#define CT16_EMC15_HIGH 2 //CT16Bn PWM15 pin is high. +#define CT16_EMC15_TOGGLE 3 //Toggle CT16Bn PWM15 pin. +#define mskCT16_EMC15_DO_NOTHING (CT16_EMC15_LOW<<30) +#define mskCT16_EMC15_LOW (CT16_EMC15_LOW<<30) +#define mskCT16_EMC15_HIGH (CT16_EMC15_HIGH<<30) +#define mskCT16_EMC15_TOGGLE (CT16_EMC15_TOGGLE<<30) + +/* CT16Bn External Match Control register2 (0x90) */ + //[1:0]CT16Bn PWM16 functionality +#define CT16_EMC16_DO_NOTHING 0 //Do nothing. +#define CT16_EMC16_LOW 1 //CT16Bn PWM16 pin is low. +#define CT16_EMC16_HIGH 2 //CT16Bn PWM16 pin is high. +#define CT16_EMC16_TOGGLE 3 //Toggle CT16Bn PWM16 pin. +#define mskCT16_EMC16_DO_NOTHING (CT16_EMC16_LOW<<0) +#define mskCT16_EMC16_LOW (CT16_EMC16_LOW<<0) +#define mskCT16_EMC16_HIGH (CT16_EMC16_HIGH<<0) +#define mskCT16_EMC16_TOGGLE (CT16_EMC16_TOGGLE<<0) + + //[3:2]CT16Bn PWM17 functionality +#define CT16_EMC17_DO_NOTHING 0 //Do nothing. +#define CT16_EMC17_LOW 1 //CT16Bn PWM17 pin is low. +#define CT16_EMC17_HIGH 2 //CT16Bn PWM17 pin is high. +#define CT16_EMC17_TOGGLE 3 //Toggle CT16Bn PWM17 pin. +#define mskCT16_EMC17_DO_NOTHING (CT16_EMC17_LOW<<2) +#define mskCT16_EMC17_LOW (CT16_EMC17_LOW<<2) +#define mskCT16_EMC17_HIGH (CT16_EMC17_HIGH<<2) +#define mskCT16_EMC17_TOGGLE (CT16_EMC17_TOGGLE<<2) + + //[5:4]CT16Bn PWM18 functionality +#define CT16_EMC18_DO_NOTHING 0 //Do nothing. +#define CT16_EMC18_LOW 1 //CT16Bn PWM18 pin is low. +#define CT16_EMC18_HIGH 2 //CT16Bn PWM18 pin is high. +#define CT16_EMC18_TOGGLE 3 //Toggle CT16Bn PWM18 pin. +#define mskCT16_EMC18_DO_NOTHING (CT16_EMC18_LOW<<4) +#define mskCT16_EMC18_LOW (CT16_EMC18_LOW<<4) +#define mskCT16_EMC18_HIGH (CT16_EMC18_HIGH<<4) +#define mskCT16_EMC18_TOGGLE (CT16_EMC18_TOGGLE<<4) + + //[7:6]CT16Bn PWM19 functionality +#define CT16_EMC19_DO_NOTHING 0 //Do nothing. +#define CT16_EMC19_LOW 1 //CT16Bn PWM19 pin is low. +#define CT16_EMC19_HIGH 2 //CT16Bn PWM19 pin is high. +#define CT16_EMC19_TOGGLE 3 //Toggle CT16Bn PWM19 pin. +#define mskCT16_EMC19_DO_NOTHING (CT16_EMC19_LOW<<6) +#define mskCT16_EMC19_LOW (CT16_EMC19_LOW<<6) +#define mskCT16_EMC19_HIGH (CT16_EMC19_HIGH<<6) +#define mskCT16_EMC19_TOGGLE (CT16_EMC19_TOGGLE<<6) + + //[9:8]CT16Bn PWM20 functionality +#define CT16_EMC20_DO_NOTHING 0 //Do nothing. +#define CT16_EMC20_LOW 1 //CT16Bn PWM20 pin is low. +#define CT16_EMC20_HIGH 2 //CT16Bn PWM20 pin is high. +#define CT16_EMC20_TOGGLE 3 //Toggle CT16Bn PWM20 pin. +#define mskCT16_EMC20_DO_NOTHING (CT16_EMC20_LOW<<8) +#define mskCT16_EMC20_LOW (CT16_EMC20_LOW<<8) +#define mskCT16_EMC20_HIGH (CT16_EMC20_HIGH<<8) +#define mskCT16_EMC20_TOGGLE (CT16_EMC20_TOGGLE<<8) + + //[11:10]CT16Bn PWM21 functionality +#define CT16_EMC21_DO_NOTHING 0 //Do nothing. +#define CT16_EMC21_LOW 1 //CT16Bn PWM21 pin is low. +#define CT16_EMC21_HIGH 2 //CT16Bn PWM21 pin is high. +#define CT16_EMC21_TOGGLE 3 //Toggle CT16Bn PWM21 pin. +#define mskCT16_EMC21_DO_NOTHING (CT16_EMC21_LOW<<10) +#define mskCT16_EMC21_LOW (CT16_EMC21_LOW<<10) +#define mskCT16_EMC21_HIGH (CT16_EMC21_HIGH<<10) +#define mskCT16_EMC21_TOGGLE (CT16_EMC21_TOGGLE<<10) + + //[13:12]CT16Bn PWM22 functionality +#define CT16_EMC22_DO_NOTHING 0 //Do nothing. +#define CT16_EMC22_LOW 1 //CT16Bn PWM22 pin is low. +#define CT16_EMC22_HIGH 2 //CT16Bn PWM22 pin is high. +#define CT16_EMC22_TOGGLE 3 //Toggle CT16Bn PWM22 pin. +#define mskCT16_EMC22_DO_NOTHING (CT16_EMC22_LOW<<12) +#define mskCT16_EMC22_LOW (CT16_EMC22_LOW<<12) +#define mskCT16_EMC22_HIGH (CT16_EMC22_HIGH<<12) +#define mskCT16_EMC22_TOGGLE (CT16_EMC22_TOGGLE<<12) + + //[15:14]CT16Bn PWM23 functionality +#define CT16_EMC23_DO_NOTHING 0 //Do nothing. +#define CT16_EMC23_LOW 1 //CT16Bn PWM23 pin is low. +#define CT16_EMC23_HIGH 2 //CT16Bn PWM23 pin is high. +#define CT16_EMC23_TOGGLE 3 //Toggle CT16Bn PWM23 pin. +#define mskCT16_EMC23_DO_NOTHING (CT16_EMC23_LOW<<14) +#define mskCT16_EMC23_LOW (CT16_EMC23_LOW<<14) +#define mskCT16_EMC23_HIGH (CT16_EMC23_HIGH<<14) +#define mskCT16_EMC23_TOGGLE (CT16_EMC23_TOGGLE<<14) + +/* CT16Bn PWM Control register (0x94) */ + //[1:0] CT16Bn PWM0 output mode. +#define CT16_PWM0MODE_1 0 // PWM mode 1. +#define CT16_PWM0MODE_2 1 // PWM mode 2. +#define CT16_PWM0MODE_FORCE_0 2 // Force 0. +#define CT16_PWM0MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM0MODE_1 (CT16_PWM0MODE_1<<0) +#define mskCT16_PWM0MODE_2 (CT16_PWM0MODE_2<<0) +#define mskCT16_PWM0MODE_FORCE_0 (CT16_PWM0MODE_FORCE_0<<0) +#define mskCT16_PWM0MODE_FORCE_1 (CT16_PWM0MODE_FORCE_1<<0) + + //[3:2] CT16Bn PWM1 output mode. +#define CT16_PWM1MODE_1 0 // PWM mode 1. +#define CT16_PWM1MODE_2 1 // PWM mode 2. +#define CT16_PWM1MODE_FORCE_0 2 // Force 0. +#define CT16_PWM1MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM1MODE_1 (CT16_PWM1MODE_1<<2) +#define mskCT16_PWM1MODE_2 (CT16_PWM1MODE_2<<2) +#define mskCT16_PWM1MODE_FORCE_0 (CT16_PWM1MODE_FORCE_0<<2) +#define mskCT16_PWM1MODE_FORCE_1 (CT16_PWM1MODE_FORCE_1<<2) + + //[5:4] CT16Bn PWM2 output mode. +#define CT16_PWM2MODE_1 0 // PWM mode 1. +#define CT16_PWM2MODE_2 1 // PWM mode 2. +#define CT16_PWM2MODE_FORCE_0 2 // Force 0. +#define CT16_PWM2MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM2MODE_1 (CT16_PWM2MODE_1<<4) +#define mskCT16_PWM2MODE_2 (CT16_PWM2MODE_2<<4) +#define mskCT16_PWM2MODE_FORCE_0 (CT16_PWM2MODE_FORCE_0<<4) +#define mskCT16_PWM2MODE_FORCE_1 (CT16_PWM2MODE_FORCE_1<<4) + + //[7:6] CT16Bn PWM3 output mode. +#define CT16_PWM3MODE_1 0 // PWM mode 1. +#define CT16_PWM3MODE_2 1 // PWM mode 2. +#define CT16_PWM3MODE_FORCE_0 2 // Force 0. +#define CT16_PWM3MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM3MODE_1 (CT16_PWM3MODE_1<<6) +#define mskCT16_PWM3MODE_2 (CT16_PWM3MODE_2<<6) +#define mskCT16_PWM3MODE_FORCE_0 (CT16_PWM3MODE_FORCE_0<<6) +#define mskCT16_PWM3MODE_FORCE_1 (CT16_PWM3MODE_FORCE_1<<6) + + //[9:8] CT16Bn PWM4 output mode. +#define CT16_PWM4MODE_1 0 // PWM mode 1. +#define CT16_PWM4MODE_2 1 // PWM mode 2. +#define CT16_PWM4MODE_FORCE_0 2 // Force 0. +#define CT16_PWM4MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM4MODE_1 (CT16_PWM4MODE_1<<8) +#define mskCT16_PWM4MODE_2 (CT16_PWM4MODE_2<<8) +#define mskCT16_PWM4MODE_FORCE_0 (CT16_PWM4MODE_FORCE_0<<8) +#define mskCT16_PWM4MODE_FORCE_1 (CT16_PWM4MODE_FORCE_1<<8) + + //[11:10] CT16Bn PWM5 output mode. +#define CT16_PWM5MODE_1 0 // PWM mode 1. +#define CT16_PWM5MODE_2 1 // PWM mode 2. +#define CT16_PWM5MODE_FORCE_0 2 // Force 0. +#define CT16_PWM5MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM5MODE_1 (CT16_PWM5MODE_1<<10) +#define mskCT16_PWM5MODE_2 (CT16_PWM5MODE_2<<10) +#define mskCT16_PWM5MODE_FORCE_0 (CT16_PWM5MODE_FORCE_0<<10) +#define mskCT16_PWM5MODE_FORCE_1 (CT16_PWM5MODE_FORCE_1<<10) + + //[13:12] CT16Bn PWM6 output mode. +#define CT16_PWM6MODE_1 0 // PWM mode 1. +#define CT16_PWM6MODE_2 1 // PWM mode 2. +#define CT16_PWM6MODE_FORCE_0 2 // Force 0. +#define CT16_PWM6MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM6MODE_1 (CT16_PWM6MODE_1<<12) +#define mskCT16_PWM6MODE_2 (CT16_PWM6MODE_2<<12) +#define mskCT16_PWM6MODE_FORCE_0 (CT16_PWM6MODE_FORCE_0<<12) +#define mskCT16_PWM6MODE_FORCE_1 (CT16_PWM6MODE_FORCE_1<<12) + + //[15:14] CT16Bn PWM7 output mode. +#define CT16_PWM7MODE_1 0 // PWM mode 1. +#define CT16_PWM7MODE_2 1 // PWM mode 2. +#define CT16_PWM7MODE_FORCE_0 2 // Force 0. +#define CT16_PWM7MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM7MODE_1 (CT16_PWM7MODE_1<<14) +#define mskCT16_PWM7MODE_2 (CT16_PWM7MODE_2<<14) +#define mskCT16_PWM7MODE_FORCE_0 (CT16_PWM7MODE_FORCE_0<<14) +#define mskCT16_PWM7MODE_FORCE_1 (CT16_PWM7MODE_FORCE_1<<14) + + //[17:16] CT16Bn PWM8 output mode. +#define CT16_PWM8MODE_1 0 // PWM mode 1. +#define CT16_PWM8MODE_2 1 // PWM mode 2. +#define CT16_PWM8MODE_FORCE_0 2 // Force 0. +#define CT16_PWM8MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM8MODE_1 (CT16_PWM8MODE_1<<16) +#define mskCT16_PWM8MODE_2 (CT16_PWM8MODE_2<<16) +#define mskCT16_PWM8MODE_FORCE_0 (CT16_PWM8MODE_FORCE_0<<16) +#define mskCT16_PWM8MODE_FORCE_1 (CT16_PWM8MODE_FORCE_1<<16) + + //[19:18] CT16Bn PWM9 output mode. +#define CT16_PWM9MODE_1 0 // PWM mode 1. +#define CT16_PWM9MODE_2 1 // PWM mode 2. +#define CT16_PWM9MODE_FORCE_0 2 // Force 0. +#define CT16_PWM9MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM9MODE_1 (CT16_PWM9MODE_1<<18) +#define mskCT16_PWM9MODE_2 (CT16_PWM9MODE_2<<18) +#define mskCT16_PWM9MODE_FORCE_0 (CT16_PWM9MODE_FORCE_0<<18) +#define mskCT16_PWM9MODE_FORCE_1 (CT16_PWM9MODE_FORCE_1<<18) + + //[21:20] CT16Bn PWM10 output mode. +#define CT16_PWM10MODE_1 0 // PWM mode 1. +#define CT16_PWM10MODE_2 1 // PWM mode 2. +#define CT16_PWM10MODE_FORCE_0 2 // Force 0. +#define CT16_PWM10MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM10MODE_1 (CT16_PWM10MODE_1<<20) +#define mskCT16_PWM10MODE_2 (CT16_PWM10MODE_2<<20) +#define mskCT16_PWM10MODE_FORCE_0 (CT16_PWM10MODE_FORCE_0<<20) +#define mskCT16_PWM10MODE_FORCE_1 (CT16_PWM10MODE_FORCE_1<<20) + + //[23:22] CT16Bn PWM11 output mode. +#define CT16_PWM11MODE_1 0 // PWM mode 1. +#define CT16_PWM11MODE_2 1 // PWM mode 2. +#define CT16_PWM11MODE_FORCE_0 2 // Force 0. +#define CT16_PWM11MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM11MODE_1 (CT16_PWM11MODE_1<<22) +#define mskCT16_PWM11MODE_2 (CT16_PWM11MODE_2<<22) +#define mskCT16_PWM11MODE_FORCE_0 (CT16_PWM11MODE_FORCE_0<<22) +#define mskCT16_PWM11MODE_FORCE_1 (CT16_PWM11MODE_FORCE_1<<22) + + //[25:24] CT16Bn PWM12 output mode. +#define CT16_PWM12MODE_1 0 // PWM mode 1. +#define CT16_PWM12MODE_2 1 // PWM mode 2. +#define CT16_PWM12MODE_FORCE_0 2 // Force 0. +#define CT16_PWM12MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM12MODE_1 (CT16_PWM12MODE_1<<24) +#define mskCT16_PWM12MODE_2 (CT16_PWM12MODE_2<<24) +#define mskCT16_PWM12MODE_FORCE_0 (CT16_PWM12MODE_FORCE_0<<24) +#define mskCT16_PWM12MODE_FORCE_1 (CT16_PWM12MODE_FORCE_1<<24) + + //[27:26] CT16Bn PWM13 output mode. +#define CT16_PWM13MODE_1 0 // PWM mode 1. +#define CT16_PWM13MODE_2 1 // PWM mode 2. +#define CT16_PWM13MODE_FORCE_0 2 // Force 0. +#define CT16_PWM13MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM13MODE_1 (CT16_PWM13MODE_1<<26) +#define mskCT16_PWM13MODE_2 (CT16_PWM13MODE_2<<26) +#define mskCT16_PWM13MODE_FORCE_0 (CT16_PWM13MODE_FORCE_0<<26) +#define mskCT16_PWM13MODE_FORCE_1 (CT16_PWM13MODE_FORCE_1<<26) + + //[29:28] CT16Bn PWM14 output mode. +#define CT16_PWM14MODE_1 0 // PWM mode 1. +#define CT16_PWM14MODE_2 1 // PWM mode 2. +#define CT16_PWM14MODE_FORCE_0 2 // Force 0. +#define CT16_PWM14MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM14MODE_1 (CT16_PWM14MODE_1<<28) +#define mskCT16_PWM14MODE_2 (CT16_PWM14MODE_2<<28) +#define mskCT16_PWM14MODE_FORCE_0 (CT16_PWM14MODE_FORCE_0<<28) +#define mskCT16_PWM14MODE_FORCE_1 (CT16_PWM14MODE_FORCE_1<<28) + + //[31:30] CT16Bn PWM15 output mode. +#define CT16_PWM15MODE_1 0 // PWM mode 1. +#define CT16_PWM15MODE_2 1 // PWM mode 2. +#define CT16_PWM15MODE_FORCE_0 2 // Force 0. +#define CT16_PWM15MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM15MODE_1 (CT16_PWM15MODE_1<<30) +#define mskCT16_PWM15MODE_2 (CT16_PWM15MODE_2<<30) +#define mskCT16_PWM15MODE_FORCE_0 (CT16_PWM15MODE_FORCE_0<<30) +#define mskCT16_PWM15MODE_FORCE_1 (CT16_PWM15MODE_FORCE_1<<30) + +/* CT16Bn PWM Control register (0x98) */ + //[1:0] CT16Bn PWM16 output mode. +#define CT16_PWM16MODE_1 0 // PWM mode 1. +#define CT16_PWM16MODE_2 1 // PWM mode 2. +#define CT16_PWM16MODE_FORCE_0 2 // Force 0. +#define CT16_PWM16MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM16MODE_1 (CT16_PWM16MODE_1<<0) +#define mskCT16_PWM16MODE_2 (CT16_PWM16MODE_2<<0) +#define mskCT16_PWM16MODE_FORCE_0 (CT16_PWM16MODE_FORCE_0<<0) +#define mskCT16_PWM16MODE_FORCE_1 (CT16_PWM16MODE_FORCE_1<<0) + + //[3:2] CT16Bn PWM17 output mode. +#define CT16_PWM17MODE_1 0 // PWM mode 1. +#define CT16_PWM17MODE_2 1 // PWM mode 2. +#define CT16_PWM17MODE_FORCE_0 2 // Force 0. +#define CT16_PWM17MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM17MODE_1 (CT16_PWM17MODE_1<<2) +#define mskCT16_PWM17MODE_2 (CT16_PWM17MODE_2<<2) +#define mskCT16_PWM17MODE_FORCE_0 (CT16_PWM17MODE_FORCE_0<<2) +#define mskCT16_PWM17MODE_FORCE_1 (CT16_PWM17MODE_FORCE_1<<2) + + //[5:4] CT16Bn PWM18 output mode. +#define CT16_PWM18MODE_1 0 // PWM mode 1. +#define CT16_PWM18MODE_2 1 // PWM mode 2. +#define CT16_PWM18MODE_FORCE_0 2 // Force 0. +#define CT16_PWM18MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM18MODE_1 (CT16_PWM18MODE_1<<4) +#define mskCT16_PWM18MODE_2 (CT16_PWM18MODE_2<<4) +#define mskCT16_PWM18MODE_FORCE_0 (CT16_PWM18MODE_FORCE_0<<4) +#define mskCT16_PWM18MODE_FORCE_1 (CT16_PWM18MODE_FORCE_1<<4) + + //[7:6] CT16Bn PWM19 output mode. +#define CT16_PWM19MODE_1 0 // PWM mode 1. +#define CT16_PWM19MODE_2 1 // PWM mode 2. +#define CT16_PWM19MODE_FORCE_0 2 // Force 0. +#define CT16_PWM19MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM19MODE_1 (CT16_PWM19MODE_1<<6) +#define mskCT16_PWM19MODE_2 (CT16_PWM19MODE_2<<6) +#define mskCT16_PWM19MODE_FORCE_0 (CT16_PWM19MODE_FORCE_0<<6) +#define mskCT16_PWM19MODE_FORCE_1 (CT16_PWM19MODE_FORCE_1<<6) + + //[9:8] CT16Bn PWM20 output mode. +#define CT16_PWM20MODE_1 0 // PWM mode 1. +#define CT16_PWM20MODE_2 1 // PWM mode 2. +#define CT16_PWM20MODE_FORCE_0 2 // Force 0. +#define CT16_PWM20MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM20MODE_1 (CT16_PWM20MODE_1<<8) +#define mskCT16_PWM20MODE_2 (CT16_PWM20MODE_2<<8) +#define mskCT16_PWM20MODE_FORCE_0 (CT16_PWM20MODE_FORCE_0<<8) +#define mskCT16_PWM20MODE_FORCE_1 (CT16_PWM20MODE_FORCE_1<<8) + + //[11:10] CT16Bn PWM21 output mode. +#define CT16_PWM21MODE_1 0 // PWM mode 1. +#define CT16_PWM21MODE_2 1 // PWM mode 2. +#define CT16_PWM21MODE_FORCE_0 2 // Force 0. +#define CT16_PWM21MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM21MODE_1 (CT16_PWM21MODE_1<<10) +#define mskCT16_PWM21MODE_2 (CT16_PWM21MODE_2<<10) +#define mskCT16_PWM21MODE_FORCE_0 (CT16_PWM21MODE_FORCE_0<<10) +#define mskCT16_PWM21MODE_FORCE_1 (CT16_PWM21MODE_FORCE_1<<10) + + //[13:12] CT16Bn PWM22 output mode. +#define CT16_PWM22MODE_1 0 // PWM mode 1. +#define CT16_PWM22MODE_2 1 // PWM mode 2. +#define CT16_PWM22MODE_FORCE_0 2 // Force 0. +#define CT16_PWM22MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM22MODE_1 (CT16_PWM22MODE_1<<12) +#define mskCT16_PWM22MODE_2 (CT16_PWM22MODE_2<<12) +#define mskCT16_PWM22MODE_FORCE_0 (CT16_PWM22MODE_FORCE_0<<12) +#define mskCT16_PWM22MODE_FORCE_1 (CT16_PWM22MODE_FORCE_1<<12) + + //[15:14] CT16Bn PWM23 output mode. +#define CT16_PWM23MODE_1 0 // PWM mode 1. +#define CT16_PWM23MODE_2 1 // PWM mode 2. +#define CT16_PWM23MODE_FORCE_0 2 // Force 0. +#define CT16_PWM23MODE_FORCE_1 3 // Force 1. +#define mskCT16_PWM23MODE_1 (CT16_PWM23MODE_1<<14) +#define mskCT16_PWM23MODE_2 (CT16_PWM23MODE_2<<14) +#define mskCT16_PWM23MODE_FORCE_0 (CT16_PWM23MODE_FORCE_0<<14) +#define mskCT16_PWM23MODE_FORCE_1 (CT16_PWM23MODE_FORCE_1<<14) + +/* CT16Bn PWM Enable register (0x9C) */ + //[0:0] CT16Bn PWM0 enable. +#define CT16_PWM0EN_EN 1 // CT16Bn PWM0 is enabled for PWM mode. +#define CT16_PWM0EN_EM0 0 // CT16Bn PWM0 is controlled by EM0. +#define mskCT16_PWM0EN_EN (CT16_PWM0EN_EN<<0) +#define mskCT16_PWM0EN_EM0 (CT16_PWM0EN_EM0<<0) + + //[1:1] CT16Bn PWM1 enable. +#define CT16_PWM1EN_EN 1 // CT16Bn PWM1 is enabled for PWM mode. +#define CT16_PWM1EN_EM1 0 // CT16Bn PWM1 is controlled by EM1. +#define mskCT16_PWM1EN_EN (CT16_PWM1EN_EN<<1) +#define mskCT16_PWM1EN_EM1 (CT16_PWM1EN_EM1<<1) + + //[2:2] CT16Bn PWM2 enable. +#define CT16_PWM2EN_EN 1 // CT16Bn PWM2 is enabled for PWM mode. +#define CT16_PWM2EN_EM2 0 // CT16Bn PWM2 is controlled by EM2. +#define mskCT16_PWM2EN_EN (CT16_PWM2EN_EN<<2) +#define mskCT16_PWM2EN_EM2 (CT16_PWM2EN_EM2<<2) + + //[3:3] CT16Bn PWM3 enable. +#define CT16_PWM3EN_EN 1 // CT16Bn PWM3 is enabled for PWM mode. +#define CT16_PWM3EN_EM3 0 // CT16Bn PWM3 is controlled by EM3. +#define mskCT16_PWM3EN_EN (CT16_PWM3EN_EN<<3) +#define mskCT16_PWM3EN_EM3 (CT16_PWM3EN_EM3<<3) + + //[4:4] CT16Bn PWM4 enable. +#define CT16_PWM4EN_EN 1 // CT16Bn PWM4 is enabled for PWM mode. +#define CT16_PWM4EN_EM4 0 // CT16Bn PWM4 is controlled by EM4. +#define mskCT16_PWM4EN_EN (CT16_PWM4EN_EN<<4) +#define mskCT16_PWM4EN_EM4 (CT16_PWM4EN_EM4<<4) + + //[5:5] CT16Bn PWM5 enable. +#define CT16_PWM5EN_EN 1 // CT16Bn PWM5 is enabled for PWM mode. +#define CT16_PWM5EN_EM5 0 // CT16Bn PWM5 is controlled by EM5. +#define mskCT16_PWM5EN_EN (CT16_PWM5EN_EN<<5) +#define mskCT16_PWM5EN_EM5 (CT16_PWM5EN_EM5<<5) + + //[6:6] CT16Bn PWM6 enable. +#define CT16_PWM6EN_EN 1 // CT16Bn PWM6 is enabled for PWM mode. +#define CT16_PWM6EN_EM6 0 // CT16Bn PWM6 is controlled by EM6. +#define mskCT16_PWM6EN_EN (CT16_PWM6EN_EN<<6) +#define mskCT16_PWM6EN_EM6 (CT16_PWM6EN_EM6<<6) + + //[7:7] CT16Bn PWM7 enable. +#define CT16_PWM7EN_EN 1 // CT16Bn PWM7 is enabled for PWM mode. +#define CT16_PWM7EN_EM7 0 // CT16Bn PWM7 is controlled by EM7. +#define mskCT16_PWM7EN_EN (CT16_PWM7EN_EN<<7) +#define mskCT16_PWM7EN_EM7 (CT16_PWM7EN_EM7<<7) + + //[8:8] CT16Bn PWM8 enable. +#define CT16_PWM8EN_EN 1 // CT16Bn PWM8 is enabled for PWM mode. +#define CT16_PWM8EN_EM8 0 // CT16Bn PWM8 is controlled by EM8. +#define mskCT16_PWM8EN_EN (CT16_PWM8EN_EN<<8) +#define mskCT16_PWM8EN_EM8 (CT16_PWM8EN_EM8<<8) + + //[9:9] CT16Bn PWM9 enable. +#define CT16_PWM9EN_EN 1 // CT16Bn PWM9 is enabled for PWM mode. +#define CT16_PWM9EN_EM9 0 // CT16Bn PWM9 is controlled by EM9. +#define mskCT16_PWM9EN_EN (CT16_PWM9EN_EN<<9) +#define mskCT16_PWM9EN_EM9 (CT16_PWM9EN_EM9<<9) + + //[10:10] CT16Bn PWM10 enable. +#define CT16_PWM10EN_EN 1 // CT16Bn PWM10 is enabled for PWM mode. +#define CT16_PWM10EN_EM10 0 // CT16Bn PWM10 is controlled by EM10. +#define mskCT16_PWM10EN_EN (CT16_PWM10EN_EN<<10) +#define mskCT16_PWM10EN_EM10 (CT16_PWM10EN_EM10<<10) + + //[11:11] CT16Bn PWM11 enable. +#define CT16_PWM11EN_EN 1 // CT16Bn PWM11 is enabled for PWM mode. +#define CT16_PWM11EN_EM11 0 // CT16Bn PWM11 is controlled by EM11. +#define mskCT16_PWM11EN_EN (CT16_PWM11EN_EN<<11) +#define mskCT16_PWM11EN_EM11 (CT16_PWM11EN_EM11<<11) + + //[12:12] CT16Bn PWM12 enable. +#define CT16_PWM12EN_EN 1 // CT16Bn PWM12 is enabled for PWM mode. +#define CT16_PWM12EN_EM12 0 // CT16Bn PWM12 is controlled by EM12. +#define mskCT16_PWM12EN_EN (CT16_PWM12EN_EN<<12) +#define mskCT16_PWM12EN_EM12 (CT16_PWM12EN_EM12<<12) + + //[13:13] CT16Bn PWM13 enable. +#define CT16_PWM13EN_EN 1 // CT16Bn PWM13 is enabled for PWM mode. +#define CT16_PWM13EN_EM13 0 // CT16Bn PWM13 is controlled by EM13. +#define mskCT16_PWM13EN_EN (CT16_PWM13EN_EN<<13) +#define mskCT16_PWM13EN_EM13 (CT16_PWM13EN_EM13<<13) + + //[14:14] CT16Bn PWM14 enable. +#define CT16_PWM14EN_EN 1 // CT16Bn PWM14 is enabled for PWM mode. +#define CT16_PWM14EN_EM14 0 // CT16Bn PWM14 is controlled by EM14. +#define mskCT16_PWM14EN_EN (CT16_PWM14EN_EN<<14) +#define mskCT16_PWM14EN_EM14 (CT16_PWM14EN_EM14<<14) + + //[15:15] CT16Bn PWM15 enable. +#define CT16_PWM15EN_EN 1 // CT16Bn PWM15 is enabled for PWM mode. +#define CT16_PWM15EN_EM15 0 // CT16Bn PWM15 is controlled by EM15. +#define mskCT16_PWM15EN_EN (CT16_PWM15EN_EN<<15) +#define mskCT16_PWM15EN_EM15 (CT16_PWM15EN_EM15<<15) + + //[16:16] CT16Bn PWM16 enable. +#define CT16_PWM16EN_EN 1 // CT16Bn PWM16 is enabled for PWM mode. +#define CT16_PWM16EN_EM16 0 // CT16Bn PWM16 is controlled by EM16. +#define mskCT16_PWM16EN_EN (CT16_PWM16EN_EN<<16) +#define mskCT16_PWM16EN_EM16 (CT16_PWM16EN_EM16<<16) + + //[17:17] CT16Bn PWM17 enable. +#define CT16_PWM17EN_EN 1 // CT16Bn PWM17 is enabled for PWM mode. +#define CT16_PWM17EN_EM17 0 // CT16Bn PWM17 is controlled by EM17. +#define mskCT16_PWM17EN_EN (CT16_PWM17EN_EN<<17) +#define mskCT16_PWM17EN_EM17 (CT16_PWM17EN_EM17<<17) + + //[18:18] CT16Bn PWM18 enable. +#define CT16_PWM18EN_EN 1 // CT16Bn PWM18 is enabled for PWM mode. +#define CT16_PWM18EN_EM18 0 // CT16Bn PWM18 is controlled by EM18. +#define mskCT16_PWM18EN_EN (CT16_PWM18EN_EN<<18) +#define mskCT16_PWM18EN_EM18 (CT16_PWM18EN_EM18<<18) + + //[19:19] CT16Bn PWM19 enable. +#define CT16_PWM19EN_EN 1 // CT16Bn PWM19 is enabled for PWM mode. +#define CT16_PWM19EN_EM19 0 // CT16Bn PWM19 is controlled by EM19. +#define mskCT16_PWM19EN_EN (CT16_PWM19EN_EN<<19) +#define mskCT16_PWM19EN_EM19 (CT16_PWM19EN_EM19<<19) + + //[20:20] CT16Bn PWM20 enable. +#define CT16_PWM20EN_EN 1 // CT16Bn PWM20 is enabled for PWM mode. +#define CT16_PWM20EN_EM20 0 // CT16Bn PWM20 is controlled by EM20. +#define mskCT16_PWM20EN_EN (CT16_PWM20EN_EN<<20) +#define mskCT16_PWM20EN_EM20 (CT16_PWM20EN_EM20<<20) + + //[21:21] CT16Bn PWM21 enable. +#define CT16_PWM21EN_EN 1 // CT16Bn PWM21 is enabled for PWM mode. +#define CT16_PWM21EN_EM21 0 // CT16Bn PWM21 is controlled by EM21. +#define mskCT16_PWM21EN_EN (CT16_PWM21EN_EN<<21) +#define mskCT16_PWM21EN_EM21 (CT16_PWM21EN_EM21<<21) + + //[22:22] CT16Bn PWM22 enable. +#define CT16_PWM22EN_EN 1 // CT16Bn PWM22 is enabled for PWM mode. +#define CT16_PWM22EN_EM22 0 // CT16Bn PWM22 is controlled by EM22. +#define mskCT16_PWM22EN_EN (CT16_PWM22EN_EN<<22) +#define mskCT16_PWM22EN_EM22 (CT16_PWM22EN_EM22<<22) + + //[23:23] CT16Bn PWM23 enable. +#define CT16_PWM23EN_EN 1 // CT16Bn PWM23 is enabled for PWM mode. +#define CT16_PWM23EN_EM23 0 // CT16Bn PWM23 is controlled by EM23. +#define mskCT16_PWM23EN_EN (CT16_PWM23EN_EN<<23) +#define mskCT16_PWM23EN_EM23 (CT16_PWM23EN_EM23<<23) + +/* CT16Bn PWM IO Enable register (0xA0) */ + //[0:0] CT16Bn PWM0 IO selection. +#define CT16_PWM0IOEN_EN 1 // PWM0 pin acts as match output. +#define CT16_PWM0IOEN_DIS 0 // PWM0 pin acts as GPIO. +#define mskCT16_PWM0IOEN_EN (CT16_PWM0IOEN_EN<<0) +#define mskCT16_PWM0IOEN_DIS (CT16_PWM0IOEN_DIS<<0) + + //[1:1] CT16Bn PWM1 IO selection. +#define CT16_PWM1IOEN_EN 1 // PWM1 pin acts as match output. +#define CT16_PWM1IOEN_DIS 0 // PWM1 pin acts as GPIO. +#define mskCT16_PWM1IOEN_EN (CT16_PWM1IOEN_EN<<1) +#define mskCT16_PWM1IOEN_DIS (CT16_PWM1IOEN_DIS<<1) + + //[2:2] CT16Bn PWM2 IO selection. +#define CT16_PWM2IOEN_EN 1 // PWM2 pin acts as match output. +#define CT16_PWM2IOEN_DIS 0 // PWM2 pin acts as GPIO. +#define mskCT16_PWM2IOEN_EN (CT16_PWM2IOEN_EN<<2) +#define mskCT16_PWM2IOEN_DIS (CT16_PWM2IOEN_DIS<<2) + + //[3:3] CT16Bn PWM3 IO selection. +#define CT16_PWM3IOEN_EN 1 // PWM3 pin acts as match output. +#define CT16_PWM3IOEN_DIS 0 // PWM3 pin acts as GPIO. +#define mskCT16_PWM3IOEN_EN (CT16_PWM3IOEN_EN<<3) +#define mskCT16_PWM3IOEN_DIS (CT16_PWM3IOEN_DIS<<3) + + //[4:4] CT16Bn PWM4 IO selection. +#define CT16_PWM4IOEN_EN 1 // PWM4 pin acts as match output. +#define CT16_PWM4IOEN_DIS 0 // PWM4 pin acts as GPIO. +#define mskCT16_PWM4IOEN_EN (CT16_PWM4IOEN_EN<<4) +#define mskCT16_PWM4IOEN_DIS (CT16_PWM4IOEN_DIS<<4) + + //[5:5] CT16Bn PWM5 IO selection. +#define CT16_PWM5IOEN_EN 1 // PWM5 pin acts as match output. +#define CT16_PWM5IOEN_DIS 0 // PWM5 pin acts as GPIO. +#define mskCT16_PWM5IOEN_EN (CT16_PWM5IOEN_EN<<5) +#define mskCT16_PWM5IOEN_DIS (CT16_PWM5IOEN_DIS<<5) + + //[6:6] CT16Bn PWM6 IO selection. +#define CT16_PWM6IOEN_EN 1 // PWM6 pin acts as match output. +#define CT16_PWM6IOEN_DIS 0 // PWM6 pin acts as GPIO. +#define mskCT16_PWM6IOEN_EN (CT16_PWM6IOEN_EN<<6) +#define mskCT16_PWM6IOEN_DIS (CT16_PWM6IOEN_DIS<<6) + + //[7:7] CT16Bn PWM7 IO selection. +#define CT16_PWM7IOEN_EN 1 // PWM7 pin acts as match output. +#define CT16_PWM7IOEN_DIS 0 // PWM7 pin acts as GPIO. +#define mskCT16_PWM7IOEN_EN (CT16_PWM7IOEN_EN<<7) +#define mskCT16_PWM7IOEN_DIS (CT16_PWM7IOEN_DIS<<7) + + //[8:8] CT16Bn PWM8 IO selection. +#define CT16_PWM8IOEN_EN 1 // PWM8 pin acts as match output. +#define CT16_PWM8IOEN_DIS 0 // PWM8 pin acts as GPIO. +#define mskCT16_PWM8IOEN_EN (CT16_PWM8IOEN_EN<<8) +#define mskCT16_PWM8IOEN_DIS (CT16_PWM8IOEN_DIS<<8) + + //[9:9] CT16Bn PWM9 IO selection. +#define CT16_PWM9IOEN_EN 1 // PWM9 pin acts as match output. +#define CT16_PWM9IOEN_DIS 0 // PWM9 pin acts as GPIO. +#define mskCT16_PWM9IOEN_EN (CT16_PWM9IOEN_EN<<9) +#define mskCT16_PWM9IOEN_DIS (CT16_PWM9IOEN_DIS<<9) + + //[10:10] CT16Bn PWM10 IO selection. +#define CT16_PWM10IOEN_EN 1 // PWM10 pin acts as match output. +#define CT16_PWM10IOEN_DIS 0 // PWM10 pin acts as GPIO. +#define mskCT16_PWM10IOEN_EN (CT16_PWM10IOEN_EN<<10) +#define mskCT16_PWM10IOEN_DIS (CT16_PWM10IOEN_DIS<<10) + + //[11:11] CT16Bn PWM11 IO selection. +#define CT16_PWM11IOEN_EN 1 // PWM11 pin acts as match output. +#define CT16_PWM11IOEN_DIS 0 // PWM11 pin acts as GPIO. +#define mskCT16_PWM11IOEN_EN (CT16_PWM11IOEN_EN<<11) +#define mskCT16_PWM11IOEN_DIS (CT16_PWM11IOEN_DIS<<11) + + //[12:12] CT16Bn PWM12 IO selection. +#define CT16_PWM12IOEN_EN 1 // PWM12 pin acts as match output. +#define CT16_PWM12IOEN_DIS 0 // PWM12 pin acts as GPIO. +#define mskCT16_PWM12IOEN_EN (CT16_PWM12IOEN_EN<<12) +#define mskCT16_PWM12IOEN_DIS (CT16_PWM12IOEN_DIS<<12) + + //[13:13] CT16Bn PWM13 IO selection. +#define CT16_PWM13IOEN_EN 1 // PWM13 pin acts as match output. +#define CT16_PWM13IOEN_DIS 0 // PWM13 pin acts as GPIO. +#define mskCT16_PWM13IOEN_EN (CT16_PWM13IOEN_EN<<13) +#define mskCT16_PWM13IOEN_DIS (CT16_PWM13IOEN_DIS<<13) + + //[14:14] CT16Bn PWM14 IO selection. +#define CT16_PWM14IOEN_EN 1 // PWM14 pin acts as match output. +#define CT16_PWM14IOEN_DIS 0 // PWM14 pin acts as GPIO. +#define mskCT16_PWM14IOEN_EN (CT16_PWM14IOEN_EN<<14) +#define mskCT16_PWM14IOEN_DIS (CT16_PWM14IOEN_DIS<<14) + + //[15:15] CT16Bn PWM15 IO selection. +#define CT16_PWM15IOEN_EN 1 // PWM15 pin acts as match output. +#define CT16_PWM15IOEN_DIS 0 // PWM15 pin acts as GPIO. +#define mskCT16_PWM15IOEN_EN (CT16_PWM15IOEN_EN<<15) +#define mskCT16_PWM15IOEN_DIS (CT16_PWM15IOEN_DIS<<15) + + //[16:16] CT16Bn PWM16 IO selection. +#define CT16_PWM16IOEN_EN 1 // PWM16 pin acts as match output. +#define CT16_PWM16IOEN_DIS 0 // PWM16 pin acts as GPIO. +#define mskCT16_PWM16IOEN_EN (CT16_PWM16IOEN_EN<<16) +#define mskCT16_PWM16IOEN_DIS (CT16_PWM16IOEN_DIS<<16) + + //[17:17] CT16Bn PWM17 IO selection. +#define CT16_PWM17IOEN_EN 1 // PWM17 pin acts as match output. +#define CT16_PWM17IOEN_DIS 0 // PWM17 pin acts as GPIO. +#define mskCT16_PWM17IOEN_EN (CT16_PWM17IOEN_EN<<17) +#define mskCT16_PWM17IOEN_DIS (CT16_PWM17IOEN_DIS<<17) + + //[18:18] CT16Bn PWM18 IO selection. +#define CT16_PWM18IOEN_EN 1 // PWM18 pin acts as match output. +#define CT16_PWM18IOEN_DIS 0 // PWM18 pin acts as GPIO. +#define mskCT16_PWM18IOEN_EN (CT16_PWM18IOEN_EN<<18) +#define mskCT16_PWM18IOEN_DIS (CT16_PWM18IOEN_DIS<<18) + + //[19:19] CT16Bn PWM19 IO selection. +#define CT16_PWM19IOEN_EN 1 // PWM19 pin acts as match output. +#define CT16_PWM19IOEN_DIS 0 // PWM19 pin acts as GPIO. +#define mskCT16_PWM19IOEN_EN (CT16_PWM19IOEN_EN<<19) +#define mskCT16_PWM19IOEN_DIS (CT16_PWM19IOEN_DIS<<19) + + //[20:20] CT16Bn PWM20 IO selection. +#define CT16_PWM20IOEN_EN 1 // PWM20 pin acts as match output. +#define CT16_PWM20IOEN_DIS 0 // PWM20 pin acts as GPIO. +#define mskCT16_PWM20IOEN_EN (CT16_PWM20IOEN_EN<<20) +#define mskCT16_PWM20IOEN_DIS (CT16_PWM20IOEN_DIS<<20) + + //[21:21] CT16Bn PWM21 IO selection. +#define CT16_PWM21IOEN_EN 1 // PWM21 pin acts as match output. +#define CT16_PWM21IOEN_DIS 0 // PWM21 pin acts as GPIO. +#define mskCT16_PWM21IOEN_EN (CT16_PWM21IOEN_EN<<21) +#define mskCT16_PWM21IOEN_DIS (CT16_PWM21IOEN_DIS<<21) + + //[22:22] CT16Bn PWM22 IO selection. +#define CT16_PWM22IOEN_EN 1 // PWM22 pin acts as match output. +#define CT16_PWM22IOEN_DIS 0 // PWM22 pin acts as GPIO. +#define mskCT16_PWM22IOEN_EN (CT16_PWM22IOEN_EN<<22) +#define mskCT16_PWM22IOEN_DIS (CT16_PWM22IOEN_DIS<<22) + + //[23:23] CT16Bn PWM23 IO selection. +#define CT16_PWM23IOEN_EN 1 // PWM23 pin acts as match output. +#define CT16_PWM23IOEN_DIS 0 // PWM23 pin acts as GPIO. +#define mskCT16_PWM23IOEN_EN (CT16_PWM23IOEN_EN<<23) +#define mskCT16_PWM23IOEN_DIS (CT16_PWM23IOEN_DIS<<23) + + +/* CT16Bn Timer Raw Interrupt Status register (0xA4) */ +/* CT16Bn Timer Interrupt Clear register (0xA8) */ +/* The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS*/ +#define mskCT16_MR0IF (0x1<<0) //[0:0] Interrupt flag for match channel 0 +#define mskCT16_MR0IC mskCT16_MR0IF +#define mskCT16_MR1IF (0x1<<1) //[1:1] Interrupt flag for match channel 1 +#define mskCT16_MR1IC mskCT16_MR1IF +#define mskCT16_MR2IF (0x1<<2) //[2:2] Interrupt flag for match channel 2 +#define mskCT16_MR2IC mskCT16_MR2IF +#define mskCT16_MR3IF (0x1<<3) //[3:3] Interrupt flag for match channel 3 +#define mskCT16_MR3IC mskCT16_MR3IF +#define mskCT16_MR4IF (0x1<<4) //[4:4] Interrupt flag for match channel 4 +#define mskCT16_MR4IC mskCT16_MR4IF +#define mskCT16_MR5IF (0x1<<5) //[5:5] Interrupt flag for match channel 5 +#define mskCT16_MR5IC mskCT16_MR5IF +#define mskCT16_MR6IF (0x1<<6) //[6:6] Interrupt flag for match channel 6 +#define mskCT16_MR6IC mskCT16_MR6IF +#define mskCT16_MR7IF (0x1<<7) //[7:7] Interrupt flag for match channel 7 +#define mskCT16_MR7IC mskCT16_MR7IF +#define mskCT16_MR8IF (0x1<<8) //[8:8] Interrupt flag for match channel 8 +#define mskCT16_MR8IC mskCT16_MR8IF +#define mskCT16_MR9IF (0x1<<9) //[9:9] Interrupt flag for match channel 9 +#define mskCT16_MR9IC mskCT16_MR9IF +#define mskCT16_MR10IF (0x1<<10) //[10:10] Interrupt flag for match channel 10 +#define mskCT16_MR10IC mskCT16_MR10IF +#define mskCT16_MR11IF (0x1<<11) //[11:11] Interrupt flag for match channel 11 +#define mskCT16_MR11IC mskCT16_MR11IF +#define mskCT16_MR12IF (0x1<<12) //[12:12] Interrupt flag for match channel 12 +#define mskCT16_MR12IC mskCT16_MR12IF +#define mskCT16_MR13IF (0x1<<13) //[13:13] Interrupt flag for match channel 13 +#define mskCT16_MR13IC mskCT16_MR13IF +#define mskCT16_MR14IF (0x1<<14) //[14:14] Interrupt flag for match channel 14 +#define mskCT16_MR14IC mskCT16_MR14IF +#define mskCT16_MR15IF (0x1<<15) //[15:15] Interrupt flag for match channel 15 +#define mskCT16_MR15IC mskCT16_MR15IF +#define mskCT16_MR16IF (0x1<<16) //[16:16] Interrupt flag for match channel 16 +#define mskCT16_MR16IC mskCT16_MR16IF +#define mskCT16_MR17IF (0x1<<17) //[17:17] Interrupt flag for match channel 17 +#define mskCT16_MR17IC mskCT16_MR17IF +#define mskCT16_MR18IF (0x1<<18) //[18:18] Interrupt flag for match channel 18 +#define mskCT16_MR18IC mskCT16_MR18IF +#define mskCT16_MR19IF (0x1<<19) //[19:19] Interrupt flag for match channel 19 +#define mskCT16_MR19IC mskCT16_MR19IF +#define mskCT16_MR20IF (0x1<<20) //[20:20] Interrupt flag for match channel 20 +#define mskCT16_MR20IC mskCT16_MR20IF +#define mskCT16_MR21IF (0x1<<21) //[21:21] Interrupt flag for match channel 21 +#define mskCT16_MR21IC mskCT16_MR21IF +#define mskCT16_MR22IF (0x1<<22) //[22:22] Interrupt flag for match channel 22 +#define mskCT16_MR22IC mskCT16_MR22IF +#define mskCT16_MR23IF (0x1<<23) //[23:23] Interrupt flag for match channel 23 +#define mskCT16_MR23IC mskCT16_MR23IF +#define mskCT16_MR24IF (0x1<<24) //[24:24] Interrupt flag for match channel 24 +#define mskCT16_MR24IC mskCT16_MR24IF +#define mskCT16_CAP0IF (0x1<<25) //[25:25] Interrupt flag for capture channel 25 +#define mskCT16_CAP0IC mskCT16_CAP0IF +/*_____ M A C R O S ________________________________________________________*/ + +#endif //*__SN32F2XX_CT16_H diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.c b/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.c new file mode 100644 index 00000000..492e24a5 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.c @@ -0,0 +1,146 @@ +/******************** (C) COPYRIGHT 2013 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2013/12 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: CT16B0 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include "sn32_ct.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +volatile uint32_t iwCT16B0_IrqEvent = 0x00; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS + +void CT16B0_Init (void); +void CT16B0_NvicEnable (void); +void CT16B0_NvicDisable (void); + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ +/***************************************************************************** +* Function : CT16B0_Init +* Description : Initialization of CT16B0 timer +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B0_Init (void) +{ + //Enable P_CLOCK for CT16B0. + sys1EnableCT16B0(); + + //CT16B0 PCLK prescalar setting + // SN_SYS1->APBCP1_b.CT16B0PRE = 0x00; //PCLK = HCLK/1 + //SN_SYS1->APBCP0_b.CT16B0PRE = 0x01; //PCLK = HCLK/2 + //SN_SYS1->APBCP0_b.CT16B0PRE = 0x02; //PCLK = HCLK/4 + //SN_SYS1->APBCP0_b.CT16B0PRE = 0x03; //PCLK = HCLK/8 + //SN_SYS1->APBCP0_b.CT16B0PRE = 0x04; //PCLK = HCLK/16 +} +/***************************************************************************** +* Function : CT16B0_ResetTimer +* Description : Reset of CT16B0 timer +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B0_ResetTimer (void) +{ + //Set CT16B0 as the up-counting mode. + SN_CT16B0->TMRCTRL = (mskCT16_CRST); + + // Wait until timer reset done. + while (SN_CT16B0->TMRCTRL & mskCT16_CRST); +} +/***************************************************************************** +* Function : CT16B0_NvicEnable +* Description : Enable CT16B0 timer interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B0_NvicEnable (void) +{ + NVIC_ClearPendingIRQ(CT16B0_IRQn); + NVIC_EnableIRQ(CT16B0_IRQn); + //NVIC_SetPriority(CT16B0_IRQn,0); // Set interrupt priority (default) +} + +/***************************************************************************** +* Function : CT16B0_NvicEnable +* Description : Disable CT16B0 timer interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B0_NvicDisable (void) +{ + NVIC_DisableIRQ(CT16B0_IRQn); +} + + + +/***************************************************************************** +* Function : CT16B0_IRQHandler +* Description : ISR of CT16B0 interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B0_IRQHandler(void) +{ + uint32_t iwRisStatus; + + iwRisStatus = SN_CT16B0->RIS; //Save the interrupt status. + + //Before checking the status, always re-check the interrupt enable register first. + //In practice, user might use only one or two timer interrupt source. + //Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary. + //User can add the directive pair of "#if 0" and "#endif" pair + //to COMMENT the un-used parts to reduce ISR overheads and ROM usage. + + //Check the status in oder. + //MR0 + if (SN_CT16B0->MCTRL_b.MR0IE) //Check if MR0 IE enables? + { + if(iwRisStatus & mskCT16_MR0IF) + { + iwCT16B0_IrqEvent |= mskCT16_MR0IF; + SN_CT16B0->IC = mskCT16_MR0IC; //Clear MR0 match interrupt status + } + } + //CAP0 + if (SN_CT16B0->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables? + { + if(iwRisStatus & mskCT16_CAP0IF) //CAP0 + { + iwCT16B0_IrqEvent |= mskCT16_CAP0IF; + SN_CT16B0->IC = mskCT16_CAP0IC; //Clear CAP0 interrupt status + } + } +} + + + diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.h b/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.h new file mode 100644 index 00000000..6b823738 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.h @@ -0,0 +1,21 @@ +#ifndef __SN32F240_CT16B0_H +#define __SN32F240_CT16B0_H + + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +#define CT16B0_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT16B0 timer and interrupt + //POLLING_METHOD: Enable CT16B0 timer ONLY + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +extern volatile uint32_t iwCT16B0_IrqEvent; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS + +extern void CT16B0_Init(void); +extern void CT16B0_ResetTimer(void); +extern void CT16B0_NvicEnable (void); +extern void CT16B0_NvicDisable (void); +#endif /*__SN32F240_CT16B0_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.c b/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.c new file mode 100644 index 00000000..51176ebd --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.c @@ -0,0 +1,355 @@ +/******************** (C) COPYRIGHT 2013 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2013/12 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: CT16B1 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include "sn32_ct.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +volatile uint32_t iwCT16B1_IrqEvent = 0x00; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS + +void CT16B1_Init (void); +void CT16B1_NvicEnable (void); +void CT16B1_NvicDisable (void); + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ +/***************************************************************************** +* Function : CT16B1_Init +* Description : Initialization of CT16B1 timer +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B1_Init (void) +{ + //Enable P_CLOCK for CT16B1. + sys1EnableCT16B1(); + + //CT16B1 PCLK prescalar setting + //SN_SYS1->APBCP1_b.CT16B1PRE = 0x00; //PCLK = HCLK/1 + //SN_SYS1->APBCP1_b.CT16B1PRE = 0x01; //PCLK = HCLK/2 + //SN_SYS1->APBCP1_b.CT16B1PRE = 0x02; //PCLK = HCLK/4 + //SN_SYS1->APBCP1_b.CT16B1PRE = 0x03; //PCLK = HCLK/8 + //SN_SYS1->APBCP1_b.CT16B1PRE = 0x04; //PCLK = HCLK/16 +} + +/***************************************************************************** +* Function : CT16B1_ResetTimer +* Description : Reset of CT16B1 timer +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B1_ResetTimer (void) +{ + //Set CT16B1 as the up-counting mode. + SN_CT16B1->TMRCTRL = (mskCT16_CRST); + + // Wait until timer reset done. + while (SN_CT16B1->TMRCTRL & mskCT16_CRST); +} + +/***************************************************************************** +* Function : CT16B1_NvicEnable +* Description : Enable CT16B1 timer interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B1_NvicEnable (void) +{ + NVIC_ClearPendingIRQ(CT16B1_IRQn); + NVIC_EnableIRQ(CT16B1_IRQn); + //NVIC_SetPriority(CT16B1_IRQn,0); // Set interrupt priority (default) +} + +/***************************************************************************** +* Function : CT16B1_NvicDisable +* Description : Enable CT16B1 timer interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B1_NvicDisable (void) +{ + NVIC_DisableIRQ(CT16B1_IRQn); +} + +/***************************************************************************** +* Function : CT16B1_IRQHandler +* Description : ISR of CT16B1 interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void CT16B1_IRQHandler(void) +{ + uint32_t iwRisStatus; + + iwRisStatus = SN_CT16B1->RIS; //Save the interrupt status. + + //Before checking the status, always re-check the interrupt enable register first. + //In practice, user might use only one or two timer interrupt source. + //Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary. + //User can add the directive pair of "#if 0" and "#endif" pair + //to COMMENT the un-used parts to reduce ISR overheads and ROM usage. + + //Check the status in oder. + //MR0 + if (SN_CT16B1->MCTRL_b.MR0IE) //Check if MR0 IE enables? + { + if(iwRisStatus & mskCT16_MR0IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR0IF; + SN_CT16B1->IC = mskCT16_MR0IC; //Clear MR0 match interrupt status + } + } + //MR1 + if (SN_CT16B1->MCTRL_b.MR1IE) //Check if MR1 IE enables? + { + if(iwRisStatus & mskCT16_MR1IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR1IF; + SN_CT16B1->IC = mskCT16_MR1IC; //Clear MR1 match interrupt status + } + } + //MR2 + if (SN_CT16B1->MCTRL_b.MR2IE) //Check if MR2 IE enables? + { + if(iwRisStatus & mskCT16_MR2IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR2IF; + SN_CT16B1->IC = mskCT16_MR2IC; //Clear MR2 match interrupt status + } + } + //MR3 + if (SN_CT16B1->MCTRL_b.MR3IE) //Check if MR3 IE enables? + { + if(iwRisStatus & mskCT16_MR3IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR3IF; + SN_CT16B1->IC = mskCT16_MR3IC; //Clear MR3 match interrupt status + } + } + //MR4 + if (SN_CT16B1->MCTRL_b.MR4IE) //Check if MR4 IE enables? + { + if(iwRisStatus & mskCT16_MR4IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR4IF; + SN_CT16B1->IC = mskCT16_MR4IC; //Clear MR4 match interrupt status + } + } + //MR5 + if (SN_CT16B1->MCTRL_b.MR5IE) //Check if MR5 IE enables? + { + if(iwRisStatus & mskCT16_MR5IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR5IF; + SN_CT16B1->IC = mskCT16_MR5IC; //Clear MR5 match interrupt status + } + } + //MR6 + if (SN_CT16B1->MCTRL_b.MR6IE) //Check if MR6 IE enables? + { + if(iwRisStatus & mskCT16_MR6IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR6IF; + SN_CT16B1->IC = mskCT16_MR6IC; //Clear MR6 match interrupt status + } + } + //MR7 + if (SN_CT16B1->MCTRL_b.MR7IE) //Check if MR7 IE enables? + { + if(iwRisStatus & mskCT16_MR7IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR7IF; + SN_CT16B1->IC = mskCT16_MR7IC; //Clear MR7 match interrupt status + } + } + //MR8 + if (SN_CT16B1->MCTRL_b.MR8IE) //Check if MR8 IE enables? + { + if(iwRisStatus & mskCT16_MR8IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR8IF; + SN_CT16B1->IC = mskCT16_MR8IC; //Clear MR8 match interrupt status + } + } + //MR9 + if (SN_CT16B1->MCTRL_b.MR9IE) //Check if MR9 IE enables? + { + if(iwRisStatus & mskCT16_MR9IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR9IF; + SN_CT16B1->IC = mskCT16_MR9IC; //Clear MR9 match interrupt status + } + } + //MR10 + if (SN_CT16B1->MCTRL2_b.MR10IE) //Check if MR10 IE enables? + { + if(iwRisStatus & mskCT16_MR10IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR10IF; + SN_CT16B1->IC = mskCT16_MR10IC; //Clear MR10 match interrupt status + } + } + //MR11 + if (SN_CT16B1->MCTRL2_b.MR11IE) //Check if MR11 IE enables? + { + if(iwRisStatus & mskCT16_MR11IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR11IF; + SN_CT16B1->IC = mskCT16_MR11IC; //Clear MR11 match interrupt status + } + } + //MR12 + if (SN_CT16B1->MCTRL2_b.MR12IE) //Check if MR12 IE enables? + { + if(iwRisStatus & mskCT16_MR12IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR12IF; + SN_CT16B1->IC = mskCT16_MR12IC; //Clear MR12 match interrupt status + } + } + //MR13 + if (SN_CT16B1->MCTRL2_b.MR13IE) //Check if MR13 IE enables? + { + if(iwRisStatus & mskCT16_MR13IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR13IF; + SN_CT16B1->IC = mskCT16_MR13IC; //Clear MR13 match interrupt status + } + } + //MR14 + if (SN_CT16B1->MCTRL2_b.MR14IE) //Check if MR14 IE enables? + { + if(iwRisStatus & mskCT16_MR14IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR14IF; + SN_CT16B1->IC = mskCT16_MR14IC; //Clear MR14 match interrupt status + } + } + //MR15 + if (SN_CT16B1->MCTRL2_b.MR15IE) //Check if MR15 IE enables? + { + if(iwRisStatus & mskCT16_MR15IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR15IF; + SN_CT16B1->IC = mskCT16_MR15IC; //Clear MR15 match interrupt status + } + } + //MR16 + if (SN_CT16B1->MCTRL2_b.MR16IE) //Check if MR16 IE enables? + { + if(iwRisStatus & mskCT16_MR16IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR16IF; + SN_CT16B1->IC = mskCT16_MR16IC; //Clear MR16 match interrupt status + } + } + //MR17 + if (SN_CT16B1->MCTRL2_b.MR17IE) //Check if MR17 IE enables? + { + if(iwRisStatus & mskCT16_MR17IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR17IF; + SN_CT16B1->IC = mskCT16_MR17IC; //Clear MR17 match interrupt status + } + } + //MR18 + if (SN_CT16B1->MCTRL2_b.MR18IE) //Check if MR18 IE enables? + { + if(iwRisStatus & mskCT16_MR18IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR18IF; + SN_CT16B1->IC = mskCT16_MR18IC; //Clear MR18 match interrupt status + } + } + //MR19 + if (SN_CT16B1->MCTRL2_b.MR19IE) //Check if MR19 IE enables? + { + if(iwRisStatus & mskCT16_MR19IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR19IF; + SN_CT16B1->IC = mskCT16_MR19IC; //Clear MR19 match interrupt status + } + } + //MR20 + if (SN_CT16B1->MCTRL3_b.MR20IE) //Check if MR20 IE enables? + { + if(iwRisStatus & mskCT16_MR20IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR20IF; + SN_CT16B1->IC = mskCT16_MR20IC; //Clear MR20 match interrupt status + } + } + //MR21 + if (SN_CT16B1->MCTRL3_b.MR21IE) //Check if MR21 IE enables? + { + if(iwRisStatus & mskCT16_MR21IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR21IF; + SN_CT16B1->IC = mskCT16_MR21IC; //Clear MR21 match interrupt status + } + } + //MR22 + if (SN_CT16B1->MCTRL3_b.MR22IE) //Check if MR22 IE enables? + { + if(iwRisStatus & mskCT16_MR22IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR22IF; + SN_CT16B1->IC = mskCT16_MR22IC; //Clear MR22 match interrupt status + } + } + //MR23 + if (SN_CT16B1->MCTRL3_b.MR23IE) //Check if MR23 IE enables? + { + if(iwRisStatus & mskCT16_MR23IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR23IF; + SN_CT16B1->IC = mskCT16_MR23IC; //Clear MR23 match interrupt status + } + } +#if SN32_CT16B1_CHANNELS > 23 + //MR24 + if (SN_CT16B1->MCTRL3_b.MR24IE) //Check if MR24 IE enables? + { + if(iwRisStatus & mskCT16_MR24IF) + { + iwCT16B1_IrqEvent |= mskCT16_MR24IF; + SN_CT16B1->IC = mskCT16_MR24IC; //Clear MR24 match interrupt status + } + } +#endif +} + + + diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.h b/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.h new file mode 100644 index 00000000..bd7ad697 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.h @@ -0,0 +1,22 @@ +#ifndef __SN32F2XX_CT16B1_H +#define __SN32F2XX_CT16B1_H + + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +#define CT16B1_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT16B1 timer and interrupt + //POLLING_METHOD: Enable CT16B1 timer ONLY + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +extern volatile uint32_t iwCT16B1_IrqEvent; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS + +extern void CT16B1_Init(void); +extern void CT16B1_ResetTimer(void); +extern void CT16B1_NvicEnable(void); +extern void CT16B1_NvicDisable(void); +extern void CT16B1_IRQHandler(void); +#endif /*__SN32F2XX_CT16B1_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/driver.mk b/os/hal/ports/SN32/LLD/SN32F2xx/CT/driver.mk new file mode 100644 index 00000000..bc6c94dd --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/driver.mk @@ -0,0 +1,19 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_CT TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.c +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.c +endif +ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.c +endif +ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.c +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.c +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.c +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.c new file mode 100644 index 00000000..3d262510 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.c @@ -0,0 +1,285 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file CT/hal_gpt_lld.c + * @brief SN32 GPT subsystem low level driver source. + * + * @addtogroup GPT + * @{ + */ + +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ +#define GPT_CLK SN32_HCLK +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief GPTD1 driver identifier. + * @note The driver GPTD1 allocates the complex timer CT16B0 when enabled. + */ +#if SN32_GPT_USE_CT16B0 || defined(__DOXYGEN__) +GPTDriver GPTD1; +#endif + +/** + * @brief GPTD2 driver identifier. + * @note The driver GPTD2 allocates the timer CT16B1 when enabled. + */ +#if SN32_GPT_USE_CT16B1 || defined(__DOXYGEN__) +GPTDriver GPTD2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SN32_GPT_USE_CT16B0 || defined(__DOXYGEN__) +#if !defined(SN32_CT16B0_SUPPRESS_ISR) +#if !defined(SN32_CT16B0_HANDLER) +#error "SN32_CT16B0_HANDLER not defined" +#endif +/** + * @brief CT16B0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(SN32_CT16B0_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD1); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(SN32_CT16B0_SUPPRESS_ISR) */ +#endif /* SN32_GPT_USE_CT16B0 */ + +#if SN32_GPT_USE_CT16B1 || defined(__DOXYGEN__) +#if !defined(SN32_CT16B1_SUPPRESS_ISR) +#if !defined(SN32_CT16B1_HANDLER) +#error "SN32_CT16B1_HANDLER not defined" +#endif +/** + * @brief CT16B1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(SN32_CT16B1_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD2); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(SN32_CT16B1_SUPPRESS_ISR) */ +#endif /* SN32_GPT_USE_CT16B1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) { + +#if SN32_GPT_USE_CT16B0 + /* Driver initialization.*/ + GPTD1.ct = SN32_CT16B0; + gptObjectInit(&GPTD1); +#endif + +#if SN32_GPT_USE_CT16B1 + /* Driver initialization.*/ + GPTD2.ct = SN32_CT16B1; + gptObjectInit(&GPTD2); +#endif +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) { + uint16_t psc; + + if (gptp->state == GPT_STOP) { + /* Clock activation.*/ +#if SN32_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + sys1EnableCT16B0(); + CT16B0_ResetTimer(); +#if !defined(SN32_CT16B0_SUPPRESS_ISR) + nvicEnableVector(SN32_CT16B0_NUMBER, SN32_GPT_CT16B0_IRQ_PRIORITY); +#endif + gptp->clock = GPT_CLK; + } +#endif + +#if SN32_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + sys1EnableCT16B1(); + CT16B1_ResetTimer(); +#if !defined(SN32_CT16B1_SUPPRESS_ISR) + nvicEnableVector(SN32_CT16B1_NUMBER, SN32_GPT_CT16B1_IRQ_PRIORITY); +#endif + gptp->clock = GPT_CLK; + } +#endif + } + + /* Prescaler value calculation.*/ + psc = (uint8_t)((gptp->clock / gptp->config->frequency) - 1); + osalDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock, + "invalid frequency"); + + /* Timer configuration.*/ + gptp->ct->TMRCTRL = CT16_CEN_DIS; /* Initially stopped. */ + gptp->ct->CNTCTRL = gptp->config->cntctrl; + gptp->ct->PRE = psc; /* Prescaler value. */ + gptp->ct->IC &= 0x1FFFFFF; /* Clear pending IRQs. */ +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) { + + if (gptp->state == GPT_READY) { + gptp->ct->TMRCTRL = CT16_CEN_DIS; /* Timer disabled. */ + gptp->ct->IC &= 0x1FFFFFF; /* Clear pending IRQs. */ + +#if SN32_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { +#if !defined(SN32_CT16B0_SUPPRESS_ISR) + nvicDisableVector(SN32_CT16B0_NUMBER); +#endif + sys1DisableCT16B0(); + } +#endif + +#if SN32_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { +#if !defined(SN32_CT16B1_SUPPRESS_ISR) + nvicDisableVector(SN32_CT16B1_NUMBER); +#endif + sys1DisableCT16B1(); + } +#endif + } +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { + + gptp->ct->MR0 = (uint32_t)(interval - 1U); /* Time constant. */ + gptp->ct->TMRCTRL = mskCT16_CRST; /* Reset counter. */ + gptp->ct->IC &= 0x1FFFFFF; /* Clear pending IRQs. */ + if (NULL != gptp->config->callback) + gptp->ct->MCTRL |= mskCT16_MR0IE_EN; + gptp->ct->TMRCTRL |= mskCT16_CEN_EN; +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) { + + gptp->ct->TMRCTRL = CT16_CEN_DIS; /* Initially stopped. */ + gptp->ct->IC &= 0x1FFFFFF; /* Clear pending IRQs. */ + gptp->ct->MCTRL &= ~mskCT16_MR0IE_EN; /* Disable the interrupt */ + +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + + gptp->ct->MR0 = (uint32_t)(interval - 1U); /* Time constant. */ + gptp->ct->IC &= 0x1FFFFFF; /* Clear pending IRQs. */ + gptp->ct->MCTRL = (mskCT16_MR0IE_EN | mskCT16_MR0STOP_EN); + gptp->ct->TMRCTRL |= mskCT16_CEN_EN; + while (!(gptp->ct->RIS & mskCT16_MR0IF)) + ; + gptp->ct->IC &= 0x1FFFFFF; /* Clear pending IRQs. */ +} + +/** + * @brief Shared IRQ handler. + * + * @param[in] gptp pointer to a @p GPTDriver object + * + * @notapi + */ +void gpt_lld_serve_interrupt(GPTDriver *gptp) { + + gptp->ct->IC &= 0x1FFFFFF; + if (gptp->state == GPT_ONESHOT) { + gptp->state = GPT_READY; /* Back in GPT_READY state. */ + gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */ + } + gptp->config->callback(gptp); +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.h new file mode 100644 index 00000000..cdfb960d --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.h @@ -0,0 +1,269 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file CT/hal_gpt_lld.h + * @brief SN32 GPT subsystem low level driver header. + * + * @addtogroup GPT + * @{ + */ + +#ifndef HAL_GPT_LLD_H +#define HAL_GPT_LLD_H + +#include "sn32_ct.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief GPTD1 driver enable switch. + * @details If set to @p TRUE the support for GPTD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(SN32_GPT_USE_CT16B0) || defined(__DOXYGEN__) +#define SN32_GPT_USE_CT16B0 FALSE +#endif + +/** + * @brief GPTD2 driver enable switch. + * @details If set to @p TRUE the support for GPTD2 is included. + * @note The default is @p TRUE. + */ +#if !defined(SN32_GPT_USE_CT16B1) || defined(__DOXYGEN__) +#define SN32_GPT_USE_CT16B1 FALSE +#endif + +/** + * @brief GPTD1 interrupt priority level setting. + */ +#if !defined(SN32_GPT_CT16B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SN32_GPT_CT16B0_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPTD2 interrupt priority level setting. + */ +#if !defined(SN32_GPT_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SN32_GPT_CT16B1_IRQ_PRIORITY 3 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !defined(SN32_HAS_CT16B0) +#define SN32_HAS_CT16B0 FALSE +#endif + +#if !defined(SN32_HAS_CT16B1) +#define SN32_HAS_CT16B1 FALSE +#endif + +#if SN32_GPT_USE_CT16B0 && !SN32_HAS_CT16B0 +#error "CT16B0 not present in the selected device" +#endif + +#if SN32_GPT_USE_CT16B1 && !SN32_HAS_CT16B1 +#error "CT16B1 not present in the selected device" +#endif + +#if !SN32_GPT_USE_CT16B0 && !SN32_GPT_USE_CT16B0 && \ + !SN32_GPT_USE_CT16B1 && !SN32_GPT_USE_CT16B1 +#error "GPT driver activated but no CT16 peripheral assigned" +#endif + +/* Checks on allocation of CT16Bx units.*/ +#if SN32_GPT_USE_CT16B0 +#if defined(SN32_CT16B0_IS_USED) +#error "GPTD1 requires CT16B0 but the timer is already used" +#else +#define SN32_CT16B0_IS_USED +#endif +#endif + +#if SN32_GPT_USE_CT16B1 +#if defined(SN32_CT16B1_IS_USED) +#error "GPTD2 requires CT16B1 but the timer is already used" +#else +#define SN32_CT16B1_IS_USED +#endif +#endif + +/* IRQ priority checks.*/ +#if SN32_GPT_USE_CT16B0 && !defined(SN32_CT16B0_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(SN32_GPT_CT16B0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to CT16B0" +#endif + +#if SN32_GPT_USE_CT16B1 && !defined(SN32_CT16B1_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(SN32_GPT_CT16B1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to CT16B1" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint16_t gptcnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + * @note This callback can be set to @p NULL but in that case the + * one-shot mode cannot be used. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ + /** + * @brief CT16 CNTCTRL register initialization data. + * @note The value of this field should normally be equal to zero. + */ + uint32_t cntctrl; +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver { + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; +#if defined(GPT_DRIVER_EXT_FIELDS) + GPT_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + uint32_t clock; + /** + * @brief Pointer to the CT registers block. + */ + sn32_ct_t *ct; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the interval of GPT peripheral. + * @details This function changes the interval of a running GPT unit. + * @pre The GPT unit must be running in continuous mode. + * @post The GPT unit interval is changed to the new value. + * @note The function has effect at the next cycle start. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @param[in] interval new cycle time in timer ticks + * + * @notapi + */ +#define gpt_lld_change_interval(gptp, interval) \ + ((gptp)->ct->MR0 = (uint32_t)((interval) - 1U)) + +/** + * @brief Returns the interval of GPT peripheral. + * @pre The GPT unit must be running in continuous mode. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @return The current interval. + * + * @notapi + */ +#define gpt_lld_get_interval(gptp) ((gptcnt_t)((gptp)->ct->MR0 + 1U)) + +/** + * @brief Returns the counter value of GPT peripheral. + * @pre The GPT unit must be running in continuous mode. + * @note The nature of the counter is not defined, it may count upward + * or downward, it could be continuously running or not. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @return The current counter value. + * + * @notapi + */ +#define gpt_lld_get_counter(gptp) ((gptcnt_t)(gptp)->ct->TC) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SN32_GPT_USE_CT16B0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD1; +#endif + +#if SN32_GPT_USE_CT16B1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void gpt_lld_init(void); + void gpt_lld_start(GPTDriver *gptp); + void gpt_lld_stop(GPTDriver *gptp); + void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); + void gpt_lld_stop_timer(GPTDriver *gptp); + void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); + void gpt_lld_serve_interrupt(GPTDriver *gptp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* HAL_GPT_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.c new file mode 100644 index 00000000..f871a1f3 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.c @@ -0,0 +1,1055 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file CT/hal_pwm_lld.c + * @brief SN32 PWM subsystem low level driver header. + * + * @addtogroup PWM + * @{ + */ + +#include "hal.h" + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ +#define PWM_CLK SN32_HCLK +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief PWMD1 driver identifier. + * @note The driver PWMD1 allocates the complex timer CT16B1 when enabled. + */ +#if SN32_PWM_USE_CT16B1 || defined(__DOXYGEN__) +PWMDriver PWMD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SN32_PWM_USE_CT16B1 || defined(__DOXYGEN__) +#if !defined(SN32_CT16B1_SUPPRESS_ISR) +#if !defined(SN32_CT16B1_HANDLER) +#error "SN32_CT16B1_HANDLER not defined" +#endif +/** + * @brief CT16B1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(SN32_CT16B1_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + pwm_lld_serve_interrupt(&PWMD1); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(SN32_CT16B0_SUPPRESS_ISR) */ +#endif /* SN32_PWM_USE_CT16B1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level PWM driver initialization. + * + * @notapi + */ +void pwm_lld_init(void) { + +#if SN32_PWM_USE_CT16B1 + /* Driver initialization.*/ + pwmObjectInit(&PWMD1); + PWMD1.channels = PWM_CHANNELS; + PWMD1.ct = SN32_CT16B1; +#endif +} + +/** + * @brief Configures and activates the PWM peripheral. + * @note Starting a driver that is already in the @p PWM_READY state + * disables all the active channels. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_start(PWMDriver *pwmp) { + uint32_t psc; + uint32_t pwmctrl; + uint32_t pwmctrl2; + uint32_t pwmen; + uint32_t pwmioen; + + if (pwmp->state == PWM_STOP) { + /* Clock activation and timer reset.*/ +#if SN32_PWM_USE_CT16B1 + if (&PWMD1 == pwmp) { + sys1EnableCT16B1(); + CT16B1_ResetTimer(); +#if !defined(SN32_CT16B1_SUPPRESS_ISR) + nvicEnableVector(SN32_CT16B1_NUMBER, SN32_PWM_CT16B1_IRQ_PRIORITY); +#endif + pwmp->clock = PWM_CLK; + } +#endif + +#if defined(SN32F240B) + /* PFPA - Map all PWM outputs to their PWM A pins */ + SN_PFPA->CT16B1 = 0x00000000; + /* PFPA assignment for PWM B-pin mapping.*/ + for(uint8_t i=0; iconfig->channels[i].pfpamsk != 0) { + SN_PFPA->CT16B1 |= (1<config->channels[0].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl |= mskCT16_PWM0MODE_1; + pwmen |= mskCT16_PWM0EN_EN; + pwmioen |= mskCT16_PWM0IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl |= mskCT16_PWM0MODE_2; + pwmen |= mskCT16_PWM0EN_EN; + pwmioen |= mskCT16_PWM0IOEN_EN; + break; + } + switch (pwmp->config->channels[1].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl |= mskCT16_PWM1MODE_1; + pwmen |= mskCT16_PWM1EN_EN; + pwmioen |= mskCT16_PWM1IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl |= mskCT16_PWM1MODE_2; + pwmen |= mskCT16_PWM1EN_EN; + pwmioen |= mskCT16_PWM1IOEN_EN; + break; + } + switch (pwmp->config->channels[2].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl |= mskCT16_PWM2MODE_1; + pwmen |= mskCT16_PWM2EN_EN; + pwmioen |= mskCT16_PWM2IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl |= mskCT16_PWM2MODE_2; + pwmen |= mskCT16_PWM2EN_EN; + pwmioen |= mskCT16_PWM2IOEN_EN; + break; + } + switch (pwmp->config->channels[3].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl |= mskCT16_PWM3MODE_1; + pwmen |= mskCT16_PWM3EN_EN; + pwmioen |= mskCT16_PWM3IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl |= mskCT16_PWM3MODE_2; + pwmen |= mskCT16_PWM3EN_EN; + pwmioen |= mskCT16_PWM3IOEN_EN; + break; + } + switch (pwmp->config->channels[4].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl |= mskCT16_PWM4MODE_1; + pwmen |= mskCT16_PWM4EN_EN; + pwmioen |= mskCT16_PWM4IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl |= mskCT16_PWM4MODE_2; + pwmen |= mskCT16_PWM4EN_EN; + pwmioen |= mskCT16_PWM4IOEN_EN; + break; + } + switch (pwmp->config->channels[5].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl |= mskCT16_PWM5MODE_1; + pwmen |= mskCT16_PWM5EN_EN; + pwmioen |= mskCT16_PWM5IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl |= mskCT16_PWM5MODE_2; + pwmen |= mskCT16_PWM5EN_EN; + pwmioen |= mskCT16_PWM5IOEN_EN; + break; + } + switch (pwmp->config->channels[6].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl |= mskCT16_PWM6MODE_1; + pwmen |= mskCT16_PWM6EN_EN; + pwmioen |= mskCT16_PWM6IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl |= mskCT16_PWM6MODE_2; + pwmen |= mskCT16_PWM6EN_EN; + pwmioen |= mskCT16_PWM6IOEN_EN; + break; + } + switch (pwmp->config->channels[7].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl |= mskCT16_PWM7MODE_1; + pwmen |= mskCT16_PWM7EN_EN; + pwmioen |= mskCT16_PWM7IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl |= mskCT16_PWM7MODE_2; + pwmen |= mskCT16_PWM7EN_EN; + pwmioen |= mskCT16_PWM7IOEN_EN; + break; + } + switch (pwmp->config->channels[8].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl |= mskCT16_PWM8MODE_1; + pwmen |= mskCT16_PWM8EN_EN; + pwmioen |= mskCT16_PWM8IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl |= mskCT16_PWM8MODE_2; + pwmen |= mskCT16_PWM8EN_EN; + pwmioen |= mskCT16_PWM8IOEN_EN; + break; + } + switch (pwmp->config->channels[9].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl |= mskCT16_PWM9MODE_1; + pwmen |= mskCT16_PWM9EN_EN; + pwmioen |= mskCT16_PWM9IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl |= mskCT16_PWM9MODE_2; + pwmen |= mskCT16_PWM9EN_EN; + pwmioen |= mskCT16_PWM9IOEN_EN; + break; + } + switch (pwmp->config->channels[10].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl |= mskCT16_PWM10MODE_1; + pwmen |= mskCT16_PWM10EN_EN; + pwmioen |= mskCT16_PWM10IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl |= mskCT16_PWM10MODE_2; + pwmen |= mskCT16_PWM10EN_EN; + pwmioen |= mskCT16_PWM10IOEN_EN; + break; + } + switch (pwmp->config->channels[11].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl |= mskCT16_PWM11MODE_1; + pwmen |= mskCT16_PWM11EN_EN; + pwmioen |= mskCT16_PWM11IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl |= mskCT16_PWM11MODE_2; + pwmen |= mskCT16_PWM11EN_EN; + pwmioen |= mskCT16_PWM11IOEN_EN; + break; + } + switch (pwmp->config->channels[12].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl |= mskCT16_PWM12MODE_1; + pwmen |= mskCT16_PWM12EN_EN; + pwmioen |= mskCT16_PWM12IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl |= mskCT16_PWM12MODE_2; + pwmen |= mskCT16_PWM12EN_EN; + pwmioen |= mskCT16_PWM12IOEN_EN; + break; + } + switch (pwmp->config->channels[13].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl |= mskCT16_PWM13MODE_1; + pwmen |= mskCT16_PWM13EN_EN; + pwmioen |= mskCT16_PWM13IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl |= mskCT16_PWM13MODE_2; + pwmen |= mskCT16_PWM13EN_EN; + pwmioen |= mskCT16_PWM13IOEN_EN; + break; + } + switch (pwmp->config->channels[14].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl |= mskCT16_PWM14MODE_1; + pwmen |= mskCT16_PWM14EN_EN; + pwmioen |= mskCT16_PWM14IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl |= mskCT16_PWM14MODE_2; + pwmen |= mskCT16_PWM14EN_EN; + pwmioen |= mskCT16_PWM14IOEN_EN; + break; + } + switch (pwmp->config->channels[15].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl |= mskCT16_PWM15MODE_1; + pwmen |= mskCT16_PWM15EN_EN; + pwmioen |= mskCT16_PWM15IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl |= mskCT16_PWM15MODE_2; + pwmen |= mskCT16_PWM15EN_EN; + pwmioen |= mskCT16_PWM15IOEN_EN; + break; + } + switch (pwmp->config->channels[16].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl2 |= mskCT16_PWM16MODE_1; + pwmen |= mskCT16_PWM16EN_EN; + pwmioen |= mskCT16_PWM16IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl2 |= mskCT16_PWM16MODE_2; + pwmen |= mskCT16_PWM16EN_EN; + pwmioen |= mskCT16_PWM16IOEN_EN; + break; + } + switch (pwmp->config->channels[17].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl2 |= mskCT16_PWM17MODE_1; + pwmen |= mskCT16_PWM17EN_EN; + pwmioen |= mskCT16_PWM17IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl2 |= mskCT16_PWM17MODE_2; + pwmen |= mskCT16_PWM17EN_EN; + pwmioen |= mskCT16_PWM17IOEN_EN; + break; + } + switch (pwmp->config->channels[18].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl2 |= mskCT16_PWM18MODE_1; + pwmen |= mskCT16_PWM18EN_EN; + pwmioen |= mskCT16_PWM18IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl2 |= mskCT16_PWM18MODE_2; + pwmen |= mskCT16_PWM18EN_EN; + pwmioen |= mskCT16_PWM18IOEN_EN; + break; + } + switch (pwmp->config->channels[19].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl2 |= mskCT16_PWM19MODE_1; + pwmen |= mskCT16_PWM19EN_EN; + pwmioen |= mskCT16_PWM19IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl2 |= mskCT16_PWM19MODE_2; + pwmen |= mskCT16_PWM19EN_EN; + pwmioen |= mskCT16_PWM19IOEN_EN; + break; + } + switch (pwmp->config->channels[20].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl2 |= mskCT16_PWM20MODE_1; + pwmen |= mskCT16_PWM20EN_EN; + pwmioen |= mskCT16_PWM20IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl2 |= mskCT16_PWM20MODE_2; + pwmen |= mskCT16_PWM20EN_EN; + pwmioen |= mskCT16_PWM20IOEN_EN; + break; + } + switch (pwmp->config->channels[21].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl2 |= mskCT16_PWM21MODE_1; + pwmen |= mskCT16_PWM21EN_EN; + pwmioen |= mskCT16_PWM21IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl2 |= mskCT16_PWM21MODE_2; + pwmen |= mskCT16_PWM21EN_EN; + pwmioen |= mskCT16_PWM21IOEN_EN; + break; + } + switch (pwmp->config->channels[22].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl2 |= mskCT16_PWM22MODE_1; + pwmen |= mskCT16_PWM22EN_EN; + pwmioen |= mskCT16_PWM22IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl2 |= mskCT16_PWM22MODE_2; + pwmen |= mskCT16_PWM22EN_EN; + pwmioen |= mskCT16_PWM22IOEN_EN; + break; + } +#if PWM_CHANNELS > 23 + switch (pwmp->config->channels[23].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_ACTIVE_LOW: + pwmctrl2 |= mskCT16_PWM23MODE_1; + pwmen |= mskCT16_PWM23EN_EN; + pwmioen |= mskCT16_PWM23IOEN_EN; + break; + case PWM_OUTPUT_ACTIVE_HIGH: + pwmctrl2 |= mskCT16_PWM23MODE_2; + pwmen |= mskCT16_PWM23EN_EN; + pwmioen |= mskCT16_PWM23IOEN_EN; + break; + } +#endif + pwmp->ct->PWMCTRL = pwmctrl; + pwmp->ct->PWMCTRL2 = pwmctrl2; + pwmp->ct->PWMENB = pwmen; + pwmp->ct->PWMIOENB = pwmioen; + } + else { + /* Driver re-configuration scenario, it must be stopped first.*/ + pwmp->ct->TMRCTRL = CT16_CEN_DIS; /* Timer disabled. */ + CT16B1_ResetTimer(); /* Counter reset to zero. */ + } + + /* Timer configuration.*/ + psc = (pwmp->clock / pwmp->config->frequency) - 1; + osalDbgAssert((psc <= 0xFF) && /* Prescaler calculation. */ + ((psc + 1) * pwmp->config->frequency) == pwmp->clock, + "invalid frequency"); + pwmp->ct->PRE = psc; +#if PWM_CHANNELS > 23 + pwmp->ct->MR24 = pwmp->period - 1; + +#if SN32_PWM_USE_ONESHOT || defined(__DOXYGEN__) + pwmp->ct->MCTRL3 |= mskCT16_MR24STOP_EN; +#elif !defined(SN32_PWM_NO_RESET) + pwmp->ct->MCTRL3 |= mskCT16_MR24RST_EN; +#endif +#else + pwmp->ct->MR23 = pwmp->period - 1; + +#if SN32_PWM_USE_ONESHOT || defined(__DOXYGEN__) + pwmp->ct->MCTRL3 |= mskCT16_MR23STOP_EN; +#elif !defined(SN32_PWM_NO_RESET) + pwmp->ct->MCTRL3 |= mskCT16_MR23RST_EN; +#endif +#endif + pwmp->ct->IC &= 0x1FFFFFF; /* Clear pending IRQs. */ + + /* Timer configured and started.*/ + pwmp->ct->TMRCTRL |= mskCT16_CEN_EN; +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_stop(PWMDriver *pwmp) { + + /* If in ready state then disables the PWM clock.*/ + if (pwmp->state == PWM_READY) { + pwmp->ct->TMRCTRL = CT16_CEN_DIS; /* Timer disabled. */ + pwmp->ct->IC &= 0x1FFFFFF; /* Clear pending IRQs. */ + +#if SN32_PWM_USE_CT16B1 + if (&PWMD1 == pwmp) { +#if !defined(SN32_CT16B1_SUPPRESS_ISR) + nvicDisableVector(SN32_CT16B1_NUMBER); +#endif + sys1DisableCT16B1(); + } +#endif + } +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note The function has effect at the next cycle start. + * @note Channel notification is not enabled. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @notapi + */ +void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width) { + + /* Changing channel duty cycle on the fly.*/ + switch(channel){ + case 0: + pwmp->ct->MR0 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM0IOEN_EN; + break; + case 1: + pwmp->ct->MR1 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM1IOEN_EN; + break; + case 2: + pwmp->ct->MR2 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM2IOEN_EN; + break; + case 3: + pwmp->ct->MR3 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM3IOEN_EN; + break; + case 4: + pwmp->ct->MR4 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM4IOEN_EN; + break; + case 5: + pwmp->ct->MR5 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM5IOEN_EN; + break; + case 6: + pwmp->ct->MR6 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM6IOEN_EN; + break; + case 7: + pwmp->ct->MR7 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM7IOEN_EN; + break; + case 8: + pwmp->ct->MR8 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM8IOEN_EN; + break; + case 9: + pwmp->ct->MR9 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM9IOEN_EN; + break; + case 10: + pwmp->ct->MR10 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM10IOEN_EN; + break; + case 11: + pwmp->ct->MR11 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM11IOEN_EN; + break; + case 12: + pwmp->ct->MR12 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM12IOEN_EN; + break; + case 13: + pwmp->ct->MR13 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM13IOEN_EN; + break; + case 14: + pwmp->ct->MR14 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM14IOEN_EN; + break; + case 15: + pwmp->ct->MR15 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM15IOEN_EN; + break; + case 16: + pwmp->ct->MR16 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM16IOEN_EN; + break; + case 17: + pwmp->ct->MR17 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM17IOEN_EN; + break; + case 18: + pwmp->ct->MR18 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM18IOEN_EN; + break; + case 19: + pwmp->ct->MR19 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM19IOEN_EN; + break; + case 20: + pwmp->ct->MR20 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM20IOEN_EN; + break; + case 21: + pwmp->ct->MR21 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM21IOEN_EN; + break; + case 22: + pwmp->ct->MR22 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM22IOEN_EN; + break; +#if PWM_CHANNELS > 23 + case 23: + pwmp->ct->MR23 = width; + pwmp->ct->PWMIOENB |= mskCT16_PWM23IOEN_EN; + break; +#endif + default: + ; + } +} + +/** + * @brief Disables a PWM channel and its notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note The function has effect at the next cycle start. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { + + switch(channel){ + case 0: + pwmp->ct->IC |= mskCT16_MR0IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM0IOEN_EN; + break; + case 1: + pwmp->ct->IC |= mskCT16_MR1IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM1IOEN_EN; + break; + case 2: + pwmp->ct->IC |= mskCT16_MR2IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM2IOEN_EN; + break; + case 3: + pwmp->ct->IC |= mskCT16_MR3IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM3IOEN_EN; + break; + case 4: + pwmp->ct->IC |= mskCT16_MR4IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM4IOEN_EN; + break; + case 5: + pwmp->ct->IC |= mskCT16_MR5IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM5IOEN_EN; + break; + case 6: + pwmp->ct->IC |= mskCT16_MR6IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM6IOEN_EN; + break; + case 7: + pwmp->ct->IC |= mskCT16_MR7IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM7IOEN_EN; + break; + case 8: + pwmp->ct->IC |= mskCT16_MR8IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM8IOEN_EN; + break; + case 9: + pwmp->ct->IC |= mskCT16_MR9IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM9IOEN_EN; + break; + case 10: + pwmp->ct->IC |= mskCT16_MR10IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM10IOEN_EN; + break; + case 11: + pwmp->ct->IC |= mskCT16_MR11IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM11IOEN_EN; + break; + case 12: + pwmp->ct->IC |= mskCT16_MR12IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM12IOEN_EN; + break; + case 13: + pwmp->ct->IC |= mskCT16_MR13IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM13IOEN_EN; + break; + case 14: + pwmp->ct->IC |= mskCT16_MR14IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM14IOEN_EN; + break; + case 15: + pwmp->ct->IC |= mskCT16_MR15IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM15IOEN_EN; + break; + case 16: + pwmp->ct->IC |= mskCT16_MR16IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM16IOEN_EN; + break; + case 17: + pwmp->ct->IC |= mskCT16_MR17IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM17IOEN_EN; + break; + case 18: + pwmp->ct->IC |= mskCT16_MR18IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM18IOEN_EN; + break; + case 19: + pwmp->ct->IC |= mskCT16_MR19IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM19IOEN_EN; + break; + case 20: + pwmp->ct->IC |= mskCT16_MR20IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM20IOEN_EN; + break; + case 21: + pwmp->ct->IC |= mskCT16_MR21IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM21IOEN_EN; + break; + case 22: + pwmp->ct->IC |= mskCT16_MR22IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM22IOEN_EN; + break; +#if PWM_CHANNELS > 23 + case 23: + pwmp->ct->IC |= mskCT16_MR23IC; + pwmp->ct->PWMIOENB &= ~mskCT16_PWM23IOEN_EN; + break; +#endif + default: + ; + } +} + +/** + * @brief Enables the periodic activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @note If the notification is already enabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) { +#if PWM_CHANNELS > 23 + pwmp->ct->MCTRL3 |= mskCT16_MR24IE_EN; +#else + pwmp->ct->MCTRL3 |= mskCT16_MR23IE_EN; +#endif +} + +/** + * @brief Disables the periodic activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @note If the notification is already disabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) { +#if PWM_CHANNELS > 23 + pwmp->ct->IC |= mskCT16_MR24IC; + pwmp->ct->MCTRL3 &= ~mskCT16_MR24IE_EN; +#else + pwmp->ct->IC |= mskCT16_MR23IC; + pwmp->ct->MCTRL3 &= ~mskCT16_MR23IE_EN; +#endif +} + +/** + * @brief Enables a channel de-activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @pre The channel must have been activated using @p pwmEnableChannel(). + * @note If the notification is already enabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_enable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel) { + switch(channel){ + case 0: + pwmp->ct->MCTRL |= mskCT16_MR0IE_EN; + break; + case 1: + pwmp->ct->MCTRL |= mskCT16_MR1IE_EN; + break; + case 2: + pwmp->ct->MCTRL |= mskCT16_MR2IE_EN; + break; + case 3: + pwmp->ct->MCTRL |= mskCT16_MR3IE_EN; + break; + case 4: + pwmp->ct->MCTRL |= mskCT16_MR4IE_EN; + break; + case 5: + pwmp->ct->MCTRL |= mskCT16_MR5IE_EN; + break; + case 6: + pwmp->ct->MCTRL |= mskCT16_MR6IE_EN; + break; + case 7: + pwmp->ct->MCTRL |= mskCT16_MR7IE_EN; + break; + case 8: + pwmp->ct->MCTRL |= mskCT16_MR8IE_EN; + break; + case 9: + pwmp->ct->MCTRL |= mskCT16_MR9IE_EN; + break; + case 10: + pwmp->ct->MCTRL2 |= mskCT16_MR10IE_EN; + break; + case 11: + pwmp->ct->MCTRL2 |= mskCT16_MR11IE_EN; + break; + case 12: + pwmp->ct->MCTRL2 |= mskCT16_MR12IE_EN; + break; + case 13: + pwmp->ct->MCTRL2 |= mskCT16_MR13IE_EN; + break; + case 14: + pwmp->ct->MCTRL2 |= mskCT16_MR14IE_EN; + break; + case 15: + pwmp->ct->MCTRL2 |= mskCT16_MR15IE_EN; + break; + case 16: + pwmp->ct->MCTRL2 |= mskCT16_MR16IE_EN; + break; + case 17: + pwmp->ct->MCTRL2 |= mskCT16_MR17IE_EN; + break; + case 18: + pwmp->ct->MCTRL2 |= mskCT16_MR18IE_EN; + break; + case 19: + pwmp->ct->MCTRL2 |= mskCT16_MR19IE_EN; + break; + case 20: + pwmp->ct->MCTRL3 |= mskCT16_MR20IE_EN; + break; + case 21: + pwmp->ct->MCTRL3 |= mskCT16_MR21IE_EN; + break; + case 22: + pwmp->ct->MCTRL3 |= mskCT16_MR22IE_EN; + break; +#if PWM_CHANNELS > 23 + case 23: + pwmp->ct->MCTRL3 |= mskCT16_MR23IE_EN; + break; +#endif + default: + ; + } +} + +/** + * @brief Disables a channel de-activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @pre The channel must have been activated using @p pwmEnableChannel(). + * @note If the notification is already disabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_disable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel) { + switch(channel){ + case 0: + pwmp->ct->MCTRL &= ~mskCT16_MR0IE_EN; + break; + case 1: + pwmp->ct->MCTRL &= ~mskCT16_MR1IE_EN; + break; + case 2: + pwmp->ct->MCTRL &= ~mskCT16_MR2IE_EN; + break; + case 3: + pwmp->ct->MCTRL &= ~mskCT16_MR3IE_EN; + break; + case 4: + pwmp->ct->MCTRL &= ~mskCT16_MR4IE_EN; + break; + case 5: + pwmp->ct->MCTRL &= ~mskCT16_MR5IE_EN; + break; + case 6: + pwmp->ct->MCTRL &= ~mskCT16_MR6IE_EN; + break; + case 7: + pwmp->ct->MCTRL &= ~mskCT16_MR7IE_EN; + break; + case 8: + pwmp->ct->MCTRL &= ~mskCT16_MR8IE_EN; + break; + case 9: + pwmp->ct->MCTRL &= ~mskCT16_MR9IE_EN; + break; + case 10: + pwmp->ct->MCTRL2 &= ~mskCT16_MR10IE_EN; + break; + case 11: + pwmp->ct->MCTRL2 &= ~mskCT16_MR11IE_EN; + break; + case 12: + pwmp->ct->MCTRL2 &= ~mskCT16_MR12IE_EN; + break; + case 13: + pwmp->ct->MCTRL2 &= ~mskCT16_MR13IE_EN; + break; + case 14: + pwmp->ct->MCTRL2 &= ~mskCT16_MR14IE_EN; + break; + case 15: + pwmp->ct->MCTRL2 &= ~mskCT16_MR15IE_EN; + break; + case 16: + pwmp->ct->MCTRL2 &= ~mskCT16_MR16IE_EN; + break; + case 17: + pwmp->ct->MCTRL2 &= ~mskCT16_MR17IE_EN; + break; + case 18: + pwmp->ct->MCTRL2 &= ~mskCT16_MR18IE_EN; + break; + case 19: + pwmp->ct->MCTRL2 &= ~mskCT16_MR19IE_EN; + break; + case 20: + pwmp->ct->MCTRL3 &= ~mskCT16_MR20IE_EN; + break; + case 21: + pwmp->ct->MCTRL3 &= ~mskCT16_MR21IE_EN; + break; + case 22: + pwmp->ct->MCTRL3 &= ~mskCT16_MR22IE_EN; + break; +#if PWM_CHANNELS > 23 + case 23: + pwmp->ct->MCTRL3 &= ~mskCT16_MR23IE_EN; + break; +#endif + default: + ; + }} + +/** + * @brief Common CT IRQ handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_serve_interrupt(PWMDriver *pwmp) { + uint32_t ris; + + ris = pwmp->ct->RIS; + if (((ris & mskCT16_MR0IF) != 0) && + (pwmp->config->channels[0].callback != NULL)) + pwmp->config->channels[0].callback(pwmp); + if (((ris & mskCT16_MR1IF) != 0) && + (pwmp->config->channels[1].callback != NULL)) + pwmp->config->channels[1].callback(pwmp); + if (((ris & mskCT16_MR2IF) != 0) && + (pwmp->config->channels[2].callback != NULL)) + pwmp->config->channels[2].callback(pwmp); + if (((ris & mskCT16_MR3IF) != 0) && + (pwmp->config->channels[3].callback != NULL)) + pwmp->config->channels[3].callback(pwmp); + if (((ris & mskCT16_MR4IF) != 0) && + (pwmp->config->channels[4].callback != NULL)) + pwmp->config->channels[4].callback(pwmp); + if (((ris & mskCT16_MR5IF) != 0) && + (pwmp->config->channels[5].callback != NULL)) + pwmp->config->channels[5].callback(pwmp); + if (((ris & mskCT16_MR6IF) != 0) && + (pwmp->config->channels[6].callback != NULL)) + pwmp->config->channels[6].callback(pwmp); + if (((ris & mskCT16_MR7IF) != 0) && + (pwmp->config->channels[7].callback != NULL)) + pwmp->config->channels[7].callback(pwmp); + if (((ris & mskCT16_MR8IF) != 0) && + (pwmp->config->channels[8].callback != NULL)) + pwmp->config->channels[8].callback(pwmp); + if (((ris & mskCT16_MR9IF) != 0) && + (pwmp->config->channels[9].callback != NULL)) + pwmp->config->channels[9].callback(pwmp); + if (((ris & mskCT16_MR10IF) != 0) && + (pwmp->config->channels[10].callback != NULL)) + pwmp->config->channels[10].callback(pwmp); + if (((ris & mskCT16_MR11IF) != 0) && + (pwmp->config->channels[11].callback != NULL)) + pwmp->config->channels[11].callback(pwmp); + if (((ris & mskCT16_MR12IF) != 0) && + (pwmp->config->channels[12].callback != NULL)) + pwmp->config->channels[12].callback(pwmp); + if (((ris & mskCT16_MR13IF) != 0) && + (pwmp->config->channels[13].callback != NULL)) + pwmp->config->channels[13].callback(pwmp); + if (((ris & mskCT16_MR14IF) != 0) && + (pwmp->config->channels[14].callback != NULL)) + pwmp->config->channels[14].callback(pwmp); + if (((ris & mskCT16_MR15IF) != 0) && + (pwmp->config->channels[15].callback != NULL)) + pwmp->config->channels[15].callback(pwmp); + if (((ris & mskCT16_MR16IF) != 0) && + (pwmp->config->channels[16].callback != NULL)) + pwmp->config->channels[16].callback(pwmp); + if (((ris & mskCT16_MR17IF) != 0) && + (pwmp->config->channels[17].callback != NULL)) + pwmp->config->channels[17].callback(pwmp); + if (((ris & mskCT16_MR18IF) != 0) && + (pwmp->config->channels[18].callback != NULL)) + pwmp->config->channels[18].callback(pwmp); + if (((ris & mskCT16_MR19IF) != 0) && + (pwmp->config->channels[19].callback != NULL)) + pwmp->config->channels[19].callback(pwmp); + if (((ris & mskCT16_MR20IF) != 0) && + (pwmp->config->channels[20].callback != NULL)) + pwmp->config->channels[20].callback(pwmp); + if (((ris & mskCT16_MR21IF) != 0) && + (pwmp->config->channels[21].callback != NULL)) + pwmp->config->channels[21].callback(pwmp); + if (((ris & mskCT16_MR22IF) != 0) && + (pwmp->config->channels[22].callback != NULL)) + pwmp->config->channels[22].callback(pwmp); +#if PWM_CHANNELS > 23 + if (((ris & mskCT16_MR23IF) != 0) && + (pwmp->config->channels[23].callback != NULL)) + pwmp->config->channels[23].callback(pwmp); + if (((ris & mskCT16_MR24IF) != 0) && (pwmp->config->callback != NULL)) + pwmp->config->callback(pwmp); +#else + if (((ris & mskCT16_MR23IF) != 0) && (pwmp->config->callback != NULL)) + pwmp->config->callback(pwmp); +#endif +} + +#endif /* HAL_USE_PWM */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.h new file mode 100644 index 00000000..7c6ea689 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.h @@ -0,0 +1,293 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file CT/hal_pwm_lld.h + * @brief SN32 PWM subsystem low level driver header. + * + * @addtogroup PWM + * @{ + */ + +#ifndef HAL_PWM_LLD_H +#define HAL_PWM_LLD_H + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +#include "sn32_ct.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Number of PWM channels per PWM driver. + */ +#define PWM_CHANNELS SN32_CT16B1_CHANNELS + +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief PWMD1 driver enable switch. + * @details If set to @p TRUE the support for PWMD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(SN32_PWM_USE_CT16B1) || defined(__DOXYGEN__) +#define SN32_PWM_USE_CT16B1 FALSE +#endif + +/** + * @brief PWMD1 interrupt priority level setting. + */ +#if !defined(SN32_PWM_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SN32_PWM_CT16B1_IRQ_PRIORITY 2 +#endif +/** @} */ + +/*===========================================================================*/ +/* Configuration checks. */ +/*===========================================================================*/ + +#if !defined(SN32_HAS_CT16B1) +#define SN32_HAS_CT16B1 FALSE +#endif + +#if SN32_PWM_USE_CT16B1 && !SN32_HAS_CT16B1 +#error "CT16B1 not present in the selected device" +#endif + +#if !SN32_PWM_USE_CT16B1 +#error "PWM driver activated but no CT peripheral assigned" +#endif + +/* Checks on allocation of CT units.*/ +#if SN32_PWM_USE_CT16B1 +#if defined(SN32_CT16B1_IS_USED) +#error "PWMD1 requires CT16B1 but the timer is already used" +#else +#define SN32_CT16B1_IS_USED +#endif +#endif + +/* IRQ priority checks.*/ +#if SN32_PWM_USE_CT16B1 && !defined(SN32_CT16B1_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(SN32_PWM_CT16B1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to CT16B1" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a PWM mode. + */ +typedef uint32_t pwmmode_t; + +/** + * @brief Type of a PWM channel. + */ +typedef uint8_t pwmchannel_t; + +/** + * @brief Type of a channels mask. + */ +typedef uint32_t pwmchnmsk_t; + +/** + * @brief Type of a PWM counter. + */ +typedef uint32_t pwmcnt_t; + +/** + * @brief Type of a PWM driver channel configuration structure. + */ +typedef struct { + /** + * @brief Channel active logic level. + */ + pwmmode_t mode; + /** + * @brief Channel callback pointer. + * @note This callback is invoked on the channel compare event. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /* End of the mandatory fields.*/ + /** + * @brief CT16 PFPA register initialization data. + * @note The value of this field should normally be equal to zero. + */ + uint8_t pfpamsk; +} PWMChannelConfig; + +/** + * @brief Type of a PWM driver configuration structure. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + uint32_t frequency; + /** + * @brief PWM period in ticks. + * @note The low level can use assertions in order to catch invalid + * period specifications. + */ + pwmcnt_t period; + /** + * @brief Periodic callback pointer. + * @note This callback is invoked on PWM counter reset. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /** + * @brief Channels configurations. + */ + PWMChannelConfig channels[PWM_CHANNELS]; + /* End of the mandatory fields.*/ + /** + * @brief CT16 CNTCTRL register initialization data. + * @note The value of this field should normally be equal to zero. + */ + uint32_t cntctrl; +} PWMConfig; + +/** + * @brief Structure representing a PWM driver. + */ +struct PWMDriver { + /** + * @brief Driver state. + */ + pwmstate_t state; + /** + * @brief Current driver configuration data. + */ + const PWMConfig *config; + /** + * @brief Current PWM period in ticks. + */ + pwmcnt_t period; + /** + * @brief Mask of the enabled channels. + */ + pwmchnmsk_t enabled; + /** + * @brief Number of channels in this instance. + */ + pwmchannel_t channels; +#if defined(PWM_DRIVER_EXT_FIELDS) + PWM_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + uint32_t clock; + /** + * @brief Pointer to the CT registers block. + */ + sn32_ct_t *ct; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the period of the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note The function has effect at the next cycle start. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @notapi + */ +#if PWM_CHANNELS > 23 +#define pwm_lld_change_period(pwmp, period) \ + ((pwmp)->ct->MR24 = ((period) - 1)) +#else +#define pwm_lld_change_period(pwmp, period) \ + ((pwmp)->ct->MR23 = ((period) - 1)) +#endif + +/** + * @brief Changes the timer counter of the PWM peripheral. + * @details This function changes the timer counter of a PWM unit that has + * already been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit timer counter is changed to the new value. + * @note The function overrides the TC value of the PWM peripheral + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] counter new timer counter value in bits + * + * @notapi + */ +#define pwm_lld_change_counter(pwmp, counter) \ + ((pwmp)->ct->TC = (counter)) +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SN32_PWM_USE_CT16B1 && !defined(__DOXYGEN__) +extern PWMDriver PWMD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void pwm_lld_init(void); + void pwm_lld_start(PWMDriver *pwmp); + void pwm_lld_stop(PWMDriver *pwmp); + void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); + void pwm_lld_enable_periodic_notification(PWMDriver *pwmp); + void pwm_lld_disable_periodic_notification(PWMDriver *pwmp); + void pwm_lld_enable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel); + void pwm_lld_disable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel); + void pwm_lld_serve_interrupt(PWMDriver *pwmp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM */ + +#endif /* HAL_PWM_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/CT/sn32_ct.h b/os/hal/ports/SN32/LLD/SN32F2xx/CT/sn32_ct.h new file mode 100644 index 00000000..847bf96b --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/CT/sn32_ct.h @@ -0,0 +1,125 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file CT/sn32_ct.h + * @brief SN32 CT units common header. + * @note This file requires definitions from the SN32 header file. + * + * @{ + */ + +#ifndef SN32_CT_H +#define SN32_CT_H + +#include +#include "CT16.h" +#include "CT16B0.h" +#include "CT16B1.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name CT units references + * @{ + */ +#define SN32_CT16B0 ((sn32_ct_t *)SN_CT16B0_BASE) +#define SN32_CT16B1 ((sn32_ct_t *)SN_CT16B1_BASE) +#if defined(SN32F240B) +#define SN32_CT16B1_CHANNELS 24 +#elif defined(SN32F260) +#define SN32_CT16B1_CHANNELS 23 +#else +#error "CT not supported in the selected device" +#endif +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief SN32 CT registers block. + * @note This is the most general known form, not all timers have + * necessarily all registers and bits. + */ +typedef struct { /*!< (@ 0x40002000) SN_CT16Bn Structure */ + volatile uint32_t TMRCTRL; /*!< (@ 0x00000000) Offset:0x00 CT16Bn Timer Control Register */ + volatile uint32_t TC; /*!< (@ 0x00000004) Offset:0x04 CT16Bn Timer Counter Register */ + volatile uint32_t PRE; /*!< (@ 0x00000008) Offset:0x08 CT16Bn Prescale Register */ + volatile uint32_t PC; /*!< (@ 0x0000000C) Offset:0x0C CT16Bn Prescale Counter Register */ + volatile uint32_t CNTCTRL; /*!< (@ 0x00000010) Offset:0x10 CT16Bn Counter Control Register */ + volatile uint32_t MCTRL; /*!< (@ 0x00000014) Offset:0x14 CT16Bn Match Control Register */ + volatile uint32_t MCTRL2; /*!< (@ 0x00000018) Offset:0x18 CT16Bn Match Control Register 2 */ + volatile uint32_t MCTRL3; /*!< (@ 0x0000001C) Offset:0x1C CT16Bn Match Control Register 3 */ + volatile uint32_t MR0; /*!< (@ 0x00000020) Offset:0x20 CT16Bn MR0 Register */ + volatile uint32_t MR1; /*!< (@ 0x00000024) Offset:0x24 CT16Bn MR1 Register */ + volatile uint32_t MR2; /*!< (@ 0x00000028) Offset:0x28 CT16Bn MR2 Register */ + volatile uint32_t MR3; /*!< (@ 0x0000002C) Offset:0x2C CT16Bn MR3 Register */ + volatile uint32_t MR4; /*!< (@ 0x00000030) Offset:0x30 CT16Bn MR4 Register */ + volatile uint32_t MR5; /*!< (@ 0x00000034) Offset:0x34 CT16Bn MR5 Register */ + volatile uint32_t MR6; /*!< (@ 0x00000038) Offset:0x38 CT16Bn MR6 Register */ + volatile uint32_t MR7; /*!< (@ 0x0000003C) Offset:0x3C CT16Bn MR7 Register */ + volatile uint32_t MR8; /*!< (@ 0x00000040) Offset:0x40 CT16Bn MR8 Register */ + volatile uint32_t MR9; /*!< (@ 0x00000044) Offset:0x44 CT16Bn MR9 Register */ + volatile uint32_t MR10; /*!< (@ 0x00000048) Offset:0x48 CT16Bn MR10 Register */ + volatile uint32_t MR11; /*!< (@ 0x0000004C) Offset:0x4C CT16Bn MR11 Register */ + volatile uint32_t MR12; /*!< (@ 0x00000050) Offset:0x50 CT16Bn MR12 Register */ + volatile uint32_t MR13; /*!< (@ 0x00000054) Offset:0x54 CT16Bn MR13 Register */ + volatile uint32_t MR14; /*!< (@ 0x00000058) Offset:0x58 CT16Bn MR14 Register */ + volatile uint32_t MR15; /*!< (@ 0x0000005C) Offset:0x5C CT16Bn MR15 Register */ + volatile uint32_t MR16; /*!< (@ 0x00000060) Offset:0x60 CT16Bn MR16 Register */ + volatile uint32_t MR17; /*!< (@ 0x00000064) Offset:0x64 CT16Bn MR17 Register */ + volatile uint32_t MR18; /*!< (@ 0x00000068) Offset:0x68 CT16Bn MR18 Register */ + volatile uint32_t MR19; /*!< (@ 0x0000006C) Offset:0x6C CT16Bn MR19 Register */ + volatile uint32_t MR20; /*!< (@ 0x00000070) Offset:0x70 CT16Bn MR20 Register */ + volatile uint32_t MR21; /*!< (@ 0x00000074) Offset:0x74 CT16Bn MR21 Register */ + volatile uint32_t MR22; /*!< (@ 0x00000078) Offset:0x78 CT16Bn MR22 Register */ + volatile uint32_t MR23; /*!< (@ 0x0000007C) Offset:0x7C CT16Bn MR23 Register */ + volatile uint32_t MR24; /*!< (@ 0x00000080) Offset:0x80 CT16Bn MR24 Register */ + volatile uint32_t CAP0; /*!< (@ 0x00000084) Offset:0x84 CT16Bn CAP0 Register */ + volatile uint32_t EM; /*!< (@ 0x00000088) Offset:0x88 CT16Bn External Match Register */ + volatile uint32_t EMC; /*!< (@ 0x0000008C) Offset:0x8C CT16Bn External Match Control register */ + volatile uint32_t EMC2; /*!< (@ 0x00000090) Offset:0x90 CT16Bn External Match Control register 2 */ + volatile uint32_t PWMCTRL; /*!< (@ 0x00000094) Offset:0x94 CT16Bn PWM Control Register */ + volatile uint32_t PWMCTRL2; /*!< (@ 0x00000098) Offset:0x98 CT16Bn PWM Control Register 2 */ + volatile uint32_t PWMENB; /*!< (@ 0x0000009C) Offset:0x9C CT16Bn PWM Enable register */ + volatile uint32_t PWMIOENB; /*!< (@ 0x000000A0) Offset:0xA0 CT16Bn PWM IO Enable register */ + volatile uint32_t RIS; /*!< (@ 0x000000A4) Offset:0xA4 CT16Bn Raw Interrupt Status Register */ + volatile uint32_t IC; /*!< (@ 0x000000A8) Offset:0xA8 CT16Bn Interrupt Clear Register */ +} sn32_ct_t; /*!< Size = 172 (0xac) */ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#endif /* SN32_CT_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/FLASH/Flash.c b/os/hal/ports/SN32/LLD/SN32F2xx/FLASH/Flash.c new file mode 100644 index 00000000..f573bf7a --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/FLASH/Flash.c @@ -0,0 +1,140 @@ +/******************** (C) COPYRIGHT 2017 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2017/07 +* AUTHOR: SA1 +* IC: SN32F240B +* DESCRIPTION: Flash related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2017/07/07 SA1 First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include "Flash.h" + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + +/*_____ D E F I N I T I O N S ______________________________________________*/ +#define SN32_JUMPLOADER_SIZE 0x200 + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ +/***************************************************************************** +* Function : FLASH_EraseSector +* Description : Erase assigned sector address in Flash ROM +* Input : adr - Sector start address +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +FLASH_Status FLASH_EraseSector (uint32_t adr) +{ + // never touch the jumploader + if (adr < SN32_JUMPLOADER_SIZE) return FLASH_FAIL; + + SN_FLASH->CTRL = FLASH_PER; // Page Erase Enabled + SN_FLASH->ADDR = adr; // Page Address + + FLASH_WAIT_FOR_DONE + + SN_FLASH->CTRL |= FLASH_START; // Start Erase + + FLASH_WAIT_FOR_DONE + + return (FLASH_OKAY); +} + + +/***************************************************************************** +* Function : Flash_ProgramPage +* Description : Program assigned page in Flash ROM +* Input : adr - Page start address (word-alignment) of Flash +* sz - Content size to be programmed (Bytes) +* Data - the Source data +* Output : None +* Return : FLASH_OKAY or FLASH_FAIL +* Note : None +*****************************************************************************/ +FLASH_Status FLASH_ProgramPage (uint32_t adr, uint32_t sz, uint32_t Data) +{ + // never touch the jumploader + if (adr < SN32_JUMPLOADER_SIZE) return FLASH_FAIL; + + SN_FLASH->CTRL = FLASH_PG; // Programming Enabled + SN_FLASH->ADDR = adr; + + FLASH_WAIT_FOR_DONE + + *(uint32_t*)adr = Data; + + while (sz) { + + SN_FLASH->DATA = Data; + + FLASH_WAIT_FOR_DONE + + // Go to next Word + adr += 4; + sz -= 4; + } + + // Check for Errors + if ((SN_FLASH->STATUS & FLASH_ERR) == FLASH_ERR) { + SN_FLASH->STATUS = 0; + return (FLASH_FAIL); + } + + SN_FLASH->CTRL |= FLASH_START; // Start Program + + FLASH_WAIT_FOR_DONE + + // Check for Errors + if ((SN_FLASH->STATUS & FLASH_ERR) == FLASH_ERR) { + SN_FLASH->STATUS = 0; + return (FLASH_FAIL); + } + + return (FLASH_OKAY); +} + +/***************************************************************************** +* Function : FLASH_ProgramWord +* Description : Program a word at a specified address +* Input : adr - Page start address (word-alignment) of Flash +* Data - the Source data +* Output : None +* Return : FLASH_OKAY or FLASH_ERR +* Note : None +*****************************************************************************/ +FLASH_Status FLASH_ProgramDWord(uint32_t adr, uint32_t Data) { + FLASH_Status status = FLASH_ProgramPage(adr, 4, Data); + + return status; +} + +/***************************************************************************** +* Function : FLASH_Checksum +* Description : Calculate Checksum in Flash ROM +* Input : None +* Output : Checksum of User ROM +* Return : None +* Note : None +*****************************************************************************/ +uint16_t FLASH_Checksum (void) +{ + SN_FLASH->CTRL = FLASH_CHK; + + FLASH_WAIT_FOR_DONE + + return (uint16_t) (SN_FLASH->CHKSUM); +} diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/FLASH/Flash.h b/os/hal/ports/SN32/LLD/SN32F2xx/FLASH/Flash.h new file mode 100644 index 00000000..2a2973dd --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/FLASH/Flash.h @@ -0,0 +1,48 @@ +#ifndef __SN32F2XX_FLASH_H +#define __SN32F2XX_FLASH_H + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +//FLASH HW +#define FLASH_PAGE_SIZE 64 +#define FLASH_F240B_MAX_ROM_SIZE 0xFFFF + + +// Flash Control Register definitions +#define FLASH_PG 0x00000001 +#define FLASH_PER 0x00000002 +#define FLASH_MER 0x00000004 +#define FLASH_START 0x00000040 +#define FLASH_CHK 0x00000080 + +// Flash Status Register definitions +#define FLASH_BUSY 0x00000001 +#define FLASH_ERR 0x00000004 + +#define FLASH_WAIT_FOR_DONE while (SN_FLASH->STATUS & FLASH_BUSY) {__asm__("NOP");} + + +/*_____ M A C R O S ________________________________________________________*/ + +//Flash Low Power Mode +#define __FLASH_LPM_DISABLE SN_FLASH->LPCTRL = 0x5AFA0000; //HCLK<=12MHz +#define __FLASH_LPM_MEDIUM_MODE SN_FLASH->LPCTRL = 0x5AFA0003; //12MHzLPCTRL = 0x5AFA0004;SN_FLASH->LPCTRL = 0x5AFA0005;SN_FLASH->LPCTRL = 0x5AFA000D; //HCLK>24MHz + +//Flash Status +#define __FLASH_CLEAR_ERROR_STATUS SN_FLASH->STATUS &= ~FLASH_PGERR + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +typedef enum { FLASH_FAIL, FLASH_OKAY} FLASH_Status; + +void FLASH_MassErase (void); +FLASH_Status FLASH_EraseSector (uint32_t); +FLASH_Status FLASH_ProgramPage (uint32_t, uint32_t, uint32_t); +FLASH_Status FLASH_ProgramDWord(uint32_t, uint32_t); +uint16_t FLASH_Checksum(void); + +#endif /* __SN32F2XX_FLASH_H */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/FLASH/driver.mk b/os/hal/ports/SN32/LLD/SN32F2xx/FLASH/driver.mk new file mode 100644 index 00000000..16061a83 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/FLASH/driver.mk @@ -0,0 +1,3 @@ +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/FLASH/Flash.c + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/FLASH \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/GPIO.c b/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/GPIO.c new file mode 100644 index 00000000..dd4bb55b --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/GPIO.c @@ -0,0 +1,762 @@ +/******************** (C) COPYRIGHT 2017 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2017/07 +* AUTHOR: SA1 +* IC: SN32F240B +* DESCRIPTION: GPIO related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2017/07/07 SA1 1. First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include "GPIO.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + +/***************************************************************************** +* Function : GPIO_Init +* Description : GPIO Init +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void GPIO_Init (void) +{ + //P2.0 as Input + GPIO_Mode (GPIO_PORT2, GPIO_PIN0, GPIO_MODE_INPUT); + //P2.0 need to add External Pull-down Resistors for Demo rising edge trigger + //P2.0 as rising edge + GPIO_P2Trigger(GPIO_PIN0, GPIO_IS_EDGE, GPIO_IBS_EDGE_TRIGGER, GPIO_IEV_RISING_EDGE); + GPIO_Interrupt(GPIO_PORT2, GPIO_PIN0, GPIO_IE_EN); + + //P2.1 as Input Pull-up + GPIO_Mode (GPIO_PORT2, GPIO_PIN1, GPIO_MODE_INPUT); + GPIO_Config (GPIO_PORT2, GPIO_PIN1, GPIO_CFG_PULL_UP); + //P2.1 as falling edge + GPIO_P2Trigger(GPIO_PIN1, GPIO_IS_EDGE, GPIO_IBS_EDGE_TRIGGER, GPIO_IEV_FALLING_EDGE); + GPIO_Interrupt(GPIO_PORT2, GPIO_PIN1, GPIO_IE_EN); + + //P2.2 as Input Pull-up + GPIO_Mode (GPIO_PORT2, GPIO_PIN2, GPIO_MODE_INPUT); + GPIO_Config (GPIO_PORT2, GPIO_PIN2, GPIO_CFG_PULL_UP); + //P2.2 as both edge + GPIO_P2Trigger(GPIO_PIN2, GPIO_IS_EDGE, GPIO_IBS_BOTH_EDGE_TRIGGER, GPIO_IEV_RISING_EDGE); + GPIO_Interrupt(GPIO_PORT2, GPIO_PIN2, GPIO_IE_EN); + + //P2.3 as Input + GPIO_Mode (GPIO_PORT2, GPIO_PIN3, GPIO_MODE_INPUT); + //P2.3 need to add External Pull-down Resistors for Demo high level trigger + //P2.3 as high level + GPIO_P2Trigger(GPIO_PIN3, GPIO_IS_EVENT, GPIO_IBS_EDGE_TRIGGER, GPIO_IEV_RISING_EDGE); + GPIO_Interrupt(GPIO_PORT2, GPIO_PIN3, GPIO_IE_EN); + + //P2.4 as Input Pullup + GPIO_Mode (GPIO_PORT2, GPIO_PIN4, GPIO_MODE_INPUT); + GPIO_Config (GPIO_PORT2, GPIO_PIN4, GPIO_CFG_PULL_UP); + //P2.4 as low level trigger + GPIO_P2Trigger(GPIO_PIN4, GPIO_IS_EVENT, GPIO_IBS_EDGE_TRIGGER, GPIO_IEV_FALLING_EDGE); + GPIO_Interrupt(GPIO_PORT2, GPIO_PIN4, GPIO_IE_EN); + + //P2.5 as Output Low + GPIO_Mode (GPIO_PORT2, GPIO_PIN5, GPIO_MODE_OUTPUT); + GPIO_Clr (GPIO_PORT2, GPIO_PIN5); +} + +/***************************************************************************** +* Function : GPIO_Mode +* Description : set GPIO as input or output +* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3 + pin_number - GPIO_PIN0, 1, 2, ...,15 + mode - 0 as Input + 1 as output +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void GPIO_Mode(uint32_t port_number, uint32_t pin_number, uint32_t mode) +{ + uint32_t wGpiomode=0; + switch(port_number){ + case 0: + wGpiomode=(uint32_t)SN_GPIO0->MODE; + wGpiomode&=~(1<<(uint32_t) pin_number); + wGpiomode|=(mode<<(uint32_t) pin_number); + SN_GPIO0->MODE=wGpiomode; + wGpiomode=SN_GPIO0->MODE; //for check + break; + case 1: + wGpiomode=(uint32_t)SN_GPIO1->MODE; + wGpiomode&=~(1<<(uint32_t) pin_number); + wGpiomode|=(mode<<(uint32_t) pin_number); + SN_GPIO1->MODE=wGpiomode; + wGpiomode=SN_GPIO1->MODE; //for check + break; + case 2: + wGpiomode=(uint32_t)SN_GPIO2->MODE; + wGpiomode&=~(1<<(uint32_t) pin_number); + wGpiomode|=(mode<<(uint32_t) pin_number); + SN_GPIO2->MODE=wGpiomode; + wGpiomode=SN_GPIO2->MODE; //for check + break; + case 3: + wGpiomode=(uint32_t)SN_GPIO3->MODE; + wGpiomode&=~(1<<(uint32_t) pin_number); + wGpiomode|=(mode<<(uint32_t) pin_number); + SN_GPIO3->MODE=wGpiomode; + wGpiomode=SN_GPIO3->MODE; //for check + break; + default: + break; + } + return; +} + +/***************************************************************************** +* Function : GPIO_Set +* Description : set GPIO high +* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3 + pin_number - GPIO_PIN0, 1, 2, ...,15 +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void GPIO_Set(uint32_t port_number, uint32_t pin_number) +{ + switch(port_number){ + case 0: + SN_GPIO0->BSET|=(1<BSET|=(1<BSET|=(1<BSET|=(1<BCLR|=(1<BCLR|=(1<BCLR|=(1<BCLR|=(1<IS; + wGpiovalue&=~(1<IS=wGpiovalue; + wGpiovalue=SN_GPIO0->IBS; + wGpiovalue&=~(1<IBS=wGpiovalue; + wGpiovalue=SN_GPIO0->IEV; + wGpiovalue&=~(1<IEV=wGpiovalue; +} + +/***************************************************************************** +* Function : GPIO_P1Trigger +* Description : set GPIO as edge or level trigger +* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3 + pin_number - GPIO_PIN0, 1, 2, ...,15 + is - 0: edge sensitive + 1: event sensitive + ibs - 0: edge trigger + 1: both edge trigger + iev - 0: Rising edges or HIGH level trigger + 1: Falling edges or LOW level trigger +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void GPIO_P1Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev) +{ + uint32_t wGpiovalue=0; + + wGpiovalue=SN_GPIO1->IS; + wGpiovalue&=~(1<IS=wGpiovalue; + wGpiovalue=SN_GPIO1->IBS; + wGpiovalue&=~(1<IBS=wGpiovalue; + wGpiovalue=SN_GPIO1->IEV; + wGpiovalue&=~(1<IEV=wGpiovalue; +} + +/***************************************************************************** +* Function : GPIO_P2Trigger +* Description : set GPIO as edge or level trigger +* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3 + pin_number - GPIO_PIN0, 1, 2, ...,15 + is - 0: edge sensitive + 1: event sensitive + ibs - 0: edge trigger + 1: both edge trigger + iev - 0: Rising edges or HIGH level trigger + 1: Falling edges or LOW level trigger +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void GPIO_P2Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev) +{ + uint32_t wGpiovalue=0; + + wGpiovalue=SN_GPIO2->IS; + wGpiovalue&=~(1<IS=wGpiovalue; + wGpiovalue=SN_GPIO2->IBS; + wGpiovalue&=~(1<IBS=wGpiovalue; + wGpiovalue=SN_GPIO2->IEV; + wGpiovalue&=~(1<IEV=wGpiovalue; +} + +/***************************************************************************** +* Function : GPIO_P3Trigger +* Description : set GPIO as edge or level trigger +* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3 + pin_number - GPIO_PIN0, 1, 2, ...,15 + is - 0: edge sensitive + 1: event sensitive + ibs - 0: edge trigger + 1: both edge trigger + iev - 0: Rising edges or HIGH level trigger + 1: Falling edges or LOW level trigger +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void GPIO_P3Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev) +{ + uint32_t wGpiovalue=0; + + wGpiovalue=SN_GPIO3->IS; + wGpiovalue&=~(1<IS=wGpiovalue; + wGpiovalue=SN_GPIO3->IBS; + wGpiovalue&=~(1<IBS=wGpiovalue; + wGpiovalue=SN_GPIO3->IEV; + wGpiovalue&=~(1<IEV=wGpiovalue; +} + +/***************************************************************************** +* Function : GPIO_Interrupt +* Description : set GPIO interrupt and NVIC +* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3 + pin_number - GPIO_PIN0, 1, 2, ...,15 + enable - 0 as disable + 1 as enable +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void GPIO_Interrupt(uint32_t port_number, uint32_t pin_number, uint32_t enable) +{ + switch(port_number){ + case 0: + //check SWD pin + if ((pin_number == GPIO_PIN8) || (pin_number == GPIO_PIN9)){ + if(SN_SYS0->SWDCTRL!=0x1) return; + } + SN_GPIO0->IC=0xFFFF; + SN_GPIO0->IE&=~(1<IE|=(enable<IC=0xFFFF; + SN_GPIO1->IE&=~(1<IE|=(enable<IC=0xFFFF; + SN_GPIO2->IE&=~(1<IE|=(enable<EXRSTCTRL!=1) return; + } + SN_GPIO3->IC=0xFFFF; + SN_GPIO3->IE&=~(1<IE|=(enable<IC=(1<IC=(1<IC=(1<IC=(1<CFG&=~(3<CFG|=(value<CFG&=~(3<CFG|=(value<CFG&=~(3<CFG|=(value<CFG&=~(3<CFG|=(value<RIS >>pin_number); + break; + case 1: + wreturn_value=(SN_GPIO1->RIS >>pin_number); + break; + case 2: + wreturn_value=(SN_GPIO2->RIS >>pin_number); + break; + case 3: + wreturn_value=(SN_GPIO3->RIS >>pin_number); + break; + default: + break; + } + wreturn_value&=0x01; + return wreturn_value; +} + + +/***************************************************************************** +* Function : P0_IRQHandler +* Description : Set GPIO P0 IRQ +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void P0_IRQHandler(void) +{ + if (GPIO_IntStatus(GPIO_PORT0,GPIO_PIN0)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN0); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN1)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN1); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN2)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN2); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN3)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN3); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN4)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN4); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN5)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN5); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN6)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN6); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN7)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN7); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN8)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN8); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN9)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN9); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN10)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN10); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN11)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN11); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN12)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN12); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN13)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN13); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN14)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN14); + } + else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN15)==1) + { + GPIO_IntClr(GPIO_PORT0,GPIO_PIN15); + } +} + +/***************************************************************************** +* Function : P1_IRQHandler +* Description : Set GPIO P1 IRQ +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void P1_IRQHandler(void) +{ + if (GPIO_IntStatus(GPIO_PORT1,GPIO_PIN0)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN0); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN1)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN1); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN2)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN2); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN3)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN3); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN4)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN4); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN5)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN5); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN6)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN6); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN7)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN7); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN8)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN8); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN9)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN9); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN10)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN10); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN11)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN11); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN12)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN12); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN13)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN13); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN14)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN14); + } + else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN15)==1) + { + GPIO_IntClr(GPIO_PORT1,GPIO_PIN15); + } +} + +/***************************************************************************** +* Function : P2_IRQHandler +* Description : Set GPIO P2 IRQ +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void P2_IRQHandler(void) +{ + if (GPIO_IntStatus(GPIO_PORT2,GPIO_PIN0)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN0); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN1)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN1); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN2)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN2); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN3)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN3); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN4)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN4); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN5)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN5); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN6)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN6); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN7)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN7); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN8)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN8); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN9)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN9); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN10)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN10); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN11)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN11); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN12)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN12); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN13)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN13); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN14)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN14); + } + else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN15)==1) + { + GPIO_IntClr(GPIO_PORT2,GPIO_PIN15); + } +} + +/***************************************************************************** +* Function : P3_IRQHandler +* Description : Set GPIO P3 IRQ +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void P3_IRQHandler(void) +{ + if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN3)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN3); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN4)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN4); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN5)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN5); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN6)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN6); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN7)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN7); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN8)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN8); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN9)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN9); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN10)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN10); + } + else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN11)==1) + { + GPIO_IntClr(GPIO_PORT3,GPIO_PIN11); + } +} + diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/GPIO.h b/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/GPIO.h new file mode 100644 index 00000000..28f9941b --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/GPIO.h @@ -0,0 +1,110 @@ +#ifndef __SN32F2XX_GPIO_H +#define __SN32F2XX_GPIO_H + +/*_____ I N C L U D E S ____________________________________________________*/ +#include + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +/* +Base Address: 0x4004 4000 (GPIO 0) + 0x4004 6000 (GPIO 1) + 0x4004 8000 (GPIO 2) + 0x4004 A000 (GPIO 3) +*/ + +/* GPIO Port n Data register (0x00) */ + + +/* GPIO Port n Mode register (0x04) */ +#define GPIO_MODE_INPUT 0 +#define GPIO_MODE_OUTPUT 1 + + +/* GPIO Port n Configuration register (0x08) */ +#define GPIO_CFG_PULL_UP 0 +#define GPIO_CFG_INACTIVE_Schmitt_EN 2 +#define GPIO_CFG_INACTIVE_Schmitt_DIS 3 + +/* GPIO Port n Interrupt Sense register (0x0C) */ +#define GPIO_IS_EDGE 0 +#define GPIO_IS_EVENT 1 + + +/* GPIO Port n Interrupt Both-edge Sense registe (0x10) */ +#define GPIO_IBS_EDGE_TRIGGER 0 +#define GPIO_IBS_BOTH_EDGE_TRIGGER 1 + + +/* GPIO Port n Interrupt Event register (0x14) */ +#define GPIO_IEV_RISING_EDGE 0 +#define GPIO_IEV_FALLING_EDGE 1 + + +/* GPIO Port n Interrupt Enable register (0x18) */ +#define GPIO_IE_DIS 0 +#define GPIO_IE_EN 1 + + +/* GPIO Port n Raw Interrupt Status register (0x1C/0x20) */ +#define mskPIN0IF (0x1<<0) +#define mskPIN1IF (0x1<<1) +#define mskPIN2IF (0x1<<2) +#define mskPIN3IF (0x1<<3) +#define mskPIN4IF (0x1<<4) +#define mskPIN5IF (0x1<<5) +#define mskPIN6IF (0x1<<6) +#define mskPIN7IF (0x1<<7) +#define mskPIN8IF (0x1<<8) +#define mskPIN9IF (0x1<<9) +#define mskPIN10IF (0x1<<10) +#define mskPIN11IF (0x1<<11) +#define mskPIN12IF (0x1<<12) +#define mskPIN13IF (0x1<<13) +#define mskPIN14IF (0x1<<14) +#define mskPIN15IF (0x1<<15) + +/* GPIO Port Name Define */ +//GPIO name define +#define GPIO_PORT0 0 +#define GPIO_PORT1 1 +#define GPIO_PORT2 2 +#define GPIO_PORT3 3 + +/* GPIO Pin Name Define */ +#define GPIO_PIN0 0 +#define GPIO_PIN1 1 +#define GPIO_PIN2 2 +#define GPIO_PIN3 3 +#define GPIO_PIN4 4 +#define GPIO_PIN5 5 +#define GPIO_PIN6 6 +#define GPIO_PIN7 7 +#define GPIO_PIN8 8 +#define GPIO_PIN9 9 +#define GPIO_PIN10 10 +#define GPIO_PIN11 11 +#define GPIO_PIN12 12 +#define GPIO_PIN13 13 +#define GPIO_PIN14 14 +#define GPIO_PIN15 15 + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +void GPIO_Init (void); +void GPIO_Mode(uint32_t port_number, uint32_t pin_number, uint32_t mode); +void GPIO_Set(uint32_t port_number, uint32_t pin_number); +void GPIO_Clr(uint32_t port_number, uint32_t pin_number); +void GPIO_P0Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev); +void GPIO_P1Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev); +void GPIO_P2Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev); +void GPIO_P3Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev); +void GPIO_Interrupt(uint32_t port_number, uint32_t pin_number, uint32_t enable); +void GPIO_IntClr(uint32_t port_number, uint32_t pin_number); +void GPIO_Config(uint32_t port_number, uint32_t pin_number, uint32_t value); +void GPIO_OpenDrain(uint32_t port_number, uint32_t pin_number, uint32_t value); +uint32_t GPIO_IntStatus(uint32_t port_number, uint32_t pin_number); +#endif /*__SN32F2XX_GPIO_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/driver.mk b/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/driver.mk new file mode 100644 index 00000000..1a0049be --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/GPIO \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.c new file mode 100644 index 00000000..5935e92d --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.c @@ -0,0 +1,147 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file GPIOv3/hal_pal_lld.c + * @brief SN32 PAL low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void initgpio(SN_GPIO0_Type *gpiop, const sn32_gpio_setup_t *config) { + + gpiop->DATA = config->data; + gpiop->MODE = config->mode; + gpiop->CFG = config->cfg; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief SN32 I/O ports configuration. + * @details Ports A-D clocks enabled. + * + * @param[in] config the SN32 ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + /* + * Initial GPIO setup. + */ + +#if SN32_HAS_GPIOA + initgpio(GPIOA, &config->PAData); +#endif +#if SN32_HAS_GPIOB + initgpio(GPIOB, &config->PBData); +#endif +#if SN32_HAS_GPIOC + initgpio(GPIOC, &config->PCData); +#endif +#if SN32_HAS_GPIOD + initgpio(GPIOD, &config->PDData); +#endif + +} + +/** + * @brief Pad mode setup. + * @details This function programs a pad + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum + * speed. + * + * @param[in] port the port identifier + * @param[in] pad the pad number + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setpadmode(ioportid_t port, + uint32_t pad, + iomode_t mode) { + + switch (mode) + { + + case PAL_MODE_UNCONNECTED: + break; + + case PAL_MODE_INPUT: + port->MODE &= ~(1 << pad); + break; + + case PAL_MODE_INPUT_PULLUP: + port->MODE &= ~(1 << pad); + port->CFG &= ~(3 << (pad * 2)); + // port->BSET = (1 << pad); // High 1 + break; + + case PAL_MODE_INPUT_PULLDOWN: + port->MODE &= ~(1 << pad); + port->CFG &= ~(3 << (pad * 2)); + // port->BCLR = (1 << pad); // Low 0 + break; + + case PAL_MODE_INPUT_ANALOG: + port->MODE &= ~(1 << pad); + port->CFG &= ~(3 << (pad * 2)); + break; + + case PAL_MODE_OUTPUT_PUSHPULL: + port->MODE |= (1 << pad); + break; + + case 7: + break; + + default: + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.h new file mode 100644 index 00000000..ba737998 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.h @@ -0,0 +1,423 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file GPIOv3/hal_pal_lld.h + * @brief SN32 PAL low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef HAL_PAL_LLD_H +#define HAL_PAL_LLD_H + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +// /* Specifies palInit() without parameter, required until all platforms will +// be updated to the new style.*/ +// // #define PAL_NEW_INIT + + +/* Discarded definitions from the ST headers, the PAL driver uses its own + definitions in order to have an unified handling for all devices. + Unfortunately the ST headers have no uniform definitions for the same + objects across the various sub-families.*/ +#undef GPIOA +#undef GPIOB +#undef GPIOC +#undef GPIOD + +/** + * @name GPIO ports definitions + * @{ + */ +#define GPIOA ((SN_GPIO0_Type *)SN_GPIO0_BASE)// SN_GPIO0// +#define GPIOB ((SN_GPIO0_Type *)SN_GPIO1_BASE)// SN_GPIO1// +#define GPIOC ((SN_GPIO0_Type *)SN_GPIO2_BASE)// SN_GPIO2// +#define GPIOD ((SN_GPIO0_Type *)SN_GPIO3_BASE)// SN_GPIO3// + +/** @} */ + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @name Port related definitions + * @{ + */ +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 16 + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) +/** @} */ + +// GPIO0 = 40044000 +// pad = 5 + +// line = 40044005 + +/** + * @name Line handling macros + * @{ + */ +/** + * @brief Forms a line identifier. + * @details A port/pad pair are encoded into an @p ioline_t type. The encoding + * of this type is platform-dependent. + * @note In this driver the pad number is encoded in the lower 4 bits of + * the GPIO address which are guaranteed to be zero. + */ +#define PAL_LINE(port, pad) \ + ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad))) + +/** + * @brief Decodes a port identifier from a line identifier. + */ +#define PAL_PORT(line) \ + ((SN_GPIO0_Type *)(((uint32_t)(line)) & 0xFFFFFFF0U)) + +/** + * @brief Decodes a pad identifier from a line identifier. + */ +#define PAL_PAD(line) \ + ((uint32_t)((uint32_t)(line) & 0x0000000FU)) + +/** + * @brief Value identifying an invalid line. + */ +#define PAL_NOLINE 0U +/** @} */ + +/** + * @brief GPIO port setup info. + */ +typedef struct { + /** Initial value for DATA register.*/ + uint32_t data; + /** Initial value for MODE register.*/ + uint32_t mode; + /** Initial value for CFG register.*/ + uint32_t cfg; + /** Initial value for IS register.*/ + uint32_t is; + /** Initial value for IBS register.*/ + uint32_t ibs; + /** Initial value for IEV register.*/ + uint32_t iev; + /** Initial value for IE register.*/ + uint32_t ie; + /** Initial value for RIS register.*/ + uint32_t ris; + /** Initial value for IC register.*/ + uint32_t ic; + /** Initial value for BSET register.*/ + uint32_t bset; + /** Initial value for BCLR register.*/ + uint32_t bclr; +} sn32_gpio_setup_t; + +/** + * @brief SN32 GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialize the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { +#if SN32_HAS_GPIOA || defined(__DOXYGEN__) + /** @brief Port A setup data.*/ + sn32_gpio_setup_t PAData; +#endif +#if SN32_HAS_GPIOB || defined(__DOXYGEN__) + /** @brief Port B setup data.*/ + sn32_gpio_setup_t PBData; +#endif +#if SN32_HAS_GPIOC || defined(__DOXYGEN__) + /** @brief Port C setup data.*/ + sn32_gpio_setup_t PCData; +#endif +#if SN32_HAS_GPIOD || defined(__DOXYGEN__) + /** @brief Port D setup data.*/ + sn32_gpio_setup_t PDData; +#endif +} PALConfig; + +/** + * @brief Type of digital I/O port sized unsigned integer. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Type of digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Type of an I/O line. + */ +typedef uint32_t ioline_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef SN_GPIO0_Type * ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/* The low level driver wraps the definitions already present in the SN32 */ +/* firmware library. */ +/*===========================================================================*/ + +/** + * @brief GPIO port A identifier. + */ +#if SN32_HAS_GPIOA || defined(__DOXYGEN__) +#define IOPORT1 GPIOA +#endif + +/** + * @brief GPIO port B identifier. + */ +#if SN32_HAS_GPIOB || defined(__DOXYGEN__) +#define IOPORT2 GPIOB +#endif + +/** + * @brief GPIO port C identifier. + */ +#if SN32_HAS_GPIOC || defined(__DOXYGEN__) +#define IOPORT3 GPIOC +#endif + +/** + * @brief GPIO port D identifier. + */ +#if SN32_HAS_GPIOD || defined(__DOXYGEN__) +#define IOPORT4 GPIOD +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->DATA) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +// #define pal_lld_readlatch(port) ((port)->RIS) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->DATA = (uint16_t)(bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((port)->BSET = (uint16_t)(bits)) + +/** + * @brief Clears a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((port)->BCLR = ~(uint16_t)(bits)) + +/** + * @brief Writes a group of bits. + * @details This function is implemented by writing the GPIO BSET register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset the group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group + * width are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) { \ + uint32_t w = ((~(uint32_t)(bits) & (uint32_t)(mask)) << (16U + (offset))) | \ + ((uint32_t)(bits) & (uint32_t)(mask)) << (offset); \ + (port)->DATA = w; \ +} + +/** + * @brief Reads a logical state from an I/O pad. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @return The logical state. + * @retval PAL_LOW low logical state. + * @retval PAL_HIGH high logical state. + * + * @notapi + */ +#define pal_lld_readpad(port, pad) (((port)->DATA >> pad) & 1) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) ((port)->DATA = (bit << pad)) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) ((port)->BSET = (0x1 << pad)) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) ((port)->BCLR = (0x1 << pad)) + +/** + * @brief Toggles a pad logical state. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +// #define pal_lld_togglepad(port, pad) + +/** + * @brief Pad mode setup. + * @details This function programs a pad with the specified mode. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad mode + * + * @notapi + */ +// #define pal_lld_setpadmode(port, pad, mode) ((port)->MODE |= mode << pad) + +#define pal_lld_setpadmode(port, pad, mode) \ + _pal_lld_setpadmode(port, pad, mode) + +#ifdef __cplusplus +extern "C" { +#endif + extern const PALConfig pal_default_config; + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setpadmode(ioportid_t port, + uint32_t pad, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* HAL_PAL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/I2C/I2C.c b/os/hal/ports/SN32/LLD/SN32F2xx/I2C/I2C.c new file mode 100644 index 00000000..53efe1ba --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/I2C/I2C.c @@ -0,0 +1,368 @@ +/******************** (C) COPYRIGHT 2017 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2017/07 +* AUTHOR: SA1 +* IC: SN32F240B +* DESCRIPTION: I2C0 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2017/07/07 SA1 First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include +#include "I2C.h" + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +uint8_t bI2C_RxFIFO[I2C_RX_FIFO_LENGTH]; +uint8_t bI2C_TxFIFO[I2C_TX_FIFO_LENGTH] = {0}; +uint8_t bI2C_RxFIFO_cnts, bI2C_Rx_cnts; +uint8_t bI2C_TxFIFO_cnts, bI2C_Tx_cnts; +uint8_t *bTX_ptr; +uint8_t EEPROM_ADR_H, EEPROM_ADR_L; +uint8_t EEPROM_WR; // 0 : write + // 1 : read +uint8_t Busy = 1, Error = 0; +uint8_t Read_Down = 0; +uint8_t Send_Address; +uint8_t temp = 0; +volatile uint8_t Timeout = 0; + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ +/***************************************************************************** +* Function : I2C_Init +* Description : Initialization of I2C +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C_Init (void) +{ + SN_SYS1->AHBCLKEN_b.I2C0CLKEN = 1; //Enables HCLK for I2C0 + + //I2C speed + SN_I2C0->SCLHT = I2C0_SCLHT; + SN_I2C0->SCLLT = I2C0_SCLLT; + + SN_I2C0->CTRL_b.I2CEN = 1; //Enable I2C + + //===NVIC=== + NVIC_ClearPendingIRQ(I2C0_IRQn); + NVIC_EnableIRQ(I2C0_IRQn); +} +/***************************************************************************** +* Function : I2C_Start +* Description : transmit a START bit +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C_Start(void) +{ + SN_I2C0->CTRL_b.STA = 1; +} +/***************************************************************************** +* Function : I2C_Stop +* Description : transmit a STOP condition in master mode +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2C_Stop(void) +{ + SN_I2C0->CTRL_b.STO = 1; +} +/***************************************************************************** +* Function : I2C_Read +* Description : read N Byte data from EEPROM +* Input : eeprom_adr - data word address +* : read_num - byte length +* Output : None +* Return : OK or Fail +* Note : None +*****************************************************************************/ +uint8_t I2C_Read(uint16_t eeprom_adr, uint8_t read_num) +{ + bI2C_Rx_cnts = 0; + + EEPROM_ADR_H = eeprom_adr >> 8; //data word address low byte + EEPROM_ADR_L = eeprom_adr & 0x00ff; //data word address high byte + + bI2C_RxFIFO_cnts = read_num; //byte length + + Busy = 1; + + EEPROM_WR = 0; //write + + I2C_Start(); //I2C start + + SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt + + Send_Address = 1; //data word address setting flag + + while(Busy == 1 && Timeout == 0); + + SysTick->CTRL = 0x0; //Disable SysTick timer and interrupt + + if(Error == 1 || Timeout == 1) return FALSE; + + #if (EEPROM_less_than_32K == 0) + + SN_I2C0->TXDATA = EEPROM_ADR_H; //data word address high byte + + SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt + + Busy = 1; + + while(Busy == 1 && Timeout == 0); + + SysTick->CTRL = 0x0; //Disable SysTick timer and interrupt + + if(Error == 1 || Timeout == 1) return FALSE; + + #endif + + SN_I2C0->TXDATA = EEPROM_ADR_L; //data word address low byte + + SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt + + Busy = 1; + + while(Busy == 1 && Timeout == 0); + + SysTick->CTRL = 0x0; //Disable SysTick timer and interrupt + + if(Error == 1 || Timeout == 1) return FALSE; + + Read_Down = 0; + + Send_Address = 0; + + EEPROM_WR = 1; //read + + I2C_Start(); //I2C start + + SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt + + while(Read_Down == 0 && Timeout == 0); + + SysTick->CTRL = 0x0; //Disable SysTick timer and interrupt + + Read_Down = 0; + + if(Error == 1 || Timeout == 1) return FALSE; + + return TRUE; +} +/***************************************************************************** +* Function : I2C_Write +* Description : write N Byte data to EEPROM +* Input : eeprom_adr - data word address +* : write_num - byte length +* Output : None +* Return : OK or Fail +* Note : None +*****************************************************************************/ +uint8_t I2C_Write(uint16_t eeprom_adr, uint8_t write_num) +{ + Timeout = 0; + + bI2C_Tx_cnts = 0; + + bTX_ptr = &bI2C_TxFIFO[0]; //write data buffer + + EEPROM_ADR_H = eeprom_adr >> 8; //data word address high byte + + EEPROM_ADR_L = eeprom_adr & 0x00ff; //data word address low byte + + bI2C_TxFIFO_cnts = write_num; //byte length + + Busy = 1; + + EEPROM_WR = 0; //write + + SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt + + I2C_Start(); //I2C start + + Send_Address = 1; //data word address setting flag + + while(Busy == 1 && Timeout == 0); + + SysTick->CTRL = 0x0; //Disable SysTick timer and interrupt + + if(Error == 1 || Timeout == 1) return FALSE; + + #if (EEPROM_less_than_32K == 0) + + SN_I2C0->TXDATA = EEPROM_ADR_H; //data word address high byte + + SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt + + Busy = 1; + + while(Busy == 1 && Timeout == 0); + + SysTick->CTRL = 0x0; //Disable SysTick timer and interrupt + + if(Error == 1 || Timeout == 1) return FALSE; + + #endif + + SN_I2C0->TXDATA = EEPROM_ADR_L; //data word address low byte + + SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt + + Busy = 1; + + while(Busy == 1 && Timeout == 0); + + if(Error == 1 || Timeout == 1 ) return FALSE; + + SysTick->CTRL = 0x0; //Disable SysTick timer and interrupt + + Send_Address = 0; + + SN_I2C0->TXDATA = *bTX_ptr++; //write data + + SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt + + Busy = 1; + + while(Busy == 1 && Timeout == 0); + + if(Error == 1 || Timeout == 1) return FALSE; + + SysTick->CTRL = 0x0; //Disable SysTick timer and interrupt + + Busy = 1; + + I2C_Stop(); + + SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt + + while(Busy == 1 && Timeout == 0); + + if(Error == 1 || Timeout == 1) return FALSE; + + SysTick->CTRL = 0x0; //Disable SysTick timer and interrupt + + return TRUE; +} + +/***************************************************************************** +* Function : I2C_IRQHandler +* Description : I2C interrupt service routine +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void I2C0_IRQHandler(void) +{ + if(((SN_I2C0->STAT) & (mskI2C_LOST_ARB_LOST_ARBITRATION)) == Lost_Arbitration) + { + SN_I2C0->STAT_b.I2CIF = 1; + SN_I2C0->CTRL_b.I2CEN = 0; //Disable I2C + SN_I2C0->CTRL_b.I2CEN = 1; //Enable I2C + I2C_Start(); //Re-start + } + + /* Stop Done */ + else if(((SN_I2C0->STAT) & (mskI2C_STA_MASTER_STA_STO)) == STOP_DONE) + { + Busy = 0; + SN_I2C0->STAT_b.I2CIF = 1; + if(EEPROM_WR == 1) + Read_Down = 1; + } + else + { + SN_I2C0->STAT_b.I2CIF = 1; + + switch (SN_I2C0->STAT) + { + case (Lost_Arbitration | mskI2C_MST_MASTER): + I2C_Start(); + break; + + /* RX with ACK/NACK transfer is down */ + case (RX_DONE | mskI2C_MST_MASTER): + bI2C_RxFIFO[bI2C_Rx_cnts++] = SN_I2C0->RXDATA; + if(bI2C_Rx_cnts < (bI2C_RxFIFO_cnts - 1)) + SN_I2C0->CTRL_b.ACK = 1; + else if(bI2C_Rx_cnts == (bI2C_RxFIFO_cnts - 1)) + SN_I2C0->CTRL_b.NACK = 1; + else if(bI2C_Rx_cnts == bI2C_RxFIFO_cnts) + I2C_Stop(); + Busy = 0; + break; + + /* SLA+W or Data has been transmitted and ACK has been received */ + case (ACK_DONE | mskI2C_MST_MASTER): + if(EEPROM_WR == 1) + { + Busy = 0; + if(bI2C_RxFIFO_cnts == 1) + SN_I2C0->CTRL_b.NACK = 1; + else + SN_I2C0->CTRL_b.ACK = 1; + } + if(EEPROM_WR == 0) + { + if(Send_Address == 0) + { + bI2C_Tx_cnts++; + if(bI2C_Tx_cnts < bI2C_TxFIFO_cnts) + SN_I2C0->TXDATA = *bTX_ptr++; + else if(bI2C_Tx_cnts == bI2C_TxFIFO_cnts) + Busy = 0; + } + else + Busy = 0; + } + break; + + /* SLA+W or Data has been transmitted and NACK has been received */ + case (NACK_DONE | mskI2C_MST_MASTER): + SN_I2C0->CTRL_b.STO = 1; + Error = 1; + break; + + /* START has been transmitted and prepare SLA+W/SLA+R */ + case (START_DONE | mskI2C_MST_MASTER): + #if (EEPROM_less_than_32K == 1) + SN_I2C0->TXDATA = Device_ADDRESS | (EEPROM_ADR_H << 1) | EEPROM_WR; + #else + SN_I2C0->TXDATA = Device_ADDRESS | EEPROM_WR; + #endif + break; + + default: + SN_I2C0->CTRL_b.I2CEN = 0; + SN_I2C0->CTRL_b.I2CEN = 1; + SN_I2C0->CTRL_b.STA = 1; + break; + } + } +} + diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/I2C/I2C.h b/os/hal/ports/SN32/LLD/SN32F2xx/I2C/I2C.h new file mode 100644 index 00000000..7835a05b --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/I2C/I2C.h @@ -0,0 +1,120 @@ +#ifndef __SN32F2XX_I2C_H +#define __SN32F2XX_I2C_H + +/*_____ I N C L U D E S ____________________________________________________*/ +#include + +/*_____ D E F I N I T I O N S ______________________________________________*/ +#define EEPROM_less_than_32K 1 // 1: for EEPROM size less than 32K bits (4096x8) + // 0: for EEPROM size more than or equal to 32K bits (4096x8) + +#define Device_ADDRESS 0xA0 +#define Lost_Arbitration 0x100 +#define SLAVE_ADDRESS_HIT_TX 0x80 +#define SLAVE_ADDRESS_HIT_RX 0x40 +#define START_DONE 0x10 +#define STOP_DONE 0x08 +#define NACK_DONE 0x04 +#define ACK_DONE 0x02 +#define RX_DONE 0x01 + +/* I2C n SCL High Time register <(I2Cn_SCLHT> (0x20) */ +#define I2C0_SCLHT 14 //[7:0], Count for SCL High Period time + //SCL High Period Time = (SCLH+1) * I2C0_PCLK cycle +#define I2C0_SCLLT 14 //[7:0], Count for SCL Low Period time + //SCL Loq Period Time = (SCLL+1) * I2C0_PCLK cycle + + +/* I2C n Status register (0x04) */ + //[0:0]RX done status +#define I2C_RX_DN_NO_HANDSHAKE 0 //No RX with ACK/NACK transfer +#define I2C_RX_DN_HANDSHAKE 1 //8-bit RX with ACK/NACK transfer is done +#define mskI2C_RX_DN_NO_HANDSHAKE (I2C_RX_DN_NO_HANDSHAKE<<0) +#define mskI2C_RX_DN_HANDSHAKE (I2C_RX_DN_HANDSHAKE<<0) + + //[1:1]ACK done status +#define I2C_ACK_STAT_NO_RECEIVED_ACK 0 //Not received an ACK +#define I2C_ACK_STAT_RECEIVED_ACK 1 //Received an ACK +#define mskI2C_ACK_STAT_NO_RECEIVED_ACK (I2C_ACK_STAT_NO_RECEIVED_ACK<<1) +#define mskI2C_ACK_STAT_RECEIVED_ACK (I2C_ACK_STAT_RECEIVED_ACK<<1) + + + //[2:2]NACK done status +#define I2C_NACK_STAT_NO_RECEIVED_NACK 0 //Not received a NACK +#define I2C_NACK_STAT_RECEIVED_NACK 1 //Received a NACK +#define mskI2C_NACK_STAT_NO_RECEIVED_NACK (I2C_NACK_STAT_NO_RECEIVED_NACK<<2) +#define mskI2C_NACK_STAT_RECEIVED_NACK (I2C_NACK_STAT_RECEIVED_NACK<<2) + + //[3:3]Stop done status +#define I2C_STOP_DN_NO_STOP 0 //No STOP bit +#define I2C_STOP_DN_STOP 1 //MASTER mode, a STOP condition was issued + //SLAVE mode, a STOP condition was received +#define mskI2C_STOP_DN_NO_STOP (I2C_STOP_DN_NO_STOP<<3) +#define mskI2C_STOP_DN_STOP (I2C_STOP_DN_STOP<<3) + + //[4:4]Start done status +#define I2C_START_DN_NO_START 0 //No START bit +#define I2C_START_DN_START 1 //MASTER mode, a START bit was issued + //SLAVE mode, a START bit was received +#define mskI2C_START_DN_NO_START (I2C_START_DN_NO_START<<4) +#define mskI2C_START_DN_START (I2C_START_DN_START<<4) + + +#define I2C_MST_SLAVE 0 //[5:5]Master/Slave status +#define I2C_MST_MASTER 1 +#define mskI2C_MST_SLAVE (I2C_MST_SLAVE<<5) +#define mskI2C_MST_MASTER (I2C_MST_MASTER<<5) + +#define mskI2C_STA_STA_STO ((I2C_START_DN_START<<4)|(I2C_STOP_DN_STOP<<3)) +#define mskI2C_STA_MASTER_STA_STO ((I2C_MST_MASTER<<5)|(I2C_START_DN_START<<4)|(I2C_STOP_DN_STOP<<3)) + + + //[6:6]Slave address check +#define I2C_SLV_RX_NO_MATCH_ADDR 0 //No matched slave address +#define I2C_SLV_RX_MATCH_ADDR 1 //Slave address hit, and is called for RX in slave mode +#define mskI2C_SLV_RX_NO_MATCH_ADDR (I2C_SLV_RX_NO_MATCH_ADDR<<6) +#define mskI2C_SLV_RX_MATCH_ADDR (I2C_SLV_RX_MATCH_ADDR<<6) + + //[7:7]Slave address check +#define I2C_SLV_TX_NO_MATCH_ADDR 0 //No matched slave address +#define I2C_SLV_TX_MATCH_ADDR 1 //Slave address hit, and is called for TX in slave mode. +#define mskI2C_SLV_TX_NO_MATCH_ADDR (I2C_SLV_TX_NO_MATCH_ADDR<<7) +#define mskI2C_SLV_TX_MATCH_ADDR (I2C_SLV_TX_MATCH_ADDR<<7) + + //[8:8]Lost arbitration +#define I2C_LOST_ARB_NO_LOST 0 //Not lost arbitration +#define I2C_LOST_ARB_LOST_ARBITRATION 1 //Lost arbitration +#define mskI2C_LOST_ARB_NO_LOST (I2C_LOST_ARB_NO_LOST<<8) +#define mskI2C_LOST_ARB_LOST_ARBITRATION (I2C_LOST_ARB_LOST_ARBITRATION<<8) + + //[9:9]Time-out status +#define I2C_TIMEOUT_NO_TIMEOUT 0 //No Timeout +#define I2C_TIMEOUT_TIMEOUT 1 //Timeout +#define mskI2C_TIMEOUT_TIMEOUT (I2C_TIMEOUT_TIMEOUT<<9) +#define mskI2C_TIMEOUT_NO_TIMEOUT (I2C_TIMEOUT_NO_TIMEOUT<<9) + + //[15:15]I2C Interrupt flag +#define I2C_I2CIF_STAUS_NO_CHANGE 0 //I2C status doesn’t change +#define I2C_I2CIF_INTERRUPT 1 //Read, I2C status changes + //Write, Clear this flag +#define mskI2C_I2CIF_STAUS_NO_CHANGE (I2C_I2CIF_STAUS_NO_CHANGE<<15) +#define mskI2C_I2CIF_INTERRUPT (I2C_I2CIF_INTERRUPT<<15) + + +//Recv FIFO +#define I2C_RX_FIFO_LENGTH 32 + +//TX FIFO +#define I2C_TX_FIFO_LENGTH 32 + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + +void I2C_Init(void); +void I2C_Start(void); +void I2C_Stop(void); +uint8_t I2C_Read(uint16_t eeprom_adr, uint8_t read_num); +uint8_t I2C_Write(uint16_t eeprom_adr, uint8_t write_num); +#endif /*__SN32F2XX_I2C_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/I2S/I2S.c b/os/hal/ports/SN32/LLD/SN32F2xx/I2S/I2S.c new file mode 100644 index 00000000..d881fef3 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/I2S/I2S.c @@ -0,0 +1,152 @@ +/******************** (C) COPYRIGHT 2014 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2014/02 +* AUTHOR: SA1 +* IC: SN32F240/730/220 +* DESCRIPTION: I2S related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 1. First release +* 2.0 2014/02/27 SA1 1. Update I2S functions. +* 3.2 2019/05/31 SA1 1. Fix I2S_Master_Init and I2S_Slave_Init. +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include "I2S.h" + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ +/************************************************************** +* Function : I2S_Master_INIT +* Description : Set I2S as master +* Input : None +* Output : None +* Return : None +* Note : None +****************************************************************/ +void I2S_Master_Init(void) +{ + __I2S_ENABLE_I2SHCLK; //Enable HCLK for I2S + + SN_I2S->CTRL_b.I2SEN = I2S_I2SEN_EN; //I2S enable bit + SN_I2S->CTRL_b.CHLENGTH = I2S_CHLENGTH_32BITS; //Single channel[4:0] + SN_I2S->CTRL_b.RXFIFOTH = I2S_RXFIFOTH_2; //RX FIFO Threshold level + SN_I2S->CTRL_b.TXFIFOTH = I2S_TXFIFOTH_6; //TX FIFO Threshold level + + SN_I2S->CTRL_b.DL = I2S_DL_24BITS; //I2S Data Length + __I2S_RESET_RXFIFO; //Clear I2S RX FIFO + __I2S_RESET_TXFIFO; //Clear I2S TX FIFO + SN_I2S->CTRL_b.RXEN = I2S_RXEN_EN; //Receiver enable bit + SN_I2S->CTRL_b.TXEN = I2S_TXEN_EN; //Transmit enable bit + + SN_I2S->CTRL_b.FORMAT=I2S_FORMAT_STANDARD; //I2S operation format + SN_I2S->CTRL_b.MS=I2S_MS_MASTER_MODE; //Master selection bit + SN_I2S->CTRL_b.MONO=I2S_MONO_STERO; //Stereo selection bit + SN_I2S->CTRL_b.MUTE=I2S_MUTE_DIS; //Mute enable bit + + //I2S clk + SN_I2S->CLK = mskI2S_CLKSEL_HCLK| //I2S clock source selection + mskI2S_BCLKDIV_DIV| //MCLK/n, n = 2, 4, 6, 8, ...,512 + mskI2S_MCLKSEL_I2S_PCLK| //MCLK source of master is from I2S_PCLK + mskI2S_MCLKOEN_OUTPUT_DIS| //MCLK output enable bit + mskI2S_MCLKDIV_DIV3; //MCLK = MCLK source / 6 +} + +/************************************************************** +* Function : I2S_Slave_Init +* Description : Set I2S as slave +* Input : None +* Output : None +* Return : None +* Note : None +****************************************************************/ +void I2S_Slave_Init(void) +{ + __I2S_ENABLE_I2SHCLK; //Enable HCLK for I2S + + SN_I2S->CTRL_b.I2SEN = I2S_I2SEN_EN ; //I2S enable bit + SN_I2S->CTRL_b.CHLENGTH = I2S_CHLENGTH_32BITS; //Single channel[4:0] + SN_I2S->CTRL_b.RXFIFOTH = I2S_RXFIFOTH_2; //RX FIFO Threshold level + SN_I2S->CTRL_b.TXFIFOTH = I2S_TXFIFOTH_6; + + SN_I2S->CTRL_b.DL = I2S_DL_24BITS; //I2S Data Length + __I2S_RESET_RXFIFO; //Clear I2S RX FIFO + __I2S_RESET_TXFIFO; //Clear I2S TX FIFO + SN_I2S->CTRL_b.RXEN = I2S_RXEN_EN; //Receiver enable bit + SN_I2S->CTRL_b.TXEN = I2S_TXEN_EN; + + SN_I2S->CTRL_b.FORMAT=I2S_FORMAT_STANDARD; //I2S operation format + SN_I2S->CTRL_b.MS=I2S_MS_SLAVE_MODE; //Master selection bit + SN_I2S->CTRL_b.MONO=I2S_MONO_STERO; //Stereo selection bit + SN_I2S->CTRL_b.MUTE=I2S_MUTE_DIS; +} + +/***************************************************************************** +* Function : I2S_Enable +* Description : I2S enable +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2S_Enable(void) +{ + __I2S_ENABLE_I2SHCLK; //Enable HCLK for I2S + + SN_I2S->CTRL_b.I2SEN = I2S_I2SEN_EN ; //I2S enable bit + __I2S_RESET_TXFIFO; + __I2S_RESET_RXFIFO; +} + +/***************************************************************************** +* Function : I2S_Disable +* Description : I2S disable +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void I2S_Disable(void) +{ + SN_I2S->CTRL_b.I2SEN = I2S_I2SEN_DIS; //I2S disable bit + + __I2S_DISABLE_I2SHCLK; //Disable HCLK for I2S +} + +/********************************** +* Function : I2S_Interrupt_Enable +* Description : I2S interrupt enable +* Input : None +* Output : None +* Return : None +* Note : None +**********************************/ +void I2S_Interrupt_Enable(void) +{ + SN_I2S->IC = mskI2S_RXFIFOTHIC| //Clear RXFIFOTHIF bit + mskI2S_TXFIFOTHIC| //Clear TXFIFOTHIF bit + mskI2S_RXFIFOUDIC| //Clear RXFIFOOUDIF bit + mskI2S_TXFIFOOVIC; //Clear TXFIFOOVIF bit + + SN_I2S->IE = mskI2S_TXFIFOOVFIEN_EN| //TX FIFO overflow interrupt enable bit + mskI2S_RXFIFOUDFIEN_EN| //RX FIFO underflow interrupt enable bit + mskI2S_TXFIFOTHIEN_EN| //TX FIFO threshold interrupt enable bit + mskI2S_RXFIFOTHIEN_EN; //RX FIFO threshold interrupt enable bit +} diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/I2S/I2S.h b/os/hal/ports/SN32/LLD/SN32F2xx/I2S/I2S.h new file mode 100644 index 00000000..7ccdcba6 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/I2S/I2S.h @@ -0,0 +1,216 @@ +#ifndef __SN32F2XX_I2S_H +#define __SN32F2XX_I2S_H + +/*_____ I N C L U D E S ____________________________________________________*/ + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +/* +Base Address: 0x4001 A000 +*/ + +/* I2S Control register (0x00) */ + +#define I2S_START_DIS 0 //[0:0]Start Transmit/Receive bit +#define I2S_START_EN 1 +#define mskI2S_START_DIS (mskI2S_START_DIS<<0) +#define mskI2S_START_EN (mskI2S_START_EN<<0) + +#define I2S_MUTE_DIS 0 //[1:1]Mute enable bit +#define I2S_MUTE_EN 1 +#define mskI2S_MUTE_DIS (I2S_MUTE_DIS<<1) +#define mskI2S_MUTE_EN (I2S_MUTE_EN<<1) + +#define I2S_MONO_STERO 0 //[2:2]Mono/Stereo selection bit +#define I2S_MONO_MONO 1 +#define mskI2S_MONO_STERO (I2S_MONO_STERO<<2) +#define mskI2S_MONO_MONO (I2S_MONO_MONO<<2) + +#define I2S_MS_MASTER_MODE 0 //[3:3]Master/Slave selection bit +#define I2S_MS_SLAVE_MODE 1 +#define mskI2S_MS_MASTER_MODE (I2S_MS_MASTER_MODE<<3) +#define mskI2S_MS_SLAVE_MODE (I2S_MS_SLAVE_MODE<<3) + + //[5:4]I2S operation format +#define I2S_FORMAT_STANDARD 0 //Standard I2S format +#define I2S_FORMAT_LEFTJUST 1 //Left-justified format +#define I2S_FORMAT_RIGHTJUST 2 //Right(MSB)-justified format +#define mskI2S_FORMAT_STANDARD (I2S_FORMAT_STANDARD<<4) +#define mskI2S_FORMAT_LEFTJUST (I2S_FORMAT_LEFTJUST<<4) +#define mskI2S_FORMAT_RIGHTJUST (I2S_FORMAT_RIGHTJUST<<4) + +#define I2S_TXEN_DIS 0 //[6:6]Transmit enable bit +#define I2S_TXEN_EN 1 +#define mskI2S_TXEN_DIS (I2S_TXEN_DIS<<6) +#define mskI2S_TXEN_EN (I2S_TXEN_EN<<6) + +#define I2S_RXEN_DIS 0 //[7:7]Receiver enable bit +#define I2S_RXEN_EN 1 +#define mskI2S_RXEN_DIS (I2S_RXEN_DIS<<7) +#define mskI2S_RXEN_EN (I2S_RXEN_EN<<7) + +#define I2S_CLRTXFIFO_RESET_TXFIFO 1 //[8:8]Clear I2S TX FIFO +#define I2S_CLRRXFIFO_RESET_RXFIFO 1 //[9:9]Clear I2S TX FIFO + +#define I2S_DL_8BITS 0 //[11:10]I2S Data Length +#define I2S_DL_16BITS 1 +#define I2S_DL_24BITS 2 +#define I2S_DL_32BITS 3 + +#define I2S_TXFIFOTH_0 0 //[14:12]TX FIFO Threshold level[2:0] +#define I2S_TXFIFOTH_1 1 +#define I2S_TXFIFOTH_2 2 +#define I2S_TXFIFOTH_3 3 +#define I2S_TXFIFOTH_4 4 +#define I2S_TXFIFOTH_5 5 +#define I2S_TXFIFOTH_6 6 +#define I2S_TXFIFOTH_7 7 + +#define I2S_RXFIFOTH_0 0 //[18:16]RX FIFO Threshold level[2:0] +#define I2S_RXFIFOTH_1 1 +#define I2S_RXFIFOTH_2 2 +#define I2S_RXFIFOTH_3 3 +#define I2S_RXFIFOTH_4 4 +#define I2S_RXFIFOTH_5 5 +#define I2S_RXFIFOTH_6 6 +#define I2S_RXFIFOTH_7 7 + +#define I2S_CHLENGTH_8BITS 7 //[24:20]Bit number of single channel[4:0] +#define I2S_CHLENGTH_9BITS 8 +#define I2S_CHLENGTH_10BITS 9 +#define I2S_CHLENGTH_11BITS 10 +#define I2S_CHLENGTH_12BITS 11 +#define I2S_CHLENGTH_13BITS 12 +#define I2S_CHLENGTH_14BITS 13 +#define I2S_CHLENGTH_15BITS 14 +#define I2S_CHLENGTH_16BITS 15 +#define I2S_CHLENGTH_17BITS 16 +#define I2S_CHLENGTH_18BITS 17 +#define I2S_CHLENGTH_19BITS 18 +#define I2S_CHLENGTH_20BITS 19 +#define I2S_CHLENGTH_21BITS 20 +#define I2S_CHLENGTH_22BITS 21 +#define I2S_CHLENGTH_23BITS 22 +#define I2S_CHLENGTH_24BITS 23 +#define I2S_CHLENGTH_25BITS 24 +#define I2S_CHLENGTH_26BITS 25 +#define I2S_CHLENGTH_27BITS 26 +#define I2S_CHLENGTH_28BITS 27 +#define I2S_CHLENGTH_29BITS 28 +#define I2S_CHLENGTH_30BITS 29 +#define I2S_CHLENGTH_31BITS 30 +#define I2S_CHLENGTH_32BITS 31 + +#define I2S_I2SEN_DIS 0 //[31:31]I2S enable bit +#define I2S_I2SEN_EN 1 +#define mskI2S_I2SEN_DIS (I2S_I2SEN_DIS<<31) +#define mskI2S_I2SEN_EN (I2S_I2SEN_EN<<31) + +/* I2S Clock register (0x04) */ + //[2:0]MCLK divider +#define I2S_MCLKDIV_DIV0 0 //MCLK = MCLK source +#define mskI2S_MCLKDIV_DIV0 (I2S_MCLKDIV_DIV0<<0) +#define I2S_MCLKDIV_DIV1 1 //MCLK = MCLK source / 2 +#define mskI2S_MCLKDIV_DIV1 (I2S_MCLKDIV_DIV1<<0) +#define I2S_MCLKDIV_DIV2 2 //MCLK = MCLK source / 4 +#define mskI2S_MCLKDIV_DIV2 (I2S_MCLKDIV_DIV2<<0) +#define I2S_MCLKDIV_DIV3 3 //MCLK = MCLK source / 6 +#define mskI2S_MCLKDIV_DIV3 (I2S_MCLKDIV_DIV3<<0) +#define I2S_MCLKDIV_DIV4 4 //MCLK = MCLK source / 8 +#define mskI2S_MCLKDIV_DIV4 (I2S_MCLKDIV_DIV4<<0) +#define I2S_MCLKDIV_DIV5 5 //MCLK = MCLK source / 10 +#define mskI2S_MCLKDIV_DIV5 (I2S_MCLKDIV_DIV5<<0) +#define I2S_MCLKDIV_DIV6 6 //MCLK = MCLK source / 12 +#define mskI2S_MCLKDIV_DIV6 (I2S_MCLKDIV_DIV6<<0) +#define I2S_MCLKDIV_DIV7 7 //MCLK = MCLK source / 14 +#define mskI2S_MCLKDIV_DIV7 (I2S_MCLKDIV_DIV7<<0) + + +#define I2S_MCLKOEN_OUTPUT_DIS 0 //[3:3]MCLK output enable bit +#define I2S_MCLKOEN_OUTPUT_EN 1 +#define mskI2S_MCLKOEN_OUTPUT_DIS (I2S_MCLKOEN_OUTPUT_DIS<<3) +#define mskI2S_MCLKOEN_OUTPUT_EN (I2S_MCLKOEN_OUTPUT_EN<<3) + + //[4:4]MCLK source selection bit +#define I2S_MCLKSEL_I2S_PCLK 0 //MCLK source of master is from I2S_PCLK +#define I2S_MCLKSEL_GPIO 1 //MCLK source of master is from GPIO +#define mskI2S_MCLKSEL_I2S_PCLK (I2S_MCLKSEL_I2S_PCLK<<4) +#define mskI2S_MCLKSEL_GPIO (I2S_MCLKSEL_GPIO<<4) + + //[15:8]BCLK divider +#define I2S_BCLKDIV_DIV 0 // MCLK/n, n = 2, 4, 6, 8, ...,512 +#define mskI2S_BCLKDIV_DIV (I2S_BCLKDIV_DIV<<8) + //[16:16]I2S clock source selection +#define I2S_CLKSEL_HCLK 0 //HCLK +#define I2S_CLKSEL_EHS 1 //EHS +#define mskI2S_CLKSEL_HCLK (I2S_CLKSEL_HCLK<<16) +#define mskI2S_CLKSEL_EHS (I2S_CLKSEL_EHS<<16) + + +/* I2S Status register (0x08) */ +#define mskI2S_I2SINT (0x1<<0) //I2S interrupt flag +#define mskI2S_RIGHTCH (0x1<<1) //Current channel status +#define mskI2S_TXFIFOTHF (0x1<<6) //TX FIFO threshold flag +#define mskI2S_RXFIFOTHF (0x1<<7) //RX FIFO threshold flag +#define mskI2S_TXFIFOFULL (0x1<<8) //TX FIFO full flag +#define mskI2S_RXFIFOFULL (0x1<<9) //RX FIFO full flag +#define mskI2S_TXFIFOEMPTY (0x1<<10) //TX FIFO empty flag +#define mskI2S_RXFIFOEMPTY (0x1<<11) //RX FIFO empty flag +#define mskI2S_TXFIFOLV (0xf<<12) //TX FIFO used level +#define mskI2S_RXFIFOLV (0xf<<17) //RX FIFO used level + + +/* I2S Interrupt Enable register (0x0C) */ +#define I2S_TXFIFOOVFIEN_DIS 0 //[4:4]TX FIFO overflow interrupt enable bit +#define I2S_TXFIFOOVFIEN_EN 1 +#define mskI2S_TXFIFOOVFIEN_DIS (I2S_TXFIFOOVFIEN_DIS<<4) +#define mskI2S_TXFIFOOVFIEN_EN (I2S_TXFIFOOVFIEN_EN<<4) + +#define I2S_RXFIFOUDFIEN_DIS 0 //[5:5]RX FIFO underflow interrupt enable bit +#define I2S_RXFIFOUDFIEN_EN 1 +#define mskI2S_RXFIFOUDFIEN_DIS (I2S_RXFIFOUDFIEN_DIS<<5) +#define mskI2S_RXFIFOUDFIEN_EN (I2S_RXFIFOUDFIEN_EN<<5) + +#define I2S_TXFIFOTHIEN_DIS 0 //[6:6]TX FIFO threshold interrupt enable bit +#define I2S_TXFIFOTHIEN_EN 1 +#define mskI2S_TXFIFOTHIEN_DIS (I2S_TXFIFOTHIEN_DIS<<6) +#define mskI2S_TXFIFOTHIEN_EN (I2S_TXFIFOTHIEN_EN<<6) + +#define I2S_RXFIFOTHIEN_DIS 0 //[7:7]RX FIFO threshold interrupt enable bit +#define I2S_RXFIFOTHIEN_EN 1 +#define mskI2S_RXFIFOTHIEN_DIS (I2S_RXFIFOTHIEN_DIS<<7) +#define mskI2S_RXFIFOTHIEN_EN (I2S_RXFIFOTHIEN_EN<<7) + + +/* I2S Raw Interrupt Status register (0x10) */ +/* I2S Interrupt Clear register (0x14) */ +#define mskI2S_TXFIFOOVIF (0x1<<4) //TX FIFO overflow interrupt flag +#define mskI2S_TXFIFOOVIC mskI2S_TXFIFOOVIF +#define mskI2S_RXFIFOUDIF (0x1<<5) //RX FIFO underflow interrupt flag +#define mskI2S_RXFIFOUDIC mskI2S_RXFIFOUDIF +#define mskI2S_TXFIFOTHIF (0x1<<6) //TX FIFO threshold interrupt flag +#define mskI2S_TXFIFOTHIC mskI2S_TXFIFOTHIF +#define mskI2S_RXFIFOTHIF (0x1<<7) //RX FIFO threshold interrupt flag +#define mskI2S_RXFIFOTHIC mskI2S_RXFIFOTHIF + + +/*_____ M A C R O S ________________________________________________________*/ +//I2S HCLK Enable/Disable +#define __I2S_ENABLE_I2SHCLK SN_SYS1->AHBCLKEN |= (1<<22) +#define __I2S_DISABLE_I2SHCLK SN_SYS1->AHBCLKEN &= ~(1<<22) + +//Reset I2S FIFO +#define __I2S_RESET_TXFIFO (SN_I2S->CTRL_b.CLRTXFIFO = I2S_CLRTXFIFO_RESET_TXFIFO) +#define __I2S_RESET_RXFIFO (SN_I2S->CTRL_b.CLRRXFIFO = I2S_CLRRXFIFO_RESET_RXFIFO) + +//I2S Start +#define __I2S_START (SN_I2S->CTRL_b.START = 1) + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +void I2S_Master_Init(void); +void I2S_Slave_Init(void); +void I2S_Enable(void); +void I2S_Disable(void); +void I2S_Interrupt_Enable(void); + +#endif /*__SN32F2XX_I2S_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/PMU/PMU_drive.c b/os/hal/ports/SN32/LLD/SN32F2xx/PMU/PMU_drive.c new file mode 100644 index 00000000..82b0fb14 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/PMU/PMU_drive.c @@ -0,0 +1,51 @@ +/******************** (C) COPYRIGHT 2017 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2017/07 +* AUTHOR: SA1 +* IC: SN32F240B +* DESCRIPTION: PMU related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2017/07/07 SA1 1. First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + +/*************************************************************************************************** +* Function : PMU_Setting +* Description : Setting and enter specified Low power mode +* Input : mode - specified Low power mode (PMU_SLEEP, PMU_DEEP_SLEEP, PMU_DEEP_PWR_DOWN) +* Output : None +* Return : None +* Note : None +****************************************************************************************************/ +void PMU_Setting(uint16_t mode) +{ + + SN_PMU->CTRL = mode; + + __WFI(); + + SN_PMU->CTRL = 0x0; +} diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/PMU/PMU_drive.h b/os/hal/ports/SN32/LLD/SN32F2xx/PMU/PMU_drive.h new file mode 100644 index 00000000..988c6909 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/PMU/PMU_drive.h @@ -0,0 +1,18 @@ +#ifndef __SN32F2XX_PMU_H +#define __SN32F2XX_PMU_H + +/*_____ I N C L U D E S ____________________________________________________*/ +#include + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +#define PMU_SLEEP 4 +#define PMU_DEEP_SLEEP 2 + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +void PMU_Setting(uint16_t mode_sel); + +#endif /*__SN32F2XX_PMU_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/SPI/SPI.h b/os/hal/ports/SN32/LLD/SN32F2xx/SPI/SPI.h new file mode 100644 index 00000000..47861e9a --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/SPI/SPI.h @@ -0,0 +1,194 @@ +#ifndef __SN32F2XX_SPI_H +#define __SN32F2XX_SPI_H +#include "hal.h" + + +/*_____ I N C L U D E S ____________________________________________________*/ + +/*_____ D E F I N I T I O N S ______________________________________________*/ +/* +Base Address: 0x4001 C000 (SPI0) + +*/ + +/* SPI n Control register 0 (0x00) */ +#define SPI_SPIEN_DIS 0 //[0:0] SPI enable bit +#define SPI_SPIEN_EN 1 +#define mskSPI_SPIEN_DIS (SPI_SPIEN_DIS<<0) +#define mskSPI_SPIEN_EN (SPI_SPIEN_EN<<0) + + //[1:1] Loop back mode disable +#define SPI_LOOPBACK_DIS 0 //Disable +#define SPI_LOOPBACK_EN 1 //Data input from data output +#define mskSPI_LOOPBACK_DIS (SPI_LOOPBACK_DIS<<1) +#define mskSPI_LOOPBACK_EN (SPI_LOOPBACK_EN<<1) + + //[2:2] Slave data output disable bit (ONLY used in slave mode) +#define SPI_SDODIS_EN 0 //Enable slave data output +#define SPI_SDODIS_DIS 1 //Disable slave data output. (MISO=0) +#define mskSPI_SDODIS_EN (SPI_SDODIS_EN<<2) +#define mskSPI_SDODIS_DIS (SPI_SDODIS_DIS<<2) + +#define SPI_MS_MASTER_MODE 0 //[3:3] Master/Slave selection bit +#define SPI_MS_SLAVE_MODE 1 +#define mskSPI_MS_MASTER_MODE (SPI_MS_MASTER_MODE<<3) +#define mskSPI_MS_SLAVE_MODE (SPI_MS_SLAVE_MODE<<3) + + //[7:6] SPI FSM and FIFO Reset bit +#define SPI_FRESET_DO_NOTHING 0 //Do nothing +#define SPI_FRESET_RESET_FIFO 3 //Reset finite state machine and FIFO +#define mskSPI_FRESET_DO_NOTHING (SPI_FRESET_DO_NOTHING<<6) +#define mskSPI_FRESET_RESET_FIFO (SPI_FRESET_RESET_FIFO<<6) + +#define SPI_DL_3 2 //[11:8] Data Length = DL[3:0]+1 +#define SPI_DL_4 3 +#define SPI_DL_5 4 +#define SPI_DL_6 5 +#define SPI_DL_7 6 +#define SPI_DL_8 7 +#define SPI_DL_9 8 +#define SPI_DL_10 9 +#define SPI_DL_11 10 +#define SPI_DL_12 11 +#define SPI_DL_13 12 +#define SPI_DL_14 13 +#define SPI_DL_15 14 +#define SPI_DL_16 15 + +#define SPI_TXFIFOTH_0 0 //[14:12]TX FIFO Threshold level +#define SPI_TXFIFOTH_1 1 +#define SPI_TXFIFOTH_2 2 +#define SPI_TXFIFOTH_3 3 +#define SPI_TXFIFOTH_4 4 +#define SPI_TXFIFOTH_5 5 +#define SPI_TXFIFOTH_6 6 +#define SPI_TXFIFOTH_7 7 + +#define SPI_RXFIFOTH_0 0 //[17:15]RX FIFO Threshold level +#define SPI_RXFIFOTH_1 1 +#define SPI_RXFIFOTH_2 2 +#define SPI_RXFIFOTH_3 3 +#define SPI_RXFIFOTH_4 4 +#define SPI_RXFIFOTH_5 5 +#define SPI_RXFIFOTH_6 6 +#define SPI_RXFIFOTH_7 7 + + //[18:18]Auto-SEL disable bit. For SPI mode only. +#define SPI_SELDIS_EN 0 //Enable Auto-SEL flow control +#define SPI_SELDIS_DIS 1 //Disable Auto-SEL flow control +#define mskSPI_SELDIS_EN (SPI_SELDIS_EN<<18) +#define mskSPI_SELDIS_DIS (SPI_SELDIS_DIS<<18) + + +/* SPI n Control register 1 (0x04) */ + //[0:0]MSB/LSB selection bit +#define SPI_MLSB_MSB 0 //MSB transmit first +#define SPI_MLSB_LSB 1 //LSB transmit first +#define mskSPI_MLSB_MSB (SPI_MLSB_MSB<<0) +#define mskSPI_MLSB_LSB (SPI_MLSB_LSB<<0) + + //[1:1]Clock polarity selection bit +#define SPI_CPOL_SCK_IDLE_LOW 0 //SCK idles at Low level +#define SPI_CPOL_SCK_IDLE_HIGH 1 //SCK idles at High level +#define mskSPI_CPOL_SCK_IDLE_LOW (SPI_CPOL_SCK_IDLE_LOW<<1) +#define mskSPI_CPOL_SCK_IDLE_HIGH (SPI_CPOL_SCK_IDLE_HIGH<<1) + + //[2:2]Clock phase for edge sampling +#define SPI_CPHA_FALLING_EDGE 0 //Data changes at clock falling edge +#define SPI_CPHA_RISING_EDGE 1 //Data changes at clock rising edge +#define mskSPI_CPHA_FALLING_EDGE (SPI_CPHA_FALLING_EDGE<<2) +#define mskSPI_CPHA_RISING_EDGE (SPI_CPHA_RISING_EDGE<<2) + + +/* SPI n Clock Divider register (0x08) */ + //[7:0]SPIn clock divider +#define SPI_DIV 6 //MCLK/n,MCLK=system clk n = 2, 4, 6, 8, ...,512 + + +/* SPI n Status register (0x0C) */ +#define mskSPI_TX_EMPTY (0x1<<0) //TX FIFO empty flag +#define mskSPI_TX_FULL (0x1<<1) //TX FIFO full flag +#define mskSPI_RX_EMPTY (0x1<<2) //RX FIFO empty flag +#define mskSPI_RX_FULL (0x1<<3) //RX FIFO full flag +#define mskSPI_BUSY (0x1<<4) //Busy flag +#define mskSPI_TXFIFOTHF (0x1<<5) //TX FIFO threshold flag +#define mskSPI_RXFIFOTHF (0x1<<6) //RX FIFO threshold flag + + +/* SPI n Interrupt Enable register (0x10) */ +#define SPI_RXOVFIE_DIS 0 //[0:0]RX Overflow interrupt enable +#define SPI_RXOVFIE_EN 1 +#define mskSPI_RXOVFIE_DIS (SPI_RXOVFIE_DIS<<0) +#define mskSPI_RXOVFIE_EN (SPI_RXOVFIE_EN<<0) + +#define SPI_RXTOIE_DIS 0 //[1:1]RX time-out interrupt enable +#define SPI_RXTOIE_EN 1 +#define mskSPI_RXTOIE_DIS (SPI_RXTOIE_DIS<<1) +#define mskSPI_RXTOIE_EN (SPI_RXTOIE_EN<<1) + +#define SPI_RXFIFOTHIE_DIS 0 //[2:2]RX FIFO threshold interrupt enable +#define SPI_RXFIFOTHIE_EN 1 +#define mskSPI_RXFIFOTHIE_DIS (SPI_RXFIFOTHIE_DIS<<2) +#define mskSPI_RXFIFOTHIE_EN (SPI_RXFIFOTHIE_EN <<2) + +#define SPI_TXFIFOTHIE_DIS 0 //[3:3]TX FIFO threshold interrupt enable +#define SPI_TXFIFOTHIE_EN 1 +#define mskSPI_TXFIFOTHIE_DIS (SPI_TXFIFOTHIE_DIS<<3) +#define mskSPI_TXFIFOTHIE_EN (SPI_TXFIFOTHIE_EN<<3) + + +/* SPI n Raw Interrupt Status register (0x14) */ +/* SPI n Interrupt Clear register (0x18) */ +#define mskSPI_RXOVFIF (0x1<<0) //[0:0]RX overflow interrupt flag +#define mskSPI_RXOVFIC mskSPI_RXOVFIF + +#define mskSPI_RXTOIF (0x1<<1) //[1:1]RX time-out interrupt flag +#define mskSPI_RXTOIC mskSPI_RXTOIF + +#define mskSPI_RXFIFOTHIF (0x1<<2) //[2:2]RX FIFO threshold interrupt flag +#define mskSPI_RXFIFOTHIC mskSPI_RXFIFOTHIF + +#define mskSPI_TXFIFOTHIF (0x1<<3) //[3:3]TX FIFO threshold interrupt flag +#define mskSPI_TXFIFOTHIC mskSPI_TXFIFOTHIF + + +/* SPI n Data Fetch register (0x20) */ +//[0:0]SPI data fetch control bit +#define SPI_DF_DIS 0 //Disable +#define SPI_DF_EN 1 //Enable when SCKn frequency > 6MHz +#define mskSPI_DF_DIS (SPI_DF_DIS<<0) +#define mskSPI_SPI_DF_EN (SPI_DF_EN<<0) + + +/*_____ M A C R O S ________________________________________________________*/ +#define __SPI0_FIFO_RESET (SN_SPI0->CTRL0_b.FRESET = SPI_FRESET_RESET_FIFO) +#define __SPI1_FIFO_RESET (SN_SPI1->CTRL0_b.FRESET = SPI_FRESET_RESET_FIFO) +#define __SPI0_CLR_SEL0 (SN_GPIO2->DATA_b.DATA9 = 0) +#define __SPI0_SET_SEL0 (SN_GPIO2->DATA_b.DATA9 = 1) +#define __SPI1_CLR_SEL0 (SN_GPIO2->DATA_b.DATA10 = 0) +#define __SPI1_SET_SEL0 (SN_GPIO2->DATA_b.DATA10 = 1) + +//SPI Data Fetch speed (High: SCK>6MHz) +#if defined(SN32F260) +#define __SPI0_DATA_FETCH_HIGH_SPEED (SN_SPI0->DF = SPI_DF_EN) +#define __SPI1_DATA_FETCH_HIGH_SPEED (SN_SPI1->DF = SPI_DF_EN) +#else +#define __SPI0_DATA_FETCH_HIGH_SPEED (SN_SPI0->DFDLY = SPI_DF_EN) +#define __SPI1_DATA_FETCH_HIGH_SPEED (SN_SPI1->DFDLY = SPI_DF_EN) +#endif + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +extern void SPI0_Init(void); +extern void SPI0_Enable(void); +extern void SPI0_Disable(void); +extern void SPI0_Write1(uint8_t data); +extern void SPI0_Write(uint8_t *data, uint8_t len); +extern void SPI0_Write_End(void); + +extern void SPI1_Init(void); +extern void SPI1_Enable(void); +extern void SPI1_Disable(void); +extern void SPI1_Write1(uint8_t data); +extern void SPI1_Write(uint8_t *data, uint8_t len); +extern void SPI1_Write_End(void); +#endif /*__SN32F2xx_SPI_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/SPI/SPI0.c b/os/hal/ports/SN32/LLD/SN32F2xx/SPI/SPI0.c new file mode 100644 index 00000000..cb57523b --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/SPI/SPI0.c @@ -0,0 +1,138 @@ +/******************** (C) COPYRIGHT 2014 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2014/05 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: SPI0 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 1. First release +* 1.1 2014/05/23 SA1 1. Add __SSP0_DATA_FETCH_HIGH_SPEED macro +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include "SPI.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + +/***************************************************************************** +* Function : SPI0_Init +* Description : Initialization of SPI0 init +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void SPI0_Init() { + sys1EnableSPI0(); + SN_SPI0->CTRL0_b.DL = SPI_DL_8; + +#ifdef SN32_SPI_SLAVE_MODE + SN_SPI0->CTRL0_b.MS = SPI_MS_SLAVE_MODE; + SN_SPI0->CTRL0_b.SDODIS = SPI_SDODIS_EN; +#else + SN_SPI0->CTRL0_b.MS = SPI_MS_MASTER_MODE; +#endif + + SN_SPI0->CTRL0_b.LOOPBACK = SPI_LOOPBACK_DIS; + +#ifdef SN32_SPI_RXFIFO_THRESHOLD + SN_SPI0->CTRL0_b.RXFIFOTH = SN32_SPI_TXFIFO_THRESHOLD; +#endif + +#ifdef SN32_SPI_TXFIFO_THRESHOLD + SN_SPI0->CTRL0_b.TXFIFOTH = SN32_SPI_TXFIFO_THRESHOLD; +#endif + +#ifdef SN32_SPI_CLKDIV + SN_SPI0->CLKDIV_b.DIV = SN32_SPI_CLKDIV; +#else + SN_SPI0->CLKDIV_b.DIV = (SPI_DIV / 2) - 1; +#endif + + SN_SPI0->CTRL1_b.CPHA = SPI_CPHA_FALLING_EDGE; + SN_SPI0->CTRL1_b.CPOL = SPI_CPOL_SCK_IDLE_LOW; + SN_SPI0->CTRL1_b.MLSB = SPI_MLSB_MSB; + +#ifdef SN32_SPI_AUTOSEL + SN_SPI0->CTRL0_b.SELDIS = SN32_SPI_AUTOSEL; +#endif + + __SPI0_FIFO_RESET; + + uint32_t spiClock = (SN32_HCLK / ((2 * SN_SPI0->CLKDIV_b.DIV) + 2)); + if (spiClock > 6000000) { + __SPI0_DATA_FETCH_HIGH_SPEED; + } + + NVIC_DisableIRQ(SN32_SPI0_NUMBER); +} + +/***************************************************************************** +* Function : SPI0_Enable +* Description : SPI0 enable setting +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void SPI0_Enable() { + sys1EnableSPI0(); +#if defined(SN32F260) + SN_SPI0->CTRL0_b.SSPEN = SPI_SPIEN_EN; +#else + SN_SPI0->CTRL0_b.SPIEN = SPI_SPIEN_EN; +#endif + __SPI0_FIFO_RESET; +} + +/***************************************************************************** +* Function : SPI0_Disable +* Description : SPI0 disable setting +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void SPI0_Disable() { +#if defined(SN32F260) + SN_SPI0->CTRL0_b.SSPEN = SPI_SPIEN_DIS; +#else + SN_SPI0->CTRL0_b.SPIEN = SPI_SPIEN_DIS; +#endif + //Disable HCLK for SSP0 + sys1DisableSPI0(); +} + +void SPI0_Write1(uint8_t data) { + while (SN_SPI0->STAT_b.TX_FULL); + SN_SPI0->DATA = data; +} + +void SPI0_Write(uint8_t *data, uint8_t len) { + for (uint8_t i = 0; i < len; i++) { + SPI0_Write1(data[i]); + } +} + +void SPI0_Write_End() { + while (!SN_SPI0->STAT_b.TX_EMPTY); +} diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/SPI/SPI1.c b/os/hal/ports/SN32/LLD/SN32F2xx/SPI/SPI1.c new file mode 100644 index 00000000..8253a9b4 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/SPI/SPI1.c @@ -0,0 +1,133 @@ +/******************** (C) COPYRIGHT 2014 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2014/05 +* AUTHOR: SA1 +* IC: SN32F240/230/220 +* DESCRIPTION: SPI1 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2013/12/17 SA1 1. First release +* 1.1 2014/05/23 SA1 1. Add __SSP1_DATA_FETCH_HIGH_SPEED macro +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include "SPI.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + +/***************************************************************************** +* Function : SPI1_Init +* Description : Initialization of SPI1 init +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void SPI1_Init() { + sys1EnableSPI1(); + SN_SPI1->CTRL0_b.DL = SPI_DL_8; + +#ifdef SN32_SPI_SLAVE_MODE + SN_SPI1->CTRL0_b.MS = SPI_MS_SLAVE_MODE; + SN_SPI1->CTRL0_b.SDODIS = SPI_SDODIS_EN; +#else + SN_SPI1->CTRL0_b.MS = SPI_MS_MASTER_MODE; +#endif + + SN_SPI1->CTRL0_b.LOOPBACK = SPI_LOOPBACK_DIS; + +#ifdef SN32_SPI_RXFIFO_THRESHOLD + SN_SPI1->CTRL0_b.RXFIFOTH = SN32_SPI_TXFIFO_THRESHOLD; +#endif + +#ifdef SN32_SPI_TXFIFO_THRESHOLD + SN_SPI1->CTRL0_b.TXFIFOTH = SN32_SPI_TXFIFO_THRESHOLD; +#endif + +#ifdef SN32_SPI_CLKDIV + SN_SPI1->CLKDIV_b.DIV = SN32_SPI_CLKDIV; +#else + SN_SPI1->CLKDIV_b.DIV = (SPI_DIV / 2) - 1; +#endif + + SN_SPI1->CTRL1_b.CPHA = SPI_CPHA_FALLING_EDGE; + SN_SPI1->CTRL1_b.CPOL = SPI_CPOL_SCK_IDLE_LOW; + SN_SPI1->CTRL1_b.MLSB = SPI_MLSB_MSB; + +#ifdef SN32_SPI_AUTOSEL + SN_SPI1->CTRL0_b.SELDIS = SN32_SPI_AUTOSEL; +#endif + + __SPI1_FIFO_RESET; + + uint32_t spiClock = (SN32_HCLK / ((2 * SN_SPI1->CLKDIV_b.DIV) + 2)); + if (spiClock > 6000000) { + __SPI1_DATA_FETCH_HIGH_SPEED; + } + + NVIC_DisableIRQ(SN32_SPI1_NUMBER); +} + +/***************************************************************************** +* Function : SPI1_Enable +* Description : SPI1 enable setting +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void SPI1_Enable() { + sys1EnableSPI1(); + + SN_SPI1->CTRL0_b.SPIEN = SPI_SPIEN_EN; + + __SPI1_FIFO_RESET; +} + +/***************************************************************************** +* Function : SPI1_Disable +* Description : SPI1 disable setting +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void SPI1_Disable() { + SN_SPI1->CTRL0_b.SPIEN = SPI_SPIEN_DIS; + + //Disable HCLK for SSP1 + sys1DisableSPI1(); +} + +void SPI1_Write1(uint8_t data) { + while (SN_SPI1->STAT_b.TX_FULL); + SN_SPI1->DATA = data; +} + +void SPI1_Write(uint8_t *data, uint8_t len) { + for (uint8_t i = 0; i < len; i++) { + SPI1_Write1(data[i]); + } +} + +void SPI1_Write_End() { + while (!SN_SPI1->STAT_b.TX_EMPTY); +} diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/SPI/driver.mk b/os/hal/ports/SN32/LLD/SN32F2xx/SPI/driver.mk new file mode 100644 index 00000000..a36e42a5 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/SPI/driver.mk @@ -0,0 +1,3 @@ +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/SPI/SPI0.c + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/SPI diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/SysTick.c b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/SysTick.c new file mode 100644 index 00000000..e754c430 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/SysTick.c @@ -0,0 +1,71 @@ +/******************** (C) COPYRIGHT 2017 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2017/07 +* AUTHOR: SA1 +* IC: SN32F240B +* DESCRIPTION: SysTick related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2017/07/07 SA1 First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include "SysTick.h" + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ +/***************************************************************************** +* Function : SysTick_Init +* Description : Initialization of SysTick timer +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void SysTick_Init (void) +{ + SystemCoreClockUpdate(); + + __SYSTICK_SET_TIMER_PERIOD(10); //RELOAD = (system tick clock frequency ¡Ñ 10 ms)/1000 -1 + + __SYSTICK_CLEAR_COUNTER_AND_FLAG; + +#if SYSTICK_IRQ == INTERRUPT_METHOD + SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt +#else + SysTick->CTRL = 0x5; //Enable SysTick timer ONLY +#endif +} + + +/***************************************************************************** +* Function : SysTick_Handler +* Description : ISR of SysTick interrupt +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void SysTick_Handler(void) +{ + __SYSTICK_CLEAR_COUNTER_AND_FLAG; +} + + diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/SysTick.h b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/SysTick.h new file mode 100644 index 00000000..7a6379a7 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/SysTick.h @@ -0,0 +1,23 @@ +#ifndef __SN32F2XX_SYSTICK_H +#define __SN32F2XX_SYSTICK_H + + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include + + +/*_____ D E F I N I T I O N S ______________________________________________*/ +#define SYSTICK_IRQ POLLING_METHOD //INTERRUPT_METHOD: Enable SysTick timer and interrupt + //POLLING_METHOD: Enable SysTick timer ONLY + +/*_____ M A C R O S ________________________________________________________*/ +#define __SYSTICK_SET_TIMER_PERIOD(ms) SysTick->LOAD = SystemCoreClock * ms /1000 - 1 +#define __SYSTICK_CLEAR_COUNTER_AND_FLAG SysTick->VAL = 0xFF + + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +void SysTick_Init(void); + +#endif /*__SN32F2XX_SYSTICK_H*/ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/driver.mk b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/driver.mk new file mode 100644 index 00000000..35e23189 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_SYSTICK TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.c +endif +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/SysTick + diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.c new file mode 100644 index 00000000..4c97c39f --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.c @@ -0,0 +1,177 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_st_lld.c + * @brief PLATFORM ST subsystem low level driver source. + * + * @addtogroup ST + * @{ + */ + +#include "hal.h" + +#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ +#define SYSTICK_CK SN32_HCLK + +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + +#if (OSAL_ST_RESOLUTION == 32) +#error "Tickless mode on SN32 supports only 16bit timers" +#endif + +#if SN32_ST_USE_TIMER == CT16B0 + +#if !SN32_HAS_CT16B0 +#error "CT16B0 not present in the selected device" +#endif + +#define ST_HANDLER SN32_CT16B0_HANDLER +#define ST_NUMBER SN32_CT16B0_NUMBER +#define ST_ENABLE_CLOCK() sys1EnableCT16B0() +#define ST_INIT_CLOCK() CT16B0_ResetTimer() + +#elif SN32_ST_USE_TIMER == CT16B1 + +#if !SN32_HAS_CT16B1 +#error "CT16B1 not present in the selected device" +#endif + +#define ST_HANDLER SN32_CT16B1_HANDLER +#define ST_NUMBER SN32_CT16B1_NUMBER +#define ST_ENABLE_CLOCK() sys1EnableCT16B1() +#define ST_INIT_CLOCK() CT16B1_ResetTimer() + +#else +#error "SN32_ST_USE_TIMER specifies an unsupported timer" +#endif + +#if SYSTICK_CK % OSAL_ST_FREQUENCY != 0 +#error "the selected ST frequency is not obtainable because integer rounding" +#endif + +#if (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1 > 0xFF +#error "the selected ST frequency is not obtainable because CT16 timer prescaler limits" +#endif + +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC + +#define ST_HANDLER SysTick_Handler + +#if SYSTICK_CK % OSAL_ST_FREQUENCY != 0 +#error "the selected ST frequency is not obtainable because integer rounding" +#endif + +#if (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1 > 0xFFFFFF +#error "the selected ST frequency is not obtainable because SysTick timer counter limits" +#endif + +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +OSAL_IRQ_HANDLER(ST_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + st_lld_serve_interrupt(); + OSAL_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ST driver initialization. + * + * @notapi + */ +void st_lld_init(void) { + +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + /* Free running counter mode.*/ + + /* Enabling timer clock.*/ + ST_ENABLE_CLOCK(); + ST_INIT_CLOCK(); + /* Initializing the counter in free running mode.*/ + SN32_ST_TIM->PRE = (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1; + SN32_ST_TIM->IC &= 0x1FFFFFF; + SN32_ST_TIM->TMRCTRL |= mskCT16_CEN_EN; + + /* IRQ enabled.*/ + nvicEnableVector(ST_NUMBER, SN32_ST_IRQ_PRIORITY); +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC + + /* Periodic systick mode, the Cortex-Mx internal systick timer is used + in this mode.*/ + SysTick->LOAD = (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + /* IRQ enabled.*/ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, SN32_ST_IRQ_PRIORITY); +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ +} + +/** + * @brief IRQ handling code. + */ +void st_lld_serve_interrupt(void) { +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + uint32_t ris; + sn32_ct_t *ct = SN32_ST_TIM; + + ris = ct->RIS; + if ((ris & mskCT16_MR0IF) != 0U) +#endif + { + osalSysLockFromISR(); + osalOsTimerHandlerI(); + osalSysUnlockFromISR(); + } +} +#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.h new file mode 100644 index 00000000..1c899ca7 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.h @@ -0,0 +1,202 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_st_lld.h + * @brief PLATFORM ST subsystem low level driver header. + * @details This header is designed to be include-able without having to + * include other files from the HAL. + * + * @addtogroup ST + * @{ + */ + +#ifndef HAL_ST_LLD_H +#define HAL_ST_LLD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief SysTick timer IRQ priority. + */ +#if !defined(SN32_ST_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SN32_ST_IRQ_PRIORITY 8 +#endif + +/** + * @brief CT16Bx unit (by number) to be used for free running operations. + * @note You must select a 16 bits timer if a 16 bits @p systick_t type + * is required. + * @note Timers CT16B0 and CT16B1 are supported. + */ +#if !defined(SN32_ST_USE_TIMER) || defined(__DOXYGEN__) +#define SN32_ST_USE_TIMER CT16B0 +#endif +/** @} */ +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ +#if !defined(SN32_HAS_CT16B0) +#define SN32_HAS_CT16B0 FALSE +#endif + +#if !defined(SN32_HAS_CT16B1) +#define SN32_HAS_CT16B1 FALSE +#endif +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + +#if SN32_ST_USE_TIMER == CT16B0 + +#if defined(SN32_CT16B0_IS_USED) +#error "ST requires CT16B0 but the timer is already used" +#else +#define SN32_CT16B0_IS_USED +#endif + +#define SN32_ST_TIM SN32_CT16B0 +#define ST_LLD_NUM_ALARMS 1 + +#elif SN32_ST_USE_TIMER == CT16B1 + +#if defined(SN32_CT16B1_IS_USED) +#error "ST requires CT16B1 but the timer is already used" +#else +#define SN32_CT16B1_IS_USED +#endif + +#define SN32_ST_TIM SN32_CT16B1 +#define ST_LLD_NUM_ALARMS 1 + +#else +#error "SN32_ST_USE_TIMER specifies an unsupported timer" +#endif + +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void st_lld_init(void); + void st_lld_serve_interrupt(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Driver inline functions. */ +/*===========================================================================*/ + +#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__) + +/** + * @brief Returns the time counter value. + * + * @return The counter value. + * + * @notapi + */ +static inline systime_t st_lld_get_counter(void) { + return (systime_t)(SN32_ST_TIM->TC & 0x0000FFFF); +} + +/** + * @brief Starts the alarm. + * @note Makes sure that no spurious alarms are triggered after + * this call. + * + * @param[in] abstime the time to be set for the first alarm + * + * @notapi + */ +static inline void st_lld_start_alarm(systime_t abstime) { + SN32_ST_TIM->MR0 = (uint32_t)abstime; + SN32_ST_TIM->IC &= 0x1FFFFFF; + SN32_ST_TIM->MCTRL |= mskCT16_MR0IE_EN; +} + +/** + * @brief Stops the alarm interrupt. + * + * @notapi + */ +static inline void st_lld_stop_alarm(void) { + SN32_ST_TIM->MCTRL &= ~mskCT16_MR0IE_EN; +} + +/** + * @brief Sets the alarm time. + * + * @param[in] abstime the time to be set for the next alarm + * + * @notapi + */ +static inline void st_lld_set_alarm(systime_t abstime) { + SN32_ST_TIM->MR0 = (uint32_t)abstime; +} + +/** + * @brief Returns the current alarm time. + * + * @return The currently set alarm time. + * + * @notapi + */ +static inline systime_t st_lld_get_alarm(void) { + + return (systime_t)(SN32_ST_TIM->MR0 & 0x0000FFFF); +} + +/** + * @brief Determines if the alarm is active. + * + * @return The alarm status. + * @retval false if the alarm is not active. + * @retval true is the alarm is active + * + * @notapi + */ +static inline bool st_lld_is_alarm_active(void) { + + return (bool)((SN32_ST_TIM->MCTRL & mskCT16_MR0IE_EN) != 0); +} + +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +#endif /* HAL_ST_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART.h b/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART.h new file mode 100644 index 00000000..cd33abbe --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART.h @@ -0,0 +1,184 @@ +#ifndef __SN32F2XX_UART_H +#define __SN32F2XX_UART_H + + +/*_____ I N C L U D E S ____________________________________________________*/ +#include + +/*_____ D E F I N I T I O N S ______________________________________________*/ +/* +Base Address: 0x4001 6000 (UART0) + 0x4001 4000 (UART1) + 0x4001 2000 (UART1) +*/ +#define UART0_CLK_EN (0x01<<16) +#define UART1_CLK_EN (0x01<<17) +#define UART2_CLK_EN (0x01<<18) + +/**************Line Control Define******/ +#define UART_CHARACTER_LEN5BIT (0x00) +#define UART_CHARACTER_LEN6BIT (0x01) +#define UART_CHARACTER_LEN7BIT (0x02) +#define UART_CHARACTER_LEN8BIT (0x03) +/***********************/ +#define UART_STOPBIT_1BIT (0x0<<2) +#define UART_STOPBIT_2BIT (0x1<<2) +/***********************/ +#define UART_PARITY_BIT_DISEN (0x0<<3) +#define UART_PARITY_BIT_EN (0x1<<3) +/***********************/ +#define UART_PARITY_SELECTODD (0x00<<4) +#define UART_PARITY_SELECTEVEN (0x01<<4) +#define UART_PARITY_SELECTFORC1 (0x02<<4) +#define UART_PARITY_SELECTFORC0 (0x03<<4) +/***********************/ +#define UART_BREAK_DISEN (0x0<<6) +#define UART_BREAK_EN (0x1<<6) +/***********************/ +#define UART_DIVISOR_DISEN (0x0<<7) +#define UART_DIVISOR_EN (0x1<<7) + +#define UART_OVER_SAMPLE_16 (0x0<<8) +#define UART_OVER_SAMPLE_8 (0x1<<8) +/***Baud rate pre-scaler multilier = MULVAL+1***/ +#define UART_MULVAL_0 (0x0000<<4) +#define UART_MULVAL_1 (0x0001<<4) +#define UART_MULVAL_2 (0x0002<<4) +#define UART_MULVAL_3 (0x0003<<4) +#define UART_MULVAL_4 (0x0004<<4) +#define UART_MULVAL_5 (0x0005<<4) +#define UART_MULVAL_6 (0x0006<<4) +#define UART_MULVAL_7 (0x0007<<4) +#define UART_MULVAL_8 (0x0008<<4) +#define UART_MULVAL_9 (0x0009<<4) +#define UART_MULVAL_10 (0x000A<<4) +#define UART_MULVAL_11 (0x000B<<4) +#define UART_MULVAL_12 (0x000C<<4) +#define UART_MULVAL_13 (0x000D<<4) +#define UART_MULVAL_14 (0x000E<<4) +#define UART_MULVAL_15 (0x000F<<4) +/***Buad rate pre-scaler divisor value********/ +#define UART_DIVADDVAL_0 (0x000) +#define UART_DIVADDVAL_1 (0x001) +#define UART_DIVADDVAL_2 (0x002) +#define UART_DIVADDVAL_3 (0x003) +#define UART_DIVADDVAL_4 (0x004) +#define UART_DIVADDVAL_5 (0x005) +#define UART_DIVADDVAL_6 (0x006) +#define UART_DIVADDVAL_7 (0x007) +#define UART_DIVADDVAL_8 (0x008) +#define UART_DIVADDVAL_9 (0x009) +#define UART_DIVADDVAL_10 (0x00A) +#define UART_DIVADDVAL_11 (0x00B) +#define UART_DIVADDVAL_12 (0x00C) +#define UART_DIVADDVAL_13 (0x00D) +#define UART_DIVADDVAL_14 (0x00E) +#define UART_DIVADDVAL_15 (0x00F) +/***UART divisor latch MSB reg[7:0]. determines the baud rate***/ + + +/***UART divisor latch LSB reg[7:0]. determines the baud rate***/ + + +#define UART_FIFO_ENABLE (0x01) +#define UART_RXFIFO_RESET (0x01<<1) +#define UART_TXFIFO_RESET (0x01<<2) + +#define UART_RXTRIGGER_LEVEL1 (0x00<<6) + + +/***UART Interrupt Enable register***/ +#define UART_ABTOIE_EN (0x01<<9) //auto-buad time out INT +#define UART_ABEOIE_EN (0x01<<8) //End of auto-buad INT +#define UART_TEMTIE_EN (0x01<<4) //Transmitter empty flag +#define UART_RLSIE_EN (0x01<<2) //Rx Receive line status(RLS) INT +#define UART_THREIE_EN (0x01<<1) //Transmitter holding register empty flag INT +#define UART_RDAIE_EN (0x01) //character receive(RDA) time-out INT + +/*** UARTn_CTRL************/ +#define UART_EN (0x01) +#define UART_RX_EN (0x01<<6) +#define UART_TX_EN (0x01<<7) +#define UART_CTRL_EN 1 +#define UART_CTRL_DIS 0 +#define UART_FIFOCTRL_RESET 1 + +/*** UARTn_ABCCTRL************/ +#define UART_ABCCTRL_START (0x01) //START:1(Auto-baud is running), START:0(Auto-baud is not running) +#define UART_ABCCTRL_MODE0 (0x00<<1) +#define UART_ABCCTRL_MODE1 (0x01<<1) +#define UART_ABCCTRL_RESTART (0x01<<2) +#define UART_ABEO_EN (0x01<<8) +#define UART_ABTO_EN (0x01<<9) + +/*** Line status register************/ +#define UART_LS_RDR (0x01) //receiver data ready flag +#define UART_LS_OE (0x01<<1) //overrun error flag +#define UART_LS_PE (0x01<<2) //parity error flag +#define UART_LS_FE (0x01<<3) //framing error flag +#define UART_LS_BI (0x01<<4) //break interrupt flag +#define UART_LS_THRE (0x01<<5) //transmitter holding register empty flag +#define UART_LS_TEMT (0x01<<6) //transmitter empty flag +#define UART_LS_RXFE (0x01<<7) //error in RX FIFO flag +#define mskUART_LS_RDR (0x01) +#define mskUART_LS_OE (0x01<<1) +#define mskUART_LS_PE (0x01<<2) +#define mskUART_LS_FE (0x01<<3) +#define mskUART_LS_BI (0x01<<4) +#define mskUART_LS_THRE (0x01<<5) +#define mskUART_LS_TEMT (0x01<<6) +#define mskUART_LS_RXFE (0x01<<7) + +/*** Interrupt Identification register************/ +#define UART_RLS 3 +#define UART_RDA 2 +#define UART_THRE 1 +#define UART_TEMT 7 +#define UART_II_STATUS 0 //the INTstatus can be determined by UARTn_II[3:1] +#define UART_II_ABEOIF (0x01<<8) //end of auto-baud interrupt flag +#define UART_II_ABTOIF (0x01<<9) //auto-baud time-out interrupt flag +#define mskUART_INTID_STATUS 7 //interrupt corresponding to the UARTn RX FIFO +#define mskUART_II_STATUS (0x01) +#define mskUART_II_ABEOIF (0x01<<8) +#define mskUART_II_ABTOIF (0x01<<9) + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +extern uint32_t GulNum; +extern uint8_t bUART0_RecvFIFO[]; +extern uint32_t GulNum1; +extern uint8_t bUART1_RecvFIFO[]; +extern uint32_t GulNum2; +extern uint8_t bUART2_RecvFIFO[]; +extern volatile uint8_t bUART0_RecvNew; +extern volatile uint8_t bUART1_RecvNew; +extern volatile uint8_t bUART2_RecvNew; + + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +extern void UART0_Init(void); +extern void UART0_SendByte (uint8_t ucDat); +extern void UART0_Enable(void); +extern void UART0_Disable(void); +extern void UART0_InterruptEnable(void); +extern void UART0_AutoBaudrateInit(void); + +extern void UART1_Init(void); +extern void UART1_SendByte (uint8_t ucDat); +extern void UART1_Enable(void); +extern void UART1_Disable(void); +extern void UART1_InterruptEnable(void); +extern void UART1_AutoBaudrateInit(void); + +void UART2_Init(void); +void UART2_SendByte (uint8_t ucDat); +void UART2_Enable(void); +void UART2_Disable(void); +void UART2_InterruptEnable(void); +void UART2_AutoBaudrateInit(void); + +#endif /*__SN32F2XX_UART_H*/ + diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART0.c b/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART0.c new file mode 100644 index 00000000..960affc6 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART0.c @@ -0,0 +1,250 @@ +/******************** (C) COPYRIGHT 2017 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2017/07 +* AUTHOR: SA1 +* IC: SN32F240B +* DESCRIPTION: UART0 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2017/07/07 SA1 First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include "UART.h" + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +volatile uint8_t bUART0_RecvNew; +uint32_t GulNum; +uint8_t bUART0_RecvFIFO[56]; + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + +/***************************************************************************** +* Function : UART0_IRQHandler +* Description : UART0 interrupt service routine +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void UART0_IRQHandler (void) +{ + uint32_t II_Buf, LS_Buf; + volatile uint32_t Null_Buf; + + II_Buf = SN_UART0->II; + while ((II_Buf & mskUART_II_STATUS) == UART_II_STATUS) //check interrupt status, the INT can be determined by USARTn_II[3:1] + { + switch ((II_Buf>>1) & mskUART_INTID_STATUS) + { + case UART_RLS: //Receive Line Status + LS_Buf = SN_UART0->LS; + if((LS_Buf & mskUART_LS_OE) == UART_LS_OE) //Overrun Error + { } + if((LS_Buf & mskUART_LS_RXFE) == UART_LS_RXFE)//RX FIFO Error + { + if((LS_Buf & mskUART_LS_PE) == UART_LS_PE)//Parity Error + Null_Buf = SN_UART0->RB; //Clear interrupt + if((LS_Buf & mskUART_LS_FE) == UART_LS_FE) //Framing Error + Null_Buf = SN_UART0->RB; //Clear interrupt + if((LS_Buf & mskUART_LS_BI) == UART_LS_BI) //Break Interrupt + Null_Buf = SN_UART0->RB; //Clear interrupt + } + break; + + case UART_RDA: //Receive Data Available + LS_Buf = SN_UART0->LS; + bUART0_RecvNew = 1; + if((LS_Buf & mskUART_LS_RDR) == UART_LS_RDR)//Receiver Data Ready + { + bUART0_RecvFIFO[GulNum] = SN_UART0->RB; + GulNum++; + } + if(GulNum == 56) + GulNum = 0; + break; + + case UART_THRE: //THRE interrupt + LS_Buf = SN_UART0->LS; + if((LS_Buf & mskUART_LS_THRE) == UART_LS_THRE)//THRE empty + { //SN_UART0->TH = Null_Buf; //Clear interrupt + } + break; + + case UART_TEMT: //TEMT interrupt + LS_Buf = SN_UART0->LS; + if((LS_Buf & mskUART_LS_TEMT) == UART_LS_TEMT) + { //SN_UART0->TH = Null_Buf; //Clear interrupt + } + break; + + default: + break; + } //end switch ((II_Buf>>1) & mskUART_INTID_STATUS) + + II_Buf = SN_UART0->II; + } //end while ((II_Buf&0x01) == mskUART_II_STATUS) + + if ((II_Buf & mskUART_II_ABEOIF) == UART_II_ABEOIF) //Auto Baud interrupt + SN_UART0->ABCTRL |= UART_ABEO_EN; + else if((II_Buf & mskUART_II_ABTOIF) == UART_II_ABTOIF) //Auto Baud time-out interrupt + SN_UART0->ABCTRL |= UART_ABTO_EN; +} + + +/***************************************************************************** +* Function : UART0_Init +* Description : Initialization of UART0 +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void UART0_Init (void) +{ + SN_SYS1->AHBCLKEN |= UART0_CLK_EN; //Enables clock for UART0 + + //===Line Control=== + //setting character Word length(5/6/7/8 bit) + SN_UART0->LC = (UART_CHARACTER_LEN8BIT //8bit character length. + | UART_STOPBIT_1BIT //stop bit of 1 bit + | UART_PARITY_BIT_DISEN //parity bit is disable + | UART_PARITY_SELECTODD //parity bit is odd + | UART_BREAK_DISEN //Break Transmission control disable + | UART_DIVISOR_EN); //Divisor Latch Access enable + + //===Baud Rate Calculation=== + //UART PCLK = 12MHz, Baud rate = 115200 + SN_UART0->FD = (UART_OVER_SAMPLE_16|UART_MULVAL_7|UART_DIVADDVAL_5); + SN_UART0->DLM = 0; + SN_UART0->DLL = 4; + /* + //UART PCLK = 12MHz, Baud rate = 57600 + SN_UART0->FD = (OVER_SAMPLE_16|UART_MULVAL_7|UART_DIVADDVAL_5); + SN_UART0->DLM = 0; + SN_UART0->DLL = 8; + */ + SN_UART0->LC &= ~(UART_DIVISOR_EN); //Disable divisor latch + + //===Auto Baud Rate=== + //UART0_Autobaudrate_Init(); //Auto buad rate initial + + //===FIFO Control=== + SN_UART0->FIFOCTRL =(UART_FIFO_ENABLE //Enable USART FIFOs + | UART_RXFIFO_RESET //RX FIFO Reset + | UART_TXFIFO_RESET //TX FIFO Reset + | UART_RXTRIGGER_LEVEL1); //RX Trigger Level(1 characters) + + //===Oversampling=== + //SN_UART0->FD |= UART_OVER_SAMPLE_8; //OVER8(Oversampling Value), 1:Oversampling by 8. 0:Oversampling by 16 + + //===Half-duplex=== + //SN_UART0->HDEN = 1; //Half-duplex mode enable + + //===Interrupt Enable=== + UART0_InterruptEnable(); + + //===UART Control=== + SN_UART0->CTRL =(UART_EN //Enable USART0 + | UART_RX_EN //Enable RX + | UART_TX_EN); //Enable TX + //===NVIC=== + NVIC_EnableIRQ(UART0_IRQn); //Enable USART0 INT + +} + +/***************************************************************************** +* Function : UART0_SendByte +* Description : MCU sends Byte through UTXD0 +* Input : ucDat - data to be sent +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void UART0_SendByte (uint8_t ucDat) +{ + SN_UART0->TH = ucDat; + while ((SN_UART0->LS & 0x40) == 0); +} + +/***************************************************************************** +* Function : UART0_AutoBaudrateInit +* Description : Initialization of UART0 Auto baud rate. +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void UART0_AutoBaudrateInit(void) +{ + SN_UART0->ABCTRL =(UART_ABTO_EN //Clear Auto Baud Time-out interrupt + | UART_ABEO_EN //Clear Auto Baud interrupt + | UART_ABCCTRL_RESTART //Restart in case of time-out + | UART_ABCCTRL_MODE1 //Auto Baud mode, 0:mode 0, 1:mode 1 + | UART_ABCCTRL_START); //Auto Baud start, 0:stop(not running), 1:start(running) +} + +/***************************************************************************** +* Function : UART0_Enable +* Description : Enable UART0 +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void UART0_Enable(void) +{ + //Enable HCLK for UART0 + SN_SYS1->AHBCLKEN |= UART0_CLK_EN; //Enables clock for UART0 + SN_UART0->CTRL_b.UARTEN = UART_CTRL_EN; //UART enable bit +} + +/***************************************************************************** +* Function : UART0_Disable +* Description : Disable UART0 +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void UART0_Disable(void) +{ + SN_UART0->CTRL_b.UARTEN = UART_CTRL_DIS; //UART disable + //Disable HCLK for UART0 + SN_SYS1->AHBCLKEN &= ~(UART0_CLK_EN); //Disable clock for UART0 +} + +/***************************************************************************** +* Function : UART0_InterruptEnable +* Description : Interrupt Enable +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void UART0_InterruptEnable(void) +{ + SN_UART0->IE =(UART_RDAIE_EN //Enables the Receive Data Available(RDA) interrupt + | UART_THREIE_EN //Enable THRE interrupt + | UART_RLSIE_EN //Enable Receive Line Status(RLS) interrupt + | UART_TEMTIE_EN //Enable TEMT interrupt + | UART_ABEOIE_EN //Enable Auto Baud interrupt + | UART_ABTOIE_EN); //Enable Auto Baud time-out interrupt +} + diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART1.c b/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART1.c new file mode 100644 index 00000000..18a55c5e --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART1.c @@ -0,0 +1,253 @@ +/******************** (C) COPYRIGHT 2017 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2017/07 +* AUTHOR: SA1 +* IC: SN32F240B +* DESCRIPTION: UART1 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2017/07/07 SA1 First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include "UART.h" + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +volatile uint8_t bUART1_RecvNew; +uint32_t GulNum1; +uint8_t bUART1_RecvFIFO[56]; + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + +/***************************************************************************** +* Function : UART1_IRQHandler +* Description : UART1 interrupt service routine +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void UART1_IRQHandler (void) +{ + uint32_t II_Buf, LS_Buf; + volatile uint32_t Null_Buf; + + II_Buf = SN_UART1->II; + while ((II_Buf & mskUART_II_STATUS) == UART_II_STATUS) //check interrupt status, the INT can be determined by UARTn_II[3:1] + { + switch ((II_Buf>>1) & mskUART_INTID_STATUS) + { + case UART_RLS: //Receive Line Status + LS_Buf = SN_UART1->LS; + if((LS_Buf & mskUART_LS_OE) == UART_LS_OE) //Overrun Error + { } + if((LS_Buf & mskUART_LS_RXFE) == UART_LS_RXFE)//RX FIFO Error + { + if((LS_Buf & mskUART_LS_PE) == UART_LS_PE)//Parity Error + Null_Buf = SN_UART1->RB; //Clear interrupt + if((LS_Buf & mskUART_LS_FE) == UART_LS_FE) //Framing Error + Null_Buf = SN_UART1->RB; //Clear interrupt + if((LS_Buf & mskUART_LS_BI) == UART_LS_BI) //Break Interrupt + Null_Buf = SN_UART1->RB; //Clear interrupt + } + break; + + case UART_RDA: //Receive Data Available + LS_Buf = SN_UART1->LS; + bUART1_RecvNew = 1; + if((LS_Buf & mskUART_LS_RDR) == UART_LS_RDR)//Receiver Data Ready + { + bUART1_RecvFIFO[GulNum1] = SN_UART1->RB; + GulNum1++; + } + if(GulNum1 == 56) + GulNum1 = 0; + break; + + case UART_THRE: //THRE interrupt + LS_Buf = SN_UART1->LS; + if((LS_Buf & mskUART_LS_THRE) == UART_LS_THRE)//THRE empty + { //SN_UART1->TH = Null_Buf; //Clear interrupt + } + break; + + case UART_TEMT: //TEMT interrupt + LS_Buf = SN_UART1->LS; + if((LS_Buf & mskUART_LS_TEMT) == UART_LS_TEMT) + { //SN_UART1->TH = Null_Buf; //Clear interrupt + } + break; + + default: + break; + } //end switch ((II_Buf>>1) & mskUART_INTID_STATUS) + + II_Buf = SN_UART1->II; + } //end while ((II_Buf&0x01) == mskUART_II_STATUS) + + if ((II_Buf & mskUART_II_ABEOIF) == UART_II_ABEOIF) //Auto Baud interrupt + SN_UART1->ABCTRL |= UART_ABEO_EN; + else if((II_Buf & mskUART_II_ABTOIF) == UART_II_ABTOIF) //Auto Baud time-out interrupt + SN_UART1->ABCTRL |= UART_ABTO_EN; +} + + +/***************************************************************************** +* Function : UART1_Init +* Description : Initialization of UART1 +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void UART1_Init (void) +{ + SN_SYS1->AHBCLKEN |= UART1_CLK_EN; //Enables clock for UART1 + + //===Line Control=== + //setting character Word length(5/6/7/8 bit) + SN_UART1->LC = (UART_CHARACTER_LEN8BIT //8bit character length. + | UART_STOPBIT_1BIT //stop bit of 1 bit + | UART_PARITY_BIT_DISEN //parity bit is disable + | UART_PARITY_SELECTODD //parity bit is odd + | UART_BREAK_DISEN //Break Transmission control disable + | UART_DIVISOR_EN); //Divisor Latch Access enable + + //===Baud Rate Calculation=== + //UART PCLK = 12MHz, Baud rate = 115200 + SN_UART1->FD = (UART_OVER_SAMPLE_16|UART_MULVAL_7|UART_DIVADDVAL_5); + SN_UART1->DLM = 0; + SN_UART1->DLL = 4; + /* + //UART PCLK = 12MHz, Baud rate = 57600 + SN_UART1->FD = (OVER_SAMPLE_16|UART_MULVAL_7|UART_DIVADDVAL_5); + SN_UART1->DLM = 0; + SN_UART1->DLL = 8; + */ + SN_UART1->LC &= ~(UART_DIVISOR_EN); //Disable divisor latch + + //===Auto Baud Rate=== + //UART1_Autobaudrate_Init(); //Auto buad rate initial + + //===FIFO Control=== + SN_UART1->FIFOCTRL =(UART_FIFO_ENABLE //Enable UART FIFOs + | UART_RXFIFO_RESET //RX FIFO Reset + | UART_TXFIFO_RESET //TX FIFO Reset + | UART_RXTRIGGER_LEVEL1); //RX Trigger Level(1/4/8/14 characters) + + //===Scratch Pad=== + //SN_UART1->SP = 0; //A readable, writable byte + + //===Oversampling=== + //SN_UART1->FD |= UART_OVER_SAMPLE_8; //OVER8(Oversampling Value), 1:Oversampling by 8. 0:Oversampling by 16 + + //===Half-duplex=== + //SN_UART1->HDEN = 1; //Half-duplex mode enable + + //===Interrupt Enable=== + UART1_InterruptEnable(); + + //===UART Control=== + SN_UART1->CTRL =(UART_EN //Enable UART0 + | UART_RX_EN //Enable RX + | UART_TX_EN); //Enable TX + //===NVIC=== + NVIC_EnableIRQ(UART1_IRQn); //Enable UART1 INT + +} + +/***************************************************************************** +* Function : UART1_SendByte +* Description : MCU sends Byte through UTXD1 +* Input : ucDat - data to be sent +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void UART1_SendByte (uint8_t ucDat) +{ + SN_UART1->TH = ucDat; + while ((SN_UART1->LS & 0x40) == 0); +} + +/***************************************************************************** +* Function : UART1_AutoBaudrateInit +* Description : Initialization of UART1 Auto baud rate. +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void UART1_AutoBaudrateInit(void) +{ + SN_UART1->ABCTRL =(UART_ABTO_EN //Clear Auto Baud Time-out interrupt + | UART_ABEO_EN //Clear Auto Baud interrupt + | UART_ABCCTRL_RESTART //Restart in case of time-out + | UART_ABCCTRL_MODE1 //Auto Baud mode, 0:mode 0, 1:mode 1 + | UART_ABCCTRL_START); //Auto Baud start, 0:stop(not running), 1:start(running) +} + +/***************************************************************************** +* Function : UART1_Enable +* Description : Enable UART1 +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void UART1_Enable(void) +{ + //Enable HCLK for UART1 + SN_SYS1->AHBCLKEN |= UART1_CLK_EN; //Enables clock for UART1 + SN_UART1->CTRL_b.UARTEN = UART_CTRL_EN; //UART enable bit +} + +/***************************************************************************** +* Function : UART1_Disable +* Description : Disable UART1 +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void UART1_Disable(void) +{ + SN_UART1->CTRL_b.UARTEN = UART_CTRL_DIS; //UART disable + //Disable HCLK for UART1 + SN_SYS1->AHBCLKEN &= ~(UART1_CLK_EN); //Disable clock for UART1 +} + +/***************************************************************************** +* Function : UART1_InterruptEnable +* Description : Interrupt Enable +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void UART1_InterruptEnable(void) +{ + SN_UART1->IE =(UART_RDAIE_EN //Enables the Receive Data Available(RDA) interrupt + | UART_THREIE_EN //Enable THRE interrupt + | UART_RLSIE_EN //Enable Receive Line Status(RLS) interrupt + | UART_TEMTIE_EN //Enable TEMT interrupt + | UART_ABEOIE_EN //Enable Auto Baud interrupt + | UART_ABTOIE_EN); //Enable Auto Baud time-out interrupt +} + diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART2.c b/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART2.c new file mode 100644 index 00000000..f46091b6 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART2.c @@ -0,0 +1,253 @@ +/******************** (C) COPYRIGHT 2017 SONiX ******************************* +* COMPANY: SONiX +* DATE: 2017/07 +* AUTHOR: SA1 +* IC: SN32F240B +* DESCRIPTION: UART2 related functions. +*____________________________________________________________________________ +* REVISION Date User Description +* 1.0 2017/07/07 SA1 First release +* +*____________________________________________________________________________ +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. +* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL +* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE +* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN +* IN CONNECTION WITH THEIR PRODUCTS. +*****************************************************************************/ + +/*_____ I N C L U D E S ____________________________________________________*/ +#include +#include "UART.h" + +/*_____ D E C L A R A T I O N S ____________________________________________*/ +volatile uint8_t bUART2_RecvNew; +uint32_t GulNum2; +uint8_t bUART2_RecvFIFO[56]; + + +/*_____ D E F I N I T I O N S ______________________________________________*/ + + +/*_____ M A C R O S ________________________________________________________*/ + + +/*_____ F U N C T I O N S __________________________________________________*/ + +/***************************************************************************** +* Function : UART2_IRQHandler +* Description : UART2 interrupt service routine +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +__irq void UART2_IRQHandler (void) +{ + uint32_t II_Buf, LS_Buf; + volatile uint32_t Null_Buf; + + II_Buf = SN_UART2->II; + while ((II_Buf & mskUART_II_STATUS) == UART_II_STATUS) //check interrupt status, the INT can be determined by UARTn_II[3:1] + { + switch ((II_Buf>>1) & mskUART_INTID_STATUS) + { + case UART_RLS: //Receive Line Status + LS_Buf = SN_UART2->LS; + if((LS_Buf & mskUART_LS_OE) == UART_LS_OE) //Overrun Error + { } + if((LS_Buf & mskUART_LS_RXFE) == UART_LS_RXFE)//RX FIFO Error + { + if((LS_Buf & mskUART_LS_PE) == UART_LS_PE)//Parity Error + Null_Buf = SN_UART2->RB; //Clear interrupt + if((LS_Buf & mskUART_LS_FE) == UART_LS_FE) //Framing Error + Null_Buf = SN_UART2->RB; //Clear interrupt + if((LS_Buf & mskUART_LS_BI) == UART_LS_BI) //Break Interrupt + Null_Buf = SN_UART2->RB; //Clear interrupt + } + break; + + case UART_RDA: //Receive Data Available + LS_Buf = SN_UART2->LS; + bUART2_RecvNew = 1; + if((LS_Buf & mskUART_LS_RDR) == UART_LS_RDR)//Receiver Data Ready + { + bUART2_RecvFIFO[GulNum2] = SN_UART2->RB; + GulNum2++; + } + if(GulNum2 == 56) + GulNum2 = 0; + break; + + case UART_THRE: //THRE interrupt + LS_Buf = SN_UART2->LS; + if((LS_Buf & mskUART_LS_THRE) == UART_LS_THRE)//THRE empty + { //SN_UART2->TH = Null_Buf; //Clear interrupt + } + break; + + case UART_TEMT: //TEMT interrupt + LS_Buf = SN_UART2->LS; + if((LS_Buf & mskUART_LS_TEMT) == UART_LS_TEMT) + { //SN_UART2->TH = Null_Buf; //Clear interrupt + } + break; + + default: + break; + } //end switch ((II_Buf>>1) & mskUART_INTID_STATUS) + + II_Buf = SN_UART2->II; + } //end while ((II_Buf&0x01) == mskUART_II_STATUS) + + if ((II_Buf & mskUART_II_ABEOIF) == UART_II_ABEOIF) //Auto Baud interrupt + SN_UART2->ABCTRL |= UART_ABEO_EN; + else if((II_Buf & mskUART_II_ABTOIF) == UART_II_ABTOIF) //Auto Baud time-out interrupt + SN_UART2->ABCTRL |= UART_ABTO_EN; +} + + +/***************************************************************************** +* Function : UART2_Init +* Description : Initialization of UART2 +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void UART2_Init (void) +{ + SN_SYS1->AHBCLKEN |= UART2_CLK_EN; //Enables clock for UART2 + + //===Line Control=== + //setting character Word length(5/6/7/8 bit) + SN_UART2->LC = (UART_CHARACTER_LEN8BIT //8bit character length. + | UART_STOPBIT_1BIT //stop bit of 1 bit + | UART_PARITY_BIT_DISEN //parity bit is disable + | UART_PARITY_SELECTODD //parity bit is odd + | UART_BREAK_DISEN //Break Transmission control disable + | UART_DIVISOR_EN); //Divisor Latch Access enable + + //===Baud Rate Calculation=== + //UART PCLK = 12MHz, Baud rate = 115200 + SN_UART2->FD = (UART_OVER_SAMPLE_16|UART_MULVAL_7|UART_DIVADDVAL_5); + SN_UART2->DLM = 0; + SN_UART2->DLL = 4; + /* + //UART PCLK = 12MHz, Baud rate = 57600 + SN_UART2->FD = (OVER_SAMPLE_16|UART_MULVAL_7|UART_DIVADDVAL_5); + SN_UART2->DLM = 0; + SN_UART2->DLL = 8; + */ + SN_UART2->LC &= ~(UART_DIVISOR_EN); //Disable divisor latch + + //===Auto Baud Rate=== + //UART2_Autobaudrate_Init(); //Auto buad rate initial + + //===FIFO Control=== + SN_UART2->FIFOCTRL =(UART_FIFO_ENABLE //Enable UART FIFOs + | UART_RXFIFO_RESET //RX FIFO Reset + | UART_TXFIFO_RESET //TX FIFO Reset + | UART_RXTRIGGER_LEVEL1); //RX Trigger Level(1/4/8/14 characters) + + //===Scratch Pad=== + //SN_UART2->SP = 0; //A readable, writable byte + + //===Oversampling=== + //SN_UART2->FD |= UART_OVER_SAMPLE_8; //OVER8(Oversampling Value), 1:Oversampling by 8. 0:Oversampling by 16 + + //===Half-duplex=== + //SN_UART2->HDEN = 1; //Half-duplex mode enable + + //===Interrupt Enable=== + UART2_InterruptEnable(); + + //===UART Control=== + SN_UART2->CTRL =(UART_EN //Enable UART0 + | UART_RX_EN //Enable RX + | UART_TX_EN); //Enable TX + //===NVIC=== + NVIC_EnableIRQ(UART2_IRQn); //Enable UART2 INT + +} + +/***************************************************************************** +* Function : UART2_SendByte +* Description : MCU sends Byte through UTXD1 +* Input : ucDat - data to be sent +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void UART2_SendByte (uint8_t ucDat) +{ + SN_UART2->TH = ucDat; + while ((SN_UART2->LS & 0x40) == 0); +} + +/***************************************************************************** +* Function : UART2_AutoBaudrateInit +* Description : Initialization of UART2 Auto baud rate. +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void UART2_AutoBaudrateInit(void) +{ + SN_UART2->ABCTRL =(UART_ABTO_EN //Clear Auto Baud Time-out interrupt + | UART_ABEO_EN //Clear Auto Baud interrupt + | UART_ABCCTRL_RESTART //Restart in case of time-out + | UART_ABCCTRL_MODE1 //Auto Baud mode, 0:mode 0, 1:mode 1 + | UART_ABCCTRL_START); //Auto Baud start, 0:stop(not running), 1:start(running) +} + +/***************************************************************************** +* Function : UART2_Enable +* Description : Enable UART2 +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void UART2_Enable(void) +{ + //Enable HCLK for UART2 + SN_SYS1->AHBCLKEN |= UART2_CLK_EN; //Enables clock for UART2 + SN_UART2->CTRL_b.UARTEN = UART_CTRL_EN; //UART enable bit +} + +/***************************************************************************** +* Function : UART2_Disable +* Description : Disable UART2 +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void UART2_Disable(void) +{ + SN_UART2->CTRL_b.UARTEN = UART_CTRL_DIS; //UART disable + //Disable HCLK for UART2 + SN_SYS1->AHBCLKEN &= ~(UART2_CLK_EN); //Disable clock for UART2 +} + +/***************************************************************************** +* Function : UART2_InterruptEnable +* Description : Interrupt Enable +* Input : None +* Output : None +* Return : None +* Note : None +*****************************************************************************/ +void UART2_InterruptEnable(void) +{ + SN_UART2->IE =(UART_RDAIE_EN //Enables the Receive Data Available(RDA) interrupt + | UART_THREIE_EN //Enable THRE interrupt + | UART_RLSIE_EN //Enable Receive Line Status(RLS) interrupt + | UART_TEMTIE_EN //Enable TEMT interrupt + | UART_ABEOIE_EN //Enable Auto Baud interrupt + | UART_ABTOIE_EN); //Enable Auto Baud time-out interrupt +} + diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/USB/driver.mk b/os/hal/ports/SN32/LLD/SN32F2xx/USB/driver.mk new file mode 100644 index 00000000..a65d21ca --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/USB/driver.mk @@ -0,0 +1,3 @@ +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/USB/hal_usb_lld.c + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/USB diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/USB/hal_usb_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/USB/hal_usb_lld.c new file mode 100644 index 00000000..cc637fe4 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/USB/hal_usb_lld.c @@ -0,0 +1,936 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_usb_lld.c + * @brief PLATFORM USB subsystem low level driver source. + * + * @addtogroup USB + * @{ + */ + +#include +#include "hal.h" + +#if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief USB1 driver identifier. + */ +#if (SN32_USB_USE_USB1 == TRUE) || defined(__DOXYGEN__) +USBDriver USBD1; +#endif /* SN32_USB_USE_USB1 == TRUE */ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static uint8_t nakcnt[USB_MAX_ENDPOINTS + 1] = {0}; + +/** + * @brief EP0 state. + * @note It is an union because IN and OUT endpoints are never used at the + * same time for EP0. + */ +static union { + /** + * @brief IN EP0 state. + */ + USBInEndpointState in; + /** + * @brief OUT EP0 state. + */ + USBOutEndpointState out; +} ep0_state; + +/** + * @brief Buffer for the EP0 setup packets. + */ +static uint8_t ep0setup_buffer[8]; + +/** + * @brief EP0 initialization structure. + */ +static const USBEndpointConfig ep0config = { + .ep_mode = USB_EP_MODE_TYPE_CTRL, + .setup_cb = _usb_ep0setup, + .in_cb = _usb_ep0in, + .out_cb = _usb_ep0out, + .in_maxsize = 0x40, + .out_maxsize = 0x40, + .in_state = &ep0_state.in, + .out_state = &ep0_state.out, + .ep_buffers = 1, + .setup_buf = ep0setup_buffer +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Resets the packet memory allocator. + * + * @param[in] usbp pointer to the @p USBDriver object + */ +static void usb_pm_reset(USBDriver *usbp) { + + /* The first 64 bytes are reserved for the descriptors table. The effective + available RAM for endpoint buffers is just 192/448 bytes.*/ + usbp->pmnext = 64; +} + +/** + * @brief Sets the packet memory allocator. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] size size of the packet buffer to allocate + * @return The packet buffer address. + */ +static uint32_t usb_pm_alloc(USBDriver *usbp, size_t size) { + uint32_t next; + + next = usbp->pmnext; + usbp->pmnext += (size + 1) & ~1; + osalDbgAssert(usbp->pmnext <= SN32_USB_PMA_SIZE, "PMA overflow"); + return next; +} + +static void sn32_usb_read_fifo(usbep_t ep, uint8_t *buf, size_t sz, bool intr) { + size_t ep_offset; + if (ep == 0) { + ep_offset = 0; + } + else { + ep_offset = SN32_USB->EPBUFOS[ep-1]; + } + size_t off; + size_t chunk; + uint32_t data; + + off = 0; + while (off != sz) { + chunk = 4; + if (off + chunk > sz) + chunk = sz - off; + + if(intr) { + SN32_USB->RWADDR = off + ep_offset; + SN32_USB->RWSTATUS = 0x02; + while (SN32_USB->RWSTATUS & 0x02); + data = SN32_USB->RWDATA; + } + else { + SN32_USB->RWADDR2 = off + ep_offset; + SN32_USB->RWSTATUS2 = 0x02; + while (SN32_USB->RWSTATUS2 & 0x02); + data = SN32_USB->RWDATA2; + } + + //dest, src, size + memcpy(buf, &data, chunk); + + off += chunk; + buf += chunk; + } +} + +static void sn32_usb_write_fifo(usbep_t ep, const uint8_t *buf, size_t sz, bool intr) { + size_t ep_offset; + if (ep == 0) { + ep_offset = 0; + } + else { + ep_offset = SN32_USB->EPBUFOS[ep-1]; + } + size_t off; + size_t chunk; + uint32_t data; + + off = 0; + + while (off != sz) { + chunk = 4; + if (off + chunk > sz) + chunk = sz - off; + + //dest, src, size + memcpy(&data, buf, chunk); + + if(intr) { + SN32_USB->RWADDR = off + ep_offset; + SN32_USB->RWDATA = data; + SN32_USB->RWSTATUS = 0x01; + while (SN32_USB->RWSTATUS & 0x01); + } + else { + SN32_USB->RWADDR2 = off + ep_offset; + SN32_USB->RWDATA2 = data; + SN32_USB->RWSTATUS2 = 0x01; + while (SN32_USB->RWSTATUS2 & 0x01); + } + + off += chunk; + buf += chunk; + } +} + +/** + * @brief USB shared ISR. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +static void usb_lld_serve_interrupt(USBDriver *usbp) { + uint32_t iwIntFlag; + + /* Get Interrupt Status and clear immediately. */ + iwIntFlag = SN32_USB->INSTS; + /* Keep only PRESETUP & ERR_SETUP flags. */ + SN32_USB->INSTSC = ~(mskEP0_PRESETUP | mskERR_SETUP); + + if (iwIntFlag == 0) { + //@20160902 add for EMC protection + SN32_USB->CFG |= (mskESD_EN|mskPHY_EN); + return; + } + + ///////////////////////////////////////////////////////////////// + /* Device Status Interrupt (BusReset, Suspend, Resume, Wakeup) */ + ///////////////////////////////////////////////////////////////// + if (iwIntFlag & (mskBUS_RESET | mskBUS_SUSPEND | mskBUS_RESUME | mskBUS_WAKEUP)) { + if (iwIntFlag & mskBUS_RESET) { + /* BusReset */ + SN32_USB->CFG |= (mskESD_EN|mskPHY_EN); + SN32_USB->INSTSC = (mskBUS_RESET); + _usb_reset(usbp); + } + else if (iwIntFlag & mskBUS_SUSPEND) { + /* Suspend */ + SN32_USB->CFG &= ~(mskESD_EN|mskPHY_EN); + _usb_suspend(usbp); + SN32_USB->INSTSC = (mskBUS_SUSPEND); + } + else if(iwIntFlag & mskBUS_RESUME) { + /* Resume */ + SN32_USB->CFG |= (mskESD_EN|mskPHY_EN); + SN32_USB->INSTSC = (mskBUS_RESUME); + } + else if(iwIntFlag & mskBUS_WAKEUP) { + /* Wakeup */ + SN32_USB->CFG |= (mskESD_EN|mskPHY_EN); + SN32_USB->INSTSC = (mskBUS_WAKEUP); + _usb_wakeup(usbp); + } + } + ///////////////////////////////////////////////// + /* Device Status Interrupt (SETUP, IN, OUT) */ + ///////////////////////////////////////////////// + else if (iwIntFlag & mskERR_SETUP) { + SN32_USB->INSTSC = (mskERR_SETUP); + usb_lld_stall_in(usbp, 0); + } + else if (iwIntFlag & (mskEP0_SETUP|mskEP0_IN|mskEP0_OUT|mskEP0_IN_STALL|mskEP0_OUT_STALL)) { + const USBEndpointConfig *epcp = usbp->epc[0]; + + if (iwIntFlag & mskEP0_SETUP) { + /* SETUP */ + /* Clear receiving in the chibios state machine */ + (usbp)->receiving &= ~1; + SN32_USB->INSTSC = (mskEP0_PRESETUP); + /* Call SETUP function (ChibiOS core), which prepares + * for send or receive and releases the buffer + */ + _usb_isr_invoke_setup_cb(usbp, 0); + SN32_USB->INSTSC = (mskEP0_SETUP); + } + else if (iwIntFlag & mskEP0_IN) { + USBInEndpointState *isp = epcp->in_state; + + /* IN */ + /* Special case for SetAddress for EP0*/ + if((((uint16_t)usbp->setup[0]<<8)|usbp->setup[1]) == 0x0500) { + usbp->address = usbp->setup[2]; + usb_lld_set_address(usbp); + _usb_isr_invoke_event_cb(usbp, USB_EVENT_ADDRESS); + usbp->state = USB_SELECTED; + usb_lld_stall_in(usbp, 0); + } + + isp->txcnt += isp->txlast; + size_t txed = isp->txsize - isp->txcnt; + if (txed > 0) { + /* Transfer not completed, there are more packets to send.*/ + if (txed > epcp->in_maxsize) + txed = epcp->in_maxsize; + + /* Writes the packet from the defined buffer.*/ + isp->txbuf += isp->txlast; + isp->txlast = txed; + osalSysLockFromISR(); + sn32_usb_write_fifo(0, isp->txbuf, txed, true); + osalSysUnlockFromISR(); + + EPCTL_SET_STAT_ACK(0, txed); + } + else { + /* Transfer complete, invokes the callback.*/ + //EPCTL_SET_STAT_NAK(0); //useless mcu resets it anyways + _usb_isr_invoke_in_cb(usbp, 0); + } + + SN32_USB->INSTSC = (mskEP0_IN); + } + else if (iwIntFlag & mskEP0_OUT) { + USBOutEndpointState *osp = epcp->out_state; + /* OUT */ + + size_t rxed = SN32_USB->EPCTL[0] & mskEPn_CNT; + if (rxed) { + osalSysLockFromISR(); + sn32_usb_read_fifo(0, osp->rxbuf, rxed, true); + osalSysUnlockFromISR(); + + /* Update transaction data */ + epcp->out_state->rxbuf += rxed; + epcp->out_state->rxcnt += rxed; + epcp->out_state->rxsize -= rxed; + epcp->out_state->rxpkts -= 1; + + /* The transaction is completed if the specified number of packets + has been received or the current packet is a short packet.*/ + if ((rxed < epcp->out_maxsize) || (epcp->out_state->rxpkts == 0)) + { + /* Transfer complete, invokes the callback.*/ + //EPCTL_SET_STAT_NAK(0); //useless mcu resets it anyways + _usb_isr_invoke_out_cb(usbp, 0); + } + else { + /* Transfer not complete, there are more packets to receive.*/ + EPCTL_SET_STAT_ACK(0, 0); + } + } + + SN32_USB->INSTSC = (mskEP0_OUT); + } + else if (iwIntFlag & (mskEP0_IN_STALL)) { + /* EP0_IN_STALL */ + usb_lld_stall_in(usbp, 0); + SN32_USB->INSTSC = (mskEP0_IN_STALL); + } + else if (iwIntFlag & (mskEP0_OUT_STALL)) + { + /* EP0_OUT_STALL */ + usb_lld_stall_out(usbp, 0); + SN32_USB->INSTSC = (mskEP0_OUT_STALL); + } + } + ///////////////////////////////////////////////// + /* Device Status Interrupt (EPnACK) */ + ///////////////////////////////////////////////// + else if (iwIntFlag & (mskEP6_ACK|mskEP5_ACK|mskEP4_ACK|mskEP3_ACK|mskEP2_ACK|mskEP1_ACK)) { + // Determine the interrupting endpoint, direction, and clear the interrupt flag + for(usbep_t ep = 1; ep <= USB_MAX_ENDPOINTS; ep++) { + if (iwIntFlag & mskEPn_ACK(ep)){ + handleACK(usbp, ep); + SN32_USB->INSTSC = (mskEPn_ACK(ep)); + } + } + } + else if (iwIntFlag & (mskEP6_NAK|mskEP5_NAK|mskEP4_NAK|mskEP3_NAK|mskEP2_NAK|mskEP1_NAK)) { + // Determine the interrupting endpoint, direction, and clear the interrupt flag + for(usbep_t ep = 1; ep <= USB_MAX_ENDPOINTS; ep++) { + if (iwIntFlag & mskEPn_NAK(ep)){ + handleNAK(usbp, ep); + SN32_USB->INSTSC = (mskEPn_NAK(ep)); + } + } + } + + ///////////////////////////////////////////////// + /* Device Status Interrupt (SOF) */ + ///////////////////////////////////////////////// + if ((iwIntFlag & mskUSB_SOF) && (SN32_USB->INTEN & mskUSB_SOF_IE)) { + /* SOF */ + _usb_isr_invoke_sof_cb(usbp); + SN32_USB->INSTSC = (mskUSB_SOF); + } +} + +void handleACK(USBDriver* usbp, usbep_t ep) { + uint8_t out = 0; + uint8_t cnt = 0; + + if(ep > 0 && ep <= USB_MAX_ENDPOINTS) { + out = ( SN32_USB->CFG & mskEPn_DIR(ep) ) == mskEPn_DIR(ep); + cnt = SN32_USB->EPCTL[ep] & mskEPn_CNT; + } + else { + return; + } + nakcnt[ep] = 0; + + // Get the endpoint config and state + const USBEndpointConfig *epcp = usbp->epc[ep]; + USBInEndpointState *isp = epcp->in_state; + USBOutEndpointState *osp = epcp->out_state; + + // Process based on endpoint direction + if(out) { + // Read size of received data + size_t rxed = cnt; + if (rxed) { + osalSysLockFromISR(); + sn32_usb_read_fifo(ep, osp->rxbuf, rxed, true); + osalSysUnlockFromISR(); + + /* Update transaction data */ + epcp->out_state->rxbuf += rxed; + epcp->out_state->rxcnt += rxed; + epcp->out_state->rxsize -= rxed; + epcp->out_state->rxpkts -= 1; + + /* The transaction is completed if the specified number of packets + has been received or the current packet is a short packet.*/ + if ((rxed < epcp->out_maxsize) || (epcp->out_state->rxpkts == 0)) + { + /* Transfer complete, invokes the callback.*/ + //EPCTL_SET_STAT_NAK(0); //useless mcu resets it anyways + _usb_isr_invoke_out_cb(usbp, ep); + } + else { + /* Transfer not complete, there are more packets to receive.*/ + EPCTL_SET_STAT_ACK(ep, 0); + } + } + } + else { + // Process transmit queue + isp->txcnt += isp->txlast; + size_t txed = isp->txsize - isp->txcnt; + + if (txed > 0) + { + /* Transfer not completed, there are more packets to send.*/ + if (txed > epcp->in_maxsize) + { + txed = epcp->in_maxsize; + } + + /* Writes the packet from the defined buffer.*/ + isp->txbuf += isp->txlast; + isp->txlast = txed; + osalSysLockFromISR(); + sn32_usb_write_fifo(ep, isp->txbuf, txed, true); + osalSysUnlockFromISR(); + + EPCTL_SET_STAT_ACK(ep, txed); + } + else { + /* Transfer complete, invokes the callback.*/ + //EPCTL_SET_STAT_NAK(ep); //useless mcu resets it anyways + _usb_isr_invoke_in_cb(usbp, ep); + } + } +} + +void handleNAK(USBDriver *usbp, usbep_t ep) { + uint8_t out = 0; + + if(ep > 0 && ep <= USB_MAX_ENDPOINTS) { + out = ( SN32_USB->CFG & mskEPn_DIR(ep) ) == mskEPn_DIR(ep); + } + else { + return; + } + + + if(out) + { + // no ack required here + } + else + { + // This is not a retransmission, retransmission is transparent and happens on phy layer + // NAK happens when host polls IN EP and device has nothing to send + // It has been observed that sometimes USB phy doesn't generate ACK (unknown why) + // (count ACK interrupts didn't match count of usb_lld_start_in calls per EP) + // However while USB transmitting and qmk thread wants to send another packet qmk goes to + // infinite sleep, expecting that successfull USB transmission will wake it up + // If USB transmission never completes (no ACK) then qmk never wakes up and keyboard locks up + // To prevent this every NAK (1ms or 8ms depending on host poll interval) was calling + // callbacks and wake up function to wake up qmk thread, however packet was not delivered to host + // (for unknown reason) and thus we have seen: + // 1) stuck keypresses when usb packets to press key delivered but key release packet lost + // 2) untyped key when usb packet to press key was lost but key release packet delivered + // Because callback was called every NAK some qmk features didnt work such as CONSOLE + // since callback might release buffers and endup in deadlock via disabled interrupts + // callback for keyboard is empty thus its repated calling is harmless + #if defined(SN32_USB_ORIGINAL_NAK_HANDLING) + _usb_isr_invoke_in_cb(usbp, ep); + #else + //To fake missing ACK we can send 0 sized packet + //however (again for unknown reason) packets now being delivered to host as well! + //- value 2 has been selected to allow at least 2 NAK delivery (2ms or 16ms depending on + //host polling interval) between moment qmk called start_in and moment USB phy actually + //started transmission + //- value 10 was selected arbitrary. + //- values 3-10 we are delivering 0 sized packet trying to get at least one ack + if (nakcnt[ep] > 0) { + //qmk called start_in + if (nakcnt[ep] > 10) { + //11-.... + //consider packet undeliverable but ack it to the qmk + nakcnt[ep] = 0; + _usb_isr_invoke_in_cb(usbp, ep); + } + else if (nakcnt[ep] > 2) { + //3-10 + nakcnt[ep]++; + EPCTL_SET_STAT_ACK(ep, 0); + } + else { + //1-2 + //give it sometime to deliver the packet + nakcnt[ep]++; + } + } + #endif + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers and threads. */ +/*===========================================================================*/ +#if (SN32_USB_USE_USB1 == TRUE) || defined(__DOXYGEN__) +/** + * @brief SN32 USB Interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(SN32_USB_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + usb_lld_serve_interrupt(&USBD1); + OSAL_IRQ_EPILOGUE(); +} +#endif /* SN32_USB_USE_USB1 == TRUE */ +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level USB driver initialization. + * + * @notapi + */ +void usb_lld_init(void) { +#if SN32_USB_USE_USB1 == TRUE + /* Driver initialization.*/ + usbObjectInit(&USBD1); +#endif /* SN32_USB_USE_USB1 == TRUE */ +} + +/** + * @brief Configures and activates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_start(USBDriver *usbp) { + if (usbp->state == USB_STOP) { + /* Clock activation.*/ +#if SN32_USB_USE_USB1 + if (&USBD1 == usbp) { + /* USB clock enabled.*/ + sys1EnableUSB(); + /* Powers up the transceiver while holding the USB in reset state.*/ + SN32_USB->SGCTL = (mskBUS_DRVEN|mskBUS_J_STATE); + SN32_USB->CFG = (mskVREG33_EN|mskPHY_EN|mskDPPU_EN|mskSIE_EN|mskESD_EN); + /* Set up hardware configuration.*/ + SN32_USB->PHYPRM = 0x80000000; + SN32_USB->PHYPRM2 = 0x00004004; + /* Enable the USB Bus Interrupts.*/ + SN32_USB->INTEN = mskBUS_IE; + + nvicEnableVector(SN32_USB_NUMBER, SN32_USB_IRQ_PRIORITY); + /* Releases the reset state.*/ + SN32_USB->SGCTL &= ~mskBUS_DRVEN; + } +#endif /* SN32_USB_USE_USB1 == TRUE */ + /* Reset procedure enforced on driver start.*/ + usb_lld_reset(usbp); + } +} + +/** + * @brief Deactivates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_stop(USBDriver *usbp) { + /* If in ready state then disables the USB clock.*/ + if (usbp->state != USB_STOP) { +#if SN32_USB_USE_USB1 == TRUE + /* Disables the peripheral.*/ + if (&USBD1 == usbp) { + nvicDisableVector(SN32_USB_NUMBER); + sys1DisableUSB(); + } +#endif /* SN32_USB_USE_USB1 == TRUE */ + } +} + +/** + * @brief USB low level reset routine. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_reset(USBDriver *usbp) { + /* Post reset initialization.*/ + SN32_USB->INSTSC = (0xFFFFFFFF); + + /* Set the address to zero during enumeration.*/ + usbp->address = 0; + SN32_USB->ADDR = 0; + + /* Resets the packet memory allocator.*/ + usb_pm_reset(usbp); + + /* EP0 initialization.*/ + usbp->epc[0] = &ep0config; + usb_lld_init_endpoint(usbp, 0); + + /* Enable other interrupts.*/ + SN32_USB->INTEN |= (mskUSB_IE|mskEPnACK_EN|mskBUSWK_IE|mskUSB_SOF_IE); + SN32_USB->INTEN |= (mskEP1_NAK_EN|mskEP2_NAK_EN|mskEP3_NAK_EN|mskEP4_NAK_EN); +#if (USB_ENDPOINTS_NUMBER > 4) + SN32_USB->INTEN |= (mskEP5_NAK_EN|mskEP6_NAK_EN); +#endif /* (USB_ENDPOINTS_NUMBER > 4) */ + +} + +/** + * @brief Sets the USB address. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_set_address(USBDriver *usbp) { + + SN32_USB->ADDR = usbp->address & 0x7F; +} + +/** + * @brief Enables an endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { + const USBEndpointConfig *epcp = usbp->epc[ep]; + + /* Make sure direction flags are not set.*/ + if(ep > 0 && ep <= USB_MAX_ENDPOINTS) { + SN32_USB->CFG &= ~mskEPn_DIR(ep); + } + + /* Set the endpoint type. */ + switch (epcp->ep_mode & USB_EP_MODE_TYPE) { + case USB_EP_MODE_TYPE_ISOC: + break; + case USB_EP_MODE_TYPE_BULK: + break; + case USB_EP_MODE_TYPE_INTR: + break; + default: + break; + } + + /* IN endpoint? */ + if (epcp->in_state != NULL) { + if(ep ==0) { + usb_lld_stall_in(usbp, 0); + } + else if(ep <= USB_MAX_ENDPOINTS) { + /* Set endpoint direction flag in USB configuration register.*/ + SN32_USB->CFG &= ~mskEPn_DIR(ep); + /* Set endpoint PMA buffer offset in USB configuration register.*/ + uint32_t buff_addr = usb_pm_alloc(usbp, epcp->in_maxsize); + USB_SET_BUFFER_OFST(ep,buff_addr); + } + } + + /* OUT endpoint? */ + if (epcp->out_state != NULL) { + if(ep ==0) { + usb_lld_stall_out(usbp, 0); + } + else if(ep <= USB_MAX_ENDPOINTS) { + /* Set endpoint direction flag in USB configuration register.*/ + SN32_USB->CFG |= mskEPn_DIR(ep); + /* Set endpoint PMA buffer offset in USB configuration register.*/ + uint32_t buff_addr = usb_pm_alloc(usbp, epcp->out_maxsize); + USB_SET_BUFFER_OFST(ep,buff_addr); + } + } + + /* Enable endpoint. */ + if(ep <= USB_MAX_ENDPOINTS) { + SN32_USB->EPCTL[ep] |= mskEPn_ENDP_EN; + } +} + +/** + * @brief Disables all the active endpoints except the endpoint zero. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_disable_endpoints(USBDriver *usbp) { + + /* Resets the packet memory allocator.*/ + usb_pm_reset(usbp); + + /* Disabling all endpoints.*/ + for(usbep_t ep=1; ep <= USB_MAX_ENDPOINTS; ep++) { + SN32_USB->EPCTL[ep] = 0; + SN32_USB->CFG &= ~mskEPn_DIR(ep); + } +} + +/** + * @brief Returns the status of an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) { + (void)usbp; + if (ep > USB_MAX_ENDPOINTS) + return EP_STATUS_DISABLED; + if ((SN32_USB->EPCTL[ep] & mskEPn_ENDP_EN) != mskEPn_ENDP_EN) + return EP_STATUS_DISABLED; + if ((SN32_USB->EPCTL[ep] & mskEPn_ENDP_STATE) == mskEPn_ENDP_STATE_STALL) + return EP_STATUS_STALLED; + return EP_STATUS_ACTIVE; +} + +/** + * @brief Returns the status of an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) { + (void)usbp; + if (ep > USB_MAX_ENDPOINTS) + return EP_STATUS_DISABLED; + if ((SN32_USB->EPCTL[ep] & mskEPn_ENDP_EN) != mskEPn_ENDP_EN) + return EP_STATUS_DISABLED; + if ((SN32_USB->EPCTL[ep] & mskEPn_ENDP_STATE) == mskEPn_ENDP_STATE_STALL) + return EP_STATUS_STALLED; + return EP_STATUS_ACTIVE; +} + +/** + * @brief Reads a setup packet from the dedicated packet buffer. + * @details This function must be invoked in the context of the @p setup_cb + * callback in order to read the received setup packet. + * @pre In order to use this function the endpoint must have been + * initialized as a control endpoint. + * @post The endpoint is ready to accept another packet. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the packet data + * + * @notapi + */ + +void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { + osalSysLockFromISR(); + sn32_usb_read_fifo(ep, buf, 8, false); + osalSysUnlockFromISR(); +} + +/** + * @brief Starts a receive operation on an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { + + USBOutEndpointState *osp = usbp->epc[ep]->out_state; + + /* Transfer initialization.*/ + if (osp->rxsize == 0) /* Special case for zero sized packets.*/ + osp->rxpkts = 1; + else + osp->rxpkts = (uint16_t)((osp->rxsize + usbp->epc[ep]->out_maxsize - 1) / + usbp->epc[ep]->out_maxsize); + EPCTL_SET_STAT_ACK(ep, 0); +} + +/** + * @brief Starts a transmit operation on an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_start_in(USBDriver *usbp, usbep_t ep) +{ + size_t n; + USBInEndpointState *isp = usbp->epc[ep]->in_state; + + /* Transfer initialization.*/ + n = isp->txsize; + + if((n >= 0) || (ep == 0)) { + + if (n > (size_t)usbp->epc[ep]->in_maxsize) + n = (size_t)usbp->epc[ep]->in_maxsize; + + isp->txlast = n; + osalSysLockFromISR(); + sn32_usb_write_fifo(ep, isp->txbuf, n, false); + osalSysUnlockFromISR(); + nakcnt[ep] = 1; + EPCTL_SET_STAT_ACK(ep, n); + } + else { + _usb_isr_invoke_in_cb(usbp, ep); + } +} + +/** + * @brief Brings an OUT endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) { + (void)usbp; + if (ep == 0 ) { + if (SN32_USB->INSTS & mskEP0_PRESETUP) { + return; + } + if (SN32_USB->INSTS & mskEP0_OUT_STALL) { + SN32_USB->EPCTL[ep] |= mskEP0_OUT_STALL_EN; + return; + } + } + EPCTL_SET_STAT_STALL(ep); +} + +/** + * @brief Brings an IN endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) { + (void)usbp; + if (ep == 0 ) { + if (SN32_USB->INSTS & mskEP0_PRESETUP) { + return; + } + if (SN32_USB->INSTS & mskEP0_IN_STALL) { + SN32_USB->EPCTL[ep] |= mskEP0_IN_STALL_EN; + return; + } + } + EPCTL_SET_STAT_STALL(ep); +} + +/** + * @brief Brings an OUT endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) { + (void)usbp; + /* Makes sure to not put to NAK an endpoint that is already + transferring.*/ + if (!(SN32_USB->EPCTL[ep] & mskEPn_ENDP_STATE_NAK)) + EPCTL_SET_STAT_NAK(ep); +} + +/** + * @brief Brings an IN endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) { + (void)usbp; + /* Makes sure to not put to NAK an endpoint that is already + transferring.*/ + if (!(SN32_USB->EPCTL[ep] & mskEPn_ENDP_STATE_NAK)) + EPCTL_SET_STAT_NAK(ep); +} + +#endif /* HAL_USE_USB == TRUE */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/USB/hal_usb_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/USB/hal_usb_lld.h new file mode 100644 index 00000000..44a19f2c --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/USB/hal_usb_lld.h @@ -0,0 +1,436 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_usb_lld.h + * @brief PLATFORM USB subsystem low level driver header. + * + * @addtogroup USB + * @{ + */ + +#ifndef HAL_USB_LLD_H +#define HAL_USB_LLD_H + +#if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__) + +#include "sn32_usb.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Maximum endpoint address. + */ +#define USB_MAX_ENDPOINTS USB_ENDPOINTS_NUMBER + +/** + * @brief Status stage handling method. + */ +#define USB_EP0_STATUS_STAGE USB_EP0_STATUS_STAGE_SW + +/** + * @brief This device requires the address change after the status packet. + */ +#define USB_SET_ADDRESS_MODE USB_LATE_SET_ADDRESS + +/** + * @brief Method for set address acknowledge. + */ +#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_SW + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ +/** + * @brief USB driver enable switch. + * @details If set to @p TRUE the support for USB1 is included. + * @note The default is @p FALSE. + */ +#if !defined(SN32_USB_USE_USB1) || defined(__DOXYGEN__) +#define SN32_USB_USE_USB1 TRUE +#endif + +/** + * @brief USB interrupt priority level setting. + */ +#if !defined(SN32_USB_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SN32_USB_IRQ_PRIORITY 3 +#endif + +/** + * @brief Host wake-up procedure duration. + */ +#if !defined(SN32_USB_HOST_WAKEUP_DURATION) || defined(__DOXYGEN__) +#define SN32_USB_HOST_WAKEUP_DURATION 2 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an IN endpoint state structure. + */ +typedef struct { + /** + * @brief Requested transmit transfer size. + */ + size_t txsize; + /** + * @brief Transmitted bytes so far. + */ + size_t txcnt; + /** + * @brief Pointer to the transmission linear buffer. + */ + const uint8_t *txbuf; +#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + thread_reference_t thread; +#endif + /* End of the mandatory fields.*/ + /** + * @brief Size of the last transmitted packet. + */ + size_t txlast; +} USBInEndpointState; + +/** + * @brief Type of an OUT endpoint state structure. + */ +typedef struct { + /** + * @brief Requested receive transfer size. + */ + size_t rxsize; + /** + * @brief Received bytes so far. + */ + size_t rxcnt; + /** + * @brief Pointer to the receive linear buffer. + */ + uint8_t *rxbuf; +#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + thread_reference_t thread; +#endif + /* End of the mandatory fields.*/ + /** + * @brief Number of packets to receive. + */ + uint16_t rxpkts; +} USBOutEndpointState; + +/** + * @brief Type of an USB endpoint configuration structure. + * @note Platform specific restrictions may apply to endpoints. + */ +typedef struct { + /** + * @brief Type and mode of the endpoint. + */ + uint32_t ep_mode; + /** + * @brief Setup packet notification callback. + * @details This callback is invoked when a setup packet has been + * received. + * @post The application must immediately call @p usbReadPacket() in + * order to access the received packet. + * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL + * endpoints, it should be set to @p NULL for other endpoint + * types. + */ + usbepcallback_t setup_cb; + /** + * @brief IN endpoint notification callback. + * @details This field must be set to @p NULL if the IN endpoint is not + * used. + */ + usbepcallback_t in_cb; + /** + * @brief OUT endpoint notification callback. + * @details This field must be set to @p NULL if the OUT endpoint is not + * used. + */ + usbepcallback_t out_cb; + /** + * @brief IN endpoint maximum packet size. + * @details This field must be set to zero if the IN endpoint is not + * used. + */ + uint16_t in_maxsize; + /** + * @brief OUT endpoint maximum packet size. + * @details This field must be set to zero if the OUT endpoint is not + * used. + */ + uint16_t out_maxsize; + /** + * @brief @p USBEndpointState associated to the IN endpoint. + * @details This structure maintains the state of the IN endpoint. + */ + USBInEndpointState *in_state; + /** + * @brief @p USBEndpointState associated to the OUT endpoint. + * @details This structure maintains the state of the OUT endpoint. + */ + USBOutEndpointState *out_state; + /* End of the mandatory fields.*/ + /** + * @brief Reserved field, not currently used. + * @note Initialize this field to 1 in order to be forward compatible. + */ + uint16_t ep_buffers; + /** + * @brief Pointer to a buffer for setup packets. + * @details Setup packets require a dedicated 8-bytes buffer, set this + * field to @p NULL for non-control endpoints. + */ + uint8_t *setup_buf; +} USBEndpointConfig; + +/** + * @brief Type of an USB driver configuration structure. + */ +typedef struct { + /** + * @brief USB events callback. + * @details This callback is invoked when an USB driver event is registered. + */ + usbeventcb_t event_cb; + /** + * @brief Device GET_DESCRIPTOR request callback. + * @note This callback is mandatory and cannot be set to @p NULL. + */ + usbgetdescriptor_t get_descriptor_cb; + /** + * @brief Requests hook callback. + * @details This hook allows to be notified of standard requests or to + * handle non standard requests. + */ + usbreqhandler_t requests_hook_cb; + /** + * @brief Start Of Frame callback. + */ + usbcallback_t sof_cb; + /* End of the mandatory fields.*/ +} USBConfig; + +/** + * @brief Structure representing an USB driver. + */ +struct USBDriver { + /** + * @brief Driver state. + */ + usbstate_t state; + /** + * @brief Current configuration data. + */ + const USBConfig *config; + /** + * @brief Bit map of the transmitting IN endpoints. + */ + uint16_t transmitting; + /** + * @brief Bit map of the receiving OUT endpoints. + */ + uint16_t receiving; + /** + * @brief Active endpoints configurations. + */ + const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1]; + /** + * @brief Fields available to user, it can be used to associate an + * application-defined handler to an IN endpoint. + * @note The base index is one, the endpoint zero does not have a + * reserved element in this array. + */ + void *in_params[USB_MAX_ENDPOINTS]; + /** + * @brief Fields available to user, it can be used to associate an + * application-defined handler to an OUT endpoint. + * @note The base index is one, the endpoint zero does not have a + * reserved element in this array. + */ + void *out_params[USB_MAX_ENDPOINTS]; + /** + * @brief Endpoint 0 state. + */ + usbep0state_t ep0state; + /** + * @brief Next position in the buffer to be transferred through endpoint 0. + */ + uint8_t *ep0next; + /** + * @brief Number of bytes yet to be transferred through endpoint 0. + */ + size_t ep0n; + /** + * @brief Endpoint 0 end transaction callback. + */ + usbcallback_t ep0endcb; + /** + * @brief Setup packet buffer. + */ + uint8_t setup[8]; + /** + * @brief Current USB device status. + */ + uint16_t status; + /** + * @brief Assigned USB address. + */ + uint8_t address; + /** + * @brief Current USB device configuration. + */ + uint8_t configuration; + /** + * @brief State of the driver when a suspend happened. + */ + usbstate_t saved_state; +#if defined(USB_DRIVER_EXT_FIELDS) + USB_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the next address in the packet memory. + */ + uint32_t pmnext; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the current frame number. + * + * @param[in] usbp pointer to the @p USBDriver object + * @return The current frame number. + * + * @notapi + */ +#define usb_lld_get_frame_number(usbp) (SN32_USB->FRMNO & mskFRAME_NO) + +/** + * @brief Returns the exact size of a receive transaction. + * @details The received size can be different from the size specified in + * @p usbStartReceiveI() because the last packet could have a size + * different from the expected one. + * @pre The OUT endpoint must have been configured in transaction mode + * in order to use this function. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return Received data size. + * + * @notapi + */ +#define usb_lld_get_transaction_size(usbp, ep) \ + ((usbp)->epc[ep]->out_state->rxcnt) + +/** + * @brief Connects the USB device. + * + * @api + */ +#define usb_lld_connect_bus(usbp) \ + do { \ + SN32_USB->CFG |= mskDPPU_EN; \ + } while (false) + +/** + * @brief Disconnect the USB device. + * + * @api + */ +#define usb_lld_disconnect_bus(usbp) \ + do { \ + SN32_USB->CFG &= ~mskDPPU_EN; \ + } while (false) + + +/** + * @brief Start of host wake-up procedure. + * + * @notapi + */ +#define usb_lld_wakeup_host(usbp) \ + do { \ + SN32_USB->SGCTL = (mskBUS_DRVEN|mskBUS_K_STATE); \ + osalThreadSleepMilliseconds(SN32_USB_HOST_WAKEUP_DURATION); \ + SN32_USB->SGCTL &= ~mskBUS_DRVEN; \ + } while (false) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if (SN32_USB_USE_USB1 == TRUE) && !defined(__DOXYGEN__) +extern USBDriver USBD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void usb_lld_init(void); + void usb_lld_start(USBDriver *usbp); + void usb_lld_stop(USBDriver *usbp); + void usb_lld_reset(USBDriver *usbp); + void usb_lld_set_address(USBDriver *usbp); + void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep); + void usb_lld_disable_endpoints(USBDriver *usbp); + usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep); + usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep); + void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf); + void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep); + void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep); + void usb_lld_start_out(USBDriver *usbp, usbep_t ep); + void usb_lld_start_in(USBDriver *usbp, usbep_t ep); + void usb_lld_stall_out(USBDriver *usbp, usbep_t ep); + void usb_lld_stall_in(USBDriver *usbp, usbep_t ep); + void usb_lld_clear_out(USBDriver *usbp, usbep_t ep); + void usb_lld_clear_in(USBDriver *usbp, usbep_t ep); + void handleACK(USBDriver* usbp, usbep_t ep); + void handleNAK(USBDriver* usbp, usbep_t ep); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_USB == TRUE */ + +#endif /* HAL_USB_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/USB/sn32_usb.h b/os/hal/ports/SN32/LLD/SN32F2xx/USB/sn32_usb.h new file mode 100644 index 00000000..c5974b06 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/USB/sn32_usb.h @@ -0,0 +1,114 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file USB/sn32_usb.h + * @brief SN32 USB registers layout header. + * @note This file requires definitions from the SN32 header files + * + * @addtogroup USB + * @{ + */ + +#ifndef SN32_USB_H +#define SN32_USB_H + +#include "usbhw.h" + +/** + * @brief Number of the available endpoints. + * @details This value does not include the endpoint 0 which is always present. + */ +#define HAL_MAX_ENDPOINTS 6 +#if (defined(SN32F240B) || defined(SN32F260)) +#define USB_ENDPOINTS_NUMBER 4 +#define SN32_USB_PMA_SIZE 256 +#elif (defined(SN32F280) || defined(SN32F290)) +#define USB_ENDPOINTS_NUMBER HAL_MAX_ENDPOINTS +#define SN32_USB_PMA_SIZE 512 +#else +#error "USB driver not supported in the selected device" +#endif + +/** + * @brief USB registers block. + */ + typedef struct { + volatile uint32_t INTEN; /*!< (@ 0x00000000) Offset:0x00 USB Interrupt Enable Register */ + volatile uint32_t INSTS; /*!< (@ 0x00000004) Offset:0x04 USB Interrupt Event Status Register */ + volatile uint32_t INSTSC; /*!< (@ 0x00000008) Offset:0x08 USB Interrupt Event Status Clear Register */ + volatile uint32_t ADDR; /*!< (@ 0x0000000C) Offset:0x0C USB Device Address Register */ + volatile uint32_t CFG; /*!< (@ 0x00000010) Offset:0x10 USB Configuration Register */ + volatile uint32_t SGCTL; /*!< (@ 0x00000014) Offset:0x14 USB Signal Control Register */ + volatile uint32_t EPCTL[HAL_MAX_ENDPOINTS +1]; /*!< (@ 0x00000018) Offset:0x18 USB Endpoint 0-6 Control Registers */ + volatile uint32_t RESERVED[2]; + volatile uint32_t EPTOGGLE; /*!< (@ 0x0000003C) Offset:0x3C USB Endpoint Data Toggle Register */ + volatile uint32_t RESERVED1[2]; + volatile uint32_t EPBUFOS[HAL_MAX_ENDPOINTS]; /*!< (@ 0x00000048) Offset:0x48 USB Endpoint 1-6 Buffer Offset Registers */ + volatile uint32_t FRMNO; /*!< (@ 0x00000060) Offset:0x60 USB Frame Number Register */ + volatile uint32_t PHYPRM; /*!< (@ 0x00000064) Offset:0x64 USB PHY Parameter Register */ + volatile uint32_t RESERVED3; + volatile uint32_t PHYPRM2; /*!< (@ 0x0000006C) Offset:0x6C USB PHY Parameter 2 Register */ + volatile uint32_t PS2CTL; /*!< (@ 0x00000070) Offset:0x70 PS/2 Control Register */ + volatile uint32_t RESERVED4; + volatile uint32_t RWADDR; /*!< (@ 0x00000078) Offset:0x78 USB Read/Write Address Register */ + volatile uint32_t RWDATA; /*!< (@ 0x0000007C) Offset:0x7C USB Read/Write Data Register */ + volatile uint32_t RWSTATUS; /*!< (@ 0x00000080) Offset:0x80 USB Read/Write Status Register */ + volatile uint32_t RWADDR2; /*!< (@ 0x00000084) Offset:0x84 USB Read/Write Address Register 2 */ + volatile uint32_t RWDATA2; /*!< (@ 0x00000088) Offset:0x88 USB Read/Write Data Register 2 */ + volatile uint32_t RWSTATUS2; /*!< (@ 0x0000008C) Offset:0x8C USB Read/Write Status Register 2 */ +} sn32_usb_t; /*!< Size = 144 (0x90) */ + +/** @} */ + +/** + * @brief USB registers block numeric address. + */ +#define SN32_USB_BASE SN_USB_BASE + +/** + * @brief USB RAM numeric address. + */ +#define SN32_USBRAM_BASE (SN_USB_BASE + 0x100) + +/** + * @brief Pointer to the USB registers block. + */ +#define SN32_USB ((sn32_usb_t *)SN32_USB_BASE) + +/** + * @brief Pointer to the USB RAM. + */ +#define SN32_USBRAM ((sn32_usb_pma_t *)SN32_USBRAM_BASE) +#define mskEPn_NAK(ep) (0x1<<(ep -1)) +#define mskEPn_ACK(ep) (0x1<<(8+(ep-1))) +#define mskEPn_DIR(ep) (0x1<<(ep-1)) +#define mskEPn_DATA_TOGGLE(ep) (0x1<<(ep-1)) + +#define EPCTL_SET_STAT_ACK(ep, bBytecnt) \ + SN32_USB->EPCTL[ep] = (mskEPn_ENDP_EN|mskEPn_ENDP_STATE_ACK|bBytecnt) +#define EPCTL_SET_STAT_NAK(ep) \ + SN32_USB->EPCTL[ep] = (mskEPn_ENDP_EN) +#define EPCTL_SET_STAT_STALL(ep) \ + SN32_USB->EPCTL[ep] = (mskEPn_ENDP_EN|mskEPn_ENDP_STATE_STALL) +#define EPCTL_TOGGLE(ep) \ + SN32_USB->EPTOGGLE = mskEPn_DATA_TOGGLE(ep) +#define USB_SET_BUFFER_OFST(ep, addr) \ + SN32_USB->EPBUFOS[ep-1] = addr + +#endif /* SN32_USB_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/USB/usbhw.h b/os/hal/ports/SN32/LLD/SN32F2xx/USB/usbhw.h new file mode 100644 index 00000000..36a2f2e9 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/USB/usbhw.h @@ -0,0 +1,126 @@ +/**************************************************************************** + **************************************************************************** +****************************************************************************/ +#ifndef __USBHW_H__ +#define __USBHW_H__ + +/* USB Interrupt Enable Bit Definitions */ +#define mskEP1_NAK_EN (0x1<<0) +#define mskEP2_NAK_EN (0x1<<1) +#define mskEP3_NAK_EN (0x1<<2) +#define mskEP4_NAK_EN (0x1<<3) +#define mskEP5_NAK_EN (0x1<<4) +#define mskEP6_NAK_EN (0x1<<5) +#define mskEPnACK_EN (0x1<<6) + +#define mskBUSWK_IE (0x1<<28) +#define mskUSB_IE (0x1<<29) +#define mskUSB_SOF_IE (0x1<<30) +#define mskBUS_IE (0x1U<<31) + +/* USB Interrupt Event Status Bit Definitions */ +#define mskEP1_NAK (0x1<<0) +#define mskEP2_NAK (0x1<<1) +#define mskEP3_NAK (0x1<<2) +#define mskEP4_NAK (0x1<<3) +#define mskEP5_NAK (0x1<<4) +#define mskEP6_NAK (0x1<<5) + +#define mskEP1_ACK (0x1<<8) +#define mskEP2_ACK (0x1<<9) +#define mskEP3_ACK (0x1<<10) +#define mskEP4_ACK (0x1<<11) +#define mskEP5_ACK (0x1<<12) +#define mskEP6_ACK (0x1<<13) + + +#define mskERR_TIMEOUT (0x1<<17) +#define mskERR_SETUP (0x1<<18) +#define mskEP0_OUT_STALL (0x1<<19) +#define mskEP0_IN_STALL (0x1<<20) +#define mskEP0_OUT (0x1<<21) +#define mskEP0_IN (0x1<<22) +#define mskEP0_SETUP (0x1<<23) +#define mskEP0_PRESETUP (0x1<<24) +#define mskBUS_WAKEUP (0x1<<25) +#define mskUSB_SOF (0x1<<26) +#define mskBUS_RESUME (0x1<<29) +#define mskBUS_SUSPEND (0x1<<30) +#define mskBUS_RESET (0x1U<<31) + +/* USB Device Address Bit Definitions */ +#define mskUADDR (0x7F<<0) + +/* USB Configuration Bit Definitions */ +#define mskEP1_DIR (0x1<<0) +#define mskEP2_DIR (0x1<<1) +#define mskEP3_DIR (0x1<<2) +#define mskEP4_DIR (0x1<<3) +#define mskEP5_DIR (0x1<<4) +#define mskEP6_DIR (0x1<<5) + +#define mskDIS_PDEN (0x1<<26) +#define mskESD_EN (0x1<<27) +#define mskSIE_EN (0x1<<28) +#define mskDPPU_EN (0x1<<29) +#define mskPHY_EN (0x1<<30) +#define mskVREG33_EN (0x1U<<31) + +/* USB Signal Control Bit Definitions */ +#define mskBUS_DRVEN (0x1<<2) +#define mskBUS_DPDN_STATE (0x3<<0) +#define mskBUS_J_STATE (0x2<<0) // D+ = 1, D- = 0 +#define mskBUS_K_STATE (0x1<<0) // D+ = 0, D- = 1 +#define mskBUS_SE0_STATE (0x0<<0) // D+ = 0, D- = 0 +#define mskBUS_SE1_STATE (0x3<<0) // D+ = 1, D- = 1 +#define mskBUS_IDLE_STATE mskBUS_J_STATE + +/* USB Configuration Bit Definitions */ +#define mskEPn_CNT (0x1FF<<0) +#define mskEP0_OUT_STALL_EN (0x1<<27) +#define mskEP0_IN_STALL_EN (0x1<<28) +#define mskEPn_ENDP_STATE (0x3<<29) +#define mskEPn_ENDP_STATE_ACK (0x1<<29) +#define mskEPn_ENDP_STATE_NAK (0x0<<29) +#define mskEPn_ENDP_STATE_STALL (0x3<<29) +#define mskEPn_ENDP_EN (0x1U<<31) + +/* USB Endpoint Data Toggle Bit Definitions */ +#define mskEP1_CLEAR_DATA0 (0x1<<0) +#define mskEP2_CLEAR_DATA0 (0x1<<1) +#define mskEP3_CLEAR_DATA0 (0x1<<2) +#define mskEP4_CLEAR_DATA0 (0x1<<3) + +/* USB Endpoint n Buffer Offset Bit Definitions */ +#define mskEPn_OFFSET (0x1FF<<0) + +/* USB Frame Number Bit Definitions */ +#define mskFRAME_NO (0x7FF<<0) + +/* Rx & Tx Packet Length Definitions */ +#define PKT_LNGTH_MASK 0x000003FF + +/* nUsb_Status Register Definitions */ +#define mskBUSRESET (0x1<<0) +#define mskBUSSUSPEND (0x1<<1) +#define mskBUSRESUME (0x1<<2) +#define mskREMOTEWAKEUP (0x1<<3) +#define mskSETCONFIGURATION0CMD (0x1<<4) +#define mskSETADDRESS (0x1<<5) +#define mskSETADDRESSCMD (0x1<<6) +#define mskREMOTE_WAKEUP (0x1<<7) +#define mskDEV_FEATURE_CMD (0x1<<8) +#define mskSET_REPORT_FLAG (0x1<<9) +#define mskPROTOCOL_GET_REPORT (0x1<<10) +#define mskPROTOCOL_SET_IDLE (0x1<<11) +#define mskPROTOCOL_ARRIVAL (0x1<<12) +#define mskSET_REPORT_DONE (0x1<<13) +#define mskNOT_8BYTE_ENDDING (0x1<<14) +#define mskSETUP_OUT (0x1<<15) +#define mskSETUP_IN (0x1<<16) +#define mskINITREPEAT (0x1<<17) +#define mskREMOTE_WAKEUP_ACT (0x1<<18) + +/***************************************/ + +#endif /* __USBHW_H__ */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/WDT/driver.mk b/os/hal/ports/SN32/LLD/SN32F2xx/WDT/driver.mk new file mode 100644 index 00000000..704566f4 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/WDT/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/WDT/hal_wdg_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/WDT/hal_wdg_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/WDT diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/WDT/hal_wdg_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/WDT/hal_wdg_lld.c new file mode 100644 index 00000000..13156d7b --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/WDT/hal_wdg_lld.c @@ -0,0 +1,122 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file WDT/hal_wdg_lld.c + * @brief WDG Driver subsystem low level driver source. + * + * @addtogroup WDG + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if SN32_WDG_USE_WDT || defined(__DOXYGEN__) +WDGDriver WDGD1; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level WDG driver initialization. + * + * @notapi + */ +void wdg_lld_init(void) { + +#if SN32_WDG_USE_WDT + WDGD1.state = WDG_STOP; + WDGD1.wdg = SN_WDT; +#endif +} + +/** + * @brief Configures and activates the WDG peripheral. + * + * @param[in] wdgp pointer to the @p WDGDriver object + * + * @notapi + */ +void wdg_lld_start(WDGDriver *wdgp) { + uint32_t wRegBuf; + /* Enable WDT and unlock for write.*/ + sys1EnableWDT(); + wRegBuf = mskWDT_WDTIE_DISABLE; //WDT as reset mode + wRegBuf = wRegBuf & (~mskWDT_WDTINT); //Clear WDT interrupt flag + wRegBuf = wRegBuf | mskWDT_WDKEY; + wdgp->wdg->CFG = wRegBuf; + + /* Write configuration.*/ + sys1SelectWDTPRE(wdgp->config->pr); + wdgp->wdg->TC = (wdgp->config->tc | mskWDT_WDKEY); + wdg_lld_reset(&WDGD1); + + /* Start .*/ + wdgp->wdg->CFG = (mskWDT_WDKEY | mskWDT_WDTEN_ENABLE); +} + +/** + * @brief Deactivates the WDG peripheral. + * + * @param[in] wdgp pointer to the @p WDGDriver object + * + * @notapi + */ +void wdg_lld_stop(WDGDriver *wdgp) { + if (wdgp->state == WDG_READY) { + wdgp->wdg->CFG = (mskWDT_WDKEY | (wdgp->wdg->CFG & ~mskWDT_WDTEN_ENABLE)); + sys1DisableWDT(); + } +} + +/** + * @brief Reloads WDG's counter. + * + * @param[in] wdgp pointer to the @p WDGDriver object + * + * @notapi + */ +void wdg_lld_reset(WDGDriver * wdgp) { + wdgp->wdg->FEED = (mskWDT_WDKEY | mskWDT_FV); +} + +#endif /* HAL_USE_WDG == TRUE */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/WDT/hal_wdg_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/WDT/hal_wdg_lld.h new file mode 100644 index 00000000..203c15a6 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/WDT/hal_wdg_lld.h @@ -0,0 +1,152 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file WDT/hal_wdg_lld.h + * @brief WDG Driver subsystem low level driver header. + * + * @addtogroup WDG + * @{ + */ + +#ifndef HAL_WDG_LLD_H +#define HAL_WDG_LLD_H + +#if (HAL_USE_WDG == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +//Watchdog register key +#define mskWDT_WDKEY (0x5AFA<<16) + +//Watchdog interrupt flag +#define mskWDT_WDTINT (1<<2) + +//Watchdog interrupt enable +#define WDT_WDTIE_DISABLE 0 +#define WDT_WDTIE_ENABLE 1 +#define mskWDT_WDTIE_DISABLE (WDT_WDTIE_DISABLE<<1) +#define mskWDT_WDTIE_ENABLE (WDT_WDTIE_ENABLE<<1) + +//Watchdog enable +#define mskWDT_WDTEN_DISABLE 0 +#define mskWDT_WDTEN_ENABLE 1 + +//Watchdog Feed value +#define mskWDT_FV 0x55AA +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief WDT driver enable switch. + * @details If set to @p TRUE the support for WDT is included. + * @note The default is @p FALSE. + */ +#if !defined(SN32_WDG_USE_WDT) || defined(__DOXYGEN__) +#define SN32_WDG_USE_WDT FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !SN32_WDG_USE_WDT +#error "WDG driver activated but no WDT peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an WDG driver. + */ +typedef struct WDGDriver WDGDriver; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Configuration of the WDT preloader. + * @details See the SN32 reference manual for details. + */ + uint32_t pr; + /** + * @brief Configuration of the WDT_TC register. + * @details See the SN32 reference manual for details. + */ + uint32_t tc; +} WDGConfig; + +/** + * @brief Structure representing an WDG driver. + */ +struct WDGDriver { + /** + * @brief Driver state. + */ + wdgstate_t state; + /** + * @brief Current configuration data. + */ + const WDGConfig *config; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the WDT registers block. + */ + SN_WDT_Type *wdg; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SN32_WDG_USE_WDT && !defined(__DOXYGEN__) +extern WDGDriver WDGD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void wdg_lld_init(void); + void wdg_lld_start(WDGDriver *wdgp); + void wdg_lld_stop(WDGDriver *wdgp); + void wdg_lld_reset(WDGDriver *wdgp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_WDG == TRUE */ + +#endif /* HAL_WDG_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/SN32F240/hal_lld.c b/os/hal/ports/SN32/SN32F240/hal_lld.c new file mode 100644 index 00000000..43802345 --- /dev/null +++ b/os/hal/ports/SN32/SN32F240/hal_lld.c @@ -0,0 +1,73 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_lld.c + * @brief PLATFORM HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "hal.h" +#include + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief SN32F24xx clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +void sn32_clock_init(void) { + SystemCoreClockUpdate(); +} + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + SystemInit(); + sn32_clock_init(); +} + +/** @} */ \ No newline at end of file diff --git a/os/hal/ports/SN32/SN32F240/hal_lld.h b/os/hal/ports/SN32/SN32F240/hal_lld.h new file mode 100644 index 00000000..5ac220e0 --- /dev/null +++ b/os/hal/ports/SN32/SN32F240/hal_lld.h @@ -0,0 +1,89 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_lld.h + * @brief PLATFORM HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#include "sn32_registry.h" + +/** + * @name Platform identification macros + * @{ + */ +#define PLATFORM_NAME "SN32F24x" +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ +#define SN32_HCLK SystemCoreClock +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(PLATFORM_MCUCONF) +#error "Using a wrong mcuconf.h file, PLATFORM_MCUCONF not defined" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* Various helpers.*/ +#include "nvic.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void sn32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/SN32/SN32F240/platform.mk b/os/hal/ports/SN32/SN32F240/platform.mk new file mode 100644 index 00000000..e604cb35 --- /dev/null +++ b/os/hal/ports/SN32/SN32F240/platform.mk @@ -0,0 +1,28 @@ +# Required platform files. +PLATFORMSRC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/SN32F240/hal_lld.c + +# Required include directories. +PLATFORMINC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ + ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24x \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/SN32F240 + +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(CONFDIR),) + CONFDIR = . +endif + +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define")) + +endif + +# Drivers compatible with the platform. +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24x/GPIO/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24x/USB/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24x/CT/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC_CONTRIB) +ALLINC += $(PLATFORMINC_CONTRIB) \ No newline at end of file diff --git a/os/hal/ports/SN32/SN32F240/sn32_registry.h b/os/hal/ports/SN32/SN32F240/sn32_registry.h new file mode 100644 index 00000000..709d8bd8 --- /dev/null +++ b/os/hal/ports/SN32/SN32F240/sn32_registry.h @@ -0,0 +1,153 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SN32F240/sn32_registry.h + * @brief SN32F24x capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef SN32_REGISTRY_H +#define SN32_REGISTRY_H + +/* Common identifier of all SN32F2xx devices.*/ +#if !defined(SN32F2xx) || defined(__DOXYGEN__) +#define SN32F2xx +#endif + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name SN32F24x capabilities + * @{ + */ + +/* Common identifier of all SN32F24x devices.*/ +#if !defined(SN32F240) || defined(__DOXYGEN__) +#define SN32F240 +#endif + +/* + * ST unit + */ +#define SN32_ST_HANDLER Vector3C +#define SN32_ST_NUMBER SysTick_IRQn + +/* + * NDT unit. + */ +#define SN32_NDT_HANDLER Vector40 +#define SN32_NDT_NUMBER NDT_IRQn + +/* + * USB unit. + */ +#define SN32_USB_HANDLER Vector44 +#define SN32_USB_NUMBER USB_IRQn + +#define USBD_INTSTS_EPEVT_Pos USBD_INTSTS_EPEVT0_Pos +#define USBD_INTSTS_EPEVT_Msk (0xFFul << USBD_INTSTS_EPEVT_Pos) + +/* + * SPI unit. + */ +#define SN32_SPI0_HANDLER Vector58 +#define SN32_SPI0_NUMBER SPI0_IRQn + +/* + * I2C unit. + */ +#define SN32_I2C0_GLOBAL_HANDLER Vector68 +#define SN32_I2C0_GLOBAL_NUMBER I2C0_IRQn + +/* + * USART units. + */ +#define SN32_USART0_HANDLER Vector70 +#define SN32_USART1_HANDLER Vector74 +#define SN32_USART2_HANDLER Vector78 + +#define SN32_USART0_NUMBER UART0_IRQn +#define SN32_USART1_NUMBER UART1_IRQn +#define SN32_USART2_NUMBER UART2_IRQn + +/* + * CT16 units. + */ +#define SN32_CT16B0_HANDLER Vector7C +#define SN32_CT16B1_HANDLER Vector80 +#define SN32_CT16B2_HANDLER Vector84 + +#define SN32_CT16B0_NUMBER CT16B0_IRQn +#define SN32_CT16B1_NUMBER CT16B1_IRQn +#define SN32_CT16B2_NUMBER CT16B2_IRQn + +/* + * CT32 units. + */ +#define SN32_CT32B0_HANDLER Vector8C +#define SN32_CT32B1_HANDLER Vector90 +#define SN32_CT32B2_HANDLER Vector94 + +#define SN32_CT32B0_NUMBER CT32B0_IRQn +#define SN32_CT32B1_NUMBER CT32B1_IRQn +#define SN32_CT32B2_NUMBER CT32B2_IRQn + +/* + * ADC unit. + */ +#define SN32_ADC_HANDLER VectorA0 +#define SN32_ADC_NUMBER ADC_IRQn + +/* + * WDT unit. + */ +#define SN32_WDT_HANDLER VectorA4 +#define SN32_WDT_NUMBER WDT_IRQn + +/* + * LVD unit. + */ +#define SN32_LVD_HANDLER VectorA8 +#define SN32_LVD_NUMBER LVD_IRQn + +/* + * GPIO units. + */ +#define SN32_GPIOD_HANDLER VectorB0 +#define SN32_GPIOC_HANDLER VectorB4 +#define SN32_GPIOB_HANDLER VectorB8 +#define SN32_GPIOA_HANDLER VectorBC + +#define SN32_GPIOD_NUMBER P3_IRQn +#define SN32_GPIOC_NUMBER P2_IRQn +#define SN32_GPIOB_NUMBER P1_IRQn +#define SN32_GPIOA_NUMBER P0_IRQn +/*===========================================================================*/ +/* Common. */ +/*===========================================================================*/ + + + +/** @} */ + +#endif /* SN32_REGISTRY_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/SN32F240B/hal_lld.c b/os/hal/ports/SN32/SN32F240B/hal_lld.c new file mode 100644 index 00000000..a6794a05 --- /dev/null +++ b/os/hal/ports/SN32/SN32F240B/hal_lld.c @@ -0,0 +1,74 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_lld.c + * @brief PLATFORM HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "hal.h" +#include + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief SN32F24xx clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +void sn32_clock_init(void) { + SystemCoreClockUpdate(); + FlashClockUpdate(); +} + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + SystemInit(); + sn32_clock_init(); +} + +/** @} */ diff --git a/os/hal/ports/SN32/SN32F240B/hal_lld.h b/os/hal/ports/SN32/SN32F240B/hal_lld.h new file mode 100644 index 00000000..68a4c407 --- /dev/null +++ b/os/hal/ports/SN32/SN32F240B/hal_lld.h @@ -0,0 +1,90 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_lld.h + * @brief PLATFORM HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#include "sn32_registry.h" + +/** + * @name Platform identification macros + * @{ + */ +#define PLATFORM_NAME "SN32F24xB" +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ +#define SN32_HCLK SystemCoreClock +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(PLATFORM_MCUCONF) +#error "Using a wrong mcuconf.h file, PLATFORM_MCUCONF not defined" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* Various helpers.*/ +#include "nvic.h" +#include "sn32_ct.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void sn32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/SN32/SN32F240B/platform.mk b/os/hal/ports/SN32/SN32F240B/platform.mk new file mode 100644 index 00000000..66b64149 --- /dev/null +++ b/os/hal/ports/SN32/SN32F240B/platform.mk @@ -0,0 +1,32 @@ +# Required platform files. +PLATFORMSRC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/SN32F240B/hal_lld.c + +# Required include directories. +PLATFORMINC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ + ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/SN32F240B + +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(CONFDIR),) + CONFDIR = . +endif + +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define")) + +endif + +# Drivers compatible with the platform. +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/USB/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/CT/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/FLASH/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SPI/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/WDT/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC_CONTRIB) +ALLINC += $(PLATFORMINC_CONTRIB) \ No newline at end of file diff --git a/os/hal/ports/SN32/SN32F240B/sn32_registry.h b/os/hal/ports/SN32/SN32F240B/sn32_registry.h new file mode 100644 index 00000000..a615cf7e --- /dev/null +++ b/os/hal/ports/SN32/SN32F240B/sn32_registry.h @@ -0,0 +1,140 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SN32F240B/sn32_registry.h + * @brief SN32F24xB capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef SN32_REGISTRY_H +#define SN32_REGISTRY_H + +/* Common identifier of all SN32F2xx devices.*/ +#if !defined(SN32F2xx) || defined(__DOXYGEN__) +#define SN32F2xx +#endif + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name SN32F24xB capabilities + * @{ + */ + +/* Common identifier of all SN32F24xB devices.*/ +#if !defined(SN32F240B) || defined(__DOXYGEN__) +#define SN32F240B +#endif + +/* + * ST unit + */ +#define SN32_ST_HANDLER Vector3C +#define SN32_ST_NUMBER SysTick_IRQn + +/* + * NDT unit. + */ +#define SN32_NDT_HANDLER Vector40 +#define SN32_NDT_NUMBER NDT_IRQn + +/* + * USB unit. + */ +#define SN32_USB_HANDLER Vector44 +#define SN32_USB_NUMBER USB_IRQn + +#define USBD_INTSTS_EPEVT_Pos USBD_INTSTS_EPEVT0_Pos +#define USBD_INTSTS_EPEVT_Msk (0xFFul << USBD_INTSTS_EPEVT_Pos) + +/* + * SPI unit. + */ +#define SN32_SPI0_HANDLER Vector58 +#define SN32_SPI0_NUMBER SPI0_IRQn + +/* + * I2C unit. + */ +#define SN32_I2C0_GLOBAL_HANDLER Vector68 +#define SN32_I2C0_GLOBAL_NUMBER I2C0_IRQn + +/* + * UART units. + */ +#define SN32_UART0_HANDLER Vector70 +#define SN32_UART1_HANDLER Vector74 +#define SN32_UART2_HANDLER Vector78 + +#define SN32_UART0_NUMBER UART0_IRQn +#define SN32_UART1_NUMBER UART1_IRQn +#define SN32_UART2_NUMBER UART2_IRQn + +/* + * CT16 units. + */ +#define SN32_CT16B0_HANDLER Vector7C +#define SN32_CT16B1_HANDLER Vector80 + +#define SN32_CT16B0_NUMBER CT16B0_IRQn +#define SN32_CT16B1_NUMBER CT16B1_IRQn + +/* + * ADC unit. + */ +#define SN32_ADC_HANDLER VectorA0 +#define SN32_ADC_NUMBER ADC_IRQn + +/* + * WDT unit. + */ +#define SN32_WDT_HANDLER VectorA4 +#define SN32_WDT_NUMBER WDT_IRQn + +/* + * LVD unit. + */ +#define SN32_LVD_HANDLER VectorA8 +#define SN32_LVD_NUMBER LVD_IRQn + +/* + * GPIO units. + */ +#define SN32_GPIOD_HANDLER VectorB0 +#define SN32_GPIOC_HANDLER VectorB4 +#define SN32_GPIOB_HANDLER VectorB8 +#define SN32_GPIOA_HANDLER VectorBC + +#define SN32_GPIOD_NUMBER P3_IRQn +#define SN32_GPIOC_NUMBER P2_IRQn +#define SN32_GPIOB_NUMBER P1_IRQn +#define SN32_GPIOA_NUMBER P0_IRQn +/*===========================================================================*/ +/* Common. */ +/*===========================================================================*/ + + + +/** @} */ + +#endif /* SN32_REGISTRY_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/SN32F240B/sn32_sys1.h b/os/hal/ports/SN32/SN32F240B/sn32_sys1.h new file mode 100644 index 00000000..f7a82f64 --- /dev/null +++ b/os/hal/ports/SN32/SN32F240B/sn32_sys1.h @@ -0,0 +1,407 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SN32F240B/sn32_sys1.h + * @brief SYS1 helper driver header. + * @note This file requires definitions from the SN32 header file + * @p SN32F240B.h. + * + * @addtogroup SN32F24xB_SYS1 + * @{ + */ + +#ifndef SN32_SYS1_H +#define SN32_SYS1_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic AHB operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define sys1EnableAHB(mask) { \ + SN_SYS1->AHBCLKEN |= (mask); \ + (void)SN_SYS1->AHBCLKEN; \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define sys1DisableAHB(mask) { \ + SN_SYS1->AHBCLKEN &= ~(mask); \ + (void)SN_SYS1->AHBCLKEN; \ +} + +/** + * @brief Selects the clock prescaler of one or more peripheral on the APB bus. + * + * @param[in] mask APB peripherals mask + * + * @api + */ +#define sys1SelectAPB(mask) { \ + SN_SYS1->APBCP1 |= (mask); \ + (void)SN_SYS1->APBCP1; \ +} + +/** @} */ + +/** + * @name P0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the P0 peripheral clock. + * + + * + * @api + */ +#define sys1EnableP0() sys1EnableAHB(0x1<<0) + +/** + * @brief Disables the P0 peripheral clock. + * + * @api + */ +#define sys1DisableP0() sys1DisableAHB(0x1<<0) + +/** + * @name P1 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the P1 peripheral clock. + * + * @api + */ +#define sys1EnableP1() sys1EnableAHB(0x1<<1) + +/** + * @brief Disables the P1 peripheral clock. + * + * @api + */ +#define sys1DisableP1() sys1DisableAHB(0x1<<1) + +/** + * @name P2 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the P2 peripheral clock. + * + * @api + */ +#define sys1EnableP2() sys1EnableAHB(0x1<<2) + +/** + * @brief Disables the P2 peripheral clock. + * + * @api + */ +#define sys1DisableP2() sys1DisableAHB(0x1<<2) + +/** + * @name P3 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the P3 peripheral clock. + * + * @api + */ +#define sys1EnableP3() sys1EnableAHB(0x1<<3) + +/** + * @brief Disables the P3 peripheral clock. + * + * @api + */ +#define sys1DisableP3() sys1DisableAHB(0x1<<3) + +/** + * @name USB peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the USB peripheral clock. + * + * @api + */ +#define sys1EnableUSB() sys1EnableAHB(0x1<<4) + +/** + * @brief Disables the USB peripheral clock. + * + * @api + */ +#define sys1DisableUSB() sys1DisableAHB(0x1<<4) + +/** + * @name CT16B0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CT16B0 peripheral clock. + * + * @api + */ +#define sys1EnableCT16B0() sys1EnableAHB(0x1<<6) + +/** + * @brief Disables the CT16B0 peripheral clock. + * + * @api + */ +#define sys1DisableCT16B0() sys1DisableAHB(0x1<<6) + +/** + * @name CT16B1 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CT16B1 peripheral clock. + * + * @api + */ +#define sys1EnableCT16B1() sys1EnableAHB(0x1<<7) + +/** + * @brief Disables the CT16B0 peripheral clock. + * + * @api + */ +#define sys1DisableCT16B1() sys1DisableAHB(0x1<<7) + +/** + * @name ADC peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the ADC peripheral clock. + * + * @api + */ +#define sys1EnableADC() sys1EnableAHB(0x1<<11) + +/** + * @brief Disables the ADC peripheral clock. + * + * @api + */ +#define sys1DisableADC() sys1DisableAHB(0x1<<11) + +/** + * @name SPI0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the SPI0 peripheral clock. + * + * @api + */ +#define sys1EnableSPI0() sys1EnableAHB(0x1<<12) + +/** + * @brief Disables the SPI0 peripheral clock. + * + * @api + */ +#define sys1DisableSPI0() sys1DisableAHB(0x1<<12) + +/** + * @name UART0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the UART0 peripheral clock. + * + * @api + */ +#define sys1EnableUART0() sys1EnableAHB(0x1<<16) + +/** + * @brief Disables the UART0 peripheral clock. + * + * @api + */ +#define sys1DisableUART0() sys1DisableAHB(0x1<<16) + +/** + * @name UART1 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the UART1 peripheral clock. + * + * @api + */ +#define sys1EnableUART1() sys1EnableAHB(0x1<<17) + +/** + * @brief Disables the UART1 peripheral clock. + * + * @api + */ +#define sys1DisableUART1() sys1DisableAHB(0x1<<17) + +/** + * @name UART2 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the UART2 peripheral clock. + * + * @api + */ +#define sys1EnableUART2() sys1EnableAHB(0x1<<18) + +/** + * @brief Disables the UART2 peripheral clock. + * + * @api + */ +#define sys1DisableUART2() sys1DisableAHB(0x1<<18) + +/** + * @name I2C0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the I2C0 peripheral clock. + * + * @api + */ +#define sys1EnableI2C0() sys1EnableAHB(0x1<<21) + +/** + * @brief Disables the I2C0 peripheral clock. + * + * @api + */ +#define sys1DisableI2C0() sys1DisableAHB(0x1<<21) + +/** + * @name WDT peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the WDT peripheral clock. + * + * @api + */ +#define sys1EnableWDT() sys1EnableAHB(0x1<<24) + +/** + * @brief Disables the WDT peripheral clock. + * + * @api + */ +#define sys1DisableWDT() sys1DisableAHB(0x1<<24) + +/** + * @brief Configures the WDT peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectWDTPRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB(pre<<20) \ +} + +/** + * @name CLKOUT peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CLKOUT peripheral clock. + * + * @param[in] clkval clock output source + * * @api + */ +#define sys1EnableCLKOUT(clkval) { \ + if(clkval > 0) \ + sys1EnableAHB(clkval<<28) \ +} + +/** + * @brief Disables the CLKOUT peripheral clock. + * + * @api + */ +#define sys1DisableCLKOUT() { \ + SN_SYS1->AHBCLKEN_b.CLKOUTSEL= 0; \ + (void)SN_SYS1->AHBCLKEN; \ +} + +/** + * @brief Configures the CLKOUT peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectCLKOUTPRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB(pre<<28) \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* SN32_SYS1_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/SN32F260/hal_lld.c b/os/hal/ports/SN32/SN32F260/hal_lld.c new file mode 100644 index 00000000..cdbdbc33 --- /dev/null +++ b/os/hal/ports/SN32/SN32F260/hal_lld.c @@ -0,0 +1,73 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_lld.c + * @brief PLATFORM HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "hal.h" +#include + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief SN32F260 clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +void sn32_clock_init(void) { + SystemCoreClockUpdate(); +} + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + SystemInit(); + sn32_clock_init(); +} + +/** @} */ diff --git a/os/hal/ports/SN32/SN32F260/hal_lld.h b/os/hal/ports/SN32/SN32F260/hal_lld.h new file mode 100644 index 00000000..b182d1c2 --- /dev/null +++ b/os/hal/ports/SN32/SN32F260/hal_lld.h @@ -0,0 +1,90 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_lld.h + * @brief PLATFORM HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#include "sn32_registry.h" + +/** + * @name Platform identification macros + * @{ + */ +#define PLATFORM_NAME "SN32F26x" +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ +#define SN32_HCLK SystemCoreClock +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(PLATFORM_MCUCONF) +#error "Using a wrong mcuconf.h file, PLATFORM_MCUCONF not defined" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* Various helpers.*/ +#include "nvic.h" +#include "sn32_ct.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void sn32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/SN32/SN32F260/platform.mk b/os/hal/ports/SN32/SN32F260/platform.mk new file mode 100644 index 00000000..2082c739 --- /dev/null +++ b/os/hal/ports/SN32/SN32F260/platform.mk @@ -0,0 +1,32 @@ +# Required platform files. +PLATFORMSRC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/SN32F260/hal_lld.c + +# Required include directories. +PLATFORMINC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ + ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx \ + $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/SN32F260 + +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(CONFDIR),) + CONFDIR = . +endif + +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define")) + +endif + +# Drivers compatible with the platform. +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/USB/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/CT/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/FLASH/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SPI/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/WDT/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC_CONTRIB) +ALLINC += $(PLATFORMINC_CONTRIB) diff --git a/os/hal/ports/SN32/SN32F260/sn32_registry.h b/os/hal/ports/SN32/SN32F260/sn32_registry.h new file mode 100644 index 00000000..c2a9346b --- /dev/null +++ b/os/hal/ports/SN32/SN32F260/sn32_registry.h @@ -0,0 +1,115 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SN32F260/sn32_registry.h + * @brief SN32F26x capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef SN32_REGISTRY_H +#define SN32_REGISTRY_H + +/* Common identifier of all SN32F2xx devices.*/ +#if !defined(SN32F2xx) || defined(__DOXYGEN__) +#define SN32F2xx +#endif + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name SN32F26x capabilities + * @{ + */ + +/* Common identifier of all SN32F26x devices.*/ +#if !defined(SN32F260) || defined(__DOXYGEN__) +#define SN32F260 +#endif + +/* + * ST unit + */ +#define SN32_ST_HANDLER Vector3C +#define SN32_ST_NUMBER SysTick_IRQn + +/* + * NDT unit. + */ +#define SN32_NDT_HANDLER Vector40 +#define SN32_NDT_NUMBER NDT_IRQn + +/* + * USB unit. + */ +#define SN32_USB_HANDLER Vector44 +#define SN32_USB_NUMBER USB_IRQn + +/* + * SPI unit. + */ +#define SN32_SPI0_HANDLER Vector74 +#define SN32_SPI0_NUMBER SPI0_IRQn + +/* + * I2C unit. + */ +#define SN32_I2C0_GLOBAL_HANDLER Vector7C +#define SN32_I2C0_GLOBAL_NUMBER I2C0_IRQn + +/* + * CT16 units. + */ +#define SN32_CT16B0_HANDLER Vector80 +#define SN32_CT16B1_HANDLER Vector84 + +#define SN32_CT16B0_NUMBER CT16B0_IRQn +#define SN32_CT16B1_NUMBER CT16B1_IRQn + +/* + * WDT unit. + */ +#define SN32_WDT_HANDLER VectorA4 +#define SN32_WDT_NUMBER WDT_IRQn + +/* + * LVD unit. + */ +#define SN32_LVD_HANDLER VectorA8 +#define SN32_LVD_NUMBER LVD_IRQn + +/* + * GPIO units. + */ +#define SN32_GPIOD_HANDLER VectorB0 +#define SN32_GPIOC_HANDLER VectorB4 +#define SN32_GPIOB_HANDLER VectorB8 +#define SN32_GPIOA_HANDLER VectorBC + +#define SN32_GPIOD_NUMBER P3_IRQn +#define SN32_GPIOC_NUMBER P2_IRQn +#define SN32_GPIOB_NUMBER P1_IRQn +#define SN32_GPIOA_NUMBER P0_IRQn + +/** @} */ + +#endif /* SN32_REGISTRY_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/SN32F260/sn32_sys1.h b/os/hal/ports/SN32/SN32F260/sn32_sys1.h new file mode 100644 index 00000000..7e7559e1 --- /dev/null +++ b/os/hal/ports/SN32/SN32F260/sn32_sys1.h @@ -0,0 +1,347 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SN32F260B/sn32_sys1.h + * @brief SYS1 helper driver header. + * @note This file requires definitions from the SN32 header file + * @p SN32F260.h. + * + * @addtogroup SN32F26x_SYS1 + * @{ + */ + +#ifndef SN32_SYS1_H +#define SN32_SYS1_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic AHB operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define sys1EnableAHB(mask) { \ + SN_SYS1->AHBCLKEN |= (mask); \ + (void)SN_SYS1->AHBCLKEN; \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define sys1DisableAHB(mask) { \ + SN_SYS1->AHBCLKEN &= ~(mask); \ + (void)SN_SYS1->AHBCLKEN; \ +} + +/** + * @brief Selects the clock prescaler of one or more peripheral on the APB bus. + * + * @param[in] mask APB peripherals mask + * + * @api + */ +#define sys1SelectAPB(mask) { \ + SN_SYS1->APBCP1 |= (mask); \ + (void)SN_SYS1->APBCP1; \ +} + +/** @} */ + +/** + * @name P0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the P0 peripheral clock. + * + + * + * @api + */ +#define sys1EnableP0() sys1EnableAHB(0x1<<0) + +/** + * @brief Disables the P0 peripheral clock. + * + * @api + */ +#define sys1DisableP0() sys1DisableAHB(0x1<<0) + +/** + * @name P1 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the P1 peripheral clock. + * + * @api + */ +#define sys1EnableP1() sys1EnableAHB(0x1<<1) + +/** + * @brief Disables the P1 peripheral clock. + * + * @api + */ +#define sys1DisableP1() sys1DisableAHB(0x1<<1) + +/** + * @name P2 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the P2 peripheral clock. + * + * @api + */ +#define sys1EnableP2() sys1EnableAHB(0x1<<2) + +/** + * @brief Disables the P2 peripheral clock. + * + * @api + */ +#define sys1DisableP2() sys1DisableAHB(0x1<<2) + +/** + * @name P3 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the P3 peripheral clock. + * + * @api + */ +#define sys1EnableP3() sys1EnableAHB(0x1<<3) + +/** + * @brief Disables the P3 peripheral clock. + * + * @api + */ +#define sys1DisableP3() sys1DisableAHB(0x1<<3) + +/** + * @name USB peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the USB peripheral clock. + * + * @api + */ +#define sys1EnableUSB() sys1EnableAHB(0x1<<4) + +/** + * @brief Disables the USB peripheral clock. + * + * @api + */ +#define sys1DisableUSB() sys1DisableAHB(0x1<<4) + +/** + * @name CT16B0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CT16B0 peripheral clock. + * + * @api + */ +#define sys1EnableCT16B0() sys1EnableAHB(0x1<<6) + +/** + * @brief Disables the CT16B0 peripheral clock. + * + * @api + */ +#define sys1DisableCT16B0() sys1DisableAHB(0x1<<6) + +/** + * @name CT16B1 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CT16B1 peripheral clock. + * + * @api + */ +#define sys1EnableCT16B1() sys1EnableAHB(0x1<<7) + +/** + * @brief Disables the CT16B0 peripheral clock. + * + * @api + */ +#define sys1DisableCT16B1() sys1DisableAHB(0x1<<7) + +/** + * @name SPI0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the SPI0 peripheral clock. + * + * @api + */ +#define sys1EnableSPI0() sys1EnableAHB(0x1<<12) + +/** + * @brief Disables the SPI0 peripheral clock. + * + * @api + */ +#define sys1DisableSPI0() sys1DisableAHB(0x1<<12) + +/** + * @name I2C0 peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the I2C0 peripheral clock. + * + * @api + */ +#define sys1EnableI2C0() sys1EnableAHB(0x1<<21) + +/** + * @brief Disables the I2C0 peripheral clock. + * + * @api + */ +#define sys1DisableI2C0() sys1DisableAHB(0x1<<21) + +/** + * @name WDT peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the WDT peripheral clock. + * + * @api + */ +#define sys1EnableWDT() sys1EnableAHB(0x1<<24) + +/** + * @brief Disables the WDT peripheral clock. + * + * @api + */ +#define sys1DisableWDT() sys1DisableAHB(0x1<<24) + +/** + * @brief Configures the WDT peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectWDTPRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB(pre<<20) \ +} + +/** + * @name CLKOUT peripherals specific SYS1 operations + * @{ + */ +/** + * @brief Enables the CLKOUT peripheral clock. + * + * @param[in] clkval clock output source + * * @api + */ +#define sys1EnableCLKOUT(clkval) { \ + if(clkval > 0) \ + sys1EnableAHB(clkval<<28) \ +} + +/** + * @brief Disables the CLKOUT peripheral clock. + * + * @api + */ +#define sys1DisableCLKOUT() { \ + SN_SYS1->AHBCLKEN_b.CLKOUTSEL= 0; \ + (void)SN_SYS1->AHBCLKEN; \ +} + +/** + * @brief Configures the CLKOUT peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectCLKOUTPRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB(pre<<28) \ +} + +/** + * @brief Configures the SysTick peripheral clock. + * + * @param[in] pre clock source prescaler + * * @api + */ +#define sys1SelectSYSTICKPRE(pre) { \ + if(pre > 0) \ + sys1SelectAPB(pre<<16) \ +} + +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* SN32_SYS1_H */ + +/** @} */