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Update the DMA configuration of the ADC.

This commit is contained in:
Joy 2022-05-13 18:19:53 +08:00
parent 9da9be4514
commit ea52b392fc
3 changed files with 122 additions and 41 deletions
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45
os/hal/ports/WB32/LLD/ADCv1/hal_adc_lld.c
View File

@ -96,31 +96,15 @@ void adc_lld_init(void) {
#if WB32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD1.adc = ADC;
ADCD1.dmastp = NULL;
ADCD1.dmamode.interrupt = WB32_DMAC_INTERRUPT_EN;
ADCD1.dmamode.src_width = WB32_DMAC_SRC_WIDTH_HWORD;
ADCD1.dmamode.dst_width = WB32_DMAC_DST_WIDTH_HWORD;
ADCD1.dmamode.src_addr_inc = WB32_DMAC_SRC_ADDR_NOC;
ADCD1.dmamode.dst_addr_inc = WB32_DMAC_DST_ADDR_INC;
ADCD1.dmamode.trf_tfc = WB32_DMAC_TRF_TFC_P2MD;
ADCD1.dmamode.src_master_if = WB32_DMAC_SRC_MASTER_IF_APB;
ADCD1.dmamode.dst_master_if = WB32_DMAC_DST_MASTER_IF_AHB;
ADCD1.dmamode.src_auto_reload = WB32_DMAC_SRC_AUTO_RELOAD_DIS;
ADCD1.dmamode.dst_auto_reload = WB32_DMAC_DST_AUTO_RELOAD_EN;
ADCD1.dmamode.ch_priority = WB32_ADC_ADC1_DMA_PRIORITY;
ADCD1.dmamode.src_hwhif = WB32_DMAC_HWHIF_ADC_Regular;
ADCD1.dmamode.src_hifs = WB32_DMAC_SRC_HIFS_HW;
ADCD1.dmamode.dst_hifs = WB32_DMAC_DST_HIFS_HW;
ADCD1.dmamode.fc_mode = WB32_DMAC_FC_MODE0;
ADCD1.dmamode.fifo_mode = WB32_DMAC_FIFO_MODE0;
ADCD1.dmamode.dst_hifp = WB32_DMAC_DST_HIFP_HIGH;
ADCD1.dmamode.src_hifp = WB32_DMAC_SRC_HIFP_HIGH;
ADCD1.dmamode.src_trs_len = WB32_DMAC_SRC_TRS_LEN_1;
ADCD1.dmamode.dst_trs_len = WB32_DMAC_DST_TRS_LEN_1;
ADCD1.dmamode.dst_hwhif = 0;
ADCD1.dmamode.brs_maxlen = 0;
ADCD1.dmamode.prot_ctl = 1;
ADCD1.adc = ADC;
ADCD1.dmastp = NULL;
ADCD1.dmamode = WB32_DMA_CHCFG_HWHIF(WB32_DMAC_HWHIF_ADC_Regular) | \
WB32_DMA_CHCFG_PL(WB32_ADC_ADC1_DMA_PRIORITY) | \
WB32_DMA_CHCFG_PSIZE_HWORD | \
WB32_DMA_CHCFG_MSIZE_HWORD | \
WB32_DMA_CHCFG_DIR_P2M | \
WB32_DMA_CHCFG_MINC | \
WB32_DMA_CHCFG_CIRC;
/* Temporary activation.*/
rccEnableADC();
@ -232,19 +216,18 @@ void adc_lld_stop(ADCDriver *adcp) {
* @notapi
*/
void adc_lld_start_conversion(ADCDriver *adcp) {
uint32_t cr2, tmpreg1 = 0;
wb32_dmac_chinit_t mode;
const ADCConversionGroup *grpp = adcp->grpp;
uint32_t cr2, mode;
uint32_t tmpreg1 = 0;
const ADCConversionGroup *grpp = adcp->grpp;
/* DMA setup.*/
mode = adcp->dmamode;
if (grpp->circular) {
mode.dst_auto_reload = WB32_DMAC_DST_AUTO_RELOAD_EN;
mode |= WB32_DMA_CHCFG_CIRC;
if (adcp->depth > 1) {
/* If circular buffer depth > 1, then the half transfer interrupt
is enabled in order to allow streaming processing.*/
mode.interrupt = WB32_DMAC_INTERRUPT_EN;
dmaStreamEnableInterrupt(adcp->dmastp, WB32_DMAC_IT_TFR);
mode |= WB32_DMA_CHCFG_TCIE;
}
}
dmaStreamSetDestination(adcp->dmastp, adcp->samples);

4
os/hal/ports/WB32/LLD/ADCv1/hal_adc_lld.h
View File

@ -175,9 +175,9 @@ typedef enum {
/* Pointer to the ADCx registers block.*/ \
ADC_TypeDef *adc; \
/* Pointer to associated DMA channel.*/ \
const wb32_dma_stream_t *dmastp; \
const wb32_dma_stream_t *dmastp; \
/* DMA mode bit mask.*/ \
wb32_dmac_chinit_t dmamode
uint32_t dmamode \
/**
* @brief Low level fields of the ADC configuration structure.

114
os/hal/ports/WB32/LLD/DMAv1/wb32_dma.h
View File

@ -340,13 +340,31 @@
* @{
*/
/* The following definitions is only used for DMAC1. */
#define WB32_DMAC_HWHIF_TIM1_CH1_TIM2_UP_TIM3_CH3 0
#define WB32_DMAC_HWHIF_TIM1_CH4_TIM1_TRIG_TIM1_COM_TIM4_CH2 1
#define WB32_DMAC_HWHIF_TIM1_UP_TIM2_CH1_TIM4_CH3 2
#define WB32_DMAC_HWHIF_TIM1_CH3_TIM3_CH1_TIM3_TRIG 3
#define WB32_DMAC_HWHIF_TIM2_CH3_TIM4_CH1 4
#define WB32_DMAC_HWHIF_TIM2_CH2_TIM2_CH4_TIM4_UP 5
#define WB32_DMAC_HWHIF_TIM3_CH4_TIM3_UP_TIM1_CH2 6
#define WB32_DMAC_HWHIF_TIM1_UP 2
#define WB32_DMAC_HWHIF_TIM1_COM 1
#define WB32_DMAC_HWHIF_TIM1_CH1 0
#define WB32_DMAC_HWHIF_TIM1_CH2 6
#define WB32_DMAC_HWHIF_TIM1_CH3 3
#define WB32_DMAC_HWHIF_TIM1_CH4 1
#define WB32_DMAC_HWHIF_TIM1_TRIG 1
#define WB32_DMAC_HWHIF_TIM2_UP 0
#define WB32_DMAC_HWHIF_TIM2_CH1 2
#define WB32_DMAC_HWHIF_TIM2_CH2 5
#define WB32_DMAC_HWHIF_TIM2_CH3 4
#define WB32_DMAC_HWHIF_TIM2_CH4 5
#define WB32_DMAC_HWHIF_TIM3_UP 6
#define WB32_DMAC_HWHIF_TIM3_CH1 3
#define WB32_DMAC_HWHIF_TIM3_CH3 0
#define WB32_DMAC_HWHIF_TIM3_CH4 6
#define WB32_DMAC_HWHIF_TIM3_TRIG 3
#define WB32_DMAC_HWHIF_TIM4_UP 5
#define WB32_DMAC_HWHIF_TIM4_CH1 4
#define WB32_DMAC_HWHIF_TIM4_CH2 1
#define WB32_DMAC_HWHIF_TIM4_CH3 2
#define WB32_DMAC_HWHIF_QSPI_RX 7
#define WB32_DMAC_HWHIF_QSPI_TX 8
#define WB32_DMAC_HWHIF_SPIS1_RX 9
@ -373,6 +391,37 @@
* @}
*/
/** @defgroup DMAC configuration parameters for use simple config.
* @{
*/
#define WB32_DMA_CHCFG_SIZE_MASK (0x1FFU)
#define WB32_DMA_CHCFG_EN (0x01U << 0)
#define WB32_DMA_CHCFG_TCIE (0x01U << 1)
#define WB32_DMA_CHCFG_HTIE (0x01U << 2)
#define WB32_DMA_CHCFG_TEIE (0x01U << 3)
#define WB32_DMA_CHCFG_DIR_MASK (0x03U << 4)
#define WB32_DMA_CHCFG_DIR_M2M (0x00U << 4)
#define WB32_DMA_CHCFG_DIR_M2P (0x01U << 4)
#define WB32_DMA_CHCFG_DIR_P2M (0x02U << 4)
#define WB32_DMA_CHCFG_CIRC (0x01U << 6)
#define WB32_DMA_CHCFG_PINC (0x01U << 7)
#define WB32_DMA_CHCFG_MINC (0x01U << 8)
#define WB32_DMA_CHCFG_PSIZE_MASK (0x03U << 9)
#define WB32_DMA_CHCFG_PSIZE_BYTE (0x00U << 9)
#define WB32_DMA_CHCFG_PSIZE_HWORD (0x01U << 9)
#define WB32_DMA_CHCFG_PSIZE_WORD (0x02U << 9)
#define WB32_DMA_CHCFG_MSIZE_MASK (0x03U << 11)
#define WB32_DMA_CHCFG_MSIZE_BYTE (0x00U << 11)
#define WB32_DMA_CHCFG_MSIZE_HWORD (0x01U << 11)
#define WB32_DMA_CHCFG_MSIZE_WORD (0x02U << 11)
#define WB32_DMA_CHCFG_PL_MASK (0x07U << 13)
#define WB32_DMA_CHCFG_PL(n) ((n) << 13)
#define WB32_DMA_CHCFG_HWHIF_MASK (0xFFU << 16)
#define WB32_DMA_CHCFG_HWHIF(n) ((n) << 16)
/**
* @}
*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@ -554,7 +603,55 @@ typedef struct {
*
* @special
*/
#define dmaStreamSetMode(dmastp, mode) { \
#define dmaStreamSetMode(dmastp, mode) { \
switch ((uint32_t)(mode) & WB32_DMA_CHCFG_DIR_MASK) { \
case WB32_DMA_CHCFG_DIR_M2M: /* M2M */ \
(dmastp)->dmac->Ch[(dmastp)->channel].CFGL = WB32_DMAC_TRF_TFC_M2MD | \
WB32_DMAC_SRC_MASTER_IF_AHB | \
WB32_DMAC_DST_MASTER_IF_AHB | \
(((mode) & WB32_DMA_CHCFG_PSIZE_MASK) >> 5) | \
(((mode) & WB32_DMA_CHCFG_MSIZE_MASK) >> 10) | \
((!((mode) & WB32_DMA_CHCFG_PINC)) << 10) | \
((!((mode) & WB32_DMA_CHCFG_MINC)) << 8); \
(dmastp)->dmac->Ch[(dmastp)->channel].CFGH = (1U << 2); \
break; \
case WB32_DMA_CHCFG_DIR_M2P: /* M2P */ \
(dmastp)->dmac->Ch[(dmastp)->channel].CTLL = WB32_DMAC_TRF_TFC_M2PD | \
WB32_DMAC_SRC_MASTER_IF_AHB | \
WB32_DMAC_DST_MASTER_IF_APB | \
(((mode) & WB32_DMA_CHCFG_MSIZE_MASK) >> 7) | \
(((mode) & WB32_DMA_CHCFG_PSIZE_MASK) >> 8) | \
((!((mode) & WB32_DMA_CHCFG_MINC)) << 10) | \
((!((mode) & WB32_DMA_CHCFG_PINC)) << 8); \
(dmastp)->dmac->Ch[(dmastp)->channel].CFGH = (((mode) & WB32_DMA_CHCFG_HWHIF_MASK) >> 5) | \
(1U << 2); \
break; \
case WB32_DMA_CHCFG_DIR_P2M: /* P2M */ \
(dmastp)->dmac->Ch[(dmastp)->channel].CTLL = WB32_DMAC_TRF_TFC_P2MD | \
WB32_DMAC_SRC_MASTER_IF_APB | \
WB32_DMAC_DST_MASTER_IF_AHB | \
(((mode) & WB32_DMA_CHCFG_PSIZE_MASK) >> 5) | \
(((mode) & WB32_DMA_CHCFG_MSIZE_MASK) >> 10) | \
((!((mode) & WB32_DMA_CHCFG_PINC)) << 10) | \
((!((mode) & WB32_DMA_CHCFG_MINC)) << 8); \
(dmastp)->dmac->Ch[(dmastp)->channel].CFGH = (((mode) & WB32_DMA_CHCFG_HWHIF_MASK) >> 9) | \
(1U << 2); \
break; \
} \
(dmastp)->dmac->Ch[(dmastp)->channel].CFGL = (((mode) & WB32_DMA_CHCFG_PL_MASK) >> 8) | \
(((mode) & WB32_DMA_CHCFG_CIRC) << 24) | \
(((mode) & WB32_DMA_CHCFG_CIRC) << 25); \
if ((mode) & (WB32_DMA_CHCFG_TCIE | WB32_DMA_CHCFG_HTIE)) { \
(dmastp)->dmac->Ch[(dmastp)->channel].CTLL |= WB32_DMAC_INTERRUPT_EN; \
dmaStreamEnableInterrupt(dmastp, WB32_DMAC_IT_TFR); \
} \
if ((mode) & WB32_DMA_CHCFG_TEIE) { \
(dmastp)->dmac->Ch[(dmastp)->channel].CTLL |= WB32_DMAC_INTERRUPT_EN; \
dmaStreamEnableInterrupt(dmastp, WB32_DMAC_IT_ERR); \
} \
}
#define dmaStreamSetModeI(dmastp, mode) { \
(dmastp)->dmac->Ch[(dmastp)->channel].CTLL = (mode).interrupt | \
(mode).dst_width | \
(mode).src_width | \
@ -580,6 +677,7 @@ typedef struct {
((mode).dst_hwhif << 11); \
}
/**
* @brief DMA stream enable interrupt configuration.
* @note This function can be invoked in both ISR or thread context.