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Added Tiva board files.

This commit is contained in:
marcoveeneman 2014-10-13 22:58:53 +02:00
parent 4efd390b03
commit ed9baddee3
6 changed files with 1550 additions and 0 deletions
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os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c Normal file
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/*
Copyright (C) 2014 Marco Veeneman
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "hal.h"
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
#if HAL_USE_PAL || defined(__DOXYGEN__)
const PALConfig pal_default_config =
{
{VAL_GPIOA_DATA, VAL_GPIOA_DIR, VAL_GPIOA_AFSEL, VAL_GPIOA_DR2R,
VAL_GPIOA_DR4R, VAL_GPIOA_DR8R, VAL_GPIOA_ODR, VAL_GPIOA_PUR,
VAL_GPIOA_PDR, VAL_GPIOA_SLR, VAL_GPIOA_DEN, VAL_GPIOA_AMSEL,
VAL_GPIOA_PCTL},
{VAL_GPIOB_DATA, VAL_GPIOB_DIR, VAL_GPIOB_AFSEL, VAL_GPIOB_DR2R,
VAL_GPIOB_DR4R, VAL_GPIOB_DR8R, VAL_GPIOB_ODR, VAL_GPIOB_PUR,
VAL_GPIOB_PDR, VAL_GPIOB_SLR, VAL_GPIOB_DEN, VAL_GPIOB_AMSEL,
VAL_GPIOB_PCTL},
{VAL_GPIOC_DATA, VAL_GPIOC_DIR, VAL_GPIOC_AFSEL, VAL_GPIOC_DR2R,
VAL_GPIOC_DR4R, VAL_GPIOC_DR8R, VAL_GPIOC_ODR, VAL_GPIOC_PUR,
VAL_GPIOC_PDR, VAL_GPIOC_SLR, VAL_GPIOC_DEN, VAL_GPIOC_AMSEL,
VAL_GPIOC_PCTL},
{VAL_GPIOD_DATA, VAL_GPIOD_DIR, VAL_GPIOD_AFSEL, VAL_GPIOD_DR2R,
VAL_GPIOD_DR4R, VAL_GPIOD_DR8R, VAL_GPIOD_ODR, VAL_GPIOD_PUR,
VAL_GPIOD_PDR, VAL_GPIOD_SLR, VAL_GPIOD_DEN, VAL_GPIOD_AMSEL,
VAL_GPIOD_PCTL},
{VAL_GPIOE_DATA, VAL_GPIOE_DIR, VAL_GPIOE_AFSEL, VAL_GPIOE_DR2R,
VAL_GPIOE_DR4R, VAL_GPIOE_DR8R, VAL_GPIOE_ODR, VAL_GPIOE_PUR,
VAL_GPIOE_PDR, VAL_GPIOE_SLR, VAL_GPIOE_DEN, VAL_GPIOE_AMSEL,
VAL_GPIOE_PCTL},
{VAL_GPIOF_DATA, VAL_GPIOF_DIR, VAL_GPIOF_AFSEL, VAL_GPIOF_DR2R,
VAL_GPIOF_DR4R, VAL_GPIOF_DR8R, VAL_GPIOF_ODR, VAL_GPIOF_PUR,
VAL_GPIOF_PDR, VAL_GPIOF_SLR, VAL_GPIOF_DEN, VAL_GPIOF_AMSEL,
VAL_GPIOF_PCTL}
};
#endif
/**
* @brief Early initialization code.
* @details This initialization is performed just after reset before BSS and
* DATA segments initialization.
*/
void __early_init(void)
{
tiva_clock_init();
}
/**
* @brief Late initialization code.
* @note This initialization is performed after BSS and DATA segments
* initialization and before invoking the main() function.
*/
void boardInit(void)
{
}

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os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h Normal file
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/*
Copyright (C) 2014 Marco Veeneman
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* Setup for Texas Instruments TM4C123G Launchpad Board.
*/
/*
* Board identifier.
*/
#define BOARD_TI_TM4C123G_LAUNCHPAD
#define BOARD_NAME "Texas Instruments TM4C123G Launchpad"
/*
* MCU type
*/
//#define TM4C1230C3PM
//#define TM4C1230D5PM
//#define TM4C1230E6PM
//#define TM4C1230H6PM
//#define TM4C1231C3PM
//#define TM4C1231D5PM
//#define TM4C1231D5PZ
//#define TM4C1231E6PM
//#define TM4C1231E6PZ
//#define TM4C1231H6PGE
//#define TM4C1231H6PM
//#define TM4C1231H6PZ
//#define TM4C1232C3PM
//#define TM4C1232D5PM
//#define TM4C1232E6PM
//#define TM4C1232H6PM
//#define TM4C1233C3PM
//#define TM4C1233D5PM
//#define TM4C1233D5PZ
//#define TM4C1233E6PM
//#define TM4C1233E6PZ
//#define TM4C1233H6PGE
//#define TM4C1233H6PM
//#define TM4C1233H6PZ
//#define TM4C1236D5PM
//#define TM4C1236E6PM
//#define TM4C1236H6PM
//#define TM4C1237D5PM
//#define TM4C1237D5PZ
//#define TM4C1237E6PM
//#define TM4C1237E6PZ
//#define TM4C1237H6PGE
//#define TM4C1237H6PM
//#define TM4C1237H6PZ
//#define TM4C123AE6PM
//#define TM4C123AH6PM
//#define TM4C123BE6PM
//#define TM4C123BE6PZ
//#define TM4C123BH6PGE
//#define TM4C123BH6PM
//#define TM4C123BH6PZ
//#define TM4C123BH6ZRB
//#define TM4C123FE6PM
//#define TM4C123FH6PM
//#define TM4C123GE6PM
//#define TM4C123GE6PZ
//#define TM4C123GH6PGE
#define TM4C123GH6PM
//#define TM4C123GH6PZ
//#define TM4C123GH6ZRB
//#define TM4C123GH5ZXR
/*
* Board oscillators-related settings.
*/
#define TIVA_XTAL_VALUE 16000000
/*
* IO pins assignments.
*/
#define GPIOA_UART0_RX 0
#define GPIOA_UART0_TX 1
#define GPIOA_PIN2 2
#define GPIOA_PIN3 3
#define GPIOA_PIN4 4
#define GPIOA_PIN5 5
#define GPIOA_PIN6 6
#define GPIOA_PIN7 7
#define GPIOB_PIN0 0
#define GPIOB_PIN1 1
#define GPIOB_I2C0_SCL 2
#define GPIOB_I2C0_SDA 3
#define GPIOB_PIN4 4
#define GPIOB_PIN5 5
#define GPIOB_PIN6 6
#define GPIOB_PIN7 7
#define GPIOC_TCK_SWCLK 0
#define GPIOC_TMS_SWDIO 1
#define GPIOC_TDI 2
#define GPIOC_TDO_SWO 3
#define GPIOC_PIN4 4
#define GPIOC_PIN5 5
#define GPIOC_PIN6 6
#define GPIOC_PIN7 7
#define GPIOD_PIN0 0
#define GPIOD_PIN1 1
#define GPIOD_PIN2 2
#define GPIOD_PIN3 3
#define GPIOD_PIN4 4
#define GPIOD_PIN5 5
#define GPIOD_PIN6 6
#define GPIOD_PIN7 7
#define GPIOE_PIN0 0
#define GPIOE_PIN1 1
#define GPIOE_PIN2 2
#define GPIOE_PIN3 3
#define GPIOE_PIN4 4
#define GPIOE_PIN5 5
#define GPIOE_PIN6 6
#define GPIOE_PIN7 7
#define GPIOF_SW2 0
#define GPIOF_LED_RED 1
#define GPIOF_LED_BLUE 2
#define GPIOF_LED_GREEN 3
#define GPIOF_SW1 4
#define GPIOF_PIN5 5
#define GPIOF_PIN6 6
#define GPIOF_PIN7 7
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
*/
#define PIN_DATA_LOW(n) (0U << (n))
#define PIN_DATA_HIGH(n) (1U << (n))
#define PIN_DIR_IN(n) (0U << (n))
#define PIN_DIR_OUT(n) (1U << (n))
#define PIN_AFSEL_GPIO(n) (0U << (n))
#define PIN_AFSEL_ALTERNATE(n) (1U << (n))
#define PIN_ODR_DISABLE(n) (0U << (n))
#define PIN_ODR_ENABLE(n) (1U << (n))
#define PIN_PxR_DISABLE(n) (0U << (n))
#define PIN_PxR_ENABLE(n) (1U << (n))
#define PIN_DEN_DISABLE(n) (0U << (n))
#define PIN_DEN_ENABLE(n) (1U << (n))
#define PIN_AMSEL_DISABLE(n) (0U << (n))
#define PIN_AMSEL_ENABLE(n) (1U << (n))
#define PIN_DRxR_DISABLE(n) (0U << (n))
#define PIN_DRxR_ENABLE(n) (1U << (n))
#define PIN_SLR_DISABLE(n) (0U << (n))
#define PIN_SLR_ENABLE(n) (1U << (n))
#define PIN_PCTL_MODE(n, mode) (mode << ((n) * 4))
/*
* GPIOA Setup:
*
* PA0 - UART0 RX (alternate 1)
* PA1 - UART0 TX (alternate 1)
* PA2 - PIN2 ()
* PA3 - PIN3 ()
* PA4 - PIN4 ()
* PA5 - PIN5 ()
* PA6 - PIN6 ()
* PA7 - PIN7 ()
*/
#define VAL_GPIOA_DATA (PIN_DATA_LOW(GPIOA_UART0_RX) | \
PIN_DATA_LOW(GPIOA_UART0_TX) | \
PIN_DATA_LOW(GPIOA_PIN2) | \
PIN_DATA_LOW(GPIOA_PIN3) | \
PIN_DATA_LOW(GPIOA_PIN4) | \
PIN_DATA_LOW(GPIOA_PIN5) | \
PIN_DATA_LOW(GPIOA_PIN6) | \
PIN_DATA_LOW(GPIOA_PIN7))
#define VAL_GPIOA_DIR (PIN_DIR_IN(GPIOA_UART0_RX) | \
PIN_DIR_IN(GPIOA_UART0_TX) | \
PIN_DIR_IN(GPIOA_PIN2) | \
PIN_DIR_IN(GPIOA_PIN3) | \
PIN_DIR_IN(GPIOA_PIN4) | \
PIN_DIR_IN(GPIOA_PIN5) | \
PIN_DIR_IN(GPIOA_PIN6) | \
PIN_DIR_IN(GPIOA_PIN7))
#define VAL_GPIOA_AFSEL (PIN_AFSEL_ALTERNATE(GPIOA_UART0_RX) | \
PIN_AFSEL_ALTERNATE(GPIOA_UART0_TX) | \
PIN_AFSEL_GPIO(GPIOA_PIN2) | \
PIN_AFSEL_GPIO(GPIOA_PIN3) | \
PIN_AFSEL_GPIO(GPIOA_PIN4) | \
PIN_AFSEL_GPIO(GPIOA_PIN5) | \
PIN_AFSEL_GPIO(GPIOA_PIN6) | \
PIN_AFSEL_GPIO(GPIOA_PIN7))
#define VAL_GPIOA_ODR (PIN_ODR_DISABLE(GPIOA_UART0_RX) | \
PIN_ODR_DISABLE(GPIOA_UART0_TX) | \
PIN_ODR_DISABLE(GPIOA_PIN2) | \
PIN_ODR_DISABLE(GPIOA_PIN3) | \
PIN_ODR_DISABLE(GPIOA_PIN4) | \
PIN_ODR_DISABLE(GPIOA_PIN5) | \
PIN_ODR_DISABLE(GPIOA_PIN6) | \
PIN_ODR_DISABLE(GPIOA_PIN7))
#define VAL_GPIOA_PUR (PIN_PxR_DISABLE(GPIOA_UART0_RX) | \
PIN_PxR_DISABLE(GPIOA_UART0_TX) | \
PIN_PxR_DISABLE(GPIOA_PIN2) | \
PIN_PxR_DISABLE(GPIOA_PIN3) | \
PIN_PxR_DISABLE(GPIOA_PIN4) | \
PIN_PxR_DISABLE(GPIOA_PIN5) | \
PIN_PxR_DISABLE(GPIOA_PIN6) | \
PIN_PxR_DISABLE(GPIOA_PIN7))
#define VAL_GPIOA_PDR (PIN_PxR_DISABLE(GPIOA_UART0_RX) | \
PIN_PxR_DISABLE(GPIOA_UART0_TX) | \
PIN_PxR_DISABLE(GPIOA_PIN2) | \
PIN_PxR_DISABLE(GPIOA_PIN3) | \
PIN_PxR_DISABLE(GPIOA_PIN4) | \
PIN_PxR_DISABLE(GPIOA_PIN5) | \
PIN_PxR_DISABLE(GPIOA_PIN6) | \
PIN_PxR_DISABLE(GPIOA_PIN7))
#define VAL_GPIOA_DEN (PIN_DEN_ENABLE(GPIOA_UART0_RX) | \
PIN_DEN_ENABLE(GPIOA_UART0_TX) | \
PIN_DEN_ENABLE(GPIOA_PIN2) | \
PIN_DEN_ENABLE(GPIOA_PIN3) | \
PIN_DEN_ENABLE(GPIOA_PIN4) | \
PIN_DEN_ENABLE(GPIOA_PIN5) | \
PIN_DEN_ENABLE(GPIOA_PIN6) | \
PIN_DEN_ENABLE(GPIOA_PIN7))
#define VAL_GPIOA_AMSEL (PIN_AMSEL_DISABLE(GPIOA_UART0_RX) | \
PIN_AMSEL_DISABLE(GPIOA_UART0_TX) | \
PIN_AMSEL_DISABLE(GPIOA_PIN2) | \
PIN_AMSEL_DISABLE(GPIOA_PIN3))
#define VAL_GPIOA_DR2R (PIN_DRxR_ENABLE(GPIOA_UART0_RX) | \
PIN_DRxR_ENABLE(GPIOA_UART0_TX) | \
PIN_DRxR_ENABLE(GPIOA_PIN2) | \
PIN_DRxR_ENABLE(GPIOA_PIN3) | \
PIN_DRxR_ENABLE(GPIOA_PIN4) | \
PIN_DRxR_ENABLE(GPIOA_PIN5) | \
PIN_DRxR_ENABLE(GPIOA_PIN6) | \
PIN_DRxR_ENABLE(GPIOA_PIN7))
#define VAL_GPIOA_DR4R (PIN_DRxR_DISABLE(GPIOA_UART0_RX) | \
PIN_DRxR_DISABLE(GPIOA_UART0_TX) | \
PIN_DRxR_DISABLE(GPIOA_PIN2) | \
PIN_DRxR_DISABLE(GPIOA_PIN3) | \
PIN_DRxR_DISABLE(GPIOA_PIN4) | \
PIN_DRxR_DISABLE(GPIOA_PIN5) | \
PIN_DRxR_DISABLE(GPIOA_PIN6) | \
PIN_DRxR_DISABLE(GPIOA_PIN7))
#define VAL_GPIOA_DR8R (PIN_DRxR_DISABLE(GPIOA_UART0_RX) | \
PIN_DRxR_DISABLE(GPIOA_UART0_TX) | \
PIN_DRxR_DISABLE(GPIOA_PIN2) | \
PIN_DRxR_DISABLE(GPIOA_PIN3) | \
PIN_DRxR_DISABLE(GPIOA_PIN4) | \
PIN_DRxR_DISABLE(GPIOA_PIN5) | \
PIN_DRxR_DISABLE(GPIOA_PIN6) | \
PIN_DRxR_DISABLE(GPIOA_PIN7))
#define VAL_GPIOA_SLR (PIN_SLR_DISABLE(GPIOA_UART0_RX) | \
PIN_SLR_DISABLE(GPIOA_UART0_TX) | \
PIN_SLR_DISABLE(GPIOA_PIN2) | \
PIN_SLR_DISABLE(GPIOA_PIN3) | \
PIN_SLR_DISABLE(GPIOA_PIN4) | \
PIN_SLR_DISABLE(GPIOA_PIN5) | \
PIN_SLR_DISABLE(GPIOA_PIN6) | \
PIN_SLR_DISABLE(GPIOA_PIN7))
#define VAL_GPIOA_PCTL (PIN_PCTL_MODE(GPIOA_UART0_RX, 1) | \
PIN_PCTL_MODE(GPIOA_UART0_TX, 1) | \
PIN_PCTL_MODE(GPIOA_PIN2, 0) | \
PIN_PCTL_MODE(GPIOA_PIN3, 0) | \
PIN_PCTL_MODE(GPIOA_PIN4, 0) | \
PIN_PCTL_MODE(GPIOA_PIN5, 0) | \
PIN_PCTL_MODE(GPIOA_PIN6, 0) | \
PIN_PCTL_MODE(GPIOA_PIN7, 0))
/*
* GPIOB Setup:
*
* PB0 - PIN0 ()
* PB1 - PIN1 ()
* PB2 - I2C0_SCL (alternate 3)
* PB3 - I2C0_SDA (alternate 3)
* PB4 - PIN4 ()
* PB5 - PIN5 ()
* PB6 - PIN6 ()
* PB7 - PIN7 ()
*/
#define VAL_GPIOB_DATA (PIN_DATA_LOW(GPIOB_PIN0) | \
PIN_DATA_LOW(GPIOB_PIN1) | \
PIN_DATA_LOW(GPIOB_I2C0_SCL) | \
PIN_DATA_LOW(GPIOB_I2C0_SDA) | \
PIN_DATA_LOW(GPIOB_PIN4) | \
PIN_DATA_LOW(GPIOB_PIN5) | \
PIN_DATA_LOW(GPIOB_PIN6) | \
PIN_DATA_LOW(GPIOB_PIN7))
#define VAL_GPIOB_DIR (PIN_DIR_IN(GPIOB_PIN0) | \
PIN_DIR_IN(GPIOB_PIN1) | \
PIN_DIR_IN(GPIOB_I2C0_SCL) | \
PIN_DIR_IN(GPIOB_I2C0_SDA) | \
PIN_DIR_IN(GPIOB_PIN4) | \
PIN_DIR_IN(GPIOB_PIN5) | \
PIN_DIR_IN(GPIOB_PIN6) | \
PIN_DIR_IN(GPIOB_PIN7))
#define VAL_GPIOB_AFSEL (PIN_AFSEL_GPIO(GPIOB_PIN0) | \
PIN_AFSEL_GPIO(GPIOB_PIN1) | \
PIN_AFSEL_ALTERNATE(GPIOB_I2C0_SCL) | \
PIN_AFSEL_ALTERNATE(GPIOB_I2C0_SDA) | \
PIN_AFSEL_GPIO(GPIOB_PIN4) | \
PIN_AFSEL_GPIO(GPIOB_PIN5) | \
PIN_AFSEL_GPIO(GPIOB_PIN6) | \
PIN_AFSEL_GPIO(GPIOB_PIN7))
#define VAL_GPIOB_DR2R (PIN_DRxR_ENABLE(GPIOB_PIN0) | \
PIN_DRxR_ENABLE(GPIOB_PIN1) | \
PIN_DRxR_ENABLE(GPIOB_I2C0_SCL) | \
PIN_DRxR_ENABLE(GPIOB_I2C0_SDA) | \
PIN_DRxR_ENABLE(GPIOB_PIN4) | \
PIN_DRxR_ENABLE(GPIOB_PIN5) | \
PIN_DRxR_ENABLE(GPIOB_PIN6) | \
PIN_DRxR_ENABLE(GPIOB_PIN7))
#define VAL_GPIOB_DR4R (PIN_DRxR_DISABLE(GPIOB_PIN0) | \
PIN_DRxR_DISABLE(GPIOB_PIN1) | \
PIN_DRxR_DISABLE(GPIOB_I2C0_SCL) | \
PIN_DRxR_DISABLE(GPIOB_I2C0_SDA) | \
PIN_DRxR_DISABLE(GPIOB_PIN4) | \
PIN_DRxR_DISABLE(GPIOB_PIN5) | \
PIN_DRxR_DISABLE(GPIOB_PIN6) | \
PIN_DRxR_DISABLE(GPIOB_PIN7))
#define VAL_GPIOB_DR8R (PIN_DRxR_DISABLE(GPIOB_PIN0) | \
PIN_DRxR_DISABLE(GPIOB_PIN1) | \
PIN_DRxR_DISABLE(GPIOB_I2C0_SCL) | \
PIN_DRxR_DISABLE(GPIOB_I2C0_SDA) | \
PIN_DRxR_DISABLE(GPIOB_PIN4) | \
PIN_DRxR_DISABLE(GPIOB_PIN5) | \
PIN_DRxR_DISABLE(GPIOB_PIN6) | \
PIN_DRxR_DISABLE(GPIOB_PIN7))
#define VAL_GPIOB_ODR (PIN_ODR_DISABLE(GPIOB_PIN0) | \
PIN_ODR_DISABLE(GPIOB_PIN1) | \
PIN_ODR_DISABLE(GPIOB_I2C0_SCL) | \
PIN_ODR_ENABLE(GPIOB_I2C0_SDA) | \
PIN_ODR_DISABLE(GPIOB_PIN4) | \
PIN_ODR_DISABLE(GPIOB_PIN5) | \
PIN_ODR_DISABLE(GPIOB_PIN6) | \
PIN_ODR_DISABLE(GPIOB_PIN7))
#define VAL_GPIOB_PUR (PIN_PxR_DISABLE(GPIOB_PIN0) | \
PIN_PxR_DISABLE(GPIOB_PIN1) | \
PIN_PxR_DISABLE(GPIOB_I2C0_SCL) | \
PIN_PxR_DISABLE(GPIOB_I2C0_SDA) | \
PIN_PxR_DISABLE(GPIOB_PIN4) | \
PIN_PxR_DISABLE(GPIOB_PIN5) | \
PIN_PxR_DISABLE(GPIOB_PIN6) | \
PIN_PxR_DISABLE(GPIOB_PIN7))
#define VAL_GPIOB_PDR (PIN_PxR_DISABLE(GPIOB_PIN0) | \
PIN_PxR_DISABLE(GPIOB_PIN1) | \
PIN_PxR_DISABLE(GPIOB_I2C0_SCL) | \
PIN_PxR_DISABLE(GPIOB_I2C0_SDA) | \
PIN_PxR_DISABLE(GPIOB_PIN4) | \
PIN_PxR_DISABLE(GPIOB_PIN5) | \
PIN_PxR_DISABLE(GPIOB_PIN6) | \
PIN_PxR_DISABLE(GPIOB_PIN7))
#define VAL_GPIOB_SLR (PIN_SLR_DISABLE(GPIOB_PIN0) | \
PIN_SLR_DISABLE(GPIOB_PIN1) | \
PIN_SLR_DISABLE(GPIOB_I2C0_SCL) | \
PIN_SLR_DISABLE(GPIOB_I2C0_SDA) | \
PIN_SLR_DISABLE(GPIOB_PIN4) | \
PIN_SLR_DISABLE(GPIOB_PIN5) | \
PIN_SLR_DISABLE(GPIOB_PIN6) | \
PIN_SLR_DISABLE(GPIOB_PIN7))
#define VAL_GPIOB_DEN (PIN_DEN_ENABLE(GPIOB_PIN0) | \
PIN_DEN_ENABLE(GPIOB_PIN1) | \
PIN_DEN_ENABLE(GPIOB_I2C0_SCL) | \
PIN_DEN_ENABLE(GPIOB_I2C0_SDA) | \
PIN_DEN_ENABLE(GPIOB_PIN4) | \
PIN_DEN_ENABLE(GPIOB_PIN5) | \
PIN_DEN_ENABLE(GPIOB_PIN6) | \
PIN_DEN_ENABLE(GPIOB_PIN7))
#define VAL_GPIOB_AMSEL (PIN_AMSEL_DISABLE(GPIOB_PIN0) | \
PIN_AMSEL_DISABLE(GPIOB_PIN1) | \
PIN_AMSEL_DISABLE(GPIOB_I2C0_SCL) | \
PIN_AMSEL_DISABLE(GPIOB_I2C0_SDA))
#define VAL_GPIOB_PCTL (PIN_PCTL_MODE(GPIOB_PIN0, 0) | \
PIN_PCTL_MODE(GPIOB_PIN1, 0) | \
PIN_PCTL_MODE(GPIOB_I2C0_SCL, 3) | \
PIN_PCTL_MODE(GPIOB_I2C0_SDA, 3) | \
PIN_PCTL_MODE(GPIOB_PIN4, 0) | \
PIN_PCTL_MODE(GPIOB_PIN5, 0) | \
PIN_PCTL_MODE(GPIOB_PIN6, 0) | \
PIN_PCTL_MODE(GPIOB_PIN7, 0))
/*
* GPIOC Setup:
*
* PC0 - TCK_SWCLK (alternate 1)
* PC1 - TMS_SWDIO (alternate 1)
* PC2 - TDI (alternate 1)
* PC3 - TDO_SWO (alternate 1)
* PC4 - PIN4 ()
* PC5 - PIN5 ()
* PC6 - PIN6 ()
* PC7 - PIN7 ()
*/
#define VAL_GPIOC_DATA (PIN_DATA_LOW(GPIOC_TCK_SWCLK) | \
PIN_DATA_LOW(GPIOC_TMS_SWDIO) | \
PIN_DATA_LOW(GPIOC_TDI) | \
PIN_DATA_LOW(GPIOC_TDO_SWO) | \
PIN_DATA_LOW(GPIOC_PIN4) | \
PIN_DATA_LOW(GPIOC_PIN5) | \
PIN_DATA_LOW(GPIOC_PIN6) | \
PIN_DATA_LOW(GPIOC_PIN7))
#define VAL_GPIOC_DIR (PIN_DIR_IN(GPIOC_TCK_SWCLK) | \
PIN_DIR_IN(GPIOC_TMS_SWDIO) | \
PIN_DIR_IN(GPIOC_TDI) | \
PIN_DIR_OUT(GPIOC_TDO_SWO) | \
PIN_DIR_IN(GPIOC_PIN4) | \
PIN_DIR_IN(GPIOC_PIN5) | \
PIN_DIR_IN(GPIOC_PIN6) | \
PIN_DIR_IN(GPIOC_PIN7))
#define VAL_GPIOC_AFSEL (PIN_AFSEL_ALTERNATE(GPIOC_TCK_SWCLK) | \
PIN_AFSEL_ALTERNATE(GPIOC_TMS_SWDIO) | \
PIN_AFSEL_ALTERNATE(GPIOC_TDI) | \
PIN_AFSEL_ALTERNATE(GPIOC_TDO_SWO) | \
PIN_AFSEL_GPIO(GPIOC_PIN4) | \
PIN_AFSEL_GPIO(GPIOC_PIN5) | \
PIN_AFSEL_GPIO(GPIOC_PIN6) | \
PIN_AFSEL_GPIO(GPIOC_PIN7))
#define VAL_GPIOC_DR2R (PIN_DRxR_ENABLE(GPIOC_TCK_SWCLK) | \
PIN_DRxR_ENABLE(GPIOC_TMS_SWDIO) | \
PIN_DRxR_ENABLE(GPIOC_TDI) | \
PIN_DRxR_ENABLE(GPIOC_TDO_SWO) | \
PIN_DRxR_ENABLE(GPIOC_PIN4) | \
PIN_DRxR_ENABLE(GPIOC_PIN5) | \
PIN_DRxR_ENABLE(GPIOC_PIN6) | \
PIN_DRxR_ENABLE(GPIOC_PIN7))
#define VAL_GPIOC_DR4R (PIN_DRxR_DISABLE(GPIOC_TCK_SWCLK) | \
PIN_DRxR_DISABLE(GPIOC_TMS_SWDIO) | \
PIN_DRxR_DISABLE(GPIOC_TDI) | \
PIN_DRxR_DISABLE(GPIOC_TDO_SWO) | \
PIN_DRxR_DISABLE(GPIOC_PIN4) | \
PIN_DRxR_DISABLE(GPIOC_PIN5) | \
PIN_DRxR_DISABLE(GPIOC_PIN6) | \
PIN_DRxR_DISABLE(GPIOC_PIN7))
#define VAL_GPIOC_DR8R (PIN_DRxR_DISABLE(GPIOC_TCK_SWCLK) | \
PIN_DRxR_DISABLE(GPIOC_TMS_SWDIO) | \
PIN_DRxR_DISABLE(GPIOC_TDI) | \
PIN_DRxR_DISABLE(GPIOC_TDO_SWO) | \
PIN_DRxR_DISABLE(GPIOC_PIN4) | \
PIN_DRxR_DISABLE(GPIOC_PIN5) | \
PIN_DRxR_DISABLE(GPIOC_PIN6) | \
PIN_DRxR_DISABLE(GPIOC_PIN7))
#define VAL_GPIOC_ODR (PIN_ODR_DISABLE(GPIOC_TCK_SWCLK) | \
PIN_ODR_DISABLE(GPIOC_TMS_SWDIO) | \
PIN_ODR_DISABLE(GPIOC_TDI) | \
PIN_ODR_DISABLE(GPIOC_TDO_SWO) | \
PIN_ODR_DISABLE(GPIOC_PIN4) | \
PIN_ODR_DISABLE(GPIOC_PIN5) | \
PIN_ODR_DISABLE(GPIOC_PIN6) | \
PIN_ODR_DISABLE(GPIOC_PIN7))
#define VAL_GPIOC_PUR (PIN_PxR_DISABLE(GPIOC_TCK_SWCLK) | \
PIN_PxR_DISABLE(GPIOC_TMS_SWDIO) | \
PIN_PxR_DISABLE(GPIOC_TDI) | \
PIN_PxR_DISABLE(GPIOC_TDO_SWO) | \
PIN_PxR_DISABLE(GPIOC_PIN4) | \
PIN_PxR_DISABLE(GPIOC_PIN5) | \
PIN_PxR_DISABLE(GPIOC_PIN6) | \
PIN_PxR_DISABLE(GPIOC_PIN7))
#define VAL_GPIOC_PDR (PIN_PxR_DISABLE(GPIOC_TCK_SWCLK) | \
PIN_PxR_DISABLE(GPIOC_TMS_SWDIO) | \
PIN_PxR_DISABLE(GPIOC_TDI) | \
PIN_PxR_DISABLE(GPIOC_TDO_SWO) | \
PIN_PxR_DISABLE(GPIOC_PIN4) | \
PIN_PxR_DISABLE(GPIOC_PIN5) | \
PIN_PxR_DISABLE(GPIOC_PIN6) | \
PIN_PxR_DISABLE(GPIOC_PIN7))
#define VAL_GPIOC_SLR (PIN_SLR_DISABLE(GPIOC_TCK_SWCLK) | \
PIN_SLR_DISABLE(GPIOC_TMS_SWDIO) | \
PIN_SLR_DISABLE(GPIOC_TDI) | \
PIN_SLR_DISABLE(GPIOC_TDO_SWO) | \
PIN_SLR_DISABLE(GPIOC_PIN4) | \
PIN_SLR_DISABLE(GPIOC_PIN5) | \
PIN_SLR_DISABLE(GPIOC_PIN6) | \
PIN_SLR_DISABLE(GPIOC_PIN7))
#define VAL_GPIOC_DEN (PIN_DEN_ENABLE(GPIOC_TCK_SWCLK) | \
PIN_DEN_ENABLE(GPIOC_TMS_SWDIO) | \
PIN_DEN_ENABLE(GPIOC_TDI) | \
PIN_DEN_ENABLE(GPIOC_TDO_SWO) | \
PIN_DEN_ENABLE(GPIOC_PIN4) | \
PIN_DEN_ENABLE(GPIOC_PIN5) | \
PIN_DEN_ENABLE(GPIOC_PIN6) | \
PIN_DEN_ENABLE(GPIOC_PIN7))
#define VAL_GPIOC_AMSEL (PIN_AMSEL_DISABLE(GPIOC_TCK_SWCLK) | \
PIN_AMSEL_DISABLE(GPIOC_TMS_SWDIO) | \
PIN_AMSEL_DISABLE(GPIOC_TDI) | \
PIN_AMSEL_DISABLE(GPIOC_TDO_SWO))
#define VAL_GPIOC_PCTL (PIN_PCTL_MODE(GPIOC_TCK_SWCLK, 1) | \
PIN_PCTL_MODE(GPIOC_TMS_SWDIO, 1) | \
PIN_PCTL_MODE(GPIOC_TDI, 1) | \
PIN_PCTL_MODE(GPIOC_TDO_SWO, 1) | \
PIN_PCTL_MODE(GPIOC_PIN4, 0) | \
PIN_PCTL_MODE(GPIOC_PIN5, 0) | \
PIN_PCTL_MODE(GPIOC_PIN6, 0) | \
PIN_PCTL_MODE(GPIOC_PIN7, 0))
/*
* GPIOD Setup:
*
* PD0 - PIN0 ()
* PD1 - PIN1 ()
* PD2 - PIN2 ()
* PD3 - PIN3 ()
* PD4 - PIN4 ()
* PD5 - PIN5 ()
* PD6 - PIN6 ()
* PD7 - PIN7 ()
*/
#define VAL_GPIOD_DATA (PIN_DATA_LOW(GPIOD_PIN0) | \
PIN_DATA_LOW(GPIOD_PIN1) | \
PIN_DATA_LOW(GPIOD_PIN2) | \
PIN_DATA_LOW(GPIOD_PIN3) | \
PIN_DATA_LOW(GPIOD_PIN4) | \
PIN_DATA_LOW(GPIOD_PIN5) | \
PIN_DATA_LOW(GPIOD_PIN6) | \
PIN_DATA_LOW(GPIOD_PIN7))
#define VAL_GPIOD_DIR (PIN_DIR_IN(GPIOD_PIN0) | \
PIN_DIR_IN(GPIOD_PIN1) | \
PIN_DIR_IN(GPIOD_PIN2) | \
PIN_DIR_IN(GPIOD_PIN3) | \
PIN_DIR_IN(GPIOD_PIN4) | \
PIN_DIR_IN(GPIOD_PIN5) | \
PIN_DIR_IN(GPIOD_PIN6) | \
PIN_DIR_IN(GPIOD_PIN7))
#define VAL_GPIOD_AFSEL (PIN_AFSEL_GPIO(GPIOD_PIN0) | \
PIN_AFSEL_GPIO(GPIOD_PIN1) | \
PIN_AFSEL_GPIO(GPIOD_PIN2) | \
PIN_AFSEL_GPIO(GPIOD_PIN3) | \
PIN_AFSEL_GPIO(GPIOD_PIN4) | \
PIN_AFSEL_GPIO(GPIOD_PIN5) | \
PIN_AFSEL_GPIO(GPIOD_PIN6) | \
PIN_AFSEL_GPIO(GPIOD_PIN7))
#define VAL_GPIOD_DR2R (PIN_DRxR_ENABLE(GPIOD_PIN0) | \
PIN_DRxR_ENABLE(GPIOD_PIN1) | \
PIN_DRxR_ENABLE(GPIOD_PIN2) | \
PIN_DRxR_ENABLE(GPIOD_PIN3) | \
PIN_DRxR_ENABLE(GPIOD_PIN4) | \
PIN_DRxR_ENABLE(GPIOD_PIN5) | \
PIN_DRxR_ENABLE(GPIOD_PIN6) | \
PIN_DRxR_ENABLE(GPIOD_PIN7))
#define VAL_GPIOD_DR4R (PIN_DRxR_DISABLE(GPIOD_PIN0) | \
PIN_DRxR_DISABLE(GPIOD_PIN1) | \
PIN_DRxR_DISABLE(GPIOD_PIN2) | \
PIN_DRxR_DISABLE(GPIOD_PIN3) | \
PIN_DRxR_DISABLE(GPIOD_PIN4) | \
PIN_DRxR_DISABLE(GPIOD_PIN5) | \
PIN_DRxR_DISABLE(GPIOD_PIN6) | \
PIN_DRxR_DISABLE(GPIOD_PIN7))
#define VAL_GPIOD_DR8R (PIN_DRxR_DISABLE(GPIOD_PIN0) | \
PIN_DRxR_DISABLE(GPIOD_PIN1) | \
PIN_DRxR_DISABLE(GPIOD_PIN2) | \
PIN_DRxR_DISABLE(GPIOD_PIN3) | \
PIN_DRxR_DISABLE(GPIOD_PIN4) | \
PIN_DRxR_DISABLE(GPIOD_PIN5) | \
PIN_DRxR_DISABLE(GPIOD_PIN6) | \
PIN_DRxR_DISABLE(GPIOD_PIN7))
#define VAL_GPIOD_ODR (PIN_ODR_DISABLE(GPIOD_PIN0) | \
PIN_ODR_DISABLE(GPIOD_PIN1) | \
PIN_ODR_DISABLE(GPIOD_PIN2) | \
PIN_ODR_DISABLE(GPIOD_PIN3) | \
PIN_ODR_DISABLE(GPIOD_PIN4) | \
PIN_ODR_DISABLE(GPIOD_PIN5) | \
PIN_ODR_DISABLE(GPIOD_PIN6) | \
PIN_ODR_DISABLE(GPIOD_PIN7))
#define VAL_GPIOD_PUR (PIN_PxR_DISABLE(GPIOD_PIN0) | \
PIN_PxR_DISABLE(GPIOD_PIN1) | \
PIN_PxR_DISABLE(GPIOD_PIN2) | \
PIN_PxR_DISABLE(GPIOD_PIN3) | \
PIN_PxR_DISABLE(GPIOD_PIN4) | \
PIN_PxR_DISABLE(GPIOD_PIN5) | \
PIN_PxR_DISABLE(GPIOD_PIN6) | \
PIN_PxR_DISABLE(GPIOD_PIN7))
#define VAL_GPIOD_PDR (PIN_PxR_DISABLE(GPIOD_PIN0) | \
PIN_PxR_DISABLE(GPIOD_PIN1) | \
PIN_PxR_DISABLE(GPIOD_PIN2) | \
PIN_PxR_DISABLE(GPIOD_PIN3) | \
PIN_PxR_DISABLE(GPIOD_PIN4) | \
PIN_PxR_DISABLE(GPIOD_PIN5) | \
PIN_PxR_DISABLE(GPIOD_PIN6) | \
PIN_PxR_DISABLE(GPIOD_PIN7))
#define VAL_GPIOD_SLR (PIN_SLR_DISABLE(GPIOD_PIN0) | \
PIN_SLR_DISABLE(GPIOD_PIN1) | \
PIN_SLR_DISABLE(GPIOD_PIN2) | \
PIN_SLR_DISABLE(GPIOD_PIN3) | \
PIN_SLR_DISABLE(GPIOD_PIN4) | \
PIN_SLR_DISABLE(GPIOD_PIN5) | \
PIN_SLR_DISABLE(GPIOD_PIN6) | \
PIN_SLR_DISABLE(GPIOD_PIN7))
#define VAL_GPIOD_DEN (PIN_DEN_ENABLE(GPIOD_PIN0) | \
PIN_DEN_ENABLE(GPIOD_PIN1) | \
PIN_DEN_ENABLE(GPIOD_PIN2) | \
PIN_DEN_ENABLE(GPIOD_PIN3) | \
PIN_DEN_ENABLE(GPIOD_PIN4) | \
PIN_DEN_ENABLE(GPIOD_PIN5) | \
PIN_DEN_ENABLE(GPIOD_PIN6) | \
PIN_DEN_ENABLE(GPIOD_PIN7))
#define VAL_GPIOD_AMSEL (PIN_AMSEL_DISABLE(GPIOD_PIN0) | \
PIN_AMSEL_DISABLE(GPIOD_PIN1) | \
PIN_AMSEL_DISABLE(GPIOD_PIN2) | \
PIN_AMSEL_DISABLE(GPIOD_PIN3))
#define VAL_GPIOD_PCTL (PIN_PCTL_MODE(GPIOD_PIN0, 0) | \
PIN_PCTL_MODE(GPIOD_PIN1, 0) | \
PIN_PCTL_MODE(GPIOD_PIN2, 0) | \
PIN_PCTL_MODE(GPIOD_PIN3, 0) | \
PIN_PCTL_MODE(GPIOD_PIN4, 0) | \
PIN_PCTL_MODE(GPIOD_PIN5, 0) | \
PIN_PCTL_MODE(GPIOD_PIN6, 0) | \
PIN_PCTL_MODE(GPIOD_PIN7, 0))
/*
* GPIOE Setup:
*
* PE0 - PIN0 ()
* PE1 - PIN1 ()
* PE2 - PIN2 ()
* PE3 - PIN3 ()
* PE4 - PIN4 ()
* PE5 - PIN5 ()
* PE6 - PIN6 ()
* PE7 - PIN7 ()
*/
#define VAL_GPIOE_DATA (PIN_DATA_LOW(GPIOE_PIN0) | \
PIN_DATA_LOW(GPIOE_PIN1) | \
PIN_DATA_LOW(GPIOE_PIN2) | \
PIN_DATA_LOW(GPIOE_PIN3) | \
PIN_DATA_LOW(GPIOE_PIN4) | \
PIN_DATA_LOW(GPIOE_PIN5) | \
PIN_DATA_LOW(GPIOE_PIN6) | \
PIN_DATA_LOW(GPIOE_PIN7))
#define VAL_GPIOE_DIR (PIN_DIR_IN(GPIOE_PIN0) | \
PIN_DIR_IN(GPIOE_PIN1) | \
PIN_DIR_IN(GPIOE_PIN2) | \
PIN_DIR_IN(GPIOE_PIN3) | \
PIN_DIR_IN(GPIOE_PIN4) | \
PIN_DIR_IN(GPIOE_PIN5) | \
PIN_DIR_IN(GPIOE_PIN6) | \
PIN_DIR_IN(GPIOE_PIN7))
#define VAL_GPIOE_AFSEL (PIN_AFSEL_GPIO(GPIOE_PIN0) | \
PIN_AFSEL_GPIO(GPIOE_PIN1) | \
PIN_AFSEL_GPIO(GPIOE_PIN2) | \
PIN_AFSEL_GPIO(GPIOE_PIN3) | \
PIN_AFSEL_GPIO(GPIOE_PIN4) | \
PIN_AFSEL_GPIO(GPIOE_PIN5) | \
PIN_AFSEL_GPIO(GPIOE_PIN6) | \
PIN_AFSEL_GPIO(GPIOE_PIN7))
#define VAL_GPIOE_DR2R (PIN_DRxR_ENABLE(GPIOE_PIN0) | \
PIN_DRxR_ENABLE(GPIOE_PIN1) | \
PIN_DRxR_ENABLE(GPIOE_PIN2) | \
PIN_DRxR_ENABLE(GPIOE_PIN3) | \
PIN_DRxR_ENABLE(GPIOE_PIN4) | \
PIN_DRxR_ENABLE(GPIOE_PIN5) | \
PIN_DRxR_ENABLE(GPIOE_PIN6) | \
PIN_DRxR_ENABLE(GPIOE_PIN7))
#define VAL_GPIOE_DR4R (PIN_DRxR_DISABLE(GPIOE_PIN0) | \
PIN_DRxR_DISABLE(GPIOE_PIN1) | \
PIN_DRxR_DISABLE(GPIOE_PIN2) | \
PIN_DRxR_DISABLE(GPIOE_PIN3) | \
PIN_DRxR_DISABLE(GPIOE_PIN4) | \
PIN_DRxR_DISABLE(GPIOE_PIN5) | \
PIN_DRxR_DISABLE(GPIOE_PIN6) | \
PIN_DRxR_DISABLE(GPIOE_PIN7))
#define VAL_GPIOE_DR8R (PIN_DRxR_DISABLE(GPIOE_PIN0) | \
PIN_DRxR_DISABLE(GPIOE_PIN1) | \
PIN_DRxR_DISABLE(GPIOE_PIN2) | \
PIN_DRxR_DISABLE(GPIOE_PIN3) | \
PIN_DRxR_DISABLE(GPIOE_PIN4) | \
PIN_DRxR_DISABLE(GPIOE_PIN5) | \
PIN_DRxR_DISABLE(GPIOE_PIN6) | \
PIN_DRxR_DISABLE(GPIOE_PIN7))
#define VAL_GPIOE_ODR (PIN_ODR_DISABLE(GPIOE_PIN0) | \
PIN_ODR_DISABLE(GPIOE_PIN1) | \
PIN_ODR_DISABLE(GPIOE_PIN2) | \
PIN_ODR_DISABLE(GPIOE_PIN3) | \
PIN_ODR_DISABLE(GPIOE_PIN4) | \
PIN_ODR_DISABLE(GPIOE_PIN5) | \
PIN_ODR_DISABLE(GPIOE_PIN6) | \
PIN_ODR_DISABLE(GPIOE_PIN7))
#define VAL_GPIOE_PUR (PIN_PxR_DISABLE(GPIOE_PIN0) | \
PIN_PxR_DISABLE(GPIOE_PIN1) | \
PIN_PxR_DISABLE(GPIOE_PIN2) | \
PIN_PxR_DISABLE(GPIOE_PIN3) | \
PIN_PxR_DISABLE(GPIOE_PIN4) | \
PIN_PxR_DISABLE(GPIOE_PIN5) | \
PIN_PxR_DISABLE(GPIOE_PIN6) | \
PIN_PxR_DISABLE(GPIOE_PIN7))
#define VAL_GPIOE_PDR (PIN_PxR_DISABLE(GPIOE_PIN0) | \
PIN_PxR_DISABLE(GPIOE_PIN1) | \
PIN_PxR_DISABLE(GPIOE_PIN2) | \
PIN_PxR_DISABLE(GPIOE_PIN3) | \
PIN_PxR_DISABLE(GPIOE_PIN4) | \
PIN_PxR_DISABLE(GPIOE_PIN5) | \
PIN_PxR_DISABLE(GPIOE_PIN6) | \
PIN_PxR_DISABLE(GPIOE_PIN7))
#define VAL_GPIOE_SLR (PIN_SLR_DISABLE(GPIOE_PIN0) | \
PIN_SLR_DISABLE(GPIOE_PIN1) | \
PIN_SLR_DISABLE(GPIOE_PIN2) | \
PIN_SLR_DISABLE(GPIOE_PIN3) | \
PIN_SLR_DISABLE(GPIOE_PIN4) | \
PIN_SLR_DISABLE(GPIOE_PIN5) | \
PIN_SLR_DISABLE(GPIOE_PIN6) | \
PIN_SLR_DISABLE(GPIOE_PIN7))
#define VAL_GPIOE_DEN (PIN_DEN_ENABLE(GPIOE_PIN0) | \
PIN_DEN_ENABLE(GPIOE_PIN1) | \
PIN_DEN_ENABLE(GPIOE_PIN2) | \
PIN_DEN_ENABLE(GPIOE_PIN3) | \
PIN_DEN_ENABLE(GPIOE_PIN4) | \
PIN_DEN_ENABLE(GPIOE_PIN5) | \
PIN_DEN_ENABLE(GPIOE_PIN6) | \
PIN_DEN_ENABLE(GPIOE_PIN7))
#define VAL_GPIOE_AMSEL (PIN_AMSEL_DISABLE(GPIOE_PIN0) | \
PIN_AMSEL_DISABLE(GPIOE_PIN1) | \
PIN_AMSEL_DISABLE(GPIOE_PIN2) | \
PIN_AMSEL_DISABLE(GPIOE_PIN3))
#define VAL_GPIOE_PCTL (PIN_PCTL_MODE(GPIOE_PIN0, 0) | \
PIN_PCTL_MODE(GPIOE_PIN1, 0) | \
PIN_PCTL_MODE(GPIOE_PIN2, 0) | \
PIN_PCTL_MODE(GPIOE_PIN3, 0) | \
PIN_PCTL_MODE(GPIOE_PIN4, 0) | \
PIN_PCTL_MODE(GPIOE_PIN5, 0) | \
PIN_PCTL_MODE(GPIOE_PIN6, 0) | \
PIN_PCTL_MODE(GPIOE_PIN7, 0))
/*
* GPIOF Setup:
*
* PF0 - SW2 ()
* PF1 - LED_RED ()
* PF2 - LED_BLUE ()
* PF3 - LED_GREEN ()
* PF4 - SW1 ()
* PF5 - PIN5 ()
* PF6 - PIN6 ()
* PF7 - PIN7 ()
*/
#define VAL_GPIOF_DATA (PIN_DATA_LOW(GPIOF_SW2) | \
PIN_DATA_LOW(GPIOF_LED_RED) | \
PIN_DATA_LOW(GPIOF_LED_BLUE) | \
PIN_DATA_LOW(GPIOF_LED_GREEN) | \
PIN_DATA_LOW(GPIOF_SW1) | \
PIN_DATA_LOW(GPIOF_PIN5) | \
PIN_DATA_LOW(GPIOF_PIN6) | \
PIN_DATA_LOW(GPIOF_PIN7))
#define VAL_GPIOF_DIR (PIN_DIR_IN(GPIOF_SW2) | \
PIN_DIR_OUT(GPIOF_LED_RED) | \
PIN_DIR_OUT(GPIOF_LED_BLUE) | \
PIN_DIR_OUT(GPIOF_LED_GREEN) | \
PIN_DIR_IN(GPIOF_SW1) | \
PIN_DIR_IN(GPIOF_PIN5) | \
PIN_DIR_IN(GPIOF_PIN6) | \
PIN_DIR_IN(GPIOF_PIN7))
#define VAL_GPIOF_AFSEL (PIN_AFSEL_GPIO(GPIOF_SW2) | \
PIN_AFSEL_GPIO(GPIOF_LED_RED) | \
PIN_AFSEL_GPIO(GPIOF_LED_BLUE) | \
PIN_AFSEL_GPIO(GPIOF_LED_GREEN) | \
PIN_AFSEL_GPIO(GPIOF_SW1) | \
PIN_AFSEL_GPIO(GPIOF_PIN5) | \
PIN_AFSEL_GPIO(GPIOF_PIN6) | \
PIN_AFSEL_GPIO(GPIOF_PIN7))
#define VAL_GPIOF_DR2R (PIN_DRxR_ENABLE(GPIOF_SW2) | \
PIN_DRxR_ENABLE(GPIOF_LED_RED) | \
PIN_DRxR_ENABLE(GPIOF_LED_BLUE) | \
PIN_DRxR_ENABLE(GPIOF_LED_GREEN) | \
PIN_DRxR_ENABLE(GPIOF_SW1) | \
PIN_DRxR_ENABLE(GPIOF_PIN5) | \
PIN_DRxR_ENABLE(GPIOF_PIN6) | \
PIN_DRxR_ENABLE(GPIOF_PIN7))
#define VAL_GPIOF_DR4R (PIN_DRxR_DISABLE(GPIOF_SW2) | \
PIN_DRxR_DISABLE(GPIOF_LED_RED) | \
PIN_DRxR_DISABLE(GPIOF_LED_BLUE) | \
PIN_DRxR_DISABLE(GPIOF_LED_GREEN) | \
PIN_DRxR_DISABLE(GPIOF_SW1) | \
PIN_DRxR_DISABLE(GPIOF_PIN5) | \
PIN_DRxR_DISABLE(GPIOF_PIN6) | \
PIN_DRxR_DISABLE(GPIOF_PIN7))
#define VAL_GPIOF_DR8R (PIN_DRxR_DISABLE(GPIOF_SW2) | \
PIN_DRxR_DISABLE(GPIOF_LED_RED) | \
PIN_DRxR_DISABLE(GPIOF_LED_BLUE) | \
PIN_DRxR_DISABLE(GPIOF_LED_GREEN) | \
PIN_DRxR_DISABLE(GPIOF_SW1) | \
PIN_DRxR_DISABLE(GPIOF_PIN5) | \
PIN_DRxR_DISABLE(GPIOF_PIN6) | \
PIN_DRxR_DISABLE(GPIOF_PIN7))
#define VAL_GPIOF_ODR (PIN_ODR_DISABLE(GPIOF_SW2) | \
PIN_ODR_DISABLE(GPIOF_LED_RED) | \
PIN_ODR_DISABLE(GPIOF_LED_BLUE) | \
PIN_ODR_DISABLE(GPIOF_LED_GREEN) | \
PIN_ODR_DISABLE(GPIOF_SW1) | \
PIN_ODR_DISABLE(GPIOF_PIN5) | \
PIN_ODR_DISABLE(GPIOF_PIN6) | \
PIN_ODR_DISABLE(GPIOF_PIN7))
#define VAL_GPIOF_PUR (PIN_PxR_ENABLE(GPIOF_SW2) | \
PIN_PxR_DISABLE(GPIOF_LED_RED) | \
PIN_PxR_DISABLE(GPIOF_LED_BLUE) | \
PIN_PxR_DISABLE(GPIOF_LED_GREEN) | \
PIN_PxR_ENABLE(GPIOF_SW1) | \
PIN_PxR_DISABLE(GPIOF_PIN5) | \
PIN_PxR_DISABLE(GPIOF_PIN6) | \
PIN_PxR_DISABLE(GPIOF_PIN7))
#define VAL_GPIOF_PDR (PIN_PxR_DISABLE(GPIOF_SW2) | \
PIN_PxR_DISABLE(GPIOF_LED_RED) | \
PIN_PxR_DISABLE(GPIOF_LED_BLUE) | \
PIN_PxR_DISABLE(GPIOF_LED_GREEN) | \
PIN_PxR_DISABLE(GPIOF_SW1) | \
PIN_PxR_DISABLE(GPIOF_PIN5) | \
PIN_PxR_DISABLE(GPIOF_PIN6) | \
PIN_PxR_DISABLE(GPIOF_PIN7))
#define VAL_GPIOF_SLR (PIN_SLR_DISABLE(GPIOF_SW2) | \
PIN_SLR_DISABLE(GPIOF_LED_RED) | \
PIN_SLR_DISABLE(GPIOF_LED_BLUE) | \
PIN_SLR_DISABLE(GPIOF_LED_GREEN) | \
PIN_SLR_DISABLE(GPIOF_SW1) | \
PIN_SLR_DISABLE(GPIOF_PIN5) | \
PIN_SLR_DISABLE(GPIOF_PIN6) | \
PIN_SLR_DISABLE(GPIOF_PIN7))
#define VAL_GPIOF_DEN (PIN_DEN_ENABLE(GPIOF_SW2) | \
PIN_DEN_ENABLE(GPIOF_LED_RED) | \
PIN_DEN_ENABLE(GPIOF_LED_BLUE) | \
PIN_DEN_ENABLE(GPIOF_LED_GREEN) | \
PIN_DEN_ENABLE(GPIOF_SW1) | \
PIN_DEN_ENABLE(GPIOF_PIN5) | \
PIN_DEN_ENABLE(GPIOF_PIN6) | \
PIN_DEN_ENABLE(GPIOF_PIN7))
#define VAL_GPIOF_AMSEL (PIN_AMSEL_DISABLE(GPIOF_SW2) | \
PIN_AMSEL_DISABLE(GPIOF_LED_RED) | \
PIN_AMSEL_DISABLE(GPIOF_LED_BLUE) | \
PIN_AMSEL_DISABLE(GPIOF_LED_GREEN))
#define VAL_GPIOF_PCTL (PIN_PCTL_MODE(GPIOF_SW2, 0) | \
PIN_PCTL_MODE(GPIOF_LED_RED, 0) | \
PIN_PCTL_MODE(GPIOF_LED_BLUE, 0) | \
PIN_PCTL_MODE(GPIOF_LED_GREEN, 0) | \
PIN_PCTL_MODE(GPIOF_SW1, 0) | \
PIN_PCTL_MODE(GPIOF_PIN5, 0) | \
PIN_PCTL_MODE(GPIOF_PIN6, 0) | \
PIN_PCTL_MODE(GPIOF_PIN7, 0))
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */

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os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk Normal file
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# List of all the board related files.
BOARDSRC = ${CHIBIOS}/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c
# Required include directories
BOARDINC = ${CHIBIOS}/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD

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os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c Normal file
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/*
Copyright (C) 2014 Marco Veeneman
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "hal.h"
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
#if HAL_USE_PAL || defined(__DOXYGEN__)
const PALConfig pal_default_config =
{
{VAL_GPIOA_DATA, VAL_GPIOA_DIR, VAL_GPIOA_AFSEL, VAL_GPIOA_DR2R,
VAL_GPIOA_DR4R, VAL_GPIOA_DR8R, VAL_GPIOA_ODR, VAL_GPIOA_PUR,
VAL_GPIOA_PDR, VAL_GPIOA_SLR, VAL_GPIOA_DEN, VAL_GPIOA_AMSEL,
VAL_GPIOA_PCTL},
{VAL_GPIOB_DATA, VAL_GPIOB_DIR, VAL_GPIOB_AFSEL, VAL_GPIOB_DR2R,
VAL_GPIOB_DR4R, VAL_GPIOB_DR8R, VAL_GPIOB_ODR, VAL_GPIOB_PUR,
VAL_GPIOB_PDR, VAL_GPIOB_SLR, VAL_GPIOB_DEN, VAL_GPIOB_AMSEL,
VAL_GPIOB_PCTL},
{VAL_GPIOC_DATA, VAL_GPIOC_DIR, VAL_GPIOC_AFSEL, VAL_GPIOC_DR2R,
VAL_GPIOC_DR4R, VAL_GPIOC_DR8R, VAL_GPIOC_ODR, VAL_GPIOC_PUR,
VAL_GPIOC_PDR, VAL_GPIOC_SLR, VAL_GPIOC_DEN, VAL_GPIOC_AMSEL,
VAL_GPIOC_PCTL},
{VAL_GPIOD_DATA, VAL_GPIOD_DIR, VAL_GPIOD_AFSEL, VAL_GPIOD_DR2R,
VAL_GPIOD_DR4R, VAL_GPIOD_DR8R, VAL_GPIOD_ODR, VAL_GPIOD_PUR,
VAL_GPIOD_PDR, VAL_GPIOD_SLR, VAL_GPIOD_DEN, VAL_GPIOD_AMSEL,
VAL_GPIOD_PCTL},
{VAL_GPIOE_DATA, VAL_GPIOE_DIR, VAL_GPIOE_AFSEL, VAL_GPIOE_DR2R,
VAL_GPIOE_DR4R, VAL_GPIOE_DR8R, VAL_GPIOE_ODR, VAL_GPIOE_PUR,
VAL_GPIOE_PDR, VAL_GPIOE_SLR, VAL_GPIOE_DEN, VAL_GPIOE_AMSEL,
VAL_GPIOE_PCTL},
{VAL_GPIOF_DATA, VAL_GPIOF_DIR, VAL_GPIOF_AFSEL, VAL_GPIOF_DR2R,
VAL_GPIOF_DR4R, VAL_GPIOF_DR8R, VAL_GPIOF_ODR, VAL_GPIOF_PUR,
VAL_GPIOF_PDR, VAL_GPIOF_SLR, VAL_GPIOF_DEN, VAL_GPIOF_AMSEL,
VAL_GPIOF_PCTL},
{VAL_GPIOG_DATA, VAL_GPIOG_DIR, VAL_GPIOG_AFSEL, VAL_GPIOG_DR2R,
VAL_GPIOG_DR4R, VAL_GPIOG_DR8R, VAL_GPIOG_ODR, VAL_GPIOG_PUR,
VAL_GPIOG_PDR, VAL_GPIOG_SLR, VAL_GPIOG_DEN, VAL_GPIOG_AMSEL,
VAL_GPIOG_PCTL},
{VAL_GPIOH_DATA, VAL_GPIOH_DIR, VAL_GPIOH_AFSEL, VAL_GPIOH_DR2R,
VAL_GPIOH_DR4R, VAL_GPIOH_DR8R, VAL_GPIOH_ODR, VAL_GPIOH_PUR,
VAL_GPIOH_PDR, VAL_GPIOH_SLR, VAL_GPIOH_DEN, VAL_GPIOH_AMSEL,
VAL_GPIOH_PCTL},
{VAL_GPIOJ_DATA, VAL_GPIOJ_DIR, VAL_GPIOJ_AFSEL, VAL_GPIOJ_DR2R,
VAL_GPIOJ_DR4R, VAL_GPIOJ_DR8R, VAL_GPIOJ_ODR, VAL_GPIOJ_PUR,
VAL_GPIOJ_PDR, VAL_GPIOJ_SLR, VAL_GPIOJ_DEN, VAL_GPIOJ_AMSEL,
VAL_GPIOJ_PCTL},
{VAL_GPIOK_DATA, VAL_GPIOK_DIR, VAL_GPIOK_AFSEL, VAL_GPIOK_DR2R,
VAL_GPIOK_DR4R, VAL_GPIOK_DR8R, VAL_GPIOK_ODR, VAL_GPIOK_PUR,
VAL_GPIOK_PDR, VAL_GPIOK_SLR, VAL_GPIOK_DEN, VAL_GPIOK_AMSEL,
VAL_GPIOK_PCTL},
{VAL_GPIOL_DATA, VAL_GPIOL_DIR, VAL_GPIOL_AFSEL, VAL_GPIOL_DR2R,
VAL_GPIOL_DR4R, VAL_GPIOL_DR8R, VAL_GPIOL_ODR, VAL_GPIOL_PUR,
VAL_GPIOL_PDR, VAL_GPIOL_SLR, VAL_GPIOL_DEN, VAL_GPIOL_AMSEL,
VAL_GPIOL_PCTL},
{VAL_GPIOM_DATA, VAL_GPIOM_DIR, VAL_GPIOM_AFSEL, VAL_GPIOM_DR2R,
VAL_GPIOM_DR4R, VAL_GPIOM_DR8R, VAL_GPIOM_ODR, VAL_GPIOM_PUR,
VAL_GPIOM_PDR, VAL_GPIOM_SLR, VAL_GPIOM_DEN, VAL_GPIOM_AMSEL,
VAL_GPIOM_PCTL},
{VAL_GPION_DATA, VAL_GPION_DIR, VAL_GPION_AFSEL, VAL_GPION_DR2R,
VAL_GPION_DR4R, VAL_GPION_DR8R, VAL_GPION_ODR, VAL_GPION_PUR,
VAL_GPION_PDR, VAL_GPION_SLR, VAL_GPION_DEN, VAL_GPION_AMSEL,
VAL_GPION_PCTL},
{VAL_GPIOP_DATA, VAL_GPIOP_DIR, VAL_GPIOP_AFSEL, VAL_GPIOP_DR2R,
VAL_GPIOP_DR4R, VAL_GPIOP_DR8R, VAL_GPIOP_ODR, VAL_GPIOP_PUR,
VAL_GPIOP_PDR, VAL_GPIOP_SLR, VAL_GPIOP_DEN, VAL_GPIOP_AMSEL,
VAL_GPIOP_PCTL},
{VAL_GPIOQ_DATA, VAL_GPIOQ_DIR, VAL_GPIOQ_AFSEL, VAL_GPIOQ_DR2R,
VAL_GPIOQ_DR4R, VAL_GPIOQ_DR8R, VAL_GPIOQ_ODR, VAL_GPIOQ_PUR,
VAL_GPIOQ_PDR, VAL_GPIOQ_SLR, VAL_GPIOQ_DEN, VAL_GPIOQ_AMSEL,
VAL_GPIOQ_PCTL}
};
#endif
/**
* @brief Early initialization code.
* @details This initialization is performed just after reset before BSS and
* DATA segments initialization.
*/
void __early_init(void) {
tiva_clock_init();
}
/**
* @brief Late initialization code.
* @note This initialization is performed after BSS and DATA segments
* initialization and before invoking the main() function.
*/
void boardInit(void) {
}

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/*
Copyright (C) 2014 Marco Veeneman
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* Setup for Texas Instruments TM4C1294 Launchpad Board.
*/
/*
* Board identifier.
*/
#define BOARD_TI_TM4C1294_LAUNCHPAD
#define BOARD_NAME "Texas Instruments TM4C1294 Launchpad"
/*
* MCU type
*/
//#define TM4C1290NCPDT
//#define TM4C1290NCZAD
//#define TM4C1292NCPDT
//#define TM4C1292NCZAD
//#define TM4C1294KCPDT
#define TM4C1294NCPDT
//#define TM4C1294NCZAD
//#define TM4C1297NCZAD
//#define TM4C1299KCZAD
//#define TM4C1299NCZAD
//#define TM4C129CNCPDT
//#define TM4C129CNCZAD
//#define TM4C129DNCPDT
//#define TM4C129DNCZAD
//#define TM4C129EKCPDT
//#define TM4C129ENCPDT
//#define TM4C129ENCZAD
//#define TM4C129LNCZAD
//#define TM4C129XKCZAD
//#define TM4C129XNCZAD
/*
* Board oscillators-related settings.
*/
#define TIVA_XTAL_VALUE 25000000
/*
* IO pins assignments.
*/
#define GPIOA_UART0_RX 0
#define GPIOA_UART0_TX 1
#define GPIOA_PIN2 2
#define GPIOA_PIN3 3
#define GPIOA_PIN4 4
#define GPIOA_PIN5 5
#define GPIOA_PIN6 6
#define GPIOA_PIN7 7
#define GPIOB_PIN0 0
#define GPIOB_PIN1 1
#define GPIOB_PIN2 2
#define GPIOB_PIN3 3
#define GPIOB_PIN4 4
#define GPIOB_PIN5 5
#define GPIOB_PIN6 6
#define GPIOB_PIN7 7
#define GPIOC_TCK_SWCLK 0
#define GPIOC_TMS_SWDIO 1
#define GPIOC_TDI 2
#define GPIOC_TDO_SWO 3
#define GPIOC_PIN4 4
#define GPIOC_PIN5 5
#define GPIOC_PIN6 6
#define GPIOC_PIN7 7
#define GPIOD_PIN0 0
#define GPIOD_PIN1 1
#define GPIOD_PIN2 2
#define GPIOD_PIN3 3
#define GPIOD_PIN4 4
#define GPIOD_PIN5 5
#define GPIOD_PIN6 6
#define GPIOD_PIN7 7
#define GPIOE_PIN0 0
#define GPIOE_PIN1 1
#define GPIOE_PIN2 2
#define GPIOE_PIN3 3
#define GPIOE_PIN4 4
#define GPIOE_PIN5 5
#define GPIOE_PIN6 6
#define GPIOE_PIN7 7
#define GPIOF_LED0 0
#define GPIOF_PIN1 1
#define GPIOF_PIN2 2
#define GPIOF_PIN3 3
#define GPIOF_LED1 4
#define GPIOF_PIN5 5
#define GPIOF_PIN6 6
#define GPIOF_PIN7 7
#define GPIOG_PIN0 0
#define GPIOG_PIN1 1
#define GPIOG_PIN2 2
#define GPIOG_PIN3 3
#define GPIOG_PIN4 4
#define GPIOG_PIN5 5
#define GPIOG_PIN6 6
#define GPIOG_PIN7 7
#define GPIOH_PIN0 0
#define GPIOH_PIN1 1
#define GPIOH_PIN2 2
#define GPIOH_PIN3 3
#define GPIOH_PIN4 4
#define GPIOH_PIN5 5
#define GPIOH_PIN6 6
#define GPIOH_PIN7 7
#define GPIOJ_SW1 0
#define GPIOJ_PIN1 1
#define GPIOJ_PIN2 2
#define GPIOJ_PIN3 3
#define GPIOJ_PIN4 4
#define GPIOJ_PIN5 5
#define GPIOJ_PIN6 6
#define GPIOJ_PIN7 7
#define GPIOK_PIN0 0
#define GPIOK_PIN1 1
#define GPIOK_PIN2 2
#define GPIOK_PIN3 3
#define GPIOK_PIN4 4
#define GPIOK_PIN5 5
#define GPIOK_PIN6 6
#define GPIOK_PIN7 7
#define GPIOL_PIN0 0
#define GPIOL_PIN1 1
#define GPIOL_PIN2 2
#define GPIOL_PIN3 3
#define GPIOL_PIN4 4
#define GPIOL_PIN5 5
#define GPIOL_PIN6 6
#define GPIOL_PIN7 7
#define GPIOM_PIN0 0
#define GPIOM_PIN1 1
#define GPIOM_PIN2 2
#define GPIOM_PIN3 3
#define GPIOM_PIN4 4
#define GPIOM_PIN5 5
#define GPIOM_PIN6 6
#define GPIOM_PIN7 7
#define GPION_LED2 0
#define GPION_LED3 1
#define GPION_PIN2 2
#define GPION_PIN3 3
#define GPION_PIN4 4
#define GPION_PIN5 5
#define GPION_PIN6 6
#define GPION_PIN7 7
#define GPIOP_PIN0 0
#define GPIOP_PIN1 1
#define GPIOP_PIN2 2
#define GPIOP_PIN3 3
#define GPIOP_PIN4 4
#define GPIOP_PIN5 5
#define GPIOP_PIN6 6
#define GPIOP_PIN7 7
#define GPIOQ_PIN0 0
#define GPIOQ_PIN1 1
#define GPIOQ_PIN2 2
#define GPIOQ_PIN3 3
#define GPIOQ_PIN4 4
#define GPIOQ_PIN5 5
#define GPIOQ_PIN6 6
#define GPIOQ_PIN7 7
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
*/
#define VAL_GPIOA_DATA 0b00000000
#define VAL_GPIOA_DIR 0b00000000
#define VAL_GPIOA_AFSEL 0b00000011
#define VAL_GPIOA_DR2R 0b11111111
#define VAL_GPIOA_DR4R 0b00000000
#define VAL_GPIOA_DR8R 0b00000000
#define VAL_GPIOA_ODR 0b00000000
#define VAL_GPIOA_PUR 0b00000000
#define VAL_GPIOA_PDR 0b00000000
#define VAL_GPIOA_SLR 0b00000000
#define VAL_GPIOA_DEN 0b11111111
#define VAL_GPIOA_AMSEL 0b0000
#define VAL_GPIOA_PCTL 0x00000011
#define VAL_GPIOB_DATA 0b00000000
#define VAL_GPIOB_DIR 0b00000000
#define VAL_GPIOB_AFSEL 0b00001100
#define VAL_GPIOB_DR2R 0b11111111
#define VAL_GPIOB_DR4R 0b00000000
#define VAL_GPIOB_DR8R 0b00000000
#define VAL_GPIOB_ODR 0b00001000
#define VAL_GPIOB_PUR 0b00000000
#define VAL_GPIOB_PDR 0b00000000
#define VAL_GPIOB_SLR 0b00000000
#define VAL_GPIOB_DEN 0b11111111
#define VAL_GPIOB_AMSEL 0b0000
#define VAL_GPIOB_PCTL 0x00003300
#define VAL_GPIOC_DATA 0b00000000
#define VAL_GPIOC_DIR 0b00001000
#define VAL_GPIOC_AFSEL 0b00001111
#define VAL_GPIOC_DR2R 0b11111111
#define VAL_GPIOC_DR4R 0b00000000
#define VAL_GPIOC_DR8R 0b00000000
#define VAL_GPIOC_ODR 0b00000000
#define VAL_GPIOC_PUR 0b00001111
#define VAL_GPIOC_PDR 0b00000000
#define VAL_GPIOC_SLR 0b00000000
#define VAL_GPIOC_DEN 0b11111111
#define VAL_GPIOC_AMSEL 0b0000
#define VAL_GPIOC_PCTL 0x00001111
#define VAL_GPIOD_DATA 0b00000000
#define VAL_GPIOD_DIR 0b00000000
#define VAL_GPIOD_AFSEL 0b00000000
#define VAL_GPIOD_DR2R 0b11111111
#define VAL_GPIOD_DR4R 0b00000000
#define VAL_GPIOD_DR8R 0b00000000
#define VAL_GPIOD_ODR 0b00000000
#define VAL_GPIOD_PUR 0b00000000
#define VAL_GPIOD_PDR 0b00000000
#define VAL_GPIOD_SLR 0b00000000
#define VAL_GPIOD_DEN 0b11111111
#define VAL_GPIOD_AMSEL 0b0000
#define VAL_GPIOD_PCTL 0x00000000
#define VAL_GPIOE_DATA 0b00000000
#define VAL_GPIOE_DIR 0b00000000
#define VAL_GPIOE_AFSEL 0b00000000
#define VAL_GPIOE_DR2R 0b11111111
#define VAL_GPIOE_DR4R 0b00000000
#define VAL_GPIOE_DR8R 0b00000000
#define VAL_GPIOE_ODR 0b00000000
#define VAL_GPIOE_PUR 0b00000000
#define VAL_GPIOE_PDR 0b00000000
#define VAL_GPIOE_SLR 0b00000000
#define VAL_GPIOE_DEN 0b11111111
#define VAL_GPIOE_AMSEL 0b0000
#define VAL_GPIOE_PCTL 0x00000000
#define VAL_GPIOF_DATA 0b00000000
#define VAL_GPIOF_DIR 0b00010001
#define VAL_GPIOF_AFSEL 0b00000000
#define VAL_GPIOF_DR2R 0b11111111
#define VAL_GPIOF_DR4R 0b00000000
#define VAL_GPIOF_DR8R 0b00000000
#define VAL_GPIOF_ODR 0b00000000
#define VAL_GPIOF_PUR 0b00010001
#define VAL_GPIOF_PDR 0b00000000
#define VAL_GPIOF_SLR 0b00000000
#define VAL_GPIOF_DEN 0b11111111
#define VAL_GPIOF_AMSEL 0b0000
#define VAL_GPIOF_PCTL 0x00000000
#define VAL_GPIOG_DATA 0b00000000
#define VAL_GPIOG_DIR 0b00000000
#define VAL_GPIOG_AFSEL 0b00000000
#define VAL_GPIOG_DR2R 0b11111111
#define VAL_GPIOG_DR4R 0b00000000
#define VAL_GPIOG_DR8R 0b00000000
#define VAL_GPIOG_ODR 0b00000000
#define VAL_GPIOG_PUR 0b00000000
#define VAL_GPIOG_PDR 0b00000000
#define VAL_GPIOG_SLR 0b00000000
#define VAL_GPIOG_DEN 0b11111111
#define VAL_GPIOG_AMSEL 0b0000
#define VAL_GPIOG_PCTL 0x00000000
#define VAL_GPIOH_DATA 0b00000000
#define VAL_GPIOH_DIR 0b00000000
#define VAL_GPIOH_AFSEL 0b00000000
#define VAL_GPIOH_DR2R 0b11111111
#define VAL_GPIOH_DR4R 0b00000000
#define VAL_GPIOH_DR8R 0b00000000
#define VAL_GPIOH_ODR 0b00000000
#define VAL_GPIOH_PUR 0b00000000
#define VAL_GPIOH_PDR 0b00000000
#define VAL_GPIOH_SLR 0b00000000
#define VAL_GPIOH_DEN 0b11111111
#define VAL_GPIOH_AMSEL 0b0000
#define VAL_GPIOH_PCTL 0x00000000
#define VAL_GPIOJ_DATA 0b00000000
#define VAL_GPIOJ_DIR 0b00000000
#define VAL_GPIOJ_AFSEL 0b00000000
#define VAL_GPIOJ_DR2R 0b11111111
#define VAL_GPIOJ_DR4R 0b00000000
#define VAL_GPIOJ_DR8R 0b00000000
#define VAL_GPIOJ_ODR 0b00000000
#define VAL_GPIOJ_PUR 0b00000001
#define VAL_GPIOJ_PDR 0b00000000
#define VAL_GPIOJ_SLR 0b00000000
#define VAL_GPIOJ_DEN 0b11111111
#define VAL_GPIOJ_AMSEL 0b0000
#define VAL_GPIOJ_PCTL 0x00000000
#define VAL_GPIOK_DATA 0b00000000
#define VAL_GPIOK_DIR 0b00000000
#define VAL_GPIOK_AFSEL 0b00000000
#define VAL_GPIOK_DR2R 0b11111111
#define VAL_GPIOK_DR4R 0b00000000
#define VAL_GPIOK_DR8R 0b00000000
#define VAL_GPIOK_ODR 0b00000000
#define VAL_GPIOK_PUR 0b00000000
#define VAL_GPIOK_PDR 0b00000000
#define VAL_GPIOK_SLR 0b00000000
#define VAL_GPIOK_DEN 0b11111111
#define VAL_GPIOK_AMSEL 0b0000
#define VAL_GPIOK_PCTL 0x00000000
#define VAL_GPIOL_DATA 0b00000000
#define VAL_GPIOL_DIR 0b00000000
#define VAL_GPIOL_AFSEL 0b00000000
#define VAL_GPIOL_DR2R 0b11111111
#define VAL_GPIOL_DR4R 0b00000000
#define VAL_GPIOL_DR8R 0b00000000
#define VAL_GPIOL_ODR 0b00000000
#define VAL_GPIOL_PUR 0b00000000
#define VAL_GPIOL_PDR 0b00000000
#define VAL_GPIOL_SLR 0b00000000
#define VAL_GPIOL_DEN 0b11111111
#define VAL_GPIOL_AMSEL 0b0000
#define VAL_GPIOL_PCTL 0x00000000
#define VAL_GPIOM_DATA 0b00000000
#define VAL_GPIOM_DIR 0b00000000
#define VAL_GPIOM_AFSEL 0b00000000
#define VAL_GPIOM_DR2R 0b11111111
#define VAL_GPIOM_DR4R 0b00000000
#define VAL_GPIOM_DR8R 0b00000000
#define VAL_GPIOM_ODR 0b00000000
#define VAL_GPIOM_PUR 0b00000000
#define VAL_GPIOM_PDR 0b00000000
#define VAL_GPIOM_SLR 0b00000000
#define VAL_GPIOM_DEN 0b11111111
#define VAL_GPIOM_AMSEL 0b0000
#define VAL_GPIOM_PCTL 0x00000000
#define VAL_GPION_DATA 0b00000000
#define VAL_GPION_DIR 0b00000011
#define VAL_GPION_AFSEL 0b00000000
#define VAL_GPION_DR2R 0b11111111
#define VAL_GPION_DR4R 0b00000000
#define VAL_GPION_DR8R 0b00000000
#define VAL_GPION_ODR 0b00000000
#define VAL_GPION_PUR 0b00000000
#define VAL_GPION_PDR 0b00000000
#define VAL_GPION_SLR 0b00000000
#define VAL_GPION_DEN 0b11111111
#define VAL_GPION_AMSEL 0b0000
#define VAL_GPION_PCTL 0x00000000
#define VAL_GPIOP_DATA 0b00000000
#define VAL_GPIOP_DIR 0b00000000
#define VAL_GPIOP_AFSEL 0b00000000
#define VAL_GPIOP_DR2R 0b11111111
#define VAL_GPIOP_DR4R 0b00000000
#define VAL_GPIOP_DR8R 0b00000000
#define VAL_GPIOP_ODR 0b00000000
#define VAL_GPIOP_PUR 0b00000000
#define VAL_GPIOP_PDR 0b00000000
#define VAL_GPIOP_SLR 0b00000000
#define VAL_GPIOP_DEN 0b11111111
#define VAL_GPIOP_AMSEL 0b0000
#define VAL_GPIOP_PCTL 0x00000000
#define VAL_GPIOQ_DATA 0b00000000
#define VAL_GPIOQ_DIR 0b00000000
#define VAL_GPIOQ_AFSEL 0b00000000
#define VAL_GPIOQ_DR2R 0b11111111
#define VAL_GPIOQ_DR4R 0b00000000
#define VAL_GPIOQ_DR8R 0b00000000
#define VAL_GPIOQ_ODR 0b00000000
#define VAL_GPIOQ_PUR 0b00000000
#define VAL_GPIOQ_PDR 0b00000000
#define VAL_GPIOQ_SLR 0b00000000
#define VAL_GPIOQ_DEN 0b11111111
#define VAL_GPIOQ_AMSEL 0b0000
#define VAL_GPIOQ_PCTL 0x00000000
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */

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# List of all the board related files.
BOARDSRC = ${CHIBIOS}/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c
# Required include directories
BOARDINC = ${CHIBIOS}/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD