Fixed the MAC driver.
While moving the MAC driver to TivaWare the addresses used in the HWREG macros were incorrect. The base address was missing.
This commit is contained in:
parent
79fc9cfe5d
commit
ed9c079d62
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@ -89,10 +89,10 @@ static uint32_t tb[TIVA_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE];
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*/
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*/
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static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value)
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static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value)
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{
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{
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HWREG(EMAC_O_MIIDATA) = value;
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HWREG(EMAC0_BASE + EMAC_O_MIIDATA) = value;
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HWREG(EMAC_O_MIIADDR) = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB;
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HWREG(EMAC0_BASE + EMAC_O_MIIADDR) = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB;
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while ((HWREG(EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) != 0)
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while ((HWREG(EMAC0_BASE + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) != 0)
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;
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;
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}
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}
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@ -126,12 +126,12 @@ static void mii_write_extended(MACDriver *macp, uint32_t reg, uint32_t value)
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*/
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*/
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static uint32_t mii_read(MACDriver *macp, uint32_t reg)
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static uint32_t mii_read(MACDriver *macp, uint32_t reg)
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{
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{
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HWREG(EMAC_O_MIIADDR) = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB;
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HWREG(EMAC0_BASE + EMAC_O_MIIADDR) = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB;
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while ((HWREG(EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) != 0)
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while ((HWREG(EMAC0_BASE + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) != 0)
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;
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;
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return HWREG(EMAC_O_MIIDATA);
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return HWREG(EMAC0_BASE + EMAC_O_MIIDATA);
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}
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}
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/**
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/**
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@ -171,7 +171,7 @@ static void mii_find_phy(MACDriver *macp)
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#endif
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#endif
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for (i = 0; i < 31; i++) {
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for (i = 0; i < 31; i++) {
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macp->phyaddr = i << 11;
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macp->phyaddr = i << 11;
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HWREG(EMAC_O_MIIDATA) = (i << 6) | MACMIIADDR_CR;
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HWREG(EMAC0_BASE + EMAC_O_MIIDATA) = (i << 6) | MACMIIADDR_CR;
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if ((mii_read(macp, TIVA_ID1) == (BOARD_PHY_ID >> 16)) &&
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if ((mii_read(macp, TIVA_ID1) == (BOARD_PHY_ID >> 16)) &&
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((mii_read(macp, TIVA_ID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) {
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((mii_read(macp, TIVA_ID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) {
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return;
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return;
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@ -196,20 +196,20 @@ static void mac_lld_set_address(const uint8_t *p)
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{
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{
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/* MAC address configuration, only a single address comparator is used,
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/* MAC address configuration, only a single address comparator is used,
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hash table not used.*/
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hash table not used.*/
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HWREG(EMAC_O_ADDR0H) = ((uint32_t)p[5] << 8) |
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HWREG(EMAC0_BASE + EMAC_O_ADDR0H) = ((uint32_t)p[5] << 8) |
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((uint32_t)p[4] << 0);
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((uint32_t)p[4] << 0);
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HWREG(EMAC_O_ADDR0L) = ((uint32_t)p[3] << 24) |
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HWREG(EMAC0_BASE + EMAC_O_ADDR0L) = ((uint32_t)p[3] << 24) |
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((uint32_t)p[2] << 16) |
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((uint32_t)p[2] << 16) |
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((uint32_t)p[1] << 8) |
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((uint32_t)p[1] << 8) |
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((uint32_t)p[0] << 0);
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((uint32_t)p[0] << 0);
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HWREG(EMAC_O_ADDR1H) = 0x0000FFFF;
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HWREG(EMAC0_BASE + EMAC_O_ADDR1H) = 0x0000FFFF;
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HWREG(EMAC_O_ADDR1L) = 0xFFFFFFFF;
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HWREG(EMAC0_BASE + EMAC_O_ADDR1L) = 0xFFFFFFFF;
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HWREG(EMAC_O_ADDR2H) = 0x0000FFFF;
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HWREG(EMAC0_BASE + EMAC_O_ADDR2H) = 0x0000FFFF;
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HWREG(EMAC_O_ADDR2L) = 0xFFFFFFFF;
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HWREG(EMAC0_BASE + EMAC_O_ADDR2L) = 0xFFFFFFFF;
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HWREG(EMAC_O_ADDR3H) = 0x0000FFFF;
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HWREG(EMAC0_BASE + EMAC_O_ADDR3H) = 0x0000FFFF;
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HWREG(EMAC_O_ADDR3L) = 0xFFFFFFFF;
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HWREG(EMAC0_BASE + EMAC_O_ADDR3L) = 0xFFFFFFFF;
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HWREG(EMAC_O_HASHTBLH) = 0;
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HWREG(EMAC0_BASE + EMAC_O_HASHTBLH) = 0;
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HWREG(EMAC_O_HASHTBLL) = 0;
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HWREG(EMAC0_BASE + EMAC_O_HASHTBLL) = 0;
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}
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}
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/*===========================================================================*/
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/*===========================================================================*/
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@ -222,8 +222,8 @@ CH_IRQ_HANDLER(TIVA_MAC_HANDLER)
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CH_IRQ_PROLOGUE();
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CH_IRQ_PROLOGUE();
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dmaris = HWREG(EMAC_O_DMARIS);
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dmaris = HWREG(EMAC0_BASE + EMAC_O_DMARIS);
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HWREG(EMAC_O_DMARIS) = dmaris & 0x0001FFFF; /* Clear status bits.*/
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HWREG(EMAC0_BASE + EMAC_O_DMARIS) = dmaris & 0x0001FFFF; /* Clear status bits.*/
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if (dmaris & (1 << 6)) {
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if (dmaris & (1 << 6)) {
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/* Data Received.*/
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/* Data Received.*/
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@ -280,7 +280,7 @@ void mac_lld_init(void)
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;
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;
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/* Set PHYHOLD bit */
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/* Set PHYHOLD bit */
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HWREG(EMAC_O_PC) |= 1;
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HWREG(EMAC0_BASE + EMAC_O_PC) |= 1;
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/* Enable PHY clock */
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/* Enable PHY clock */
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HWREG(SYSCTL_RCGCEPHY) = 1;
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HWREG(SYSCTL_RCGCEPHY) = 1;
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@ -292,9 +292,9 @@ void mac_lld_init(void)
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while (HWREG(SYSCTL_PREPHY) != 0x01)
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while (HWREG(SYSCTL_PREPHY) != 0x01)
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;
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;
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#if BOARD_PHY_RMII
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#if BOARD_PHY_RMII
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HWREG(EMAC_O_PC) = EMAC_PHY_CONFIG | (0x04 << 28);
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HWREG(EMAC0_BASE + EMAC_O_PC) = EMAC_PHY_CONFIG | (0x04 << 28);
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#else
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#else
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HWREG(EMAC_O_PC) = EMAC_PHY_CONFIG;
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HWREG(EMAC0_BASE + EMAC_O_PC) = EMAC_PHY_CONFIG;
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#endif
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#endif
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/*
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/*
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@ -310,12 +310,12 @@ void mac_lld_init(void)
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/* Set done bit after writing EMACPC register */
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/* Set done bit after writing EMACPC register */
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mii_write(ÐD1, TIVA_CFG1, (1 << 15) | mii_read(ÐD1, TIVA_CFG1));
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mii_write(ÐD1, TIVA_CFG1, (1 << 15) | mii_read(ÐD1, TIVA_CFG1));
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while(HWREG(EMAC_O_DMABUSMOD) & 1)
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while(HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) & 1)
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;
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;
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/* Reset MAC */
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/* Reset MAC */
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HWREG(EMAC_O_DMABUSMOD) |= 1;
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HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) |= 1;
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while (HWREG(EMAC_O_DMABUSMOD) & 1)
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while (HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) & 1)
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;
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;
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/* PHY address setup.*/
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/* PHY address setup.*/
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@ -392,9 +392,9 @@ void mac_lld_start(MACDriver *macp)
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#endif
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#endif
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/* MAC configuration.*/
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/* MAC configuration.*/
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HWREG(EMAC_O_FRAMEFLTR) = 0;
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HWREG(EMAC0_BASE + EMAC_O_FRAMEFLTR) = 0;
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HWREG(EMAC_O_FLOWCTL) = 0;
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HWREG(EMAC0_BASE + EMAC_O_FLOWCTL) = 0;
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HWREG(EMAC_O_VLANTG) = 0;
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HWREG(EMAC0_BASE + EMAC_O_VLANTG) = 0;
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/* MAC address setup.*/
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/* MAC address setup.*/
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if (macp->config->mac_address == NULL)
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if (macp->config->mac_address == NULL)
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@ -406,30 +406,30 @@ void mac_lld_start(MACDriver *macp)
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Note that the complete setup of the MAC is performed when the link
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Note that the complete setup of the MAC is performed when the link
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status is detected.*/
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status is detected.*/
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#if TIVA_MAC_IP_CHECKSUM_OFFLOAD
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#if TIVA_MAC_IP_CHECKSUM_OFFLOAD
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HWREG(EMAC_O_CFG) = (1 << 10) | (1 << 3) | (1 << 2);
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HWREG(EMAC0_BASE + EMAC_O_CFG) = (1 << 10) | (1 << 3) | (1 << 2);
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#else
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#else
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HWREG(EMAC_O_CFG) = (1 << 3) | (1 << 2);
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HWREG(EMAC0_BASE + EMAC_O_CFG) = (1 << 3) | (1 << 2);
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#endif
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#endif
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/* DMA configuration:
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/* DMA configuration:
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Descriptor chains pointers.*/
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Descriptor chains pointers.*/
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HWREG(EMAC_O_RXDLADDR) = (uint32_t)rd;
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HWREG(EMAC0_BASE + EMAC_O_RXDLADDR) = (uint32_t)rd;
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HWREG(EMAC_O_TXDLADDR) = (uint32_t)td;
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HWREG(EMAC0_BASE + EMAC_O_TXDLADDR) = (uint32_t)td;
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/* Enabling required interrupt sources.*/
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/* Enabling required interrupt sources.*/
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HWREG(EMAC_O_DMARIS) &= 0xFFFF;
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HWREG(EMAC0_BASE + EMAC_O_DMARIS) &= 0xFFFF;
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HWREG(EMAC_O_DMAIM) = (1 << 16) | (1 << 6) | (1 << 0);
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HWREG(EMAC0_BASE + EMAC_O_DMAIM) = (1 << 16) | (1 << 6) | (1 << 0);
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/* DMA general settings.*/
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/* DMA general settings.*/
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HWREG(EMAC_O_DMABUSMOD) = (1 << 25) | (1 << 17) | (1 << 8);
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HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) = (1 << 25) | (1 << 17) | (1 << 8);
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/* Transmit FIFO flush.*/
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/* Transmit FIFO flush.*/
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HWREG(EMAC_O_DMAOPMODE) = (1 << 20);
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HWREG(EMAC0_BASE + EMAC_O_DMAOPMODE) = (1 << 20);
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while (HWREG(EMAC_O_DMAOPMODE) & (1 << 20))
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while (HWREG(EMAC0_BASE + EMAC_O_DMAOPMODE) & (1 << 20))
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;
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;
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/* DMA final configuration and start.*/
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/* DMA final configuration and start.*/
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HWREG(EMAC_O_DMAOPMODE) = (1 << 26) | (1 << 25) | (1 << 21) |
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HWREG(EMAC0_BASE + EMAC_O_DMAOPMODE) = (1 << 26) | (1 << 25) | (1 << 21) |
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(1 << 13) | (1 << 1);
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(1 << 13) | (1 << 1);
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}
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}
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@ -449,10 +449,10 @@ void mac_lld_stop(MACDriver *macp)
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#endif
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#endif
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/* MAC and DMA stopped.*/
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/* MAC and DMA stopped.*/
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HWREG(EMAC_O_CFG) = 0;
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HWREG(EMAC0_BASE + EMAC_O_CFG) = 0;
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HWREG(EMAC_O_DMAOPMODE) = 0;
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HWREG(EMAC0_BASE + EMAC_O_DMAOPMODE) = 0;
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HWREG(EMAC_O_DMAIM) = 0;
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HWREG(EMAC0_BASE + EMAC_O_DMAIM) = 0;
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HWREG(EMAC_O_DMARIS) &= 0xFFFF;
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HWREG(EMAC0_BASE + EMAC_O_DMARIS) &= 0xFFFF;
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/* MAC clocks stopped.*/
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/* MAC clocks stopped.*/
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HWREG(SYSCTL_RCGCEMAC) = 0;
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HWREG(SYSCTL_RCGCEMAC) = 0;
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@ -537,9 +537,9 @@ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp)
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tdp->physdesc->locked = 0;
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tdp->physdesc->locked = 0;
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/* If the DMA engine is stalled then a restart request is issued.*/
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/* If the DMA engine is stalled then a restart request is issued.*/
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if ((HWREG(EMAC_O_DMARIS) & (0x7 << 20)) == (6 << 20)) {
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if ((HWREG(EMAC0_BASE + EMAC_O_DMARIS) & (0x7 << 20)) == (6 << 20)) {
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HWREG(EMAC_O_DMARIS) = (1 << 2);
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HWREG(EMAC0_BASE + EMAC_O_DMARIS) = (1 << 2);
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HWREG(EMAC_O_TXPOLLD) = 1; /* Any value is OK.*/
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HWREG(EMAC0_BASE + EMAC_O_TXPOLLD) = 1; /* Any value is OK.*/
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}
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}
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osalSysUnlock();
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osalSysUnlock();
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@ -616,9 +616,9 @@ void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp)
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rdp->physdesc->rdes0 = TIVA_RDES0_OWN;
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rdp->physdesc->rdes0 = TIVA_RDES0_OWN;
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/* If the DMA engine is stalled then a restart request is issued.*/
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/* If the DMA engine is stalled then a restart request is issued.*/
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if ((HWREG(EMAC_O_STATUS) & (0xf << 17)) == (4 << 17)) {
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if ((HWREG(EMAC0_BASE + EMAC_O_STATUS) & (0xf << 17)) == (4 << 17)) {
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HWREG(EMAC_O_DMARIS) = (1 << 7);
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HWREG(EMAC0_BASE + EMAC_O_DMARIS) = (1 << 7);
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HWREG(EMAC_O_TXPOLLD) = 1; /* Any value is OK.*/
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HWREG(EMAC0_BASE + EMAC_O_TXPOLLD) = 1; /* Any value is OK.*/
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}
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}
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osalSysUnlock();
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osalSysUnlock();
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@ -638,7 +638,7 @@ bool mac_lld_poll_link_status(MACDriver *macp)
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{
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{
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uint32_t maccfg, bmsr, bmcr;
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uint32_t maccfg, bmsr, bmcr;
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maccfg = HWREG(EMAC_O_CFG);
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maccfg = HWREG(EMAC0_BASE + EMAC_O_CFG);
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/* PHY CR and SR registers read.*/
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/* PHY CR and SR registers read.*/
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(void)mii_read(macp, MII_BMSR);
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(void)mii_read(macp, MII_BMSR);
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@ -688,7 +688,7 @@ bool mac_lld_poll_link_status(MACDriver *macp)
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}
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}
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/* Changes the mode in the MAC.*/
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/* Changes the mode in the MAC.*/
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HWREG(EMAC_O_CFG) = maccfg;
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HWREG(EMAC0_BASE + EMAC_O_CFG) = maccfg;
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/* Returns the link status.*/
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/* Returns the link status.*/
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return macp->link_up = true;
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return macp->link_up = true;
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