diff --git a/os/hal/ports/GD/GD32VF103/I2C/hal_i2c_lld.c b/os/hal/ports/GD/GD32VF103/I2C/hal_i2c_lld.c
index 84d6cf24..215d5cf9 100644
--- a/os/hal/ports/GD/GD32VF103/I2C/hal_i2c_lld.c
+++ b/os/hal/ports/GD/GD32VF103/I2C/hal_i2c_lld.c
@@ -138,7 +138,7 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
 
   osalDbgCheck((i2cp != NULL) &&
                (clock_speed > 0) &&
-               (clock_speed <= 400000));
+               (clock_speed <= 1000000));
 
   /* CR2 Configuration.*/
   dp->CTL1 &= (uint16_t)~I2C_CTL1_I2CCLK;
@@ -164,8 +164,8 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
     /* Sets the Maximum Rise Time for standard mode.*/
     dp->RT = I2C_CLK_FREQ + 1;
   }
-  else if (clock_speed <= 400000) {
-    /* Configure clock_div in fast mode.*/
+  else if (clock_speed <= 1000000) {
+    /* Configure clock_div in fast mode and fast mode plus.*/
     osalDbgAssert((duty == FAST_DUTY_CYCLE_2) ||
                   (duty == FAST_DUTY_CYCLE_16_9),
                   "invalid fast mode duty cycle");
@@ -190,9 +190,12 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
 
     /* Sets the Maximum Rise Time for fast mode.*/
     dp->RT = (I2C_CLK_FREQ * 300 / 1000) + 1;
-    } else if (clock_speed <= 1000000){
-      /* TODO: Add fast mode plus*/
+
+    if(clock_speed > 400000) {
+      /* Enable Fast mode plus */
+      dp->FMPCFG = I2C_FMPCFG_FMPEN;
     }
+  }
 
   osalDbgAssert((clock_div <= I2C_CKCFG_CLKC), "the selected clock is too low");
 
@@ -236,17 +239,13 @@ static void i2c_lld_set_opmode(I2CDriver *i2cp) {
  */
 static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) {
    I2C_TypeDef *dp = i2cp->i2c;
-   uint32_t regSR2 = dp->STAT1;
+   uint32_t regSTAT1 = dp->STAT1;
    uint32_t event = dp->STAT0;
 
-   /*for(int32_t i = 0; i < 20; i++){
-     __asm__ volatile ("nop");
-   }*/
-
   /* Interrupts are disabled just before dmaStreamEnable() because there
      is no need of interrupts until next transaction begin. All the work is
      done by the DMA.*/
-  switch (I2C_EV_MASK & (event | (regSR2 << 16))) {
+  switch (I2C_EV_MASK & (event | (regSTAT1 << 16))) {
   case I2C_EV5_MASTER_MODE_SELECT:
   case I2C_EV5_MASTER_MODE_SELECT_NO_BUSY:
     if ((i2cp->addr >> 8) > 0) {
diff --git a/os/hal/ports/GD/GD32VF103/I2C/hal_i2c_lld.h b/os/hal/ports/GD/GD32VF103/I2C/hal_i2c_lld.h
index 7648545a..31bb7305 100644
--- a/os/hal/ports/GD/GD32VF103/I2C/hal_i2c_lld.h
+++ b/os/hal/ports/GD/GD32VF103/I2C/hal_i2c_lld.h
@@ -116,10 +116,10 @@
 #define GD32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")
 #endif
 
-#define GD32_I2C_I2C1_RX_DMA_STREAM        GD32_DMA_STREAM_ID(1, 7)
-#define GD32_I2C_I2C1_TX_DMA_STREAM        GD32_DMA_STREAM_ID(1, 6)
-#define GD32_I2C_I2C2_RX_DMA_STREAM        GD32_DMA_STREAM_ID(1, 5)
-#define GD32_I2C_I2C2_TX_DMA_STREAM        GD32_DMA_STREAM_ID(1, 4)
+#define GD32_I2C_I2C1_RX_DMA_STREAM        GD32_DMA_STREAM_ID(0, 6)
+#define GD32_I2C_I2C1_TX_DMA_STREAM        GD32_DMA_STREAM_ID(0, 5)
+#define GD32_I2C_I2C2_RX_DMA_STREAM        GD32_DMA_STREAM_ID(0, 4)
+#define GD32_I2C_I2C2_TX_DMA_STREAM        GD32_DMA_STREAM_ID(0, 3)
 
 /** @} */
 
@@ -165,20 +165,12 @@
 #endif
 
 /* Check clock range. */
-#if defined(STM32F10X_LD_VL) || defined(GD32VF103_MD_VL) ||               \
-      defined(STM32F10X_HD_VL)
-#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 24)
-#error "I2C peripheral clock frequency out of range."
-#endif
-
-#elif defined(STM32F10X_LD) || defined(GD32VF103CB) ||                     \
-      defined(STM32F10X_HD) || defined(STM32F10X_XL) ||                     \
-      defined(STM32F10X_CL)
-#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 36)
+#if defined(GD32VF103) 
+#if !(I2C_CLK_FREQ >= 2) && (I2C_CLK_FREQ <= 48)
 #error "I2C peripheral clock frequency out of range."
 #endif
 #else
-#error "unspecified, unsupported or invalid STM32 platform"
+#error "unspecified, unsupported or invalid GD32 platform"
 #endif
 
 /*===========================================================================*/
@@ -221,8 +213,8 @@ typedef struct {
   i2copmode_t     op_mode;       /**< @brief Specifies the I2C mode.        */
   uint32_t        clock_speed;   /**< @brief Specifies the clock frequency.
                                       @note Must be set to a value lower
-                                      than 400kHz.                          */
-  i2cdutycycle_t  duty_cycle;    /**< @brief Specifies the I2C fast mode
+                                      than 1MHz.                            */
+  i2cdutycycle_t  duty_cycle;    /**< @brief Specifies the I2C fast mode (plus)
                                       duty cycle.                           */
 } I2CConfig;
 
diff --git a/os/hal/ports/GD/GD32VF103/stm32f105xc.h b/os/hal/ports/GD/GD32VF103/stm32f105xc.h
index 264cae4a..1cb18ee2 100644
--- a/os/hal/ports/GD/GD32VF103/stm32f105xc.h
+++ b/os/hal/ports/GD/GD32VF103/stm32f105xc.h
@@ -394,6 +394,7 @@ typedef struct
   __IO uint32_t STAT1;
   __IO uint32_t CKCFG;
   __IO uint32_t RT;
+  uint32_t RESERVED[27];
   __IO uint32_t FMPCFG;
 } I2C_TypeDef;