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Merge pull request #10 from TexZK/ltdc_dma2d 

Removed dependency on ST library for SDRAM
This commit is contained in:
Uladzimir Pylinski 2015-06-29 00:19:37 +03:00
parent d66299ff75 58f5fd1d72
commit f16e69497b
15 changed files with 299 additions and 3272 deletions
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8
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.project
View File

@ -77,14 +77,14 @@
</natures>
<linkedResources>
<link>
<name>os</name>
<name>os-community</name>
<type>2</type>
<locationURI>CHIBIOS/os</locationURI>
<locationURI>PARENT-3-PROJECT_LOC/os</locationURI>
</link>
<link>
<name>test</name>
<name>os-git</name>
<type>2</type>
<locationURI>CHIBIOS/test</locationURI>
<locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
</link>
</linkedResources>
</projectDescription>

11
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.settings/language.settings.xml
View File

@ -1,11 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
<configuration id="0.114656749" name="Default">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
</extension>
</configuration>
</project>

3
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/Makefile
View File

@ -120,8 +120,6 @@ CSRC = $(STARTUPSRC) \
./main.c \
./wolf3d_palette.c \
./res/wolf3d_vgagraph_chunk87.c \
./stmdrivers/stm32f4xx_fmc.c \
./stmdrivers/stm32f429i_discovery_sdram.c \
# eol
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
@ -157,7 +155,6 @@ INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
$(CHIBIOS)/os/hal/lib/streams \
$(CHIBIOS)/community/os/various/devices_lib/lcd \
./res \
./stmdrivers \
# eol
#

104
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (Run Only).launch → demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (OpenOCD, Run Only).launch
View File

@ -1,52 +1,52 @@
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6
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf.h
View File

@ -329,6 +329,12 @@
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* Community drivers' includes */
/*===========================================================================*/
#include "halconf_community.h"
#endif /* _HALCONF_H_ */
/** @} */

70
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h Normal file
View File

@ -0,0 +1,70 @@
/*
ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _HALCONF_COMMUNITY_H_
#define _HALCONF_COMMUNITY_H_
/**
* @brief Enables the community overlay.
*/
#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__)
#define HAL_USE_COMMUNITY TRUE
#endif
/**
* @brief Enables the NAND subsystem.
*/
#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__)
#define HAL_USE_NAND FALSE
#endif
/**
* @brief Enables the 1-wire subsystem.
*/
#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__)
#define HAL_USE_ONEWIRE FALSE
#endif
/*===========================================================================*/
/* FSMCNAND driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define NAND_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* 1-wire driver related settings. */
/*===========================================================================*/
/**
* @brief Enables strong pull up feature.
* @note Disabling this option saves both code and data space.
*/
#define ONEWIRE_USE_STRONG_PULLUP FALSE
/**
* @brief Enables search ROM feature.
* @note Disabling this option saves both code and data space.
*/
#define ONEWIRE_USE_SEARCH_ROM TRUE
#endif /* _HALCONF_COMMUNITY_H_ */
/** @} */

375
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c
View File

@ -24,15 +24,138 @@
#include "usbcfg.h"
#endif
#include "stmdrivers/stm32f429i_discovery_sdram.h"
#include "stmdrivers/stm32f4xx_fmc.h"
#include "fsmc_sdram.h"
#include "ili9341.h"
#include "stm32_ltdc.h"
#include "stm32_dma2d.h"
#include "res/wolf3d_vgagraph_chunk87.h"
/*===========================================================================*/
/* SDRAM related. */
/*===========================================================================*/
// TODO: Move constants below elsewhere, and normalize their name
/* SDRAM bank base address.*/
#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000)
/*
* FMC SDRAM Mode definition register defines
*/
#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000)
#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001)
#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002)
#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004)
#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020)
#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030)
#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
/*
* FMC_ReadPipe_Delay
*/
#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000)
#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000)
#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000)
#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000)
/*
* FMC_Read_Burst
*/
#define FMC_Read_Burst_Disable ((uint32_t)0x00000000)
#define FMC_Read_Burst_Enable ((uint32_t)0x00001000)
#define FMC_Read_Burst_Mask ((uint32_t)0x00001000)
/*
* FMC_SDClock_Period
*/
#define FMC_SDClock_Disable ((uint32_t)0x00000000)
#define FMC_SDClock_Period_2 ((uint32_t)0x00000800)
#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00)
#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00)
/*
* FMC_ColumnBits_Number
*/
#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000)
#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001)
#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002)
#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003)
/*
* FMC_RowBits_Number
*/
#define FMC_RowBits_Number_11b ((uint32_t)0x00000000)
#define FMC_RowBits_Number_12b ((uint32_t)0x00000004)
#define FMC_RowBits_Number_13b ((uint32_t)0x00000008)
/*
* FMC_SDMemory_Data_Width
*/
#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000)
#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010)
#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020)
/*
* FMC_InternalBank_Number
*/
#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000)
#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040)
/*
* FMC_CAS_Latency
*/
#define FMC_CAS_Latency_1 ((uint32_t)0x00000080)
#define FMC_CAS_Latency_2 ((uint32_t)0x00000100)
#define FMC_CAS_Latency_3 ((uint32_t)0x00000180)
/*
* FMC_Write_Protection
*/
#define FMC_Write_Protection_Disable ((uint32_t)0x00000000)
#define FMC_Write_Protection_Enable ((uint32_t)0x00000200)
/*
* SDRAM driver configuration structure.
*/
static const SDRAMConfig sdram_cfg = {
.sdcr = (uint32_t)(FMC_ColumnBits_Number_8b |
FMC_RowBits_Number_12b |
FMC_SDMemory_Width_16b |
FMC_InternalBank_Number_4 |
FMC_CAS_Latency_3 |
FMC_Write_Protection_Disable |
FMC_SDClock_Period_2 |
FMC_Read_Burst_Disable |
FMC_ReadPipe_Delay_1),
.sdtr = (uint32_t)((2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles)
(7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns))
(4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns))
(7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns))
(2 << 16) | // FMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns))
(2 << 20) | // FMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns)
(2 << 24)), // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns)
.sdcmr = (uint32_t)(((4 - 1) << 5) |
((FMC_SDCMR_MRD_BURST_LENGTH_2 |
FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |
FMC_SDCMR_MRD_CAS_LATENCY_3 |
FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |
FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9)),
/* if (STM32_SYSCLK == 180000000) ->
64ms / 4096 = 15.625us
15.625us * 90MHz = 1406 - 20 = 1386 */
//.sdrtr = (1386 << 1),
.sdrtr = (uint32_t)(683 << 1),
};
/* SDRAM size, in bytes.*/
#define IS42S16400J_SIZE (8 * 1024 * 1024)
/*
@ -424,251 +547,11 @@ static void cmd_reset(BaseSequentialStream *chp, int argc, char *argv[]) {
NVIC_SystemReset();
}
static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) {
uint32_t counter = 0;
uint8_t ubWritedata_8b = 0x3C;
uint32_t uwReadwritestatus = 0;
time_measurement_t tm;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: write\r\n");
return;
}
chTMObjectInit(&tm);
chTMStartMeasurementX(&tm);
/* Write data value to all SDRAM memory */
for (counter = 0; counter < IS42S16400J_SIZE; counter++)
{
*(volatile uint8_t*) (SDRAM_BANK_ADDR + counter) = (uint8_t)(ubWritedata_8b + counter);
}
chTMStopMeasurementX(&tm);
uint32_t write_ms = RTT2MS(tm.last);
if (!uwReadwritestatus) {
chprintf(chp, "SDRAM written in %dms.\r\n", write_ms);
}
}
static void cmd_erase(BaseSequentialStream *chp, int argc, char *argv[]) {
uint32_t counter = 0;
uint32_t uwReadwritestatus = 0;
time_measurement_t tm;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: erase\r\n");
return;
}
chTMObjectInit(&tm);
//XXX chTMStartMeasurement(&tm);
/* Write data value to all SDRAM memory */
/* Erase SDRAM memory */
for (counter = 0; counter < IS42S16400J_SIZE; counter++)
{
*(volatile uint8_t*) (SDRAM_BANK_ADDR + counter) = (uint8_t)0x0;
}
//XXX chTMStopMeasurement(&tm);
uint32_t write_ms = 0;//XXX RTT2MS(tm.last);
if (!uwReadwritestatus) {
chprintf(chp, "SDRAM erased in %dms.\r\n", write_ms);
}
}
static void cmd_selfrefresh(BaseSequentialStream *chp, int argc, char *argv[]) {
(void)argv;
FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
if (argc > 0) {
chprintf(chp, "Usage: selfrefresh\r\n");
return;
}
/* Program a self-refresh mode command */
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_Selfrefresh;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
/* Send the command */
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) {
}
/* Check the bank mode status */
if(FMC_GetModeStatus(FMC_Bank2_SDRAM) != FMC_SelfRefreshMode_Status) {
chprintf(chp, "SDRAM is not in self refresh mode, command FAILED.\r\n");
} else {
chprintf(chp, "SDRAM is in self refresh mode.\r\n");
}
}
static void cmd_normal(BaseSequentialStream *chp, int argc, char *argv[]) {
(void)argv;
FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
if (argc > 0) {
chprintf(chp, "Usage: normal\r\n");
return;
}
/* Program a self-refresh mode command */
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_normal;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
/* Send the command */
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) {
}
/* Check the bank mode status */
if(FMC_GetModeStatus(FMC_Bank2_SDRAM) != FMC_NormalMode_Status) {
chprintf(chp, "SDRAM is not in normal mode, command FAILED.\r\n");
} else {
chprintf(chp, "SDRAM is in normal mode.\r\n");
}
}
static void cmd_check(BaseSequentialStream *chp, int argc, char *argv[]) {
uint32_t counter = 0;
uint8_t ubWritedata_8b = 0x3C, ubReaddata_8b = 0;
uint32_t uwReadwritestatus = 0;
time_measurement_t tm;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: check\r\n");
return;
}
chTMObjectInit(&tm);
chTMStartMeasurementX(&tm);
/* Read back SDRAM memory and check content correctness*/
counter = 0;
uwReadwritestatus = 0;
while ((counter < IS42S16400J_SIZE) && (uwReadwritestatus == 0))
{
ubReaddata_8b = *(volatile uint8_t*)(SDRAM_BANK_ADDR + counter);
if ( ubReaddata_8b != (uint8_t)(ubWritedata_8b + counter))
{
uwReadwritestatus = 1;
chprintf(chp, "Error at %d, expected %d but read %d.\r\n", counter, ubWritedata_8b + counter, ubReaddata_8b);
}
counter++;
}
chTMStopMeasurementX(&tm);
uint32_t check_ms = RTT2MS(tm.last);
//FIXME time this
if (!uwReadwritestatus) {
chprintf(chp, "SDRAM read and check completed successfully in %dms.\r\n", check_ms);
}
}
static void cmd_sdram(BaseSequentialStream *chp, int argc, char *argv[]) {
uint32_t counter = 0;
uint8_t ubWritedata_8b = 0x3C, ubReaddata_8b = 0;
uint32_t uwReadwritestatus = 0;
time_measurement_t tm;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: sdram\r\n");
return;
}
chTMObjectInit(&tm);
chTMStartMeasurementX(&tm);
// /* Erase SDRAM memory */
// for (counter = 0; counter < IS42S16400J_SIZE; counter++)
// {
// *(volatile uint8_t*) (SDRAM_BANK_ADDR + counter) = (uint8_t)0x0;
// }
/* Write data value to all SDRAM memory */
for (counter = 0; counter < IS42S16400J_SIZE; counter++)
{
*(volatile uint8_t*) (SDRAM_BANK_ADDR + counter) = (uint8_t)(ubWritedata_8b + counter);
}
chTMStopMeasurementX(&tm);
uint32_t write_ms = RTT2MS(tm.last);
chTMStartMeasurementX(&tm);
/* Read back SDRAM memory */
counter = 0;
while ((counter < IS42S16400J_SIZE))
{
ubReaddata_8b = *(volatile uint8_t*)(SDRAM_BANK_ADDR + counter);
counter++;
}
chTMStopMeasurementX(&tm);
uint32_t read_ms = RTT2MS(tm.last);
/* Read back SDRAM memory and check content correctness*/
counter = 0;
uwReadwritestatus = 0;
while ((counter < IS42S16400J_SIZE) && (uwReadwritestatus == 0))
{
ubReaddata_8b = *(volatile uint8_t*)(SDRAM_BANK_ADDR + counter);
if ( ubReaddata_8b != (uint8_t)(ubWritedata_8b + counter))
{
uwReadwritestatus = 1;
chprintf(chp, "Error at %d, expected %d but read %d.\r\n", counter, ubWritedata_8b + counter, ubReaddata_8b);
}
counter++;
}
if (!uwReadwritestatus) {
chprintf(chp, "SDRAM test completed successfully, writing entire memory took %dms, reading it took %dms.\r\n", write_ms, read_ms);
}
}
static const ShellCommand commands[] = {
{"mem", cmd_mem},
{"threads", cmd_threads},
{"test", cmd_test},
{"sdram", cmd_sdram},
{"reset", cmd_reset},
{"write", cmd_write},
{"check", cmd_check},
{"erase", cmd_erase},
{"selfrefresh", cmd_selfrefresh},
{"normal", cmd_normal},
{NULL, NULL}
};
@ -730,10 +613,10 @@ int main(void) {
#endif /* HAL_USE_SERIAL_USB */
/*
* Initialise SDRAM, board.h has already configured GPIO correctly
* (except that ST example uses 50MHz not 100MHz?)
* Initialise FSMC for SDRAM.
*/
SDRAM_Init();
fsmcSdramInit();
fsmcSdramStart(&SDRAMD, &sdram_cfg);
sdram_bulk_erase();
/*

5
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf.h
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@ -352,4 +352,9 @@
#define STM32_DMA2D_USE_DMA2D TRUE
#define STM32_DMA2D_IRQ_PRIORITY 11
/*
* Header for community drivers.
*/
#include "mcuconf_community.h"
#endif /* _MCUCONF_H_ */

28
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h Normal file
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@ -0,0 +1,28 @@
/*
ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* FSMC driver system settings.
*/
#define STM32_FSMC_USE_FSMC1 TRUE
#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10
/*
* FSMC SDRAM driver system settings.
*/
#define STM32_USE_FSMC_SDRAM TRUE
#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE
#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE

332
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f429i_discovery_sdram.c
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@ -1,332 +0,0 @@
#include "ch.h"
#include "hal.h"
#include "stm32f429i_discovery_sdram.h"
#include "stm32f4xx_fmc.h"
/**
* @brief Configures the FMC and GPIOs to interface with the SDRAM memory.
* This function must be called before any read/write operation
* on the SDRAM.
* @param None
* @retval None
*/
void SDRAM_Init(void)
{
FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure;
FMC_SDRAMTimingInitTypeDef FMC_SDRAMTimingInitStructure;
/* Enable FMC clock */
rccEnableAHB3(RCC_AHB3ENR_FMCEN, FALSE);
/* FMC Configuration ---------------------------------------------------------*/
/* FMC SDRAM Bank configuration */
/* Timing configuration for 84 Mhz of SD clock frequency (168Mhz/2) */
/* TMRD: 2 Clock cycles */
FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
/* TXSR: min=70ns (6x11.90ns) */
FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7;
/* TRAS: min=42ns (4x11.90ns) max=120k (ns) */
FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
/* TRC: min=63 (6x11.90ns) */
FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 7;
/* TWR: 2 Clock cycles */
FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
/* TRP: 15ns => 2x11.90ns */
FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
/* TRCD: 15ns => 2x11.90ns */
FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
/* FMC SDRAM control configuration */
FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank2_SDRAM;
/* Row addressing: [7:0] */
FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
/* Column addressing: [11:0] */
FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b;
FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH;
FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
FMC_SDRAMInitStructure.FMC_CASLatency = SDRAM_CAS_LATENCY;
FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
FMC_SDRAMInitStructure.FMC_SDClockPeriod = SDCLOCK_PERIOD;
FMC_SDRAMInitStructure.FMC_ReadBurst = SDRAM_READBURST;
FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
/* FMC SDRAM bank initialization */
FMC_SDRAMInit(&FMC_SDRAMInitStructure);
/* FMC SDRAM device initialization sequence */
SDRAM_InitSequence();
}
/*-- GPIOs Configuration -----------------------------------------------------*/
/*
+-------------------+--------------------+--------------------+--------------------+
+ SDRAM pins assignment +
+-------------------+--------------------+--------------------+--------------------+
| PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
| PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
| PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG8 <-> FMC_SDCLK |
| PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG15 <-> FMC_NCAS |
| PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 |--------------------+
| PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 |
| PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS |
+-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 |
| PE13 <-> FMC_D10 | PF13 <-> FMC_A7 |
| PE14 <-> FMC_D11 | PF14 <-> FMC_A8 |
| PE15 <-> FMC_D12 | PF15 <-> FMC_A9 |
+-------------------+--------------------+--------------------+
| PB5 <-> FMC_SDCKE1|
| PB6 <-> FMC_SDNE1 |
| PC0 <-> FMC_SDNWE |
+-------------------+
*/
// /* Common GPIO configuration */
// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
// GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
//
// /* GPIOB configuration */
// GPIO_PinAFConfig(GPIOB, GPIO_PinSource5 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOB, GPIO_PinSource6 , GPIO_AF_FMC);
//
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6;
//
// GPIO_Init(GPIOB, &GPIO_InitStructure);
//
// /* GPIOC configuration */
// GPIO_PinAFConfig(GPIOC, GPIO_PinSource0 , GPIO_AF_FMC);
//
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
//
// GPIO_Init(GPIOC, &GPIO_InitStructure);
//
// /* GPIOD configuration */
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC);
//
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 |
// GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 |
// GPIO_Pin_15;
//
// GPIO_Init(GPIOD, &GPIO_InitStructure);
//
// /* GPIOE configuration */
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FMC);
//
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_7 |
// GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
// GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
// GPIO_Pin_14 | GPIO_Pin_15;
//
// GPIO_Init(GPIOE, &GPIO_InitStructure);
//
// /* GPIOF configuration */
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource11 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FMC);
//
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 |
// GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 |
// GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
// GPIO_Pin_14 | GPIO_Pin_15;
//
// GPIO_Init(GPIOF, &GPIO_InitStructure);
//
// /* GPIOG configuration */
// GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOG, GPIO_PinSource8 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOG, GPIO_PinSource15 , GPIO_AF_FMC);
//
//
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 |
// GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_15;
//
// GPIO_Init(GPIOG, &GPIO_InitStructure);
/**
* @brief Executes the SDRAM memory initialization sequence.
* @param None.
* @retval None.
*/
void SDRAM_InitSequence(void)
{
FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
uint32_t tmpr = 0;
/* Step 3 --------------------------------------------------------------------*/
/* Configure a clock configuration enable command */
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* Send the command */
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
//In the ST example, this is 100ms, but the 429 RM says 100us is typical, and
//the ISSI datasheet confirms this. 1ms seems plenty, and is much shorter than
//refresh interval, meaning we won't risk losing contents if the SDRAM is in self-refresh
//mode
/* Step 4 --------------------------------------------------------------------*/
/* Insert 1 ms delay */
chThdSleepMilliseconds(1);
/* Step 5 --------------------------------------------------------------------*/
/* Configure a PALL (precharge all) command */
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* Send the command */
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
/* Step 6 --------------------------------------------------------------------*/
/* Configure a Auto-Refresh command */
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* Send the first command */
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* Send the second command */
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
/* Step 7 --------------------------------------------------------------------*/
/* Program the external memory mode register */
tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 |
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
SDRAM_MODEREG_CAS_LATENCY_3 |
SDRAM_MODEREG_OPERATING_MODE_STANDARD |
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
/* Configure a load Mode register command*/
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr;
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* Send the command */
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
/* Step 8 --------------------------------------------------------------------*/
/* Set the refresh rate counter */
/* (7.81 us x Freq) - 20 */
/* Set the device refresh counter */
FMC_SetRefreshCount(683);
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
}
/**
* @brief Writes a Entire-word buffer to the SDRAM memory.
* @param pBuffer: pointer to buffer.
* @param uwWriteAddress: SDRAM memory internal address from which the data will be
* written.
* @param uwBufferSize: number of words to write.
* @retval None.
*/
void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize)
{
__IO uint32_t write_pointer = (uint32_t)uwWriteAddress;
/* Disable write protection */
FMC_SDRAMWriteProtectionConfig(FMC_Bank2_SDRAM, DISABLE);
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* While there is data to write */
for (; uwBufferSize != 0; uwBufferSize--)
{
/* Transfer data to the memory */
*(uint32_t *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++;
/* Increment the address*/
write_pointer += 4;
}
}
/**
* @brief Reads data buffer from the SDRAM memory.
* @param pBuffer: pointer to buffer.
* @param ReadAddress: SDRAM memory internal address from which the data will be
* read.
* @param uwBufferSize: number of words to write.
* @retval None.
*/
void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize)
{
__IO uint32_t write_pointer = (uint32_t)uwReadAddress;
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* Read data */
for(; uwBufferSize != 0x00; uwBufferSize--)
{
*pBuffer++ = *(__IO uint32_t *)(SDRAM_BANK_ADDR + write_pointer );
/* Increment the address*/
write_pointer += 4;
}
}

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demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f429i_discovery_sdram.h
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@ -1,96 +0,0 @@
/**
******************************************************************************
* @file stm32f429i_discovery_sdram.h
* @author MCD Application Team
* @version V1.0.0
* @date 20-September-2013
* @brief This file contains all the functions prototypes for the
* stm324x9i_disco_sdram.c driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32429I_DISCO_SDRAM_H
#define __STM32429I_DISCO_SDRAM_H
#ifdef __cplusplus
extern "C" {
#endif
//FIXME this should not be needed
#define STM32F429_439xx
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
/**
* @brief FMC SDRAM Bank address
*/
#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000)
/**
* @brief FMC SDRAM Memory Width
*/
/* #define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_8b */
#define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_16b
/**
* @brief FMC SDRAM CAS Latency
*/
/* #define SDRAM_CAS_LATENCY FMC_CAS_Latency_2 */
#define SDRAM_CAS_LATENCY FMC_CAS_Latency_3
/**
* @brief FMC SDRAM Memory clock period
*/
#define SDCLOCK_PERIOD FMC_SDClock_Period_2 /* Default configuration used with LCD */
/* #define SDCLOCK_PERIOD FMC_SDClock_Period_3 */
/**
* @brief FMC SDRAM Memory Read Burst feature
*/
#define SDRAM_READBURST FMC_Read_Burst_Disable /* Default configuration used with LCD */
/* #define SDRAM_READBURST FMC_Read_Burst_Enable */
/**
* @brief FMC SDRAM Mode definition register defines
*/
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
void SDRAM_Init(void);
void SDRAM_InitSequence(void);
void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize);
void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize);
#ifdef __cplusplus
}
#endif
#endif

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8
os/hal/ports/STM32/LLD/FSMCv1/fsmc.c
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@ -24,7 +24,7 @@
#include "hal.h"
#include "fsmc.h"
#if HAL_USE_NAND || STM32_USE_FSMC_SRAM || STM32_USE_FSMC_SDRAM || \
#if (HAL_USE_NAND || STM32_USE_FSMC_SRAM || STM32_USE_FSMC_SDRAM) || \
defined(__DOXYGEN__)
/*===========================================================================*/
@ -119,7 +119,7 @@ void fsmc_init(void) {
void fsmc_start(FSMCDriver *fsmcp) {
osalDbgAssert((fsmcp->state == FSMC_STOP) || (fsmcp->state == FSMC_READY),
"invalid state");
"invalid state");
if (fsmcp->state == FSMC_STOP) {
/* Enables the peripheral.*/
@ -174,12 +174,12 @@ CH_IRQ_HANDLER(STM32_FSMC_HANDLER) {
CH_IRQ_PROLOGUE();
#if STM32_NAND_USE_FSMC_NAND1
if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK){
if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK) {
NANDD1.isr_handler(&NANDD1);
}
#endif
#if STM32_NAND_USE_FSMC_NAND2
if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK){
if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK) {
NANDD2.isr_handler(&NANDD2);
}
#endif

2
os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c
View File

@ -102,7 +102,7 @@ static void _sdram_init_sequence(const SDRAMConfig *cfgp) {
SDRAMD.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target;
/* Step 4: Insert delay (tipically 100uS).*/
osalThreadSleepMilliseconds(100);
osalThreadSleepMilliseconds(1);
/* Step 5: Configure a PALL (precharge all) command.*/
_sdram_wait_ready();