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[Comp] Cleaning example, removing dependencies and adding checks.

This commit is contained in:
Fabien Poussin 2017-02-07 15:20:28 +01:00
parent 7059c87ab4
commit f4687bd298
4 changed files with 180 additions and 193 deletions
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230
os/hal/ports/STM32/LLD/COMPv1/hal_comp_lld.c
View File

@ -122,87 +122,157 @@ void comp_lld_init(void) {
#if STM32_COMP_USE_COMP1 #if STM32_COMP_USE_COMP1
/* Driver initialization.*/ /* Driver initialization.*/
compObjectInit(&COMPD1); compObjectInit(&COMPD1);
COMPD1.comp = COMP; COMPD1.reg = COMP;
COMPD1.reg->CSR = 0;
#if STM32_COMP_USE_INTERRUPTS
nvicEnableVector(COMP1_2_3_IRQn, STM32_COMP_1_2_3_IRQ_PRIORITY);
#endif
#endif #endif
#if STM32_COMP_USE_COMP2 #if STM32_COMP_USE_COMP2
/* Driver initialization.*/ /* Driver initialization.*/
compObjectInit(&COMPD2); compObjectInit(&COMPD2);
COMPD2.comp = COMP2; COMPD2.reg = COMP2;
COMPD2.reg->CSR = 0;
#if STM32_COMP_USE_INTERRUPTS
nvicEnableVector(COMP1_2_3_IRQn, STM32_COMP_1_2_3_IRQ_PRIORITY);
#endif
#endif #endif
#if STM32_COMP_USE_COMP3 #if STM32_COMP_USE_COMP3
/* Driver initialization.*/ /* Driver initialization.*/
compObjectInit(&COMPD3); compObjectInit(&COMPD3);
COMPD3.comp = COMP3; COMPD3.reg = COMP3;
COMPD3.reg->CSR = 0;
#if STM32_COMP_USE_INTERRUPTS
nvicEnableVector(COMP1_2_3_IRQn, STM32_COMP_1_2_3_IRQ_PRIORITY);
#endif
#endif #endif
#if STM32_COMP_USE_COMP4 #if STM32_COMP_USE_COMP4
/* Driver initialization.*/ /* Driver initialization.*/
compObjectInit(&COMPD4); compObjectInit(&COMPD4);
COMPD4.comp = COMP4; COMPD4.reg = COMP4;
COMPD4.reg->CSR = 0;
#if STM32_COMP_USE_INTERRUPTS
nvicEnableVector(COMP4_5_6_IRQn, STM32_COMP_1_2_3_IRQ_PRIORITY);
#endif
#endif #endif
#if STM32_COMP_USE_COMP5 #if STM32_COMP_USE_COMP5
/* Driver initialization.*/ /* Driver initialization.*/
compObjectInit(&COMPD5); compObjectInit(&COMPD5);
COMPD8.comp = COMP5; COMPD5.reg = COMP5;
COMPD5.reg->CSR = 0;
#if STM32_COMP_USE_INTERRUPTS
nvicEnableVector(COMP4_5_6_IRQn, STM32_COMP_1_2_3_IRQ_PRIORITY);
#endif
#endif #endif
#if STM32_COMP_USE_COMP6 #if STM32_COMP_USE_COMP6
/* Driver initialization.*/ /* Driver initialization.*/
compObjectInit(&COMPD6); compObjectInit(&COMPD6);
COMPD6.comp = COMP6; COMPD6.reg = COMP6;
COMPD6.reg->CSR = 0;
#if STM32_COMP_USE_INTERRUPTS
nvicEnableVector(COMP4_5_6_IRQn, STM32_COMP_1_2_3_IRQ_PRIORITY);
#endif
#endif #endif
#if STM32_COMP_USE_COMP7 #if STM32_COMP_USE_COMP7
/* Driver initialization.*/ /* Driver initialization.*/
compObjectInit(&COMPD7); compObjectInit(&COMPD7);
COMPD7.comp = COMP7; COMPD7.reg = COMP7;
COMPD7.reg->CSR = 0;
#if STM32_COMP_USE_INTERRUPTS
nvicEnableVector(COMP7_IRQn, STM32_COMP_7_IRQ_PRIORITY);
#endif
#endif #endif
} }
#if STM32_COMP_USE_INTERRUPTS
static void comp_lld_cb(EXTDriver *extp, expchannel_t channel) {
(void) extp; /**
switch (channel) { * @brief COMP1, COMP2, COMP3 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(Vector140) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & ((1U << 21) | (1U << 22) | (1U << 29));
EXTI->PR = pr;
#if STM32_COMP_USE_COMP1 #if STM32_COMP_USE_COMP1
case 21: if (pr & (1U << 21) && COMPD1.config->cb != NULL)
COMPD1.config->cb(&COMPD1); COMPD1.config->cb(&COMPD1);
#endif #endif
#if STM32_COMP_USE_COMP2 #if STM32_COMP_USE_COMP2
case 22: if (pr & (1U << 22) && COMPD2.config->cb != NULL)
COMPD2.config->cb(&COMPD2); COMPD2.config->cb(&COMPD2);
#endif #endif
#if STM32_COMP_USE_COMP3 #if STM32_COMP_USE_COMP3
case 29: if (pr & (1U << 29) && COMPD3.config->cb != NULL)
COMPD3.config->cb(&COMPD3); COMPD3.config->cb(&COMPD3);
#endif #endif
OSAL_IRQ_EPILOGUE();
}
/**
* @brief COMP4, COMP5, COMP6 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(Vector144) {
uint32_t pr;
OSAL_IRQ_PROLOGUE();
pr = EXTI->PR;
pr &= EXTI->IMR & ((1U << 30) | (1U << 31));
EXTI->PR = pr;
#if STM32_COMP_USE_COMP4 #if STM32_COMP_USE_COMP4
case 30: if (pr & (1U << 30) && COMPD4.config->cb != NULL)
COMPD4.config->cb(&COMPD4); COMPD4.config->cb(&COMPD4);
#endif #endif
#if STM32_COMP_USE_COMP5 #if STM32_COMP_USE_COMP5
case 31: if (pr & (1U << 31) && COMPD5.config->cb != NULL)
COMPD5.config->cb(&COMPD5); COMPD5.config->cb(&COMPD5);
#endif #endif
#if STM32_COMP_USE_COMP6
case 32:
COMPD6.config->cb(&COMPD6);
#endif
#if STM32_COMP_USE_COMP7
case 33:
COMPD7.config->cb(&COMPD7);
#endif
default:
return;
}
} #if STM32_COMP_USE_COMP6
pr = EXTI->PR2 & EXTI->IMR2 & (1U << 0);
EXTI->PR2 = pr;
if (pr & (1U << 0) && COMPD6.config->cb != NULL)
COMPD6.config->cb(&COMPD6);
#endif #endif
OSAL_IRQ_EPILOGUE();
}
/**
* @brief COMP7 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(Vector148) {
uint32_t pr2;
OSAL_IRQ_PROLOGUE();
pr2 = EXTI->PR2;
pr2 = EXTI->IMR & (1U << 1);
EXTI->PR2 = pr2;
#if STM32_COMP_USE_COMP7
if (pr2 & (1U << 1) && COMPD7.config->cb != NULL)
COMPD7.config->cb(&COMPD7);
#endif
OSAL_IRQ_EPILOGUE();
}
/** /**
* @brief Configures and activates the COMP peripheral. * @brief Configures and activates the COMP peripheral.
* *
@ -213,58 +283,11 @@ static void comp_lld_cb(EXTDriver *extp, expchannel_t channel) {
void comp_lld_start(COMPDriver *compp) { void comp_lld_start(COMPDriver *compp) {
// Apply CSR Execpt the enable bit. // Apply CSR Execpt the enable bit.
compp->comp->CSR = compp->config->csr & ~COMP_CSR_COMPxEN; compp->reg->CSR = compp->config->csr & ~COMP_CSR_COMPxEN;
// Inverted output // Inverted output
if (compp->config->mode == COMP_OUTPUT_INVERTED) if (compp->config->mode == COMP_OUTPUT_INVERTED)
compp->comp->CSR |= COMP_CSR_COMPxPOL; compp->reg->CSR |= COMP_CSR_COMPxPOL;
EXTChannelConfig chn_cfg = {EXT_CH_MODE_BOTH_EDGES, comp_lld_cb};
EXTConfig *cfg = (EXTConfig*)EXTD1.config;
#if STM32_COMP_USE_COMP1 && STM32_COMP_USE_INTERRUPTS
if (&COMPD1 == compp) {
cfg->channels[21] = chn_cfg;
ext_lld_channel_enable(&EXTD1, 21);
}
#endif
#if STM32_COMP_USE_COMP2 && STM32_COMP_USE_INTERRUPTS
if (&COMPD2 == compp) {
cfg->channels[22] = chn_cfg;
ext_lld_channel_enable(&EXTD1, 22);
}
#endif
#if STM32_COMP_USE_COMP3 && STM32_COMP_USE_INTERRUPTS
if (&COMPD3 == compp) {
cfg->channels[29] = chn_cfg;
ext_lld_channel_enable(&EXTD1, 29);
}
#endif
#if STM32_COMP_USE_COMP4 && STM32_COMP_USE_INTERRUPTS
if (&COMPD4 == compp) {
cfg->channels[30] = chn_cfg;
ext_lld_channel_enable(&EXTD1, 30);
}
#endif
#if STM32_COMP_USE_COMP5 && STM32_COMP_USE_INTERRUPTS
if (&COMPD5 == compp) {
cfg->channels[31] = chn_cfg;
ext_lld_channel_enable(&EXTD1, 31);
}
#endif
#if STM32_COMP_USE_COMP6 && STM32_COMP_USE_INTERRUPTS
if (&COMPD6 == compp) {
cfg->channels[32] = chn_cfg;
ext_lld_channel_enable(&EXTD1, 32);
}
#endif
#if STM32_COMP_USE_COMP7 && STM32_COMP_USE_INTERRUPTS
if (&COMPD7 == compp) {
cfg->channels[33] = chn_cfg;
ext_lld_channel_enable(&EXTD1, 33);
}
#endif
} }
@ -279,42 +302,7 @@ void comp_lld_stop(COMPDriver *compp) {
if (compp->state == COMP_READY) { if (compp->state == COMP_READY) {
compp->reg->CSR = 0;
#if STM32_COMP_USE_COMP1 && STM32_COMP_USE_INTERRUPTS
if (&COMPD1 == compp) {
ext_lld_channel_disable(&EXTD1, 21);
}
#endif
#if STM32_COMP_USE_COMP2 && STM32_COMP_USE_INTERRUPTS
if (&COMPD2 == compp) {
ext_lld_channel_disable(&EXTD1, 22);
}
#endif
#if STM32_COMP_USE_COMP3 && STM32_COMP_USE_INTERRUPTS
if (&COMPD3 == compp) {
ext_lld_channel_disable(&EXTD1, 29);
}
#endif
#if STM32_COMP_USE_COMP4 && STM32_COMP_USE_INTERRUPTS
if (&COMPD4 == compp) {
ext_lld_channel_disable(&EXTD1, 30);
}
#endif
#if STM32_COMP_USE_COMP5 && STM32_COMP_USE_INTERRUPTS
if (&COMPD5 == compp) {
ext_lld_channel_disable(&EXTD1, 31);
}
#endif
#if STM32_COMP_USE_COMP6 && STM32_COMP_USE_INTERRUPTS
if (&COMPD6 == compp) {
ext_lld_channel_disable(&EXTD1, 32);
}
#endif
#if STM32_COMP_USE_COMP7 && STM32_COMP_USE_INTERRUPTS
if (&COMPD7 == compp) {
ext_lld_channel_disable(&EXTD1, 33);
}
#endif
} }
} }
@ -327,8 +315,7 @@ void comp_lld_stop(COMPDriver *compp) {
*/ */
void comp_lld_enable(COMPDriver *compp) { void comp_lld_enable(COMPDriver *compp) {
compp->comp->CSR |= COMP_CSR_COMPxEN; /* Enable */ compp->reg->CSR |= COMP_CSR_COMPxEN; /* Enable */
} }
/** /**
@ -340,8 +327,7 @@ void comp_lld_enable(COMPDriver *compp) {
*/ */
void comp_lld_disable(COMPDriver *compp) { void comp_lld_disable(COMPDriver *compp) {
compp->comp->CSR &= ~COMP_CSR_COMPxEN; /* Disable */ compp->reg->CSR &= ~COMP_CSR_COMPxEN; /* Disable */
} }
#endif /* HAL_USE_COMP */ #endif /* HAL_USE_COMP */

72
os/hal/ports/STM32/LLD/COMPv1/hal_comp_lld.h
View File

@ -34,39 +34,51 @@
/* Driver constants. */ /* Driver constants. */
/*===========================================================================*/ /*===========================================================================*/
#if defined(STM32F303x8) #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F303x8) \
|| defined(STM32F318xx) || defined(STM32F328xx) || defined(STM32F334x8)
#define STM32_HAS_COMP1 FALSE #define STM32_HAS_COMP1 FALSE
#define STM32_HAS_COMP2 TRUE #define STM32_HAS_COMP2 TRUE
#define STM32_HAS_COMP3 FALSE #define STM32_HAS_COMP3 FALSE
#define STM32_HAS_COMP4 TRUE #define STM32_HAS_COMP4 TRUE
#define STM32_HAS_COMP5 FALSE #define STM32_HAS_COMP5 FALSE
#define STM32_HAS_COMP6 TRUE
#define STM32_HAS_COMP7 FALSE
#elif defined(STM32F302xc) || defined(STM32F302xe)
#define STM32_HAS_COMP1 TRUE
#define STM32_HAS_COMP2 TRUE
#define STM32_HAS_COMP3 FALSE
#define STM32_HAS_COMP4 TRUE
#define STM32_HAS_COMP5 FALSE
#define STM32_HAS_COMP6 TRUE
#define STM32_HAS_COMP7 FALSE
#elif defined(STM32F303xC) || defined(STM32F303xE) || defined(STM32F358xx) || defined(STM32F398xx)
#define STM32_HAS_COMP1 TRUE
#define STM32_HAS_COMP2 TRUE
#define STM32_HAS_COMP3 TRUE
#define STM32_HAS_COMP4 TRUE
#define STM32_HAS_COMP5 TRUE
#define STM32_HAS_COMP6 TRUE
#define STM32_HAS_COMP7 TRUE
#elif defined(STM32F373xx) || defined(STM32F378xx) || defined(STM32L0XX) || defined(STM32L1XX)
#define STM32_HAS_COMP1 TRUE
#define STM32_HAS_COMP2 TRUE
#define STM32_HAS_COMP3 FALSE
#define STM32_HAS_COMP4 FALSE
#define STM32_HAS_COMP5 FALSE
#define STM32_HAS_COMP6 FALSE #define STM32_HAS_COMP6 FALSE
#define STM32_HAS_COMP7 FALSE #define STM32_HAS_COMP7 FALSE
#endif #else
#define STM32_HAS_COMP1 FALSE
#if defined(STM32F303xC) #define STM32_HAS_COMP2 FALSE
#define STM32_HAS_COMP3 FALSE
#define STM32_HAS_COMP1 TRUE #define STM32_HAS_COMP4 FALSE
#define STM32_HAS_COMP2 TRUE #define STM32_HAS_COMP5 FALSE
#define STM32_HAS_COMP3 TRUE #define STM32_HAS_COMP6 FALSE
#define STM32_HAS_COMP4 TRUE #define STM32_HAS_COMP7 FALSE
#define STM32_HAS_COMP5 TRUE
#define STM32_HAS_COMP6 TRUE
#define STM32_HAS_COMP7 TRUE
#endif
#if defined(STM32F303xE)
#define STM32_HAS_COMP1 TRUE
#define STM32_HAS_COMP2 TRUE
#define STM32_HAS_COMP3 TRUE
#define STM32_HAS_COMP4 TRUE
#define STM32_HAS_COMP5 TRUE
#define STM32_HAS_COMP6 TRUE
#define STM32_HAS_COMP7 TRUE
#endif #endif
@ -157,12 +169,10 @@
/* Derived constants and error checks. */ /* Derived constants and error checks. */
/*===========================================================================*/ /*===========================================================================*/
#if STM32_COMP_USE_INTERRUPTS && !HAL_USE_EXT
#error "COMP needs HAL_USE_EXT to use interrupts"
#endif
#if STM32_COMP_USE_INTERRUPTS #if STM32_COMP_USE_INTERRUPTS
#include "hal_ext_lld.h" #if !defined(STM32_DISABLE_EXTI21_22_29_HANDLER) || !defined(STM32_DISABLE_EXTI30_32_HANDLER) || !defined(STM32_DISABLE_EXTI33_HANDLER)
#error "COMP needs these defines in mcuconf to use interrupts: STM32_DISABLE_EXTI21_22_29_HANDLER STM32_DISABLE_EXTI30_32_HANDLER STM32_DISABLE_EXTI33_HANDLER"
#endif
#endif #endif
#if STM32_COMP_USE_COMP1 && !STM32_HAS_COMP1 #if STM32_COMP_USE_COMP1 && !STM32_HAS_COMP1
@ -256,7 +266,7 @@ struct COMPDriver {
/** /**
* @brief Pointer to the COMPx registers block. * @brief Pointer to the COMPx registers block.
*/ */
COMP_TypeDef *comp; COMP_TypeDef *reg;
}; };
/*===========================================================================*/ /*===========================================================================*/

48
testhal/STM32/STM32F3xx/COMP/main.c
View File

@ -17,44 +17,30 @@
#include "ch.h" #include "ch.h"
#include "hal.h" #include "hal.h"
static const EXTConfig extcfg = { void comp2_cb(COMPDriver *comp) {
{
{EXT_CH_MODE_DISABLED, NULL}, if (comp->reg->CSR & COMP_CSR_COMPxOUT) {
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL}
} }
};
}
void comp4_cb(COMPDriver *comp) {
(void) comp;
}
static const COMPConfig comp2_conf = { static const COMPConfig comp2_conf = {
COMP_OUTPUT_NORMAL, COMP_OUTPUT_NORMAL,
NULL, comp2_cb,
0 COMP_CSR_COMPxINSEL_0 | COMP_CSR_COMPxOUTSEL_0 // CSR
}; };
static const COMPConfig comp4_conf = { static const COMPConfig comp4_conf = {
COMP_OUTPUT_INVERTED, COMP_OUTPUT_INVERTED,
NULL, comp4_cb,
0 COMP_CSR_COMPxINSEL_0 | COMP_CSR_COMPxOUTSEL_1 // CSR
}; };
@ -66,7 +52,6 @@ int main(void) {
halInit(); halInit();
chSysInit(); chSysInit();
extStart(&EXTD1, &extcfg);
compStart(&COMPD2, &comp2_conf); compStart(&COMPD2, &comp2_conf);
compStart(&COMPD4, &comp4_conf); compStart(&COMPD4, &comp4_conf);
@ -74,7 +59,6 @@ int main(void) {
* Normal main() thread activity, it resets the watchdog. * Normal main() thread activity, it resets the watchdog.
*/ */
while (true) { while (true) {
palToggleLine(LINE_LED4_BLUE);
chThdSleepMilliseconds(500); chThdSleepMilliseconds(500);
} }
return 0; return 0;

23
testhal/STM32/STM32F3xx/COMP/mcuconf_community.h
View File

@ -64,15 +64,22 @@
/* /*
* COMP driver system settings. * COMP driver system settings.
* IRQ priority is set with the EXT driver (lines 21-22, 29-33)
*/ */
#define STM32_COMP_USE_COMP1 FALSE #define STM32_COMP_USE_COMP1 TRUE
#define STM32_COMP_USE_COMP2 TRUE #define STM32_COMP_USE_COMP2 TRUE
#define STM32_COMP_USE_COMP3 FALSE #define STM32_COMP_USE_COMP3 TRUE
#define STM32_COMP_USE_COMP4 TRUE #define STM32_COMP_USE_COMP4 TRUE
#define STM32_COMP_USE_COMP5 FALSE #define STM32_COMP_USE_COMP5 TRUE
#define STM32_COMP_USE_COMP6 FALSE #define STM32_COMP_USE_COMP6 TRUE
#define STM32_COMP_USE_COMP7 FALSE #define STM32_COMP_USE_COMP7 TRUE
#define STM32_COMP_USE_INTERRUPTS TRUE
#define STM32_COMP_USE_INTERRUPTS TRUE
#define STM32_COMP_1_2_3_IRQ_PRIORITY 5
#define STM32_COMP_4_5_6_IRQ_PRIORITY 5
#define STM32_COMP_7_IRQ_PRIORITY 5
#if STM32_COMP_USE_INTERRUPTS
#define STM32_DISABLE_EXTI21_22_29_HANDLER
#define STM32_DISABLE_EXTI30_32_HANDLER
#define STM32_DISABLE_EXTI33_HANDLER
#endif