diff --git a/os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.c b/os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.c index 3a50ebc8..d08a1303 100644 --- a/os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.c +++ b/os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.c @@ -124,9 +124,6 @@ static const dacparams_t dac1_ch1_params = { .regshift = 0U, .regmask = 0xFFFF0000U, .dmastream = GD32_DAC_DAC1_CH1_DMA_STREAM, -#if GD32_DMA_SUPPORTS_DMAMUX - .peripheral = GD32_DMAMUX1_DAC1_CH1, -#endif .dmamode = GD32_DMA_CTL_CHSEL(DAC1_CH1_DMA_CHANNEL) | GD32_DMA_CTL_PRIO(GD32_DAC_DAC1_CH1_DMA_PRIORITY) | GD32_DMA_CTL_MNAGA | GD32_DMA_CTL_CMEN | GD32_DMA_CTL_DIR_M2P | @@ -143,9 +140,6 @@ static const dacparams_t dac1_ch2_params = { .regshift = 16U, .regmask = 0x0000FFFFU, .dmastream = GD32_DAC_DAC1_CH2_DMA_STREAM, -#if GD32_DMA_SUPPORTS_DMAMUX - .peripheral = GD32_DMAMUX1_DAC1_CH2, -#endif .dmamode = GD32_DMA_CTL_CHSEL(DAC1_CH2_DMA_CHANNEL) | GD32_DMA_CTL_PRIO(GD32_DAC_DAC1_CH2_DMA_PRIORITY) | GD32_DMA_CTL_MNAGA | GD32_DMA_CTL_CMEN | GD32_DMA_CTL_DIR_M2P | @@ -162,9 +156,6 @@ static const dacparams_t dac2_ch1_params = { .regshift = 0U, .regmask = 0xFFFF0000U, .dmastream = GD32_DAC_DAC2_CH1_DMA_STREAM, -#if GD32_DMA_SUPPORTS_DMAMUX - .peripheral = GD32_DMAMUX1_DAC2_CH1, -#endif .dmamode = GD32_DMA_CTL_CHSEL(DAC2_CH1_DMA_CHANNEL) | GD32_DMA_CTL_PRIO(GD32_DAC_DAC2_CH1_DMA_PRIORITY) | GD32_DMA_CTL_MNAGA | GD32_DMA_CTL_CMEN | GD32_DMA_CTL_DIR_M2P | @@ -181,9 +172,6 @@ static const dacparams_t dac2_ch2_params = { .regshift = 16U, .regmask = 0x0000FFFFU, .dmastream = GD32_DAC_DAC2_CH2_DMA_STREAM, -#if GD32_DMA_SUPPORTS_DMAMUX - .peripheral = GD32_DMAMUX1_DAC2_CH2, -#endif .dmamode = GD32_DMA_CTL_CHSEL(DAC2_CH2_DMA_CHANNEL) | GD32_DMA_CTL_PRIO(GD32_DAC_DAC2_CH2_DMA_PRIORITY) | GD32_DMA_CTL_MNAGA | GD32_DMA_CTL_CMEN | GD32_DMA_CTL_DIR_M2P | @@ -433,23 +421,23 @@ void dac_lld_start(DACDriver *dacp) { zero.*/ #if GD32_DAC_DUAL_MODE == FALSE { - uint32_t cr; + uint32_t ctl; - cr = dacp->params->dac->CR; - cr &= dacp->params->regmask; - cr |= (DAC_CR_EN1 | dacp->config->cr) << dacp->params->regshift; - dacp->params->dac->CR = cr; + ctl = dacp->params->dac->CTL; + ctl &= dacp->params->regmask; + ctl |= (DAC_CTL_DEN0 | dacp->config->ctl) << dacp->params->regshift; + dacp->params->dac->CTL = ctl; dac_lld_put_channel(dacp, channel, dacp->config->init); } #else if ((dacp->config->datamode == DAC_DHRM_12BIT_RIGHT_DUAL) || (dacp->config->datamode == DAC_DHRM_12BIT_LEFT_DUAL) || (dacp->config->datamode == DAC_DHRM_8BIT_RIGHT_DUAL)) { - dacp->params->dac->CR = DAC_CR_EN2 | (dacp->config->cr << 16) | DAC_CR_EN1 | dacp->config->cr; + dacp->params->dac->CTL = DAC_CTL_DEN1 | (dacp->config->ctl << 16) | DAC_CTL_DEN0 | dacp->config->ctl; dac_lld_put_channel(dacp, 1U, dacp->config->init); } else { - dacp->params->dac->CR = DAC_CR_EN1 | dacp->config->cr; + dacp->params->dac->CTL = DAC_CTL_DEN0 | dacp->config->ctl; } dac_lld_put_channel(dacp, channel, dacp->config->init); #endif @@ -469,11 +457,11 @@ void dac_lld_stop(DACDriver *dacp) { if (dacp->state == DAC_READY) { /* Disabling DAC.*/ - dacp->params->dac->CR &= dacp->params->regmask; + dacp->params->dac->CTL &= dacp->params->regmask; #if GD32_DAC_USE_DAC1_CH1 if (&DACD1 == dacp) { - if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) { + if ((dacp->params->dac->CTL & DAC_CTL_DEN1) == 0U) { rccDisableDAC1(); } } @@ -481,7 +469,7 @@ void dac_lld_stop(DACDriver *dacp) { #if GD32_DAC_USE_DAC1_CH2 if (&DACD2 == dacp) { - if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) { + if ((dacp->params->dac->CTL & DAC_CTL_DEN0) == 0U) { rccDisableDAC1(); } } @@ -489,7 +477,7 @@ void dac_lld_stop(DACDriver *dacp) { #if GD32_DAC_USE_DAC2_CH1 if (&DACD3 == dacp) { - if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) { + if ((dacp->params->dac->CTL & DAC_CTL_DEN1) == 0U) { rccDisableDAC2(); } } @@ -497,7 +485,7 @@ void dac_lld_stop(DACDriver *dacp) { #if GD32_DAC_USE_DAC2_CH2 if (&DACD4 == dacp) { - if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) { + if ((dacp->params->dac->CTL & DAC_CTL_DEN0) == 0U) { rccDisableDAC2(); } } @@ -505,7 +493,7 @@ void dac_lld_stop(DACDriver *dacp) { #if GD32_DAC_USE_DAC3_CH1 if (&DACD5 == dacp) { - if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) { + if ((dacp->params->dac->CTL & DAC_CTL_DEN1) == 0U) { rccDisableDAC3(); } } @@ -513,7 +501,7 @@ void dac_lld_stop(DACDriver *dacp) { #if GD32_DAC_USE_DAC3_CH2 if (&DACD6 == dacp) { - if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) { + if ((dacp->params->dac->CTL & DAC_CTL_DEN0) == 0U) { rccDisableDAC3(); } } @@ -521,7 +509,7 @@ void dac_lld_stop(DACDriver *dacp) { #if GD32_DAC_USE_DAC4_CH1 if (&DACD7 == dacp) { - if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) { + if ((dacp->params->dac->CTL & DAC_CTL_DEN1) == 0U) { rccDisableDAC4(); } } @@ -529,7 +517,7 @@ void dac_lld_stop(DACDriver *dacp) { #if GD32_DAC_USE_DAC4_CH2 if (&DACD8 == dacp) { - if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) { + if ((dacp->params->dac->CTL & DAC_CTL_DEN0) == 0U) { rccDisableDAC4(); } } @@ -557,15 +545,15 @@ void dac_lld_put_channel(DACDriver *dacp, #endif if (channel == 0U) { #if GD32_DAC_DUAL_MODE - dacp->params->dac->DHR12R1 = (uint32_t)sample; + dacp->params->dac->R12DH0 = (uint32_t)sample; #else - *(&dacp->params->dac->DHR12R1 + dacp->params->dataoffset) = (uint32_t)sample; + *(&dacp->params->dac->R12DH0 + dacp->params->dataoffset) = (uint32_t)sample; #endif } #if (GD32_HAS_DAC1_CH2 || GD32_HAS_DAC2_CH2 || \ GD32_HAS_DAC3_CH2 || GD32_HAS_DAC4_CH2) else { - dacp->params->dac->DHR12R2 = (uint32_t)sample; + dacp->params->dac->R12DH1 = (uint32_t)sample; } #endif break; @@ -575,15 +563,15 @@ void dac_lld_put_channel(DACDriver *dacp, #endif if (channel == 0U) { #if GD32_DAC_DUAL_MODE - dacp->params->dac->DHR12L1 = (uint32_t)sample; + dacp->params->dac->L12DH0 = (uint32_t)sample; #else - *(&dacp->params->dac->DHR12L1 + dacp->params->dataoffset) = (uint32_t)sample; + *(&dacp->params->dac->L12DH0 + dacp->params->dataoffset) = (uint32_t)sample; #endif } #if (GD32_HAS_DAC1_CH2 || GD32_HAS_DAC2_CH2 || \ GD32_HAS_DAC3_CH2 || GD32_HAS_DAC4_CH2) else { - dacp->params->dac->DHR12L2 = (uint32_t)sample; + dacp->params->dac->L12DH1 = (uint32_t)sample; } #endif break; @@ -593,15 +581,15 @@ void dac_lld_put_channel(DACDriver *dacp, #endif if (channel == 0U) { #if GD32_DAC_DUAL_MODE - dacp->params->dac->DHR8R1 = (uint32_t)sample; + dacp->params->dac->R8DH0 = (uint32_t)sample; #else - *(&dacp->params->dac->DHR8R1 + dacp->params->dataoffset) = (uint32_t)sample; + *(&dacp->params->dac->R8DH0 + dacp->params->dataoffset) = (uint32_t)sample; #endif } #if (GD32_HAS_DAC1_CH2 || GD32_HAS_DAC2_CH2 || \ GD32_HAS_DAC3_CH2 || GD32_HAS_DAC4_CH2) else { - dacp->params->dac->DHR8R2 = (uint32_t)sample; + dacp->params->dac->R8DH1 = (uint32_t)sample; } #endif break; @@ -628,7 +616,7 @@ void dac_lld_put_channel(DACDriver *dacp, * @notapi */ void dac_lld_start_conversion(DACDriver *dacp) { - uint32_t n, cr, dmamode; + uint32_t n, ctl, dmamode; /* Number of DMA operations per buffer.*/ n = dacp->depth * dacp->grpp->num_channels; @@ -649,7 +637,7 @@ void dac_lld_start_conversion(DACDriver *dacp) { case DAC_DHRM_12BIT_RIGHT: osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels"); - dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12R1 + + dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->R12DH0 + dacp->params->dataoffset); dmamode = dacp->params->dmamode | GD32_DMA_CTL_PWIDTH_HWORD | GD32_DMA_CTL_MWIDTH_HWORD; @@ -657,7 +645,7 @@ void dac_lld_start_conversion(DACDriver *dacp) { case DAC_DHRM_12BIT_LEFT: osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels"); - dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12L1 + + dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->L12DH0 + dacp->params->dataoffset); dmamode = dacp->params->dmamode | GD32_DMA_CTL_PWIDTH_HWORD | GD32_DMA_CTL_MWIDTH_HWORD; @@ -665,7 +653,7 @@ void dac_lld_start_conversion(DACDriver *dacp) { case DAC_DHRM_8BIT_RIGHT: osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels"); - dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR8R1 + + dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->R8DH0 + dacp->params->dataoffset); dmamode = dacp->params->dmamode | GD32_DMA_CTL_PWIDTH_BYTE | GD32_DMA_CTL_MWIDTH_BYTE; @@ -678,7 +666,7 @@ void dac_lld_start_conversion(DACDriver *dacp) { case DAC_DHRM_12BIT_RIGHT_DUAL: osalDbgAssert(dacp->grpp->num_channels == 2, "invalid number of channels"); - dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12RD); + dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->R12DH); dmamode = dacp->params->dmamode | GD32_DMA_CTL_PWIDTH_WORD | GD32_DMA_CTL_MWIDTH_WORD; n /= 2; @@ -686,7 +674,7 @@ void dac_lld_start_conversion(DACDriver *dacp) { case DAC_DHRM_12BIT_LEFT_DUAL: osalDbgAssert(dacp->grpp->num_channels == 2, "invalid number of channels"); - dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12LD); + dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->L12DH); dmamode = dacp->params->dmamode | GD32_DMA_CTL_PWIDTH_WORD | GD32_DMA_CTL_MWIDTH_WORD; n /= 2; @@ -694,7 +682,7 @@ void dac_lld_start_conversion(DACDriver *dacp) { case DAC_DHRM_8BIT_RIGHT_DUAL: osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels"); - dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR8RD); + dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->R8DH); dmamode = dacp->params->dmamode | GD32_DMA_CTL_PWIDTH_HWORD | GD32_DMA_CTL_MWIDTH_HWORD; n /= 2; @@ -713,17 +701,17 @@ void dac_lld_start_conversion(DACDriver *dacp) { dmaStreamEnable(dacp->dma); /* DAC configuration.*/ - cr = dacp->params->dac->CR; + ctl = dacp->params->dac->CTL; #if GD32_DAC_DUAL_MODE == FALSE - cr &= dacp->params->regmask; - cr |= (DAC_CR_DMAEN1 | (dacp->grpp->trigger << DAC_CR_TSEL1_Pos) | DAC_CR_TEN1 | DAC_CR_EN1 | dacp->config->cr) << dacp->params->regshift; + ctl &= dacp->params->regmask; + ctl |= (DAC_CTL_DDMAEN0 | (dacp->grpp->trigger << DAC_CTL_DTSEL0_Pos) | DAC_CTL_DTEN0 | DAC_CTL_DEN0 | dacp->config->ctl) << dacp->params->regshift; #else - cr = DAC_CR_DMAEN1 | (dacp->grpp->trigger << DAC_CR_TSEL1_Pos) | DAC_CR_TEN1 | DAC_CR_EN1 | dacp->config->cr - | (dacp->grpp->trigger << DAC_CR_TSEL2_Pos) | DAC_CR_TEN2 | DAC_CR_EN2 | (dacp->config->cr << 16); + ctl = DAC_CTL_DDMAEN0 | (dacp->grpp->trigger << DAC_CTL_DTSEL0_Pos) | DAC_CTL_DTEN0 | DAC_CTL_DEN0 | dacp->config->ctl + | (dacp->grpp->trigger << DAC_CTL_DTSEL1_Pos) | DAC_CTL_DTEN1 | DAC_CTL_DEN1 | (dacp->config->ctl << 16); #endif - dacp->params->dac->CR = cr; + dacp->params->dac->CTL = ctl; } /** @@ -737,31 +725,31 @@ void dac_lld_start_conversion(DACDriver *dacp) { * @iclass */ void dac_lld_stop_conversion(DACDriver *dacp) { - uint32_t cr; + uint32_t ctl; /* DMA channel disabled and released.*/ dmaStreamDisable(dacp->dma); dmaStreamFreeI(dacp->dma); dacp->dma = NULL; - cr = dacp->params->dac->CR; + ctl = dacp->params->dac->CTL; #if GD32_DAC_DUAL_MODE == FALSE - cr &= dacp->params->regmask; - cr |= (DAC_CR_EN1 | dacp->config->cr) << dacp->params->regshift; + ctl &= dacp->params->regmask; + ctl |= (DAC_CTL_DEN0 | dacp->config->ctl) << dacp->params->regshift; #else if ((dacp->config->datamode == DAC_DHRM_12BIT_RIGHT_DUAL) || (dacp->config->datamode == DAC_DHRM_12BIT_LEFT_DUAL) || (dacp->config->datamode == DAC_DHRM_8BIT_RIGHT_DUAL)) { - cr = DAC_CR_EN2 | (dacp->config->cr << 16) | - DAC_CR_EN1 | dacp->config->cr; + ctl = DAC_CTL_DEN1 | (dacp->config->ctl << 16) | + DAC_CTL_DEN0 | dacp->config->ctl; } else { - cr = DAC_CR_EN1 | dacp->config->cr; + ctl = DAC_CTL_DEN0 | dacp->config->ctl; } #endif - dacp->params->dac->CR = cr; + dacp->params->dac->CTL = ctl; } #endif /* HAL_USE_DAC */ diff --git a/os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.h b/os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.h index cc323a8c..148e204b 100644 --- a/os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.h +++ b/os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.h @@ -539,12 +539,6 @@ typedef struct { * @brief DMA channel IRQ priority. */ uint32_t dmairqprio; -#if (GD32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(__DOXYGEN__) - /** - * @brief DMAMUX peripheral selector. - */ - uint32_t peripheral; -#endif } dacparams_t; /** @@ -593,7 +587,7 @@ typedef enum { /* DAC data holding register mode.*/ \ dacdhrmode_t datamode; \ /* DAC control register lower 16 bits.*/ \ - uint32_t cr + uint32_t ctl /** * @brief Low level fields of the DAC group configuration structure. diff --git a/os/hal/ports/GD/GD32VF103/stm32f105xc.h b/os/hal/ports/GD/GD32VF103/stm32f105xc.h index af5ed447..033cf500 100644 --- a/os/hal/ports/GD/GD32VF103/stm32f105xc.h +++ b/os/hal/ports/GD/GD32VF103/stm32f105xc.h @@ -260,19 +260,19 @@ typedef struct typedef struct { - __IO uint32_t CR; - __IO uint32_t SWTRIGR; - __IO uint32_t DHR12R1; - __IO uint32_t DHR12L1; - __IO uint32_t DHR8R1; - __IO uint32_t DHR12R2; - __IO uint32_t DHR12L2; - __IO uint32_t DHR8R2; - __IO uint32_t DHR12RD; - __IO uint32_t DHR12LD; - __IO uint32_t DHR8RD; - __IO uint32_t DOR1; - __IO uint32_t DOR2; + __IO uint32_t CTL; + __IO uint32_t SWT; + __IO uint32_t R12DH0; + __IO uint32_t L12DH0; + __IO uint32_t R8DH0; + __IO uint32_t R12DH1; + __IO uint32_t L12DH1; + __IO uint32_t R8DH1; + __IO uint32_t R12DH; + __IO uint32_t L12DH; + __IO uint32_t R8DH; + __IO uint32_t DO0; + __IO uint32_t DO1; } DAC_TypeDef; /** @@ -4442,75 +4442,75 @@ typedef struct /* */ /******************************************************************************/ -/******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1_Pos (0U) -#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */ -#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ -#define DAC_CR_BOFF1_Pos (1U) -#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ -#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */ -#define DAC_CR_TEN1_Pos (2U) -#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ -#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */ +/******************** Bit definition for DAC_CTL register ********************/ +#define DAC_CTL_DEN0_Pos (0U) +#define DAC_CTL_DEN0_Msk (0x1U << DAC_CTL_DEN0_Pos) /*!< 0x00000001 */ +#define DAC_CTL_DEN0 DAC_CTL_DEN0_Msk /*!< DAC channel1 enable */ +#define DAC_CTL_DBOFF0_Pos (1U) +#define DAC_CTL_DBOFF0_Msk (0x1U << DAC_CTL_DBOFF0_Pos) /*!< 0x00000002 */ +#define DAC_CTL_DBOFF0 DAC_CTL_DBOFF0_Msk /*!< DAC channel1 output buffer disable */ +#define DAC_CTL_DTEN0_Pos (2U) +#define DAC_CTL_DTEN0_Msk (0x1U << DAC_CTL_DTEN0_Pos) /*!< 0x00000004 */ +#define DAC_CTL_DTEN0 DAC_CTL_DTEN0_Msk /*!< DAC channel1 Trigger enable */ -#define DAC_CR_TSEL1_Pos (3U) -#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ -#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ -#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ -#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ +#define DAC_CTL_DTSEL0_Pos (3U) +#define DAC_CTL_DTSEL0_Msk (0x7U << DAC_CTL_DTSEL0_Pos) /*!< 0x00000038 */ +#define DAC_CTL_DTSEL0 DAC_CTL_DTSEL0_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CTL_DTSEL0_0 (0x1U << DAC_CTL_DTSEL0_Pos) /*!< 0x00000008 */ +#define DAC_CTL_DTSEL0_1 (0x2U << DAC_CTL_DTSEL0_Pos) /*!< 0x00000010 */ +#define DAC_CTL_DTSEL0_2 (0x4U << DAC_CTL_DTSEL0_Pos) /*!< 0x00000020 */ -#define DAC_CR_WAVE1_Pos (6U) -#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ -#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ -#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ +#define DAC_CTL_DWM0_Pos (6U) +#define DAC_CTL_DWM0_Msk (0x3U << DAC_CTL_DWM0_Pos) /*!< 0x000000C0 */ +#define DAC_CTL_DWM0 DAC_CTL_DWM0_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_CTL_DWM0_0 (0x1U << DAC_CTL_DWM0_Pos) /*!< 0x00000040 */ +#define DAC_CTL_DWM0_1 (0x2U << DAC_CTL_DWM0_Pos) /*!< 0x00000080 */ -#define DAC_CR_MAMP1_Pos (8U) -#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ -#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ -#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ -#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ -#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ -#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ +#define DAC_CTL_DWBW0_Pos (8U) +#define DAC_CTL_DWBW0_Msk (0xFU << DAC_CTL_DWBW0_Pos) /*!< 0x00000F00 */ +#define DAC_CTL_DWBW0 DAC_CTL_DWBW0_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_CTL_DWBW0_0 (0x1U << DAC_CTL_DWBW0_Pos) /*!< 0x00000100 */ +#define DAC_CTL_DWBW0_1 (0x2U << DAC_CTL_DWBW0_Pos) /*!< 0x00000200 */ +#define DAC_CTL_DWBW0_2 (0x4U << DAC_CTL_DWBW0_Pos) /*!< 0x00000400 */ +#define DAC_CTL_DWBW0_3 (0x8U << DAC_CTL_DWBW0_Pos) /*!< 0x00000800 */ -#define DAC_CR_DMAEN1_Pos (12U) -#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ -#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ -#define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ -#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */ -#define DAC_CR_BOFF2_Pos (17U) -#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ -#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */ -#define DAC_CR_TEN2_Pos (18U) -#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ -#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */ +#define DAC_CTL_DDMAEN0_Pos (12U) +#define DAC_CTL_DDMAEN0_Msk (0x1U << DAC_CTL_DDMAEN0_Pos) /*!< 0x00001000 */ +#define DAC_CTL_DDMAEN0 DAC_CTL_DDMAEN0_Msk /*!< DAC channel1 DMA enable */ +#define DAC_CTL_DEN1_Pos (16U) +#define DAC_CTL_DEN1_Msk (0x1U << DAC_CTL_DEN1_Pos) /*!< 0x00010000 */ +#define DAC_CTL_DEN1 DAC_CTL_DEN1_Msk /*!< DAC channel2 enable */ +#define DAC_CTL_DBOFF1_Pos (17U) +#define DAC_CTL_DBOFF1_Msk (0x1U << DAC_CTL_DBOFF1_Pos) /*!< 0x00020000 */ +#define DAC_CTL_DBOFF1 DAC_CTL_DBOFF1_Msk /*!< DAC channel2 output buffer disable */ +#define DAC_CTL_DTEN1_Pos (18U) +#define DAC_CTL_DTEN1_Msk (0x1U << DAC_CTL_DTEN1_Pos) /*!< 0x00040000 */ +#define DAC_CTL_DTEN1 DAC_CTL_DTEN1_Msk /*!< DAC channel2 Trigger enable */ -#define DAC_CR_TSEL2_Pos (19U) -#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ -#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ -#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ -#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ -#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ +#define DAC_CTL_DTSEL1_Pos (19U) +#define DAC_CTL_DTSEL1_Msk (0x7U << DAC_CTL_DTSEL1_Pos) /*!< 0x00380000 */ +#define DAC_CTL_DTSEL1 DAC_CTL_DTSEL1_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_CTL_DTSEL1_0 (0x1U << DAC_CTL_DTSEL1_Pos) /*!< 0x00080000 */ +#define DAC_CTL_DTSEL1_1 (0x2U << DAC_CTL_DTSEL1_Pos) /*!< 0x00100000 */ +#define DAC_CTL_DTSEL1_2 (0x4U << DAC_CTL_DTSEL1_Pos) /*!< 0x00200000 */ -#define DAC_CR_WAVE2_Pos (22U) -#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ -#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ -#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ +#define DAC_CTL_DWM1_Pos (22U) +#define DAC_CTL_DWM1_Msk (0x3U << DAC_CTL_DWM1_Pos) /*!< 0x00C00000 */ +#define DAC_CTL_DWM1 DAC_CTL_DWM1_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_CTL_DWM1_0 (0x1U << DAC_CTL_DWM1_Pos) /*!< 0x00400000 */ +#define DAC_CTL_DWM1_1 (0x2U << DAC_CTL_DWM1_Pos) /*!< 0x00800000 */ -#define DAC_CR_MAMP2_Pos (24U) -#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ -#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ -#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ -#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ -#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ -#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ +#define DAC_CTL_DWBW1_Pos (24U) +#define DAC_CTL_DWBW1_Msk (0xFU << DAC_CTL_DWBW1_Pos) /*!< 0x0F000000 */ +#define DAC_CTL_DWBW1 DAC_CTL_DWBW1_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_CTL_DWBW1_0 (0x1U << DAC_CTL_DWBW1_Pos) /*!< 0x01000000 */ +#define DAC_CTL_DWBW1_1 (0x2U << DAC_CTL_DWBW1_Pos) /*!< 0x02000000 */ +#define DAC_CTL_DWBW1_2 (0x4U << DAC_CTL_DWBW1_Pos) /*!< 0x04000000 */ +#define DAC_CTL_DWBW1_3 (0x8U << DAC_CTL_DWBW1_Pos) /*!< 0x08000000 */ -#define DAC_CR_DMAEN2_Pos (28U) -#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ -#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */ +#define DAC_CTL_DDMAEN1_Pos (28U) +#define DAC_CTL_DDMAEN1_Msk (0x1U << DAC_CTL_DDMAEN1_Pos) /*!< 0x10000000 */ +#define DAC_CTL_DDMAEN1 DAC_CTL_DDMAEN1_Msk /*!< DAC channel2 DMA enabled */ /***************** Bit definition for DAC_SWTRIGR register ******************/