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SN32 port updates 

* add preliminary support for the whole SN32F2XX series
* unify CMSIS support, no more ugly hacks
* rename the unified hal to SN32F2XX
* common header amongst the hal, points to device
* add board files for the series
* 240 gets to keep it's own hal for now
This commit is contained in:
Dimitris Mantzouranis 2022-01-10 18:14:06 +02:00
parent 42b1ebd07f
commit f4f08b1b9b
100 changed files with 20816 additions and 9292 deletions
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3002
os/common/ext/SN/SN32F24x/SN32F240.h
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64
os/common/ext/SN/SN32F24x/system_SN32F200.h
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/**************************************************************************//**
* @file system_SN32F200.h
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File
* for the SONIX SN32F200 Device
* @version V1.0
* @date January 2013
*
* @note
* Copyright (C) 2009-2013 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __SYSTEM_SN32F200_H
#define __SYSTEM_SN32F200_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_SN32F200_H */

63
os/common/ext/SN/SN32F24xB/SN32F200_Def.h
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@ -1,63 +0,0 @@
#ifndef __SN32F200_DEF_H
#define __SN32F200_DEF_H
/*_____ I N C L U D E S ____________________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
//Ture or False
// #define TRUE 0x1
// #define FALSE 0x0
//Enable or Disable
#define ENABLE 0x1
#define DISABLE 0x0
//Error Status
#define OK 0x0
#define FAIL 0x1
//Null
// #define NULL 0
//Interrupt Flag Parsing Method
#define POLLING_METHOD 0x0
#define INTERRUPT_METHOD 0x1
//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
//SN32F230_PKG
#define SN32F239 0
#define SN32F238 1
#define SN32F237 2
#define SN32F236 3
#define SN32F235 4
//SN32F240_PKG
#define SN32F249 0
#define SN32F248 1
#define SN32F247 2
#define SN32F246 3
#define SN32F245 4
//SN32F240B_PKG
#define SN32F248B 0
#define SN32F247B 1
#define SN32F246B 2
#define SN32F2451B 3
//SN32F260_PKG
#define SN32F268 0
#define SN32F267 1
#define SN32F265 2
#define SN32F2641 3
#define SN32F264 4
#define SN32F263 5
//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
/*_____ M A C R O S ________________________________________________________*/
/*_____ D E C L A R A T I O N S ____________________________________________*/
#endif /*__SN32F200_DEF_H*/

63
os/common/ext/SN/SN32F26x/SN32F200_Def.h
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@ -1,63 +0,0 @@
#ifndef __SN32F200_DEF_H
#define __SN32F200_DEF_H
/*_____ I N C L U D E S ____________________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
//Ture or False
// #define TRUE 0x1
// #define FALSE 0x0
//Enable or Disable
#define ENABLE 0x1
#define DISABLE 0x0
//Error Status
#define OK 0x0
#define FAIL 0x1
//Null
// #define NULL 0
//Interrupt Flag Parsing Method
#define POLLING_METHOD 0x0
#define INTERRUPT_METHOD 0x1
//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
//SN32F230_PKG
#define SN32F239 0
#define SN32F238 1
#define SN32F237 2
#define SN32F236 3
#define SN32F235 4
//SN32F240_PKG
#define SN32F249 0
#define SN32F248 1
#define SN32F247 2
#define SN32F246 3
#define SN32F245 4
//SN32F240B_PKG
#define SN32F248B 0
#define SN32F247B 1
#define SN32F246B 2
#define SN32F2451B 3
//SN32F260_PKG
#define SN32F268 0
#define SN32F267 1
#define SN32F265 2
#define SN32F2641 3
#define SN32F264 4
#define SN32F263 5
//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
/*_____ M A C R O S ________________________________________________________*/
/*_____ D E C L A R A T I O N S ____________________________________________*/
#endif /*__SN32F200_DEF_H*/

4
os/common/ext/SN/SN32F26x/SN32F240B.h
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// This file exists as a workaround to get the 240B USB code building on a 260.
// Previously this was done with a symlink to SN32F260.h, but that doesn't work on Windows.
// Now the #include directive is used to just include SN32F260.h
#include "SN32F260.h"

2435
os/common/ext/SN/SN32F26x/SN32F260.h
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64
os/common/ext/SN/SN32F26x/system_SN32F260.h
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/**************************************************************************//**
* @file system_SN32F200.h
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File
* for the SONIX SN32F200 Device
* @version V1.0
* @date January 2013
*
* @note
* Copyright (C) 2009-2013 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __SYSTEM_SN32F200_H
#define __SYSTEM_SN32F200_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_SN32F200_H */

0
os/common/ext/SN/SN32F24x/SN32F200_Def.h → os/common/ext/SONiX/SN32F2xx/SN32F200_Def.h
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3279
os/common/ext/SONiX/SN32F2xx/SN32F240.h Normal file
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5687
os/common/ext/SN/SN32F24xB/SN32F240B.h → os/common/ext/SONiX/SN32F2xx/SN32F240B.h
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2617
os/common/ext/SONiX/SN32F2xx/SN32F260.h Normal file
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0
os/common/ext/SN/SN32F26x/SN32F260_defines.h → os/common/ext/SONiX/SN32F2xx/SN32F260_defines.h
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4896
os/common/ext/SONiX/SN32F2xx/SN32F280.h Normal file
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4896
os/common/ext/SONiX/SN32F2xx/SN32F290.h Normal file
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57
os/common/ext/SONiX/SN32F2xx/SN32F2xx.h Normal file
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#ifndef __SN32F2xx_H
#define __SN32F2xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief SN32 Family
*/
#if !defined (SN32F2)
#define SN32F2
#endif /* SN32F2 */
/* Uncomment the line below according to the target SN32 device used in your
application
*/
#if !defined (SN32F240) && !defined (SN32F240B) && !defined (SN32F260) \
&& !defined (SN32F280) && !defined (SN32F290)
/* #define SN32F230 */ /*!< SN32F239, SN32F238, SN32F237, SN32F236,and SN32F235 Devices */
/* #define SN32F240 */ /*!< SN32F249, SN32F248, SN32F247, SN32F246 and SN32F245 Devices */
/* #define SN32F240B */ /*!< SN32F248B, SN32F247B, SN32F246B and SN32F2451B Devices */
/* #define SN32F260 */ /*!< SN32F268, SN32F267, SN32F265, SN32F2641,
SN32F264 and SN32F263 Devices */
/* #define SN32F280 */ /*!< SN32F289, SN32F288 and SN32F287 Devices */
/* #define SN32F290 */ /*!< SN32F299. SN32F298 and SN32F297 Devices */
#include "board.h"
#endif
/** @addtogroup Device_Included
* @{
*/
#if defined(SN32F240)
#include "SN32F240.h"
#elif defined(SN32F240B)
#include "SN32F240B.h"
#elif defined(SN32F260)
#include "SN32F260.h"
#elif defined(SN32F280)
#include "SN32F280.h"
#elif defined(SN32F290)
#include "SN32F290.h"
#else
#error "Please select first the target SN32F2xx device used in your application (in SN32F2xx.h file)"
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /*__SN32F2xx_H*/

4
os/common/ext/SN/SN32F24x/system_SN32F240.c → os/common/ext/SONiX/SN32F2xx/system_SN32F240.c
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@ -24,8 +24,8 @@
#include <stdint.h>
#include <SN32F240.h>
#include <system_SN32F2xx.h>
#include <mcuconf.h>
/*

2
os/common/ext/SN/SN32F24xB/system_SN32F240B.c → os/common/ext/SONiX/SN32F2xx/system_SN32F240B.c
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@ -24,7 +24,7 @@
#include <stdint.h>
#include <SN32F240B.h>
#include <system_SN32F2xx.h>
#include <mcuconf.h>

2
os/common/ext/SN/SN32F26x/system_SN32F260.c → os/common/ext/SONiX/SN32F2xx/system_SN32F260.c
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@ -24,7 +24,7 @@
#include <stdint.h>
#include <SN32F260.h>
#include <system_SN32F2xx.h>
#include <mcuconf.h>

270
os/common/ext/SONiX/SN32F2xx/system_SN32F280.c Normal file
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/******************************************************************************
* @file system_SN32F280.c
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File
* for the SONIX SN32F790 Devices
* @version V0.0.5
* @date 2018/06/14
*
* @note
* Copyright (C) 2016-2017 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include <system_SN32F2xx.h>
#include <mcuconf.h>
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Clock Configuration ----------------------------------
//
// <o0.0..2> SYSCLKSEL (SYS0_CLKCFG)
// <0=> IHRC
// <1=> ILRC
// <2=> EHS X'TAL
// <3=> ELS X'TAL
// <4=> PLL
//
// <o1> EHS Source Frequency (MHz)
// <10-25>
//
//<e2> PLL ENABLE
// <h> PLL Control Register (SYS0_PLLCTRL)
// <i> F_CLKOUT = F_VCO / P = (F_CLKIN * M) / P
// <i> 10 MHz <= F_CLKIN <= 25 MHz
// <i> 96 MHz <= (F_CLKIN * M) <= 144 MHz
// <o3> MSEL
// <0=> M = 4
// <1=> M = 6
// <2=> M = 8
// <3=> M = 10
// <4=> M = 12
// <o4> PSEL
// <0=> P = 2
// <1=> P = 4
// <o5> PLL CLKIN Source selection
// <0=> IHRC
// <1=> EHS X'TAL
// </h>
//</e>
// <o6> AHB Clock Prescaler Register (SYS0_AHBCP)
// <0=> SYSCLK/1
// <1=> SYSCLK/2
// <2=> SYSCLK/4
// <3=> SYSCLK/8
// <4=> SYSCLK/16
// <5=> SYSCLK/32
// <6=> SYSCLK/64
// <7=> SYSCLK/128
// <o7> SYSCLK prescaler Register (SYS0_AHBCP)
// <0=> SYSCLK/1
// <1=> SYSCLK/1.5
// <o8> CLKOUT selection
// <0=> Disable
// <1=> ILRC
// <2=> ELS X'TAL
// <4=> HCLK
// <5=> IHRC
// <6=> EHS X'TAL
// <7=> PLL
// <o9> CLKOUT Prescaler Register (SYS1_APBCP1)
// <0=> CLKOUT selection/1
// <1=> CLKOUT selection/2
// <2=> CLKOUT selection/4
// <3=> CLKOUT selection/8
// <4=> CLKOUT selection/16
// <5=> CLKOUT selection/32
// <6=> CLKOUT selection/64
// <7=> CLKOUT selection/128
*/
#define SYS0_CLKCFG_VAL 0
#define EHS_FREQ 16
#define PLL_ENABLE 0
#define PLL_MSEL 1
#define PLL_PSEL 0
#define PLL_CLKIN 0
#define AHB_PRESCALAR 0x0
#define AHB_1P5PRESCALAR 0x0
#define CLKOUT_SEL_VAL 0x0
#define CLKOUT_PRESCALAR 0x0
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
#define IHRC 0
#define ILRC 1
#define EHSXTAL 2
#define ELSXTAL 3
#define PLL 4
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __IHRC_FREQ (12000000UL)
#define __ILRC_FREQ (32000UL)
#define __ELS_XTAL_FREQ (32768UL)
#define SYS0_PLLCTRL_VAL (PLL_ENABLE<<15) | (PLL_CLKIN<<12) | (PLL_PSEL<<5) | PLL_MSEL
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
uint32_t AHB_prescaler;
switch (SN_SYS0->CLKCFG_b.SYSCLKST)
{
case 0: //IHRC
SystemCoreClock = __IHRC_FREQ;
break;
case 1: //ILRC
SystemCoreClock = __ILRC_FREQ;
break;
case 2: //EHS X'TAL
SystemCoreClock = EHS_FREQ * 1000000;
break;
case 3: //ELS X'TAL
SystemCoreClock = __ELS_XTAL_FREQ;
break;
case 4: //PLL
if (PLL_CLKIN == 0x0) //IHRC as F_CLKIN
SystemCoreClock = __IHRC_FREQ * (PLL_MSEL+2) / (PLL_PSEL+1);
else
SystemCoreClock = EHS_FREQ * 1000000 * (PLL_MSEL+2) / (PLL_PSEL+1);
break;
default:
break;
}
switch (SN_SYS0->AHBCP)
{
case 0: AHB_prescaler = 1; break;
case 1: AHB_prescaler = 2; break;
case 2: AHB_prescaler = 4; break;
case 3: AHB_prescaler = 8; break;
case 4: AHB_prescaler = 16; break;
case 5: AHB_prescaler = 32; break;
case 6: AHB_prescaler = 64; break;
case 7: AHB_prescaler = 128;break;
default: break;
}
SystemCoreClock /= AHB_prescaler;
if (SN_SYS0->AHBCP_b.DIV1P5 == 1)
SystemCoreClock = SystemCoreClock*2/3;
//;;;;;;;;; Need for SN32F780 Begin ;;;;;;;;;
if (SystemCoreClock > 48000000)
SN_FLASH->LPCTRL = 0x5AFA0031;
else if (SystemCoreClock > 24000000)
SN_FLASH->LPCTRL = 0x5AFA0011;
else
SN_FLASH->LPCTRL = 0x5AFA0000;
//;;;;;;;;; Need for SN32F780 End ;;;;;;;;;
return;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#if SYS0_CLKCFG_VAL == IHRC //IHRC
SN_SYS0->CLKCFG = 0x0;
while ((SN_SYS0->CLKCFG & 0x70) != 0x0);
#endif
#if SYS0_CLKCFG_VAL == ILRC //ILRC
SN_SYS0->CLKCFG = 0x1;
while ((SN_SYS0->CLKCFG & 0x70) != 0x10);
#endif
#if (SYS0_CLKCFG_VAL == EHSXTAL) //EHS XTAL
#if (EHS_FREQ > 12)
SN_SYS0->ANBCTRL_b.EHSFREQ = 1;
SN_FLASH->LPCTRL = 0x5AFA0011;
#else
SN_SYS0->ANBCTRL_b.EHSFREQ = 0;
#endif
SN_SYS0->ANBCTRL_b.EHSEN = 1;
while ((SN_SYS0->CSST & 0x10) != 0x10);
SN_SYS0->CLKCFG = 0x2;
while ((SN_SYS0->CLKCFG & 0x70) != 0x20);
#endif
#if (SYS0_CLKCFG_VAL == ELSXTAL) //ELS XTAL
SN_SYS0->ANBCTRL_b.ELSEN = 1;
while((SN_SYS0->CSST & 0x4) != 0x4);
SN_SYS0->CLKCFG = 0x3;
while ((SN_SYS0->CLKCFG & 0x70) != 0x30);
#endif
#if (PLL_ENABLE == 1)
SN_SYS0->PLLCTRL = SYS0_PLLCTRL_VAL;
if (PLL_CLKIN == 0x1) //EHS XTAL as F_CLKIN
{
//Enable EHS
#if (EHS_FREQ > 12)
SN_SYS0->ANBCTRL_b.EHSFREQ = 1;
#else
SN_SYS0->ANBCTRL_b.EHSFREQ = 0;
#endif
SN_SYS0->ANBCTRL_b.EHSEN = 1;
while ((SN_SYS0->CSST & 0x10) != 0x10);
}
while ((SN_SYS0->CSST & 0x40) != 0x40);
#if (SYS0_CLKCFG_VAL == PLL) //PLL
SN_FLASH->LPCTRL = 0x5AFA0031;
SN_SYS0->CLKCFG = 0x4;
while ((SN_SYS0->CLKCFG & 0x70) != 0x40);
#endif
#endif
SN_SYS0->AHBCP = AHB_PRESCALAR;
SN_SYS0->AHBCP_b.DIV1P5 = AHB_1P5PRESCALAR;
#if (CLKOUT_SEL_VAL > 0) //CLKOUT
SN_SYS1->AHBCLKEN_b.CLKOUTSEL = CLKOUT_SEL_VAL;
SN_SYS1->APBCP1_b.CLKOUTPRE = CLKOUT_PRESCALAR;
#endif
}

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os/common/ext/SONiX/SN32F2xx/system_SN32F290.c Normal file
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/******************************************************************************
* @file system_SN32F290.c
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File
* for the SONIX SN32F790 Devices
* @version V0.0.5
* @date 2018/06/14
*
* @note
* Copyright (C) 2016-2017 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include <system_SN32F2xx.h>
#include <mcuconf.h>
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Clock Configuration ----------------------------------
//
// <o0.0..2> SYSCLKSEL (SYS0_CLKCFG)
// <0=> IHRC
// <1=> ILRC
// <2=> EHS X'TAL
// <3=> ELS X'TAL
// <4=> PLL
//
// <o1> EHS Source Frequency (MHz)
// <10-25>
//
//<e2> PLL ENABLE
// <h> PLL Control Register (SYS0_PLLCTRL)
// <i> F_CLKOUT = F_VCO / P = (F_CLKIN * M) / P
// <i> 10 MHz <= F_CLKIN <= 25 MHz
// <i> 96 MHz <= (F_CLKIN * M) <= 144 MHz
// <o3> MSEL
// <0=> M = 4
// <1=> M = 6
// <2=> M = 8
// <3=> M = 10
// <4=> M = 12
// <o4> PSEL
// <0=> P = 2
// <1=> P = 4
// <o5> PLL CLKIN Source selection
// <0=> IHRC
// <1=> EHS X'TAL
// </h>
//</e>
// <o6> AHB Clock Prescaler Register (SYS0_AHBCP)
// <0=> SYSCLK/1
// <1=> SYSCLK/2
// <2=> SYSCLK/4
// <3=> SYSCLK/8
// <4=> SYSCLK/16
// <5=> SYSCLK/32
// <6=> SYSCLK/64
// <7=> SYSCLK/128
// <o7> SYSCLK prescaler Register (SYS0_AHBCP)
// <0=> SYSCLK/1
// <1=> SYSCLK/1.5
// <o8> CLKOUT selection
// <0=> Disable
// <1=> ILRC
// <2=> ELS X'TAL
// <4=> HCLK
// <5=> IHRC
// <6=> EHS X'TAL
// <7=> PLL
// <o9> CLKOUT Prescaler Register (SYS1_APBCP1)
// <0=> CLKOUT selection/1
// <1=> CLKOUT selection/2
// <2=> CLKOUT selection/4
// <3=> CLKOUT selection/8
// <4=> CLKOUT selection/16
// <5=> CLKOUT selection/32
// <6=> CLKOUT selection/64
// <7=> CLKOUT selection/128
*/
#define SYS0_CLKCFG_VAL 0
#define EHS_FREQ 16
#define PLL_ENABLE 0
#define PLL_MSEL 1
#define PLL_PSEL 0
#define PLL_CLKIN 0
#define AHB_PRESCALAR 0x0
#define AHB_1P5PRESCALAR 0x0
#define CLKOUT_SEL_VAL 0x0
#define CLKOUT_PRESCALAR 0x0
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
#define IHRC 0
#define ILRC 1
#define EHSXTAL 2
#define ELSXTAL 3
#define PLL 4
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __IHRC_FREQ (12000000UL)
#define __ILRC_FREQ (32000UL)
#define __ELS_XTAL_FREQ (32768UL)
#define SYS0_PLLCTRL_VAL (PLL_ENABLE<<15) | (PLL_CLKIN<<12) | (PLL_PSEL<<5) | PLL_MSEL
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
uint32_t AHB_prescaler;
switch (SN_SYS0->CLKCFG_b.SYSCLKST)
{
case 0: //IHRC
SystemCoreClock = __IHRC_FREQ;
break;
case 1: //ILRC
SystemCoreClock = __ILRC_FREQ;
break;
case 2: //EHS X'TAL
SystemCoreClock = EHS_FREQ * 1000000;
break;
case 3: //ELS X'TAL
SystemCoreClock = __ELS_XTAL_FREQ;
break;
case 4: //PLL
if (PLL_CLKIN == 0x0) //IHRC as F_CLKIN
SystemCoreClock = __IHRC_FREQ * (PLL_MSEL+2) / (PLL_PSEL+1);
else
SystemCoreClock = EHS_FREQ * 1000000 * (PLL_MSEL+2) / (PLL_PSEL+1);
break;
default:
break;
}
switch (SN_SYS0->AHBCP)
{
case 0: AHB_prescaler = 1; break;
case 1: AHB_prescaler = 2; break;
case 2: AHB_prescaler = 4; break;
case 3: AHB_prescaler = 8; break;
case 4: AHB_prescaler = 16; break;
case 5: AHB_prescaler = 32; break;
case 6: AHB_prescaler = 64; break;
case 7: AHB_prescaler = 128;break;
default: break;
}
SystemCoreClock /= AHB_prescaler;
if (SN_SYS0->AHBCP_b.DIV1P5 == 1)
SystemCoreClock = SystemCoreClock*2/3;
//;;;;;;;;; Need for SN32F780 Begin ;;;;;;;;;
if (SystemCoreClock > 48000000)
SN_FLASH->LPCTRL = 0x5AFA0031;
else if (SystemCoreClock > 24000000)
SN_FLASH->LPCTRL = 0x5AFA0011;
else
SN_FLASH->LPCTRL = 0x5AFA0000;
//;;;;;;;;; Need for SN32F780 End ;;;;;;;;;
return;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#if SYS0_CLKCFG_VAL == IHRC //IHRC
SN_SYS0->CLKCFG = 0x0;
while ((SN_SYS0->CLKCFG & 0x70) != 0x0);
#endif
#if SYS0_CLKCFG_VAL == ILRC //ILRC
SN_SYS0->CLKCFG = 0x1;
while ((SN_SYS0->CLKCFG & 0x70) != 0x10);
#endif
#if (SYS0_CLKCFG_VAL == EHSXTAL) //EHS XTAL
#if (EHS_FREQ > 12)
SN_SYS0->ANBCTRL_b.EHSFREQ = 1;
SN_FLASH->LPCTRL = 0x5AFA0011;
#else
SN_SYS0->ANBCTRL_b.EHSFREQ = 0;
#endif
SN_SYS0->ANBCTRL_b.EHSEN = 1;
while ((SN_SYS0->CSST & 0x10) != 0x10);
SN_SYS0->CLKCFG = 0x2;
while ((SN_SYS0->CLKCFG & 0x70) != 0x20);
#endif
#if (SYS0_CLKCFG_VAL == ELSXTAL) //ELS XTAL
SN_SYS0->ANBCTRL_b.ELSEN = 1;
while((SN_SYS0->CSST & 0x4) != 0x4);
SN_SYS0->CLKCFG = 0x3;
while ((SN_SYS0->CLKCFG & 0x70) != 0x30);
#endif
#if (PLL_ENABLE == 1)
SN_SYS0->PLLCTRL = SYS0_PLLCTRL_VAL;
if (PLL_CLKIN == 0x1) //EHS XTAL as F_CLKIN
{
//Enable EHS
#if (EHS_FREQ > 12)
SN_SYS0->ANBCTRL_b.EHSFREQ = 1;
#else
SN_SYS0->ANBCTRL_b.EHSFREQ = 0;
#endif
SN_SYS0->ANBCTRL_b.EHSEN = 1;
while ((SN_SYS0->CSST & 0x10) != 0x10);
}
while ((SN_SYS0->CSST & 0x40) != 0x40);
#if (SYS0_CLKCFG_VAL == PLL) //PLL
SN_FLASH->LPCTRL = 0x5AFA0031;
SN_SYS0->CLKCFG = 0x4;
while ((SN_SYS0->CLKCFG & 0x70) != 0x40);
#endif
#endif
SN_SYS0->AHBCP = AHB_PRESCALAR;
SN_SYS0->AHBCP_b.DIV1P5 = AHB_1P5PRESCALAR;
#if (CLKOUT_SEL_VAL > 0) //CLKOUT
SN_SYS1->AHBCLKEN_b.CLKOUTSEL = CLKOUT_SEL_VAL;
SN_SYS1->APBCP1_b.CLKOUTPRE = CLKOUT_PRESCALAR;
#endif
}

11
os/common/ext/SN/SN32F24xB/system_SN32F240B.h → os/common/ext/SONiX/SN32F2xx/system_SN32F2xx.h
View File

@ -23,15 +23,15 @@
******************************************************************************/
#ifndef __SYSTEM_SN32F240B_H
#define __SYSTEM_SN32F240B_H
#ifndef __SYSTEM_SN32F2xx_H
#define __SYSTEM_SN32F2xx_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "SN32F2xx.h"
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
@ -56,7 +56,7 @@ extern void SystemInit (void);
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#if defined(SN32F240B)
/**
* Initialize the Flash controller
*
@ -75,9 +75,10 @@ extern void FlashClockUpdate (void);
* @brief Special init required for SystemCoreClock <= 8000
*/
extern void SlowModeSwitch (void);
#endif /* defined(SN32F240B) */
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_SN32F240B_H */
#endif /* __SYSTEM_SN32F2xx_H */

96
os/common/startup/ARMCMx/compilers/GCC/ld/SN32F280.ld Normal file
View File

@ -0,0 +1,96 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* SN32F280 memory setup.
*/
MEMORY
{
flash0 (rx) : org = 0x00000000, len = 128k
flash1 (rx) : org = 0x00000000, len = 0
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 32k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld
_flag_start = 0xFFFC;
SECTIONS
{
.flag _flag_start :
{
KEEP(*(.flag)) ;
} > flash0
}

96
os/common/startup/ARMCMx/compilers/GCC/ld/SN32F290.ld Normal file
View File

@ -0,0 +1,96 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* SN32F290 memory setup.
*/
MEMORY
{
flash0 (rx) : org = 0x00000000, len = 256k
flash1 (rx) : org = 0x00000000, len = 0
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 32k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld
_flag_start = 0xFFFC;
SECTIONS
{
.flag _flag_start :
{
KEEP(*(.flag)) ;
} > flash0
}

5
os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f24x.mk
View File

@ -1,6 +1,6 @@
# List of the ChibiOS generic SN32F24x startup and CMSIS files.
STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
$(CHIBIOS_CONTRIB)/os/common/ext/SN/SN32F24x/system_SN32F240.c
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx/system_SN32F240.c
STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
@ -9,9 +9,10 @@ STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/SN32F24x \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
$(CHIBIOS_CONTRIB)/os/common/ext/SN/SN32F24x
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx
STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLXASMSRC += $(STARTUPASM)

5
os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f24xb.mk
View File

@ -1,6 +1,6 @@
# List of the ChibiOS generic SN32F24x startup and CMSIS files.
STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
$(CHIBIOS_CONTRIB)/os/common/ext/SN/SN32F24xB/system_SN32F240B.c
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx/system_SN32F240B.c
STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
@ -9,9 +9,10 @@ STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/SN32F24xB \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
$(CHIBIOS_CONTRIB)/os/common/ext/SN/SN32F24xB
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx
STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLXASMSRC += $(STARTUPASM)

5
os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f26x.mk
View File

@ -1,6 +1,6 @@
# List of the ChibiOS generic SN32F26x startup and CMSIS files.
STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
$(CHIBIOS_CONTRIB)/os/common/ext/SN/SN32F26x/system_SN32F260.c
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx/system_SN32F260.c
STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
@ -9,9 +9,10 @@ STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/SN32F26x \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
$(CHIBIOS_CONTRIB)/os/common/ext/SN/SN32F26x
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx
STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLXASMSRC += $(STARTUPASM)

20
os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f28x.mk Normal file
View File

@ -0,0 +1,20 @@
# List of the ChibiOS generic SN32F28x startup and CMSIS files.
STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx/system_SN32F280.c
STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/SN32F28x \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx
STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLXASMSRC += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

20
os/common/startup/ARMCMx/compilers/GCC/mk/startup_sn32f29x.mk Normal file
View File

@ -0,0 +1,20 @@
# List of the ChibiOS generic SN32F29x startup and CMSIS files.
STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx/system_SN32F290.c
STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/SN32F29x \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx
STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLXASMSRC += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

8
os/common/startup/ARMCMx/devices/SN32F26x/cmparams.h
View File

@ -15,13 +15,13 @@
*/
/**
* @file SN32F24x/cmparams.h
* @brief ARM Cortex-M0 parameters for the SN32F24x.
* @file SN32F26x/cmparams.h
* @brief ARM Cortex-M0 parameters for the SN32F26x.
*
* @defgroup ARMCMx_SN32F24x SN32F24x Specific Parameters
* @defgroup ARMCMx_SN32F26x SN32F26x Specific Parameters
* @ingroup ARMCMx_SPECIFIC
* @details This file contains the Cortex-M0 specific parameters for the
* SN32F24x platform.
* SN32F26x platform.
* @{
*/

79
os/common/startup/ARMCMx/devices/SN32F28x/cmparams.h Normal file
View File

@ -0,0 +1,79 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SN32F28x/cmparams.h
* @brief ARM Cortex-M0 parameters for the SN32F28x.
*
* @defgroup ARMCMx_SN32F28x SN32F28x Specific Parameters
* @ingroup ARMCMx_SPECIFIC
* @details This file contains the Cortex-M0 specific parameters for the
* SN32F28x platform.
* @{
*/
#ifndef CMPARAMS_H
#define CMPARAMS_H
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL 0
/**
* @brief Floating Point unit presence.
*/
#define CORTEX_HAS_FPU 0
/**
* @brief Number of bits in priority masks.
*/
#define CORTEX_PRIORITY_BITS 2
/**
* @brief Number of interrupt vectors.
* @note This number does not include the 16 system vectors and must be
* rounded to a multiple of 8.
*/
#define CORTEX_NUM_VECTORS 32
/* The following code is not processed when the file is included from an
asm module.*/
#if !defined(_FROM_ASM_)
#include "board.h"
/* Including the device CMSIS header. Note, we are not using the definitions
from this header because we need this file to be usable also from
assembler source files. We verify that the info matches instead.*/
#include "SN32F280.h"
/*lint -save -e9029 [10.4] Signedness comes from external files, it is
unpredictable but gives no problems.*/
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
#endif
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
#error "CMSIS __NVIC_PRIO_BITS mismatch"
#endif
/*lint -restore*/
#endif /* !defined(_FROM_ASM_) */
#endif /* CMPARAMS_H */
/** @} */

79
os/common/startup/ARMCMx/devices/SN32F29x/cmparams.h Normal file
View File

@ -0,0 +1,79 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SN32F29x/cmparams.h
* @brief ARM Cortex-M0 parameters for the SN32F29x.
*
* @defgroup ARMCMx_SN32F29x SN32F29x Specific Parameters
* @ingroup ARMCMx_SPECIFIC
* @details This file contains the Cortex-M0 specific parameters for the
* SN32F29x platform.
* @{
*/
#ifndef CMPARAMS_H
#define CMPARAMS_H
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL 0
/**
* @brief Floating Point unit presence.
*/
#define CORTEX_HAS_FPU 0
/**
* @brief Number of bits in priority masks.
*/
#define CORTEX_PRIORITY_BITS 2
/**
* @brief Number of interrupt vectors.
* @note This number does not include the 16 system vectors and must be
* rounded to a multiple of 8.
*/
#define CORTEX_NUM_VECTORS 32
/* The following code is not processed when the file is included from an
asm module.*/
#if !defined(_FROM_ASM_)
#include "board.h"
/* Including the device CMSIS header. Note, we are not using the definitions
from this header because we need this file to be usable also from
assembler source files. We verify that the info matches instead.*/
#include "SN32F290.h"
/*lint -save -e9029 [10.4] Signedness comes from external files, it is
unpredictable but gives no problems.*/
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
#endif
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
#error "CMSIS __NVIC_PRIO_BITS mismatch"
#endif
/*lint -restore*/
#endif /* !defined(_FROM_ASM_) */
#endif /* CMPARAMS_H */
/** @} */

67
os/hal/boards/SN_SN32F240/board.c Normal file
View File

@ -0,0 +1,67 @@
/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
const PALConfig pal_default_config = {
#if SN32_HAS_GPIOA
{.mode = VAL_GPIOA_MODE, .cfg = VAL_GPIOA_CFG},
#endif
#if SN32_HAS_GPIOB
{.mode = VAL_GPIOB_MODE, .cfg = VAL_GPIOB_CFG},
#endif
#if SN32_HAS_GPIOC
{.mode = VAL_GPIOC_MODE, .cfg = VAL_GPIOC_CFG},
#endif
#if SN32_HAS_GPIOD
{.mode = VAL_GPIOD_MODE, .cfg = VAL_GPIOD_CFG},
#endif
};
#endif
/**
* @brief Early initialization code.
* @details This initialization must be performed just after stack setup
* and before any other initialization.
*/
void __early_init(void) {
sn32_clock_init();
}
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {
SN_SYS0->EXRSTCTRL_b.RESETDIS = 1; // Disable RESET
SN_SYS0->SWDCTRL_b.SWDDIS = 1; // Disable SWD
}
void restart_usb_driver(USBDriver *usbp) {
// Do nothing. Restarting the USB driver on these boards breaks it.
}

262
os/hal/boards/SN_SN32F240/board.h Normal file
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@ -0,0 +1,262 @@
/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* Setup for Generic SN32F240 Board
*/
/*
* Board identifier.
*/
#define BOARD_GENERIC_SN32_F240
#define BOARD_NAME "SN32F240"
/*
* MCU type as defined in the SN32 header.
*/
#define SN32F240
/*
* IO pins assignments.
*/
#define GPIOA_PIN0 0U
#define GPIOA_PIN1 1U
#define GPIOA_PIN2 2U
#define GPIOA_PIN3 3U
#define GPIOA_PIN4 4U
#define GPIOA_PIN5 5U
#define GPIOA_PIN6 6U
#define GPIOA_PIN7 7U
#define GPIOA_PIN8 8U
#define GPIOA_PIN9 9U
#define GPIOA_PIN10 10U
#define GPIOA_PIN11 11U
#define GPIOA_PIN12 12U
#define GPIOA_PIN13 13U
#define GPIOA_PIN14 14U
#define GPIOA_PIN15 15U
#define GPIOB_PIN0 0U
#define GPIOB_PIN1 1U
#define GPIOB_PIN2 2U
#define GPIOB_PIN3 3U
#define GPIOB_PIN4 4U
#define GPIOB_PIN5 5U
#define GPIOB_PIN6 6U
#define GPIOB_PIN7 7U
#define GPIOB_PIN8 8U
#define GPIOB_PIN9 9U
#define GPIOB_PIN10 10U
#define GPIOB_PIN11 11U
#define GPIOB_PIN12 12U
#define GPIOB_PIN13 13U
#define GPIOB_PIN14 14U
#define GPIOB_PIN15 15U
#define GPIOC_PIN0 0U
#define GPIOC_PIN1 1U
#define GPIOC_PIN2 2U
#define GPIOC_PIN3 3U
#define GPIOC_PIN4 4U
#define GPIOC_PIN5 5U
#define GPIOC_PIN6 6U
#define GPIOC_PIN7 7U
#define GPIOC_PIN8 8U
#define GPIOC_PIN9 9U
#define GPIOC_PIN10 10U
#define GPIOC_PIN11 11U
#define GPIOC_PIN12 12U
#define GPIOC_PIN13 13U
#define GPIOC_PIN14 14U
#define GPIOC_PIN15 15U
#define GPIOD_PIN3 3U
#define GPIOD_PIN4 4U
#define GPIOD_PIN5 5U
#define GPIOD_PIN6 6U
#define GPIOD_PIN7 7U
#define GPIOD_PIN8 8U
#define GPIOD_PIN9 9U
#define GPIOD_PIN10 10U
#define GPIOD_PIN11 11U
#define GPIOD_PIN12 12U
#define GPIOD_PIN13 13U
#define GPIOD_PIN14 14U
#define GPIOD_PIN15 15U
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
* Please refer to the SN32 Reference Manual for details.
*/
#define PIN_MODE_INPUT(n) (0U << ((n)))
#define PIN_MODE_OUTPUT(n) (1U << ((n)))
#define PIN_CFG_PULLUP(n) (0U << ((n*2))) // Pull-up
#define PIN_CFG_SCHMITT_EN(n) (2U << ((n*2))) // Floating
#define PIN_CFG_SCHMITT_DIS(n) (3U << ((n*2))) // Input buffer disconnected, alway read as zero.
// Define GPIO register values used by pal_default_config.
// The following values match the chip reset values, all GPIO pins as floating inputs.
#define VAL_GPIOA_MODE \
( PIN_MODE_INPUT(GPIOA_PIN0) \
| PIN_MODE_INPUT(GPIOA_PIN1) \
| PIN_MODE_INPUT(GPIOA_PIN2) \
| PIN_MODE_INPUT(GPIOA_PIN3) \
| PIN_MODE_INPUT(GPIOA_PIN4) \
| PIN_MODE_INPUT(GPIOA_PIN5) \
| PIN_MODE_INPUT(GPIOA_PIN6) \
| PIN_MODE_INPUT(GPIOA_PIN7) \
| PIN_MODE_INPUT(GPIOA_PIN8) \
| PIN_MODE_INPUT(GPIOA_PIN9) \
| PIN_MODE_INPUT(GPIOA_PIN10) \
| PIN_MODE_INPUT(GPIOA_PIN11) \
| PIN_MODE_INPUT(GPIOA_PIN12) \
| PIN_MODE_INPUT(GPIOA_PIN13) \
| PIN_MODE_INPUT(GPIOA_PIN14) \
| PIN_MODE_INPUT(GPIOA_PIN15) )
#define VAL_GPIOA_CFG \
( PIN_CFG_SCHMITT_EN(GPIOA_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN15) )
#define VAL_GPIOB_MODE \
( PIN_MODE_INPUT(GPIOB_PIN0) \
| PIN_MODE_INPUT(GPIOB_PIN1) \
| PIN_MODE_INPUT(GPIOB_PIN2) \
| PIN_MODE_INPUT(GPIOB_PIN3) \
| PIN_MODE_INPUT(GPIOB_PIN4) \
| PIN_MODE_INPUT(GPIOB_PIN5) \
| PIN_MODE_INPUT(GPIOB_PIN6) \
| PIN_MODE_INPUT(GPIOB_PIN7) \
| PIN_MODE_INPUT(GPIOB_PIN8) \
| PIN_MODE_INPUT(GPIOB_PIN9) \
| PIN_MODE_INPUT(GPIOB_PIN10) \
| PIN_MODE_INPUT(GPIOB_PIN11) \
| PIN_MODE_INPUT(GPIOB_PIN12) \
| PIN_MODE_INPUT(GPIOB_PIN13) \
| PIN_MODE_INPUT(GPIOB_PIN14) \
| PIN_MODE_INPUT(GPIOB_PIN15) )
#define VAL_GPIOB_CFG \
( PIN_CFG_SCHMITT_EN(GPIOB_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN15) )
#define VAL_GPIOC_MODE \
( PIN_MODE_INPUT(GPIOC_PIN0) \
| PIN_MODE_INPUT(GPIOC_PIN1) \
| PIN_MODE_INPUT(GPIOC_PIN2) \
| PIN_MODE_INPUT(GPIOC_PIN3) \
| PIN_MODE_INPUT(GPIOC_PIN4) \
| PIN_MODE_INPUT(GPIOC_PIN5) \
| PIN_MODE_INPUT(GPIOC_PIN6) \
| PIN_MODE_INPUT(GPIOC_PIN7) \
| PIN_MODE_INPUT(GPIOC_PIN8) \
| PIN_MODE_INPUT(GPIOC_PIN9) \
| PIN_MODE_INPUT(GPIOC_PIN10) \
| PIN_MODE_INPUT(GPIOC_PIN11) \
| PIN_MODE_INPUT(GPIOC_PIN12) \
| PIN_MODE_INPUT(GPIOC_PIN13) \
| PIN_MODE_INPUT(GPIOC_PIN14) \
| PIN_MODE_INPUT(GPIOC_PIN15) )
#define VAL_GPIOC_CFG \
( PIN_CFG_SCHMITT_EN(GPIOC_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN15) )
#define VAL_GPIOD_MODE \
( PIN_MODE_INPUT(GPIOD_PIN3) \
| PIN_MODE_INPUT(GPIOD_PIN4) \
| PIN_MODE_INPUT(GPIOD_PIN5) \
| PIN_MODE_INPUT(GPIOD_PIN6) \
| PIN_MODE_INPUT(GPIOD_PIN7) \
| PIN_MODE_INPUT(GPIOD_PIN8) \
| PIN_MODE_INPUT(GPIOD_PIN9) \
| PIN_MODE_INPUT(GPIOD_PIN10) \
| PIN_MODE_INPUT(GPIOD_PIN11) \
| PIN_MODE_INPUT(GPIOD_PIN12) \
| PIN_MODE_INPUT(GPIOD_PIN13) \
| PIN_MODE_INPUT(GPIOD_PIN14) \
| PIN_MODE_INPUT(GPIOD_PIN15) )
#define VAL_GPIOD_CFG \
( PIN_CFG_SCHMITT_EN(GPIOD_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN15) )
#if !defined(_FROM_ASM_)
# ifdef __cplusplus
extern "C" {
# endif
void boardInit(void);
# ifdef __cplusplus
}
# endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */

9
os/hal/boards/SN_SN32F240/board.mk Normal file
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@ -0,0 +1,9 @@
# List of all the board related files.
BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F240B/board.c
# Required include directories
BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F240B
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

5
os/hal/boards/SN_SN32F240B/board.c
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@ -43,17 +43,12 @@ const PALConfig pal_default_config = {
};
#endif
static int flag __attribute__((section(".flag"))) __attribute__((__used__)) = 0xAAAA5555;
extern void enter_bootloader_mode_if_requested(void);
/**
* @brief Early initialization code.
* @details This initialization must be performed just after stack setup
* and before any other initialization.
*/
void __early_init(void) {
enter_bootloader_mode_if_requested();
sn32_clock_init();
}

4
os/hal/boards/SN_SN32F240B/board.h
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@ -28,9 +28,9 @@
#define BOARD_NAME "SN32F240B"
/*
* MCU type as defined in the ST header.
* MCU type as defined in the SN32 header.
*/
#define system_SN32F240B
#define SN32F240B
/*
* IO pins assignments.

6
os/hal/boards/SN_SN32F260/board.h
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@ -18,7 +18,7 @@
#define _BOARD_H_
/*
* Setup for Generic STM32_F303 Board
* Setup for Generic SN32F260 Board
*/
/*
@ -28,9 +28,9 @@
#define BOARD_NAME "SN32F260"
/*
* MCU type as defined in the ST header.
* MCU type as defined in the SN32 header.
*/
#define system_SN32F260
#define SN32F260
/*
* IO pins assignments.

67
os/hal/boards/SN_SN32F280/board.c Normal file
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@ -0,0 +1,67 @@
/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
const PALConfig pal_default_config = {
#if SN32_HAS_GPIOA
{.mode = VAL_GPIOA_MODE, .cfg = VAL_GPIOA_CFG},
#endif
#if SN32_HAS_GPIOB
{.mode = VAL_GPIOB_MODE, .cfg = VAL_GPIOB_CFG},
#endif
#if SN32_HAS_GPIOC
{.mode = VAL_GPIOC_MODE, .cfg = VAL_GPIOC_CFG},
#endif
#if SN32_HAS_GPIOD
{.mode = VAL_GPIOD_MODE, .cfg = VAL_GPIOD_CFG},
#endif
};
#endif
/**
* @brief Early initialization code.
* @details This initialization must be performed just after stack setup
* and before any other initialization.
*/
void __early_init(void) {
sn32_clock_init();
}
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {
SN_SYS0->EXRSTCTRL_b.RESETDIS = 1; // Disable RESET
SN_SYS0->SWDCTRL_b.SWDDIS = 1; // Disable SWD
}
void restart_usb_driver(USBDriver *usbp) {
// Do nothing. Restarting the USB driver on these boards breaks it.
}

296
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@ -0,0 +1,296 @@
/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* Setup for Generic SN32F280 Board
*/
/*
* Board identifier.
*/
#define BOARD_GENERIC_SN32_F240
#define BOARD_NAME "SN32F280"
/*
* MCU type as defined in the SN32 header.
*/
#define SN32F280
/*
* IO pins assignments.
*/
#define GPIOA_PIN0 0U
#define GPIOA_PIN1 1U
#define GPIOA_PIN2 2U
#define GPIOA_PIN3 3U
#define GPIOA_PIN4 4U
#define GPIOA_PIN5 5U
#define GPIOA_PIN6 6U
#define GPIOA_PIN7 7U
#define GPIOA_PIN8 8U
#define GPIOA_PIN9 9U
#define GPIOA_PIN10 10U
#define GPIOA_PIN11 11U
#define GPIOA_PIN12 12U
#define GPIOA_PIN13 13U
#define GPIOA_PIN14 14U
#define GPIOA_PIN15 15U
#define GPIOA_PIN16 16U
#define GPIOA_PIN17 17U
#define GPIOA_PIN18 18U
#define GPIOA_PIN19 19U
#define GPIOB_PIN0 0U
#define GPIOB_PIN1 1U
#define GPIOB_PIN2 2U
#define GPIOB_PIN3 3U
#define GPIOB_PIN4 4U
#define GPIOB_PIN5 5U
#define GPIOB_PIN6 6U
#define GPIOB_PIN7 7U
#define GPIOB_PIN8 8U
#define GPIOB_PIN9 9U
#define GPIOB_PIN10 10U
#define GPIOB_PIN11 11U
#define GPIOB_PIN12 12U
#define GPIOB_PIN13 13U
#define GPIOB_PIN14 14U
#define GPIOB_PIN15 15U
#define GPIOB_PIN16 16U
#define GPIOB_PIN17 17U
#define GPIOB_PIN18 18U
#define GPIOB_PIN19 19U
#define GPIOC_PIN0 0U
#define GPIOC_PIN1 1U
#define GPIOC_PIN2 2U
#define GPIOC_PIN5 5U
#define GPIOC_PIN6 6U
#define GPIOC_PIN7 7U
#define GPIOC_PIN8 8U
#define GPIOC_PIN9 9U
#define GPIOC_PIN10 10U
#define GPIOC_PIN11 11U
#define GPIOC_PIN12 12U
#define GPIOC_PIN13 13U
#define GPIOC_PIN14 14U
#define GPIOC_PIN15 15U
#define GPIOD_PIN3 3U
#define GPIOD_PIN4 4U
#define GPIOD_PIN5 5U
#define GPIOD_PIN6 6U
#define GPIOD_PIN7 7U
#define GPIOD_PIN8 8U
#define GPIOD_PIN9 9U
#define GPIOD_PIN10 10U
#define GPIOD_PIN11 11U
#define GPIOD_PIN12 12U
#define GPIOD_PIN13 13U
#define GPIOD_PIN14 14U
#define GPIOD_PIN15 15U
#define GPIOD_PIN16 16U
#define GPIOD_PIN17 17U
#define GPIOD_PIN18 18U
#define GPIOD_PIN19 19U
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
* Please refer to the SN32 Reference Manual for details.
*/
#define PIN_MODE_INPUT(n) (0U << ((n)))
#define PIN_MODE_OUTPUT(n) (1U << ((n)))
#define PIN_CFG_PULLUP(n) (0U << ((n*2))) // Pull-up
#define PIN_CFG_SCHMITT_EN(n) (2U << ((n*2))) // Floating
#define PIN_CFG_SCHMITT_DIS(n) (3U << ((n*2))) // Input buffer disconnected, alway read as zero.
// Define GPIO register values used by pal_default_config.
// The following values match the chip reset values, all GPIO pins as floating inputs.
#define VAL_GPIOA_MODE \
( PIN_MODE_INPUT(GPIOA_PIN0) \
| PIN_MODE_INPUT(GPIOA_PIN1) \
| PIN_MODE_INPUT(GPIOA_PIN2) \
| PIN_MODE_INPUT(GPIOA_PIN3) \
| PIN_MODE_INPUT(GPIOA_PIN4) \
| PIN_MODE_INPUT(GPIOA_PIN5) \
| PIN_MODE_INPUT(GPIOA_PIN6) \
| PIN_MODE_INPUT(GPIOA_PIN7) \
| PIN_MODE_INPUT(GPIOA_PIN8) \
| PIN_MODE_INPUT(GPIOA_PIN9) \
| PIN_MODE_INPUT(GPIOA_PIN10) \
| PIN_MODE_INPUT(GPIOA_PIN11) \
| PIN_MODE_INPUT(GPIOA_PIN12) \
| PIN_MODE_INPUT(GPIOA_PIN13) \
| PIN_MODE_INPUT(GPIOA_PIN14) \
| PIN_MODE_INPUT(GPIOA_PIN15) \
| PIN_MODE_INPUT(GPIOA_PIN16) \
| PIN_MODE_INPUT(GPIOA_PIN17) \
| PIN_MODE_INPUT(GPIOA_PIN18) \
| PIN_MODE_INPUT(GPIOA_PIN19) )
#define VAL_GPIOA_CFG \
( PIN_CFG_SCHMITT_EN(GPIOA_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN15) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN16) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN17) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN18) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN19) )
#define VAL_GPIOB_MODE \
( PIN_MODE_INPUT(GPIOB_PIN0) \
| PIN_MODE_INPUT(GPIOB_PIN1) \
| PIN_MODE_INPUT(GPIOB_PIN2) \
| PIN_MODE_INPUT(GPIOB_PIN3) \
| PIN_MODE_INPUT(GPIOB_PIN4) \
| PIN_MODE_INPUT(GPIOB_PIN5) \
| PIN_MODE_INPUT(GPIOB_PIN6) \
| PIN_MODE_INPUT(GPIOB_PIN7) \
| PIN_MODE_INPUT(GPIOB_PIN8) \
| PIN_MODE_INPUT(GPIOB_PIN9) \
| PIN_MODE_INPUT(GPIOB_PIN10) \
| PIN_MODE_INPUT(GPIOB_PIN11) \
| PIN_MODE_INPUT(GPIOB_PIN12) \
| PIN_MODE_INPUT(GPIOB_PIN13) \
| PIN_MODE_INPUT(GPIOB_PIN14) \
| PIN_MODE_INPUT(GPIOB_PIN15) \
| PIN_MODE_INPUT(GPIOB_PIN16) \
| PIN_MODE_INPUT(GPIOB_PIN17) \
| PIN_MODE_INPUT(GPIOB_PIN18) \
| PIN_MODE_INPUT(GPIOB_PIN19) )
#define VAL_GPIOB_CFG \
( PIN_CFG_SCHMITT_EN(GPIOB_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN15) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN16) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN17) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN18) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN19) )
#define VAL_GPIOC_MODE \
( PIN_MODE_INPUT(GPIOC_PIN0) \
| PIN_MODE_INPUT(GPIOC_PIN1) \
| PIN_MODE_INPUT(GPIOC_PIN2) \
| PIN_MODE_INPUT(GPIOC_PIN3) \
| PIN_MODE_INPUT(GPIOC_PIN4) \
| PIN_MODE_INPUT(GPIOC_PIN5) \
| PIN_MODE_INPUT(GPIOC_PIN6) \
| PIN_MODE_INPUT(GPIOC_PIN7) \
| PIN_MODE_INPUT(GPIOC_PIN8) \
| PIN_MODE_INPUT(GPIOC_PIN9) \
| PIN_MODE_INPUT(GPIOC_PIN10) \
| PIN_MODE_INPUT(GPIOC_PIN11) \
| PIN_MODE_INPUT(GPIOC_PIN12) \
| PIN_MODE_INPUT(GPIOC_PIN13) \
| PIN_MODE_INPUT(GPIOC_PIN14) \
| PIN_MODE_INPUT(GPIOC_PIN15) )
#define VAL_GPIOC_CFG \
( PIN_CFG_SCHMITT_EN(GPIOC_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN15) )
#define VAL_GPIOD_MODE \
( PIN_MODE_INPUT(GPIOD_PIN3) \
| PIN_MODE_INPUT(GPIOD_PIN4) \
| PIN_MODE_INPUT(GPIOD_PIN5) \
| PIN_MODE_INPUT(GPIOD_PIN6) \
| PIN_MODE_INPUT(GPIOD_PIN7) \
| PIN_MODE_INPUT(GPIOD_PIN8) \
| PIN_MODE_INPUT(GPIOD_PIN9) \
| PIN_MODE_INPUT(GPIOD_PIN10) \
| PIN_MODE_INPUT(GPIOD_PIN11) \
| PIN_MODE_INPUT(GPIOD_PIN12) \
| PIN_MODE_INPUT(GPIOD_PIN13) \
| PIN_MODE_INPUT(GPIOD_PIN14) \
| PIN_MODE_INPUT(GPIOD_PIN15) \
| PIN_MODE_INPUT(GPIOD_PIN16) \
| PIN_MODE_INPUT(GPIOD_PIN17) \
| PIN_MODE_INPUT(GPIOD_PIN18) \
| PIN_MODE_INPUT(GPIOD_PIN19) )
#define VAL_GPIOD_CFG \
( PIN_CFG_SCHMITT_EN(GPIOD_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN15) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN16) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN17) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN18) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN19) )
#if !defined(_FROM_ASM_)
# ifdef __cplusplus
extern "C" {
# endif
void boardInit(void);
# ifdef __cplusplus
}
# endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */

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os/hal/boards/SN_SN32F280/board.mk Normal file
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# List of all the board related files.
BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F280/board.c
# Required include directories
BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F280
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
const PALConfig pal_default_config = {
#if SN32_HAS_GPIOA
{.mode = VAL_GPIOA_MODE, .cfg = VAL_GPIOA_CFG},
#endif
#if SN32_HAS_GPIOB
{.mode = VAL_GPIOB_MODE, .cfg = VAL_GPIOB_CFG},
#endif
#if SN32_HAS_GPIOC
{.mode = VAL_GPIOC_MODE, .cfg = VAL_GPIOC_CFG},
#endif
#if SN32_HAS_GPIOD
{.mode = VAL_GPIOD_MODE, .cfg = VAL_GPIOD_CFG},
#endif
};
#endif
/**
* @brief Early initialization code.
* @details This initialization must be performed just after stack setup
* and before any other initialization.
*/
void __early_init(void) {
sn32_clock_init();
}
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {
SN_SYS0->EXRSTCTRL_b.RESETDIS = 1; // Disable RESET
SN_SYS0->SWDCTRL_b.SWDDIS = 1; // Disable SWD
}
void restart_usb_driver(USBDriver *usbp) {
// Do nothing. Restarting the USB driver on these boards breaks it.
}

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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* Setup for Generic SN32F290 Board
*/
/*
* Board identifier.
*/
#define BOARD_GENERIC_SN32_F240
#define BOARD_NAME "SN32F290"
/*
* MCU type as defined in the SN32 header.
*/
#define SN32F290
/*
* IO pins assignments.
*/
#define GPIOA_PIN0 0U
#define GPIOA_PIN1 1U
#define GPIOA_PIN2 2U
#define GPIOA_PIN3 3U
#define GPIOA_PIN4 4U
#define GPIOA_PIN5 5U
#define GPIOA_PIN6 6U
#define GPIOA_PIN7 7U
#define GPIOA_PIN8 8U
#define GPIOA_PIN9 9U
#define GPIOA_PIN10 10U
#define GPIOA_PIN11 11U
#define GPIOA_PIN12 12U
#define GPIOA_PIN13 13U
#define GPIOA_PIN14 14U
#define GPIOA_PIN15 15U
#define GPIOA_PIN16 16U
#define GPIOA_PIN17 17U
#define GPIOA_PIN18 18U
#define GPIOA_PIN19 19U
#define GPIOB_PIN0 0U
#define GPIOB_PIN1 1U
#define GPIOB_PIN2 2U
#define GPIOB_PIN3 3U
#define GPIOB_PIN4 4U
#define GPIOB_PIN5 5U
#define GPIOB_PIN6 6U
#define GPIOB_PIN7 7U
#define GPIOB_PIN8 8U
#define GPIOB_PIN9 9U
#define GPIOB_PIN10 10U
#define GPIOB_PIN11 11U
#define GPIOB_PIN12 12U
#define GPIOB_PIN13 13U
#define GPIOB_PIN14 14U
#define GPIOB_PIN15 15U
#define GPIOB_PIN16 16U
#define GPIOB_PIN17 17U
#define GPIOB_PIN18 18U
#define GPIOB_PIN19 19U
#define GPIOC_PIN0 0U
#define GPIOC_PIN1 1U
#define GPIOC_PIN2 2U
#define GPIOC_PIN5 5U
#define GPIOC_PIN6 6U
#define GPIOC_PIN7 7U
#define GPIOC_PIN8 8U
#define GPIOC_PIN9 9U
#define GPIOC_PIN10 10U
#define GPIOC_PIN11 11U
#define GPIOC_PIN12 12U
#define GPIOC_PIN13 13U
#define GPIOC_PIN14 14U
#define GPIOC_PIN15 15U
#define GPIOD_PIN3 3U
#define GPIOD_PIN4 4U
#define GPIOD_PIN5 5U
#define GPIOD_PIN6 6U
#define GPIOD_PIN7 7U
#define GPIOD_PIN8 8U
#define GPIOD_PIN9 9U
#define GPIOD_PIN10 10U
#define GPIOD_PIN11 11U
#define GPIOD_PIN12 12U
#define GPIOD_PIN13 13U
#define GPIOD_PIN14 14U
#define GPIOD_PIN15 15U
#define GPIOD_PIN16 16U
#define GPIOD_PIN17 17U
#define GPIOD_PIN18 18U
#define GPIOD_PIN19 19U
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
* Please refer to the SN32 Reference Manual for details.
*/
#define PIN_MODE_INPUT(n) (0U << ((n)))
#define PIN_MODE_OUTPUT(n) (1U << ((n)))
#define PIN_CFG_PULLUP(n) (0U << ((n*2))) // Pull-up
#define PIN_CFG_SCHMITT_EN(n) (2U << ((n*2))) // Floating
#define PIN_CFG_SCHMITT_DIS(n) (3U << ((n*2))) // Input buffer disconnected, alway read as zero.
// Define GPIO register values used by pal_default_config.
// The following values match the chip reset values, all GPIO pins as floating inputs.
#define VAL_GPIOA_MODE \
( PIN_MODE_INPUT(GPIOA_PIN0) \
| PIN_MODE_INPUT(GPIOA_PIN1) \
| PIN_MODE_INPUT(GPIOA_PIN2) \
| PIN_MODE_INPUT(GPIOA_PIN3) \
| PIN_MODE_INPUT(GPIOA_PIN4) \
| PIN_MODE_INPUT(GPIOA_PIN5) \
| PIN_MODE_INPUT(GPIOA_PIN6) \
| PIN_MODE_INPUT(GPIOA_PIN7) \
| PIN_MODE_INPUT(GPIOA_PIN8) \
| PIN_MODE_INPUT(GPIOA_PIN9) \
| PIN_MODE_INPUT(GPIOA_PIN10) \
| PIN_MODE_INPUT(GPIOA_PIN11) \
| PIN_MODE_INPUT(GPIOA_PIN12) \
| PIN_MODE_INPUT(GPIOA_PIN13) \
| PIN_MODE_INPUT(GPIOA_PIN14) \
| PIN_MODE_INPUT(GPIOA_PIN15) \
| PIN_MODE_INPUT(GPIOA_PIN16) \
| PIN_MODE_INPUT(GPIOA_PIN17) \
| PIN_MODE_INPUT(GPIOA_PIN18) \
| PIN_MODE_INPUT(GPIOA_PIN19) )
#define VAL_GPIOA_CFG \
( PIN_CFG_SCHMITT_EN(GPIOA_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN15) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN16) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN17) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN18) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN19) )
#define VAL_GPIOB_MODE \
( PIN_MODE_INPUT(GPIOB_PIN0) \
| PIN_MODE_INPUT(GPIOB_PIN1) \
| PIN_MODE_INPUT(GPIOB_PIN2) \
| PIN_MODE_INPUT(GPIOB_PIN3) \
| PIN_MODE_INPUT(GPIOB_PIN4) \
| PIN_MODE_INPUT(GPIOB_PIN5) \
| PIN_MODE_INPUT(GPIOB_PIN6) \
| PIN_MODE_INPUT(GPIOB_PIN7) \
| PIN_MODE_INPUT(GPIOB_PIN8) \
| PIN_MODE_INPUT(GPIOB_PIN9) \
| PIN_MODE_INPUT(GPIOB_PIN10) \
| PIN_MODE_INPUT(GPIOB_PIN11) \
| PIN_MODE_INPUT(GPIOB_PIN12) \
| PIN_MODE_INPUT(GPIOB_PIN13) \
| PIN_MODE_INPUT(GPIOB_PIN14) \
| PIN_MODE_INPUT(GPIOB_PIN15) \
| PIN_MODE_INPUT(GPIOB_PIN16) \
| PIN_MODE_INPUT(GPIOB_PIN17) \
| PIN_MODE_INPUT(GPIOB_PIN18) \
| PIN_MODE_INPUT(GPIOB_PIN19) )
#define VAL_GPIOB_CFG \
( PIN_CFG_SCHMITT_EN(GPIOB_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN15) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN16) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN17) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN18) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN19) )
#define VAL_GPIOC_MODE \
( PIN_MODE_INPUT(GPIOC_PIN0) \
| PIN_MODE_INPUT(GPIOC_PIN1) \
| PIN_MODE_INPUT(GPIOC_PIN2) \
| PIN_MODE_INPUT(GPIOC_PIN3) \
| PIN_MODE_INPUT(GPIOC_PIN4) \
| PIN_MODE_INPUT(GPIOC_PIN5) \
| PIN_MODE_INPUT(GPIOC_PIN6) \
| PIN_MODE_INPUT(GPIOC_PIN7) \
| PIN_MODE_INPUT(GPIOC_PIN8) \
| PIN_MODE_INPUT(GPIOC_PIN9) \
| PIN_MODE_INPUT(GPIOC_PIN10) \
| PIN_MODE_INPUT(GPIOC_PIN11) \
| PIN_MODE_INPUT(GPIOC_PIN12) \
| PIN_MODE_INPUT(GPIOC_PIN13) \
| PIN_MODE_INPUT(GPIOC_PIN14) \
| PIN_MODE_INPUT(GPIOC_PIN15) )
#define VAL_GPIOC_CFG \
( PIN_CFG_SCHMITT_EN(GPIOC_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN15) )
#define VAL_GPIOD_MODE \
( PIN_MODE_INPUT(GPIOD_PIN3) \
| PIN_MODE_INPUT(GPIOD_PIN4) \
| PIN_MODE_INPUT(GPIOD_PIN5) \
| PIN_MODE_INPUT(GPIOD_PIN6) \
| PIN_MODE_INPUT(GPIOD_PIN7) \
| PIN_MODE_INPUT(GPIOD_PIN8) \
| PIN_MODE_INPUT(GPIOD_PIN9) \
| PIN_MODE_INPUT(GPIOD_PIN10) \
| PIN_MODE_INPUT(GPIOD_PIN11) \
| PIN_MODE_INPUT(GPIOD_PIN12) \
| PIN_MODE_INPUT(GPIOD_PIN13) \
| PIN_MODE_INPUT(GPIOD_PIN14) \
| PIN_MODE_INPUT(GPIOD_PIN15) \
| PIN_MODE_INPUT(GPIOD_PIN16) \
| PIN_MODE_INPUT(GPIOD_PIN17) \
| PIN_MODE_INPUT(GPIOD_PIN18) \
| PIN_MODE_INPUT(GPIOD_PIN19) )
#define VAL_GPIOD_CFG \
( PIN_CFG_SCHMITT_EN(GPIOD_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN15) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN16) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN17) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN18) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN19) )
#if !defined(_FROM_ASM_)
# ifdef __cplusplus
extern "C" {
# endif
void boardInit(void);
# ifdef __cplusplus
}
# endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */

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# List of all the board related files.
BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F290/board.c
# Required include directories
BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F290
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

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ifeq ($(USE_SMART_BUILD),yes)
ifneq ($(findstring HAL_USE_CT TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/CT/CT16B0.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/CT/CT16B1.c
endif
ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/CT/hal_gpt_lld.c
endif
ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/CT/hal_pwm_lld.c
endif
else
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/CT/CT16B0.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/CT/CT16B1.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/CT/hal_gpt_lld.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/CT/hal_pwm_lld.c
endif
PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/CT

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os/hal/ports/SN32/LLD/SN32F24xB/FLASH/driver.mk
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PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/FLASH/Flash.c
PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/FLASH

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os/hal/ports/SN32/LLD/SN32F24xB/GPIO/driver.mk
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ifeq ($(USE_SMART_BUILD),yes)
ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/GPIO/hal_pal_lld.c
endif
else
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/GPIO/hal_pal_lld.c
endif
PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/GPIO

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os/hal/ports/SN32/LLD/SN32F24xB/GPIOv3/driver.mk
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ifeq ($(USE_SMART_BUILD),yes)
ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/SN32/LLD/GPIOv3/hal_pal_lld.c
endif
else
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/SN32/LLD/GPIOv3/hal_pal_lld.c
endif
PLATFORMINC += $(CHIBIOS)/os/hal/ports/SN32/LLD/GPIOv3

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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file GPIOv3/hal_pal_lld.c
* @brief SN32 PAL low level driver code.
*
* @addtogroup PAL
* @{
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
#if defined(SN32F240B)
#define AHB2_EN_MASK SN32_GPIO_EN_MASK
#define AHB2_LPEN_MASK 0
#else
#error "missing or unsupported platform for GPIOv3 PAL driver"
#endif
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static void initgpio(sn32_gpio_t *gpiop, const sn32_gpio_setup_t *config) {
gpiop->OTYPER = config->otyper;
gpiop->ASCR = config->ascr;
gpiop->OSPEEDR = config->ospeedr;
gpiop->PUPDR = config->pupdr;
gpiop->ODR = config->odr;
gpiop->AFRL = config->afrl;
gpiop->AFRH = config->afrh;
gpiop->MODER = config->moder;
gpiop->LOCKR = config->lockr;
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief SN32 I/O ports configuration.
* @details Ports A-D(E, F, G, H) clocks enabled.
*
* @param[in] config the SN32 ports configuration
*
* @notapi
*/
void _pal_lld_init(const PALConfig *config) {
/*
* Enables the GPIO related clocks.
*/
#if defined(SN32L4XX)
RCC->AHB2ENR |= AHB2_EN_MASK;
#endif
/*
* Initial GPIO setup.
*/
#if SN32_HAS_GPIOA
initgpio(GPIOA, &config->PAData);
#endif
#if SN32_HAS_GPIOB
initgpio(GPIOB, &config->PBData);
#endif
#if SN32_HAS_GPIOC
initgpio(GPIOC, &config->PCData);
#endif
#if SN32_HAS_GPIOD
initgpio(GPIOD, &config->PDData);
#endif
#if SN32_HAS_GPIOE
initgpio(GPIOE, &config->PEData);
#endif
}
/**
* @brief Pads mode setup.
* @details This function programs a pads group belonging to the same port
* with the specified mode.
* @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum
* speed.
*
* @param[in] port the port identifier
* @param[in] mask the group mask
* @param[in] mode the mode
*
* @notapi
*/
void _pal_lld_setgroupmode(ioportid_t port,
ioportmask_t mask,
iomode_t mode) {
uint32_t moder = (mode & PAL_SN32_MODE_MASK) >> 0;
uint32_t otyper = (mode & PAL_SN32_OTYPE_MASK) >> 2;
uint32_t ospeedr = (mode & PAL_SN32_OSPEED_MASK) >> 3;
uint32_t pupdr = (mode & PAL_SN32_PUPDR_MASK) >> 5;
uint32_t altr = (mode & PAL_SN32_ALTERNATE_MASK) >> 7;
uint32_t ascr = (mode & PAL_SN32_ASCR_MASK) >> 11;
uint32_t lockr = (mode & PAL_SN32_LOCKR_MASK) >> 12;
uint32_t bit = 0;
while (true) {
if ((mask & 1) != 0) {
uint32_t altrmask, m1, m2, m4;
altrmask = altr << ((bit & 7) * 4);
m1 = 1 << bit;
m2 = 3 << (bit * 2);
m4 = 15 << ((bit & 7) * 4);
port->OTYPER = (port->OTYPER & ~m1) | otyper;
port->ASCR = (port->ASCR & ~m1) | ascr;
port->OSPEEDR = (port->OSPEEDR & ~m2) | ospeedr;
port->PUPDR = (port->PUPDR & ~m2) | pupdr;
if ((mode & PAL_SN32_MODE_MASK) == PAL_SN32_MODE_ALTERNATE) {
/* If going in alternate mode then the alternate number is set
before switching mode in order to avoid glitches.*/
if (bit < 8)
port->AFRL = (port->AFRL & ~m4) | altrmask;
else
port->AFRH = (port->AFRH & ~m4) | altrmask;
port->MODER = (port->MODER & ~m2) | moder;
}
else {
/* If going into a non-alternate mode then the mode is switched
before setting the alternate mode in order to avoid glitches.*/
port->MODER = (port->MODER & ~m2) | moder;
if (bit < 8)
port->AFRL = (port->AFRL & ~m4) | altrmask;
else
port->AFRH = (port->AFRH & ~m4) | altrmask;
}
port->LOCKR = (port->LOCKR & ~m1) | lockr;
}
mask >>= 1;
if (!mask)
return;
otyper <<= 1;
ospeedr <<= 2;
pupdr <<= 2;
moder <<= 2;
bit++;
}
}
#endif /* HAL_USE_PAL */
/** @} */

480
os/hal/ports/SN32/LLD/SN32F24xB/GPIOv3/hal_pal_lld.h
View File

@ -1,480 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file GPIOv3/hal_pal_lld.h
* @brief SN32 PAL low level driver header.
*
* @addtogroup PAL
* @{
*/
#ifndef HAL_PAL_LLD_H
#define HAL_PAL_LLD_H
#if HAL_USE_PAL || defined(__DOXYGEN__)
/*===========================================================================*/
/* Unsupported modes and specific modes */
/*===========================================================================*/
#undef PAL_MODE_RESET
#undef PAL_MODE_UNCONNECTED
#undef PAL_MODE_INPUT
#undef PAL_MODE_INPUT_PULLUP
#undef PAL_MODE_INPUT_PULLDOWN
#undef PAL_MODE_INPUT_ANALOG
#undef PAL_MODE_OUTPUT_PUSHPULL
#undef PAL_MODE_OUTPUT_OPENDRAIN
/**
* @name SN32-specific I/O mode flags
* @{
*/
#define PAL_SN32_MODE_MASK (3U << 0U)
#define PAL_SN32_MODE_INPUT (0U << 0U)
#define PAL_SN32_MODE_OUTPUT (1U << 0U)
#define PAL_SN32_MODE_ALTERNATE (2U << 0U)
#define PAL_SN32_MODE_ANALOG (3U << 0U)
#define PAL_SN32_OTYPE_MASK (1U << 2U)
#define PAL_SN32_OTYPE_PUSHPULL (0U << 2U)
#define PAL_SN32_OTYPE_OPENDRAIN (1U << 2U)
#define PAL_SN32_OSPEED_MASK (3U << 3U)
#define PAL_SN32_OSPEED_LOW (0U << 3U)
#define PAL_SN32_OSPEED_MEDIUM (1U << 3U)
#define PAL_SN32_OSPEED_FAST (2U << 3U)
#define PAL_SN32_OSPEED_HIGH (3U << 3U)
#define PAL_SN32_PUPDR_MASK (3U << 5U)
#define PAL_SN32_PUPDR_FLOATING (0U << 5U)
#define PAL_SN32_PUPDR_PULLUP (1U << 5U)
#define PAL_SN32_PUPDR_PULLDOWN (2U << 5U)
#define PAL_SN32_ALTERNATE_MASK (15U << 7U)
#define PAL_SN32_ALTERNATE(n) ((n) << 7U)
#define PAL_SN32_ASCR_MASK (1U << 11U)
#define PAL_SN32_ASCR_OFF (0U << 11U)
#define PAL_SN32_ASCR_ON (1U << 11U)
#define PAL_SN32_LOCKR_MASK (1U << 12U)
#define PAL_SN32_LOCKR_OFF (0U << 12U)
#define PAL_SN32_LOCKR_ON (1U << 12U)
/**
* @brief Alternate function.
*
* @param[in] n alternate function selector
*/
#define PAL_MODE_ALTERNATE(n) (PAL_SN32_MODE_ALTERNATE | \
PAL_SN32_ALTERNATE(n))
/** @} */
/**
* @name Standard I/O mode flags
* @{
*/
/**
* @brief Implemented as input.
*/
#define PAL_MODE_RESET PAL_SN32_MODE_INPUT
/**
* @brief Implemented as analog with analog switch disabled and lock.
*/
#define PAL_MODE_UNCONNECTED (PAL_SN32_MODE_ANALOG | \
PAL_SN32_ASCR_OFF | \
PAL_SN32_LOCKR_ON)
/**
* @brief Regular input high-Z pad.
*/
#define PAL_MODE_INPUT PAL_SN32_MODE_INPUT
/**
* @brief Input pad with weak pull up resistor.
*/
#define PAL_MODE_INPUT_PULLUP (PAL_SN32_MODE_INPUT | \
PAL_SN32_PUPDR_PULLUP)
/**
* @brief Input pad with weak pull down resistor.
*/
#define PAL_MODE_INPUT_PULLDOWN (PAL_SN32_MODE_INPUT | \
PAL_SN32_PUPDR_PULLDOWN)
/**
* @brief Analog input mode.
*/
#define PAL_MODE_INPUT_ANALOG (PAL_SN32_MODE_ANALOG | \
PAL_SN32_ASCR_ON)
/**
* @brief Push-pull output pad.
*/
#define PAL_MODE_OUTPUT_PUSHPULL (PAL_SN32_MODE_OUTPUT | \
PAL_SN32_OTYPE_PUSHPULL)
/**
* @brief Open-drain output pad.
*/
#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_SN32_MODE_OUTPUT | \
PAL_SN32_OTYPE_OPENDRAIN)
/** @} */
/* Discarded definitions from the ST headers, the PAL driver uses its own
definitions in order to have an unified handling for all devices.
Unfortunately the ST headers have no uniform definitions for the same
objects across the various sub-families.*/
#undef GPIOA
#undef GPIOB
#undef GPIOC
#undef GPIOD
/**
* @name GPIO ports definitions
* @{
*/
#define GPIOA ((sn32_gpio_t *)GPIOA_BASE)
#define GPIOB ((sn32_gpio_t *)GPIOB_BASE)
#define GPIOC ((sn32_gpio_t *)GPIOC_BASE)
#define GPIOD ((sn32_gpio_t *)GPIOD_BASE)
/** @} */
/*===========================================================================*/
/* I/O Ports Types and constants. */
/*===========================================================================*/
/**
* @name Port related definitions
* @{
*/
/**
* @brief Width, in bits, of an I/O port.
*/
#define PAL_IOPORTS_WIDTH 16
/**
* @brief Whole port mask.
* @details This macro specifies all the valid bits into a port.
*/
#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
/** @} */
/**
* @name Line handling macros
* @{
*/
/**
* @brief Forms a line identifier.
* @details A port/pad pair are encoded into an @p ioline_t type. The encoding
* of this type is platform-dependent.
* @note In this driver the pad number is encoded in the lower 4 bits of
* the GPIO address which are guaranteed to be zero.
*/
#define PAL_LINE(port, pad) \
((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad)))
/**
* @brief Decodes a port identifier from a line identifier.
*/
#define PAL_PORT(line) \
((sn32_gpio_t *)(((uint32_t)(line)) & 0xFFFFFFF0U))
/**
* @brief Decodes a pad identifier from a line identifier.
*/
#define PAL_PAD(line) \
((uint32_t)((uint32_t)(line) & 0x0000000FU))
/**
* @brief Value identifying an invalid line.
*/
#define PAL_NOLINE 0U
/** @} */
/**
* @brief SN32 GPIO registers block.
*/
typedef struct {
volatile uint32_t MODER;
volatile uint32_t OTYPER;
volatile uint32_t OSPEEDR;
volatile uint32_t PUPDR;
volatile uint32_t IDR;
volatile uint32_t ODR;
volatile union {
uint32_t W;
struct {
uint16_t set;
uint16_t clear;
} H;
} BSRR;
volatile uint32_t LOCKR;
volatile uint32_t AFRL;
volatile uint32_t AFRH;
volatile uint32_t BRR;
volatile uint32_t ASCR;
} sn32_gpio_t;
/**
* @brief GPIO port setup info.
*/
typedef struct {
/** Initial value for MODER register.*/
uint32_t moder;
/** Initial value for OTYPER register.*/
uint32_t otyper;
/** Initial value for OSPEEDR register.*/
uint32_t ospeedr;
/** Initial value for PUPDR register.*/
uint32_t pupdr;
/** Initial value for ODR register.*/
uint32_t odr;
/** Initial value for AFRL register.*/
uint32_t afrl;
/** Initial value for AFRH register.*/
uint32_t afrh;
/** Initial value for ASCR register.*/
uint32_t ascr;
/** Initial value for LOCKR register.*/
uint32_t lockr;
} sn32_gpio_setup_t;
/**
* @brief SN32 GPIO static initializer.
* @details An instance of this structure must be passed to @p palInit() at
* system startup time in order to initialize the digital I/O
* subsystem. This represents only the initial setup, specific pads
* or whole ports can be reprogrammed at later time.
*/
typedef struct {
#if SN32_HAS_GPIOA || defined(__DOXYGEN__)
/** @brief Port A setup data.*/
sn32_gpio_setup_t PAData;
#endif
#if SN32_HAS_GPIOB || defined(__DOXYGEN__)
/** @brief Port B setup data.*/
sn32_gpio_setup_t PBData;
#endif
#if SN32_HAS_GPIOC || defined(__DOXYGEN__)
/** @brief Port C setup data.*/
sn32_gpio_setup_t PCData;
#endif
#if SN32_HAS_GPIOD || defined(__DOXYGEN__)
/** @brief Port D setup data.*/
sn32_gpio_setup_t PDData;
#endif
} PALConfig;
/**
* @brief Type of digital I/O port sized unsigned integer.
*/
typedef uint32_t ioportmask_t;
/**
* @brief Type of digital I/O modes.
*/
typedef uint32_t iomode_t;
/**
* @brief Type of an I/O line.
*/
typedef uint32_t ioline_t;
/**
* @brief Port Identifier.
* @details This type can be a scalar or some kind of pointer, do not make
* any assumption about it, use the provided macros when populating
* variables of this type.
*/
typedef sn32_gpio_t * ioportid_t;
/*===========================================================================*/
/* I/O Ports Identifiers. */
/* The low level driver wraps the definitions already present in the SN32 */
/* firmware library. */
/*===========================================================================*/
/**
* @brief GPIO port A identifier.
*/
#if SN32_HAS_GPIOA || defined(__DOXYGEN__)
#define IOPORT1 GPIOA
#endif
/**
* @brief GPIO port B identifier.
*/
#if SN32_HAS_GPIOB || defined(__DOXYGEN__)
#define IOPORT2 GPIOB
#endif
/**
* @brief GPIO port C identifier.
*/
#if SN32_HAS_GPIOC || defined(__DOXYGEN__)
#define IOPORT3 GPIOC
#endif
/**
* @brief GPIO port D identifier.
*/
#if SN32_HAS_GPIOD || defined(__DOXYGEN__)
#define IOPORT4 GPIOD
#endif
/*===========================================================================*/
/* Implementation, some of the following macros could be implemented as */
/* functions, if so please put them in pal_lld.c. */
/*===========================================================================*/
/**
* @brief GPIO ports subsystem initialization.
*
* @notapi
*/
#define pal_lld_init(config) _pal_lld_init(config)
/**
* @brief Reads an I/O port.
* @details This function is implemented by reading the GPIO IDR register, the
* implementation has no side effects.
* @note This function is not meant to be invoked directly by the application
* code.
*
* @param[in] port port identifier
* @return The port bits.
*
* @notapi
*/
#define pal_lld_readport(port) ((port)->IDR)
/**
* @brief Reads the output latch.
* @details This function is implemented by reading the GPIO ODR register, the
* implementation has no side effects.
* @note This function is not meant to be invoked directly by the application
* code.
*
* @param[in] port port identifier
* @return The latched logical states.
*
* @notapi
*/
#define pal_lld_readlatch(port) ((port)->ODR)
/**
* @brief Writes on a I/O port.
* @details This function is implemented by writing the GPIO ODR register, the
* implementation has no side effects.
*
* @param[in] port port identifier
* @param[in] bits bits to be written on the specified port
*
* @notapi
*/
#define pal_lld_writeport(port, bits) ((port)->ODR = (bits))
/**
* @brief Sets a bits mask on a I/O port.
* @details This function is implemented by writing the GPIO BSRR register, the
* implementation has no side effects.
*
* @param[in] port port identifier
* @param[in] bits bits to be ORed on the specified port
*
* @notapi
*/
#define pal_lld_setport(port, bits) ((port)->BSRR.H.set = (uint16_t)(bits))
/**
* @brief Clears a bits mask on a I/O port.
* @details This function is implemented by writing the GPIO BSRR register, the
* implementation has no side effects.
*
* @param[in] port port identifier
* @param[in] bits bits to be cleared on the specified port
*
* @notapi
*/
#define pal_lld_clearport(port, bits) ((port)->BSRR.H.clear = (uint16_t)(bits))
/**
* @brief Writes a group of bits.
* @details This function is implemented by writing the GPIO BSRR register, the
* implementation has no side effects.
*
* @param[in] port port identifier
* @param[in] mask group mask
* @param[in] offset the group bit offset within the port
* @param[in] bits bits to be written. Values exceeding the group
* width are masked.
*
* @notapi
*/
#define pal_lld_writegroup(port, mask, offset, bits) \
((port)->BSRR.W = ((~(bits) & (mask)) << (16U + (offset))) | \
(((bits) & (mask)) << (offset)))
/**
* @brief Pads group mode setup.
* @details This function programs a pads group belonging to the same port
* with the specified mode.
*
* @param[in] port port identifier
* @param[in] mask group mask
* @param[in] offset group bit offset within the port
* @param[in] mode group mode
*
* @notapi
*/
#define pal_lld_setgroupmode(port, mask, offset, mode) \
_pal_lld_setgroupmode(port, mask << offset, mode)
/**
* @brief Writes a logical state on an output pad.
*
* @param[in] port port identifier
* @param[in] pad pad number within the port
* @param[in] bit logical value, the value must be @p PAL_LOW or
* @p PAL_HIGH
*
* @notapi
*/
#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit)
extern const PALConfig pal_default_config;
#ifdef __cplusplus
extern "C" {
#endif
void _pal_lld_init(const PALConfig *config);
void _pal_lld_setgroupmode(ioportid_t port,
ioportmask_t mask,
iomode_t mode);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_PAL */
#endif /* HAL_PAL_LLD_H */
/** @} */

9
os/hal/ports/SN32/LLD/SN32F24xB/SysTick/driver.mk
View File

@ -1,9 +0,0 @@
ifeq ($(USE_SMART_BUILD),yes)
ifneq ($(findstring HAL_USE_SYSTICK TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/SysTick/hal_st_lld.c
endif
else
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/SysTick/hal_st_lld.c
endif
PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/SysTick

4
os/hal/ports/SN32/LLD/SN32F24xB/USB/driver.mk
View File

@ -1,4 +0,0 @@
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/USB/hal_usb_lld.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/USB/usbhw.c
PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24xB/USB

6
os/hal/ports/SN32/LLD/SN32F24xB/ADC/ADC.c → os/hal/ports/SN32/LLD/SN32F2xx/ADC/ADC.c
View File

@ -18,11 +18,9 @@
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F2xx.h>
#include <SN32F200_Def.h>
#include "ADC.h"
#include "..\..\Utility\Utility.h"
#include "ADC.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
uint8_t bADC_StartConv;

8
os/hal/ports/SN32/LLD/SN32F24xB/ADC/ADC.h → os/hal/ports/SN32/LLD/SN32F2xx/ADC/ADC.h
View File

@ -1,8 +1,8 @@
#ifndef __SN32F240B_ADC_H
#define __SN32F240B_ADC_H
#ifndef __SN32F2XX_ADC_H
#define __SN32F2XX_ADC_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F2xx.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
//ADC Internal Reference Voltage level
@ -114,4 +114,4 @@ uint16_t ADC_Read(void);
void ADC_NvicEnable(void);
void ADC_NvicDisable(void);
#endif /*__SN32F240B_ADC_H*/
#endif /*__SN32F2XX_ADC_H*/

6
os/hal/ports/SN32/LLD/SN32F24xB/CT/CT16.h → os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16.h
View File

@ -1,5 +1,5 @@
#ifndef __SN32F240_CT16_H
#define __SN32F240_CT16_H
#ifndef __SN32F2XX_CT16_H
#define __SN32F2XX_CT16_H
/*_____ I N C L U D E S ____________________________________________________*/
@ -1327,4 +1327,4 @@ Base Address: 0x4000 0000 (CT16B0)
#define mskCT16_CAP0IC mskCT16_CAP0IF
/*_____ M A C R O S ________________________________________________________*/
#endif //*__SN32F240B_CT16_H
#endif //*__SN32F2XX_CT16_H

2
os/hal/ports/SN32/LLD/SN32F24xB/CT/CT16B0.c → os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.c
View File

@ -18,7 +18,7 @@
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F2xx.h>
#include "CT16.h"
#include "CT16B0.h"

0
os/hal/ports/SN32/LLD/SN32F24xB/CT/CT16B0.h → os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.h
View File

5
os/hal/ports/SN32/LLD/SN32F24xB/CT/CT16B1.c → os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.c
View File

@ -18,7 +18,8 @@
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F2xx.h>
#include "sn32_ct.h"
#include "CT16.h"
#include "CT16B1.h"
@ -340,6 +341,7 @@ void CT16B1_IRQHandler(void)
SN_CT16B1->IC = mskCT16_MR23IC; //Clear MR23 match interrupt status
}
}
#if SN32_CT16B1_CHANNELS > 23
//MR24
if (SN_CT16B1->MCTRL3_b.MR24IE) //Check if MR24 IE enables?
{
@ -349,6 +351,7 @@ void CT16B1_IRQHandler(void)
SN_CT16B1->IC = mskCT16_MR24IC; //Clear MR24 match interrupt status
}
}
#endif
}

6
os/hal/ports/SN32/LLD/SN32F24xB/CT/CT16B1.h → os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.h
View File

@ -1,5 +1,5 @@
#ifndef __SN32F240_CT16B1_H
#define __SN32F240_CT16B1_H
#ifndef __SN32F2XX_CT16B1_H
#define __SN32F2XX_CT16B1_H
/*_____ I N C L U D E S ____________________________________________________*/
@ -25,4 +25,4 @@ extern void CT16B1_ResetTimer(void);
extern void CT16B1_NvicEnable(void);
extern void CT16B1_NvicDisable(void);
extern void CT16B1_IRQHandler(void);
#endif /*__SN32F240_CT16B1_H*/
#endif /*__SN32F2XX_CT16B1_H*/

19
os/hal/ports/SN32/LLD/SN32F2xx/CT/driver.mk Normal file
View File

@ -0,0 +1,19 @@
ifeq ($(USE_SMART_BUILD),yes)
ifneq ($(findstring HAL_USE_CT TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.c
endif
ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.c
endif
ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.c
endif
else
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.c
endif
PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/CT

0
os/hal/ports/SN32/LLD/SN32F24xB/CT/hal_gpt_lld.c → os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.c
View File

0
os/hal/ports/SN32/LLD/SN32F24xB/CT/hal_gpt_lld.h → os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.h
View File

0
os/hal/ports/SN32/LLD/SN32F24xB/CT/hal_pwm_lld.c → os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.c
View File

0
os/hal/ports/SN32/LLD/SN32F24xB/CT/hal_pwm_lld.h → os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.h
View File

0
os/hal/ports/SN32/LLD/SN32F24xB/CT/sn32_ct.h → os/hal/ports/SN32/LLD/SN32F2xx/CT/sn32_ct.h
View File

0
os/hal/ports/SN32/LLD/SN32F24xB/FLASH/Flash.c → os/hal/ports/SN32/LLD/SN32F2xx/FLASH/Flash.c
View File

8
os/hal/ports/SN32/LLD/SN32F24xB/FLASH/Flash.h → os/hal/ports/SN32/LLD/SN32F2xx/FLASH/Flash.h
View File

@ -1,8 +1,8 @@
#ifndef __SN32F240B_FLASH_H
#define __SN32F240B_FLASH_H
#ifndef __SN32F2XX_FLASH_H
#define __SN32F2XX_FLASH_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F2xx.h>
#include <SN32F200_Def.h>
@ -45,4 +45,4 @@ FLASH_Status FLASH_ProgramPage (uint32_t, uint32_t, uint32_t);
FLASH_Status FLASH_ProgramDWord(uint32_t, uint32_t);
uint16_t FLASH_Checksum(void);
#endif /* __SN32F240B_FLASH_H */
#endif /* __SN32F2XX_FLASH_H */

3
os/hal/ports/SN32/LLD/SN32F2xx/FLASH/driver.mk Normal file
View File

@ -0,0 +1,3 @@
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/FLASH/Flash.c
PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/FLASH

0
os/hal/ports/SN32/LLD/SN32F24xB/GPIO/GPIO.c → os/hal/ports/SN32/LLD/SN32F2xx/GPIO/GPIO.c
View File

8
os/hal/ports/SN32/LLD/SN32F24xB/GPIO/GPIO.h → os/hal/ports/SN32/LLD/SN32F2xx/GPIO/GPIO.h
View File

@ -1,8 +1,8 @@
#ifndef __SN32F240B_GPIO_H
#define __SN32F240B_GPIO_H
#ifndef __SN32F2XX_GPIO_H
#define __SN32F2XX_GPIO_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F2xx.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
@ -107,4 +107,4 @@ void GPIO_IntClr(uint32_t port_number, uint32_t pin_number);
void GPIO_Config(uint32_t port_number, uint32_t pin_number, uint32_t value);
void GPIO_OpenDrain(uint32_t port_number, uint32_t pin_number, uint32_t value);
uint32_t GPIO_IntStatus(uint32_t port_number, uint32_t pin_number);
#endif /*__SN32F240B_GPIO_H*/
#endif /*__SN32F2XX_GPIO_H*/

9
os/hal/ports/SN32/LLD/SN32F2xx/GPIO/driver.mk Normal file
View File

@ -0,0 +1,9 @@
ifeq ($(USE_SMART_BUILD),yes)
ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.c
endif
else
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.c
endif
PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/GPIO

0
os/hal/ports/SN32/LLD/SN32F24xB/GPIO/hal_pal_lld.c → os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.c
View File

0
os/hal/ports/SN32/LLD/SN32F24xB/GPIO/hal_pal_lld.h → os/hal/ports/SN32/LLD/SN32F2xx/GPIO/hal_pal_lld.h
View File

2
os/hal/ports/SN32/LLD/SN32F24xB/I2C/I2C.c → os/hal/ports/SN32/LLD/SN32F2xx/I2C/I2C.c
View File

@ -18,7 +18,7 @@
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F2xx.h>
#include <SN32F200_Def.h>
#include "I2C.h"

6
os/hal/ports/SN32/LLD/SN32F24xB/I2C/I2C.h → os/hal/ports/SN32/LLD/SN32F2xx/I2C/I2C.h
View File

@ -1,5 +1,5 @@
#ifndef __SN32F240B_I2C_H
#define __SN32F240B_I2C_H
#ifndef __SN32F2XX_I2C_H
#define __SN32F2XX_I2C_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <stdint.h>
@ -117,4 +117,4 @@ void I2C_Start(void);
void I2C_Stop(void);
uint8_t I2C_Read(uint16_t eeprom_adr, uint8_t read_num);
uint8_t I2C_Write(uint16_t eeprom_adr, uint8_t write_num);
#endif
#endif /*__SN32F2XX_I2C_H*/

3
os/hal/ports/SN32/LLD/SN32F24xB/I2S/I2S.c → os/hal/ports/SN32/LLD/SN32F2xx/I2S/I2S.c
View File

@ -20,9 +20,8 @@
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F2xx.h>
#include "I2S.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/

6
os/hal/ports/SN32/LLD/SN32F24xB/I2S/I2S.h → os/hal/ports/SN32/LLD/SN32F2xx/I2S/I2S.h
View File

@ -1,5 +1,5 @@
#ifndef __SN32F240_I2S_H
#define __SN32F240_I2S_H
#ifndef __SN32F2XX_I2S_H
#define __SN32F2XX_I2S_H
/*_____ I N C L U D E S ____________________________________________________*/
@ -213,4 +213,4 @@ void I2S_Enable(void);
void I2S_Disable(void);
void I2S_Interrupt_Enable(void);
#endif /*__SN32F240_I2S_H*/
#endif /*__SN32F2XX_I2S_H*/

2
os/hal/ports/SN32/LLD/SN32F24xB/PMU/PMU_drive.c → os/hal/ports/SN32/LLD/SN32F2xx/PMU/PMU_drive.c
View File

@ -18,7 +18,7 @@
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F2xx.h>
/*_____ D E C L A R A T I O N S ____________________________________________*/

6
os/hal/ports/SN32/LLD/SN32F24xB/PMU/PMU_drive.h → os/hal/ports/SN32/LLD/SN32F2xx/PMU/PMU_drive.h
View File

@ -1,5 +1,5 @@
#ifndef __SN32F240B_PMU_H
#define __SN32F240B_PMU_H
#ifndef __SN32F2XX_PMU_H
#define __SN32F2XX_PMU_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <stdint.h>
@ -15,4 +15,4 @@
/*_____ D E C L A R A T I O N S ____________________________________________*/
void PMU_Setting(uint16_t mode_sel);
#endif /*__SN32F240B_PMU_H*/
#endif /*__SN32F2XX_PMU_H*/

6
os/hal/ports/SN32/LLD/SN32F24xB/SPI/SPI.h → os/hal/ports/SN32/LLD/SN32F2xx/SPI/SPI.h
View File

@ -1,5 +1,5 @@
#ifndef __SN32F240_SSP_H
#define __SN32F240_SSP_H
#ifndef __SN32F2XX_SSP_H
#define __SN32F2XX_SSP_H
/*_____ I N C L U D E S ____________________________________________________*/
@ -184,5 +184,5 @@ extern void SPI0_Disable(void);
extern void SPI1_Init(void);
extern void SPI1_Enable(void);
extern void SPI1_Disable(void);
#endif /*__SN32F760_SSP_H*/
#endif /*__SN32F2XX_SSP_H*/

3
os/hal/ports/SN32/LLD/SN32F24xB/SPI/SPI0.c → os/hal/ports/SN32/LLD/SN32F2xx/SPI/SPI0.c
View File

@ -19,9 +19,8 @@
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F2xx.h>
#include "SPI.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/

3
os/hal/ports/SN32/LLD/SN32F24xB/SPI/SPI1.c → os/hal/ports/SN32/LLD/SN32F2xx/SPI/SPI1.c
View File

@ -19,9 +19,8 @@
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F2xx.h>
#include "SPI.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/

0
os/hal/ports/SN32/LLD/SN32F24xB/SysTick/SysTick.c → os/hal/ports/SN32/LLD/SN32F2xx/SysTick/SysTick.c
View File

8
os/hal/ports/SN32/LLD/SN32F24xB/SysTick/SysTick.h → os/hal/ports/SN32/LLD/SN32F2xx/SysTick/SysTick.h
View File

@ -1,9 +1,9 @@
#ifndef __SN32F240B_SYSTICK_H
#define __SN32F240B_SYSTICK_H
#ifndef __SN32F2XX_SYSTICK_H
#define __SN32F2XX_SYSTICK_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F2xx.h>
#include <SN32F200_Def.h>
@ -20,4 +20,4 @@
/*_____ D E C L A R A T I O N S ____________________________________________*/
void SysTick_Init(void);
#endif /*__SN32F240B_SYSTICK_H*/
#endif /*__SN32F2XX_SYSTICK_H*/

9
os/hal/ports/SN32/LLD/SN32F2xx/SysTick/driver.mk Normal file
View File

@ -0,0 +1,9 @@
ifeq ($(USE_SMART_BUILD),yes)
ifneq ($(findstring HAL_USE_SYSTICK TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.c
endif
else
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.c
endif
PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/SysTick

0
os/hal/ports/SN32/LLD/SN32F24xB/SysTick/hal_st_lld.c → os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.c
View File

0
os/hal/ports/SN32/LLD/SN32F24xB/SysTick/hal_st_lld.h → os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.h
View File

6
os/hal/ports/SN32/LLD/SN32F24xB/UART/UART.h → os/hal/ports/SN32/LLD/SN32F2xx/UART/UART.h
View File

@ -1,5 +1,5 @@
#ifndef __SN32F240B_UART_H
#define __SN32F240B_UART_H
#ifndef __SN32F2XX_UART_H
#define __SN32F2XX_UART_H
/*_____ I N C L U D E S ____________________________________________________*/
@ -180,5 +180,5 @@ void UART2_Disable(void);
void UART2_InterruptEnable(void);
void UART2_AutoBaudrateInit(void);
#endif /*__SN32F240B_UART_H*/
#endif /*__SN32F2XX_UART_H*/

4
os/hal/ports/SN32/LLD/SN32F24xB/UART/UART0.c → os/hal/ports/SN32/LLD/SN32F2xx/UART/UART0.c
View File

@ -18,10 +18,8 @@
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F2xx.h>
#include "UART.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
volatile uint8_t bUART0_RecvNew;

4
os/hal/ports/SN32/LLD/SN32F24xB/UART/UART1.c → os/hal/ports/SN32/LLD/SN32F2xx/UART/UART1.c
View File

@ -18,10 +18,8 @@
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F2xx.h>
#include "UART.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
volatile uint8_t bUART1_RecvNew;

4
os/hal/ports/SN32/LLD/SN32F24xB/UART/UART2.c → os/hal/ports/SN32/LLD/SN32F2xx/UART/UART2.c
View File

@ -18,10 +18,8 @@
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F2xx.h>
#include "UART.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
volatile uint8_t bUART2_RecvNew;

4
os/hal/ports/SN32/LLD/SN32F2xx/USB/driver.mk Normal file
View File

@ -0,0 +1,4 @@
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/USB/hal_usb_lld.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/USB/usbhw.c
PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/USB

2
os/hal/ports/SN32/LLD/SN32F24xB/USB/hal_usb_lld.c → os/hal/ports/SN32/LLD/SN32F2xx/USB/hal_usb_lld.c
View File

@ -22,7 +22,7 @@
* @{
*/
#include <SN32F240B.h>
#include <SN32F2xx.h>
#include <string.h>
#include "hal.h"
#include "usbhw.h"

0
os/hal/ports/SN32/LLD/SN32F24xB/USB/hal_usb_lld.h → os/hal/ports/SN32/LLD/SN32F2xx/USB/hal_usb_lld.h
View File

0
os/hal/ports/SN32/LLD/SN32F24xB/USB/sn32_usb.h → os/hal/ports/SN32/LLD/SN32F2xx/USB/sn32_usb.h
View File

2
os/hal/ports/SN32/LLD/SN32F24xB/USB/usbhw.c → os/hal/ports/SN32/LLD/SN32F2xx/USB/usbhw.c
View File

@ -6,7 +6,7 @@
* Version: V1.01
* Date: 2017/07
*------------------------------------------------------------------------------*/
#include <SN32F240B.h>
#include <SN32F2xx.h>
#include "SN32F200_Def.h"
#include "usbhw.h"

0
os/hal/ports/SN32/LLD/SN32F24xB/USB/usbhw.h → os/hal/ports/SN32/LLD/SN32F2xx/USB/usbhw.h
View File

2
os/hal/ports/SN32/LLD/SN32F24xB/WDT/WDT.c → os/hal/ports/SN32/LLD/SN32F2xx/WDT/WDT.c
View File

@ -18,7 +18,7 @@
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F2xx.h>
#include <SN32F200_Def.h>
#include "WDT.h"

8
os/hal/ports/SN32/LLD/SN32F24xB/WDT/WDT.h → os/hal/ports/SN32/LLD/SN32F2xx/WDT/WDT.h
View File

@ -1,8 +1,8 @@
#ifndef __SN32F240B_WDT_H
#define __SN32F240B_WDT_H
#ifndef __SN32F2XX_WDT_H
#define __SN32F2XX_WDT_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240B.h>
#include <SN32F2xx.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
#define RESET 0 //WDT as Reset mode
@ -45,4 +45,4 @@ void WDT_Init(void);
void WDT_ReloadValue(uint32_t time);
void WDT_NvicEnable(void);
void WDT_NvicDisable(void);
#endif /*__SN32F240B_WDT_H*/
#endif /*__SN32F2XX_WDT_H*/

18
os/hal/ports/SN32/SN32F240B/platform.mk
View File

@ -24,17 +24,17 @@ else
endif
# Drivers compatible with the platform.
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/GPIO/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/USB/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/CT/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/FLASH/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/SysTick/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/USB/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/CT/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/FLASH/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/driver.mk
# include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/TIM/driver.mk
# include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/GPIOv3/driver.mk
# include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/USBv1/driver.mk
# include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/TIMv1/driver.mk
# include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/TIM/driver.mk
# include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/GPIOv3/driver.mk
# include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/USBv1/driver.mk
# include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/TIMv1/driver.mk
# PLATFORMINC += $(CHIBIOS)/os/hal/templates/
# PLATFORMSRC += ${CHIBIOS}/os/hal/templates/hal_usb_lld.c

10
os/hal/ports/SN32/SN32F260/platform.mk
View File

@ -24,11 +24,11 @@ else
endif
# Drivers compatible with the platform.
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/GPIO/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/USB/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/CT/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/FLASH/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F24xB/SysTick/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/GPIO/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/USB/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/CT/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/FLASH/driver.mk
include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/driver.mk
# include $(CHIBIOS)/os/hal/ports/SN32/LLD/TIM/driver.mk