From f53e4267802dfbcc8692a7ea76d4da92600ca09f Mon Sep 17 00:00:00 2001 From: Konstantin Oblaukhov Date: Sun, 5 Jan 2020 12:11:10 +0700 Subject: [PATCH] Update NRF52832 device headers to latest version from NRF5 SDK. --- .../ARMCMx/devices/NRF52832/cmparams.h | 2 +- os/hal/ports/NRF5/LLD/TWIv1/hal_i2c_lld.c | 5 - os/hal/ports/NRF5/NRF52832/hal_lld.c | 6 +- os/hal/ports/NRF5/NRF52832/hal_lld.h | 12 +- os/hal/ports/NRF5/NRF52832/nrf.h | 61 + os/hal/ports/NRF5/NRF52832/nrf51_to_nrf52.h | 2372 +++++++++++ os/hal/ports/NRF5/NRF52832/nrf52.h | 3667 +++++++++-------- os/hal/ports/NRF5/NRF52832/nrf52_bitfields.h | 2815 ++----------- .../ports/NRF5/NRF52832/nrf52_name_change.h | 91 + 9 files changed, 4815 insertions(+), 4216 deletions(-) create mode 100644 os/hal/ports/NRF5/NRF52832/nrf.h create mode 100644 os/hal/ports/NRF5/NRF52832/nrf51_to_nrf52.h create mode 100644 os/hal/ports/NRF5/NRF52832/nrf52_name_change.h diff --git a/os/common/startup/ARMCMx/devices/NRF52832/cmparams.h b/os/common/startup/ARMCMx/devices/NRF52832/cmparams.h index b349291b..cea9d97c 100644 --- a/os/common/startup/ARMCMx/devices/NRF52832/cmparams.h +++ b/os/common/startup/ARMCMx/devices/NRF52832/cmparams.h @@ -65,7 +65,7 @@ /* Including the device CMSIS header. Note, we are not using the definitions from this header because we need this file to be usable also from assembler source files. We verify that the info matches instead.*/ -#include "nrf52.h" +#include "nrf.h" #if CORTEX_MODEL != __CORTEX_M #error "CMSIS __CORTEX_M mismatch" diff --git a/os/hal/ports/NRF5/LLD/TWIv1/hal_i2c_lld.c b/os/hal/ports/NRF5/LLD/TWIv1/hal_i2c_lld.c index a9391dda..0efd2b96 100644 --- a/os/hal/ports/NRF5/LLD/TWIv1/hal_i2c_lld.c +++ b/os/hal/ports/NRF5/LLD/TWIv1/hal_i2c_lld.c @@ -299,13 +299,8 @@ void i2c_lld_start(I2CDriver *i2cp) { (void)i2c->EVENTS_RXDREADY; (void)i2c->EVENTS_TXDSENT; #endif -#if NRF_SERIES == 51 i2c->PSELSCL = cfg->scl_pad; i2c->PSELSDA = cfg->sda_pad; -#else - i2c->PSEL.SCL = cfg->scl_pad; - i2c->PSEL.SDA = cfg->sda_pad; -#endif switch (cfg->clock) { case 100000: diff --git a/os/hal/ports/NRF5/NRF52832/hal_lld.c b/os/hal/ports/NRF5/NRF52832/hal_lld.c index 11307f82..6dffeb60 100644 --- a/os/hal/ports/NRF5/NRF52832/hal_lld.c +++ b/os/hal/ports/NRF5/NRF52832/hal_lld.c @@ -63,7 +63,7 @@ void hal_lld_init(void) #error "A 32Mhz crystal is mandatory on nRF52 boards." #endif -#if (NRF5_HFCLK_SOURCE == NRF5_HFCLK_HFXO) +#if (NRF5_HFCLK_SOURCE == CLOCK_HFCLKSTAT_SRC_Xtal) NRF_CLOCK->EVENTS_HFCLKSTARTED = 0; NRF_CLOCK->TASKS_HFCLKSTART = 1; while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0); @@ -73,14 +73,14 @@ void hal_lld_init(void) */ #if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) #if (NRF5_ST_USE_RTC0 || NRF5_ST_USE_RTC1) && \ - (NRF5_LFCLK_SOURCE == NRF5_LFCLK_RC) + (NRF5_LFCLK_SOURCE == CLOCK_LFCLKSTAT_SRC_RC) #error "A NRF5_SYSTEM_TICKS_AS_RTC requires LFCLK clock to be started." #endif #endif NRF_CLOCK->TASKS_LFCLKSTOP = 1; -#if (NRF5_LFCLK_SOURCE != NRF5_LFCLK_RC) +#if (NRF5_LFCLK_SOURCE != CLOCK_LFCLKSTAT_SRC_RC) NRF_CLOCK->LFCLKSRC = NRF5_LFCLK_SOURCE; NRF_CLOCK->EVENTS_LFCLKSTARTED = 0; diff --git a/os/hal/ports/NRF5/NRF52832/hal_lld.h b/os/hal/ports/NRF5/NRF52832/hal_lld.h index 0620b5f9..f56c5905 100644 --- a/os/hal/ports/NRF5/NRF52832/hal_lld.h +++ b/os/hal/ports/NRF5/NRF52832/hal_lld.h @@ -66,7 +66,7 @@ * 1 : 32 MHz external crystal oscillator (HFXO) */ #if !defined(NRF5_HFCLK_SOURCE) || defined(__DOXYGEN__) -#define NRF5_HFCLK_SOURCE NRF5_HFCLK_HFINT +#define NRF5_HFCLK_SOURCE CLOCK_HFCLKSTAT_SRC_RC #endif /** @@ -79,7 +79,7 @@ * internal RC oscillator that synthesizing the clock. */ #if !defined(NRF5_LFCLK_SOURCE) || defined(__DOXYGEN__) -#define NRF5_LFCLK_SOURCE NRF5_LFCLK_RC +#define NRF5_LFCLK_SOURCE CLOCK_LFCLKSTAT_SRC_RC #endif /*===========================================================================*/ @@ -105,14 +105,6 @@ /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ -#if 0 // moved to board.h -#define NRF5_HFCLK_HFINT 0 -#define NRF5_HFCLK_HFXO 1 - -#define NRF5_LFCLK_RC 0 -#define NRF5_LFCLK_XTAL 1 -#define NRF5_LFCLK_SYNTH 2 -#endif #include "nvic.h" #include "nrf52_isr.h" diff --git a/os/hal/ports/NRF5/NRF52832/nrf.h b/os/hal/ports/NRF5/NRF52832/nrf.h new file mode 100644 index 00000000..9c7c5f5f --- /dev/null +++ b/os/hal/ports/NRF5/NRF52832/nrf.h @@ -0,0 +1,61 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +/** @addtogroup Nordic Semiconductor + * @{ + */ + +/** @addtogroup nrf52 + * @{ + */ + +#ifndef NRF_H +#define NRF_H + +#include "nrf52.h" +#include "nrf52_bitfields.h" +#include "nrf51_to_nrf52.h" +#include "nrf52_name_change.h" + +#endif /* NRF_H */ + +/** @} */ /* End of group nrf52 */ +/** @} */ /* End of group Nordic Semiconductor */ diff --git a/os/hal/ports/NRF5/NRF52832/nrf51_to_nrf52.h b/os/hal/ports/NRF5/NRF52832/nrf51_to_nrf52.h new file mode 100644 index 00000000..5ef2b4ba --- /dev/null +++ b/os/hal/ports/NRF5/NRF52832/nrf51_to_nrf52.h @@ -0,0 +1,2372 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +/** @addtogroup Nordic Semiconductor + * @{ + */ + +/** @addtogroup nrf52 + * @{ + */ + +#ifndef NRF51_TO_NRF52_H +#define NRF51_TO_NRF52_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices. + * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros + * from the nrf51_deprecated.h file. */ + + +/* IRQ */ +/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ +#ifndef UART0_IRQHandler + #define UART0_IRQHandler UARTE0_UART0_IRQHandler +#endif +#ifndef SPI0_TWI0_IRQHandler + #define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#endif +#ifndef SPI1_TWI1_IRQHandler + #define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#endif +#ifndef ADC_IRQHandler + #define ADC_IRQHandler SAADC_IRQHandler +#endif +#ifndef LPCOMP_IRQHandler + #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler +#endif +#ifndef SWI0_IRQHandler + #define SWI0_IRQHandler SWI0_EGU0_IRQHandler +#endif +#ifndef SWI1_IRQHandler + #define SWI1_IRQHandler SWI1_EGU1_IRQHandler +#endif +#ifndef SWI2_IRQHandler + #define SWI2_IRQHandler SWI2_EGU2_IRQHandler +#endif +#ifndef SWI3_IRQHandler + #define SWI3_IRQHandler SWI3_EGU3_IRQHandler +#endif +#ifndef SWI4_IRQHandler + #define SWI4_IRQHandler SWI4_EGU4_IRQHandler +#endif +#ifndef SWI5_IRQHandler + #define SWI5_IRQHandler SWI5_EGU5_IRQHandler +#endif + +#ifndef UART0_IRQn + #define UART0_IRQn UARTE0_UART0_IRQn +#endif +#ifndef SPI0_TWI0_IRQn + #define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn +#endif +#ifndef SPI1_TWI1_IRQn + #define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn +#endif +#ifndef ADC_IRQn + #define ADC_IRQn SAADC_IRQn +#endif +#ifndef LPCOMP_IRQn + #define LPCOMP_IRQn COMP_LPCOMP_IRQn +#endif +#ifndef SWI0_IRQn + #define SWI0_IRQn SWI0_EGU0_IRQn +#endif +#ifndef SWI1_IRQn + #define SWI1_IRQn SWI1_EGU1_IRQn +#endif +#ifndef SWI2_IRQn + #define SWI2_IRQn SWI2_EGU2_IRQn +#endif +#ifndef SWI3_IRQn + #define SWI3_IRQn SWI3_EGU3_IRQn +#endif +#ifndef SWI4_IRQn + #define SWI4_IRQn SWI4_EGU4_IRQn +#endif +#ifndef SWI5_IRQn + #define SWI5_IRQn SWI5_EGU5_IRQn +#endif + + +/* UICR */ +/* Register RBPCONF was renamed to APPROTECT. */ +#ifndef RBPCONF + #define RBPCONF APPROTECT +#endif + +#ifndef UICR_RBPCONF_PALL_Pos + #define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos +#endif +#ifndef UICR_RBPCONF_PALL_Msk + #define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk +#endif +#ifndef UICR_RBPCONF_PALL_Enabled + #define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled +#endif +#ifndef UICR_RBPCONF_PALL_Disabled + #define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled +#endif + +/* GPIO */ +/* GPIO port was renamed to P0. */ +#ifndef NRF_GPIO + #define NRF_GPIO NRF_P0 +#endif +#ifndef NRF_GPIO_BASE + #define NRF_GPIO_BASE NRF_P0_BASE +#endif + +/* QDEC */ +/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ +#ifndef PSELLED + #define PSELLED PSEL.LED +#endif +#ifndef PSELA + #define PSELA PSEL.A +#endif +#ifndef PSELB + #define PSELB PSEL.B +#endif + + +/* SPIS */ +/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ +#ifndef PSELSCK + #define PSELSCK PSEL.SCK +#endif +#ifndef PSELMISO + #define PSELMISO PSEL.MISO +#endif +#ifndef PSELMOSI + #define PSELMOSI PSEL.MOSI +#endif +#ifndef PSELCSN + #define PSELCSN PSEL.CSN +#endif + +/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ +#ifndef RXDPTR + #define RXDPTR RXD.PTR +#endif +#ifndef MAXRX + #define MAXRX RXD.MAXCNT +#endif +#ifndef AMOUNTRX + #define AMOUNTRX RXD.AMOUNT +#endif + +#ifndef SPIS_MAXRX_MAXRX_Pos + #define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos +#endif +#ifndef SPIS_MAXRX_MAXRX_Msk + #define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk +#endif + +#ifndef SPIS_AMOUNTRX_AMOUNTRX_Pos + #define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos +#endif +#ifndef SPIS_AMOUNTRX_AMOUNTRX_Msk + #define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk +#endif + +/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ +#ifndef TXDPTR + #define TXDPTR TXD.PTR +#endif +#ifndef MAXTX + #define MAXTX TXD.MAXCNT +#endif +#ifndef AMOUNTTX + #define AMOUNTTX TXD.AMOUNT +#endif + +#ifndef SPIS_MAXTX_MAXTX_Pos + #define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos +#endif +#ifndef SPIS_MAXTX_MAXTX_Msk + #define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk +#endif + +#ifndef SPIS_AMOUNTTX_AMOUNTTX_Pos + #define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos +#endif +#ifndef SPIS_AMOUNTTX_AMOUNTTX_Msk + #define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk +#endif + +/* MPU */ +/* Part of MPU module was renamed BPROT, while the rest was eliminated. */ +#ifndef NRF_MPU + #define NRF_MPU NRF_BPROT +#endif + +/* Register DISABLEINDEBUG macros were affected. */ +#ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos + #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos +#endif +#ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk + #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk +#endif +#ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled + #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled +#endif +#ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled + #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled +#endif + +/* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */ +#ifndef PROTENSET0 + #define PROTENSET0 CONFIG0 +#endif +#ifndef PROTENSET1 + #define PROTENSET1 CONFIG1 +#endif + +#ifndef MPU_PROTENSET1_PROTREG63_Pos + #define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG63_Msk + #define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG63_Disabled + #define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG63_Enabled + #define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG63_Set + #define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG62_Pos + #define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG62_Msk + #define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG62_Disabled + #define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG62_Enabled + #define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG62_Set + #define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG61_Pos + #define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG61_Msk + #define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG61_Disabled + #define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG61_Enabled + #define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG61_Set + #define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG60_Pos + #define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG60_Msk + #define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG60_Disabled + #define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG60_Enabled + #define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG60_Set + #define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG59_Pos + #define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG59_Msk + #define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG59_Disabled + #define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG59_Enabled + #define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG59_Set + #define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG58_Pos + #define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG58_Msk + #define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG58_Disabled + #define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG58_Enabled + #define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG58_Set + #define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG57_Pos + #define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG57_Msk + #define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG57_Disabled + #define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG57_Enabled + #define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG57_Set + #define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG56_Pos + #define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG56_Msk + #define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG56_Disabled + #define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG56_Enabled + #define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG56_Set + #define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG55_Pos + #define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG55_Msk + #define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG55_Disabled + #define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG55_Enabled + #define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG55_Set + #define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG54_Pos + #define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG54_Msk + #define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG54_Disabled + #define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG54_Enabled + #define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG54_Set + #define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG53_Pos + #define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG53_Msk + #define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG53_Disabled + #define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG53_Enabled + #define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG53_Set + #define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG52_Pos + #define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG52_Msk + #define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG52_Disabled + #define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG52_Enabled + #define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG52_Set + #define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG51_Pos + #define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG51_Msk + #define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG51_Disabled + #define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG51_Enabled + #define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG51_Set + #define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG50_Pos + #define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG50_Msk + #define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG50_Disabled + #define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG50_Enabled + #define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG50_Set + #define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG49_Pos + #define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG49_Msk + #define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG49_Disabled + #define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG49_Enabled + #define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG49_Set + #define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG48_Pos + #define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG48_Msk + #define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG48_Disabled + #define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG48_Enabled + #define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG48_Set + #define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG47_Pos + #define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG47_Msk + #define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG47_Disabled + #define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG47_Enabled + #define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG47_Set + #define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG46_Pos + #define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG46_Msk + #define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG46_Disabled + #define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG46_Enabled + #define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG46_Set + #define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG45_Pos + #define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG45_Msk + #define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG45_Disabled + #define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG45_Enabled + #define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG45_Set + #define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG44_Pos + #define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG44_Msk + #define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG44_Disabled + #define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG44_Enabled + #define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG44_Set + #define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG43_Pos + #define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG43_Msk + #define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG43_Disabled + #define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG43_Enabled + #define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG43_Set + #define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG42_Pos + #define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG42_Msk + #define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG42_Disabled + #define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG42_Enabled + #define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG42_Set + #define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG41_Pos + #define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG41_Msk + #define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG41_Disabled + #define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG41_Enabled + #define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG41_Set + #define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG40_Pos + #define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG40_Msk + #define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG40_Disabled + #define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG40_Enabled + #define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG40_Set + #define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG39_Pos + #define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG39_Msk + #define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG39_Disabled + #define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG39_Enabled + #define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG39_Set + #define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG38_Pos + #define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG38_Msk + #define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG38_Disabled + #define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG38_Enabled + #define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG38_Set + #define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG37_Pos + #define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG37_Msk + #define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG37_Disabled + #define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG37_Enabled + #define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG37_Set + #define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG36_Pos + #define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG36_Msk + #define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG36_Disabled + #define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG36_Enabled + #define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG36_Set + #define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG35_Pos + #define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG35_Msk + #define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG35_Disabled + #define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG35_Enabled + #define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG35_Set + #define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG34_Pos + #define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG34_Msk + #define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG34_Disabled + #define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG34_Enabled + #define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG34_Set + #define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG33_Pos + #define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG33_Msk + #define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG33_Disabled + #define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG33_Enabled + #define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG33_Set + #define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG32_Pos + #define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG32_Msk + #define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG32_Disabled + #define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG32_Enabled + #define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG32_Set + #define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG31_Pos + #define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG31_Msk + #define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG31_Disabled + #define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG31_Enabled + #define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG31_Set + #define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG30_Pos + #define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG30_Msk + #define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG30_Disabled + #define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG30_Enabled + #define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG30_Set + #define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG29_Pos + #define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG29_Msk + #define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG29_Disabled + #define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG29_Enabled + #define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG29_Set + #define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG28_Pos + #define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG28_Msk + #define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG28_Disabled + #define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG28_Enabled + #define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG28_Set + #define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG27_Pos + #define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG27_Msk + #define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG27_Disabled + #define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG27_Enabled + #define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG27_Set + #define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG26_Pos + #define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG26_Msk + #define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG26_Disabled + #define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG26_Enabled + #define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG26_Set + #define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG25_Pos + #define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG25_Msk + #define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG25_Disabled + #define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG25_Enabled + #define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG25_Set + #define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG24_Pos + #define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG24_Msk + #define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG24_Disabled + #define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG24_Enabled + #define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG24_Set + #define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG23_Pos + #define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG23_Msk + #define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG23_Disabled + #define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG23_Enabled + #define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG23_Set + #define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG22_Pos + #define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG22_Msk + #define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG22_Disabled + #define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG22_Enabled + #define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG22_Set + #define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG21_Pos + #define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG21_Msk + #define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG21_Disabled + #define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG21_Enabled + #define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG21_Set + #define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG20_Pos + #define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG20_Msk + #define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG20_Disabled + #define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG20_Enabled + #define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG20_Set + #define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG19_Pos + #define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG19_Msk + #define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG19_Disabled + #define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG19_Enabled + #define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG19_Set + #define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG18_Pos + #define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG18_Msk + #define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG18_Disabled + #define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG18_Enabled + #define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG18_Set + #define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG17_Pos + #define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG17_Msk + #define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG17_Disabled + #define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG17_Enabled + #define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG17_Set + #define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG16_Pos + #define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG16_Msk + #define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG16_Disabled + #define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG16_Enabled + #define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG16_Set + #define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG16_Set + #define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG15_Msk + #define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG15_Disabled + #define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG15_Enabled + #define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG15_Set + #define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG14_Pos + #define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG14_Msk + #define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG14_Disabled + #define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG14_Enabled + #define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG14_Set + #define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG13_Pos + #define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG13_Msk + #define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG13_Disabled + #define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG13_Enabled + #define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG13_Set + #define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG12_Pos + #define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG12_Msk + #define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG12_Disabled + #define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG12_Enabled + #define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG12_Set + #define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG11_Pos + #define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG11_Msk + #define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG11_Disabled + #define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG11_Enabled + #define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG11_Set + #define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG10_Pos + #define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG10_Msk + #define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG10_Disabled + #define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG10_Enabled + #define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG10_Set + #define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG9_Pos + #define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG9_Msk + #define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG9_Disabled + #define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG9_Enabled + #define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG9_Set + #define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG8_Pos + #define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG8_Msk + #define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG8_Disabled + #define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG8_Enabled + #define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG8_Set + #define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG7_Pos + #define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG7_Msk + #define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG7_Disabled + #define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG7_Enabled + #define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG7_Set + #define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG6_Pos + #define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG6_Msk + #define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG6_Disabled + #define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG6_Enabled + #define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG6_Set + #define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG5_Pos + #define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG5_Msk + #define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG5_Disabled + #define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG5_Enabled + #define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG5_Set + #define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG4_Pos + #define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG4_Msk + #define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG4_Disabled + #define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG4_Enabled + #define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG4_Set + #define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG3_Pos + #define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG3_Msk + #define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG3_Disabled + #define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG3_Enabled + #define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG3_Set + #define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG2_Pos + #define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG2_Msk + #define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG2_Disabled + #define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG2_Enabled + #define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG2_Set + #define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG1_Pos + #define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG1_Msk + #define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG1_Disabled + #define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG1_Enabled + #define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG1_Set + #define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG0_Pos + #define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG0_Msk + #define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG0_Disabled + #define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG0_Enabled + #define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG0_Set + #define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled +#endif + + +/* From nrf51_deprecated.h */ + +/* NVMC */ +/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ +#ifndef ERASEPROTECTEDPAGE + #define ERASEPROTECTEDPAGE ERASEPCR0 +#endif + + +/* IRQ */ +/* COMP module was eliminated. Adapted to nrf52 headers. */ +#ifndef LPCOMP_COMP_IRQHandler + #define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler +#endif +#ifndef LPCOMP_COMP_IRQn + #define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn +#endif + + +/* REFSEL register redefined enumerated values and added some more. */ +#ifndef LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd +#endif + +/* RADIO */ +/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ +#ifndef RADIO_CRCCNF_SKIP_ADDR_Pos + #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Msk + #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Include + #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Skip + #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip +#endif + + +/* FICR */ +/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ +#ifndef DEVICEID0 + #define DEVICEID0 DEVICEID[0] +#endif +#ifndef DEVICEID1 + #define DEVICEID1 DEVICEID[1] +#endif + +/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ +#ifndef ER0 + #define ER0 ER[0] +#endif +#ifndef ER1 + #define ER1 ER[1] +#endif +#ifndef ER2 + #define ER2 ER[2] +#endif +#ifndef ER3 + #define ER3 ER[3] +#endif + +/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ +#ifndef IR0 + #define IR0 IR[0] +#endif +#ifndef IR1 + #define IR1 IR[1] +#endif +#ifndef IR2 + #define IR2 IR[2] +#endif +#ifndef IR3 + #define IR3 IR[3] +#endif + +/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ +#ifndef DEVICEADDR0 + #define DEVICEADDR0 DEVICEADDR[0] +#endif +#ifndef DEVICEADDR1 + #define DEVICEADDR1 DEVICEADDR[1] +#endif + + +/* PPI */ +/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ +#ifndef TASKS_CHG0EN + #define TASKS_CHG0EN TASKS_CHG[0].EN +#endif +#ifndef TASKS_CHG0DIS + #define TASKS_CHG0DIS TASKS_CHG[0].DIS +#endif +#ifndef TASKS_CHG1EN + #define TASKS_CHG1EN TASKS_CHG[1].EN +#endif +#ifndef TASKS_CHG1DIS + #define TASKS_CHG1DIS TASKS_CHG[1].DIS +#endif +#ifndef TASKS_CHG2EN + #define TASKS_CHG2EN TASKS_CHG[2].EN +#endif +#ifndef TASKS_CHG2DIS + #define TASKS_CHG2DIS TASKS_CHG[2].DIS +#endif +#ifndef TASKS_CHG3EN + #define TASKS_CHG3EN TASKS_CHG[3].EN +#endif +#ifndef TASKS_CHG3DIS + #define TASKS_CHG3DIS TASKS_CHG[3].DIS +#endif + +/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ +#ifndef CH0_EEP + #define CH0_EEP CH[0].EEP +#endif +#ifndef CH0_TEP + #define CH0_TEP CH[0].TEP +#endif +#ifndef CH1_EEP + #define CH1_EEP CH[1].EEP +#endif +#ifndef CH1_TEP + #define CH1_TEP CH[1].TEP +#endif +#ifndef CH2_EEP + #define CH2_EEP CH[2].EEP +#endif +#ifndef CH2_TEP + #define CH2_TEP CH[2].TEP +#endif +#ifndef CH3_EEP + #define CH3_EEP CH[3].EEP +#endif +#ifndef CH3_TEP + #define CH3_TEP CH[3].TEP +#endif +#ifndef CH4_EEP + #define CH4_EEP CH[4].EEP +#endif +#ifndef CH4_TEP + #define CH4_TEP CH[4].TEP +#endif +#ifndef CH5_EEP + #define CH5_EEP CH[5].EEP +#endif +#ifndef CH5_TEP + #define CH5_TEP CH[5].TEP +#endif +#ifndef CH6_EEP + #define CH6_EEP CH[6].EEP +#endif +#ifndef CH6_TEP + #define CH6_TEP CH[6].TEP +#endif +#ifndef CH7_EEP + #define CH7_EEP CH[7].EEP +#endif +#ifndef CH7_TEP + #define CH7_TEP CH[7].TEP +#endif +#ifndef CH8_EEP + #define CH8_EEP CH[8].EEP +#endif +#ifndef CH8_TEP + #define CH8_TEP CH[8].TEP +#endif +#ifndef CH9_EEP + #define CH9_EEP CH[9].EEP +#endif +#ifndef CH9_TEP + #define CH9_TEP CH[9].TEP +#endif +#ifndef CH10_EEP + #define CH10_EEP CH[10].EEP +#endif +#ifndef CH10_TEP + #define CH10_TEP CH[10].TEP +#endif +#ifndef CH11_EEP + #define CH11_EEP CH[11].EEP +#endif +#ifndef CH11_TEP + #define CH11_TEP CH[11].TEP +#endif +#ifndef CH12_EEP + #define CH12_EEP CH[12].EEP +#endif +#ifndef CH12_TEP + #define CH12_TEP CH[12].TEP +#endif +#ifndef CH13_EEP + #define CH13_EEP CH[13].EEP +#endif +#ifndef CH13_TEP + #define CH13_TEP CH[13].TEP +#endif +#ifndef CH14_EEP + #define CH14_EEP CH[14].EEP +#endif +#ifndef CH14_TEP + #define CH14_TEP CH[14].TEP +#endif +#ifndef CH15_EEP + #define CH15_EEP CH[15].EEP +#endif +#ifndef CH15_TEP + #define CH15_TEP CH[15].TEP +#endif + +/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ +#ifndef CHG0 + #define CHG0 CHG[0] +#endif +#ifndef CHG1 + #define CHG1 CHG[1] +#endif +#ifndef CHG2 + #define CHG2 CHG[2] +#endif +#ifndef CHG3 + #define CHG3 CHG[3] +#endif + +/* All bitfield macros for the CHGx registers therefore changed name. */ +#ifndef PPI_CHG0_CH15_Pos + #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG0_CH15_Msk + #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG0_CH15_Excluded + #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG0_CH15_Included + #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG0_CH14_Pos + #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG0_CH14_Msk + #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG0_CH14_Excluded + #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG0_CH14_Included + #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG0_CH13_Pos + #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG0_CH13_Msk + #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG0_CH13_Excluded + #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG0_CH13_Included + #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG0_CH12_Pos + #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG0_CH12_Msk + #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG0_CH12_Excluded + #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG0_CH12_Included + #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG0_CH11_Pos + #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG0_CH11_Msk + #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG0_CH11_Excluded + #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG0_CH11_Included + #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG0_CH10_Pos + #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG0_CH10_Msk + #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG0_CH10_Excluded + #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG0_CH10_Included + #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG0_CH9_Pos + #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG0_CH9_Msk + #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG0_CH9_Excluded + #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG0_CH9_Included + #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG0_CH8_Pos + #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG0_CH8_Msk + #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG0_CH8_Excluded + #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG0_CH8_Included + #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG0_CH7_Pos + #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG0_CH7_Msk + #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG0_CH7_Excluded + #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG0_CH7_Included + #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG0_CH6_Pos + #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG0_CH6_Msk + #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG0_CH6_Excluded + #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG0_CH6_Included + #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG0_CH5_Pos + #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG0_CH5_Msk + #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG0_CH5_Excluded + #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG0_CH5_Included + #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG0_CH4_Pos + #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG0_CH4_Msk + #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG0_CH4_Excluded + #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG0_CH4_Included + #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG0_CH3_Pos + #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG0_CH3_Msk + #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG0_CH3_Excluded + #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG0_CH3_Included + #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG0_CH2_Pos + #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG0_CH2_Msk + #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG0_CH2_Excluded + #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG0_CH2_Included + #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG0_CH1_Pos + #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG0_CH1_Msk + #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG0_CH1_Excluded + #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG0_CH1_Included + #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG0_CH0_Pos + #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG0_CH0_Msk + #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG0_CH0_Excluded + #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG0_CH0_Included + #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG1_CH15_Pos + #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG1_CH15_Msk + #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG1_CH15_Excluded + #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG1_CH15_Included + #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG1_CH14_Pos + #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG1_CH14_Msk + #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG1_CH14_Excluded + #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG1_CH14_Included + #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG1_CH13_Pos + #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG1_CH13_Msk + #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG1_CH13_Excluded + #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG1_CH13_Included + #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG1_CH12_Pos + #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG1_CH12_Msk + #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG1_CH12_Excluded + #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG1_CH12_Included + #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG1_CH11_Pos + #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG1_CH11_Msk + #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG1_CH11_Excluded + #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG1_CH11_Included + #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG1_CH10_Pos + #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG1_CH10_Msk + #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG1_CH10_Excluded + #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG1_CH10_Included + #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG1_CH9_Pos + #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG1_CH9_Msk + #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG1_CH9_Excluded + #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG1_CH9_Included + #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG1_CH8_Pos + #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG1_CH8_Msk + #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG1_CH8_Excluded + #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG1_CH8_Included + #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG1_CH7_Pos + #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG1_CH7_Msk + #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG1_CH7_Excluded + #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG1_CH7_Included + #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG1_CH6_Pos + #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG1_CH6_Msk + #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG1_CH6_Excluded + #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG1_CH6_Included + #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG1_CH5_Pos + #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG1_CH5_Msk + #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG1_CH5_Excluded + #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG1_CH5_Included + #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG1_CH4_Pos + #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG1_CH4_Msk + #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG1_CH4_Excluded + #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG1_CH4_Included + #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG1_CH3_Pos + #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG1_CH3_Msk + #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG1_CH3_Excluded + #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG1_CH3_Included + #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG1_CH2_Pos + #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG1_CH2_Msk + #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG1_CH2_Excluded + #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG1_CH2_Included + #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG1_CH1_Pos + #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG1_CH1_Msk + #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG1_CH1_Excluded + #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG1_CH1_Included + #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG1_CH0_Pos + #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG1_CH0_Msk + #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG1_CH0_Excluded + #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG1_CH0_Included + #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG2_CH15_Pos + #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG2_CH15_Msk + #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG2_CH15_Excluded + #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG2_CH15_Included + #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG2_CH14_Pos + #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG2_CH14_Msk + #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG2_CH14_Excluded + #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG2_CH14_Included + #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG2_CH13_Pos + #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG2_CH13_Msk + #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG2_CH13_Excluded + #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG2_CH13_Included + #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG2_CH12_Pos + #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG2_CH12_Msk + #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG2_CH12_Excluded + #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG2_CH12_Included + #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG2_CH11_Pos + #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG2_CH11_Msk + #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG2_CH11_Excluded + #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG2_CH11_Included + #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG2_CH10_Pos + #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG2_CH10_Msk + #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG2_CH10_Excluded + #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG2_CH10_Included + #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG2_CH9_Pos + #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG2_CH9_Msk + #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG2_CH9_Excluded + #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG2_CH9_Included + #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG2_CH8_Pos + #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG2_CH8_Msk + #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG2_CH8_Excluded + #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG2_CH8_Included + #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG2_CH7_Pos + #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG2_CH7_Msk + #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG2_CH7_Excluded + #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG2_CH7_Included + #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG2_CH6_Pos + #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG2_CH6_Msk + #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG2_CH6_Excluded + #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG2_CH6_Included + #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG2_CH5_Pos + #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG2_CH5_Msk + #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG2_CH5_Excluded + #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG2_CH5_Included + #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG2_CH4_Pos + #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG2_CH4_Msk + #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG2_CH4_Excluded + #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG2_CH4_Included + #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG2_CH3_Pos + #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG2_CH3_Msk + #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG2_CH3_Excluded + #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG2_CH3_Included + #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG2_CH2_Pos + #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG2_CH2_Msk + #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG2_CH2_Excluded + #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG2_CH2_Included + #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG2_CH1_Pos + #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG2_CH1_Msk + #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG2_CH1_Excluded + #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG2_CH1_Included + #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG2_CH0_Pos + #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG2_CH0_Msk + #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG2_CH0_Excluded + #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG2_CH0_Included + #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG3_CH15_Pos + #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG3_CH15_Msk + #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG3_CH15_Excluded + #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG3_CH15_Included + #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG3_CH14_Pos + #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG3_CH14_Msk + #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG3_CH14_Excluded + #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG3_CH14_Included + #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG3_CH13_Pos + #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG3_CH13_Msk + #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG3_CH13_Excluded + #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG3_CH13_Included + #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG3_CH12_Pos + #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG3_CH12_Msk + #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG3_CH12_Excluded + #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG3_CH12_Included + #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG3_CH11_Pos + #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG3_CH11_Msk + #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG3_CH11_Excluded + #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG3_CH11_Included + #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG3_CH10_Pos + #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG3_CH10_Msk + #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG3_CH10_Excluded + #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG3_CH10_Included + #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG3_CH9_Pos + #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG3_CH9_Msk + #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG3_CH9_Excluded + #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG3_CH9_Included + #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG3_CH8_Pos + #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG3_CH8_Msk + #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG3_CH8_Excluded + #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG3_CH8_Included + #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG3_CH7_Pos + #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG3_CH7_Msk + #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG3_CH7_Excluded + #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG3_CH7_Included + #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG3_CH6_Pos + #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG3_CH6_Msk + #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG3_CH6_Excluded + #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG3_CH6_Included + #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG3_CH5_Pos + #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG3_CH5_Msk + #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG3_CH5_Excluded + #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG3_CH5_Included + #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG3_CH4_Pos + #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG3_CH4_Msk + #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG3_CH4_Excluded + #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG3_CH4_Included + #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG3_CH3_Pos + #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG3_CH3_Msk + #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG3_CH3_Excluded + #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG3_CH3_Included + #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG3_CH2_Pos + #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG3_CH2_Msk + #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG3_CH2_Excluded + #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG3_CH2_Included + #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG3_CH1_Pos + #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG3_CH1_Msk + #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG3_CH1_Excluded + #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG3_CH1_Included + #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG3_CH0_Pos + #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG3_CH0_Msk + #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG3_CH0_Excluded + #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG3_CH0_Included + #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included +#endif + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_TO_NRF52_H */ + +/** @} */ /* End of group nrf52 */ +/** @} */ /* End of group Nordic Semiconductor */ diff --git a/os/hal/ports/NRF5/NRF52832/nrf52.h b/os/hal/ports/NRF5/NRF52832/nrf52.h index 1902d337..68ccf760 100644 --- a/os/hal/ports/NRF5/NRF52832/nrf52.h +++ b/os/hal/ports/NRF5/NRF52832/nrf52.h @@ -1,53 +1,54 @@ - -/****************************************************************************************************//** +/* + * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * * @file nrf52.h - * - * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for - * nrf52 from Nordic Semiconductor. - * - * @version V1 - * @date 23. February 2016 - * - * @note Generated with SVDConv V2.81d - * from CMSIS SVD File 'nrf52.svd' Version 1, - * - * @par Copyright (c) 2015, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - *******************************************************************************************************/ - + * @brief CMSIS HeaderFile + * @version 1 + * @date 08. February 2019 + * @note Generated by SVDConv V3.3.18 on Friday, 08.02.2019 16:48:11 + * from File 'nrf52.svd', + * last modified on Friday, 08.02.2019 15:48:07 + */ /** @addtogroup Nordic Semiconductor * @{ */ - /** @addtogroup nrf52 * @{ */ @@ -55,2072 +56,2346 @@ #ifndef NRF52_H #define NRF52_H -#include "nrf52_bitfields.h" - #ifdef __cplusplus extern "C" { #endif -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum { -/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation - and No Match */ - BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory - related Fault */ - UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -/* ---------------------- nrf52 Specific Interrupt Numbers ---------------------- */ - POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ - RADIO_IRQn = 1, /*!< 1 RADIO */ - UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ - NFCT_IRQn = 5, /*!< 5 NFCT */ - GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ - SAADC_IRQn = 7, /*!< 7 SAADC */ - TIMER0_IRQn = 8, /*!< 8 TIMER0 */ - TIMER1_IRQn = 9, /*!< 9 TIMER1 */ - TIMER2_IRQn = 10, /*!< 10 TIMER2 */ - RTC0_IRQn = 11, /*!< 11 RTC0 */ - TEMP_IRQn = 12, /*!< 12 TEMP */ - RNG_IRQn = 13, /*!< 13 RNG */ - ECB_IRQn = 14, /*!< 14 ECB */ - CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ - WDT_IRQn = 16, /*!< 16 WDT */ - RTC1_IRQn = 17, /*!< 17 RTC1 */ - QDEC_IRQn = 18, /*!< 18 QDEC */ - COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ - SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ - SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ - SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ - SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ - SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ - SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ - TIMER3_IRQn = 26, /*!< 26 TIMER3 */ - TIMER4_IRQn = 27, /*!< 27 TIMER4 */ - PWM0_IRQn = 28, /*!< 28 PWM0 */ - PDM_IRQn = 29, /*!< 29 PDM */ - MWU_IRQn = 32, /*!< 32 MWU */ - PWM1_IRQn = 33, /*!< 33 PWM1 */ - PWM2_IRQn = 34, /*!< 34 PWM2 */ - SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ - RTC2_IRQn = 36, /*!< 36 RTC2 */ - I2S_IRQn = 37, /*!< 37 I2S */ - FPU_IRQn = 38 /*!< 38 FPU */ -} IRQn_Type; - - /** @addtogroup Configuration_of_CMSIS * @{ */ -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ -/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ -#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* =========================================== nrf52 Specific Interrupt Numbers ============================================ */ + POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ + RADIO_IRQn = 1, /*!< 1 RADIO */ + UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ + NFCT_IRQn = 5, /*!< 5 NFCT */ + GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ + SAADC_IRQn = 7, /*!< 7 SAADC */ + TIMER0_IRQn = 8, /*!< 8 TIMER0 */ + TIMER1_IRQn = 9, /*!< 9 TIMER1 */ + TIMER2_IRQn = 10, /*!< 10 TIMER2 */ + RTC0_IRQn = 11, /*!< 11 RTC0 */ + TEMP_IRQn = 12, /*!< 12 TEMP */ + RNG_IRQn = 13, /*!< 13 RNG */ + ECB_IRQn = 14, /*!< 14 ECB */ + CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ + WDT_IRQn = 16, /*!< 16 WDT */ + RTC1_IRQn = 17, /*!< 17 RTC1 */ + QDEC_IRQn = 18, /*!< 18 QDEC */ + COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ + SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ + SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ + SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ + SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ + SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ + SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ + TIMER3_IRQn = 26, /*!< 26 TIMER3 */ + TIMER4_IRQn = 27, /*!< 27 TIMER4 */ + PWM0_IRQn = 28, /*!< 28 PWM0 */ + PDM_IRQn = 29, /*!< 29 PDM */ + MWU_IRQn = 32, /*!< 32 MWU */ + PWM1_IRQn = 33, /*!< 33 PWM1 */ + PWM2_IRQn = 34, /*!< 34 PWM2 */ + SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ + RTC2_IRQn = 36, /*!< 36 RTC2 */ + I2S_IRQn = 37, /*!< 37 I2S */ + FPU_IRQn = 38 /*!< 38 FPU */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __DSP_PRESENT 0 /*!< DSP present or not */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ + + /** @} */ /* End of group Configuration_of_CMSIS */ -#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ - - -/** @addtogroup Device_Peripheral_Registers +/** @addtogroup Device_Peripheral_clusters * @{ */ -/* ------------------- Start of section using anonymous unions ------------------ */ -#if defined(__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined(__ICCARM__) - #pragma language=extended -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) -/* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning 586 -#else - #warning Not supported compiler type -#endif - - +/** + * @brief FICR_INFO [INFO] (Device info) + */ typedef struct { - __I uint32_t PART; /*!< Part code */ - __I uint32_t VARIANT; /*!< Part Variant, Hardware version and Production configuration */ - __I uint32_t PACKAGE; /*!< Package option */ - __I uint32_t RAM; /*!< RAM variant */ - __I uint32_t FLASH; /*!< Flash variant */ - __IO uint32_t UNUSED0[3]; /*!< Description collection[0]: Unspecified */ -} FICR_INFO_Type; + __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ + __IM uint32_t VARIANT; /*!< (@ 0x00000004) Part Variant, Hardware version and Production + configuration */ + __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ + __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ + __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ + __IOM uint32_t UNUSED0[3]; /*!< (@ 0x00000014) Description collection[0]: Unspecified */ +} FICR_INFO_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) + */ typedef struct { - __I uint32_t A0; /*!< Slope definition A0. */ - __I uint32_t A1; /*!< Slope definition A1. */ - __I uint32_t A2; /*!< Slope definition A2. */ - __I uint32_t A3; /*!< Slope definition A3. */ - __I uint32_t A4; /*!< Slope definition A4. */ - __I uint32_t A5; /*!< Slope definition A5. */ - __I uint32_t B0; /*!< y-intercept B0. */ - __I uint32_t B1; /*!< y-intercept B1. */ - __I uint32_t B2; /*!< y-intercept B2. */ - __I uint32_t B3; /*!< y-intercept B3. */ - __I uint32_t B4; /*!< y-intercept B4. */ - __I uint32_t B5; /*!< y-intercept B5. */ - __I uint32_t T0; /*!< Segment end T0. */ - __I uint32_t T1; /*!< Segment end T1. */ - __I uint32_t T2; /*!< Segment end T2. */ - __I uint32_t T3; /*!< Segment end T3. */ - __I uint32_t T4; /*!< Segment end T4. */ -} FICR_TEMP_Type; + __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0. */ + __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1. */ + __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2. */ + __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3. */ + __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4. */ + __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5. */ + __IM uint32_t B0; /*!< (@ 0x00000018) y-intercept B0. */ + __IM uint32_t B1; /*!< (@ 0x0000001C) y-intercept B1. */ + __IM uint32_t B2; /*!< (@ 0x00000020) y-intercept B2. */ + __IM uint32_t B3; /*!< (@ 0x00000024) y-intercept B3. */ + __IM uint32_t B4; /*!< (@ 0x00000028) y-intercept B4. */ + __IM uint32_t B5; /*!< (@ 0x0000002C) y-intercept B5. */ + __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0. */ + __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1. */ + __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2. */ + __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3. */ + __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4. */ +} FICR_TEMP_Type; /*!< Size = 68 (0x44) */ + +/** + * @brief FICR_NFC [NFC] (Unspecified) + */ typedef struct { - __I uint32_t TAGHEADER0; /*!< Default header for NFC Tag. Software can read these values to - populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ - __I uint32_t TAGHEADER1; /*!< Default header for NFC Tag. Software can read these values to - populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ - __I uint32_t TAGHEADER2; /*!< Default header for NFC Tag. Software can read these values to - populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ - __I uint32_t TAGHEADER3; /*!< Default header for NFC Tag. Software can read these values to - populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ -} FICR_NFC_Type; + __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC Tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ + __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC Tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ + __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC Tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ + __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC Tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ +} FICR_NFC_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief POWER_RAM [RAM] (Unspecified) + */ typedef struct { - __IO uint32_t POWER; /*!< Description cluster[0]: RAM0 power control register */ - __O uint32_t POWERSET; /*!< Description cluster[0]: RAM0 power control set register */ - __O uint32_t POWERCLR; /*!< Description cluster[0]: RAM0 power control clear register */ - __I uint32_t RESERVED0; -} POWER_RAM_Type; + __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[0]: RAM0 power control register */ + __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[0]: RAM0 power control set + register */ + __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[0]: RAM0 power control clear + register */ + __IM uint32_t RESERVED; +} POWER_RAM_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief UARTE_PSEL [PSEL] (Unspecified) + */ typedef struct { - __IO uint32_t CPU0; /*!< AHB bus master priority register for CPU0 */ - __IO uint32_t SPIS1; /*!< AHB bus master priority register for SPIM1, SPIS1, TWIM1 and - TWIS1 */ - __IO uint32_t RADIO; /*!< AHB bus master priority register for RADIO */ - __IO uint32_t ECB; /*!< AHB bus master priority register for ECB */ - __IO uint32_t CCM; /*!< AHB bus master priority register for CCM */ - __IO uint32_t AAR; /*!< AHB bus master priority register for AAR */ - __IO uint32_t SAADC; /*!< AHB bus master priority register for SAADC */ - __IO uint32_t UARTE; /*!< AHB bus master priority register for UARTE */ - __IO uint32_t SERIAL0; /*!< AHB bus master priority register for SPIM0, SPIS0, TWIM0 and - TWIS0 */ - __IO uint32_t SERIAL2; /*!< AHB bus master priority register for SPIM2 and SPIS2 */ - __IO uint32_t NFCT; /*!< AHB bus master priority register for NFCT */ - __IO uint32_t I2S; /*!< AHB bus master priority register for I2S */ - __IO uint32_t PDM; /*!< AHB bus master priority register for PDM */ - __IO uint32_t PWM; /*!< AHB bus master priority register for PWM0, PWM1 and PWM2 */ -} AMLI_RAMPRI_Type; + __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ + __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ + __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ + __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ +} UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) + */ typedef struct { - __IO uint32_t RTS; /*!< Pin select for RTS signal */ - __IO uint32_t TXD; /*!< Pin select for TXD signal */ - __IO uint32_t CTS; /*!< Pin select for CTS signal */ - __IO uint32_t RXD; /*!< Pin select for RXD signal */ -} UARTE_PSEL_Type; + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_RXD_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) + */ typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ -} UARTE_RXD_Type; + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_TXD_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief SPIM_PSEL [PSEL] (Unspecified) + */ typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ -} UARTE_TXD_Type; + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ +} SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) + */ typedef struct { - __IO uint32_t SCK; /*!< Pin select for SCK */ - __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ - __IO uint32_t MISO; /*!< Pin select for MISO signal */ -} SPIM_PSEL_Type; + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_RXD_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) + */ typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ - __IO uint32_t LIST; /*!< EasyDMA list type */ -} SPIM_RXD_Type; + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_TXD_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief SPIS_PSEL [PSEL] (Unspecified) + */ typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ - __IO uint32_t LIST; /*!< EasyDMA list type */ -} SPIM_TXD_Type; + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ + __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ + __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ +} SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief SPIS_RXD [RXD] (Unspecified) + */ typedef struct { - __IO uint32_t SCK; /*!< Pin select for SCK */ - __IO uint32_t MISO; /*!< Pin select for MISO signal */ - __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ - __IO uint32_t CSN; /*!< Pin select for CSN signal */ -} SPIS_PSEL_Type; + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ +} SPIS_RXD_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief SPIS_TXD [TXD] (Unspecified) + */ typedef struct { - __IO uint32_t PTR; /*!< RXD data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes received in last granted transaction */ -} SPIS_RXD_Type; + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ +} SPIS_TXD_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief TWIM_PSEL [PSEL] (Unspecified) + */ typedef struct { - __IO uint32_t PTR; /*!< TXD data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transmitted in last granted transaction */ -} SPIS_TXD_Type; + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) + */ typedef struct { - __IO uint32_t SCL; /*!< Pin select for SCL signal */ - __IO uint32_t SDA; /*!< Pin select for SDA signal */ -} TWIM_PSEL_Type; + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_RXD_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) + */ typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ - __IO uint32_t LIST; /*!< EasyDMA list type */ -} TWIM_RXD_Type; + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_TXD_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief TWIS_PSEL [PSEL] (Unspecified) + */ typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ - __IO uint32_t LIST; /*!< EasyDMA list type */ -} TWIM_TXD_Type; + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) + */ typedef struct { - __IO uint32_t SCL; /*!< Pin select for SCL signal */ - __IO uint32_t SDA; /*!< Pin select for SDA signal */ -} TWIS_PSEL_Type; + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ +} TWIS_RXD_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) + */ typedef struct { - __IO uint32_t PTR; /*!< RXD Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in RXD buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last RXD transaction */ -} TWIS_RXD_Type; + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ +} TWIS_TXD_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief SPI_PSEL [PSEL] (Unspecified) + */ typedef struct { - __IO uint32_t PTR; /*!< TXD Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of bytes in TXD buffer */ - __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last TXD transaction */ -} TWIS_TXD_Type; + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO */ +} SPI_PSEL_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) + */ typedef struct { - __IO uint32_t SCK; /*!< Pin select for SCK */ - __IO uint32_t MOSI; /*!< Pin select for MOSI */ - __IO uint32_t MISO; /*!< Pin select for MISO */ -} SPI_PSEL_Type; + __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frames */ +} NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief NFCT_TXD [TXD] (Unspecified) + */ typedef struct { - __IO uint32_t RX; /*!< Result of last incoming frames */ -} NFCT_FRAMESTATUS_Type; + __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ + __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ +} NFCT_TXD_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief NFCT_RXD [RXD] (Unspecified) + */ typedef struct { - __IO uint32_t FRAMECONFIG; /*!< Configuration of outgoing frames */ - __IO uint32_t AMOUNT; /*!< Size of outgoing frame */ -} NFCT_TXD_Type; + __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ +} NFCT_RXD_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified) + */ typedef struct { - __IO uint32_t FRAMECONFIG; /*!< Configuration of incoming frames */ - __I uint32_t AMOUNT; /*!< Size of last incoming frame */ -} NFCT_RXD_Type; + __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[0]: Last results is equal + or above CH[0].LIMIT.HIGH */ + __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[0]: Last results is equal + or below CH[0].LIMIT.LOW */ +} SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief SAADC_CH [CH] (Unspecified) + */ typedef struct { - __IO uint32_t LIMITH; /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */ - __IO uint32_t LIMITL; /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */ -} SAADC_EVENTS_CH_Type; + __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[0]: Input positive pin selection + for CH[0] */ + __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[0]: Input negative pin selection + for CH[0] */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[0]: Input configuration for + CH[0] */ + __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[0]: High/low limits for event + monitoring a channel */ +} SAADC_CH_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) + */ typedef struct { - __IO uint32_t PSELP; /*!< Description cluster[0]: Input positive pin selection for CH[0] */ - __IO uint32_t PSELN; /*!< Description cluster[0]: Input negative pin selection for CH[0] */ - __IO uint32_t CONFIG; /*!< Description cluster[0]: Input configuration for CH[0] */ - __IO uint32_t LIMIT; /*!< Description cluster[0]: High/low limits for event monitoring - a channel */ -} SAADC_CH_Type; + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last + START */ +} SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief QDEC_PSEL [PSEL] (Unspecified) + */ typedef struct { - __IO uint32_t PTR; /*!< Data pointer */ - __IO uint32_t MAXCNT; /*!< Maximum number of buffer words to transfer */ - __I uint32_t AMOUNT; /*!< Number of buffer words transferred since last START */ -} SAADC_RESULT_Type; + __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ + __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ + __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ +} QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief PWM_SEQ [SEQ] (Unspecified) + */ typedef struct { - __IO uint32_t LED; /*!< Pin select for LED signal */ - __IO uint32_t A; /*!< Pin select for A signal */ - __IO uint32_t B; /*!< Pin select for B signal */ -} QDEC_PSEL_Type; + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[0]: Beginning address in + Data RAM of this sequence */ + __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[0]: Amount of values (duty + cycles) in this sequence */ + __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[0]: Amount of additional + PWM periods between samples loaded into + compare register */ + __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[0]: Time added after the + sequence */ + __IM uint32_t RESERVED[4]; +} PWM_SEQ_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief PWM_PSEL [PSEL] (Unspecified) + */ typedef struct { - __IO uint32_t PTR; /*!< Description cluster[0]: Beginning address in Data RAM of sequence - A */ - __IO uint32_t CNT; /*!< Description cluster[0]: Amount of values (duty cycles) in sequence - A */ - __IO uint32_t REFRESH; /*!< Description cluster[0]: Amount of additional PWM periods between - samples loaded to compare register (load every CNT+1 PWM periods) */ - __IO uint32_t ENDDELAY; /*!< Description cluster[0]: Time added after the sequence */ - __I uint32_t RESERVED1[4]; -} PWM_SEQ_Type; + __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[0]: Output pin select + for PWM channel 0 */ +} PWM_PSEL_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief PDM_PSEL [PSEL] (Unspecified) + */ typedef struct { - __IO uint32_t OUT[4]; /*!< Description collection[0]: Output pin select for PWM channel - 0 */ -} PWM_PSEL_Type; + __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ + __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ +} PDM_PSEL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief PDM_SAMPLE [SAMPLE] (Unspecified) + */ typedef struct { - __IO uint32_t CLK; /*!< Pin number configuration for PDM CLK signal */ - __IO uint32_t DIN; /*!< Pin number configuration for PDM DIN signal */ -} PDM_PSEL_Type; + __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with + EasyDMA */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA + mode */ +} PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) + */ typedef struct { - __IO uint32_t PTR; /*!< RAM address pointer to write samples to with EasyDMA */ - __IO uint32_t MAXCNT; /*!< Number of samples to allocate memory for in EasyDMA mode */ -} PDM_SAMPLE_Type; + __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[0]: Enable channel group + 0 */ + __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[0]: Disable channel group + 0 */ +} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief PPI_CH [CH] (PPI Channel) + */ typedef struct { - __O uint32_t EN; /*!< Description cluster[0]: Enable channel group 0 */ - __O uint32_t DIS; /*!< Description cluster[0]: Disable channel group 0 */ -} PPI_TASKS_CHG_Type; + __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[0]: Channel 0 event end-point */ + __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[0]: Channel 0 task end-point */ +} PPI_CH_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief PPI_FORK [FORK] (Fork) + */ typedef struct { - __IO uint32_t EEP; /*!< Description cluster[0]: Channel 0 event end-point */ - __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */ -} PPI_CH_Type; + __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[0]: Channel 0 task end-point */ +} PPI_FORK_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Unspecified) + */ typedef struct { - __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */ -} PPI_FORK_Type; + __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[0]: Write access to region + 0 detected */ + __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[0]: Read access to region + 0 detected */ +} MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Unspecified) + */ typedef struct { - __IO uint32_t WA; /*!< Description cluster[0]: Write access to region 0 detected */ - __IO uint32_t RA; /*!< Description cluster[0]: Read access to region 0 detected */ -} MWU_EVENTS_REGION_Type; + __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[0]: Write access to peripheral + region 0 detected */ + __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[0]: Read access to peripheral + region 0 detected */ +} MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief MWU_PERREGION [PERREGION] (Unspecified) + */ typedef struct { - __IO uint32_t WA; /*!< Description cluster[0]: Write access to peripheral region 0 - detected */ - __IO uint32_t RA; /*!< Description cluster[0]: Read access to peripheral region 0 detected */ -} MWU_EVENTS_PREGION_Type; + __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster[0]: Source of event/interrupt + in region 0, write access detected while + corresponding subregion was enabled for + watching */ + __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster[0]: Source of event/interrupt + in region 0, read access detected while + corresponding subregion was enabled for + watching */ +} MWU_PERREGION_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief MWU_REGION [REGION] (Unspecified) + */ typedef struct { - __IO uint32_t SUBSTATWA; /*!< Description cluster[0]: Source of event/interrupt in region - 0, write access detected while corresponding subregion was enabled - for watching */ - __IO uint32_t SUBSTATRA; /*!< Description cluster[0]: Source of event/interrupt in region - 0, read access detected while corresponding subregion was enabled - for watching */ -} MWU_PERREGION_Type; + __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster[0]: Start address for region + 0 */ + __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster[0]: End address of region + 0 */ + __IM uint32_t RESERVED[2]; +} MWU_REGION_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief MWU_PREGION [PREGION] (Unspecified) + */ typedef struct { - __IO uint32_t START; /*!< Description cluster[0]: Start address for region 0 */ - __IO uint32_t END; /*!< Description cluster[0]: End address of region 0 */ - __I uint32_t RESERVED2[2]; -} MWU_REGION_Type; + __IM uint32_t START; /*!< (@ 0x00000000) Description cluster[0]: Reserved for future use */ + __IM uint32_t END; /*!< (@ 0x00000004) Description cluster[0]: Reserved for future use */ + __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster[0]: Subregions of region + 0 */ + __IM uint32_t RESERVED; +} MWU_PREGION_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief I2S_CONFIG [CONFIG] (Unspecified) + */ typedef struct { - __I uint32_t START; /*!< Description cluster[0]: Reserved for future use */ - __I uint32_t END; /*!< Description cluster[0]: Reserved for future use */ - __IO uint32_t SUBS; /*!< Description cluster[0]: Subregions of region 0 */ - __I uint32_t RESERVED3; -} MWU_PREGION_Type; + __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ + __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ + __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ + __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ + __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ + __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ + __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ + __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ + __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ + __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ +} I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ + +/** + * @brief I2S_RXD [RXD] (Unspecified) + */ typedef struct { - __IO uint32_t MODE; /*!< I2S mode. */ - __IO uint32_t RXEN; /*!< Reception (RX) enable. */ - __IO uint32_t TXEN; /*!< Transmission (TX) enable. */ - __IO uint32_t MCKEN; /*!< Master clock generator enable. */ - __IO uint32_t MCKFREQ; /*!< Master clock generator frequency. */ - __IO uint32_t RATIO; /*!< MCK / LRCK ratio. */ - __IO uint32_t SWIDTH; /*!< Sample width. */ - __IO uint32_t ALIGN; /*!< Alignment of sample within a frame. */ - __IO uint32_t FORMAT; /*!< Frame format. */ - __IO uint32_t CHANNELS; /*!< Enable channels. */ -} I2S_CONFIG_Type; + __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ +} I2S_RXD_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief I2S_TXD [TXD] (Unspecified) + */ typedef struct { - __IO uint32_t PTR; /*!< Receive buffer RAM start address. */ -} I2S_RXD_Type; + __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ +} I2S_TXD_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief I2S_RXTXD [RXTXD] (Unspecified) + */ typedef struct { - __IO uint32_t PTR; /*!< Transmit buffer RAM start address. */ -} I2S_TXD_Type; + __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ +} I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief I2S_PSEL [PSEL] (Unspecified) + */ typedef struct { - __IO uint32_t MAXCNT; /*!< Size of RXD and TXD buffers. */ -} I2S_RXTXD_Type; - -typedef struct { - __IO uint32_t MCK; /*!< Pin select for MCK signal. */ - __IO uint32_t SCK; /*!< Pin select for SCK signal. */ - __IO uint32_t LRCK; /*!< Pin select for LRCK signal. */ - __IO uint32_t SDIN; /*!< Pin select for SDIN signal. */ - __IO uint32_t SDOUT; /*!< Pin select for SDOUT signal. */ -} I2S_PSEL_Type; + __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ + __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ + __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ + __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ + __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ +} I2S_PSEL_Type; /*!< Size = 20 (0x14) */ -/* ================================================================================ */ -/* ================ FICR ================ */ -/* ================================================================================ */ +/** @} */ /* End of group Device_Peripheral_clusters */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ FICR ================ */ +/* =========================================================================================================================== */ /** * @brief Factory Information Configuration Registers (FICR) */ -typedef struct { /*!< FICR Structure */ - __I uint32_t RESERVED0[4]; - __I uint32_t CODEPAGESIZE; /*!< Code memory page size */ - __I uint32_t CODESIZE; /*!< Code memory size */ - __I uint32_t RESERVED1[18]; - __I uint32_t DEVICEID[2]; /*!< Description collection[0]: Device identifier */ - __I uint32_t RESERVED2[6]; - __I uint32_t ER[4]; /*!< Description collection[0]: Encryption Root, word 0 */ - __I uint32_t IR[4]; /*!< Description collection[0]: Identity Root, word 0 */ - __I uint32_t DEVICEADDRTYPE; /*!< Device address type */ - __I uint32_t DEVICEADDR[2]; /*!< Description collection[0]: Device address 0 */ - __I uint32_t RESERVED3[21]; - FICR_INFO_Type INFO; /*!< Device info */ - __I uint32_t RESERVED4[185]; - FICR_TEMP_Type TEMP; /*!< Registers storing factory TEMP module linearization coefficients */ - __I uint32_t RESERVED5[2]; - FICR_NFC_Type NFC; /*!< Unspecified */ -} NRF_FICR_Type; +typedef struct { /*!< (@ 0x10000000) FICR Structure */ + __IM uint32_t RESERVED[4]; + __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ + __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ + __IM uint32_t RESERVED1[18]; + __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[0]: Device identifier */ + __IM uint32_t RESERVED2[6]; + __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[0]: Encryption Root, word + 0 */ + __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[0]: Identity Root, word + 0 */ + __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ + __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[0]: Device address 0 */ + __IM uint32_t RESERVED3[21]; + __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ + __IM uint32_t RESERVED4[185]; + __IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization + coefficients */ + __IM uint32_t RESERVED5[2]; + __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ +} NRF_FICR_Type; /*!< Size = 1120 (0x460) */ -/* ================================================================================ */ -/* ================ UICR ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ UICR ================ */ +/* =========================================================================================================================== */ /** * @brief User Information Configuration Registers (UICR) */ -typedef struct { /*!< UICR Structure */ - __IO uint32_t UNUSED0; /*!< Unspecified */ - __IO uint32_t UNUSED1; /*!< Unspecified */ - __IO uint32_t UNUSED2; /*!< Unspecified */ - __I uint32_t RESERVED0; - __IO uint32_t UNUSED3; /*!< Unspecified */ - __IO uint32_t NRFFW[15]; /*!< Description collection[0]: Reserved for Nordic firmware design */ - __IO uint32_t NRFHW[12]; /*!< Description collection[0]: Reserved for Nordic hardware design */ - __IO uint32_t CUSTOMER[32]; /*!< Description collection[0]: Reserved for customer */ - __I uint32_t RESERVED1[64]; - __IO uint32_t PSELRESET[2]; /*!< Description collection[0]: Mapping of the nRESET function (see - POWER chapter for details) */ - __IO uint32_t APPROTECT; /*!< Access Port protection */ - __IO uint32_t NFCPINS; /*!< Setting of pins dedicated to NFC functionality: NFC antenna - or GPIO */ -} NRF_UICR_Type; +typedef struct { /*!< (@ 0x10001000) UICR Structure */ + __IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */ + __IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */ + __IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */ + __IM uint32_t RESERVED; + __IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */ + __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[0]: Reserved for Nordic + firmware design */ + __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[0]: Reserved for Nordic + hardware design */ + __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[0]: Reserved for customer */ + __IM uint32_t RESERVED1[64]; + __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[0]: Mapping of the nRESET + function (see POWER chapter for details) */ + __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access Port protection */ + __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: + NFC antenna or GPIO */ +} NRF_UICR_Type; /*!< Size = 528 (0x210) */ -/* ================================================================================ */ -/* ================ BPROT ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ BPROT ================ */ +/* =========================================================================================================================== */ /** * @brief Block Protect (BPROT) */ -typedef struct { /*!< BPROT Structure */ - __I uint32_t RESERVED0[384]; - __IO uint32_t CONFIG0; /*!< Block protect configuration register 0 */ - __IO uint32_t CONFIG1; /*!< Block protect configuration register 1 */ - __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug interface mode */ - __IO uint32_t UNUSED0; /*!< Unspecified */ - __IO uint32_t CONFIG2; /*!< Block protect configuration register 2 */ - __IO uint32_t CONFIG3; /*!< Block protect configuration register 3 */ -} NRF_BPROT_Type; +typedef struct { /*!< (@ 0x40000000) BPROT Structure */ + __IM uint32_t RESERVED[384]; + __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */ + __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */ + __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug interface + mode */ + __IOM uint32_t UNUSED0; /*!< (@ 0x0000060C) Unspecified */ + __IOM uint32_t CONFIG2; /*!< (@ 0x00000610) Block protect configuration register 2 */ + __IOM uint32_t CONFIG3; /*!< (@ 0x00000614) Block protect configuration register 3 */ +} NRF_BPROT_Type; /*!< Size = 1560 (0x618) */ -/* ================================================================================ */ -/* ================ POWER ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ POWER ================ */ +/* =========================================================================================================================== */ /** * @brief Power control (POWER) */ -typedef struct { /*!< POWER Structure */ - __I uint32_t RESERVED0[30]; - __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode */ - __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency) */ - __I uint32_t RESERVED1[34]; - __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning */ - __I uint32_t RESERVED2[2]; - __IO uint32_t EVENTS_SLEEPENTER; /*!< CPU entered WFI/WFE sleep */ - __IO uint32_t EVENTS_SLEEPEXIT; /*!< CPU exited WFI/WFE sleep */ - __I uint32_t RESERVED3[122]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED4[61]; - __IO uint32_t RESETREAS; /*!< Reset reason */ - __I uint32_t RESERVED5[9]; - __I uint32_t RAMSTATUS; /*!< Deprecated register - RAM status register */ - __I uint32_t RESERVED6[53]; - __O uint32_t SYSTEMOFF; /*!< System OFF register */ - __I uint32_t RESERVED7[3]; - __IO uint32_t POFCON; /*!< Power failure comparator configuration */ - __I uint32_t RESERVED8[2]; - __IO uint32_t GPREGRET; /*!< General purpose retention register */ - __IO uint32_t GPREGRET2; /*!< General purpose retention register */ - __IO uint32_t RAMON; /*!< Deprecated register - RAM on/off register (this register is - retained) */ - __I uint32_t RESERVED9[11]; - __IO uint32_t RAMONB; /*!< Deprecated register - RAM on/off register (this register is - retained) */ - __I uint32_t RESERVED10[8]; - __IO uint32_t DCDCEN; /*!< DC/DC enable register */ - __I uint32_t RESERVED11[225]; - POWER_RAM_Type RAM[8]; /*!< Unspecified */ -} NRF_POWER_Type; +typedef struct { /*!< (@ 0x40000000) POWER Structure */ + __IM uint32_t RESERVED[30]; + __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ + __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ + __IM uint32_t RESERVED1[34]; + __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ + __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ + __IM uint32_t RESERVED3[122]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ + __IM uint32_t RESERVED5[9]; + __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ + __IM uint32_t RESERVED6[53]; + __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure comparator configuration */ + __IM uint32_t RESERVED8[2]; + __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ + __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ + __IOM uint32_t RAMON; /*!< (@ 0x00000524) Deprecated register - RAM on/off register (this + register is retained) */ + __IM uint32_t RESERVED9[11]; + __IOM uint32_t RAMONB; /*!< (@ 0x00000554) Deprecated register - RAM on/off register (this + register is retained) */ + __IM uint32_t RESERVED10[8]; + __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DC/DC enable register */ + __IM uint32_t RESERVED11[225]; + __IOM POWER_RAM_Type RAM[8]; /*!< (@ 0x00000900) Unspecified */ +} NRF_POWER_Type; /*!< Size = 2432 (0x980) */ -/* ================================================================================ */ -/* ================ CLOCK ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ CLOCK ================ */ +/* =========================================================================================================================== */ /** * @brief Clock control (CLOCK) */ -typedef struct { /*!< CLOCK Structure */ - __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK crystal oscillator */ - __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK crystal oscillator */ - __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK source */ - __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK source */ - __O uint32_t TASKS_CAL; /*!< Start calibration of LFRC oscillator */ - __O uint32_t TASKS_CTSTART; /*!< Start calibration timer */ - __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer */ - __I uint32_t RESERVED0[57]; - __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started */ - __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK started */ - __I uint32_t RESERVED1; - __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator complete event */ - __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout */ - __I uint32_t RESERVED2[124]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[63]; - __I uint32_t HFCLKRUN; /*!< Status indicating that HFCLKSTART task has been triggered */ - __I uint32_t HFCLKSTAT; /*!< HFCLK status */ - __I uint32_t RESERVED4; - __I uint32_t LFCLKRUN; /*!< Status indicating that LFCLKSTART task has been triggered */ - __I uint32_t LFCLKSTAT; /*!< LFCLK status */ - __I uint32_t LFCLKSRCCOPY; /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ - __I uint32_t RESERVED5[62]; - __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK */ - __I uint32_t RESERVED6[7]; - __IO uint32_t CTIV; /*!< Calibration timer interval (retained register, same reset behaviour - as RESETREAS) */ - __I uint32_t RESERVED7[8]; - __IO uint32_t TRACECONFIG; /*!< Clocking options for the Trace Port debug interface */ -} NRF_CLOCK_Type; +typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ + __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */ + __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */ + __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ + __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ + __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ + __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ + __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ + __IM uint32_t RESERVED[57]; + __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ + __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ + __IM uint32_t RESERVED1; + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */ + __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ + __IM uint32_t RESERVED2[124]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[63]; + __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been + triggered */ + __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ + __IM uint32_t RESERVED4; + __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been + triggered */ + __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ + __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART + task was triggered */ + __IM uint32_t RESERVED5[62]; + __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ + __IM uint32_t RESERVED6[7]; + __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ + __IM uint32_t RESERVED7[8]; + __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the Trace Port debug interface */ +} NRF_CLOCK_Type; /*!< Size = 1376 (0x560) */ -/* ================================================================================ */ -/* ================ AMLI ================ */ -/* ================================================================================ */ - -/** - * @brief AHB Multi-Layer Interface (AMLI) - */ - -typedef struct { /*!< AMLI Structure */ - __I uint32_t RESERVED0[896]; - AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure */ -} NRF_AMLI_Type; - - -/* ================================================================================ */ -/* ================ RADIO ================ */ -/* ================================================================================ */ +/* =========================================================================================================================== */ +/* ================ RADIO ================ */ +/* =========================================================================================================================== */ /** * @brief 2.4 GHz Radio (RADIO) */ -typedef struct { /*!< RADIO Structure */ - __O uint32_t TASKS_TXEN; /*!< Enable RADIO in TX mode */ - __O uint32_t TASKS_RXEN; /*!< Enable RADIO in RX mode */ - __O uint32_t TASKS_START; /*!< Start RADIO */ - __O uint32_t TASKS_STOP; /*!< Stop RADIO */ - __O uint32_t TASKS_DISABLE; /*!< Disable RADIO */ - __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one single sample of the receive signal - strength. */ - __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement */ - __O uint32_t TASKS_BCSTART; /*!< Start the bit counter */ - __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter */ - __I uint32_t RESERVED0[55]; - __IO uint32_t EVENTS_READY; /*!< RADIO has ramped up and is ready to be started */ - __IO uint32_t EVENTS_ADDRESS; /*!< Address sent or received */ - __IO uint32_t EVENTS_PAYLOAD; /*!< Packet payload sent or received */ - __IO uint32_t EVENTS_END; /*!< Packet sent or received */ - __IO uint32_t EVENTS_DISABLED; /*!< RADIO has been disabled */ - __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet */ - __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet */ - __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of receive signal strength complete. */ - __I uint32_t RESERVED1[2]; - __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value. */ - __I uint32_t RESERVED2; - __IO uint32_t EVENTS_CRCOK; /*!< Packet received with CRC ok */ - __IO uint32_t EVENTS_CRCERROR; /*!< Packet received with CRC error */ - __I uint32_t RESERVED3[50]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED4[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED5[61]; - __I uint32_t CRCSTATUS; /*!< CRC status */ - __I uint32_t RESERVED6; - __I uint32_t RXMATCH; /*!< Received address */ - __I uint32_t RXCRC; /*!< CRC field of previously received packet */ - __I uint32_t DAI; /*!< Device address match index */ - __I uint32_t RESERVED7[60]; - __IO uint32_t PACKETPTR; /*!< Packet pointer */ - __IO uint32_t FREQUENCY; /*!< Frequency */ - __IO uint32_t TXPOWER; /*!< Output power */ - __IO uint32_t MODE; /*!< Data rate and modulation */ - __IO uint32_t PCNF0; /*!< Packet configuration register 0 */ - __IO uint32_t PCNF1; /*!< Packet configuration register 1 */ - __IO uint32_t BASE0; /*!< Base address 0 */ - __IO uint32_t BASE1; /*!< Base address 1 */ - __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0-3 */ - __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4-7 */ - __IO uint32_t TXADDRESS; /*!< Transmit address select */ - __IO uint32_t RXADDRESSES; /*!< Receive address select */ - __IO uint32_t CRCCNF; /*!< CRC configuration */ - __IO uint32_t CRCPOLY; /*!< CRC polynomial */ - __IO uint32_t CRCINIT; /*!< CRC initial value */ - __IO uint32_t UNUSED0; /*!< Unspecified */ - __IO uint32_t TIFS; /*!< Inter Frame Spacing in us */ - __I uint32_t RSSISAMPLE; /*!< RSSI sample */ - __I uint32_t RESERVED8; - __I uint32_t STATE; /*!< Current radio state */ - __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value */ - __I uint32_t RESERVED9[2]; - __IO uint32_t BCC; /*!< Bit counter compare */ - __I uint32_t RESERVED10[39]; - __IO uint32_t DAB[8]; /*!< Description collection[0]: Device address base segment 0 */ - __IO uint32_t DAP[8]; /*!< Description collection[0]: Device address prefix 0 */ - __IO uint32_t DACNF; /*!< Device address match configuration */ - __I uint32_t RESERVED11[3]; - __IO uint32_t MODECNF0; /*!< Radio mode configuration register 0 */ - __I uint32_t RESERVED12[618]; - __IO uint32_t POWER; /*!< Peripheral power control */ -} NRF_RADIO_Type; +typedef struct { /*!< (@ 0x40001000) RADIO Structure */ + __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ + __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ + __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of + the receive signal strength. */ + __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ + __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ + __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ + __IM uint32_t RESERVED[55]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ + __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ + __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ + __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ + __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received + packet */ + __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last + received packet */ + __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete. */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value. */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ + __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ + __IM uint32_t RESERVED3[50]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED4[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED5[61]; + __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ + __IM uint32_t RESERVED6; + __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ + __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ + __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ + __IM uint32_t RESERVED7[60]; + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ + __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ + __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ + __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ + __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ + __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ + __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ + __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ + __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ + __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ + __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ + __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ + __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ + __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ + __IOM uint32_t UNUSED0; /*!< (@ 0x00000540) Unspecified */ + __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in us */ + __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ + __IM uint32_t RESERVED8; + __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ + __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ + __IM uint32_t RESERVED10[39]; + __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[0]: Device address base + segment 0 */ + __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[0]: Device address prefix + 0 */ + __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ + __IM uint32_t RESERVED11[3]; + __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ + __IM uint32_t RESERVED12[618]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ +} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ -/* ================================================================================ */ -/* ================ UARTE ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ UARTE0 ================ */ +/* =========================================================================================================================== */ /** - * @brief UART with EasyDMA (UARTE) + * @brief UART with EasyDMA (UARTE0) */ -typedef struct { /*!< UARTE Structure */ - __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */ - __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */ - __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */ - __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */ - __I uint32_t RESERVED0[7]; - __O uint32_t TASKS_FLUSHRX; /*!< Flush RX FIFO into RX buffer */ - __I uint32_t RESERVED1[52]; - __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */ - __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */ - __I uint32_t RESERVED2[2]; - __IO uint32_t EVENTS_ENDRX; /*!< Receive buffer is filled up */ - __I uint32_t RESERVED3[3]; - __IO uint32_t EVENTS_ENDTX; /*!< Last TX byte transmitted */ - __IO uint32_t EVENTS_ERROR; /*!< Error detected */ - __I uint32_t RESERVED4[7]; - __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */ - __I uint32_t RESERVED5; - __IO uint32_t EVENTS_RXSTARTED; /*!< UART receiver has started */ - __IO uint32_t EVENTS_TXSTARTED; /*!< UART transmitter has started */ - __I uint32_t RESERVED6; - __IO uint32_t EVENTS_TXSTOPPED; /*!< Transmitter stopped */ - __I uint32_t RESERVED7[41]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED8[63]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED9[93]; - __IO uint32_t ERRORSRC; /*!< Error source */ - __I uint32_t RESERVED10[31]; - __IO uint32_t ENABLE; /*!< Enable UART */ - __I uint32_t RESERVED11; - UARTE_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED12[3]; - __IO uint32_t BAUDRATE; /*!< Baud rate */ - __I uint32_t RESERVED13[3]; - UARTE_RXD_Type RXD; /*!< RXD EasyDMA channel */ - __I uint32_t RESERVED14; - UARTE_TXD_Type TXD; /*!< TXD EasyDMA channel */ - __I uint32_t RESERVED15[7]; - __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */ -} NRF_UARTE_Type; +typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[7]; + __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ + __IM uint32_t RESERVED1[52]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet + transferred to Data RAM) */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ + __IM uint32_t RESERVED6; + __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ + __IM uint32_t RESERVED7[41]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ + __IM uint32_t RESERVED10[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED11; + __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected. */ + __IM uint32_t RESERVED13[3]; + __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IM uint32_t RESERVED14; + __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED15[7]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ -/* ================================================================================ */ -/* ================ UART ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ /** - * @brief Universal Asynchronous Receiver/Transmitter (UART) + * @brief Universal Asynchronous Receiver/Transmitter (UART0) */ -typedef struct { /*!< UART Structure */ - __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */ - __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */ - __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */ - __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */ - __I uint32_t RESERVED0[3]; - __O uint32_t TASKS_SUSPEND; /*!< Suspend UART */ - __I uint32_t RESERVED1[56]; - __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */ - __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */ - __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD */ - __I uint32_t RESERVED2[4]; - __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */ - __I uint32_t RESERVED3; - __IO uint32_t EVENTS_ERROR; /*!< Error detected */ - __I uint32_t RESERVED4[7]; - __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */ - __I uint32_t RESERVED5[46]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED6[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED7[93]; - __IO uint32_t ERRORSRC; /*!< Error source */ - __I uint32_t RESERVED8[31]; - __IO uint32_t ENABLE; /*!< Enable UART */ - __I uint32_t RESERVED9; - __IO uint32_t PSELRTS; /*!< Pin select for RTS */ - __IO uint32_t PSELTXD; /*!< Pin select for TXD */ - __IO uint32_t PSELCTS; /*!< Pin select for CTS */ - __IO uint32_t PSELRXD; /*!< Pin select for RXD */ - __I uint32_t RXD; /*!< RXD register */ - __O uint32_t TXD; /*!< TXD register */ - __I uint32_t RESERVED10; - __IO uint32_t BAUDRATE; /*!< Baud rate */ - __I uint32_t RESERVED11[17]; - __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */ -} NRF_UART_Type; +typedef struct { /*!< (@ 0x40002000) UART0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[3]; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ + __IM uint32_t RESERVED1[56]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IM uint32_t RESERVED3; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5[46]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED6[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED7[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ + __IM uint32_t RESERVED8[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED9; + __IOM uint32_t PSELRTS; /*!< (@ 0x00000508) Pin select for RTS */ + __IOM uint32_t PSELTXD; /*!< (@ 0x0000050C) Pin select for TXD */ + __IOM uint32_t PSELCTS; /*!< (@ 0x00000510) Pin select for CTS */ + __IOM uint32_t PSELRXD; /*!< (@ 0x00000514) Pin select for RXD */ + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED10; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate */ + __IM uint32_t RESERVED11[17]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UART_Type; /*!< Size = 1392 (0x570) */ -/* ================================================================================ */ -/* ================ SPIM ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ SPIM0 ================ */ +/* =========================================================================================================================== */ /** - * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM) + * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) */ -typedef struct { /*!< SPIM Structure */ - __I uint32_t RESERVED0[4]; - __O uint32_t TASKS_START; /*!< Start SPI transaction */ - __O uint32_t TASKS_STOP; /*!< Stop SPI transaction */ - __I uint32_t RESERVED1; - __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction */ - __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction */ - __I uint32_t RESERVED2[56]; - __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped */ - __I uint32_t RESERVED3[2]; - __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ - __I uint32_t RESERVED4; - __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached */ - __I uint32_t RESERVED5; - __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached */ - __I uint32_t RESERVED6[10]; - __IO uint32_t EVENTS_STARTED; /*!< Transaction started */ - __I uint32_t RESERVED7[44]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED8[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED9[125]; - __IO uint32_t ENABLE; /*!< Enable SPIM */ - __I uint32_t RESERVED10; - SPIM_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED11[4]; - __IO uint32_t FREQUENCY; /*!< SPI frequency */ - __I uint32_t RESERVED12[3]; - SPIM_RXD_Type RXD; /*!< RXD EasyDMA channel */ - SPIM_TXD_Type TXD; /*!< TXD EasyDMA channel */ - __IO uint32_t CONFIG; /*!< Configuration register */ - __I uint32_t RESERVED13[26]; - __IO uint32_t ORC; /*!< Over-read character. Character clocked out in case and over-read - of the TXD buffer. */ -} NRF_SPIM_Type; +typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED4; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ + __IM uint32_t RESERVED6[10]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ + __IM uint32_t RESERVED7[44]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ + __IM uint32_t RESERVED10; + __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED11[4]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED12[3]; + __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED13[26]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in + case and over-read of the TXD buffer. */ +} NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ -/* ================================================================================ */ -/* ================ SPIS ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ SPIS0 ================ */ +/* =========================================================================================================================== */ /** - * @brief SPI Slave 0 (SPIS) + * @brief SPI Slave 0 (SPIS0) */ -typedef struct { /*!< SPIS Structure */ - __I uint32_t RESERVED0[9]; - __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore */ - __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore, enabling the SPI slave to acquire it */ - __I uint32_t RESERVED1[54]; - __IO uint32_t EVENTS_END; /*!< Granted transaction completed */ - __I uint32_t RESERVED2[2]; - __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ - __I uint32_t RESERVED3[5]; - __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired */ - __I uint32_t RESERVED4[53]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED5[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED6[61]; - __I uint32_t SEMSTAT; /*!< Semaphore status register */ - __I uint32_t RESERVED7[15]; - __IO uint32_t STATUS; /*!< Status from last transaction */ - __I uint32_t RESERVED8[47]; - __IO uint32_t ENABLE; /*!< Enable SPI slave */ - __I uint32_t RESERVED9; - SPIS_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED10[7]; - SPIS_RXD_Type RXD; /*!< Unspecified */ - __I uint32_t RESERVED11; - SPIS_TXD_Type TXD; /*!< Unspecified */ - __I uint32_t RESERVED12; - __IO uint32_t CONFIG; /*!< Configuration register */ - __I uint32_t RESERVED13; - __IO uint32_t DEF; /*!< Default character. Character clocked out in case of an ignored - transaction. */ - __I uint32_t RESERVED14[24]; - __IO uint32_t ORC; /*!< Over-read character */ -} NRF_SPIS_Type; +typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ + __IM uint32_t RESERVED[9]; + __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ + __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave + to acquire it */ + __IM uint32_t RESERVED1[54]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ + __IM uint32_t RESERVED4[53]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED6[61]; + __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ + __IM uint32_t RESERVED7[15]; + __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ + __IM uint32_t RESERVED8[47]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ + __IM uint32_t RESERVED9; + __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED10[7]; + __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ + __IM uint32_t RESERVED11; + __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ + __IM uint32_t RESERVED12; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED13; + __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case + of an ignored transaction. */ + __IM uint32_t RESERVED14[24]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ +} NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ -/* ================================================================================ */ -/* ================ TWIM ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ TWIM0 ================ */ +/* =========================================================================================================================== */ /** - * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM) + * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) */ -typedef struct { /*!< TWIM Structure */ - __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */ - __I uint32_t RESERVED0; - __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */ - __I uint32_t RESERVED1[2]; - __O uint32_t TASKS_STOP; /*!< Stop TWI transaction. Must be issued while the TWI master is - not suspended. */ - __I uint32_t RESERVED2; - __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ - __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ - __I uint32_t RESERVED3[56]; - __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ - __I uint32_t RESERVED4[7]; - __IO uint32_t EVENTS_ERROR; /*!< TWI error */ - __I uint32_t RESERVED5[8]; - __IO uint32_t EVENTS_SUSPENDED; /*!< Last byte has been sent out after the SUSPEND task has been - issued, TWI traffic is now suspended. */ - __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */ - __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */ - __I uint32_t RESERVED6[2]; - __IO uint32_t EVENTS_LASTRX; /*!< Byte boundary, starting to receive the last byte */ - __IO uint32_t EVENTS_LASTTX; /*!< Byte boundary, starting to transmit the last byte */ - __I uint32_t RESERVED7[39]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED8[63]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED9[110]; - __IO uint32_t ERRORSRC; /*!< Error source */ - __I uint32_t RESERVED10[14]; - __IO uint32_t ENABLE; /*!< Enable TWIM */ - __I uint32_t RESERVED11; - TWIM_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED12[5]; - __IO uint32_t FREQUENCY; /*!< TWI frequency */ - __I uint32_t RESERVED13[3]; - TWIM_RXD_Type RXD; /*!< RXD EasyDMA channel */ - TWIM_TXD_Type TXD; /*!< TXD EasyDMA channel */ - __I uint32_t RESERVED14[13]; - __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */ -} NRF_TWIM_Type; +typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the + TWI master is not suspended. */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND + task has been issued, TWI traffic is now + suspended. */ + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[2]; + __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ + __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last + byte */ + __IM uint32_t RESERVED7[39]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED10[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ + __IM uint32_t RESERVED11; + __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[5]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */ + __IM uint32_t RESERVED13[3]; + __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED14[13]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ -/* ================================================================================ */ -/* ================ TWIS ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ TWIS0 ================ */ +/* =========================================================================================================================== */ /** - * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS) + * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) */ -typedef struct { /*!< TWIS Structure */ - __I uint32_t RESERVED0[5]; - __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */ - __I uint32_t RESERVED1; - __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ - __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ - __I uint32_t RESERVED2[3]; - __O uint32_t TASKS_PREPARERX; /*!< Prepare the TWI slave to respond to a write command */ - __O uint32_t TASKS_PREPARETX; /*!< Prepare the TWI slave to respond to a read command */ - __I uint32_t RESERVED3[51]; - __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ - __I uint32_t RESERVED4[7]; - __IO uint32_t EVENTS_ERROR; /*!< TWI error */ - __I uint32_t RESERVED5[9]; - __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */ - __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */ - __I uint32_t RESERVED6[4]; - __IO uint32_t EVENTS_WRITE; /*!< Write command received */ - __IO uint32_t EVENTS_READ; /*!< Read command received */ - __I uint32_t RESERVED7[37]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED8[63]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED9[113]; - __IO uint32_t ERRORSRC; /*!< Error source */ - __I uint32_t MATCH; /*!< Status register indicating which address had a match */ - __I uint32_t RESERVED10[10]; - __IO uint32_t ENABLE; /*!< Enable TWIS */ - __I uint32_t RESERVED11; - TWIS_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED12[9]; - TWIS_RXD_Type RXD; /*!< RXD EasyDMA channel */ - __I uint32_t RESERVED13; - TWIS_TXD_Type TXD; /*!< TXD EasyDMA channel */ - __I uint32_t RESERVED14[14]; - __IO uint32_t ADDRESS[2]; /*!< Description collection[0]: TWI slave address 0 */ - __I uint32_t RESERVED15; - __IO uint32_t CONFIG; /*!< Configuration register for the address match mechanism */ - __I uint32_t RESERVED16[10]; - __IO uint32_t ORC; /*!< Over-read character. Character sent out in case of an over-read - of the transmit buffer. */ -} NRF_TWIS_Type; +typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ + __IM uint32_t RESERVED[5]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED2[3]; + __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ + __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ + __IM uint32_t RESERVED3[51]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[9]; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ + __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ + __IM uint32_t RESERVED7[37]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[113]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ + __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had + a match */ + __IM uint32_t RESERVED10[10]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ + __IM uint32_t RESERVED11; + __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[9]; + __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IM uint32_t RESERVED13; + __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED14[14]; + __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[0]: TWI slave address + 0 */ + __IM uint32_t RESERVED15; + __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match + mechanism */ + __IM uint32_t RESERVED16[10]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case + of an over-read of the transmit buffer. */ +} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ -/* ================================================================================ */ -/* ================ SPI ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ /** - * @brief Serial Peripheral Interface 0 (SPI) + * @brief Serial Peripheral Interface 0 (SPI0) */ -typedef struct { /*!< SPI Structure */ - __I uint32_t RESERVED0[66]; - __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received */ - __I uint32_t RESERVED1[126]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[125]; - __IO uint32_t ENABLE; /*!< Enable SPI */ - __I uint32_t RESERVED3; - SPI_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED4; - __I uint32_t RXD; /*!< RXD register */ - __IO uint32_t TXD; /*!< TXD register */ - __I uint32_t RESERVED5; - __IO uint32_t FREQUENCY; /*!< SPI frequency */ - __I uint32_t RESERVED6[11]; - __IO uint32_t CONFIG; /*!< Configuration register */ -} NRF_SPI_Type; +typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ + __IM uint32_t RESERVED[66]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ + __IM uint32_t RESERVED1[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ + __IM uint32_t RESERVED3; + __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED4; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED5; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ +} NRF_SPI_Type; /*!< Size = 1368 (0x558) */ -/* ================================================================================ */ -/* ================ TWI ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ TWI0 ================ */ +/* =========================================================================================================================== */ /** - * @brief I2C compatible Two-Wire Interface 0 (TWI) + * @brief I2C compatible Two-Wire Interface 0 (TWI0) */ -typedef struct { /*!< TWI Structure */ - __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */ - __I uint32_t RESERVED0; - __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */ - __I uint32_t RESERVED1[2]; - __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */ - __I uint32_t RESERVED2; - __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ - __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ - __I uint32_t RESERVED3[56]; - __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ - __IO uint32_t EVENTS_RXDREADY; /*!< TWI RXD byte received */ - __I uint32_t RESERVED4[4]; - __IO uint32_t EVENTS_TXDSENT; /*!< TWI TXD byte sent */ - __I uint32_t RESERVED5; - __IO uint32_t EVENTS_ERROR; /*!< TWI error */ - __I uint32_t RESERVED6[4]; - __IO uint32_t EVENTS_BB; /*!< TWI byte boundary, generated before each byte that is sent or - received */ - __I uint32_t RESERVED7[3]; - __IO uint32_t EVENTS_SUSPENDED; /*!< TWI entered the suspended state */ - __I uint32_t RESERVED8[45]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED9[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED10[110]; - __IO uint32_t ERRORSRC; /*!< Error source */ - __I uint32_t RESERVED11[14]; - __IO uint32_t ENABLE; /*!< Enable TWI */ - __I uint32_t RESERVED12; - __IO uint32_t PSELSCL; /*!< Pin select for SCL */ - __IO uint32_t PSELSDA; /*!< Pin select for SDA */ - __I uint32_t RESERVED13[2]; - __I uint32_t RXD; /*!< RXD register */ - __IO uint32_t TXD; /*!< TXD register */ - __I uint32_t RESERVED14; - __IO uint32_t FREQUENCY; /*!< TWI frequency */ - __I uint32_t RESERVED15[24]; - __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */ -} NRF_TWI_Type; +typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ + __IM uint32_t RESERVED4[4]; + __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte + that is sent or received */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ + __IM uint32_t RESERVED8[45]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED9[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED10[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED11[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ + __IM uint32_t RESERVED12; + __IOM uint32_t PSELSCL; /*!< (@ 0x00000508) Pin select for SCL */ + __IOM uint32_t PSELSDA; /*!< (@ 0x0000050C) Pin select for SDA */ + __IM uint32_t RESERVED13[2]; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED14; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */ + __IM uint32_t RESERVED15[24]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ -/* ================================================================================ */ -/* ================ NFCT ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ NFCT ================ */ +/* =========================================================================================================================== */ /** * @brief NFC-A compatible radio (NFCT) */ -typedef struct { /*!< NFCT Structure */ - __O uint32_t TASKS_ACTIVATE; /*!< Activate NFC peripheral for incoming and outgoing frames, change - state to activated */ - __O uint32_t TASKS_DISABLE; /*!< Disable NFC peripheral */ - __O uint32_t TASKS_SENSE; /*!< Enable NFC sense field mode, change state to sense mode */ - __O uint32_t TASKS_STARTTX; /*!< Start transmission of a outgoing frame, change state to transmit */ - __I uint32_t RESERVED0[3]; - __O uint32_t TASKS_ENABLERXDATA; /*!< Initializes the EasyDMA for receive. */ - __I uint32_t RESERVED1; - __O uint32_t TASKS_GOIDLE; /*!< Force state machine to IDLE state */ - __O uint32_t TASKS_GOSLEEP; /*!< Force state machine to SLEEP_A state */ - __I uint32_t RESERVED2[53]; - __IO uint32_t EVENTS_READY; /*!< The NFC peripheral is ready to receive and send frames */ - __IO uint32_t EVENTS_FIELDDETECTED; /*!< Remote NFC field detected */ - __IO uint32_t EVENTS_FIELDLOST; /*!< Remote NFC field lost */ - __IO uint32_t EVENTS_TXFRAMESTART; /*!< Marks the start of the first symbol of a transmitted frame */ - __IO uint32_t EVENTS_TXFRAMEEND; /*!< Marks the end of the last transmitted on-air symbol of a frame */ - __IO uint32_t EVENTS_RXFRAMESTART; /*!< Marks the end of the first symbol of a received frame */ - __IO uint32_t EVENTS_RXFRAMEEND; /*!< Received data have been checked (CRC, parity) and transferred - to RAM, and EasyDMA has ended accessing the RX buffer */ - __IO uint32_t EVENTS_ERROR; /*!< NFC error reported. The ERRORSTATUS register contains details - on the source of the error. */ - __I uint32_t RESERVED3[2]; - __IO uint32_t EVENTS_RXERROR; /*!< NFC RX frame error reported. The FRAMESTATUS.RX register contains - details on the source of the error. */ - __IO uint32_t EVENTS_ENDRX; /*!< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ - __IO uint32_t EVENTS_ENDTX; /*!< Transmission of data in RAM has ended, and EasyDMA has ended - accessing the TX buffer */ - __I uint32_t RESERVED4; - __IO uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< Auto collision resolution process has started */ - __I uint32_t RESERVED5[3]; - __IO uint32_t EVENTS_COLLISION; /*!< NFC Auto collision resolution error reported. */ - __IO uint32_t EVENTS_SELECTED; /*!< NFC Auto collision resolution successfully completed */ - __IO uint32_t EVENTS_STARTED; /*!< EasyDMA is ready to receive or send frames. */ - __I uint32_t RESERVED6[43]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED7[63]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED8[62]; - __IO uint32_t ERRORSTATUS; /*!< NFC Error Status register */ - __I uint32_t RESERVED9; - NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< Unspecified */ - __I uint32_t RESERVED10[8]; - __I uint32_t CURRENTLOADCTRL; /*!< Current value driven to the NFC Load Control */ - __I uint32_t RESERVED11[2]; - __I uint32_t FIELDPRESENT; /*!< Indicates the presence or not of a valid field */ - __I uint32_t RESERVED12[49]; - __IO uint32_t FRAMEDELAYMIN; /*!< Minimum frame delay */ - __IO uint32_t FRAMEDELAYMAX; /*!< Maximum frame delay */ - __IO uint32_t FRAMEDELAYMODE; /*!< Configuration register for the Frame Delay Timer */ - __IO uint32_t PACKETPTR; /*!< Packet pointer for TXD and RXD data storage in Data RAM */ - __IO uint32_t MAXLEN; /*!< Size of allocated for TXD and RXD data storage buffer in Data - RAM */ - NFCT_TXD_Type TXD; /*!< Unspecified */ - NFCT_RXD_Type RXD; /*!< Unspecified */ - __I uint32_t RESERVED13[26]; - __IO uint32_t NFCID1_LAST; /*!< Last NFCID1 part (4, 7 or 10 bytes ID) */ - __IO uint32_t NFCID1_2ND_LAST; /*!< Second last NFCID1 part (7 or 10 bytes ID) */ - __IO uint32_t NFCID1_3RD_LAST; /*!< Third last NFCID1 part (10 bytes ID) */ - __I uint32_t RESERVED14; - __IO uint32_t SENSRES; /*!< NFC-A SENS_RES auto-response settings */ - __IO uint32_t SELRES; /*!< NFC-A SEL_RES auto-response settings */ -} NRF_NFCT_Type; +typedef struct { /*!< (@ 0x40005000) NFCT Structure */ + __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFC peripheral for incoming and outgoing + frames, change state to activated */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFC peripheral */ + __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to + sense mode */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of a outgoing frame, change + state to transmit */ + __IM uint32_t RESERVED[3]; + __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ + __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ + __IM uint32_t RESERVED2[53]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFC peripheral is ready to receive and send + frames */ + __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ + __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ + __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted + frame */ + __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air + symbol of a frame */ + __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received + frame */ + __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data have been checked (CRC, parity) + and transferred to RAM, and EasyDMA has + ended accessing the RX buffer */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register + contains details on the source of the error. */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX + register contains details on the source + of the error. */ + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) + in Data RAM full. */ + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA + has ended accessing the TX buffer */ + __IM uint32_t RESERVED4; + __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ + __IM uint32_t RESERVED5[3]; + __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC Auto collision resolution error reported. */ + __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC Auto collision resolution successfully completed */ + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ + __IM uint32_t RESERVED6[43]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED7[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED8[62]; + __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ + __IM uint32_t RESERVED9; + __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ + __IM uint32_t RESERVED10[8]; + __IM uint32_t CURRENTLOADCTRL; /*!< (@ 0x00000430) Current value driven to the NFC Load Control */ + __IM uint32_t RESERVED11[2]; + __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ + __IM uint32_t RESERVED12[49]; + __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ + __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ + __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in + Data RAM */ + __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of allocated for TXD and RXD data storage + buffer in Data RAM */ + __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ + __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ + __IM uint32_t RESERVED13[26]; + __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ + __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ + __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ + __IM uint32_t RESERVED14; + __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ + __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ +} NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ -/* ================================================================================ */ -/* ================ GPIOTE ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ GPIOTE ================ */ +/* =========================================================================================================================== */ /** * @brief GPIO Tasks and Events (GPIOTE) */ -typedef struct { /*!< GPIOTE Structure */ - __O uint32_t TASKS_OUT[8]; /*!< Description collection[0]: Task for writing to pin specified - in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */ - __I uint32_t RESERVED0[4]; - __O uint32_t TASKS_SET[8]; /*!< Description collection[0]: Task for writing to pin specified - in CONFIG[0].PSEL. Action on pin is to set it high. */ - __I uint32_t RESERVED1[4]; - __O uint32_t TASKS_CLR[8]; /*!< Description collection[0]: Task for writing to pin specified - in CONFIG[0].PSEL. Action on pin is to set it low. */ - __I uint32_t RESERVED2[32]; - __IO uint32_t EVENTS_IN[8]; /*!< Description collection[0]: Event generated from pin specified - in CONFIG[0].PSEL */ - __I uint32_t RESERVED3[23]; - __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple input GPIO pins with SENSE mechanism - enabled */ - __I uint32_t RESERVED4[97]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED5[129]; - __IO uint32_t CONFIG[8]; /*!< Description collection[0]: Configuration for OUT[n], SET[n] - and CLR[n] tasks and IN[n] event */ -} NRF_GPIOTE_Type; +typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ + __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[0]: Task for writing to + pin specified in CONFIG[0].PSEL. Action + on pin is configured in CONFIG[0].POLARITY. */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[0]: Task for writing to + pin specified in CONFIG[0].PSEL. Action + on pin is to set it high. */ + __IM uint32_t RESERVED1[4]; + __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[0]: Task for writing to + pin specified in CONFIG[0].PSEL. Action + on pin is to set it low. */ + __IM uint32_t RESERVED2[32]; + __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[0]: Event generated from + pin specified in CONFIG[0].PSEL */ + __IM uint32_t RESERVED3[23]; + __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins + with SENSE mechanism enabled */ + __IM uint32_t RESERVED4[97]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED5[129]; + __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[0]: Configuration for + OUT[n], SET[n] and CLR[n] tasks and IN[n] + event */ +} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ -/* ================================================================================ */ -/* ================ SAADC ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ SAADC ================ */ +/* =========================================================================================================================== */ /** * @brief Analog to Digital Converter (SAADC) */ -typedef struct { /*!< SAADC Structure */ - __O uint32_t TASKS_START; /*!< Start the ADC and prepare the result buffer in RAM */ - __O uint32_t TASKS_SAMPLE; /*!< Take one ADC sample, if scan is enabled all channels are sampled */ - __O uint32_t TASKS_STOP; /*!< Stop the ADC and terminate any on-going conversion */ - __O uint32_t TASKS_CALIBRATEOFFSET; /*!< Starts offset auto-calibration */ - __I uint32_t RESERVED0[60]; - __IO uint32_t EVENTS_STARTED; /*!< The ADC has started */ - __IO uint32_t EVENTS_END; /*!< The ADC has filled up the Result buffer */ - __IO uint32_t EVENTS_DONE; /*!< A conversion task has been completed. Depending on the mode, - multiple conversions might be needed for a result to be transferred - to RAM. */ - __IO uint32_t EVENTS_RESULTDONE; /*!< A result is ready to get transferred to RAM. */ - __IO uint32_t EVENTS_CALIBRATEDONE; /*!< Calibration is complete */ - __IO uint32_t EVENTS_STOPPED; /*!< The ADC has stopped */ - SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< Unspecified */ - __I uint32_t RESERVED1[106]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[61]; - __I uint32_t STATUS; /*!< Status */ - __I uint32_t RESERVED3[63]; - __IO uint32_t ENABLE; /*!< Enable or disable ADC */ - __I uint32_t RESERVED4[3]; - SAADC_CH_Type CH[8]; /*!< Unspecified */ - __I uint32_t RESERVED5[24]; - __IO uint32_t RESOLUTION; /*!< Resolution configuration */ - __IO uint32_t OVERSAMPLE; /*!< Oversampling configuration. OVERSAMPLE should not be combined - with SCAN. The RESOLUTION is applied before averaging, thus - for high OVERSAMPLE a higher RESOLUTION should be used. */ - __IO uint32_t SAMPLERATE; /*!< Controls normal or continuous sample rate */ - __I uint32_t RESERVED6[12]; - SAADC_RESULT_Type RESULT; /*!< RESULT EasyDMA channel */ -} NRF_SAADC_Type; +typedef struct { /*!< (@ 0x40007000) SAADC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in + RAM */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels + are sampled */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ + __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending + on the mode, multiple conversions might + be needed for a result to be transferred + to RAM. */ + __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ + __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ + __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */ + __IM uint32_t RESERVED1[106]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ + __IM uint32_t RESERVED4[3]; + __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ + __IM uint32_t RESERVED5[24]; + __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ + __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should + not be combined with SCAN. The RESOLUTION + is applied before averaging, thus for high + OVERSAMPLE a higher RESOLUTION should be + used. */ + __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ + __IM uint32_t RESERVED6[12]; + __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ +} NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ -/* ================================================================================ */ -/* ================ TIMER ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ TIMER0 ================ */ +/* =========================================================================================================================== */ /** - * @brief Timer/Counter 0 (TIMER) + * @brief Timer/Counter 0 (TIMER0) */ -typedef struct { /*!< TIMER Structure */ - __O uint32_t TASKS_START; /*!< Start Timer */ - __O uint32_t TASKS_STOP; /*!< Stop Timer */ - __O uint32_t TASKS_COUNT; /*!< Increment Timer (Counter mode only) */ - __O uint32_t TASKS_CLEAR; /*!< Clear time */ - __O uint32_t TASKS_SHUTDOWN; /*!< Deprecated register - Shut down timer */ - __I uint32_t RESERVED0[11]; - __O uint32_t TASKS_CAPTURE[6]; /*!< Description collection[0]: Capture Timer value to CC[0] register */ - __I uint32_t RESERVED1[58]; - __IO uint32_t EVENTS_COMPARE[6]; /*!< Description collection[0]: Compare event on CC[0] match */ - __I uint32_t RESERVED2[42]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED3[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED4[126]; - __IO uint32_t MODE; /*!< Timer mode selection */ - __IO uint32_t BITMODE; /*!< Configure the number of bits used by the TIMER */ - __I uint32_t RESERVED5; - __IO uint32_t PRESCALER; /*!< Timer prescaler register */ - __I uint32_t RESERVED6[11]; - __IO uint32_t CC[6]; /*!< Description collection[0]: Capture/Compare register 0 */ -} NRF_TIMER_Type; +typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ + __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ + __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ + __IM uint32_t RESERVED[11]; + __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[0]: Capture Timer value + to CC[0] register */ + __IM uint32_t RESERVED1[58]; + __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[0]: Compare event on CC[0] + match */ + __IM uint32_t RESERVED2[42]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED3[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[126]; + __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ + __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ + __IM uint32_t RESERVED5; + __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[0]: Capture/Compare register + 0 */ +} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ -/* ================================================================================ */ -/* ================ RTC ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ RTC0 ================ */ +/* =========================================================================================================================== */ /** - * @brief Real time counter 0 (RTC) + * @brief Real time counter 0 (RTC0) */ -typedef struct { /*!< RTC Structure */ - __O uint32_t TASKS_START; /*!< Start RTC COUNTER */ - __O uint32_t TASKS_STOP; /*!< Stop RTC COUNTER */ - __O uint32_t TASKS_CLEAR; /*!< Clear RTC COUNTER */ - __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFF0 */ - __I uint32_t RESERVED0[60]; - __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment */ - __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow */ - __I uint32_t RESERVED1[14]; - __IO uint32_t EVENTS_COMPARE[4]; /*!< Description collection[0]: Compare event on CC[0] match */ - __I uint32_t RESERVED2[109]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[13]; - __IO uint32_t EVTEN; /*!< Enable or disable event routing */ - __IO uint32_t EVTENSET; /*!< Enable event routing */ - __IO uint32_t EVTENCLR; /*!< Disable event routing */ - __I uint32_t RESERVED4[110]; - __I uint32_t COUNTER; /*!< Current COUNTER value */ - __IO uint32_t PRESCALER; /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must - be written when RTC is stopped */ - __I uint32_t RESERVED5[13]; - __IO uint32_t CC[4]; /*!< Description collection[0]: Compare register 0 */ -} NRF_RTC_Type; +typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ + __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ + __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ + __IM uint32_t RESERVED1[14]; + __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[0]: Compare event on CC[0] + match */ + __IM uint32_t RESERVED2[109]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[13]; + __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ + __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ + __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ + __IM uint32_t RESERVED4[110]; + __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ + __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu + t be written when RTC is stopped */ + __IM uint32_t RESERVED5[13]; + __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[0]: Compare register 0 */ +} NRF_RTC_Type; /*!< Size = 1360 (0x550) */ -/* ================================================================================ */ -/* ================ TEMP ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ TEMP ================ */ +/* =========================================================================================================================== */ /** * @brief Temperature Sensor (TEMP) */ -typedef struct { /*!< TEMP Structure */ - __O uint32_t TASKS_START; /*!< Start temperature measurement */ - __O uint32_t TASKS_STOP; /*!< Stop temperature measurement */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready */ - __I uint32_t RESERVED1[128]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[127]; - __I int32_t TEMP; /*!< Temperature in degC (0.25deg steps) */ - __I uint32_t RESERVED3[5]; - __IO uint32_t A0; /*!< Slope of 1st piece wise linear function */ - __IO uint32_t A1; /*!< Slope of 2nd piece wise linear function */ - __IO uint32_t A2; /*!< Slope of 3rd piece wise linear function */ - __IO uint32_t A3; /*!< Slope of 4th piece wise linear function */ - __IO uint32_t A4; /*!< Slope of 5th piece wise linear function */ - __IO uint32_t A5; /*!< Slope of 6th piece wise linear function */ - __I uint32_t RESERVED4[2]; - __IO uint32_t B0; /*!< y-intercept of 1st piece wise linear function */ - __IO uint32_t B1; /*!< y-intercept of 2nd piece wise linear function */ - __IO uint32_t B2; /*!< y-intercept of 3rd piece wise linear function */ - __IO uint32_t B3; /*!< y-intercept of 4th piece wise linear function */ - __IO uint32_t B4; /*!< y-intercept of 5th piece wise linear function */ - __IO uint32_t B5; /*!< y-intercept of 6th piece wise linear function */ - __I uint32_t RESERVED5[2]; - __IO uint32_t T0; /*!< End point of 1st piece wise linear function */ - __IO uint32_t T1; /*!< End point of 2nd piece wise linear function */ - __IO uint32_t T2; /*!< End point of 3rd piece wise linear function */ - __IO uint32_t T3; /*!< End point of 4th piece wise linear function */ - __IO uint32_t T4; /*!< End point of 5th piece wise linear function */ -} NRF_TEMP_Type; +typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[127]; + __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ + __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ + __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ + __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ + __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ + __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ + __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ + __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ + __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ + __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ + __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ + __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ + __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ + __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ + __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ +} NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ -/* ================================================================================ */ -/* ================ RNG ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ RNG ================ */ +/* =========================================================================================================================== */ /** * @brief Random Number Generator (RNG) */ -typedef struct { /*!< RNG Structure */ - __O uint32_t TASKS_START; /*!< Task starting the random number generator */ - __O uint32_t TASKS_STOP; /*!< Task stopping the random number generator */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_VALRDY; /*!< Event being generated for every new random number written to - the VALUE register */ - __I uint32_t RESERVED1[63]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[126]; - __IO uint32_t CONFIG; /*!< Configuration register */ - __I uint32_t VALUE; /*!< Output random number */ -} NRF_RNG_Type; +typedef struct { /*!< (@ 0x4000D000) RNG Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number + written to the VALUE register */ + __IM uint32_t RESERVED1[63]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[126]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ +} NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ -/* ================================================================================ */ -/* ================ ECB ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ ECB ================ */ +/* =========================================================================================================================== */ /** * @brief AES ECB Mode Encryption (ECB) */ -typedef struct { /*!< ECB Structure */ - __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt */ - __O uint32_t TASKS_STOPECB; /*!< Abort a possible executing ECB operation */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete */ - __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted because of a STOPECB task or due to - an error */ - __I uint32_t RESERVED1[127]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[126]; - __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointers */ -} NRF_ECB_Type; +typedef struct { /*!< (@ 0x4000E000) ECB Structure */ + __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ + __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ + __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB + task or due to an error */ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ +} NRF_ECB_Type; /*!< Size = 1288 (0x508) */ -/* ================================================================================ */ -/* ================ CCM ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ CCM ================ */ +/* =========================================================================================================================== */ /** * @brief AES CCM Mode Encryption (CCM) */ -typedef struct { /*!< CCM Structure */ - __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by - itself when completed. */ - __O uint32_t TASKS_CRYPT; /*!< Start encryption/decryption. This operation will stop by itself - when completed. */ - __O uint32_t TASKS_STOP; /*!< Stop encryption/decryption */ - __I uint32_t RESERVED0[61]; - __IO uint32_t EVENTS_ENDKSGEN; /*!< Key-stream generation complete */ - __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt complete */ - __IO uint32_t EVENTS_ERROR; /*!< CCM error event */ - __I uint32_t RESERVED1[61]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[61]; - __I uint32_t MICSTATUS; /*!< MIC check result */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< Enable */ - __IO uint32_t MODE; /*!< Operation mode */ - __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector */ - __IO uint32_t INPTR; /*!< Input pointer */ - __IO uint32_t OUTPTR; /*!< Output pointer */ - __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */ -} NRF_CCM_Type; +typedef struct { /*!< (@ 0x4000F000) CCM Structure */ + __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation + will stop by itself when completed. */ + __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will + stop by itself when completed. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ + __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) CCM error event */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ + __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and + NONCE vector */ + __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ + __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ +} NRF_CCM_Type; /*!< Size = 1304 (0x518) */ -/* ================================================================================ */ -/* ================ AAR ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ AAR ================ */ +/* =========================================================================================================================== */ /** * @brief Accelerated Address Resolver (AAR) */ -typedef struct { /*!< AAR Structure */ - __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK - data structure */ - __I uint32_t RESERVED0; - __O uint32_t TASKS_STOP; /*!< Stop resolving addresses */ - __I uint32_t RESERVED1[61]; - __IO uint32_t EVENTS_END; /*!< Address resolution procedure complete */ - __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved */ - __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved */ - __I uint32_t RESERVED2[126]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[61]; - __I uint32_t STATUS; /*!< Resolution status */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< Enable AAR */ - __IO uint32_t NIRK; /*!< Number of IRKs */ - __IO uint32_t IRKPTR; /*!< Pointer to IRK data structure */ - __I uint32_t RESERVED5; - __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address */ - __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */ -} NRF_AAR_Type; +typedef struct { /*!< (@ 0x4000F000) AAR Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified + in the IRK data structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ + __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ + __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ + __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ + __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ + __IM uint32_t RESERVED5; + __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ +} NRF_AAR_Type; /*!< Size = 1304 (0x518) */ -/* ================================================================================ */ -/* ================ WDT ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ /** * @brief Watchdog Timer (WDT) */ -typedef struct { /*!< WDT Structure */ - __O uint32_t TASKS_START; /*!< Start the watchdog */ - __I uint32_t RESERVED0[63]; - __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout */ - __I uint32_t RESERVED1[128]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[61]; - __I uint32_t RUNSTATUS; /*!< Run status */ - __I uint32_t REQSTATUS; /*!< Request status */ - __I uint32_t RESERVED3[63]; - __IO uint32_t CRV; /*!< Counter reload value */ - __IO uint32_t RREN; /*!< Enable register for reload request registers */ - __IO uint32_t CONFIG; /*!< Configuration register */ - __I uint32_t RESERVED4[60]; - __O uint32_t RR[8]; /*!< Description collection[0]: Reload request 0 */ -} NRF_WDT_Type; +typedef struct { /*!< (@ 0x40010000) WDT Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ + __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ + __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ + __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ + __IM uint32_t RESERVED4[60]; + __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[0]: Reload request 0 */ +} NRF_WDT_Type; /*!< Size = 1568 (0x620) */ -/* ================================================================================ */ -/* ================ QDEC ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ QDEC ================ */ +/* =========================================================================================================================== */ /** * @brief Quadrature Decoder (QDEC) */ -typedef struct { /*!< QDEC Structure */ - __O uint32_t TASKS_START; /*!< Task starting the quadrature decoder */ - __O uint32_t TASKS_STOP; /*!< Task stopping the quadrature decoder */ - __O uint32_t TASKS_READCLRACC; /*!< Read and clear ACC and ACCDBL */ - __O uint32_t TASKS_RDCLRACC; /*!< Read and clear ACC */ - __O uint32_t TASKS_RDCLRDBL; /*!< Read and clear ACCDBL */ - __I uint32_t RESERVED0[59]; - __IO uint32_t EVENTS_SAMPLERDY; /*!< Event being generated for every new sample value written to - the SAMPLE register */ - __IO uint32_t EVENTS_REPORTRDY; /*!< Non-null report ready */ - __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow */ - __IO uint32_t EVENTS_DBLRDY; /*!< Double displacement(s) detected */ - __IO uint32_t EVENTS_STOPPED; /*!< QDEC has been stopped */ - __I uint32_t RESERVED1[59]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[125]; - __IO uint32_t ENABLE; /*!< Enable the quadrature decoder */ - __IO uint32_t LEDPOL; /*!< LED output pin polarity */ - __IO uint32_t SAMPLEPER; /*!< Sample period */ - __I int32_t SAMPLE; /*!< Motion sample value */ - __IO uint32_t REPORTPER; /*!< Number of samples to be taken before REPORTRDY and DBLRDY events - can be generated */ - __I int32_t ACC; /*!< Register accumulating the valid transitions */ - __I int32_t ACCREAD; /*!< Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC - task */ - QDEC_PSEL_Type PSEL; /*!< Unspecified */ - __IO uint32_t DBFEN; /*!< Enable input debounce filters */ - __I uint32_t RESERVED4[5]; - __IO uint32_t LEDPRE; /*!< Time period the LED is switched ON prior to sampling */ - __I uint32_t ACCDBL; /*!< Register accumulating the number of detected double transitions */ - __I uint32_t ACCDBLREAD; /*!< Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL - task */ -} NRF_QDEC_Type; +typedef struct { /*!< (@ 0x40012000) QDEC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ + __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ + __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ + __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ + __IM uint32_t RESERVED[59]; + __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value + written to the SAMPLE register */ + __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ + __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ + __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ + __IM uint32_t RESERVED1[59]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ + __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ + __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ + __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ + __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY + and DBLRDY events can be generated */ + __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ + __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the + READCLRACC or RDCLRACC task */ + __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ + __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ + __IM uint32_t RESERVED4[5]; + __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ + __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected + double transitions */ + __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC + or RDCLRDBL task */ +} NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ -/* ================================================================================ */ -/* ================ COMP ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ COMP ================ */ +/* =========================================================================================================================== */ /** * @brief Comparator (COMP) */ -typedef struct { /*!< COMP Structure */ - __O uint32_t TASKS_START; /*!< Start comparator */ - __O uint32_t TASKS_STOP; /*!< Stop comparator */ - __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */ - __I uint32_t RESERVED0[61]; - __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid */ - __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */ - __IO uint32_t EVENTS_UP; /*!< Upward crossing */ - __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */ - __I uint32_t RESERVED1[60]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED2[63]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[61]; - __I uint32_t RESULT; /*!< Compare result */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< COMP enable */ - __IO uint32_t PSEL; /*!< Pin select */ - __IO uint32_t REFSEL; /*!< Reference source select */ - __IO uint32_t EXTREFSEL; /*!< External reference select */ - __I uint32_t RESERVED5[8]; - __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit */ - __IO uint32_t MODE; /*!< Mode configuration */ - __IO uint32_t HYST; /*!< Comparator hysteresis enable */ - __IO uint32_t ISOURCE; /*!< Current source select on analog input */ -} NRF_COMP_Type; +typedef struct { /*!< (@ 0x40013000) COMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ + __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ + __IOM uint32_t ISOURCE; /*!< (@ 0x0000053C) Current source select on analog input */ +} NRF_COMP_Type; /*!< Size = 1344 (0x540) */ -/* ================================================================================ */ -/* ================ LPCOMP ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ LPCOMP ================ */ +/* =========================================================================================================================== */ /** * @brief Low Power Comparator (LPCOMP) */ -typedef struct { /*!< LPCOMP Structure */ - __O uint32_t TASKS_START; /*!< Start comparator */ - __O uint32_t TASKS_STOP; /*!< Stop comparator */ - __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */ - __I uint32_t RESERVED0[61]; - __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid */ - __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */ - __IO uint32_t EVENTS_UP; /*!< Upward crossing */ - __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */ - __I uint32_t RESERVED1[60]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[61]; - __I uint32_t RESULT; /*!< Compare result */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< Enable LPCOMP */ - __IO uint32_t PSEL; /*!< Input pin select */ - __IO uint32_t REFSEL; /*!< Reference select */ - __IO uint32_t EXTREFSEL; /*!< External reference select */ - __I uint32_t RESERVED5[4]; - __IO uint32_t ANADETECT; /*!< Analog detect configuration */ - __I uint32_t RESERVED6[5]; - __IO uint32_t HYST; /*!< Comparator hysteresis enable */ -} NRF_LPCOMP_Type; +typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED5[4]; + __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ + __IM uint32_t RESERVED6[5]; + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ +} NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ -/* ================================================================================ */ -/* ================ SWI ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ SWI0 ================ */ +/* =========================================================================================================================== */ /** - * @brief Software interrupt 0 (SWI) + * @brief Software interrupt 0 (SWI0) */ -typedef struct { /*!< SWI Structure */ - __I uint32_t UNUSED; /*!< Unused. */ -} NRF_SWI_Type; +typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ + __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ +} NRF_SWI_Type; /*!< Size = 4 (0x4) */ -/* ================================================================================ */ -/* ================ EGU ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ EGU0 ================ */ +/* =========================================================================================================================== */ /** - * @brief Event Generator Unit 0 (EGU) + * @brief Event Generator Unit 0 (EGU0) */ -typedef struct { /*!< EGU Structure */ - __O uint32_t TASKS_TRIGGER[16]; /*!< Description collection[0]: Trigger 0 for triggering the corresponding - TRIGGERED[0] event */ - __I uint32_t RESERVED0[48]; - __IO uint32_t EVENTS_TRIGGERED[16]; /*!< Description collection[0]: Event number 0 generated by triggering - the corresponding TRIGGER[0] task */ - __I uint32_t RESERVED1[112]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ -} NRF_EGU_Type; +typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ + __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[0]: Trigger 0 for triggering + the corresponding TRIGGERED[0] event */ + __IM uint32_t RESERVED[48]; + __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[0]: Event number 0 generated + by triggering the corresponding TRIGGER[0] + task */ + __IM uint32_t RESERVED1[112]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ +} NRF_EGU_Type; /*!< Size = 780 (0x30c) */ -/* ================================================================================ */ -/* ================ PWM ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ PWM0 ================ */ +/* =========================================================================================================================== */ /** - * @brief Pulse Width Modulation Unit 0 (PWM) + * @brief Pulse Width Modulation Unit 0 (PWM0) */ -typedef struct { /*!< PWM Structure */ - __I uint32_t RESERVED0; - __O uint32_t TASKS_STOP; /*!< Stops PWM pulse generation on all channels at the end of current - PWM period, and stops sequence playback */ - __O uint32_t TASKS_SEQSTART[2]; /*!< Description collection[0]: Loads the first PWM value on all - enabled channels from sequence 0, and starts playing that sequence - at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes - PWM generation to start it was not running. */ - __O uint32_t TASKS_NEXTSTEP; /*!< Steps by one value in the current sequence on all enabled channels - if DECODER.MODE=NextStep. Does not cause PWM generation to start - it was not running. */ - __I uint32_t RESERVED1[60]; - __IO uint32_t EVENTS_STOPPED; /*!< Response to STOP task, emitted when PWM pulses are no longer - generated */ - __IO uint32_t EVENTS_SEQSTARTED[2]; /*!< Description collection[0]: First PWM period started on sequence - 0 */ - __IO uint32_t EVENTS_SEQEND[2]; /*!< Description collection[0]: Emitted at end of every sequence - 0, when last value from RAM has been applied to wave counter */ - __IO uint32_t EVENTS_PWMPERIODEND; /*!< Emitted at the end of each PWM period */ - __IO uint32_t EVENTS_LOOPSDONE; /*!< Concatenated sequences have been played the amount of times - defined in LOOP.CNT */ - __I uint32_t RESERVED2[56]; - __IO uint32_t SHORTS; /*!< Shortcut register */ - __I uint32_t RESERVED3[63]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED4[125]; - __IO uint32_t ENABLE; /*!< PWM module enable register */ - __IO uint32_t MODE; /*!< Selects operating mode of the wave counter */ - __IO uint32_t COUNTERTOP; /*!< Value up to which the pulse generator counter counts */ - __IO uint32_t PRESCALER; /*!< Configuration for PWM_CLK */ - __IO uint32_t DECODER; /*!< Configuration of the decoder */ - __IO uint32_t LOOP; /*!< Amount of playback of a loop */ - __I uint32_t RESERVED5[2]; - PWM_SEQ_Type SEQ[2]; /*!< Unspecified */ - PWM_PSEL_Type PSEL; /*!< Unspecified */ -} NRF_PWM_Type; +typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at + the end of current PWM period, and stops + sequence playback */ + __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[0]: Loads the first PWM + value on all enabled channels from sequence + 0, and starts playing that sequence at the + rate defined in SEQ[0]REFRESH and/or DECODER.MODE. + Causes PWM generation to start it was not + running. */ + __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on + all enabled channels if DECODER.MODE=NextStep. + Does not cause PWM generation to start it + was not running. */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses + are no longer generated */ + __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[0]: First PWM period started + on sequence 0 */ + __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[0]: Emitted at end of + every sequence 0, when last value from RAM + has been applied to wave counter */ + __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ + __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount + of times defined in LOOP.CNT */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ + __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter + counts */ + __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ + __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ + __IOM uint32_t LOOP; /*!< (@ 0x00000514) Amount of playback of a loop */ + __IM uint32_t RESERVED5[2]; + __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ + __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ +} NRF_PWM_Type; /*!< Size = 1392 (0x570) */ -/* ================================================================================ */ -/* ================ PDM ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ /** * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) */ -typedef struct { /*!< PDM Structure */ - __O uint32_t TASKS_START; /*!< Starts continuous PDM transfer */ - __O uint32_t TASKS_STOP; /*!< Stops PDM transfer */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_STARTED; /*!< PDM transfer has started */ - __IO uint32_t EVENTS_STOPPED; /*!< PDM transfer has finished */ - __IO uint32_t EVENTS_END; /*!< The PDM has written the last sample specified by SAMPLE.MAXCNT - (or the last sample after a STOP task has been received) to - Data RAM */ - __I uint32_t RESERVED1[125]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED2[125]; - __IO uint32_t ENABLE; /*!< PDM module enable register */ - __IO uint32_t PDMCLKCTRL; /*!< PDM clock generator control */ - __IO uint32_t MODE; /*!< Defines the routing of the connected PDM microphones' signals */ - __I uint32_t RESERVED3[3]; - __IO uint32_t GAINL; /*!< Left output gain adjustment */ - __IO uint32_t GAINR; /*!< Right output gain adjustment */ - __I uint32_t RESERVED4[8]; - PDM_PSEL_Type PSEL; /*!< Unspecified */ - __I uint32_t RESERVED5[6]; - PDM_SAMPLE_Type SAMPLE; /*!< Unspecified */ -} NRF_PDM_Type; +typedef struct { /*!< (@ 0x4001D000) PDM Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified + by SAMPLE.MAXCNT (or the last sample after + a STOP task has been received) to Data RAM */ + __IM uint32_t RESERVED1[125]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ + __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ + __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' + signals */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ + __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ + __IM uint32_t RESERVED4[8]; + __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED5[6]; + __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ +} NRF_PDM_Type; /*!< Size = 1384 (0x568) */ -/* ================================================================================ */ -/* ================ NVMC ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ NVMC ================ */ +/* =========================================================================================================================== */ /** * @brief Non Volatile Memory Controller (NVMC) */ -typedef struct { /*!< NVMC Structure */ - __I uint32_t RESERVED0[256]; - __I uint32_t READY; /*!< Ready flag */ - __I uint32_t RESERVED1[64]; - __IO uint32_t CONFIG; /*!< Configuration register */ +typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ + __IM uint32_t RESERVED[256]; + __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ + __IM uint32_t RESERVED1[64]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ union { - __IO uint32_t ERASEPCR1; /*!< Deprecated register - Register for erasing a page in Code area. - Equivalent to ERASEPAGE. */ - __IO uint32_t ERASEPAGE; /*!< Register for erasing a page in Code area */ + __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in Code area */ + __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a + page in Code area. Equivalent to ERASEPAGE. */ }; - __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory */ - __IO uint32_t ERASEPCR0; /*!< Deprecated register - Register for erasing a page in Code area. - Equivalent to ERASEPAGE. */ - __IO uint32_t ERASEUICR; /*!< Register for erasing User Information Configuration Registers */ - __I uint32_t RESERVED2[10]; - __IO uint32_t ICACHECNF; /*!< I-Code cache configuration register. */ - __I uint32_t RESERVED3; - __IO uint32_t IHIT; /*!< I-Code cache hit counter. */ - __IO uint32_t IMISS; /*!< I-Code cache miss counter. */ -} NRF_NVMC_Type; + __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ + __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a + page in Code area. Equivalent to ERASEPAGE. */ + __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing User Information Configuration + Registers */ + __IM uint32_t RESERVED2[10]; + __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-Code cache configuration register. */ + __IM uint32_t RESERVED3; + __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-Code cache hit counter. */ + __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-Code cache miss counter. */ +} NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ -/* ================================================================================ */ -/* ================ PPI ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ PPI ================ */ +/* =========================================================================================================================== */ /** * @brief Programmable Peripheral Interconnect (PPI) */ -typedef struct { /*!< PPI Structure */ - PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< Channel group tasks */ - __I uint32_t RESERVED0[308]; - __IO uint32_t CHEN; /*!< Channel enable register */ - __IO uint32_t CHENSET; /*!< Channel enable set register */ - __IO uint32_t CHENCLR; /*!< Channel enable clear register */ - __I uint32_t RESERVED1; - PPI_CH_Type CH[20]; /*!< PPI Channel */ - __I uint32_t RESERVED2[148]; - __IO uint32_t CHG[6]; /*!< Description collection[0]: Channel group 0 */ - __I uint32_t RESERVED3[62]; - PPI_FORK_Type FORK[32]; /*!< Fork */ -} NRF_PPI_Type; +typedef struct { /*!< (@ 0x4001F000) PPI Structure */ + __IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ + __IM uint32_t RESERVED[308]; + __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ + __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ + __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ + __IM uint32_t RESERVED1; + __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ + __IM uint32_t RESERVED2[148]; + __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[0]: Channel group 0 */ + __IM uint32_t RESERVED3[62]; + __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ +} NRF_PPI_Type; /*!< Size = 2448 (0x990) */ -/* ================================================================================ */ -/* ================ MWU ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ MWU ================ */ +/* =========================================================================================================================== */ /** * @brief Memory Watch Unit (MWU) */ -typedef struct { /*!< MWU Structure */ - __I uint32_t RESERVED0[64]; - MWU_EVENTS_REGION_Type EVENTS_REGION[4]; /*!< Unspecified */ - __I uint32_t RESERVED1[16]; - MWU_EVENTS_PREGION_Type EVENTS_PREGION[2]; /*!< Unspecified */ - __I uint32_t RESERVED2[100]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[5]; - __IO uint32_t NMIEN; /*!< Enable or disable non-maskable interrupt */ - __IO uint32_t NMIENSET; /*!< Enable non-maskable interrupt */ - __IO uint32_t NMIENCLR; /*!< Disable non-maskable interrupt */ - __I uint32_t RESERVED4[53]; - MWU_PERREGION_Type PERREGION[2]; /*!< Unspecified */ - __I uint32_t RESERVED5[64]; - __IO uint32_t REGIONEN; /*!< Enable/disable regions watch */ - __IO uint32_t REGIONENSET; /*!< Enable regions watch */ - __IO uint32_t REGIONENCLR; /*!< Disable regions watch */ - __I uint32_t RESERVED6[57]; - MWU_REGION_Type REGION[4]; /*!< Unspecified */ - __I uint32_t RESERVED7[32]; - MWU_PREGION_Type PREGION[2]; /*!< Unspecified */ -} NRF_MWU_Type; +typedef struct { /*!< (@ 0x40020000) MWU Structure */ + __IM uint32_t RESERVED[64]; + __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Unspecified */ + __IM uint32_t RESERVED1[16]; + __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Unspecified */ + __IM uint32_t RESERVED2[100]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable non-maskable interrupt */ + __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable non-maskable interrupt */ + __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable non-maskable interrupt */ + __IM uint32_t RESERVED4[53]; + __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */ + __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */ + __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */ + __IM uint32_t RESERVED6[57]; + __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */ + __IM uint32_t RESERVED7[32]; + __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */ +} NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */ -/* ================================================================================ */ -/* ================ I2S ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ I2S ================ */ +/* =========================================================================================================================== */ /** * @brief Inter-IC Sound (I2S) */ -typedef struct { /*!< I2S Structure */ - __O uint32_t TASKS_START; /*!< Starts continuous I2S transfer. Also starts MCK generator when - this is enabled. */ - __O uint32_t TASKS_STOP; /*!< Stops I2S transfer. Also stops MCK generator. Triggering this - task will cause the {event:STOPPED} event to be generated. */ - __I uint32_t RESERVED0[63]; - __IO uint32_t EVENTS_RXPTRUPD; /*!< The RXD.PTR register has been copied to internal double-buffers. - When the I2S module is started and RX is enabled, this event - will be generated for every RXTXD.MAXCNT words that are received - on the SDIN pin. */ - __IO uint32_t EVENTS_STOPPED; /*!< I2S transfer stopped. */ - __I uint32_t RESERVED1[2]; - __IO uint32_t EVENTS_TXPTRUPD; /*!< The TDX.PTR register has been copied to internal double-buffers. - When the I2S module is started and TX is enabled, this event - will be generated for every RXTXD.MAXCNT words that are sent - on the SDOUT pin. */ - __I uint32_t RESERVED2[122]; - __IO uint32_t INTEN; /*!< Enable or disable interrupt */ - __IO uint32_t INTENSET; /*!< Enable interrupt */ - __IO uint32_t INTENCLR; /*!< Disable interrupt */ - __I uint32_t RESERVED3[125]; - __IO uint32_t ENABLE; /*!< Enable I2S module. */ - I2S_CONFIG_Type CONFIG; /*!< Unspecified */ - __I uint32_t RESERVED4[3]; - I2S_RXD_Type RXD; /*!< Unspecified */ - __I uint32_t RESERVED5; - I2S_TXD_Type TXD; /*!< Unspecified */ - __I uint32_t RESERVED6[3]; - I2S_RXTXD_Type RXTXD; /*!< Unspecified */ - __I uint32_t RESERVED7[3]; - I2S_PSEL_Type PSEL; /*!< Unspecified */ -} NRF_I2S_Type; +typedef struct { /*!< (@ 0x40025000) I2S Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK + generator when this is enabled. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. + Triggering this task will cause the {event:STOPPED} + event to be generated. */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal + double-buffers. When the I2S module is started + and RX is enabled, this event will be generated + for every RXTXD.MAXCNT words that are received + on the SDIN pin. */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal + double-buffers. When the I2S module is started + and TX is enabled, this event will be generated + for every RXTXD.MAXCNT words that are sent + on the SDOUT pin. */ + __IM uint32_t RESERVED2[122]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ + __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ + __IM uint32_t RESERVED4[3]; + __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ + __IM uint32_t RESERVED5; + __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED6[3]; + __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ + __IM uint32_t RESERVED7[3]; + __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ +} NRF_I2S_Type; /*!< Size = 1396 (0x574) */ -/* ================================================================================ */ -/* ================ FPU ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ FPU ================ */ +/* =========================================================================================================================== */ /** * @brief FPU (FPU) */ -typedef struct { /*!< FPU Structure */ - __I uint32_t UNUSED; /*!< Unused. */ -} NRF_FPU_Type; +typedef struct { /*!< (@ 0x40026000) FPU Structure */ + __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ +} NRF_FPU_Type; /*!< Size = 4 (0x4) */ -/* ================================================================================ */ -/* ================ GPIO ================ */ -/* ================================================================================ */ + +/* =========================================================================================================================== */ +/* ================ P0 ================ */ +/* =========================================================================================================================== */ /** - * @brief GPIO Port 1 (GPIO) + * @brief GPIO Port 1 (P0) */ -typedef struct { /*!< GPIO Structure */ - __I uint32_t RESERVED0[321]; - __IO uint32_t OUT; /*!< Write GPIO port */ - __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port */ - __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port */ - __I uint32_t IN; /*!< Read GPIO port */ - __IO uint32_t DIR; /*!< Direction of GPIO pins */ - __IO uint32_t DIRSET; /*!< DIR set register */ - __IO uint32_t DIRCLR; /*!< DIR clear register */ - __IO uint32_t LATCH; /*!< Latch register indicating what GPIO pins that have met the criteria - set in the PIN_CNF[n].SENSE registers */ - __IO uint32_t DETECTMODE; /*!< Select between default DETECT signal behaviour and LDETECT mode */ - __I uint32_t RESERVED1[118]; - __IO uint32_t PIN_CNF[32]; /*!< Description collection[0]: Configuration of GPIO pins */ -} NRF_GPIO_Type; +typedef struct { /*!< (@ 0x50000000) P0 Structure */ + __IM uint32_t RESERVED[321]; + __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ + __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ + __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ + __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ + __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ + __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ + __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ + __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that + have met the criteria set in the PIN_CNF[n].SENSE + registers */ + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour + and LDETECT mode */ + __IM uint32_t RESERVED1[118]; + __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[0]: Configuration of GPIO + pins */ +} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ -/* -------------------- End of section using anonymous unions ------------------- */ -#if defined(__CC_ARM) - #pragma pop -#elif defined(__ICCARM__) - /* leave anonymous unions enabled */ -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning restore -#else - #warning Not supported compiler type -#endif +/** @} */ /* End of group Device_Peripheral_peripherals */ +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ -/* ================================================================================ */ -/* ================ Peripheral memory map ================ */ -/* ================================================================================ */ +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ -#define NRF_FICR_BASE 0x10000000UL -#define NRF_UICR_BASE 0x10001000UL -#define NRF_BPROT_BASE 0x40000000UL -#define NRF_POWER_BASE 0x40000000UL -#define NRF_CLOCK_BASE 0x40000000UL -#define NRF_AMLI_BASE 0x40000000UL -#define NRF_RADIO_BASE 0x40001000UL -#define NRF_UARTE0_BASE 0x40002000UL -#define NRF_UART0_BASE 0x40002000UL -#define NRF_SPIM0_BASE 0x40003000UL -#define NRF_SPIS0_BASE 0x40003000UL -#define NRF_TWIM0_BASE 0x40003000UL -#define NRF_TWIS0_BASE 0x40003000UL -#define NRF_SPI0_BASE 0x40003000UL -#define NRF_TWI0_BASE 0x40003000UL -#define NRF_SPIM1_BASE 0x40004000UL -#define NRF_SPIS1_BASE 0x40004000UL -#define NRF_TWIM1_BASE 0x40004000UL -#define NRF_TWIS1_BASE 0x40004000UL -#define NRF_SPI1_BASE 0x40004000UL -#define NRF_TWI1_BASE 0x40004000UL -#define NRF_NFCT_BASE 0x40005000UL -#define NRF_GPIOTE_BASE 0x40006000UL -#define NRF_SAADC_BASE 0x40007000UL -#define NRF_TIMER0_BASE 0x40008000UL -#define NRF_TIMER1_BASE 0x40009000UL -#define NRF_TIMER2_BASE 0x4000A000UL -#define NRF_RTC0_BASE 0x4000B000UL -#define NRF_TEMP_BASE 0x4000C000UL -#define NRF_RNG_BASE 0x4000D000UL -#define NRF_ECB_BASE 0x4000E000UL -#define NRF_CCM_BASE 0x4000F000UL -#define NRF_AAR_BASE 0x4000F000UL -#define NRF_WDT_BASE 0x40010000UL -#define NRF_RTC1_BASE 0x40011000UL -#define NRF_QDEC_BASE 0x40012000UL -#define NRF_COMP_BASE 0x40013000UL -#define NRF_LPCOMP_BASE 0x40013000UL -#define NRF_SWI0_BASE 0x40014000UL -#define NRF_EGU0_BASE 0x40014000UL -#define NRF_SWI1_BASE 0x40015000UL -#define NRF_EGU1_BASE 0x40015000UL -#define NRF_SWI2_BASE 0x40016000UL -#define NRF_EGU2_BASE 0x40016000UL -#define NRF_SWI3_BASE 0x40017000UL -#define NRF_EGU3_BASE 0x40017000UL -#define NRF_SWI4_BASE 0x40018000UL -#define NRF_EGU4_BASE 0x40018000UL -#define NRF_SWI5_BASE 0x40019000UL -#define NRF_EGU5_BASE 0x40019000UL -#define NRF_TIMER3_BASE 0x4001A000UL -#define NRF_TIMER4_BASE 0x4001B000UL -#define NRF_PWM0_BASE 0x4001C000UL -#define NRF_PDM_BASE 0x4001D000UL -#define NRF_NVMC_BASE 0x4001E000UL -#define NRF_PPI_BASE 0x4001F000UL -#define NRF_MWU_BASE 0x40020000UL -#define NRF_PWM1_BASE 0x40021000UL -#define NRF_PWM2_BASE 0x40022000UL -#define NRF_SPIM2_BASE 0x40023000UL -#define NRF_SPIS2_BASE 0x40023000UL -#define NRF_SPI2_BASE 0x40023000UL -#define NRF_RTC2_BASE 0x40024000UL -#define NRF_I2S_BASE 0x40025000UL -#define NRF_FPU_BASE 0x40026000UL -#define NRF_P0_BASE 0x50000000UL +#define NRF_FICR_BASE 0x10000000UL +#define NRF_UICR_BASE 0x10001000UL +#define NRF_BPROT_BASE 0x40000000UL +#define NRF_POWER_BASE 0x40000000UL +#define NRF_CLOCK_BASE 0x40000000UL +#define NRF_RADIO_BASE 0x40001000UL +#define NRF_UARTE0_BASE 0x40002000UL +#define NRF_UART0_BASE 0x40002000UL +#define NRF_SPIM0_BASE 0x40003000UL +#define NRF_SPIS0_BASE 0x40003000UL +#define NRF_TWIM0_BASE 0x40003000UL +#define NRF_TWIS0_BASE 0x40003000UL +#define NRF_SPI0_BASE 0x40003000UL +#define NRF_TWI0_BASE 0x40003000UL +#define NRF_SPIM1_BASE 0x40004000UL +#define NRF_SPIS1_BASE 0x40004000UL +#define NRF_TWIM1_BASE 0x40004000UL +#define NRF_TWIS1_BASE 0x40004000UL +#define NRF_SPI1_BASE 0x40004000UL +#define NRF_TWI1_BASE 0x40004000UL +#define NRF_NFCT_BASE 0x40005000UL +#define NRF_GPIOTE_BASE 0x40006000UL +#define NRF_SAADC_BASE 0x40007000UL +#define NRF_TIMER0_BASE 0x40008000UL +#define NRF_TIMER1_BASE 0x40009000UL +#define NRF_TIMER2_BASE 0x4000A000UL +#define NRF_RTC0_BASE 0x4000B000UL +#define NRF_TEMP_BASE 0x4000C000UL +#define NRF_RNG_BASE 0x4000D000UL +#define NRF_ECB_BASE 0x4000E000UL +#define NRF_CCM_BASE 0x4000F000UL +#define NRF_AAR_BASE 0x4000F000UL +#define NRF_WDT_BASE 0x40010000UL +#define NRF_RTC1_BASE 0x40011000UL +#define NRF_QDEC_BASE 0x40012000UL +#define NRF_COMP_BASE 0x40013000UL +#define NRF_LPCOMP_BASE 0x40013000UL +#define NRF_SWI0_BASE 0x40014000UL +#define NRF_EGU0_BASE 0x40014000UL +#define NRF_SWI1_BASE 0x40015000UL +#define NRF_EGU1_BASE 0x40015000UL +#define NRF_SWI2_BASE 0x40016000UL +#define NRF_EGU2_BASE 0x40016000UL +#define NRF_SWI3_BASE 0x40017000UL +#define NRF_EGU3_BASE 0x40017000UL +#define NRF_SWI4_BASE 0x40018000UL +#define NRF_EGU4_BASE 0x40018000UL +#define NRF_SWI5_BASE 0x40019000UL +#define NRF_EGU5_BASE 0x40019000UL +#define NRF_TIMER3_BASE 0x4001A000UL +#define NRF_TIMER4_BASE 0x4001B000UL +#define NRF_PWM0_BASE 0x4001C000UL +#define NRF_PDM_BASE 0x4001D000UL +#define NRF_NVMC_BASE 0x4001E000UL +#define NRF_PPI_BASE 0x4001F000UL +#define NRF_MWU_BASE 0x40020000UL +#define NRF_PWM1_BASE 0x40021000UL +#define NRF_PWM2_BASE 0x40022000UL +#define NRF_SPIM2_BASE 0x40023000UL +#define NRF_SPIS2_BASE 0x40023000UL +#define NRF_SPI2_BASE 0x40023000UL +#define NRF_RTC2_BASE 0x40024000UL +#define NRF_I2S_BASE 0x40025000UL +#define NRF_FPU_BASE 0x40026000UL +#define NRF_P0_BASE 0x50000000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ -/* ================================================================================ */ -/* ================ Peripheral declaration ================ */ -/* ================================================================================ */ - -#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE) -#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE) -#define NRF_BPROT ((NRF_BPROT_Type *) NRF_BPROT_BASE) -#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE) -#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE) -#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE) -#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE) -#define NRF_UARTE0 ((NRF_UARTE_Type *) NRF_UARTE0_BASE) -#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE) -#define NRF_SPIM0 ((NRF_SPIM_Type *) NRF_SPIM0_BASE) -#define NRF_SPIS0 ((NRF_SPIS_Type *) NRF_SPIS0_BASE) -#define NRF_TWIM0 ((NRF_TWIM_Type *) NRF_TWIM0_BASE) -#define NRF_TWIS0 ((NRF_TWIS_Type *) NRF_TWIS0_BASE) -#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) -#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE) -#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE) -#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) -#define NRF_TWIM1 ((NRF_TWIM_Type *) NRF_TWIM1_BASE) -#define NRF_TWIS1 ((NRF_TWIS_Type *) NRF_TWIS1_BASE) -#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) -#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) -#define NRF_NFCT ((NRF_NFCT_Type *) NRF_NFCT_BASE) -#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) -#define NRF_SAADC ((NRF_SAADC_Type *) NRF_SAADC_BASE) -#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) -#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE) -#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE) -#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE) -#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE) -#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE) -#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE) -#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE) -#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE) -#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE) -#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) -#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) -#define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE) -#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) -#define NRF_SWI0 ((NRF_SWI_Type *) NRF_SWI0_BASE) -#define NRF_EGU0 ((NRF_EGU_Type *) NRF_EGU0_BASE) -#define NRF_SWI1 ((NRF_SWI_Type *) NRF_SWI1_BASE) -#define NRF_EGU1 ((NRF_EGU_Type *) NRF_EGU1_BASE) -#define NRF_SWI2 ((NRF_SWI_Type *) NRF_SWI2_BASE) -#define NRF_EGU2 ((NRF_EGU_Type *) NRF_EGU2_BASE) -#define NRF_SWI3 ((NRF_SWI_Type *) NRF_SWI3_BASE) -#define NRF_EGU3 ((NRF_EGU_Type *) NRF_EGU3_BASE) -#define NRF_SWI4 ((NRF_SWI_Type *) NRF_SWI4_BASE) -#define NRF_EGU4 ((NRF_EGU_Type *) NRF_EGU4_BASE) -#define NRF_SWI5 ((NRF_SWI_Type *) NRF_SWI5_BASE) -#define NRF_EGU5 ((NRF_EGU_Type *) NRF_EGU5_BASE) -#define NRF_TIMER3 ((NRF_TIMER_Type *) NRF_TIMER3_BASE) -#define NRF_TIMER4 ((NRF_TIMER_Type *) NRF_TIMER4_BASE) -#define NRF_PWM0 ((NRF_PWM_Type *) NRF_PWM0_BASE) -#define NRF_PDM ((NRF_PDM_Type *) NRF_PDM_BASE) -#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) -#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) -#define NRF_MWU ((NRF_MWU_Type *) NRF_MWU_BASE) -#define NRF_PWM1 ((NRF_PWM_Type *) NRF_PWM1_BASE) -#define NRF_PWM2 ((NRF_PWM_Type *) NRF_PWM2_BASE) -#define NRF_SPIM2 ((NRF_SPIM_Type *) NRF_SPIM2_BASE) -#define NRF_SPIS2 ((NRF_SPIS_Type *) NRF_SPIS2_BASE) -#define NRF_SPI2 ((NRF_SPI_Type *) NRF_SPI2_BASE) -#define NRF_RTC2 ((NRF_RTC_Type *) NRF_RTC2_BASE) -#define NRF_I2S ((NRF_I2S_Type *) NRF_I2S_BASE) -#define NRF_FPU ((NRF_FPU_Type *) NRF_FPU_BASE) -#define NRF_P0 ((NRF_GPIO_Type *) NRF_P0_BASE) +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ -/** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group nrf52 */ -/** @} */ /* End of group Nordic Semiconductor */ +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) +#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) +#define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) +#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) +#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) +#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) +#define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) +#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) +#define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) +#define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) +#define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) +#define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) +#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) +#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) +#define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) +#define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) +#define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) +#define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) +#define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) +#define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) +#define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) +#define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) +#define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) +#define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) +#define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) +#define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) +#define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) +#define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) +#define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) +#define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) +#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) +#define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) +#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) +#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) +#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) +#define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) +#define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) +#define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) +#define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) +#define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) +#define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) +#define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) +#define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) +#define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) +#define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) +#define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) +#define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) +#define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) +#define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) +#define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) +#define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) +#define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) +#define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) +#define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) +#define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) +#define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) +#define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) +#define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) +#define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) +#define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) +#define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) +#define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) +#define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) +#define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) +#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + #ifdef __cplusplus } #endif +#endif /* NRF52_H */ -#endif /* nrf52_H */ - +/** @} */ /* End of group nrf52 */ +/** @} */ /* End of group Nordic Semiconductor */ diff --git a/os/hal/ports/NRF5/NRF52832/nrf52_bitfields.h b/os/hal/ports/NRF5/NRF52832/nrf52_bitfields.h index ae959d4a..7bdf7742 100644 --- a/os/hal/ports/NRF5/NRF52832/nrf52_bitfields.h +++ b/os/hal/ports/NRF5/NRF52832/nrf52_bitfields.h @@ -1,32 +1,52 @@ -/* Copyright (c) 2015, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +/** @addtogroup Nordic Semiconductor + * @{ + */ + +/** @addtogroup nrf52 + * @{ + */ + #ifndef __NRF52_BITS_H #define __NRF52_BITS_H @@ -128,2292 +148,6 @@ #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ -/* Peripheral: AMLI */ -/* Description: AHB Multi-Layer Interface */ - -/* Register: AMLI_RAMPRI_CPU0 */ -/* Description: AHB bus master priority register for CPU0 */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_SPIS1 */ -/* Description: AHB bus master priority register for SPIM1, SPIS1, TWIM1 and TWIS1 */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_RADIO */ -/* Description: AHB bus master priority register for RADIO */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_ECB */ -/* Description: AHB bus master priority register for ECB */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_CCM */ -/* Description: AHB bus master priority register for CCM */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_AAR */ -/* Description: AHB bus master priority register for AAR */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_SAADC */ -/* Description: AHB bus master priority register for SAADC */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_SAADC_RAM7_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_SAADC_RAM6_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_SAADC_RAM5_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_SAADC_RAM4_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_SAADC_RAM3_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_SAADC_RAM2_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_SAADC_RAM1_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_SAADC_RAM0_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_UARTE */ -/* Description: AHB bus master priority register for UARTE */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_UARTE_RAM7_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_UARTE_RAM6_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_UARTE_RAM5_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_UARTE_RAM4_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_UARTE_RAM3_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_UARTE_RAM2_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_UARTE_RAM1_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_UARTE_RAM0_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_SERIAL0 */ -/* Description: AHB bus master priority register for SPIM0, SPIS0, TWIM0 and TWIS0 */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_SERIAL2 */ -/* Description: AHB bus master priority register for SPIM2 and SPIS2 */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_NFCT */ -/* Description: AHB bus master priority register for NFCT */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_NFCT_RAM7_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_NFCT_RAM6_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_NFCT_RAM5_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_NFCT_RAM4_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_NFCT_RAM3_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_NFCT_RAM2_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_NFCT_RAM1_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_NFCT_RAM0_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_I2S */ -/* Description: AHB bus master priority register for I2S */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_I2S_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_I2S_RAM7_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_I2S_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_I2S_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_I2S_RAM6_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_I2S_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_I2S_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_I2S_RAM5_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_I2S_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_I2S_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_I2S_RAM4_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_I2S_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_I2S_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_I2S_RAM3_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_I2S_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_I2S_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_I2S_RAM2_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_I2S_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_I2S_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_I2S_RAM1_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_I2S_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_I2S_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_I2S_RAM0_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_I2S_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_PDM */ -/* Description: AHB bus master priority register for PDM */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_PDM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_PDM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_PDM_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_PDM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_PDM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_PDM_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_PDM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_PDM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_PDM_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_PDM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_PDM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_PDM_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_PDM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_PDM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_PDM_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_PDM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_PDM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_PDM_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_PDM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_PDM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_PDM_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_PDM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_PDM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_PDM_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_PWM */ -/* Description: AHB bus master priority register for PWM0, PWM1 and PWM2 */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_PWM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_PWM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_PWM_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_PWM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_PWM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_PWM_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_PWM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_PWM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_PWM_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_PWM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_PWM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_PWM_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_PWM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_PWM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_PWM_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_PWM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_PWM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_PWM_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_PWM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_PWM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_PWM_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_PWM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_PWM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_PWM_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri15 (15UL) /*!< Priority 15 */ - - /* Peripheral: BPROT */ /* Description: Block Protect */ @@ -3462,6 +1196,18 @@ /* Register: CLOCK_LFCLKSRC */ /* Description: Clock source for the LFCLK */ +/* Bit 17 : Enable or disable external source for LFCLK */ +#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */ +#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */ + +/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */ +#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */ +#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */ + /* Bits 1..0 : Clock source */ #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ @@ -3470,7 +1216,7 @@ #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ /* Register: CLOCK_CTIV */ -/* Description: Calibration timer interval (retained register, same reset behaviour as RESETREAS) */ +/* Description: Calibration timer interval */ /* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */ #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ @@ -3654,7 +1400,7 @@ #define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ /* Register: COMP_REFSEL */ -/* Description: Reference source select */ +/* Description: Reference source select for single-ended mode */ /* Bits 2..0 : Reference select */ #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ @@ -3668,11 +1414,17 @@ /* Register: COMP_EXTREFSEL */ /* Description: External reference select */ -/* Bit 0 : External analog reference select */ +/* Bits 2..0 : External analog reference select */ #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ -#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */ /* Register: COMP_TH */ /* Description: Threshold configuration for hysteresis unit */ @@ -3688,18 +1440,18 @@ /* Register: COMP_MODE */ /* Description: Mode configuration */ -/* Bit 8 : Main operation mode */ +/* Bit 8 : Main operation modes */ #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ -#define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */ +#define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */ #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */ -/* Bits 1..0 : Speed and power mode */ +/* Bits 1..0 : Speed and power modes */ #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ -#define COMP_MODE_SP_Low (0UL) /*!< Low power mode */ +#define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */ #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */ -#define COMP_MODE_SP_High (2UL) /*!< High speed mode */ +#define COMP_MODE_SP_High (2UL) /*!< High-speed mode */ /* Register: COMP_HYST */ /* Description: Comparator hysteresis enable */ @@ -4171,8 +1923,10 @@ #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ #define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */ +#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */ #define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ #define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ +#define FICR_INFO_VARIANT_VARIANT_AAE0 (0x41414530UL) /*!< AAE0 */ #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_PACKAGE */ @@ -4183,6 +1937,8 @@ #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */ #define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_CI (0x2002UL) /*!< CIxx - 7x8 WLCSP 56 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_CK (0x2005UL) /*!< CKxx - 7x8 WLCSP 56 balls with backside coating for light protection */ #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_RAM */ @@ -4954,7 +2710,7 @@ /* Bit 0 : Result of last compare. Decision point SAMPLE task. */ #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ -#define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */ +#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */ #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-). */ /* Register: LPCOMP_ENABLE */ @@ -7095,193 +4851,193 @@ /* Register: GPIO_OUT */ /* Description: Write GPIO port */ -/* Bit 31 : P0.31 pin */ +/* Bit 31 : Pin 31 */ #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ -/* Bit 30 : P0.30 pin */ +/* Bit 30 : Pin 30 */ #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ -/* Bit 29 : P0.29 pin */ +/* Bit 29 : Pin 29 */ #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ -/* Bit 28 : P0.28 pin */ +/* Bit 28 : Pin 28 */ #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ -/* Bit 27 : P0.27 pin */ +/* Bit 27 : Pin 27 */ #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ -/* Bit 26 : P0.26 pin */ +/* Bit 26 : Pin 26 */ #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ -/* Bit 25 : P0.25 pin */ +/* Bit 25 : Pin 25 */ #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ -/* Bit 24 : P0.24 pin */ +/* Bit 24 : Pin 24 */ #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ -/* Bit 23 : P0.23 pin */ +/* Bit 23 : Pin 23 */ #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ -/* Bit 22 : P0.22 pin */ +/* Bit 22 : Pin 22 */ #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ -/* Bit 21 : P0.21 pin */ +/* Bit 21 : Pin 21 */ #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ -/* Bit 20 : P0.20 pin */ +/* Bit 20 : Pin 20 */ #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ -/* Bit 19 : P0.19 pin */ +/* Bit 19 : Pin 19 */ #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ -/* Bit 18 : P0.18 pin */ +/* Bit 18 : Pin 18 */ #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ -/* Bit 17 : P0.17 pin */ +/* Bit 17 : Pin 17 */ #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ -/* Bit 16 : P0.16 pin */ +/* Bit 16 : Pin 16 */ #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ -/* Bit 15 : P0.15 pin */ +/* Bit 15 : Pin 15 */ #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ -/* Bit 14 : P0.14 pin */ +/* Bit 14 : Pin 14 */ #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ -/* Bit 13 : P0.13 pin */ +/* Bit 13 : Pin 13 */ #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ -/* Bit 12 : P0.12 pin */ +/* Bit 12 : Pin 12 */ #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ -/* Bit 11 : P0.11 pin */ +/* Bit 11 : Pin 11 */ #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ -/* Bit 10 : P0.10 pin */ +/* Bit 10 : Pin 10 */ #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ -/* Bit 9 : P0.9 pin */ +/* Bit 9 : Pin 9 */ #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ -/* Bit 8 : P0.8 pin */ +/* Bit 8 : Pin 8 */ #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ -/* Bit 7 : P0.7 pin */ +/* Bit 7 : Pin 7 */ #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ -/* Bit 6 : P0.6 pin */ +/* Bit 6 : Pin 6 */ #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ -/* Bit 5 : P0.5 pin */ +/* Bit 5 : Pin 5 */ #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ -/* Bit 4 : P0.4 pin */ +/* Bit 4 : Pin 4 */ #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ -/* Bit 3 : P0.3 pin */ +/* Bit 3 : Pin 3 */ #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ -/* Bit 2 : P0.2 pin */ +/* Bit 2 : Pin 2 */ #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ -/* Bit 1 : P0.1 pin */ +/* Bit 1 : Pin 1 */ #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ -/* Bit 0 : P0.0 pin */ +/* Bit 0 : Pin 0 */ #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ @@ -7290,224 +5046,224 @@ /* Register: GPIO_OUTSET */ /* Description: Set individual bits in GPIO port */ -/* Bit 31 : P0.31 pin */ +/* Bit 31 : Pin 31 */ #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 30 : P0.30 pin */ +/* Bit 30 : Pin 30 */ #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 29 : P0.29 pin */ +/* Bit 29 : Pin 29 */ #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 28 : P0.28 pin */ +/* Bit 28 : Pin 28 */ #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 27 : P0.27 pin */ +/* Bit 27 : Pin 27 */ #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 26 : P0.26 pin */ +/* Bit 26 : Pin 26 */ #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 25 : P0.25 pin */ +/* Bit 25 : Pin 25 */ #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 24 : P0.24 pin */ +/* Bit 24 : Pin 24 */ #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 23 : P0.23 pin */ +/* Bit 23 : Pin 23 */ #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 22 : P0.22 pin */ +/* Bit 22 : Pin 22 */ #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 21 : P0.21 pin */ +/* Bit 21 : Pin 21 */ #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 20 : P0.20 pin */ +/* Bit 20 : Pin 20 */ #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 19 : P0.19 pin */ +/* Bit 19 : Pin 19 */ #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 18 : P0.18 pin */ +/* Bit 18 : Pin 18 */ #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 17 : P0.17 pin */ +/* Bit 17 : Pin 17 */ #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 16 : P0.16 pin */ +/* Bit 16 : Pin 16 */ #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 15 : P0.15 pin */ +/* Bit 15 : Pin 15 */ #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 14 : P0.14 pin */ +/* Bit 14 : Pin 14 */ #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 13 : P0.13 pin */ +/* Bit 13 : Pin 13 */ #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 12 : P0.12 pin */ +/* Bit 12 : Pin 12 */ #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 11 : P0.11 pin */ +/* Bit 11 : Pin 11 */ #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 10 : P0.10 pin */ +/* Bit 10 : Pin 10 */ #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 9 : P0.9 pin */ +/* Bit 9 : Pin 9 */ #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 8 : P0.8 pin */ +/* Bit 8 : Pin 8 */ #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 7 : P0.7 pin */ +/* Bit 7 : Pin 7 */ #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 6 : P0.6 pin */ +/* Bit 6 : Pin 6 */ #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 5 : P0.5 pin */ +/* Bit 5 : Pin 5 */ #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 4 : P0.4 pin */ +/* Bit 4 : Pin 4 */ #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 3 : P0.3 pin */ +/* Bit 3 : Pin 3 */ #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 2 : P0.2 pin */ +/* Bit 2 : Pin 2 */ #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 1 : P0.1 pin */ +/* Bit 1 : Pin 1 */ #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 0 : P0.0 pin */ +/* Bit 0 : Pin 0 */ #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ @@ -7517,224 +5273,224 @@ /* Register: GPIO_OUTCLR */ /* Description: Clear individual bits in GPIO port */ -/* Bit 31 : P0.31 pin */ +/* Bit 31 : Pin 31 */ #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 30 : P0.30 pin */ +/* Bit 30 : Pin 30 */ #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 29 : P0.29 pin */ +/* Bit 29 : Pin 29 */ #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 28 : P0.28 pin */ +/* Bit 28 : Pin 28 */ #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 27 : P0.27 pin */ +/* Bit 27 : Pin 27 */ #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 26 : P0.26 pin */ +/* Bit 26 : Pin 26 */ #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 25 : P0.25 pin */ +/* Bit 25 : Pin 25 */ #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 24 : P0.24 pin */ +/* Bit 24 : Pin 24 */ #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 23 : P0.23 pin */ +/* Bit 23 : Pin 23 */ #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 22 : P0.22 pin */ +/* Bit 22 : Pin 22 */ #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 21 : P0.21 pin */ +/* Bit 21 : Pin 21 */ #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 20 : P0.20 pin */ +/* Bit 20 : Pin 20 */ #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 19 : P0.19 pin */ +/* Bit 19 : Pin 19 */ #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 18 : P0.18 pin */ +/* Bit 18 : Pin 18 */ #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 17 : P0.17 pin */ +/* Bit 17 : Pin 17 */ #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 16 : P0.16 pin */ +/* Bit 16 : Pin 16 */ #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 15 : P0.15 pin */ +/* Bit 15 : Pin 15 */ #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 14 : P0.14 pin */ +/* Bit 14 : Pin 14 */ #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 13 : P0.13 pin */ +/* Bit 13 : Pin 13 */ #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 12 : P0.12 pin */ +/* Bit 12 : Pin 12 */ #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 11 : P0.11 pin */ +/* Bit 11 : Pin 11 */ #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 10 : P0.10 pin */ +/* Bit 10 : Pin 10 */ #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 9 : P0.9 pin */ +/* Bit 9 : Pin 9 */ #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 8 : P0.8 pin */ +/* Bit 8 : Pin 8 */ #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 7 : P0.7 pin */ +/* Bit 7 : Pin 7 */ #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 6 : P0.6 pin */ +/* Bit 6 : Pin 6 */ #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 5 : P0.5 pin */ +/* Bit 5 : Pin 5 */ #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 4 : P0.4 pin */ +/* Bit 4 : Pin 4 */ #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 3 : P0.3 pin */ +/* Bit 3 : Pin 3 */ #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 2 : P0.2 pin */ +/* Bit 2 : Pin 2 */ #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 1 : P0.1 pin */ +/* Bit 1 : Pin 1 */ #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 0 : P0.0 pin */ +/* Bit 0 : Pin 0 */ #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ @@ -7744,193 +5500,193 @@ /* Register: GPIO_IN */ /* Description: Read GPIO port */ -/* Bit 31 : P0.31 pin */ +/* Bit 31 : Pin 31 */ #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ -/* Bit 30 : P0.30 pin */ +/* Bit 30 : Pin 30 */ #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ -/* Bit 29 : P0.29 pin */ +/* Bit 29 : Pin 29 */ #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ -/* Bit 28 : P0.28 pin */ +/* Bit 28 : Pin 28 */ #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ -/* Bit 27 : P0.27 pin */ +/* Bit 27 : Pin 27 */ #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ -/* Bit 26 : P0.26 pin */ +/* Bit 26 : Pin 26 */ #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ -/* Bit 25 : P0.25 pin */ +/* Bit 25 : Pin 25 */ #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ -/* Bit 24 : P0.24 pin */ +/* Bit 24 : Pin 24 */ #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ -/* Bit 23 : P0.23 pin */ +/* Bit 23 : Pin 23 */ #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ -/* Bit 22 : P0.22 pin */ +/* Bit 22 : Pin 22 */ #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ -/* Bit 21 : P0.21 pin */ +/* Bit 21 : Pin 21 */ #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ -/* Bit 20 : P0.20 pin */ +/* Bit 20 : Pin 20 */ #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ -/* Bit 19 : P0.19 pin */ +/* Bit 19 : Pin 19 */ #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ -/* Bit 18 : P0.18 pin */ +/* Bit 18 : Pin 18 */ #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ -/* Bit 17 : P0.17 pin */ +/* Bit 17 : Pin 17 */ #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ -/* Bit 16 : P0.16 pin */ +/* Bit 16 : Pin 16 */ #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ -/* Bit 15 : P0.15 pin */ +/* Bit 15 : Pin 15 */ #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ -/* Bit 14 : P0.14 pin */ +/* Bit 14 : Pin 14 */ #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ -/* Bit 13 : P0.13 pin */ +/* Bit 13 : Pin 13 */ #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ -/* Bit 12 : P0.12 pin */ +/* Bit 12 : Pin 12 */ #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ -/* Bit 11 : P0.11 pin */ +/* Bit 11 : Pin 11 */ #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ -/* Bit 10 : P0.10 pin */ +/* Bit 10 : Pin 10 */ #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ -/* Bit 9 : P0.9 pin */ +/* Bit 9 : Pin 9 */ #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ -/* Bit 8 : P0.8 pin */ +/* Bit 8 : Pin 8 */ #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ -/* Bit 7 : P0.7 pin */ +/* Bit 7 : Pin 7 */ #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ -/* Bit 6 : P0.6 pin */ +/* Bit 6 : Pin 6 */ #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ -/* Bit 5 : P0.5 pin */ +/* Bit 5 : Pin 5 */ #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ -/* Bit 4 : P0.4 pin */ +/* Bit 4 : Pin 4 */ #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ -/* Bit 3 : P0.3 pin */ +/* Bit 3 : Pin 3 */ #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ -/* Bit 2 : P0.2 pin */ +/* Bit 2 : Pin 2 */ #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ -/* Bit 1 : P0.1 pin */ +/* Bit 1 : Pin 1 */ #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ -/* Bit 0 : P0.0 pin */ +/* Bit 0 : Pin 0 */ #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ @@ -7939,193 +5695,193 @@ /* Register: GPIO_DIR */ /* Description: Direction of GPIO pins */ -/* Bit 31 : P0.31 pin */ +/* Bit 31 : Pin 31 */ #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ -/* Bit 30 : P0.30 pin */ +/* Bit 30 : Pin 30 */ #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ -/* Bit 29 : P0.29 pin */ +/* Bit 29 : Pin 29 */ #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ -/* Bit 28 : P0.28 pin */ +/* Bit 28 : Pin 28 */ #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ -/* Bit 27 : P0.27 pin */ +/* Bit 27 : Pin 27 */ #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ -/* Bit 26 : P0.26 pin */ +/* Bit 26 : Pin 26 */ #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ -/* Bit 25 : P0.25 pin */ +/* Bit 25 : Pin 25 */ #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ -/* Bit 24 : P0.24 pin */ +/* Bit 24 : Pin 24 */ #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ -/* Bit 23 : P0.23 pin */ +/* Bit 23 : Pin 23 */ #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ -/* Bit 22 : P0.22 pin */ +/* Bit 22 : Pin 22 */ #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ -/* Bit 21 : P0.21 pin */ +/* Bit 21 : Pin 21 */ #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ -/* Bit 20 : P0.20 pin */ +/* Bit 20 : Pin 20 */ #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ -/* Bit 19 : P0.19 pin */ +/* Bit 19 : Pin 19 */ #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ -/* Bit 18 : P0.18 pin */ +/* Bit 18 : Pin 18 */ #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ -/* Bit 17 : P0.17 pin */ +/* Bit 17 : Pin 17 */ #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ -/* Bit 16 : P0.16 pin */ +/* Bit 16 : Pin 16 */ #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ -/* Bit 15 : P0.15 pin */ +/* Bit 15 : Pin 15 */ #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ -/* Bit 14 : P0.14 pin */ +/* Bit 14 : Pin 14 */ #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ -/* Bit 13 : P0.13 pin */ +/* Bit 13 : Pin 13 */ #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ -/* Bit 12 : P0.12 pin */ +/* Bit 12 : Pin 12 */ #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ -/* Bit 11 : P0.11 pin */ +/* Bit 11 : Pin 11 */ #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ -/* Bit 10 : P0.10 pin */ +/* Bit 10 : Pin 10 */ #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ -/* Bit 9 : P0.9 pin */ +/* Bit 9 : Pin 9 */ #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ -/* Bit 8 : P0.8 pin */ +/* Bit 8 : Pin 8 */ #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ -/* Bit 7 : P0.7 pin */ +/* Bit 7 : Pin 7 */ #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ -/* Bit 6 : P0.6 pin */ +/* Bit 6 : Pin 6 */ #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ -/* Bit 5 : P0.5 pin */ +/* Bit 5 : Pin 5 */ #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ -/* Bit 4 : P0.4 pin */ +/* Bit 4 : Pin 4 */ #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ -/* Bit 3 : P0.3 pin */ +/* Bit 3 : Pin 3 */ #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ -/* Bit 2 : P0.2 pin */ +/* Bit 2 : Pin 2 */ #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ -/* Bit 1 : P0.1 pin */ +/* Bit 1 : Pin 1 */ #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ -/* Bit 0 : P0.0 pin */ +/* Bit 0 : Pin 0 */ #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ @@ -10414,9 +8170,9 @@ #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ -/* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */ +/* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */ #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ -#define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ +#define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ @@ -10431,24 +8187,24 @@ #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ /* Register: PWM_SEQ_PTR */ -/* Description: Description cluster[0]: Beginning address in Data RAM of sequence A */ +/* Description: Description cluster[0]: Beginning address in Data RAM of this sequence */ -/* Bits 31..0 : Beginning address in Data RAM of sequence A */ +/* Bits 31..0 : Beginning address in Data RAM of this sequence */ #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: PWM_SEQ_CNT */ -/* Description: Description cluster[0]: Amount of values (duty cycles) in sequence A */ +/* Description: Description cluster[0]: Amount of values (duty cycles) in this sequence */ -/* Bits 14..0 : Amount of values (duty cycles) in sequence A */ +/* Bits 14..0 : Amount of values (duty cycles) in this sequence */ #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ /* Register: PWM_SEQ_REFRESH */ -/* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */ +/* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded into compare register */ -/* Bits 23..0 : Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */ +/* Bits 23..0 : Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ @@ -11014,13 +8770,13 @@ #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */ #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */ #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */ -#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator - -40 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xFFUL) /*!< Deprecated enumerator - -40 dBm */ /* Register: RADIO_MODE */ /* Description: Data rate and modulation */ @@ -11032,6 +8788,7 @@ #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */ #define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode */ #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */ +#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */ /* Register: RADIO_PCNF0 */ /* Description: Packet configuration register 0 */ @@ -12567,7 +10324,7 @@ #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ /* Register: SPIM_FREQUENCY */ -/* Description: SPI frequency */ +/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ /* Bits 31..0 : SPI master data rate */ #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ @@ -13366,18 +11123,21 @@ #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */ #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */ +#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Write: clear error on writing '1' */ /* Bit 1 : NACK received after sending the address (write '1' to clear) */ #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */ #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */ +#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Write: clear error on writing '1' */ /* Bit 0 : Overrun error */ #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ +#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Write: clear error on writing '1' */ /* Register: TWI_ENABLE */ /* Description: Enable TWI */ @@ -13636,6 +11396,12 @@ #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ +/* Bit 0 : Overrun error */ +#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */ + /* Register: TWIM_ENABLE */ /* Description: Enable TWIM */ @@ -14224,7 +11990,7 @@ /* Register: UART_BAUDRATE */ /* Description: Baud rate */ -/* Bits 31..0 : Baud-rate */ +/* Bits 31..0 : Baud rate */ #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ @@ -14234,7 +12000,9 @@ #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */ #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */ +#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */ +#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */ #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */ @@ -14317,12 +12085,24 @@ #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ +/* Bit 7 : Enable or disable interrupt for TXDRDY event */ +#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ + /* Bit 4 : Enable or disable interrupt for ENDRX event */ #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ +/* Bit 2 : Enable or disable interrupt for RXDRDY event */ +#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ + /* Bit 1 : Enable or disable interrupt for NCTS event */ #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ @@ -14380,6 +12160,13 @@ #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ +/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */ +#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ @@ -14387,6 +12174,13 @@ #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ +/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */ +#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + /* Bit 1 : Write '1' to Enable interrupt for NCTS event */ #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ @@ -14446,6 +12240,13 @@ #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ +/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */ +#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ @@ -14453,6 +12254,13 @@ #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ +/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */ +#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + /* Bit 1 : Write '1' to Disable interrupt for NCTS event */ #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ @@ -14556,9 +12364,9 @@ #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ /* Register: UARTE_BAUDRATE */ -/* Description: Baud rate */ +/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ -/* Bits 31..0 : Baud-rate */ +/* Bits 31..0 : Baud rate */ #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ @@ -14568,7 +12376,9 @@ #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ @@ -14669,14 +12479,14 @@ #define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */ #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bits 4..0 : GPIO number P0.n onto which Reset is exposed */ +/* Bits 5..0 : GPIO number P0.n onto which Reset is exposed */ #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ +#define UICR_PSELRESET_PIN_Msk (0x3FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ /* Register: UICR_APPROTECT */ /* Description: Access Port protection */ -/* Bits 7..0 : Enable or disable Access Port protection. */ +/* Bits 7..0 : Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection. */ #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ @@ -14859,3 +12669,6 @@ /*lint --flb "Leave library region" */ #endif + +/** @} */ /* End of group nrf52 */ +/** @} */ /* End of group Nordic Semiconductor */ diff --git a/os/hal/ports/NRF5/NRF52832/nrf52_name_change.h b/os/hal/ports/NRF5/NRF52832/nrf52_name_change.h new file mode 100644 index 00000000..02f46f24 --- /dev/null +++ b/os/hal/ports/NRF5/NRF52832/nrf52_name_change.h @@ -0,0 +1,91 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +/** @addtogroup Nordic Semiconductor + * @{ + */ + +/** @addtogroup nrf52 + * @{ + */ + +#ifndef NRF52_NAME_CHANGE_H +#define NRF52_NAME_CHANGE_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the updates made to nrf52.h and + * nrf52_bitfields.h. The macros defined in this file were available previously. Do not use these + * macros on purpose. Use the ones defined in nrf52.h and nrf52_bitfields.h instead. + */ + +/* I2S */ +/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */ +#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled +#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled +#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master +#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave +#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled +#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled +#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled +#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled +#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled +#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled +#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit +#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit +#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit +#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left +#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right +#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned +#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo +#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left +#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right + +/* LPCOMP */ +/* Corrected typo in RESULT register. */ +#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below + +/*lint --flb "Leave library region" */ + +#endif /* NRF52_NAME_CHANGE_H */ + +/** @} */ /* End of group nrf52 */ +/** @} */ /* End of group Nordic Semiconductor */