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Rename I2C1 -> I2C0

This commit is contained in:
Stefan Kerkmann 2021-03-25 18:57:11 +01:00
parent ef39596f92
commit ff5541e6c7
7 changed files with 105 additions and 105 deletions
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74
os/hal/ports/GD/GD32VF103/I2C/hal_i2c_lld.c
View File

@ -34,13 +34,13 @@
/* Driver local definitions. */ /* Driver local definitions. */
/*===========================================================================*/ /*===========================================================================*/
#define I2C1_RX_DMA_CHANNEL \ #define I2C0_RX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_I2C_I2C1_RX_DMA_STREAM, \ GD32_DMA_GETCHANNEL(GD32_I2C_I2C0_RX_DMA_STREAM, \
GD32_I2C1_RX_DMA_CHN) GD32_I2C0_RX_DMA_CHN)
#define I2C1_TX_DMA_CHANNEL \ #define I2C0_TX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_I2C_I2C1_TX_DMA_STREAM, \ GD32_DMA_GETCHANNEL(GD32_I2C_I2C0_TX_DMA_STREAM, \
GD32_I2C1_TX_DMA_CHN) GD32_I2C0_TX_DMA_CHN)
#define I2C2_RX_DMA_CHANNEL \ #define I2C2_RX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_I2C_I2C2_RX_DMA_STREAM, \ GD32_DMA_GETCHANNEL(GD32_I2C_I2C2_RX_DMA_STREAM, \
@ -84,8 +84,8 @@
/* Driver exported variables. */ /* Driver exported variables. */
/*===========================================================================*/ /*===========================================================================*/
/** @brief I2C1 driver identifier.*/ /** @brief I2C0 driver identifier.*/
#if GD32_I2C_USE_I2C1 || defined(__DOXYGEN__) #if GD32_I2C_USE_I2C0 || defined(__DOXYGEN__)
I2CDriver I2CD1; I2CDriver I2CD1;
#endif #endif
@ -409,13 +409,13 @@ static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint16_t sr) {
/* Driver interrupt handlers. */ /* Driver interrupt handlers. */
/*===========================================================================*/ /*===========================================================================*/
#if GD32_I2C_USE_I2C1 || defined(__DOXYGEN__) #if GD32_I2C_USE_I2C0 || defined(__DOXYGEN__)
/** /**
* @brief I2C1 event interrupt handler. * @brief I2C0 event interrupt handler.
* *
* @notapi * @notapi
*/ */
OSAL_IRQ_HANDLER(GD32_I2C1_EVENT_HANDLER) { OSAL_IRQ_HANDLER(GD32_I2C0_EVENT_HANDLER) {
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
@ -425,9 +425,9 @@ OSAL_IRQ_HANDLER(GD32_I2C1_EVENT_HANDLER) {
} }
/** /**
* @brief I2C1 error interrupt handler. * @brief I2C0 error interrupt handler.
*/ */
OSAL_IRQ_HANDLER(GD32_I2C1_ERROR_HANDLER) { OSAL_IRQ_HANDLER(GD32_I2C0_ERROR_HANDLER) {
uint16_t sr = I2CD1.i2c->STAT0; uint16_t sr = I2CD1.i2c->STAT0;
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
@ -437,7 +437,7 @@ OSAL_IRQ_HANDLER(GD32_I2C1_ERROR_HANDLER) {
OSAL_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
#endif /* GD32_I2C_USE_I2C1 */ #endif /* GD32_I2C_USE_I2C0 */
#if GD32_I2C_USE_I2C2 || defined(__DOXYGEN__) #if GD32_I2C_USE_I2C2 || defined(__DOXYGEN__)
/** /**
@ -482,13 +482,13 @@ OSAL_IRQ_HANDLER(GD32_I2C2_ERROR_HANDLER) {
*/ */
void i2c_lld_init(void) { void i2c_lld_init(void) {
#if GD32_I2C_USE_I2C1 #if GD32_I2C_USE_I2C0
i2cObjectInit(&I2CD1); i2cObjectInit(&I2CD1);
I2CD1.thread = NULL; I2CD1.thread = NULL;
I2CD1.i2c = I2C1; I2CD1.i2c = I2C0;
I2CD1.dmarx = NULL; I2CD1.dmarx = NULL;
I2CD1.dmatx = NULL; I2CD1.dmatx = NULL;
#endif /* GD32_I2C_USE_I2C1 */ #endif /* GD32_I2C_USE_I2C0 */
#if GD32_I2C_USE_I2C2 #if GD32_I2C_USE_I2C2
i2cObjectInit(&I2CD2); i2cObjectInit(&I2CD2);
@ -521,31 +521,31 @@ void i2c_lld_start(I2CDriver *i2cp) {
GD32_DMA_CTL_ERRIE | GD32_DMA_CTL_FTFIE | GD32_DMA_CTL_ERRIE | GD32_DMA_CTL_FTFIE |
GD32_DMA_CTL_DIR_P2M; GD32_DMA_CTL_DIR_P2M;
#if GD32_I2C_USE_I2C1 #if GD32_I2C_USE_I2C0
if (&I2CD1 == i2cp) { if (&I2CD1 == i2cp) {
rccResetI2C1(); rccResetI2C0();
i2cp->dmarx = dmaStreamAllocI(GD32_I2C_I2C1_RX_DMA_STREAM, i2cp->dmarx = dmaStreamAllocI(GD32_I2C_I2C0_RX_DMA_STREAM,
GD32_I2C_I2C1_IRQ_PRIORITY, GD32_I2C_I2C0_IRQ_PRIORITY,
(gd32_dmaisr_t)i2c_lld_serve_rx_end_irq, (gd32_dmaisr_t)i2c_lld_serve_rx_end_irq,
(void *)i2cp); (void *)i2cp);
osalDbgAssert(i2cp->dmarx != NULL, "unable to allocate stream"); osalDbgAssert(i2cp->dmarx != NULL, "unable to allocate stream");
i2cp->dmatx = dmaStreamAllocI(GD32_I2C_I2C1_TX_DMA_STREAM, i2cp->dmatx = dmaStreamAllocI(GD32_I2C_I2C0_TX_DMA_STREAM,
GD32_I2C_I2C1_IRQ_PRIORITY, GD32_I2C_I2C0_IRQ_PRIORITY,
(gd32_dmaisr_t)i2c_lld_serve_tx_end_irq, (gd32_dmaisr_t)i2c_lld_serve_tx_end_irq,
(void *)i2cp); (void *)i2cp);
osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream"); osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream");
rccEnableI2C1(true); rccEnableI2C0(true);
eclicEnableVector(I2C0_EV_IRQn, GD32_I2C_I2C1_IRQ_PRIORITY, GD32_I2C_I2C1_IRQ_TRIGGER); eclicEnableVector(I2C0_EV_IRQn, GD32_I2C_I2C0_IRQ_PRIORITY, GD32_I2C_I2C0_IRQ_TRIGGER);
eclicEnableVector(I2C0_ER_IRQn, GD32_I2C_I2C1_IRQ_PRIORITY, GD32_I2C_I2C1_IRQ_TRIGGER); eclicEnableVector(I2C0_ER_IRQn, GD32_I2C_I2C0_IRQ_PRIORITY, GD32_I2C_I2C0_IRQ_TRIGGER);
i2cp->rxdmamode |= GD32_DMA_CTL_CHSEL(I2C1_RX_DMA_CHANNEL) | i2cp->rxdmamode |= GD32_DMA_CTL_CHSEL(I2C0_RX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_I2C_I2C1_DMA_PRIORITY); GD32_DMA_CTL_PRIO(GD32_I2C_I2C0_DMA_PRIORITY);
i2cp->txdmamode |= GD32_DMA_CTL_CHSEL(I2C1_TX_DMA_CHANNEL) | i2cp->txdmamode |= GD32_DMA_CTL_CHSEL(I2C0_TX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_I2C_I2C1_DMA_PRIORITY); GD32_DMA_CTL_PRIO(GD32_I2C_I2C0_DMA_PRIORITY);
} }
#endif /* GD32_I2C_USE_I2C1 */ #endif /* GD32_I2C_USE_I2C0 */
#if GD32_I2C_USE_I2C2 #if GD32_I2C_USE_I2C2
if (&I2CD2 == i2cp) { if (&I2CD2 == i2cp) {
@ -563,8 +563,8 @@ void i2c_lld_start(I2CDriver *i2cp) {
osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream"); osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream");
rccEnableI2C2(true); rccEnableI2C2(true);
eclicEnableVector(I2C1_EV_IRQn, GD32_I2C_I2C2_IRQ_PRIORITY, GD32_I2C_I2C2_IRQ_TRIGGER); eclicEnableVector(I2C0_EV_IRQn, GD32_I2C_I2C2_IRQ_PRIORITY, GD32_I2C_I2C2_IRQ_TRIGGER);
eclicEnableVector(I2C1_ER_IRQn, GD32_I2C_I2C2_IRQ_PRIORITY, GD32_I2C_I2C2_IRQ_TRIGGER); eclicEnableVector(I2C0_ER_IRQn, GD32_I2C_I2C2_IRQ_PRIORITY, GD32_I2C_I2C2_IRQ_TRIGGER);
i2cp->rxdmamode |= GD32_DMA_CTL_CHSEL(I2C2_RX_DMA_CHANNEL) | i2cp->rxdmamode |= GD32_DMA_CTL_CHSEL(I2C2_RX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_I2C_I2C2_DMA_PRIORITY); GD32_DMA_CTL_PRIO(GD32_I2C_I2C2_DMA_PRIORITY);
@ -611,11 +611,11 @@ void i2c_lld_stop(I2CDriver *i2cp) {
i2cp->dmatx = NULL; i2cp->dmatx = NULL;
i2cp->dmarx = NULL; i2cp->dmarx = NULL;
#if GD32_I2C_USE_I2C1 #if GD32_I2C_USE_I2C0
if (&I2CD1 == i2cp) { if (&I2CD1 == i2cp) {
eclicDisableVector(I2C1_EV_IRQn); eclicDisableVector(I2C0_EV_IRQn);
eclicDisableVector(I2C1_ER_IRQn); eclicDisableVector(I2C0_ER_IRQn);
rccDisableI2C1(); rccDisableI2C0();
} }
#endif #endif

44
os/hal/ports/GD/GD32VF103/I2C/hal_i2c_lld.h
View File

@ -49,12 +49,12 @@
* @{ * @{
*/ */
/** /**
* @brief I2C1 driver enable switch. * @brief I2C0 driver enable switch.
* @details If set to @p TRUE the support for I2C1 is included. * @details If set to @p TRUE the support for I2C0 is included.
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(GD32_I2C_USE_I2C1) || defined(__DOXYGEN__) #if !defined(GD32_I2C_USE_I2C0) || defined(__DOXYGEN__)
#define GD32_I2C_USE_I2C1 FALSE #define GD32_I2C_USE_I2C0 FALSE
#endif #endif
/** /**
@ -74,10 +74,10 @@
#endif #endif
/** /**
* @brief I2C1 interrupt priority level setting. * @brief I2C0 interrupt priority level setting.
*/ */
#if !defined(GD32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__) #if !defined(GD32_I2C_I2C0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2C_I2C1_IRQ_PRIORITY 10 #define GD32_I2C_I2C0_IRQ_PRIORITY 10
#endif #endif
/** /**
@ -88,13 +88,13 @@
#endif #endif
/** /**
* @brief I2C1 DMA priority (0..3|lowest..highest). * @brief I2C0 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA streams but * @note The priority level is used for both the TX and RX DMA streams but
* because of the streams ordering the RX stream has always priority * because of the streams ordering the RX stream has always priority
* over the TX stream. * over the TX stream.
*/ */
#if !defined(GD32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__) #if !defined(GD32_I2C_I2C0_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2C_I2C1_DMA_PRIORITY 1 #define GD32_I2C_I2C0_DMA_PRIORITY 1
#endif #endif
/** /**
@ -116,8 +116,8 @@
#define GD32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") #define GD32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
#endif #endif
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 6) #define GD32_I2C_I2C0_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 6)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 5) #define GD32_I2C_I2C0_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 5)
#define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 4) #define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 4)
#define GD32_I2C_I2C2_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 3) #define GD32_I2C_I2C2_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 3)
@ -128,21 +128,21 @@
/*===========================================================================*/ /*===========================================================================*/
/** @brief error checks */ /** @brief error checks */
#if GD32_I2C_USE_I2C1 && !GD32_HAS_I2C1 #if GD32_I2C_USE_I2C0 && !GD32_HAS_I2C0
#error "I2C1 not present in the selected device" #error "I2C0 not present in the selected device"
#endif #endif
#if GD32_I2C_USE_I2C2 && !GD32_HAS_I2C2 #if GD32_I2C_USE_I2C2 && !GD32_HAS_I2C2
#error "I2C2 not present in the selected device" #error "I2C2 not present in the selected device"
#endif #endif
#if !GD32_I2C_USE_I2C1 && !GD32_I2C_USE_I2C2 #if !GD32_I2C_USE_I2C0 && !GD32_I2C_USE_I2C2
#error "I2C driver activated but no I2C peripheral assigned" #error "I2C driver activated but no I2C peripheral assigned"
#endif #endif
#if GD32_I2C_USE_I2C1 && \ #if GD32_I2C_USE_I2C0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_I2C_I2C1_IRQ_PRIORITY) !OSAL_IRQ_IS_VALID_PRIORITY(GD32_I2C_I2C0_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to I2C1" #error "Invalid IRQ priority assigned to I2C0"
#endif #endif
#if GD32_I2C_USE_I2C2 && \ #if GD32_I2C_USE_I2C2 && \
@ -150,9 +150,9 @@
#error "Invalid IRQ priority assigned to I2C2" #error "Invalid IRQ priority assigned to I2C2"
#endif #endif
#if GD32_I2C_USE_I2C1 && \ #if GD32_I2C_USE_I2C0 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_I2C_I2C1_DMA_PRIORITY) !GD32_DMA_IS_VALID_PRIORITY(GD32_I2C_I2C0_DMA_PRIORITY)
#error "Invalid DMA priority assigned to I2C1" #error "Invalid DMA priority assigned to I2C0"
#endif #endif
#if GD32_I2C_USE_I2C2 && \ #if GD32_I2C_USE_I2C2 && \
@ -297,7 +297,7 @@ struct I2CDriver {
/*===========================================================================*/ /*===========================================================================*/
#if !defined(__DOXYGEN__) #if !defined(__DOXYGEN__)
#if GD32_I2C_USE_I2C1 #if GD32_I2C_USE_I2C0
extern I2CDriver I2CD1; extern I2CDriver I2CD1;
#endif #endif

10
os/hal/ports/GD/GD32VF103/gd32_isr.h
View File

@ -57,10 +57,10 @@
/* /*
* I2C units. * I2C units.
*/ */
#define GD32_I2C1_EVENT_HANDLER vector50 #define GD32_I2C0_EVENT_HANDLER vector50
#define GD32_I2C1_ERROR_HANDLER vector51 #define GD32_I2C0_ERROR_HANDLER vector51
#define GD32_I2C1_EVENT_NUMBER 50 #define GD32_I2C0_EVENT_NUMBER 50
#define GD32_I2C1_ERROR_NUMBER 51 #define GD32_I2C0_ERROR_NUMBER 51
#define GD32_I2C2_EVENT_HANDLER vector52 #define GD32_I2C2_EVENT_HANDLER vector52
#define GD32_I2C2_ERROR_HANDLER vector53 #define GD32_I2C2_ERROR_HANDLER vector53
@ -228,7 +228,7 @@
#define GD32_GPT_TIM7_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_GPT_TIM7_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_GPT_TIM8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM9_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_GPT_TIM9_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_I2C_I2C1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_I2C_I2C0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_I2C_I2C2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_I2C_I2C2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_I2C_I2C3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_I2C_I2C3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ICU_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_ICU_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT

12
os/hal/ports/GD/GD32VF103/gd32_rcc.h
View File

@ -442,28 +442,28 @@
* @{ * @{
*/ */
/** /**
* @brief Enables the I2C1 peripheral clock. * @brief Enables the I2C0 peripheral clock.
* @note The @p lp parameter is ignored in this family. * @note The @p lp parameter is ignored in this family.
* *
* @param[in] lp low power enable flag * @param[in] lp low power enable flag
* *
* @api * @api
*/ */
#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) #define rccEnableI2C0(lp) rccEnableAPB1(RCC_APB1ENR_I2C0EN, lp)
/** /**
* @brief Disables the I2C1 peripheral clock. * @brief Disables the I2C0 peripheral clock.
* *
* @api * @api
*/ */
#define rccDisableI2C1() rccDisableAPB1(RCC_APB1ENR_I2C1EN) #define rccDisableI2C0() rccDisableAPB1(RCC_APB1ENR_I2C0EN)
/** /**
* @brief Resets the I2C1 peripheral. * @brief Resets the I2C0 peripheral.
* *
* @api * @api
*/ */
#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) #define rccResetI2C0() rccResetAPB1(RCC_APB1RSTR_I2C0RST)
/** /**
* @brief Enables the I2C2 peripheral clock. * @brief Enables the I2C2 peripheral clock.

8
os/hal/ports/GD/GD32VF103/gd32_registry.h
View File

@ -182,11 +182,11 @@
/* I2C attributes.*/ /* I2C attributes.*/
#if GD32_HAS_I2C_0 || GD32_HAS_I2C_01 #if GD32_HAS_I2C_0 || GD32_HAS_I2C_01
#define GD32_HAS_I2C1 TRUE #define GD32_HAS_I2C0 TRUE
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 6) #define GD32_I2C_I2C0_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 6)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 5) #define GD32_I2C_I2C0_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 5)
#else #else
#define GD32_HAS_I2C1 FALSE #define GD32_HAS_I2C0 FALSE
#endif #endif
#if GD32_HAS_I2C_01 #if GD32_HAS_I2C_01

36
os/hal/ports/GD/GD32VF103/stm32_registry.h
View File

@ -136,9 +136,9 @@
#define GD32_HAS_GPIOK FALSE #define GD32_HAS_GPIOK FALSE
/* I2C attributes.*/ /* I2C attributes.*/
#define GD32_HAS_I2C1 TRUE #define GD32_HAS_I2C0 TRUE
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7) #define GD32_I2C_I2C0_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6) #define GD32_I2C_I2C0_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_HAS_I2C2 TRUE #define GD32_HAS_I2C2 TRUE
#define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5) #define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
@ -349,9 +349,9 @@
#define GD32_HAS_GPIOK FALSE #define GD32_HAS_GPIOK FALSE
/* I2C attributes.*/ /* I2C attributes.*/
#define GD32_HAS_I2C1 TRUE #define GD32_HAS_I2C0 TRUE
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7) #define GD32_I2C_I2C0_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6) #define GD32_I2C_I2C0_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_HAS_I2C2 FALSE #define GD32_HAS_I2C2 FALSE
#define GD32_HAS_I2C3 FALSE #define GD32_HAS_I2C3 FALSE
@ -534,9 +534,9 @@
#define GD32_HAS_GPIOK FALSE #define GD32_HAS_GPIOK FALSE
/* I2C attributes.*/ /* I2C attributes.*/
#define GD32_HAS_I2C1 TRUE #define GD32_HAS_I2C0 TRUE
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7) #define GD32_I2C_I2C0_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6) #define GD32_I2C_I2C0_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_HAS_I2C2 TRUE #define GD32_HAS_I2C2 TRUE
#define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5) #define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
@ -752,9 +752,9 @@
#define GD32_HAS_GPIOK FALSE #define GD32_HAS_GPIOK FALSE
/* I2C attributes.*/ /* I2C attributes.*/
#define GD32_HAS_I2C1 TRUE #define GD32_HAS_I2C0 TRUE
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7) #define GD32_I2C_I2C0_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6) #define GD32_I2C_I2C0_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_HAS_I2C2 TRUE #define GD32_HAS_I2C2 TRUE
#define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5) #define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
@ -992,9 +992,9 @@
#define GD32_HAS_GPIOK FALSE #define GD32_HAS_GPIOK FALSE
/* I2C attributes.*/ /* I2C attributes.*/
#define GD32_HAS_I2C1 TRUE #define GD32_HAS_I2C0 TRUE
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7) #define GD32_I2C_I2C0_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6) #define GD32_I2C_I2C0_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_HAS_I2C2 TRUE #define GD32_HAS_I2C2 TRUE
#define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5) #define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
@ -1252,9 +1252,9 @@
#define GD32_HAS_GPIOK FALSE #define GD32_HAS_GPIOK FALSE
/* I2C attributes.*/ /* I2C attributes.*/
#define GD32_HAS_I2C1 TRUE #define GD32_HAS_I2C0 TRUE
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7) #define GD32_I2C_I2C0_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6) #define GD32_I2C_I2C0_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_HAS_I2C2 TRUE #define GD32_HAS_I2C2 TRUE
#define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5) #define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)

26
os/hal/ports/GD/GD32VF103/stm32f105xc.h
View File

@ -714,7 +714,7 @@ typedef struct
#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) #define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U) #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U)
#define UART5_BASE (APB1PERIPH_BASE + 0x00005000U) #define UART5_BASE (APB1PERIPH_BASE + 0x00005000U)
#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) #define I2C0_BASE (APB1PERIPH_BASE + 0x00005400U)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U) #define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U)
#define CAN2_BASE (APB1PERIPH_BASE + 0x00006800U) #define CAN2_BASE (APB1PERIPH_BASE + 0x00006800U)
@ -802,7 +802,7 @@ typedef struct
#define USART3 ((USART_TypeDef *)USART3_BASE) #define USART3 ((USART_TypeDef *)USART3_BASE)
#define UART4 ((USART_TypeDef *)UART4_BASE) #define UART4 ((USART_TypeDef *)UART4_BASE)
#define UART5 ((USART_TypeDef *)UART5_BASE) #define UART5 ((USART_TypeDef *)UART5_BASE)
#define I2C1 ((I2C_TypeDef *)I2C1_BASE) #define I2C0 ((I2C_TypeDef *)I2C0_BASE)
#define I2C2 ((I2C_TypeDef *)I2C2_BASE) #define I2C2 ((I2C_TypeDef *)I2C2_BASE)
#define CAN1 ((CAN_TypeDef *)CAN1_BASE) #define CAN1 ((CAN_TypeDef *)CAN1_BASE)
#define CAN2 ((CAN_TypeDef *)CAN2_BASE) #define CAN2 ((CAN_TypeDef *)CAN2_BASE)
@ -1559,9 +1559,9 @@ typedef struct
#define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Pos (17U)
#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
#define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C0RST_Pos (21U)
#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ #define RCC_APB1RSTR_I2C0RST_Msk (0x1U << RCC_APB1RSTR_I2C0RST_Pos) /*!< 0x00200000 */
#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ #define RCC_APB1RSTR_I2C0RST RCC_APB1RSTR_I2C0RST_Msk /*!< I2C 1 reset */
#define RCC_APB1RSTR_CAN1RST_Pos (25U) #define RCC_APB1RSTR_CAN1RST_Pos (25U)
#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
@ -1695,9 +1695,9 @@ typedef struct
#define RCC_APB1ENR_USART2EN_Pos (17U) #define RCC_APB1ENR_USART2EN_Pos (17U)
#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
#define RCC_APB1ENR_I2C1EN_Pos (21U) #define RCC_APB1ENR_I2C0EN_Pos (21U)
#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ #define RCC_APB1ENR_I2C0EN_Msk (0x1U << RCC_APB1ENR_I2C0EN_Pos) /*!< 0x00200000 */
#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ #define RCC_APB1ENR_I2C0EN RCC_APB1ENR_I2C0EN_Msk /*!< I2C 1 clock enable */
#define RCC_APB1ENR_CAN1EN_Pos (25U) #define RCC_APB1ENR_CAN1EN_Pos (25U)
#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
@ -2628,7 +2628,7 @@ typedef struct
#define AFIO_PCF0_SPI0_REMAP AFIO_PCF0_SPI0_REMAP_Msk /*!< SPI1 remapping */ #define AFIO_PCF0_SPI0_REMAP AFIO_PCF0_SPI0_REMAP_Msk /*!< SPI1 remapping */
#define AFIO_PCF0_I2C0_REMAP_Pos (1U) #define AFIO_PCF0_I2C0_REMAP_Pos (1U)
#define AFIO_PCF0_I2C0_REMAP_Msk (0x1U << AFIO_PCF0_I2C0_REMAP_Pos) /*!< 0x00000002 */ #define AFIO_PCF0_I2C0_REMAP_Msk (0x1U << AFIO_PCF0_I2C0_REMAP_Pos) /*!< 0x00000002 */
#define AFIO_PCF0_I2C0_REMAP AFIO_PCF0_I2C0_REMAP_Msk /*!< I2C1 remapping */ #define AFIO_PCF0_I2C0_REMAP AFIO_PCF0_I2C0_REMAP_Msk /*!< I2C0 remapping */
#define AFIO_PCF0_USART0_REMAP_Pos (2U) #define AFIO_PCF0_USART0_REMAP_Pos (2U)
#define AFIO_PCF0_USART0_REMAP_Msk (0x1U << AFIO_PCF0_USART0_REMAP_Pos) /*!< 0x00000004 */ #define AFIO_PCF0_USART0_REMAP_Msk (0x1U << AFIO_PCF0_USART0_REMAP_Pos) /*!< 0x00000004 */
#define AFIO_PCF0_USART0_REMAP AFIO_PCF0_USART0_REMAP_Msk /*!< USART1 remapping */ #define AFIO_PCF0_USART0_REMAP AFIO_PCF0_USART0_REMAP_Msk /*!< USART1 remapping */
@ -12347,9 +12347,9 @@ typedef struct
#define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U) #define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)
#define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */ #define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */
#define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */ #define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */
#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U) #define DBGMCU_CR_DBG_I2C0_SMBUS_TIMEOUT_Pos (15U)
#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */ #define DBGMCU_CR_DBG_I2C0_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C0_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ #define DBGMCU_CR_DBG_I2C0_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C0_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U) #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */ #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
@ -12630,7 +12630,7 @@ typedef struct
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/******************************** I2C Instances *******************************/ /******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C0) || \
((INSTANCE) == I2C2)) ((INSTANCE) == I2C2))
/******************************* SMBUS Instances ******************************/ /******************************* SMBUS Instances ******************************/