* [sn32] ct16: further chibios integration
general purpose and pwm driver
also introduce a reset function
* build ct16 driver
* [sn32] have some isr handling
* 240: config the board for pwm
* Revert "240: config the board for pwm"
probably best to do in pwm driver
This reverts commit c09059a8ba60ea1832ea14f4d557bd8e22df3fd7.
* ct: logic fix. remove unecessary include
* ct: typos + use notifications
* ct: the periodic notification should not stop the timer
* ct: pfpa assignment
* ct: pwm: enable channel only if configured as active
* ct: pwm: periodic tic should track the timer
* derp
* ct: our chip supports IRQ priority level [0-3]
* isr: use the appropriate priority for each device
* ct: pwm: actually handle the channels
* ct: we define the # of channels already so..
* isr: we handle this on the specific drivers
disable for now
* ct: pwm: don't override TC. Call a counter reset
* ct: pwm: Set the prescaler properly
PRE is the max value of PC. PC increments on every tick.
When PC reaches PRE, TC increments and the timer overflows
Periodic timer is software controlled
* ct: gpt: PRE is the interval. Call a counter reset
* ct: Rename reset funtion to be more precise
* ct: pwm: Invert the channel disable logic
* ct: pwm: autoreload on period match
* ct: pwm: we only care for the last 25bits of IC
* ct: gpt: we only care for the last 25bits of IC
* ct: pwm: init config as hw defaults
* ct: pwm: mr24 is the driver callback
* Revert "isr: we handle this on the specific drivers"
This reverts commit 9ca061f170d9523d0e4e42011881f3d0b8dd1599.
* Revert "[sn32] have some isr handling"
This reverts commit cf45020072ea828522f2de2f6d5d2521398a61cd.
* ct: pwm: update the periodic notification
* ct: gpt: use MR0
* ct: priority bump
* Revert "ct: priority bump"
3 is probably fine
This reverts commit d2a861097a43f367ffbd15f6fc5d6747d9f14426.
* sn32: pwm: introduce oneshot mode
enable it with by defining SN32_PWM_USE_ONESHOT TRUE
* pwm: reset: we have a function for that
* explicitly enable pwm channels
* bugfix for bad PWM_OUTPUT_MASK
if it is DISABLED, bad things occur
Only ever identify and use PWM_OUTPUT_ACTIVE_HIGH and PWM_OUTPUT_ACTIVE_LOW
* periodic notification: clear and disable it
* we definitely need this to only run at first init
* ct: pwm: support 23 channel chips
* ct: support 240b and 260 chips
* make the macro check build
* pwm: correctly set the logic level
* pwm: speed improvements
in our shared matrix driver, we only care about the last callback.
having a shortcut to that if no other flag is raised will improve speed
+ident and comment
* Revert "pwm: speed improvements"
This reverts commit e143544b807dd860d26548c803503521450822b8.
* Fixed bug in sys clock init, also reported by glory
* Removed modification of SN_FLASH->LPCTRL from SystemCoreClockUpdate(). SystemCoreClockUpdate() should only update the SystemCoreClock variable.
This is taken from the latest pack file called:
"SONiX.SN32F2_DFP.1.2.11.pack"
This pack file is found in an archive named:
"SN32F260_Startkit_Package_V1.6R.zip"
download from here:
http://www.sonix.com.tw/article-en-998-24753 or
http://www.sonix.com.tw/files/1/9BB279642CFC9359E050007F01007A12
(extract that zip file and look in the "Pack" folder)
if you rename "SONiX.SN32F2_DFP.1.2.11.pack" to "SONiX.SN32F2_DFP.1.2.11.zip" you can extract it with a normal zip program
You find the file "SN32F260.h" in the folder "Device/Include"
IsaacDynamo
dexter93
Jack
stdvar
Glory
Adam Honse
janjan
HorrorTroll