NUC123AN_v1 1.0 NUC123AN_v1 SVD file 8 32 32 read-write 0 0 SCS SCS Register Map SCS 0xE000E000 0x10 0xC registers 0x100 0x4 registers 0x180 0x4 registers 0x200 0x4 registers 0x280 0x4 registers 0x400 0x20 registers 0xD00 0x8 registers 0xD0C 0x8 registers 0xD1C 0x8 registers SYST_CSR SYST_CSR SysTick Control and Status Register 0x10 read-write 0x00000000 0xFFFFFFFF ENABLE 0 1 0 Counter Disabled #0 1 Counter will operate in a multi-shot manner #1 read-write TICKINT 1 1 0 Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred #0 1 Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick current value register by a register write in software will not cause SysTick to be pended #1 read-write CLKSRC 2 1 0 Clock source is (optional) external reference clock #0 1 Core clock used for SysTick #1 read-write COUNTFLAG Returns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register. 16 1 read-write SYST_RVR SYST_RVR SysTick Reload Value Register 0x14 read-write 0x00000000 0x00000000 RELOAD The value to load into the Current Value register when the counter reaches 0. 0 24 read-write SYST_CVR SYST_CVR SysTick Current Value Register 0x18 read-write 0x00000000 0x00000000 CURRENT Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ (see SysTick Reload Value register). 0 24 read-write NVIC_ISER NVIC_ISER IRQ0 ~ IRQ31 Set-Enable Control Register 0x100 read-write 0x00000000 0xFFFFFFFF SETENA Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nThe register reads back with the current enable state. 0 32 0 No effect 0 1 Associated interrupt Enabled 1 read-write NVIC_ICER NVIC_ICER IRQ0 ~ IRQ31 Clear-Enable Control Register 0x180 read-write 0x00000000 0xFFFFFFFF CLRENA Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nThe register reads back with the current enable state. 0 32 0 No effect 0 1 Associated interrupt Disabled 1 read-write NVIC_ISPR NVIC_ISPR IRQ0 ~ IRQ31 Set-Pending Control Register 0x200 read-write 0x00000000 0xFFFFFFFF SETPEND The register reads back with the current pending state. 0 32 0 No effect 0 1 Set pending state of the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47) 1 read-write NVIC_ICPR NVIC_ICPR IRQ0 ~ IRQ31 Clear-Pending Control Register 0x280 read-write 0x00000000 0xFFFFFFFF CLRPEND The register reads back with the current pending state. 0 32 0 No effect 0 1 Removes the pending state of associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47) 1 read-write NVIC_IPR0 NVIC_IPR0 IRQ0 ~ IRQ3 Priority Control Register 0x400 read-write 0x00000000 0xFFFFFFFF PRI_0 Priority of IRQ0\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_1 Priority of IRQ1\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write PRI_2 Priority of IRQ2\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_3 Priority of IRQ3\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_IPR1 NVIC_IPR1 IRQ4 ~ IRQ7 Priority Control Register 0x404 read-write 0x00000000 0xFFFFFFFF PRI_4 Priority of IRQ4\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_5 Priority of IRQ5\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write PRI_6 Priority of IRQ6\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_7 Priority of IRQ7\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_IPR2 NVIC_IPR2 IRQ8 ~ IRQ11 Priority Control Register 0x408 read-write 0x00000000 0xFFFFFFFF PRI_8 Priority of IRQ8\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_9 Priority of IRQ9\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write PRI_10 Priority of IRQ10\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_11 Priority of IRQ11\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_IPR3 NVIC_IPR3 IRQ12 ~ IRQ15 Priority Control Register 0x40C read-write 0x00000000 0xFFFFFFFF PRI_12 Priority of IRQ12\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_13 Priority of IRQ13\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write PRI_14 Priority of IRQ14\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_15 Priority of IRQ15\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_IPR4 NVIC_IPR4 IRQ16 ~ IRQ19 Priority Control Register 0x410 read-write 0x00000000 0xFFFFFFFF PRI_16 Priority of IRQ16\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_17 Priority of IRQ17\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write PRI_18 Priority of IRQ18\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_19 Priority of IRQ19\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_IPR5 NVIC_IPR5 IRQ20 ~ IRQ23 Priority Control Register 0x414 read-write 0x00000000 0xFFFFFFFF PRI_20 Priority of IRQ20\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_21 Priority of IRQ21\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write PRI_22 Priority of IRQ22\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_23 Priority of IRQ23\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_IPR6 NVIC_IPR6 IRQ24 ~ IRQ27 Priority Control Register 0x418 read-write 0x00000000 0xFFFFFFFF PRI_24 Priority of IRQ24\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_25 Priority of IRQ25\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write PRI_26 Priority of IRQ26\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_27 Priority of IRQ27\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_IPR7 NVIC_IPR7 IRQ28 ~ IRQ31 Priority Control Register 0x41C read-write 0x00000000 0xFFFFFFFF PRI_28 Priority of IRQ28\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_29 Priority of IRQ29\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write PRI_30 Priority of IRQ30\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_31 Priority of IRQ31\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write CPUID CPUID CPUID Register 0xD00 read-only 0x410CC200 0xFFFFFFFF REVISION Reads as 0x0 0 4 read-only PARTNO Reads as 0xC20. 4 12 read-only PART Reads as 0xC for ARMv6-M parts 16 4 read-only IMPLEMENTER 24 8 read-only ICSR ICSR Interrupt Control and State Register 0xD04 read-write 0x00000000 0xFFFFFFFF VECTACTIVE Contains the active exception number.\n 0 6 0 Thread mode 0 read-write VECTPENDING Indicates the exception number of the highest priority pending enabled exception:\n 12 6 0 No pending exceptions 0 read-write ISRPENDING Interrupt Pending Flag, Rxcluding NMI and Faults\nThis is a read only bit. 22 1 0 Interrupt not pending #0 1 Interrupt pending #1 read-write ISRPREEMPT If set, a pending exception will be serviced on exit from the debug halt state.\nThis is a read only bit. 23 1 read-write PENDSTCLR SysTick Exception Clear-pending Bit\nWrite:\nThis is a write only bit. When you want to clear PENDST bit, you must "write 0 to PENDSTSET and write 1 to PENDSTCLR" at the same time. 25 1 0 No effect #0 1 Removes the pending state from the SysTick exception #1 read-write PENDSTSET SysTick Exception Set-pending Bit\nWrite:\n 26 1 0 No effect.\nSysTick exception is not pending #0 1 Changes SysTick exception state to pending.\nSysTick exception is pending #1 read-write PENDSVCLR PendSV Clear-pending Bit\nWrite:\nThis is a write only bit. When you want to clear PENDSV bit, you must "write 0 to PENDSVSET and write 1 to PENDSVCLR" at the same time. 27 1 0 No effect #0 1 Removes the pending state from the PendSV exception #1 read-write PENDSVSET PendSV Set-pending Bit\nWrite:\nWriting 1 to this bit is the only way to set the PendSV exception state to pending. 28 1 0 No effect.\nPendSV exception is not pending #0 1 Changes PendSV exception state to pending.\nPendSV exception is pending #1 read-write NMIPENDSET NMI Set-pending Bit\nWrite:\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. 31 1 0 No effect.\nNMI exception is not pending #0 1 Changes NMI exception state to pending.\nNMI exception is pending #1 read-write AIRCR AIRCR Application Interrupt and Reset Control Register 0xD0C read-write 0xFA050000 0xFFFFFFFF VECTCLRACTIVE Set this bit to 1 will clears all active state information for fixed and configurable exceptions.\nThe bit is a write only bit and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack. 1 1 read-write SYSRESETREQ Writing this bit 1 will cause a reset signal to be asserted to the chip and indicate a reset is requested.\nThe bit is a write only and self-cleared as part of the reset sequence. 2 1 read-write VECTORKEY When write this register, this field should be 0x05FA, otherwise the write action will be unpredictable. 16 16 read-write SCR SCR System Control Register 0xD10 read-write 0x00000000 0xFFFFFFFF SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. 1 1 0 Do not sleep when returning to Thread mode #0 1 Enters sleep, or deep sleep, on return from an ISR to Thread mode #1 read-write SLEEPDEEP Controls whether the processor uses sleep or deep sleep as its low power mode:\n 2 1 0 Sleep #0 1 Deep sleep #1 read-write SEVONPEND Send Event on Pending bit:\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event. 4 1 0 Only enabled interrupts or events can wake up the processor, while disabled interrupts are excluded #0 1 Enabled events and all interrupts, including disabled interrupts, can wake up the processor #1 read-write SHPR2 SHPR2 System Handler Priority Register 2 0xD1C read-write 0x00000000 0xFFFFFFFF PRI_11 Priority of system handler 11 - SVCall\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write SHPR3 SHPR3 System Handler Priority Register 3 0xD20 read-write 0x00000000 0xFFFFFFFF PRI_14 Priority of System Handler 14 - PendSV\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_15 Priority of System Handler 15 - SysTick\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write INT INT Register Map INT 0x50000300 0x0 0x88 registers IRQ0_SRC IRQ0_SRC IRQ0 (BOD) interrupt source identity 0x0 read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: BOD_INT 0 3 read-only IRQ1_SRC IRQ1_SRC IRQ1 (WDT) interrupt source identity 0x4 read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: WDT_INT 0 3 read-only IRQ2_SRC IRQ2_SRC IRQ2 (EINT0) interrupt source identity 0x8 read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: EINT0 - external interrupt 0 from PB.14 0 3 read-only IRQ3_SRC IRQ3_SRC IRQ3 (EINT1) interrupt source identity 0xC read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: EINT1 - external interrupt 1 from PB.15 or PD.11 0 3 read-only IRQ4_SRC IRQ4_SRC IRQ4 (GPA/B) interrupt source identity 0x10 read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: GPB_INT\nBit0: GPA_INT 0 3 read-only IRQ5_SRC IRQ5_SRC IRQ5 (GPC/D/F) interrupt source identity 0x14 read-only 0x00000000 0x00000000 INT_SRC Bit3: GPF_INT\nBit2: 0\nBit1: GPD_INT\nBit0: GPC_INT 0 3 read-only IRQ6_SRC IRQ6_SRC IRQ6 (PWMA) interrupt source identity 0x18 read-only 0x00000000 0x00000000 INT_SRC Bit3: PWM3_INT\nBit2: PWM2_INT\nBit1: PWM1_INT\nBit0: PWM0_INT 0 4 read-only IRQ7_SRC IRQ7_SRC IRQ7 (Reserved) interrupt source identity 0x1C read-only 0x00000000 0x00000000 IRQ8_SRC IRQ8_SRC IRQ8 (TMR0) interrupt source identity 0x20 read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: TMR0_INT 0 3 read-only IRQ9_SRC IRQ9_SRC IRQ9 (TMR1) interrupt source identity 0x24 read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: TMR1_INT 0 3 read-only IRQ10_SRC IRQ10_SRC IRQ10 (TMR2) interrupt source identity 0x28 read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: TMR2_INT 0 3 read-only IRQ11_SRC IRQ11_SRC IRQ11 (TMR3) interrupt source identity 0x2C read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: TMR3_INT 0 3 read-only IRQ12_SRC IRQ12_SRC IRQ12 (UART0) interrupt source identity 0x30 read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: URT0_INT 0 3 read-only IRQ13_SRC IRQ13_SRC IRQ13 (UART1) interrupt source identity 0x34 read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: UART1_INT 0 3 read-only IRQ14_SRC IRQ14_SRC IRQ14 (SPI0) interrupt source identity 0x38 read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: SPI0_INT 0 3 read-only IRQ15_SRC IRQ15_SRC IRQ15 (SPI1) interrupt source identity 0x3C read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: SPI1_INT 0 3 read-only IRQ16_SRC IRQ16_SRC IRQ16 (SPI2) interrupt source identity 0x40 read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: SPI2_INT 0 3 read-only IRQ17_SRC IRQ17_SRC IRQ17 (Reserved) interrupt source identity 0x44 read-only 0x00000000 0x00000000 IRQ18_SRC IRQ18_SRC IRQ18 (I2C0) interrupt source identity 0x48 read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: I2C0_INT 0 3 read-only IRQ19_SRC IRQ19_SRC IRQ19 (I2C1) interrupt source identity 0x4C read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: I2C1_INT 0 3 read-only IRQ20_SRC IRQ20_SRC IRQ20 (Reserved) interrupt source identity 0x50 read-only 0x00000000 0x00000000 IRQ21_SRC IRQ21_SRC IRQ21 (Reserved) interrupt source identity 0x54 read-only 0x00000000 0x00000000 IRQ22_SRC IRQ22_SRC IRQ22 (Reserved ) interrupt source identity 0x58 read-only 0x00000000 0x00000000 IRQ23_SRC IRQ23_SRC IRQ23 (USBD) interrupt source identity 0x5C read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: USB_INT 0 3 read-only IRQ24_SRC IRQ24_SRC IRQ24 (PS/2) interrupt source identity 0x60 read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: PS2_INT 0 3 read-only IRQ25_SRC IRQ25_SRC IRQ25 (Reserved) interrupt source identity 0x64 read-only 0x00000000 0x00000000 IRQ26_SRC IRQ26_SRC IRQ26 (PDMA) interrupt source identity 0x68 read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: PDMA_INT 0 3 read-only IRQ27_SRC IRQ27_SRC IRQ27 (I2S) interrupt source identity 0x6C read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: I2S_INT 0 3 read-only IRQ28_SRC IRQ28_SRC IRQ28 (PWRWU) interrupt source identity 0x70 read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: PWRWU_INT 0 3 read-only IRQ29_SRC IRQ29_SRC IRQ29 (ADC) interrupt source identity 0x74 read-only 0x00000000 0x00000000 INT_SRC Bit2: 0\nBit1: 0\nBit0: ADC_INT 0 3 read-only IRQ30_SRC IRQ30_SRC IRQ30 (Reserved) interrupt source identity 0x78 read-only 0x00000000 0x00000000 IRQ31_SRC IRQ31_SRC IRQ31 (Reserved) interrupt source identity 0x7C read-only 0x00000000 0x00000000 NMI_SEL NMI_SEL NMI source interrupt select control register 0x80 read-write 0x00000000 0xFFFFFFFF NMI_SEL NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL. 0 5 read-write NMI_EN NMI Interrupt Enable\n 8 1 0 NMI interrupt Disabled #0 1 NMI interrupt Enabled #1 read-write MCU_IRQ MCU_IRQ MCU IRQ Number identity register 0x84 read-write 0x00000000 0xFFFFFFFF MCU_IRQ MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0. There are two modes to generate interrupt to Cortex-M0, Normal mode and Test mode.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them and then interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0: Set MCU_IRQ[n] 1 will generate an interrupt to Cortex_M0 NVIC[n].\nWhen the MCU_IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_bit[n] will clear the interrupt and setting MCU_IRQ[n] 0 has no effect. 0 32 read-write GCR GCR Register Map GCR 0x50000000 0x0 0x10 registers 0x18 0x4 registers 0x24 0x4 registers 0x30 0x10 registers 0x44 0x4 registers 0x50 0x8 registers 0xA0 0x4 registers 0xC0 0x8 registers 0xCC 0x4 registers 0x100 0x4 registers PDID PDID Part Device Identification Number Register 0x0 read-only 0x00012300 0xFFFFFF00 PDID Part Device Identification Number\nThis register reflects the device part number code. S/W can read this register to identify which device is used. 0 32 read-only RSTSRC RSTSRC System Reset Source Register 0x4 read-write 0x00000000 0xFFFFFF00 RSTS_POR The RSTS_POR flag is set by the "reset signal" from the Power-On Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero. 0 1 0 No reset from POR or CHIP_RST #0 1 Power-On Reset (POR) or CHIP_RST had issued the reset signal to reset the system #1 read-write RSTS_RESET The RSTS_RESET flag is set by the "reset signal" from the /RESET pin to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero. 1 1 0 No reset from /RESET pin #0 1 Pin /RESET had issued the reset signal to reset the system #1 read-write RSTS_WDT The RSTS_WDT flag is set by the "reset signal" from the watchdog timer to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero. 2 1 0 No reset from watchdog timer #0 1 Watchdog timer had issued the reset signal to reset the system #1 read-write RSTS_LVR The RSTS_LVR flag is set by the "reset signal" from the Low-Voltage-Reset controller to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero. 3 1 0 No reset from LVR #0 1 LVR controller had issued the reset signal to reset the system #1 read-write RSTS_BOD The RSTS_BOD flag is set by the "reset signal" from the Brown-out-Detector to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero. 4 1 0 No reset from BOD #0 1 BOD had issued the reset signal to reset the system #1 read-write RSTS_SYS The RSTS_SYS flag is set by the "reset signal" from the Cortex_M0 kernel to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero. 5 1 0 No reset from Cortex_M0 #0 1 Cortex_M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex_M0 kernel #1 read-write RSTS_CPU The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC).\nSoftware can write 1 to clear this bit to zero. 7 1 0 No reset from CPU #0 1 Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1 #1 read-write IPRSTC1 IPRSTC1 IP Reset Control Register1 0x8 read-write 0x00000000 0xFFFFFFFF CHIP_RST CHIP One-shot Reset (Write-protection Bit)\nSetting this bit will reset the whole chip, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.\nFor the difference between CHIP_RST and SYSRESETREQ, please refer to section 5.2.2.\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100\n 0 1 0 CHIP normal operation #0 1 CHIP one-shot reset #1 read-write CPU_RST CPU kernel one-shot reset (Write-protection Bit)\nSetting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles\nThis bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100\n 1 1 0 CPU normal operation #0 1 CPU one-shot reset #1 read-write PDMA_RST PDMA Controller Reset (Write-protection)\nSetting this bit to 1 will generate a reset signal to the PDMA. User need to set this bit to 0 to release from reset state.\nThis bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.\n 2 1 0 PDMA controller normal operation #0 1 PDMA controller reset #1 read-write IPRSTC2 IPRSTC2 IP Reset Control Register2 0xC read-write 0x00000000 0xFFFFFFFF GPIO_RST GPIO controller Reset\n 1 1 0 GPIO controller normal operation #0 1 GPIO controller reset #1 read-write TMR0_RST Timer0 controller Reset\n 2 1 0 Timer0 controller normal operation #0 1 Timer0 controller reset #1 read-write TMR1_RST Timer1 controller Reset\n 3 1 0 Timer1 controller normal operation #0 1 Timer1 controller reset #1 read-write TMR2_RST Timer2 controller Reset\n 4 1 0 Timer2 controller normal operation #0 1 Timer2 controller reset #1 read-write TMR3_RST Timer3 controller Reset\n 5 1 0 Timer3 controller normal operation #0 1 Timer3 controller reset #1 read-write I2C0_RST I2C0 controller Reset\n 8 1 0 I2C0 controller normal operation #0 1 I2C0 controller reset #1 read-write I2C1_RST I2C1 controller Reset\n 9 1 0 I2C1 controller normal operation #0 1 I2C1 controller reset #1 read-write SPI0_RST SPI0 controller Reset\n 12 1 0 SPI0 controller normal operation #0 1 SPI0 controller reset #1 read-write SPI1_RST SPI1 controller Reset\n 13 1 0 SPI1 controller normal operation #0 1 SPI1 controller reset #1 read-write SPI2_RST SPI2 controller Reset \n 14 1 0 SPI2 controller normal operation #0 1 SPI2 controller reset #1 read-write UART0_RST UART0 controller Reset\n 16 1 0 UART0 controller normal operation #0 1 UART0 controller reset #1 read-write UART1_RST UART1 controller Reset\n 17 1 0 UART1 controller normal operation #0 1 UART1 controller reset #1 read-write PWM03_RST PWM03 controller Reset\n 20 1 0 PWM03 controller normal operation #0 1 PWM03 controller reset #1 read-write PS2_RST PS/2 Controller Reset\n 23 1 0 PS/2 controller normal operation #0 1 PS/2 controller reset #1 read-write USBD_RST USB Device Controller Reset\n 27 1 0 USB device controller normal operation #0 1 USB device controller reset #1 read-write ADC_RST ADC Controller Reset\n 28 1 0 ADC controller normal operation #0 1 ADC controller reset #1 read-write I2S_RST I2S Controller Reset\n 29 1 0 I2S controller normal operation #0 1 I2S controller reset #1 read-write BODCR BODCR Brown-out Detector Control Register 0x18 read-write 0x00000080 0xFFFFFFF0 BOD_EN Brown-out Detector Enable (Write-protection Bit)\nThe default value is set by flash controller user configuration register config0 bit[23].\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 0 1 0 Brown-out Detector function Disabled #0 1 Brown-out Detector function Enabled #1 read-write BOD_VL Brown-out Detector Threshold Voltage Selection (Write-protection Bits)\n 1 2 read-write BOD_RSTEN Brown-out Reset Enable (Write-protection Bit)\nWhile the BOD function is enabled (BOD_EN high) and BOD interrupt function is enabled (BOD_RSTEN low), BOD will assert an interrupt if BOD_OUT is high. BOD interrupt will keep till to the BOD_EN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BOD_EN low).\nThe default value is set by flash controller user configuration register config0 bit[20].\nThis bit is the protected bit. It means programming this needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 3 1 0 Brown-out "INTERRUPT" function Enabled #0 1 Brown-out "RESET" function Enabled #1 read-write BOD_INTF Brown-out Detector Interrupt Flag\nSoftware can write 1 to clear this bit to zero. 4 1 0 Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting #0 1 When Brown-out Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled #1 read-write BOD_LPM Brown-out Detector Low power Mode (Write-protection Bit)\nThe BOD consumes about 100 uA in Normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.\nThis bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 5 1 0 BOD operated in Normal mode (Default) #0 1 BOD low power mode Enabled #1 read-write BOD_OUT Brown-out Detector Output Status\n 6 1 0 Brown-out Detector output status is 0, which means the detected voltage is higher than BOD_VL setting or BOD_EN is 0 #0 1 Brown-out Detector output status is 1, which means the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0, BOD function disabled , this bit always responds to 0 #1 read-write LVR_EN Low Voltage Reset Enable (Write-protection Bit)\nThe LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 7 1 0 Low Voltage Reset function Disabled #0 1 Low Voltage Reset function Enabled- After enabling the bit, the LVR function will be active with 100uS delay for LVR output stable (Default) #1 read-write PORCR PORCR Power-On-Reset Controller Register 0x24 read-write 0x00000000 0xFFFFFF00 POR_DIS_CODE The register is used for the Power-On-Reset enable control (Write-protection Bits)\nWhen powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.\nThe POR function will become active again when this field is set to another value or chip is reset by other reset source, including:\n/RESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 0 16 read-write GPA_MFP GPA_MFP GPIOA Multiple Function and Input Type Control Register 0x30 read-write 0x00000000 0xFFFFFFFF GPA_MFP10 PA.10 Pin Function Selection\n 10 1 read-write GPA_MFP11 PA.11 Pin Function Selection\n 11 1 read-write GPA_MFP12 PA.12 Pin Function Selection\n 12 1 read-write GPA_MFP13 PA.13 Pin Function Selection\n 13 1 read-write GPA_MFP14 PA.14 Pin Function Selection\n 14 1 read-write GPA_MFP15 PA.15 Pin Function Selection\n 15 1 read-write GPA_TYPEn GPA[9:0] are reserved in this chip. 16 16 0 GPIOA[15:0] I/O input Schmitt Trigger function Disabled 0 1 GPIOA[15:0] I/O input Schmitt Trigger function Enabled 1 read-write GPB_MFP GPB_MFP GPIOB Multiple Function and Input Type Control Register 0x34 read-write 0x00000000 0xFFFFFFFF GPB_MFP0 PB.0 Pin Function Selection\n 0 1 0 GPIOB[0] is selected to the pin PB.0 #0 1 UART0 RXD0 function is selected to the pin PB.0 #1 read-write GPB_MFP1 PB.1 Pin Function Selection\n 1 1 0 GPIOB[1] is selected to the pin PB.1 #0 1 UART0 TXD0 function is selected to the pin PB.1 #1 read-write GPB_MFP2 PB.2 Pin Function Selection\n 2 1 read-write GPB_MFP3 PB.3 Pin Function Selection\n 3 1 read-write GPB_MFP4 PB.4 Pin Function Selection\n 4 1 read-write GPB_MFP5 PB. 5 1 read-write GPB_MFP6 PB.6 Pin Function Selection\n 6 1 read-write GPB_MFP7 PB.7 Pin Function Selection\n 7 1 read-write GPB_MFP8 PB.8 Pin Function Selection\n 8 1 read-write GPB_MFP9 PB.9 Pin Function Selection\n 9 1 read-write GPB_MFP10 PB.10 Pin Function Selection\n 10 1 read-write GPB_MFP12 PB.12 Pin Function Selection\n 12 1 read-write GPB_MFP13 PB.13 Pin Function Selection\n 13 1 read-write GPB_MFP14 PB.14 Pin Function Selection\n 14 1 read-write GPB_MFP15 PB.15 Pin Function Selection\n 15 1 read-write GPB_TYPEn 16 16 0 GPIOB[15:0] I/O input Schmitt Trigger function Disabled 0 1 GPIOB[15:0] I/O input Schmitt Trigger function Enabled 1 read-write GPC_MFP GPC_MFP GPIOC Multiple Function and Input Type Control Register 0x38 read-write 0x00000000 0xFFFFFFFF GPC_MFP0 PC.0 Pin Function Selection\n 0 1 read-write GPC_MFP1 PC.1 Pin Function Selection\n 1 1 read-write GPC_MFP2 PC.2 Pin Function Selection\n 2 1 read-write GPC_MFP3 PC.3 Pin Function Selection\n 3 1 read-write GPC_MFP4 PC.4 Pin Function Selection\n 4 1 read-write GPC_MFP5 PC.5 Pin Function Selection\n 5 1 read-write GPC_MFP8 PC.8 Pin Function Selection\n 8 1 read-write GPC_MFP9 PC.9 Pin Function Selection\n 9 1 0 GPIOC[9] is selected to the pin PC.9 #0 1 SPICLK1 (SPI1) function is selected to the pin PC.9 #1 read-write GPC_MFP10 PC.10 Pin Function Selection\n 10 1 0 The GPIOC[10] is selected to the pin PC.10 #0 1 MISO10 (SPI1 master input, slave output pin-0) function is selected to the pin PC.10 #1 read-write GPC_MFP11 PC.11 Pin Function Selection\n 11 1 0 GPIOC[11] is selected to the pin PC.11 #0 1 MOSI10 (SPI1 master output, slave input pin-0) function is selected to the pin PC.11 #1 read-write GPC_MFP12 PC.12 Pin Function Selection\n 12 1 read-write GPC_MFP13 PC.13 Pin Function Selection\n 13 1 read-write GPC_TYPEn 16 16 0 GPIOC[15:0] I/O input Schmitt Trigger function Disabled 0 1 GPIOC[15:0] I/O input Schmitt Trigger function Enabled 1 read-write GPD_MFP GPD_MFP GPIOD Multiple Function and Input Type Control Register 0x3C read-write 0x00000000 0xFFFFFFFF GPD_MFP0 PD.0 Pin Function Selection \n 0 1 read-write GPD_MFP1 PD.1 Pin Function Selection\n 1 1 read-write GPD_MFP2 PD.2 Pin Function Selection\n 2 1 read-write GPD_MFP3 PD.3 Pin Function Selection\n 3 1 read-write GPD_MFP4 PD.4 Pin Function Selection \n 4 1 read-write GPD_MFP5 PD.5 Pin Function Selection \n 5 1 read-write GPD_MFP8 PD.8 Pin Function Selection\n 8 1 0 GPIOD[8] is selected to the pin PD8 #0 1 MOSI10 (SPI1 master output, slave input pin-0) function is selected to the pin PD8 #1 read-write GPD_MFP9 PD.9 Pin Function Selection\n 9 1 read-write GPD_MFP10 PD.10 Pin Function Selection \n 10 1 0 GPIOD[10] is selected to the pin PD.10 #0 1 CLKO function is selected to the pin PD.10 #1 read-write GPD_MFP11 PD.11 Pin Function Selection\n 11 1 0 GPIOD[11] is selected to the pin PD.11 #0 1 /INT1 function is selected to the pin PD.11 #1 read-write GPD_TYPEn 16 16 0 GPIOD[15:0] I/O input Schmitt Trigger function Disabled 0 1 GPIOD[15:0] I/O input Schmitt Trigger function Enabled 1 read-write GPF_MFP GPF_MFP GPIOF Multiple Function and Input Type Control Register 0x44 read-write 0x00000000 0xFFFFFFF0 GPF_MFP0 PF.0 Pin Function Selection\n 0 1 0 GPIOF[0] is selected to the pin PF.0 #0 1 XT1_OUT function is selected to the pin PF.0 #1 read-write GPF_MFP1 PF.1 Pin Function Selection \n 1 1 0 GPIOF[1] is selected to the pin PF.1 #0 1 XT1_IN function is selected to the pin PF.1 #1 read-write GPF_MFP2 PF.2 Pin Function Selection\n 2 1 read-write GPF_MFP3 PF.3 Pin Function Selection \n 3 1 read-write GPF_TYPEn 16 4 0 GPIOF[3:0] I/O input Schmitt Trigger function Disabled 0 1 GPIOF[3:0] I/O input Schmitt Trigger function Enabled 1 read-write ALT_MFP ALT_MFP Alternative Multiple Function Pin Control Register 0x50 read-write 0x00000000 0xFFFFFFFF PB10_MFP1 PB.10 Pin Alternate Function Selection\n 0 1 read-write PB9_MFP1 PB.9 Pin Alternate Function Selection\n 1 1 read-write PC0_MFP1 PC.0 Pin Function Selection\n 5 1 read-write PC1_MFP1 PC.1 Pin Alternate Function Selection\n 6 1 read-write PC2_MFP1 PC.2 Pin Alternate Function Selection\n 7 1 read-write PC3_MFP1 PC.3 Pin Alternate Function Selection\n 8 1 read-write PA15_MFP1 PA.15 Pin Alternate Function Selection\n 9 1 read-write PB12_MFP1 PB.12 Pin Alternate Function Selection\n 10 1 read-write PA11_MFP1 PA.11 Pin Function Selection\n 11 1 read-write PA10_MFP1 PA.10 Pin Function Selection\n 12 1 read-write PB4_MFP1 PB.4 Pin Function Selection\n 15 1 read-write PB7_MFP1 PB.7 Pin Alternate Function Selection\n 16 1 read-write PB6_MFP1 PB.6 Pin Alternate Function Selection\n 17 1 read-write PB5_MFP1 PB. 18 1 read-write PC12_MFP1 PC.12 Pin Function Selection\n 20 1 read-write PC13_MFP1 PC.13 Pin Function Selection\n 21 1 read-write PB15_MFP1 PB.15 Pin Alternate Function Selection\n 24 1 read-write PB2_MFP1 PB.2 Pin Alternate Function Selection\n 26 1 read-write PB3_MFP1 PB.3 Pin Alternate Function Selection\n 27 1 read-write PC4_MFP1 PC.4 Pin Function Selection\n 29 1 read-write PC5_MFP1 PC.5 Pin Function Selection\n 30 1 read-write ALT_MFP1 ALT_MFP1 Alternative Multiple Function Pin Control Register 1 0x54 read-write 0x00000000 0xFFFFFFFF PD0_MFP1 PD.0 Pin Function Selection \n 16 1 read-write PD1_MFP1 PD.1 Pin Function Selection\n 17 1 read-write PD2_MFP1 PD.2 Pin Function Selection\n 18 1 read-write PD3_MFP1 PD.3 Pin Function Selection\n 19 1 read-write PD4_MFP1 PD.4 Pin Function Selection \n 20 1 read-write PD5_MFP1 PD.5 Pin Function Selection \n 21 1 read-write PF2_MFP1 PF.2 Pin Function Selection\n 24 2 read-write PF3_MFP1 PF.3 Pin Function Selection \n 26 2 read-write DFP_CSR DFP_CSR Pin Conflict Status 0xA0 read-only 0x00000000 0xFFFFFFFF DFP0_CST Conflict Status of PD.9\n 0 1 0 PD.9 worked normally #0 1 PD.9 is conflicted #1 read-only DFP1_CST Conflict Status of PD.10\n 1 1 0 PD.10 worked normally #0 1 PD.10 is conflicted #1 read-only DFP2_CST Conflict Status of PD.11\n 2 1 0 PD.11 worked normally #0 1 PD.11 is conflicted #1 read-only DFP3_CST Conflict Status of PB.4\n 3 1 0 PB.4 worked normally #0 1 PB.4 is conflicted #1 read-only DFP4_CST Conflict Status of PB.5\n 4 1 0 PB.5 worked normally #0 1 PB.5 is conflicted #1 read-only DFP5_CST Conflict Status of PB.6\n 5 1 0 PB.6 worked normally #0 1 PB.6 is conflicted #1 read-only DFP6_CST Conflict Status of PB.7\n 6 1 0 PB.7 worked normally #0 1 PB.7 is conflicted #1 read-only GPA_IOCR GPA_IOCR GPIOA IO Control Register 0xC0 read-write 0x00000000 0xFFFFFFFF GPA10_DS PA.10 Pin Driving Strength Selection\n 10 1 0 PA.10 strong driving strength mode Disabled #0 1 PA.10 strong driving strength mode Enabled #1 read-write GPA11_DS PA.11 Pin Driving Strength Selection\n 11 1 0 PA.11 strong driving strength mode Disabled #0 1 PA.11 strong driving strength mode Enabled #1 read-write GPB_IOCR GPB_IOCR GPIOB IO Control Register 0xC4 read-write 0x00000000 0xFFFFFFFF GPB4_DS PB.4 Pin Driving Strength Selection\n 4 1 0 PB.4 strong driving strength mode Disabled #0 1 PB.4 strong driving strength mode Enabled #1 read-write GPB5_DS PB.5 Pin Driving Strength Selection\n 5 1 0 PB.5 strong driving strength mode Disabled #0 1 PB.5 strong driving strength mode Enabled #1 read-write GPB6_DS PB.6 Pin Driving Strength Selection\n 6 1 0 PB.6 strong driving strength mode Disabled #0 1 PB.6 strong driving strength mode Enabled #1 read-write GPB7_DS PB.7 Pin Driving Strength Selection\n 7 1 0 PB.7 strong driving strength mode Disabled #0 1 PB.7 strong driving strength mode Enabled #1 read-write GPB8_DS PB.8 Pin Driving Strength Selection\n 8 1 0 PB.8 strong driving strength mode Disabled #0 1 PB.8 strong driving strength mode Enabled #1 read-write GPB12_DS PB.12 Pin Driving Strength Selection\n 12 1 0 PB.12 strong driving strength mode Disabled #0 1 PB.12 strong driving strength mode Enabled #1 read-write GPB13_DS PB.13 Pin Driving Strength Selection\n 13 1 0 PB.13 strong driving strength mode Disabled #0 1 PB.13 strong driving strength mode Enabled #1 read-write GPB14_DS PB.14 Pin Driving Strength Selection\n 14 1 0 PB.14 strong driving strength mode Disabled #0 1 PB.14 strong driving strength mode Enabled #1 read-write GPD_IOCR GPD_IOCR GPIOD IO Control Register 0xCC read-write 0x00000000 0xFFFFFFFF GPD8_DS PD.8 Pin Driving Strength Selection\n 8 1 0 PD.8 strong driving strength mode Disabled #0 1 PD.8 strong driving strength mode Enabled #1 read-write GPD9_DS PD.9 Pin Driving Strength Selection\n 9 1 0 PD.9 strong driving strength mode Disabled #0 1 PD.9 strong driving strength mode Enabled #1 read-write GPD10_DS PD.10 Pin Driving Strength Selection\n 10 1 0 PD.10 strong driving strength mode Disabled #0 1 PD.10 strong driving strength mode Enabled #1 read-write GPD11_DS PD.11 Pin Driving Strength Selection\n 11 1 0 PD.11 strong driving strength mode Disabled #0 1 PD.11 strong driving strength mode Enabled #1 read-write REGWRPROT REGWRPROT Register Write Protect register 0x100 read-write 0x00000000 0xFFFFFFFF REGPROTDIS Register Write-Protection Disable index (Read Only)\nThe Protected registers are:\nIPRSTC1: address 0x5000_0008\nBODCR: address 0x5000_0018\nPORCR: address 0x5000_0024\nPWRCON: address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear) \nAPBCLK bit[0]: address 0x5000_0208 (bit[0] is watchdog clock enabled)\nCLKSEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source select)\nCLKSEL1 bit[1:0]: address 0x5000_0214 (for watchdog clock source select)\nISPCON: address 0x5000_C000 (Flash ISP Control register)\nWTCR: address 0x4000_4000\nFATCON: address 0x5000_C018 0 1 0 Write-protection Enabled for writing protected registers. Any write to the protected register is ignored #0 1 Write-protection Disabled for writing protected registers #1 read-only REGWRPROT Register Write-Protection Code (Write Only)\nSome registers have write-protection function. Writing these registers has to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write. 0 8 write-only CLK CLK Register Map CLK 0x50000200 0x0 0x28 registers 0x2C 0x4 registers PWRCON PWRCON System Power-down Control Register 0x0 read-write 0x00000010 0xFFFFFFF0 XTL12M_EN External 4~24 MHz High Speed Crystal Enable (Write-protection Bit)\nThe bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external 4~24 MHz high speed crystal, this bit is set to 1 automatically\n 0 1 0 External 4~24 MHz high speed crystal Disabled #0 1 External 4~24 MHz high speed crystal Enabled #1 read-write OSC22M_EN Internal 22.1184 MHz High Speed Oscillator Enable (Write-protection Bit)\n 2 1 0 Internal 22.1184 MHz high speed oscillator Disabled #0 1 Internal 22.1184 MHz high speed oscillator Enabled #1 read-write OSC10K_EN Internal 10 kHz Low Speed Oscillator Enable (Write-protection Bit)\n 3 1 0 Internal 10 kHz low speed oscillator Disabled #0 1 Internal 10 kHz low speed oscillator Enabled #1 read-write PD_WU_DLY Enable the Wake-up Delay Counter (Write-protection Bit)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high speed oscillator.\n 4 1 0 Clock cycles delay Disabled #0 1 Clock cycles delay Enabled #1 read-write PD_WU_INT_EN Power-down Mode Wake-up Interrupt Enable (Write-protection Bit)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high. 5 1 0 Disabled #0 1 Enabled #1 read-write PD_WU_STS Power-down Mode Wake-up Interrupt Status\nSet by "Power-down wake-up event", which indicates that resume from Power-down mode" \nThe flag is set if the GPIO, USB, UART, WDT, CAN, ACMP or BOD wake-up occurred.\nWrite 1 to clear the bit to zero.\nNote: This bit works only when PD_WU_INT_EN (PWRCON[5]) set to 1. 6 1 read-write PWR_DOWN_EN System Power-down Enable Bit (Write-protection Bit)\nWhen this bit is set to 1, the chip Power-down mode is enabled and chip Power-down behavior will depend on the PD_WAIT_CPU bit.\n(a) If the PD_WAIT_CPU is 0, the chip enters Power-down mode immediately after the PWR_DOWN_EN bit set.\n(b) If the PD_WAIT_CPU is 1, the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode\nWhen chip wakes up from Power-down mode, this bit is auto cleared. User needs to set this bit again for next Power-down.\nIn Power-down mode, external 4~24 MHz high speed crystal and the internal 22.1184 MHz high speed oscillator will be disabled in this mode, but the internal 10 kHz low speed oscillator is not controlled by Power-down mode.\nIn Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from the internal 10 kHz low speed oscillator.\n 7 1 0 Chip operating normally or chip in Idle mode because of WFI command #0 1 Chip entering the Power-down mode instantly or wait CPU sleep command WFI #1 read-write PD_WAIT_CPU Power-down Entry Conditions Control (Write-protection Bit)\n 8 1 0 Chip entering Power-down mode when the PWR_DOWN_EN bit is set to 1 #0 1 Chip entering Power-down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction #1 read-write AHBCLK AHBCLK AHB Devices Clock Enable Control Register 0x4 read-write 0x0000000D 0xFFFFFFFF PDMA_EN PDMA Controller Clock Enable Control\n 1 1 0 PDMA engine clock Disabled #0 1 PDMA engine clock Enabled #1 read-write ISP_EN Flash ISP Controller Clock Enable Control\n 2 1 0 Flash ISP engine clock Disabled #0 1 Flash ISP engine clock Enabled #1 read-write APBCLK APBCLK APB Devices Clock Enable Control Register 0x8 read-write 0x00000000 0xFFFFFFF0 WDT_EN Watchdog Timer Clock Enable (Write-protection Bit)\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.\n 0 1 0 Watchdog Timer Clock Disabled #0 1 Watchdog Timer Clock Enabled #1 read-write TMR0_EN Timer0 Clock Enable\n 2 1 0 Timer0 clock Disabled #0 1 Timer0 clock Enabled #1 read-write TMR1_EN Timer1 Clock Enable\n 3 1 0 Timer1 clock Disabled #0 1 Timer1 clock Enabled #1 read-write TMR2_EN Timer2 Clock Enable\n 4 1 0 Timer2 clock Disabled #0 1 Timer2 clock Enabled #1 read-write TMR3_EN Timer3 Clock Enable\n 5 1 0 Timer3 clock Disabled #0 1 Timer3 clock Enabled #1 read-write FDIV_EN Frequency Divider Output Clock Enable\n 6 1 0 FDIV clock Disabled #0 1 FDIV clock Enabled #1 read-write I2C0_EN I2C0 Clock Enable\n 8 1 0 I2C0 clock Disabled #0 1 I2C0 clock Enabled #1 read-write I2C1_EN I2C1 Clock Enable\n 9 1 0 I2C1 clock Disabled #0 1 I2C1 clock Enabled #1 read-write SPI0_EN SPI0 Clock Enable\n 12 1 0 SPI0 clock Disabled #0 1 SPI0 clock Enabled #1 read-write SPI1_EN SPI1 Clock Enable\n 13 1 0 SPI1 clock Disabled #0 1 SPI1 clock Enabled #1 read-write SPI2_EN SPI2 Clock Enable\n 14 1 0 SPI2 clock Disabled #0 1 SPI2 clock Enabled #1 read-write UART0_EN UART0 Clock Enable\n 16 1 0 UART0 clock Disabled #0 1 UART0 clock Enabled #1 read-write UART1_EN UART1 Clock Enable\n 17 1 0 UART1 clock Disabled #0 1 UART1 clock Enabled #1 read-write PWM01_EN PWM_01 Clock Enable\n 20 1 0 PWM01 clock Disabled #0 1 PWM01 clock Enabled #1 read-write PWM23_EN PWM_23 Clock Enable\n 21 1 0 PWM23 clock Disabled #0 1 PWM23 clock Enabled #1 read-write USBD_EN USB 2.0 FS Device Controller Clock Enable\n 27 1 0 USB clock Disabled #0 1 USB clock Enabled #1 read-write ADC_EN Analog-Digital-Converter (ADC) Clock Enable\n 28 1 0 ADC clock Disabled #0 1 ADC clock Enabled #1 read-write I2S_EN I2S Clock Enable\n 29 1 0 I2S Clock Disabled #0 1 I2S Clock Enabled #1 read-write PS2_EN PS/2 Clock Enable\n 31 1 0 PS/2 clock Disabled #0 1 PS/2 clock Enabled #1 read-write CLKSTATUS CLKSTATUS Clock status monitor Register 0xC read-write 0x00000000 0xFFFFFF00 XTL12M_STB External 4~24 MHz High Speed Crystal Clock Source Stable Flag\nThis is read only bit. 0 1 0 External 4~24 MHz high speed crystal clock is not stable or disabled #0 1 External 4~24 MHz high speed crystal clock is stable #1 read-write PLL_STB Internal PLL Clock Source Stable Flag\nThis is read only bit. 2 1 0 Internal PLL clock is not stable or disabled #0 1 Internal PLL clock is stable #1 read-write OSC10K_STB Internal 10 kHz Low Speed Oscillator Clock Source Stable Flag\nThis is read only bit. 3 1 0 Internal 10 kHz low speed oscillator clock is not stable or disabled #0 1 Internal 10 kHz low speed oscillator clock is stable #1 read-write OSC22M_STB Internal 22.1184 MHz High Speed Oscillator Clock Source Stable Flag\nThis is read only bit 4 1 0 Internal 22.1184 MHz high speed oscillator clock is not stable or disabled #0 1 Internal 22.1184 MHz high speed oscillator clock is stable #1 read-write CLK_SW_FAIL Clock Switching Fail Flag (Write-protection Bit)\nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nWrite 1 to clear the bit to zero. 7 1 0 Clock switching success #0 1 Clock switching failed #1 read-write CLKSEL0 CLKSEL0 Clock Source Select Control Register 0 0x10 read-write 0x00000030 0xFFFFFFF0 HCLK_S HCLK Clock Source Selection (Write-protection Bits)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turn on\nThe 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.\nThese bits are protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.\n 0 3 0 Clock source from external 4~24 MHz high speed crystal clock #000 1 Clock source from PLL clock/2 #001 2 Clock source from PLL clock #010 3 Clock source from internal 10 kHz low speed oscillator clock #011 7 Clock source from internal 22.1184 MHz high speed oscillator clock #111 read-write STCLK_S Cortex_M0 SysTick Clock Source Selection (Write-protection Bits)\n 3 3 0 Clock source from external 4~24 MHz high speed crystal clock #000 2 Clock source from external 4~24 MHz high speed crystal clock/2 #010 3 Clock source from HCLK/2 #011 7 Clock source from internal 22.1184 MHz high speed oscillator clock/2 #111 read-write CLKSEL1 CLKSEL1 Clock Source Select Control Register 1 0x14 read-write 0xFFFFFFFF 0xFFFFFFFF WDT_S Watchdog Timer Clock Source Selection (Write-protection Bits)\nThese bits are protected bits and programming this needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.\n 0 2 2 Clock source from HCLK/2048 clock #10 3 Clock source from internal 10 kHz low speed oscillator clock #11 read-write ADC_S ADC Clock Source Selection\n 2 2 0 Clock source from external 4~24 MHz high speed crystal clock #00 1 Clock source from PLL clock #01 2 Clock source from HCLK #10 3 Clock source from internal 22.1184 MHz high speed oscillator clock #11 read-write SPI0_S SPI0 Clock Source Selection\n 4 1 0 Clock source from PLL clock #0 1 Clock source from HCLK #1 read-write SPI1_S SPI1 Clock Source Selection\n 5 1 0 Clock source from PLL clock #0 1 Clock source from HCLK #1 read-write SPI2_S SPI2 Clock Source Selection\n 6 1 0 Clock source from PLL clock #0 1 Clock source from HCLK #1 read-write TMR0_S TIMER0 Clock Source Selection\n 8 3 0 Clock source from external 4~24 MHz high speed crystal clock #000 2 Clock source from HCLK #010 3 Clock source from external clock source TM0 #011 4 Clock source from internal 10 kHz low speed oscillator clock #100 7 Clock source from internal 22.1184 MHz high speed oscillator clock #111 read-write TMR1_S TIMER1 Clock Source Selection\n 12 3 0 Clock source from external 4~24 MHz high speed crystal clock #000 2 Clock source from HCLK #010 3 Clock source from external clock source TM1 #011 4 Clock source from internal 10 kHz low speed oscillator clock #100 7 Clock source from internal 22.1184 MHz high speed oscillator clock #111 read-write TMR2_S TIMER2 Clock Source Selection\n 16 3 0 Clock source from external 4~24 MHz high speed crystal clock #000 2 Clock source from HCLK #010 3 Clock source from external clock source TM2 #011 4 Clock source from internal 10 kHz low speed oscillator clock #100 7 Clock source from internal 22.1184 MHz high speed oscillator clock #111 read-write TMR3_S TIMER3 Clock Source Selection\n 20 3 0 Clock source from external 4~24 MHz high speed crystal clock #000 2 Clock source from HCLK #010 3 Reserved #011 4 Clock source from internal 10 kHz low speed oscillator clock #100 7 Clock source from internal 22.1184 MHz high speed oscillator clock #111 read-write UART_S UART Clock Source Selection\n 24 2 0 Clock source from external 4~24 MHz high speed crystal clock #00 1 Clock source from PLL clock #01 3 Clock source from internal 22.1184 MHz high speed oscillator clock #11 read-write PWM01_S PWM0 and PWM1 Clock Source Select Bit [1:0]\nPWM0 and PWM1 use the same Engine clock source, and both of them use the same prescaler\nThe Engine clock source of PWM0 and PWM1 is defined by PWM01_S[2:0] and this field is combined by CLKSEL2[8] and CLKSEL1[29:28].\n 28 2 read-write PWM23_S PWM2 and PWM3 Clock Source Select Bit [1:0]\nPWM2 and PWM3 use the same Engine clock source, and both of them use the same prescaler.\nThe Engine clock source of PWM2 and PWM3 is defined by PWM23_S[2:0] and this field is combined by CLKSEL2[9] and CLKSEL1[31:30].\n 30 2 read-write CLKDIV CLKDIV Clock Divider Number Register 0x18 read-write 0x00000000 0xFFFFFFFF HCLK_N HCLK Clock Divide Number from HCLK Clock Source\n 0 4 read-write USB_N USB Clock Divide Number from PLL Clock\n 4 4 read-write UART_N UART Clock Divide Number from UART Clock Source\n 8 4 read-write ADC_N ADC Clock Divide Number from ADC Clock Source\n 16 8 read-write CLKSEL2 CLKSEL2 Clock Source Select Control Register 2 0x1C read-write 0x000000FF 0xFFFFFFFF I2S_S I2S Clock Source Selection\n 0 2 0 Clock source from external 4~24 MHz high speed crystal clock #00 1 Clock source from PLL clock #01 2 Clock source from HCLK #10 3 Clock source from internal 22.1184 MHz high speed oscillator clock #11 read-write FRQDIV_S Clock Divider Clock Source Selection\n 2 2 0 Clock source from external 4~24 MHz high speed crystal clock #00 1 Reserved #01 2 Clock source from HCLK #10 3 Clock source from internal 22.1184 MHz high speed oscillator clock #11 read-write PWM01_S PWM0 and PWM1 Clock Source Select Bit [2]\nPWM0 and PWM1 use the same Engine clock source, and both of them use the same prescaler.\nThe Engine clock source of PWM0 and PWM1 is defined by PWM01_S[2:0] and this field is combined by CLKSEL2[8] and CLKSEL1[29:28].\n 8 1 read-write PWM23_S PWM2 and PWM3 Clock Source Select Bit [2]\nPWM2 and PWM3 use the same Engine clock source, and both of them use the same prescaler.\nThe Engine clock source of PWM2 and PWM3 is defined by PWM23_S[2:0] and this field is combined by CLKSEL2[9] and CLKSEL1[31:30].\n 9 1 read-write WWDT_S Windowed-Watchdog Timer Clock Source Selection (Write-protection Bits)\n 16 2 2 Clock source from HCLK/2048 clock #10 3 Clock source from internal 10 kHz low speed oscillator clock #11 read-write PLLCON PLLCON PLL Control Register 0x20 read-write 0x0005C22E 0xFFFFFFFF FB_DV PLL Feedback Divider Control Pins\nRefer to the formulas below the table. 0 9 read-write IN_DV PLL Input Divider Control Pins\nRefer to the formulas below the table. 9 5 read-write OUT_DV PLL Output Divider Control Pins\nRefer to the formulas below the table. 14 2 read-write PD Power-down Mode\nIf the PWR_DOWN_EN bit set to 1 in PWRCON register, the PLL will also enter Power-down mode.\n 16 1 0 PLL is in Normal mode #0 1 PLL is in Power-down mode (default) #1 read-write BP PLL Bypass Control\n 17 1 0 PLL is in Normal mode (default) #0 1 PLL clock output is the same as clock input (XTALin) #1 read-write OE PLL OE (FOUT Enable) Pin Control\n 18 1 0 PLL FOUT Enabled #0 1 PLL FOUT is fixed low #1 read-write PLL_SRC PLL Source Clock Selection\n 19 1 0 PLL source clock from external 4~24 MHz high speed crystal #0 1 PLL source clock from internal 22.1184 MHz high speed oscillator #1 read-write FRQDIV FRQDIV Frequency Divider Control Register 0x24 read-write 0x00000000 0xFFFFFFFF FSEL Divider Output Frequency Select Bits\nThe formula of output frequency is:\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0]. 0 4 read-write DIVIDER_EN Frequency Divider Enable Bit\n 4 1 0 Frequency Divider Disabled #0 1 Frequency Divider Enabled #1 read-write APBDIV APBDIV APB Divider Control Register 0x2C read-write 0x00000000 0xFFFFFFFF APBDIV APB Divider Enable Bit\n 0 1 read-write FMC FMC Register Map FMC 0x5000C000 0x0 0x1C registers ISPCON ISPCON ISP Control Register 0x0 read-write 0x00000000 0xFFFFFFFF ISPEN ISP Enable (Write-protection Bit)\nISP function enable bit. Set this bit to enable ISP function.\n 0 1 0 ISP function Disabled #0 1 ISP function Enabled #1 read-write BS Boot Select (Write-protection Bit)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened\n 1 1 0 Boot from APROM #0 1 Boot from LDROM #1 read-write APUEN APROM Update Enable (Write-protection Bit)\n 3 1 0 APROM cannot be updated when the chip runs in APROM #0 1 APROM can be updated when the chip runs in APROM #1 read-write CFGUEN Enable Config-bits Update by ISP (Write-protection Bit)\n 4 1 0 ISP Disabled to update config-bits #0 1 ISP Enabled to update config-bits #1 read-write LDUEN LDROM Update Enable (Write-protection Bit)\nLDROM update enable bit.\n 5 1 0 LDROM cannot be updated #0 1 LDROM can be updated #1 read-write ISPFF ISP Fail Flag (Write-protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Destination address is illegal, such as over an available range.\nWrite 1 to clear. 6 1 read-write ISPADR ISPADR ISP Address Register 0x4 read-write 0x00000000 0xFFFFFFFF ISPADR ISP Address\nThe NuMicro( NUC123 Series is equipped with an embedded flash, and it supports word program only. ISPADR[1:0] must be kept 00b for ISP operation. 0 32 read-write ISPDAT ISPDAT ISP Data Register 0x8 read-write 0x00000000 0xFFFFFFFF ISPDAT ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation. 0 32 read-write ISPCMD ISPCMD ISP Command Register 0xC read-write 0x00000000 0xFFFFFFFF ISPCMD ISP Command\n 0 6 read-write ISPTRG ISPTRG ISP Trigger Control Register 0x10 read-write 0x00000000 0xFFFFFFFF ISPGO ISP Start Trigger\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\n 0 1 0 ISP operation is finished #0 1 ISP is progressed #1 read-write DFBADR DFBADR Data Flash Start Address 0x14 read-only 0x00000000 0x00000000 DFBADR Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nWhen DFVSEN is set to 0, the data flash is shared with APROM. The data flash size is defined by user configuration and the content of this register is loaded from Config1.\nWhen DFVSEN is set to 1, the data flash size is fixed as 4K and the start address can be read from this register is fixed at 0x0001_F000. 0 32 read-only FATCON FATCON Flash Access Time Control Register 0x18 read-write 0x00000000 0xFFFFFFFF LFOM Low Frequency Optimization Mode (Write-protection Bit)\nWhen chip operation frequency is lower than 25 MHz, chip can work more efficiently by setting this bit to 1\n 4 1 0 Low Frequency Optimization mode Disabled #0 1 Low Frequency Optimization mode Enabled #1 read-write MFOM Middle Frequency Optimization Mode (Write-protection Bit)\nWhen chip operation frequency is lower than 50 MHz, chip can work more efficiently by setting this bit to 1\n 6 1 0 Middle Frequency Optimization mode Disabled #0 1 Middle Frequency Optimization mode Enabled #1 read-write USB USB Register Map USB 0x40060000 0x0 0x1C registers 0x90 0x4 registers 0xA4 0x4 registers 0x500 0x80 registers USB_INTEN USB_INTEN USB Interrupt Enable Register 0x0 read-write 0x00000000 0xFFFFFFFF BUS_IE Bus Event Interrupt Enable\n 0 1 0 BUS event interrupt Disabled #0 1 BUS event interrupt Enabled #1 read-write USB_IE USB Event Interrupt Enable\n 1 1 0 USB event interrupt Disabled #0 1 USB event interrupt Enabled #1 read-write FLDET_IE Floating Detected Interrupt Enable\n 2 1 0 Floating detect Interrupt Disabled #0 1 Floating detect Interrupt Enabled #1 read-write WAKEUP_IE USB Wake-up Interrupt Enable\n 3 1 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 read-write WAKEUP_EN Wake-up Function Enable\n 8 1 0 USB wake-up function Disabled #0 1 USB wake-up function Enabled #1 read-write INNAK_EN Active NAK Function and its Status in IN Token\n 15 1 0 NAK status wasn't updated into the endpoint status register when it was set to 0. It also disables the interrupt event when device responds NAK after receiving IN token #0 1 NAK status is updated into the endpoint status register, USB_EPSTS, when it is set to 1 and there is NAK response in IN token. It also enables the interrupt event when the device responds NAK after receiving IN token #1 read-write USB_INTSTS USB_INTSTS USB Interrupt Event Status Register 0x4 read-write 0x00000000 0xFFFFFFFF BUS_STS BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus.\n 0 1 0 No BUS event occurred #0 1 Bus event occurred; check USB_ATTR[3:0] to know which kind of bus event was occurred, cleared by writing 1 to USB_INTSTS[0] #1 read-write USB_STS USB event Interrupt Status\nThe USB event includes the Setup Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.\n 1 1 0 No USB event occurred #0 1 USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[1] or EPSTS0~5 and SETUP (USB_INTSTS[31]) #1 read-write FLDET_STS Floating Detected Interrupt Status\n 2 1 0 There is not attached/detached event in the USB #0 1 There is attached/detached event in the USB bus and it is cleared by writing 1 to USB_INTSTS[2] #1 read-write WAKEUP_STS Wake-up Interrupt Status\n 3 1 0 No Wake-up event occurred #0 1 Wake-up event occurred, cleared by writing 1 to USB_INTSTS[3] #1 read-write EPEVT0 Endpoint 0's USB Event Status\n 16 1 0 No event occurred on Endpoint 0 #0 1 USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[16] or USB_INTSTS[1] #1 read-write EPEVT1 Endpoint 1's USB Event Status\n 17 1 0 No event occurred on Endpoint 1 #0 1 USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[17] or USB_INTSTS[1] #1 read-write EPEVT2 Endpoint 2's USB Event Status\n 18 1 0 No event occurred on Endpoint 2 #0 1 USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[18] or USB_INTSTS[1] #1 read-write EPEVT3 Endpoint 3's USB Event Status\n 19 1 0 No event occurred on Endpoint 3 #0 1 USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[19] or USB_INTSTS[1] #1 read-write EPEVT4 Endpoint 4's USB Event Status\n 20 1 0 No event occurred on Endpoint 4 #0 1 USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[20] or USB_INTSTS[1] #1 read-write EPEVT5 Endpoint 5's USB Event Status\n 21 1 0 No event occurred on Endpoint 5 #0 1 USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[21] or USB_INTSTS[1] #1 read-write EPEVT6 Endpoint 6's USB Event Status\n 22 1 0 No event occurred on Endpoint 6 #0 1 USB event occurred on Endpoint 6, check USB_EPSTS[28:26] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[22] or USB_INTSTS[1] #1 read-write EPEVT7 Endpoint 7's USB Event Status\n 23 1 0 No event occurred in endpoint 7 #0 1 USB event occurred on Endpoint 7, check USB_EPSTS[31:29] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[23] or USB_INTSTS[1] #1 read-write SETUP Setup Event Status\n 31 1 0 No Setup event #0 1 Setup event occurred, and cleared by writing 1 to USB_INTSTS[31] #1 read-write USB_FADDR USB_FADDR USB Device Function Address Register 0x8 read-write 0x00000000 0xFFFFFFFF FADDR USB device's Function Address 0 7 read-write USB_EPSTS USB_EPSTS USB Endpoint Status Register 0xC read-only 0x00000000 0xFFFFFFFF OVERRUN Overrun\nIt indicates that the received data is over the maximum payload number or not.\n 7 1 0 No overrun #0 1 Out data is more than the Max Payload in MXPLD register or the Setup data is more than 8 Bytes #1 read-only EPSTS0 Endpoint 0 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n 8 3 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 read-only EPSTS1 Endpoint 1 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n 11 3 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 read-only EPSTS2 Endpoint 2 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n 14 3 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 read-only EPSTS3 Endpoint 3 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n 17 3 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 read-only EPSTS4 Endpoint 4 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n 20 3 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 read-only EPSTS5 Endpoint 5 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n 23 3 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 read-only EPSTS6 Endpoint 6 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n 26 3 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 read-only EPSTS7 Endpoint 7 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n 29 3 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 read-only USB_ATTR USB_ATTR USB Bus Status and Attribution Register 0x10 read-write 0x00000040 0xFFFFFFFF USBRST USB Reset Status\nIt is a read only bit. 0 1 0 No bus reset #0 1 Bus reset when SE0 (single-ended 0) more than 2.5 us #1 read-write SUSPEND Suspend Status\nIt is a read only bit. 1 1 0 No bus suspend #0 1 Bus idle more than 3ms, either cable is plugged off or host is sleeping #1 read-write RESUME Resume Status\nIt is a read only bit. 2 1 0 No bus resume #0 1 Resume from suspend #1 read-write TIME_OUT Time Out Status\nIt is a read only bit. 3 1 0 No time-out #0 1 No Bus response more than 18 bits time #1 read-write PHY_EN PHY Transceiver Function Enable\n 4 1 0 PHY transceiver function Disabled #0 1 PHY transceiver function Enabled #1 read-write RWAKEUP Remote Wake-up\n 5 1 0 Release the USB bus from K state #0 1 Force USB bus to K (USB_DP low, USB_DM: high) state, used for remote wake-up #1 read-write USB_EN USB Controller Enable\n 7 1 0 USB Controller Disabled #0 1 USB Controller Enabled #1 read-write DPPU_EN Pull-up resistor on USB_DP enable\n 8 1 0 the pull-up resistor in USB_DP bus Disabled #0 1 Pull-up resistor in USB_DP bus Enabled #1 read-write PWRDN Power-down PHY Transceiver, Low Active\n 9 1 0 Power-down related circuit of PHY transceiver #0 1 Turn-on related circuit of PHY transceiver #1 read-write BYTEM CPU access USB SRAM Size Mode Selection\n 10 1 0 Word Mode: The size of the transfer from CPU to USB SRAM can be Word only #0 1 Byte Mode: The size of the transfer from CPU to USB SRAM can be Byte only #1 read-write USB_FLDET USB_FLDET USB Floating Detected Register 0x14 read-only 0x00000000 0xFFFFFFFF FLDET Device Floating Detected\n 0 1 0 Controller isn't attached to the USB host #0 1 Controller is attached to the BUS #1 read-only USB_BUFSEG USB_BUFSEG Setup Token Buffer Segmentation Register 0x18 read-write 0x00000000 0xFFFFFFFF BUFSEG It is used to indicate the offset address for the Setup token with the USB SRAM starting address. The effective starting address is:\nUSB_SRAM address + { BUFSEG[8:3], 3'b000} \nNote: It is used for Setup token only. 3 6 read-write USB_DRVSE0 USB_DRVSE0 USB Drive SE0 Control Register 0x90 read-write 0x00000001 0xFFFFFFFF DRVSE0 Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_DP and USB_DM) are being pulled low.\n 0 1 0 None #0 1 Force USB PHY transceiver to drive SE0 #1 read-write USB_PDMA USB_PDMA USB PDMA Control Register 0xA4 read-write 0x00000000 0xFFFFFFFF PDMA_RW PDMA_RW\n 0 1 0 The PDMA will read data from memory to USB buffer #0 1 The PDMA will read data from USB buffer to memory #1 read-write PDMA_EN PDMA Function Enable\nThis bit will be automatically cleared after PDMA transfer done. 1 1 0 The PDMA function is not active #0 1 The PDMA function in USB is active #1 read-write USB_BUFSEG0 USB_BUFSEG0 Endpoint 0 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible. 0x500 read-write 0x00000000 0xFFFFFFFF BUFSEGx It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is:\nUSB_SRAM address + { BUFSEG[8:3], 3'b000}\nRefer to section 5.4.4.7 for the endpoint SRAM structure and its description. 3 6 read-write USB_MXPLD0 USB_MXPLD0 Endpoint 0 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible. 0x504 read-write 0x00000000 0xFFFFFFFF MXPLD Maximal Payload\nIt is used to define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It is also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.\n(1) When the register is written by CPU, \nFor IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.\nFor OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.\n(2) When the register is read by CPU,\nFor IN token, the value of MXPLD indicates the data length be transmitted to host\nFor OUT token, the value of MXPLD indicates the actual data length receiving from host.\nNote: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 0 9 read-write USB_CFG0 USB_CFG0 Endpoint 0 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible. 0x508 read-write 0x00000000 0xFFFFFFFF EP_NUM Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint. 0 4 read-write ISOCH Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint, no handshake.\n 4 1 0 No Isochronous endpoint #0 1 Isochronous endpoint #1 read-write STATE Endpoint STATE\n 5 2 0 Endpoint Disabled #00 1 Out endpoint #01 2 IN endpoint #10 3 Undefined #11 read-write DSQ_SYNC Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the following IN token transaction. H/W will toggle automatically in IN token base on the bit. 7 1 0 DATA0 PID #0 1 DATA1 PID #1 read-write CSTALL Clear STALL Response\n 9 1 0 Device Disabled to clear the STALL handshake in the setup stage #0 1 Clear the device to respond STALL handshake in the setup stage #1 read-write USB_CFGP0 USB_CFGP0 Endpoint 0 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible. 0x50C read-write 0x00000000 0xFFFFFFFF CLRRDY Clear Ready\nWhen the MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start, user can set this bit to 1 to turn it off and it is automatically cleared to 0.\nFor IN token, writing '1' is used to clear the IN token had ready to transmit the data to USB.\nFor OUT token, writing '1' is used to clear the OUT token had ready to receive the data from USB.\nThis bit is written 1 only and is always 0 when it was read back. 0 1 read-write SSTALL Set STALL\n 1 1 0 Device Disabled to respond STALL #0 1 Set the device to respond STALL automatically #1 read-write USB_BUFSEG1 USB_BUFSEG1 Endpoint 1 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible. 0x510 USB_MXPLD1 USB_MXPLD1 Endpoint 1 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible. 0x514 USB_CFG1 USB_CFG1 Endpoint 1 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible. 0x518 USB_CFGP1 USB_CFGP1 Endpoint 1 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible. 0x51C USB_BUFSEG2 USB_BUFSEG2 Endpoint 2 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible. 0x520 USB_MXPLD2 USB_MXPLD2 Endpoint 2 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible. 0x524 USB_CFG2 USB_CFG2 Endpoint 2 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible. 0x528 USB_CFGP2 USB_CFGP2 Endpoint 2 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible. 0x52C USB_BUFSEG3 USB_BUFSEG3 Endpoint 3 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible. 0x530 USB_MXPLD3 USB_MXPLD3 Endpoint 3 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible. 0x534 USB_CFG3 USB_CFG3 Endpoint 3 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible. 0x538 USB_CFGP3 USB_CFGP3 Endpoint 3 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible. 0x53C USB_BUFSEG4 USB_BUFSEG4 Endpoint 4 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible. 0x540 USB_MXPLD4 USB_MXPLD4 Endpoint 4 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible. 0x544 USB_CFG4 USB_CFG4 Endpoint 4 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible. 0x548 USB_CFGP4 USB_CFGP4 Endpoint 4 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible. 0x54C USB_BUFSEG5 USB_BUFSEG5 Endpoint 5 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible. 0x550 USB_MXPLD5 USB_MXPLD5 Endpoint 5 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible. 0x554 USB_CFG5 USB_CFG5 Endpoint 5 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible. 0x558 USB_CFGP5 USB_CFGP5 Endpoint 5 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible. 0x55C USB_BUFSEG6 USB_BUFSEG6 Endpoint 6 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible. 0x560 USB_MXPLD6 USB_MXPLD6 Endpoint 6 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible. 0x564 USB_CFG6 USB_CFG6 Endpoint 6 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible. 0x568 USB_CFGP6 USB_CFGP6 Endpoint 6 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible. 0x56C USB_BUFSEG7 USB_BUFSEG7 Endpoint 7 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible. 0x570 USB_MXPLD7 USB_MXPLD7 Endpoint 7 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible. 0x574 USB_CFG7 USB_CFG7 Endpoint 7 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible. 0x578 USB_CFGP7 USB_CFGP7 Endpoint 7 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible. 0x57C GP GP Register Map GP 0x50004000 0x0 0x24 registers 0x40 0x24 registers 0x80 0x24 registers 0xC0 0x24 registers 0x140 0x24 registers 0x180 0x4 registers 0x228 0x90 registers 0x2C0 0x30 registers 0x340 0x10 registers GPIOA_PMD GPIOA_PMD GPIO Port A Pin I/O Mode Control 0x0 read-write 0xFFFFFFFF 0xFFFFFFFF PMD10 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 20 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD11 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 22 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD12 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 24 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD13 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 26 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD14 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 28 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD15 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 30 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write GPIOA_OFFD GPIOA_OFFD GPIO Port A Pin OFF Digital Enable 0x4 read-write 0x00000000 0xFFFFFFFF OFFD10 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 26 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD11 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 27 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD12 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 28 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD13 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 29 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD14 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 30 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD15 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 31 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write GPIOA_DOUT GPIOA_DOUT GPIO Port A Data Output Value 0x8 read-write 0x0000FFFF 0xFFFFFFFF DOUT10 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 10 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT11 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 11 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT12 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 12 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT13 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 13 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT14 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 14 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT15 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 15 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write GPIOA_DMASK GPIOA_DMASK GPIO Port A Data Output Write Mask 0xC read-write 0x00000000 0xFFFFFFFF DMASK10 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 10 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK11 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 11 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK12 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 12 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK13 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 13 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK14 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 14 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK15 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 15 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write GPIOA_PIN GPIOA_PIN GPIO Port A Pin Value 0x10 read-only 0x00000000 0xFFFF0000 PIN10 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 10 1 read-only PIN11 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 11 1 read-only PIN12 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 12 1 read-only PIN13 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 13 1 read-only PIN14 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 14 1 read-only PIN15 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 15 1 read-only GPIOA_DBEN GPIOA_DBEN GPIO Port A De-bounce Enable 0x14 read-write 0x00000000 0xFFFFFFFF DBEN10 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 10 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN11 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 11 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN12 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 12 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN13 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 13 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN14 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 14 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN15 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 15 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write GPIOA_IMD GPIOA_IMD GPIO Port A Interrupt Mode Control 0x18 read-write 0x00000000 0xFFFFFFFF IMD10 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 10 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD11 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 11 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD12 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 12 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD13 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 13 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD14 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 14 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD15 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 15 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write GPIOA_IEN GPIOA_IEN GPIO Port A Interrupt Enable 0x1C read-write 0x00000000 0xFFFFFFFF IF_EN10 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 10 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN11 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 11 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN12 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 12 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN13 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 13 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN14 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 14 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN15 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 15 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IR_EN10 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 26 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN11 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 27 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN12 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 28 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN13 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 29 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN14 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 30 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN15 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 31 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write GPIOA_ISRC GPIOA_ISRC GPIO Port A Interrupt Source Flag 0x20 read-write 0x00000000 0xFFFFFFFF ISRC10 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 10 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC11 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 11 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC12 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 12 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC13 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 13 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC14 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 14 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC15 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 15 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write GPIOB_PMD GPIOB_PMD GPIO Port B Pin I/O Mode Control 0x40 read-write 0xFFFFFFFF 0xFFFFFFFF PMD0 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD1 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD2 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 4 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD3 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 6 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD4 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 8 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD5 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 10 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD6 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 12 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD7 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 14 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD8 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 16 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD9 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 18 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD10 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 20 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD12 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 24 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD13 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 26 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD14 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 28 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD15 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 30 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write GPIOB_OFFD GPIOB_OFFD GPIO Port B Pin OFF Digital Enable 0x44 read-write 0x00000000 0xFFFFFFFF OFFD0 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 16 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD1 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 17 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD2 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 18 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD3 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 19 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD4 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 20 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD5 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 21 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD6 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 22 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD7 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 23 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD8 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 24 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD9 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 25 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD10 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 26 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD12 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 28 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD13 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 29 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD14 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 30 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD15 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 31 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write GPIOB_DOUT GPIOB_DOUT GPIO Port B Data Output Value 0x48 read-write 0x0000FFFF 0xFFFFFFFF DOUT0 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT1 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 1 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT2 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT3 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 3 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT4 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 4 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT5 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 5 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT6 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 6 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT7 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 7 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT8 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 8 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT9 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 9 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT10 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 10 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT12 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 12 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT13 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 13 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT14 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 14 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT15 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 15 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write GPIOB_DMASK GPIOB_DMASK GPIO Port B Data Output Write Mask 0x4C read-write 0x00000000 0xFFFFFFFF DMASK0 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK1 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 1 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK2 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK3 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 3 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK4 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 4 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK5 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 5 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK6 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 6 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK7 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 7 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK8 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 8 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK9 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 9 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK10 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 10 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK12 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 12 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK13 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 13 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK14 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 14 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK15 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 15 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write GPIOB_PIN GPIOB_PIN GPIO Port B Pin Value 0x50 read-only 0x00000000 0xFFFF0000 PIN0 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 1 read-only PIN1 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 1 1 read-only PIN2 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 1 read-only PIN3 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 3 1 read-only PIN4 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 4 1 read-only PIN5 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 5 1 read-only PIN6 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 6 1 read-only PIN7 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 7 1 read-only PIN8 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 8 1 read-only PIN9 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 9 1 read-only PIN10 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 10 1 read-only PIN12 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 12 1 read-only PIN13 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 13 1 read-only PIN14 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 14 1 read-only PIN15 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 15 1 read-only GPIOB_DBEN GPIOB_DBEN GPIO Port B De-bounce Enable 0x54 read-write 0x00000000 0xFFFFFFFF DBEN0 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN1 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 1 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN2 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN3 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 3 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN4 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 4 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN5 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 5 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN6 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 6 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN7 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 7 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN8 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 8 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN9 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 9 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN10 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 10 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN12 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 12 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN13 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 13 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN14 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 14 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN15 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 15 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write GPIOB_IMD GPIOB_IMD GPIO Port B Interrupt Mode Control 0x58 read-write 0x00000000 0xFFFFFFFF IMD0 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 0 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD1 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 1 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD2 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 2 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD3 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 3 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD4 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 4 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD5 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 5 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD6 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 6 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD7 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 7 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD8 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 8 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD9 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 9 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD10 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 10 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD12 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 12 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD13 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 13 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD14 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 14 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD15 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 15 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write GPIOB_IEN GPIOB_IEN GPIO Port B Interrupt Enable 0x5C read-write 0x00000000 0xFFFFFFFF IF_EN0 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 0 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN1 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 1 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN2 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 2 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN3 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 3 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN4 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 4 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN5 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 5 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN6 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 6 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN7 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 7 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN8 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 8 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN9 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 9 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN10 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 10 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN12 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 12 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN13 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 13 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN14 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 14 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN15 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 15 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IR_EN0 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 16 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN1 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 17 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN2 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 18 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN3 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 19 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN4 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 20 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN5 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 21 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN6 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 22 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN7 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 23 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN8 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 24 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN9 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 25 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN10 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 26 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN12 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 28 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN13 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 29 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN14 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 30 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN15 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 31 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write GPIOB_ISRC GPIOB_ISRC GPIO Port B Interrupt Source Flag 0x60 read-write 0x00000000 0xFFFFFFFF ISRC0 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 0 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC1 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 1 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC2 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 2 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC3 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 3 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC4 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 4 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC5 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 5 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC6 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 6 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC7 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 7 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC8 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 8 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC9 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 9 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC10 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 10 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC12 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 12 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC13 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 13 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC14 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 14 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC15 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 15 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write GPIOC_PMD GPIOC_PMD GPIO Port C Pin I/O Mode Control 0x80 read-write 0xFFFFFFFF 0xFFFFFFFF PMD0 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD1 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD2 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 4 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD3 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 6 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD4 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 8 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD5 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 10 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD8 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 16 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD9 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 18 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD10 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 20 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD11 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 22 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD12 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 24 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD13 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 26 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write GPIOC_OFFD GPIOC_OFFD GPIO Port C Pin OFF Digital Enable 0x84 read-write 0x00000000 0xFFFFFFFF OFFD0 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 16 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD1 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 17 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD2 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 18 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD3 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 19 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD4 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 20 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD5 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 21 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD8 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 24 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD9 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 25 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD10 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 26 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD11 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 27 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD12 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 28 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD13 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 29 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write GPIOC_DOUT GPIOC_DOUT GPIO Port C Data Output Value 0x88 read-write 0x0000FFFF 0xFFFFFFFF DOUT0 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT1 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 1 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT2 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT3 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 3 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT4 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 4 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT5 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 5 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT8 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 8 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT9 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 9 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT10 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 10 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT11 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 11 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT12 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 12 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT13 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 13 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write GPIOC_DMASK GPIOC_DMASK GPIO Port C Data Output Write Mask 0x8C read-write 0x00000000 0xFFFFFFFF DMASK0 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK1 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 1 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK2 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK3 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 3 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK4 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 4 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK5 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 5 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK8 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 8 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK9 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 9 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK10 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 10 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK11 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 11 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK12 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 12 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK13 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 13 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write GPIOC_PIN GPIOC_PIN GPIO Port C Pin Value 0x90 read-only 0x00000000 0xFFFF0000 PIN0 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 1 read-only PIN1 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 1 1 read-only PIN2 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 1 read-only PIN3 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 3 1 read-only PIN4 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 4 1 read-only PIN5 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 5 1 read-only PIN8 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 8 1 read-only PIN9 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 9 1 read-only PIN10 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 10 1 read-only PIN11 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 11 1 read-only PIN12 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 12 1 read-only PIN13 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 13 1 read-only GPIOC_DBEN GPIOC_DBEN GPIO Port C De-bounce Enable 0x94 read-write 0x00000000 0xFFFFFFFF DBEN0 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN1 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 1 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN2 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN3 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 3 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN4 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 4 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN5 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 5 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN8 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 8 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN9 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 9 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN10 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 10 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN11 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 11 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN12 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 12 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN13 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 13 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write GPIOC_IMD GPIOC_IMD GPIO Port C Interrupt Mode Control 0x98 read-write 0x00000000 0xFFFFFFFF IMD0 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 0 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD1 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 1 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD2 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 2 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD3 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 3 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD4 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 4 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD5 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 5 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD8 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 8 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD9 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 9 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD10 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 10 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD11 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 11 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD12 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 12 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD13 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 13 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write GPIOC_IEN GPIOC_IEN GPIO Port C Interrupt Enable 0x9C read-write 0x00000000 0xFFFFFFFF IF_EN0 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 0 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN1 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 1 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN2 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 2 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN3 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 3 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN4 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 4 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN5 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 5 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN8 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 8 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN9 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 9 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN10 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 10 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN11 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 11 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN12 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 12 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN13 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 13 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IR_EN0 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 16 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN1 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 17 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN2 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 18 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN3 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 19 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN4 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 20 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN5 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 21 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN8 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 24 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN9 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 25 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN10 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 26 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN11 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 27 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN12 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 28 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN13 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 29 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write GPIOC_ISRC GPIOC_ISRC GPIO Port C Interrupt Source Flag 0xA0 read-write 0x00000000 0xFFFFFFFF ISRC0 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 0 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC1 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 1 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC2 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 2 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC3 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 3 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC4 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 4 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC5 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 5 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC8 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 8 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC9 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 9 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC10 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 10 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC11 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 11 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC12 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 12 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC13 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 13 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write GPIOD_PMD GPIOD_PMD GPIO Port D Pin I/O Mode Control 0xC0 read-write 0xFFFFFFFF 0xFFFFFFFF PMD0 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD1 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD2 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 4 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD3 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 6 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD4 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 8 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD5 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 10 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD8 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 16 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD9 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 18 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD10 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 20 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD11 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 22 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write GPIOD_OFFD GPIOD_OFFD GPIO Port D Pin OFF Digital Enable 0xC4 read-write 0x00000000 0xFFFFFFFF OFFD0 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 16 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD1 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 17 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD2 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 18 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD3 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 19 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD4 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 20 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD5 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 21 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD8 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 24 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD9 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 25 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD10 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 26 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD11 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 27 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write GPIOD_DOUT GPIOD_DOUT GPIO Port D Data Output Value 0xC8 read-write 0x0000FFFF 0xFFFFFFFF DOUT0 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT1 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 1 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT2 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT3 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 3 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT4 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 4 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT5 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 5 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT8 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 8 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT9 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 9 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT10 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 10 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT11 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 11 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write GPIOD_DMASK GPIOD_DMASK GPIO Port D Data Output Write Mask 0xCC read-write 0x00000000 0xFFFFFFFF DMASK0 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK1 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 1 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK2 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK3 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 3 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK4 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 4 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK5 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 5 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK8 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 8 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK9 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 9 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK10 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 10 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK11 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 11 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write GPIOD_PIN GPIOD_PIN GPIO Port D Pin Value 0xD0 read-only 0x00000000 0xFFFF0000 PIN0 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 1 read-only PIN1 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 1 1 read-only PIN2 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 1 read-only PIN3 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 3 1 read-only PIN4 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 4 1 read-only PIN5 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 5 1 read-only PIN8 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 8 1 read-only PIN9 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 9 1 read-only PIN10 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 10 1 read-only PIN11 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 11 1 read-only GPIOD_DBEN GPIOD_DBEN GPIO Port D De-bounce Enable 0xD4 read-write 0x00000000 0xFFFFFFFF DBEN0 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN1 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 1 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN2 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN3 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 3 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN4 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 4 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN5 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 5 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN8 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 8 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN9 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 9 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN10 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 10 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN11 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 11 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write GPIOD_IMD GPIOD_IMD GPIO Port D Interrupt Mode Control 0xD8 read-write 0x00000000 0xFFFFFFFF IMD0 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 0 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD1 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 1 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD2 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 2 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD3 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 3 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD4 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 4 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD5 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 5 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD8 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 8 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD9 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 9 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD10 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 10 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD11 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 11 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write GPIOD_IEN GPIOD_IEN GPIO Port D Interrupt Enable 0xDC read-write 0x00000000 0xFFFFFFFF IF_EN0 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 0 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN1 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 1 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN2 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 2 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN3 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 3 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN4 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 4 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN5 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 5 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN8 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 8 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN9 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 9 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN10 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 10 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN11 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 11 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IR_EN0 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 16 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN1 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 17 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN2 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 18 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN3 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 19 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN4 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 20 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN5 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 21 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN8 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 24 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN9 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 25 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN10 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 26 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN11 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 27 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write GPIOD_ISRC GPIOD_ISRC GPIO Port D Interrupt Source Flag 0xE0 read-write 0x00000000 0xFFFFFFFF ISRC0 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 0 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC1 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 1 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC2 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 2 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC3 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 3 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC4 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 4 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC5 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 5 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC8 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 8 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC9 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 9 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC10 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 10 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC11 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 11 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write GPIOF_PMD GPIOF_PMD GPIO Port F Pin I/O Mode Control 0x140 read-write 0x000000FF 0xFFFFFFFF PMD0 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD1 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD2 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 4 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write PMD3 GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 6 2 0 GPIO port [n] pin is in INPUT mode #00 1 GPIO port [n] pin is in OUTPUT mode #01 2 GPIO port [n] pin is in Open-Drain mode #10 3 GPIO port [n] pin is in Quasi-bidirectional mode #11 read-write GPIOF_OFFD GPIOF_OFFD GPIO Port F Pin OFF Digital Enable 0x144 read-write 0x00000000 0xFFFFFFFF OFFD0 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 16 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD1 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 17 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD2 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 18 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write OFFD3 GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 19 1 0 IO digital input path Enabled #0 1 IO digital input path Disabled (digital input tied to low) #1 read-write GPIOF_DOUT GPIOF_DOUT GPIO Port F Data Output Value 0x148 read-write 0x0000000F 0xFFFFFFFF DOUT0 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT1 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 1 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT2 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write DOUT3 GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 3 1 0 GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode #0 1 GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode #1 read-write GPIOF_DMASK GPIOF_DMASK GPIO Port F Data Output Write Mask 0x14C read-write 0x00000000 0xFFFFFFFF DMASK0 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK1 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 1 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK2 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write DMASK3 Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 3 1 0 The corresponding GPIOx_DOUT[n] bit can be updated #0 1 The corresponding GPIOx_DOUT[n] bit is protected #1 read-write GPIOF_PIN GPIOF_PIN GPIO Port F Pin Value 0x150 read-only 0x00000000 0xFFFFFFF0 PIN0 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 1 read-only PIN1 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 1 1 read-only PIN2 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 1 read-only PIN3 Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 3 1 read-only GPIOF_DBEN GPIOF_DBEN GPIO Port F De-bounce Enable 0x154 read-write 0x00000000 0xFFFFFFFF DBEN0 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 0 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN1 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 1 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN2 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 2 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write DBEN3 Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved. 3 1 0 The bit[n] de-bounce function is disabled #0 1 The bit[n] de-bounce function is enabled #1 read-write GPIOF_IMD GPIOF_IMD GPIO Port F Interrupt Mode Control 0x158 read-write 0x00000000 0xFFFFFFFF IMD0 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 0 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD1 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 1 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD2 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 2 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write IMD3 Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 3 1 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 read-write GPIOF_IEN GPIOF_IEN GPIO Port F Interrupt Enable 0x15C read-write 0x00000000 0xFFFFFFFF IF_EN0 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 0 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN1 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 1 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN2 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 2 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IF_EN3 Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 3 1 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 read-write IR_EN0 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 16 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN1 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 17 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN2 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 18 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write IR_EN3 Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 19 1 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 read-write GPIOF_ISRC GPIOF_ISRC GPIO Port F Interrupt Source Flag 0x160 read-write 0x00000000 0xFFFFFFFF ISRC0 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 0 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC1 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 1 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC2 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 2 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write ISRC3 Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved. 3 1 0 No interrupt at GPIOx[n].\nNo action #0 1 Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt #1 read-write DBNCECON DBNCECON De-bounce Cycle Control 0x180 read-write 0x00000020 0xFFFFFFFF DBCLKSEL De-bounce sampling cycle selection\n 0 4 read-write DBCLKSRC De-bounce counter clock source select\n 4 1 0 De-bounce counter clock source is the HCLK #0 1 De-bounce counter clock source is the internal 10 kHz low speed oscillator #1 read-write ICLK_ON Interrupt clock On mode\nSetting this bit to 0 will disable the interrupt generate circuit clock if the pin[n] interrupt is disabled\n 5 1 0 Clock Disabled if the GPIOA/B/C/D/F[n] interrupt is disabled #0 1 Interrupt generated circuit clock always Enabled #1 read-write PA10_PDIO PA10_PDIO GPIO PA.n Pin Data Input/Output 0x228 read-write 0x00000000 0xFFFFFFF0 GPIOxx_DOUT GPIOxx I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\nRead this register to get IO pin status.\nFor example: Writing GPIOA0_DOUT will reflect the written value to bit GPIOA_DOUT[0], read GPIOA0_DOUT will return the value of GPIOA_PIN[0] 0 1 0 Set the corresponding GPIO pin to low #0 1 Set the corresponding GPIO pin to high #1 read-write PA11_PDIO PA11_PDIO GPIO PA.n Pin Data Input/Output 0x22C PA12_PDIO PA12_PDIO GPIO PA.n Pin Data Input/Output 0x230 PA13_PDIO PA13_PDIO GPIO PA.n Pin Data Input/Output 0x234 PA14_PDIO PA14_PDIO GPIO PA.n Pin Data Input/Output 0x238 PA15_PDIO PA15_PDIO GPIO PA.n Pin Data Input/Output 0x23C PB0_PDIO PB0_PDIO GPIO PB.n Pin Data Input/Output 0x240 PB1_PDIO PB1_PDIO GPIO PB.n Pin Data Input/Output 0x244 PB2_PDIO PB2_PDIO GPIO PB.n Pin Data Input/Output 0x248 PB3_PDIO PB3_PDIO GPIO PB.n Pin Data Input/Output 0x24C PB4_PDIO PB4_PDIO GPIO PB.n Pin Data Input/Output 0x250 PB5_PDIO PB5_PDIO GPIO PB.n Pin Data Input/Output 0x254 PB6_PDIO PB6_PDIO GPIO PB.n Pin Data Input/Output 0x258 PB7_PDIO PB7_PDIO GPIO PB.n Pin Data Input/Output 0x25C PB8_PDIO PB8_PDIO GPIO PB.n Pin Data Input/Output 0x260 PB9_PDIO PB9_PDIO GPIO PB.n Pin Data Input/Output 0x264 PB10_PDIO PB10_PDIO GPIO PB.n Pin Data Input/Output 0x268 PB11_PDIO PB11_PDIO GPIO PB.n Pin Data Input/Output 0x26C PB12_PDIO PB12_PDIO GPIO PB.n Pin Data Input/Output 0x270 PB13_PDIO PB13_PDIO GPIO PB.n Pin Data Input/Output 0x274 PB14_PDIO PB14_PDIO GPIO PB.n Pin Data Input/Output 0x278 PB15_PDIO PB15_PDIO GPIO PB.n Pin Data Input/Output 0x27C PC0_PDIO PC0_PDIO GPIO PC.n Pin Data Input/Output 0x280 PC1_PDIO PC1_PDIO GPIO PC.n Pin Data Input/Output 0x284 PC2_PDIO PC2_PDIO GPIO PC.n Pin Data Input/Output 0x288 PC3_PDIO PC3_PDIO GPIO PC.n Pin Data Input/Output 0x28C PC4_PDIO PC4_PDIO GPIO PC.n Pin Data Input/Output 0x290 PC5_PDIO PC5_PDIO GPIO PC.n Pin Data Input/Output 0x294 PC6_PDIO PC6_PDIO GPIO PC.n Pin Data Input/Output 0x298 PC7_PDIO PC7_PDIO GPIO PC.n Pin Data Input/Output 0x29C PC8_PDIO PC8_PDIO GPIO PC.n Pin Data Input/Output 0x2A0 PC9_PDIO PC9_PDIO GPIO PC.n Pin Data Input/Output 0x2A4 PC10_PDIO PC10_PDIO GPIO PC.n Pin Data Input/Output 0x2A8 PC11_PDIO PC11_PDIO GPIO PC.n Pin Data Input/Output 0x2AC PC12_PDIO PC12_PDIO GPIO PC.n Pin Data Input/Output 0x2B0 PC13_PDIO PC13_PDIO GPIO PC.n Pin Data Input/Output 0x2B4 PD0_PDIO PD0_PDIO GPIO PD.n Pin Data Input/Output 0x2C0 PD1_PDIO PD1_PDIO GPIO PD.n Pin Data Input/Output 0x2C4 PD2_PDIO PD2_PDIO GPIO PD.n Pin Data Input/Output 0x2C8 PD3_PDIO PD3_PDIO GPIO PD.n Pin Data Input/Output 0x2CC PD4_PDIO PD4_PDIO GPIO PD.n Pin Data Input/Output 0x2D0 PD5_PDIO PD5_PDIO GPIO PD.n Pin Data Input/Output 0x2D4 PD6_PDIO PD6_PDIO GPIO PD.n Pin Data Input/Output 0x2D8 PD7_PDIO PD7_PDIO GPIO PD.n Pin Data Input/Output 0x2DC PD8_PDIO PD8_PDIO GPIO PD.n Pin Data Input/Output 0x2E0 PD9_PDIO PD9_PDIO GPIO PD.n Pin Data Input/Output 0x2E4 PD10_PDIO PD10_PDIO GPIO PD.n Pin Data Input/Output 0x2E8 PD11_PDIO PD11_PDIO GPIO PD.n Pin Data Input/Output 0x2EC PF0_PDIO PF0_PDIO GPIO PF.n Pin Data Input/Output 0x340 PF1_PDIO PF1_PDIO GPIO PF.n Pin Data Input/Output 0x344 PF2_PDIO PF2_PDIO GPIO PF.n Pin Data Input/Output 0x348 PF3_PDIO PF3_PDIO GPIO PF.n Pin Data Input/Output 0x34C I2C0 I2C Register Map I2C 0x40020000 0x0 0x34 registers 0x3C 0x8 registers I2CON I2CON I2C Control Register 0x0 read-write 0x00000000 0xFFFFFFFF AA Assert Acknowledge Control Bit\n 2 1 read-write SI I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to this bit. 3 1 read-write STO I2C STOP Control Bit\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a Slave mode, setting STO resets I2C hardware to the defined "not addressed" Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device. 4 1 read-write STA I2C START Control Bit\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write ENS1 I2C Controller Enable Bit\n 6 1 0 Disabled #0 1 Enabled #1 read-write EI Enable Interrupt\n 7 1 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 read-write I2CADDR0 I2CADDR0 I2C Slave Address Register0 0x4 read-write 0x00000000 0xFFFFFFFF GC General Call Function\n 0 1 0 General Call function Disabled #0 1 General Call function Enabled #1 read-write I2CADDR I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the addresses is matched. 1 7 read-write I2CDAT I2CDAT I2C Data Register 0x8 read-write 0x00000000 0xFFFFFFFF I2CDAT I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port. 0 8 read-write I2CSTATUS I2CSTATUS I2C Status Register 0xC read-only 0x000000F8 0xFFFFFFFF I2CSTATUS I2C Status Register\nThe status register of I2C:\n 0 8 read-only I2CLK I2CLK I2C Clock Divided Register 0x10 read-write 0x00000000 0xFFFFFFFF I2CLK I2C clock divided Register\n 0 8 read-write I2CTOC I2CTOC I2C Time-Out Counter Register 0x14 read-write 0x00000000 0xFFFFFFFF TIF Time-Out Flag\n 0 1 0 Software can clear the flag #0 1 Time-out flag is set by H/W. It can interrupt CPU #1 read-write DIV4 Time-out Counter Input Clock Divided by 4\nWhen Enabled, the time-out period is extend 4 times. 1 1 0 Disabled #0 1 Enabled #1 read-write ENTI Time-out Counter Enable/Disable\nWhen Enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting the flag SI to high will reset counter and re-start counting up after SI is cleared. 2 1 0 Disabled #0 1 Enabled #1 read-write I2CADDR1 I2CADDR1 I2C Slave Address Register1 0x18 I2CADDR2 I2CADDR2 I2C Slave Address Register2 0x1C I2CADDR3 I2CADDR3 I2C Slave Address Register3 0x20 I2CADM0 I2CADM0 I2C Slave Address Mask Register0 0x24 read-write 0x00000000 0xFFFFFFFF I2CADM I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, it means the received corresponding register bit should be exact the same as address register. 1 7 0 Mask Disabled (the received corresponding register bit should be exactly the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 read-write I2CADM1 I2CADM1 I2C Slave Address Mask Register1 0x28 I2CADM2 I2CADM2 I2C Slave Address Mask Register2 0x2C I2CADM3 I2CADM3 I2C Slave Address Mask Register3 0x30 I2CWKUPCON I2CWKUPCON I2C Wake-up Control Register 0x3C read-write 0x00000000 0xFFFFFFFF WKUPEN I2C Wake-up Function Enable\n 0 1 0 I2C wake-up function Disabled #0 1 I2C wake-up function Enabled #1 read-write I2CWKUPSTS I2CWKUPSTS I2C Wake-up Status Register 0x40 read-only 0x00000000 0xFFFFFFFF WKUPIF Wake-up Interrupt Flag\nSoftware can write one to clear this flag 0 1 0 Wake-up flag inactive #0 1 Wake-up flag active #1 read-only I2C1 I2C Register Map I2C 0x40120000 0x0 0x34 registers 0x3C 0x8 registers I2CON I2CON I2C Control Register 0x0 read-write 0x00000000 0xFFFFFFFF AA Assert Acknowledge Control Bit\n 2 1 read-write SI I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to this bit. 3 1 read-write STO I2C STOP Control Bit\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a Slave mode, setting STO resets I2C hardware to the defined "not addressed" Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device. 4 1 read-write STA I2C START Control Bit\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write ENS1 I2C Controller Enable Bit\n 6 1 0 Disabled #0 1 Enabled #1 read-write EI Enable Interrupt\n 7 1 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 read-write I2CADDR0 I2CADDR0 I2C Slave Address Register0 0x4 read-write 0x00000000 0xFFFFFFFF GC General Call Function\n 0 1 0 General Call function Disabled #0 1 General Call function Enabled #1 read-write I2CADDR I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the addresses is matched. 1 7 read-write I2CDAT I2CDAT I2C Data Register 0x8 read-write 0x00000000 0xFFFFFFFF I2CDAT I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port. 0 8 read-write I2CSTATUS I2CSTATUS I2C Status Register 0xC read-only 0x000000F8 0xFFFFFFFF I2CSTATUS I2C Status Register\nThe status register of I2C:\n 0 8 read-only I2CLK I2CLK I2C Clock Divided Register 0x10 read-write 0x00000000 0xFFFFFFFF I2CLK I2C clock divided Register\n 0 8 read-write I2CTOC I2CTOC I2C Time-Out Counter Register 0x14 read-write 0x00000000 0xFFFFFFFF TIF Time-Out Flag\n 0 1 0 Software can clear the flag #0 1 Time-out flag is set by H/W. It can interrupt CPU #1 read-write DIV4 Time-out Counter Input Clock Divided by 4\nWhen Enabled, the time-out period is extend 4 times. 1 1 0 Disabled #0 1 Enabled #1 read-write ENTI Time-out Counter Enable/Disable\nWhen Enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting the flag SI to high will reset counter and re-start counting up after SI is cleared. 2 1 0 Disabled #0 1 Enabled #1 read-write I2CADDR1 I2CADDR1 I2C Slave Address Register1 0x18 I2CADDR2 I2CADDR2 I2C Slave Address Register2 0x1C I2CADDR3 I2CADDR3 I2C Slave Address Register3 0x20 I2CADM0 I2CADM0 I2C Slave Address Mask Register0 0x24 read-write 0x00000000 0xFFFFFFFF I2CADM I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, it means the received corresponding register bit should be exact the same as address register. 1 7 0 Mask Disabled (the received corresponding register bit should be exactly the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 read-write I2CADM1 I2CADM1 I2C Slave Address Mask Register1 0x28 I2CADM2 I2CADM2 I2C Slave Address Mask Register2 0x2C I2CADM3 I2CADM3 I2C Slave Address Mask Register3 0x30 I2CWKUPCON I2CWKUPCON I2C Wake-up Control Register 0x3C read-write 0x00000000 0xFFFFFFFF WKUPEN I2C Wake-up Function Enable\n 0 1 0 I2C wake-up function Disabled #0 1 I2C wake-up function Enabled #1 read-write I2CWKUPSTS I2CWKUPSTS I2C Wake-up Status Register 0x40 read-only 0x00000000 0xFFFFFFFF WKUPIF Wake-up Interrupt Flag\nSoftware can write one to clear this flag 0 1 0 Wake-up flag inactive #0 1 Wake-up flag active #1 read-only PWMA PWM Register Map PWM 0x40040000 0x0 0x48 registers 0x50 0x48 registers 0xC0 0x14 registers PPR PPR PWM Prescaler Register 0x0 read-write 0x00000000 0xFFFFFFFF CP01 Clock Prescaler 0 (PWM-timer 0 / 1)\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer.\n 0 8 read-write CP23 Clock Prescaler 2 (PWM Timer2 / 3)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer.\n 8 8 read-write DZI01 Dead-zone Interval for Pair of Channel 0 and Channel 1 (PWM0 and PWM1 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits. 16 8 read-write DZI23 Dead-zone Interval for Pair of Channel2 and Channel3 (PWM2 and PWM3 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits. 24 8 read-write CSR CSR PWM Clock Selector Register 0x4 read-write 0x00000000 0xFFFFFFFF CSR0 PWM Timer 0 Clock Source Selection (PWM Timer 0)\nSelect clock input for PWM timer.\n(Table is the same as CSR3.) 0 3 read-write CSR1 PWM Timer 1 Clock Source Selection (PWM Timer 1)\nSelect clock input for PWM timer.\n(Table is the same as CSR3.) 4 3 read-write CSR2 PWM Timer 2 Clock Source Selection (PWM Timer 2)\nSelect clock input for PWM timer.\n(Table is the same as CSR3.) 8 3 read-write CSR3 PWM Timer 3 Clock Source Selection (PWM timer 3)\n 12 3 read-write PCR PCR PWM Control Register 0x8 read-write 0x00000000 0xFFFFFFFF CH0EN PWM-Timer 0 Enable (PWM timer 0)\n 0 1 0 Corresponding PWM-Timer Running Stopped #0 1 Corresponding PWM-Timer Start Run Enabled #1 read-write CH0PINV PWM-Timer 0 Output Polar Inverse Enable (PWM Timer 0)\n 1 1 0 PWM0 output polar inverse Disabled #0 1 PWM0 output polar inverse Enabled #1 read-write CH0INV PWM-Timer 0 Output Inverter Enable (PWM Timer 0)\n 2 1 0 Inverter Disabled #0 1 Inverter Enabled #1 read-write CH0MOD PWM-Timer 0 Auto-reload/One-Shot Mode (PWM Timer 0)\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be clear. 3 1 0 One-shot mode #0 1 Auto-reload mode #1 read-write DZEN01 Dead-Zone 0 Generator Enable (PWM0 and PWM1 Pair)\nNote: When dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A. 4 1 0 Disabled #0 1 Enabled #1 read-write DZEN23 Dead-Zone 2 Generator Enable (PWM2 and PWM3 Pair)\nNote: When dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B. 5 1 0 Disabled #0 1 Enabled #1 read-write CH1EN PWM-Timer 1 Enable (PWM Timer 1)\n 8 1 0 Corresponding PWM-Timer Running Stopped #0 1 Corresponding PWM-Timer Start Run Enabled #1 read-write CH1PINV PWM-Timer 1 Output Polar Inverse Enable (PWM Timer 1)\n 9 1 0 PWM1 output polar inverse Disabled #0 1 PWM1 output polar inverse Enabled #1 read-write CH1INV PWM-Timer 1 Output Inverter Enable (PWM Timer 1)\n 10 1 0 Inverter Disabled #0 1 Inverter Enabled #1 read-write CH1MOD PWM-Timer 1 Auto-reload/One-Shot Mode (PWM Timer 1)\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be clear. 11 1 0 One-shot mode #0 1 Auto-load mode #1 read-write CH2EN PWM-Timer 2 Enable (PWM Timer 2)\n 16 1 0 Corresponding PWM-Timer Running Stopped #0 1 Corresponding PWM-Timer Start Run Enabled #1 read-write CH2PINV PWM-Timer 2 Output Polar Inverse Enable (PWM Timer 2)\n 17 1 0 PWM2 output polar inverse Disabled #0 1 PWM2 output polar inverse Enabled #1 read-write CH2INV PWM-Timer 2 Output Inverter Enable (PWM Timer 2)\n 18 1 0 Inverter Disabled #0 1 Inverter Enabled #1 read-write CH2MOD PWM-Timer 2 Auto-reload/One-Shot Mode (PWM Timer 2)\nNote: If there is a transition at this bit, it will cause CNR2 and CMR2 be clear. 19 1 0 One-shot mode #0 1 Auto-reload mode #1 read-write CH3EN PWM-Timer 3 Enable (PWM Timer 3)\n 24 1 0 Corresponding PWM-Timer Running Stopped #0 1 Corresponding PWM-Timer Start Run Enabled #1 read-write CH3PINV PWM-Timer 3 Output Polar Inverse Enable (PWM Timer 3)\n 25 1 0 PWM3 output polar inverse Disabled #0 1 PWM3 output polar inverse Enabled #1 read-write CH3INV PWM-Timer 3 Output Inverter Enable (PWM Timer 3)\n 26 1 0 Inverter Disabled #0 1 Inverter Enabled #1 read-write CH3MOD PWM-Timer 3 Auto-reload/One-Shot Mode (PWM Timer 3)\nNote: If there is a transition at this bit, it will cause CNR3 and CMR3 be clear. 27 1 0 One-shot mode #0 1 Auto-reload mode #1 read-write PWMTYPE01 PWM01 Aligned Type Selection Bit (PWM0 and PWM1 Pair)\n 30 1 0 Edge-aligned type #0 1 Center-aligned type #1 read-write PWMTYPE23 PWM23 Aligned Type Selection Bit (PWM2 and PWM3 Pair)\n 31 1 0 Edge-aligned type #0 1 Center-aligned type #1 read-write CNR0 CNR0 PWM Counter Register 0 0xC read-write 0x00000000 0xFFFFFFFF CNRx PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in the next PWM cycle.\nNote: When PWM operating at center-aligned type, CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF, the PWM will work unpredictable.\nNote: When CNR value is set to 0, PWM output is always high. 0 16 read-write CMR0 CMR0 PWM Comparator Register 0 0x10 read-write 0x00000000 0xFFFFFFFF CMRx PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in the next PWM cycle. 0 16 read-write PDR0 PDR0 PWM Data Register 0 0x14 read-only 0x00000000 0xFFFFFFFF PDRx PWM Data Register\nUser can monitor PDR to know the current value in 16-bit down counter. 0 16 read-only CNR1 CNR1 PWM Counter Register 1 0x18 CMR1 CMR1 PWM Comparator Register 1 0x1C PDR1 PDR1 PWM Data Registe 1 0x20 CNR2 CNR2 PWM Counter Register 2 0x24 CMR2 CMR2 PWM Comparator Register 2 0x28 PDR2 PDR2 PWM Data Register 2 0x2C CNR3 CNR3 PWM Counter Register 3 0x30 CMR3 CMR3 PWM Comparator Register 3 0x34 PDR3 PDR3 PWM Data Register 3 0x38 PBCR PBCR PWM backward compatible Register 0x3C read-write 0x00000000 0xFFFFFFFF PIER PIER PWM Interrupt Enable Register 0x40 read-write 0x00000000 0xFFFFFFFF PWMIE0 PWM Channel 0 Interrupt Enable\n 0 1 0 Disabled #0 1 Enabled #1 read-write PWMIE1 PWM Channel 1 Interrupt Enable\n 1 1 0 Disabled #0 1 Enabled #1 read-write PWMIE2 PWM Channel 2 Interrupt Enable\n 2 1 0 Disabled #0 1 Enabled #1 read-write PWMIE3 PWM Channel 3 Interrupt Enable\n 3 1 0 Disabled #0 1 Enabled #1 read-write PWMDIE0 PWM Channel 0 Duty Interrupt Enable\n 8 1 0 Disabled #0 1 Enabled #1 read-write PWMDIE1 PWM Channel 1 Duty Interrupt Enable\n 9 1 0 Disabled #0 1 Enabled #1 read-write PWMDIE2 PWM Channel 2 Duty Interrupt Enable\n 10 1 0 Disabled #0 1 Enabled #1 read-write PWMDIE3 PWM Channel 3 Duty Interrupt Enable\n 11 1 0 Disabled #0 1 Enabled #1 read-write INTTYPE01 PWM01 Interrupt Type Selection Bit (PWM0 and PWM1 Pair)\nNote: This bit is effective when PWM in central align mode only. 16 1 0 PWMIFn will be set if PWM counter underflow #0 1 PWMIFn will be set if PWM counter matches CNRn register #1 read-write INTTYPE23 PWM12 Interrupt Type Selection Bit (PWM2 and PWM3 Pair)\nNote: This bit is effective when PWM in central align mode only. 17 1 0 PWMIFn will be set if PWM counter underflow #0 1 PWMIFn will be set if PWM counter matches CNRn register #1 read-write PIIR PIIR PWM Interrupt Indication Register 0x44 read-write 0x00000000 0xFFFFFFFF PWMIF0 PWM channel 0 Interrupt Status\nThis bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depending on INTTYPE01 bit of PIER register) if PWM0 interrupt enable bit (PWMIE0) is 1, software can write 1 to clear this bit to zero 0 1 read-write PWMIF1 PWM channel 1 Interrupt Status\nThis bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depending on INTTYPE01 bit of PIER register) if PWM1 interrupt enable bit (PWMIE1) is 1, software can write 1 to clear this bit to zero 1 1 read-write PWMIF2 PWM channel 2 Interrupt Status\nThis bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depending on INTTYPE23 bit of PIER register) if PWM2 interrupt enable bit (PWMIE2) is 1, software can write 1 to clear this bit to zero 2 1 read-write PWMIF3 PWM channel 3 Interrupt Status\nThis bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depending on INTTYPE23 bit of PIER register) if PWM3 interrupt enable bit (PWMIE3) is 1, software can write 1 to clear this bit to zero 3 1 read-write PWMDIF0 PWM channel 0 Duty Interrupt Flag\nFlag is set by hardware when channel 0 PWM counter down count and reaches CMR0, software can clear this bit by writing a one to it.\nNote: If CMR is equal to CNR, this flag is not working 8 1 read-write PWMDIF1 PWM channel 1 Duty Interrupt Flag\nFlag is set by hardware when channel 1 PWM counter down count and reaches CMR1, software can clear this bit by writing a one to it.\nNote: If CMR is equal to CNR, this flag is not working 9 1 read-write PWMDIF2 PWM channel 2 Duty Interrupt Flag\nFlag is set by hardware when channel 2 PWM counter down count and reaches CMR2, software can clear this bit by writing a one to it.\nNote: If CMR is equal to CNR, this flag is not working 10 1 read-write PWMDIF3 PWM channel 3 Duty Interrupt Flag\nFlag is set by hardware when channel 3 PWM counter down count and reaches CMR3, software can clear this bit by writing a one to it.\nNote: If CMR is equal to CNR, this flag is not working 11 1 read-write CCR0 CCR0 PWM Capture Control Register 0 0x50 read-write 0x00000000 0xFFFFFFFF INV0 Channel 0 Inverter Enable\n 0 1 0 Inverter Disabled #0 1 Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer #1 read-write CRL_IE0 Channel 0 Rising Latch Interrupt Enable\nWhen Enabled, if capture detects PWM group channel 0 has rising transition, capture issues an Interrupt. 1 1 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 read-write CFL_IE0 Channel 0 Falling Latch Interrupt Enable\nWhen Enabled, if capture detects PWM group channel 0 has falling transition, capture issues an Interrupt. 2 1 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 read-write CAPCH0EN Channel 0 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt. 3 1 0 Capture function on PWM group channel 0 Disabled #0 1 Capture function on PWM group channel 0 Enabled #1 read-write CAPIF0 Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero 4 1 read-write CRLRI0 CRLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1. 6 1 read-write CFLRI0 CFLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1. 7 1 read-write INV1 Channel 1 Inverter Enable\n 16 1 0 Inverter Disabled #0 1 Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer #1 read-write CRL_IE1 Channel 1 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 1 has rising transition, capture issues an Interrupt. 17 1 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 read-write CFL_IE1 Channel 1 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 1 has falling transition, capture issues an Interrupt. 18 1 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 read-write CAPCH1EN Channel 1 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt. 19 1 0 Capture function on PWM group channel 1 Disabled #0 1 Capture function on PWM group channel 1 Enabled #1 read-write CAPIF1 Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero 20 1 read-write CRLRI1 CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition, CRLR1 is latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1. 22 1 read-write CFLRI1 CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition, CFLR1 is latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1. 23 1 read-write CCR2 CCR2 PWM Capture Control Register 2 0x54 read-write 0x00000000 0xFFFFFFFF INV2 Channel 2 Inverter Enable\n 0 1 0 Inverter Disabled #0 1 Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer #1 read-write CRL_IE2 Channel 2 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 2 has rising transition, Capture issues an Interrupt. 1 1 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 read-write CFL_IE2 Channel 2 Falling Latch Interrupt Enable\nWhen Enabled, if capture detects PWM group channel 2 has falling transition, capture issues an Interrupt. 2 1 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 read-write CAPCH2EN Channel 2 Capture Function Enable\nWhen Enabled, capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt. 3 1 0 Capture function on PWM group channel 2 Disabled #0 1 Capture function on PWM group channel 2 Enabled #1 read-write CAPIF2 Channel 2 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero 4 1 read-write CRLRI2 CRLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1. 6 1 read-write CFLRI2 CFLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1. 7 1 read-write INV3 Channel 3 Inverter Enable\n 16 1 0 Inverter Disabled #0 1 Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer #1 read-write CRL_IE3 Channel 3 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 3 has rising transition, capture issues an Interrupt. 17 1 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 read-write CFL_IE3 Channel 3 Falling Latch Interrupt Enable\nWhen Enabled, if capture detects PWM group channel 3 has falling transition, capture issues an Interrupt. 18 1 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 read-write CAPCH3EN Channel 3 Capture Function Enable\nWhen Enabled, capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt. 19 1 0 Capture function on PWM group channel 3 Disabled #0 1 Capture function on PWM group channel 3 Enabled #1 read-write CAPIF3 Channel 3 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero 20 1 read-write CRLRI3 CRLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1. 22 1 read-write CFLRI3 CFLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1. 23 1 read-write CRLR0 CRLR0 PWM Capture Rising Latch Register (Channel 0) 0x58 read-only 0x00000000 0xFFFFFFFF CRLRx Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition. 0 16 read-only CFLR0 CFLR0 PWM Capture Falling Latch Register (Channel 0) 0x5C read-only 0x00000000 0xFFFFFFFF CFLRx Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition. 0 16 read-only CRLR1 CRLR1 PWM Capture Rising Latch Register (Channel 1) 0x60 CFLR1 CFLR1 PWM Capture Falling Latch Register (Channel 1) 0x64 CRLR2 CRLR2 PWM Capture Rising Latch Register (Channel 2) 0x68 CFLR2 CFLR2 PWM Capture Falling Latch Register (Channel 2) 0x6C CRLR3 CRLR3 PWM Capture Rising Latch Register (Channel 3) 0x70 CFLR3 CFLR3 PWM Capture Falling Latch Register (Channel 3) 0x74 CAPENR CAPENR PWM Capture Input 0~3 Enable Register 0x78 read-write 0x00000000 0xFFFFFFFF CAPENR Capture Input Enable Register\nThere are four capture inputs from pad. Bit0~Bit3 are used to control each input enable or disable. \n\nCAPENR\nBit 3210 for PWM group A\nBit xxx1 ( Capture channel 0 is from pin PA.12\nBit xx1x ( Capture channel 1 is from pin PA.13\nBit x1xx ( Capture channel 2 is from pin PA.14\nBit 1xxx ( Capture channel 3 is from pin PA.15\nBit 3210 for PWM group B\nBit xxx1 ( Capture channel 0 is from pin PB.11\nBit xx1x ( Capture channel 1 is from pin PE.5\nBit x1xx ( Capture channel 2 is from pin PE.0\nBit 1xxx ( Capture channel 3 is from pin PE.1 0 4 0 Disabled (PWMx multi-function pin input does not affect input capture function.) 0 1 Enabled (PWMx multi-function pin input will affect its input capture function.) 1 read-write POE POE PWM Output Enable for channel 0~3 0x7C read-write 0x00000000 0xFFFFFFFF PWM0 Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. 0 1 0 PWM channel 0 output to pin Disabled #0 1 PWM channel 0 output to pin Enabled #1 read-write PWM1 Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. 1 1 0 PWM channel 1 output to pin Disabled #0 1 PWM channel 1 output to pin Enabled #1 read-write PWM2 Channel 2 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. 2 1 0 PWM channel 2 output to pin Disabled #0 1 PWM channel 2 output to pin Enabled #1 read-write PWM3 Channel 3 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. 3 1 0 PWM channel 3 output to pin Disabled #0 1 PWM channel 3 output to pin Enabled #1 read-write TCON TCON PWM Trigger Control for channel 0~3 0x80 read-write 0x00000000 0xFFFFFFFF PWM0TEN Channel 0 Center-Aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter counts up to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating in Center-aligned mode. 0 1 0 PWM channel 0 trigger ADC function Disabled #0 1 PWM channel 0 trigger ADC function Enabled #1 read-write PWM1TEN Channel 1 Center-Aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter counts up to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating in Center-aligned mode 1 1 0 PWM channel 1 trigger ADC function Disabled #0 1 PWM channel 1 trigger ADC function Enabled #1 read-write PWM2TEN Channel 2 Center-Aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter counts up to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating in Center-aligned mode. 2 1 0 PWM channel 2 trigger ADC function Disabled #0 1 PWM channel 2 trigger ADC function Enabled #1 read-write PWM3TEN Channel 3 Center-Aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter counts up to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating in Center-aligned mode. 3 1 0 PWM channel 3 trigger ADC function Disabled #0 1 PWM channel 3 trigger ADC function Enabled #1 read-write TSTATUS TSTATUS PWM Trigger Status Register 0x84 read-write 0x00000000 0xFFFFFFFF PWM0TF Channel 0 Center-aligned Trigger Flag\nFor Center-aligned operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM0TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit. 0 1 read-write PWM1TF Channel 1 Center-aligned Trigger Flag\nFor Center-aligned operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM1TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit. 1 1 read-write PWM2TF Channel 2 Center-aligned Trigger Flag\nFor Center-aligned operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM2TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit. 2 1 read-write PWM3TF Channel 3 Center-aligned Trigger Flag\nFor Center-aligned operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM3TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit. 3 1 read-write SYNCBUSY0 SYNCBUSY0 PWM0 Synchronous Busy Status Register 0x88 read-only 0x00000000 0xFFFFFFFF S_BUSY PWM Synchronous Busy\nWhen software writes CNR0/CMR0/PPR or switch PWM0 operation mode (PCR[3]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes CNR0/CMR0/PPR or switch PWM0 operation mode (PCR[3]) to make sure previous setting has been update completely.\nThis bit will be set when software write CNR0/CMR0/PPR or switch PWM0 operation mode (PCR[3]) and will be cleared by hardware automatically when PWM update these value completely. 0 1 read-only SYNCBUSY1 SYNCBUSY1 PWM1 Synchronous Busy Status Register 0x8C read-only 0x00000000 0xFFFFFFFF S_BUSY PWM Synchronous Busy\nWhen software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR1/CMR1/PPR or switching PWM1 operation mode (PCR[11]) to make sure the previous setting has been updated completely.\nThis bit will be set when software write CNR1/CMR1/PPR or switch PWM1 operation mode (PCR[11]) and will be cleared by hardware automatically when PWM updates these value completely. 0 1 read-only SYNCBUSY2 SYNCBUSY2 PWM2 Synchronous Busy Status Register 0x90 read-only 0x00000000 0xFFFFFFFF S_BUSY PWM Synchronous Busy\nWhen software writes CNR2/CMR2/PPR or switch PWM2 operation mode (PCR[19]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR2/CMR2/PPR or switching PWM2 operation mode (PCR[19]) to make sure the previous setting has been updated completely.\nThis bit will be set when software write CNR2/CMR2/PPR or switch PWM2 operation mode (PCR[19]) and will be cleared by hardware automatically when PWM updates these value completely. 0 1 read-only SYNCBUSY3 SYNCBUSY3 PWM3 Synchronous Busy Status Register 0x94 read-only 0x00000000 0xFFFFFFFF S_BUSY PWM Synchronous Busy\nWhen software writes CNR3/CMR3/PPR or switch PWM3 operation mode (PCR[27]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR3/CMR3/PPR or switching PWM3 operation mode (PCR[27]) to make sure the previous setting has been updated completely.\nThis bit will be set when software write CNR3/CMR3/PPR or switch PWM3 operation mode (PCR[27]) and will be cleared by hardware automatically when PWM updates these value completely. 0 1 read-only CAPPDMACTL CAPPDMACTL PWM PDMA Control Register 0xC0 read-write 0x00000000 0xFFFFFFFF CAP0PDMAEN Channel 0 PDMA Enable\n 0 1 0 Channel 0 PDMA function Disabled #0 1 Channel 0 PDMA function Enabled for the channel 0 captured data and transfer to memory #1 read-write CAP0PDMAMOD Select CRLR0 or CFLR0 to Transfer PDMA\n 1 2 0 Reserved #00 1 CRLR0 #01 2 CFLR0 #10 3 Both CRLR0 and CFLR0 #11 read-write CAP0RFORDER 3 1 0 CFLR0 is the first captured data to memory #0 1 CRLR0 is the first captured data to memory #1 read-write CAP1PDMAEN Channel 1 PDMA Enable\n 8 1 0 Channel 1 PDMA function Disabled #0 1 Channel 1 PDMA function Enabled for the channel 1 captured data and transfer to memory #1 read-write CAP1PDMAMOD Select CRLR1 or CFLR1 to Transfer PDMA\n 9 2 0 Reserved #00 1 CRLR1 #01 2 CFLR1 #10 3 both CRLR1 and CFLR1 #11 read-write CAP1RFORDER Capture channel 1 Rising/Falling Order\n 11 1 0 CFLR1 is the first captured data to memory #0 1 CRLR1 is the first captured data to memory #1 read-write CAP2PDMAEN Channel 2 PDMA Enable\n 16 1 0 Channel 2 PDMA function Disabled #0 1 Channel 2 PDMA function Enabled for the channel 2 captured data and transfer to memory #1 read-write CAP2PDMAMOD Select CRLR2 or CFLR2 to do PDMA Transfer\n 17 2 0 Reserved #00 1 CRLR2 #01 2 CFLR2 #10 3 Both CRLR2 and CFLR2 #11 read-write CAP2RFORDER Capture channel 2 Rising/Falling Order\n 19 1 0 CFLR2 is the first captured data to memory #0 1 CRLR2 is the first captured data to memory #1 read-write CAP3PDMAEN Channel 3 PDMA enable\n 24 1 0 Channel 3 PDMA function Disabled #0 1 Channel 3 PDMA function Enabled for the channel 3 captured data and transfer to memory #1 read-write CAP3PDMAMOD Select CRLR3 or CFLR3 to do PDMA Transfer\n 25 2 0 Reserved #00 1 CRLR3 #01 2 CFLR3 #10 3 Both CRLR3 and CFLR3 #11 read-write CAP3RFORDER Capture Channel 3 Rising/Falling Order\n 27 1 0 CFLR3 is the first captured data to memory #0 1 CRLR3 is the first captured data to memory #1 read-write CAP0PDMA CAP0PDMA PWM PDMA Channel 0 Data Register 0xC4 read-only 0x00000000 0xFFFFFFFF CAP0RFPDMA PDMA data register for channel 0\nit is the capturing value(CFLR0/CRLR0) for channel 0 0 16 read-only CAP1PDMA CAP1PDMA PWM PDMA Channel 1 Data Register 0xC8 read-only 0x00000000 0xFFFFFFFF CAP1RFPDMA PDMA data register for channel 1\nit is the capturing value(CFLR1/CRLR1) for channel 1 0 16 read-only CAP2PDMA CAP2PDMA PWM PDMA Channel 2 Data Register 0xCC read-only 0x00000000 0xFFFFFFFF CAP2RFPDMA PDMA data register for channel 2\nit is the capturing value(CFLR2/CRLR2) for channel 2 0 16 read-only CAP3PDMA CAP3PDMA PWM PDMA Channel 3 Data Register 0xD0 read-only 0x00000000 0xFFFFFFFF CAP3RFPDMA PDMA data register for channel 3\nit is the capturing value(CFLR3/CRLR3) for channel 3 0 16 read-only SPI0 SPI Register Map SPI 0x40030000 0x0 0xC registers 0x10 0x8 registers 0x20 0x8 registers 0x34 0x14 registers SPI_CNTRL SPI_CNTRL Control and Status Register 0x0 read-write 0x05003004 0xFFFFFFFF GO_BUSY SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA finishes the data transfer. 0 1 0 Data transfer stopped #0 1 In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master #1 read-write RX_NEG Receive on Negative Edge\n 1 1 0 Received data input signal is latched on the rising edge of SPICLK #0 1 Received data input signal is latched on the falling edge of SPICLK #1 read-write TX_NEG Transmit on Negative Edge\n 2 1 0 Transmitted data output signal is changed on the rising edge of SPICLK #0 1 Transmitted data output signal is changed on the falling edge of SPICLK #1 read-write TX_BIT_LEN Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n 3 5 read-write LSB Send LSB First\n 10 1 0 The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first #0 1 The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1) #1 read-write CLKP Clock Polarity\n 11 1 0 SPICLK is idle low #0 1 SPICLK is idle high #1 read-write SP_CYCLE Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPICLK clock cycle. 12 4 read-write IF Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. 16 1 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 read-write IE Unit Transfer Interrupt Enable\n 17 1 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transfer interrupt Enabled #1 read-write SLAVE Slave Mode Enable\n 18 1 0 Master mode #0 1 Slave mode #1 read-write REORDER Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\n In Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\n The byte reorder function is not supported when the variable serial clock function or Dual I/O mode is enabled. 19 1 0 Byte reorder function Disabled #0 1 Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE #1 read-write FIFO FIFO Mode Enable\nNote:\nBefore enabling FIFO mode, the other related settings should be set in advance.\nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after data is written into the FIFO buffer by software; the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0. 21 1 0 FIFO mode Disabled #0 1 FIFO mode Enabled #1 read-write TWOB 2-Bit Mode Enable\nNote: When 2-bit mode is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0. 22 1 0 2-bit mode Disabled #0 1 2-bit mode Enabled #1 read-write VARCLK_EN Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode). 23 1 0 Serial clock output frequency is fixed and decided only by the value of DIVIDER #0 1 Serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2 #1 read-write RX_EMPTY Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n 24 1 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 read-only RX_FULL Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n 25 1 0 Receive FIOF buffer is not full #0 1 Receive FIFO buffer is full #1 read-only TX_EMPTY Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].\n 26 1 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 read-only TX_FULL Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n 27 1 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 read-only SPI_DIVIDER SPI_DIVIDER Clock Divider Register 0x4 read-write 0x00000000 0xFFFFFFFF DIVIDER Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI engine clock source, which is defined in the CLKSEL1 register. 0 8 read-write DIVIDER2 Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning. 16 8 read-write SPI_SSR SPI_SSR Slave Select Register 0x8 read-write 0x00000000 0xFFFFFFFF SSR Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state; writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL. \nNote: SPISSx0 is defined as the slave select input in Slave mode. 0 2 read-write SS_LVL Slave Select Active Level\nThis bit defines the active status of slave select signal (SPISSx0/1).\n 2 1 0 The slave select signal SPISSx0/1 is active on low-level/falling-edge #0 1 The slave select signal SPISSx0/1 is active on high-level/rising-edge #1 read-write AUTOSS Automatic Slave Select Function Enable (Master Only)\n 3 1 0 If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0] #0 1 If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished #1 read-write SS_LTRIG Slave Select Level Trigger Enable (Slave Only)\n 4 1 0 Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge #0 1 Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high #1 read-write LTRIG_FLAG Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning. 5 1 0 Transferred bit length of one transaction does not meet the specified requirement #0 1 Transferred bit length meets the specified requirement which defined in TX_BIT_LEN #1 read-write SPI_RX0 SPI_RX0 Data Receive Register 0 0x10 read-only 0x00000000 0xFFFFFFFF RX Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register. 0 32 read-only SPI_RX1 SPI_RX1 Data Receive Registe 1 0x14 SPI_TX0 SPI_TX0 Data Transmit Register 0 0x20 write-only 0x00000000 0xFFFFFFFF TX Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1 0 32 write-only SPI_TX1 SPI_TX1 Data Transmit Register 1 0x24 SPI_VARCLK SPI_VARCLK Variable Clock Pattern Register 0x34 read-write 0x007FFF87 0xFFFFFFFF VARCLK Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the "Variable Clock Function" paragraph for more detail description. 0 32 read-write SPI_DMA SPI_DMA SPI DMA Control Register 0x38 read-write 0x00000000 0xFFFFFFFF TX_DMA_GO Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit PDMA function is used to transfer data, the GO_BUSY bit should not be set to 1 by software. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn Slave mode and when FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI serial clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 serial clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit Transfer mode is enabled, additional 18 APB clock periods for the above conditions is required. 0 1 read-write RX_DMA_GO Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit should be set by software.\nEnabling FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn Slave mode and when FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave engine clock periods + 4 APB clock periods) for edge-trigger mode or (9.5 SPI slave engine clock periods + 4 APB clock periods) for level-trigger mode. 1 1 read-write PDMA_RST PDMA Reset\n 2 1 0 No effect #0 1 Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically #1 read-write SPI_CNTRL2 SPI_CNTRL2 Control and Status Register 2 0x3C read-write 0x00001000 0xFFFFFFFF NOSLVSEL Slave 3-Wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically. 8 1 0 4-wire bi-direction interface #0 1 3-wire bi-direction interface #1 read-write SLV_ABORT Slave 3-Wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software. 9 1 read-write SSTA_INTEN Slave 3-Wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n 10 1 0 Transaction start interrupt Disabled #0 1 Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared #1 read-write SLV_START_INTSTS Slave 3-Wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n 11 1 0 Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1 #0 1 A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit #1 read-write DUAL_IO_DIR Dual I/O Mode Direction Control\n 12 1 0 Dual Input mode #0 1 Dual Output mode #1 read-write DUAL_IO_EN Dual I/O Mode Enable\n 13 1 0 Dual I/O mode Disabled #0 1 Dual I/O mode Enabled #1 read-write SS_INT_OPT Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n 16 1 0 As the slave select signal goes to inactive level, the IF bit will NOT be set to 1 #0 1 As the slave select signal goes to inactive level, the IF bit will be set to 1 #1 read-write BCn SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details. 31 1 0 Backward compatible clock configuration #0 1 Clock configuration is not backward compatible #1 read-write SPI_FIFO_CTL SPI_FIFO_CTL SPI FIFO Control Register 0x40 read-write 0x44000000 0xFFFFFFFF RX_CLR Clear Receive FIFO Buffer\n 0 1 0 No effect #0 1 Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software #1 read-write TX_CLR Clear Transmit FIFO Buffer\n 1 1 0 No effect #0 1 Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software #1 read-write RX_INTEN Receive Threshold Interrupt Enable\n 2 1 0 RX threshold interrupt Disabled #0 1 RX threshold interrupt Enabled #1 read-write TX_INTEN Transmit Threshold Interrupt Enable\n 3 1 0 TX threshold interrupt Disabled #0 1 TX threshold interrupt Enabled #1 read-write RXOV_INTEN Receive FIFO Overrun Interrupt Enable\n 6 1 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 read-write TIMEOUT_INTEN Receive FIFO Time-out Interrupt Enable \n 21 1 0 Time-out interrupt Disabled #0 1 Time-out interrupt Enabled #1 read-write RX_THRESHOLD Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0. 24 3 read-write TX_THRESHOLD Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0. 28 3 read-write SPI_STATUS SPI_STATUS SPI Status Register 0x44 read-write 0x05000000 0xFFFFFFFF RX_INTSTS Receive FIFO Threshold Interrupt Status (Read Only)\n 0 1 0 The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD #1 read-only RX_OVERRUN Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself. 2 1 read-write TX_INTSTS Transmit FIFO Threshold Interrupt Status (Read Only)\n 4 1 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD #1 read-only SLV_START_INTSTS Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n 11 1 0 Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1 #0 1 A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit #1 read-write RX_FIFO_COUNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 12 4 read-only IF SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself. 16 1 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 read-write TIMEOUT Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. 20 1 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 read-write RX_EMPTY Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n 24 1 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 read-only RX_FULL Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n 25 1 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 read-only TX_EMPTY Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n 26 1 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 read-only TX_FULL Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n 27 1 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 read-only TX_FIFO_COUNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only SPI1 SPI Register Map SPI 0x40034000 0x0 0xC registers 0x10 0x8 registers 0x20 0x8 registers 0x34 0x14 registers SPI_CNTRL SPI_CNTRL Control and Status Register 0x0 read-write 0x05003004 0xFFFFFFFF GO_BUSY SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA finishes the data transfer. 0 1 0 Data transfer stopped #0 1 In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master #1 read-write RX_NEG Receive on Negative Edge\n 1 1 0 Received data input signal is latched on the rising edge of SPICLK #0 1 Received data input signal is latched on the falling edge of SPICLK #1 read-write TX_NEG Transmit on Negative Edge\n 2 1 0 Transmitted data output signal is changed on the rising edge of SPICLK #0 1 Transmitted data output signal is changed on the falling edge of SPICLK #1 read-write TX_BIT_LEN Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n 3 5 read-write LSB Send LSB First\n 10 1 0 The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first #0 1 The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1) #1 read-write CLKP Clock Polarity\n 11 1 0 SPICLK is idle low #0 1 SPICLK is idle high #1 read-write SP_CYCLE Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPICLK clock cycle. 12 4 read-write IF Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. 16 1 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 read-write IE Unit Transfer Interrupt Enable\n 17 1 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transfer interrupt Enabled #1 read-write SLAVE Slave Mode Enable\n 18 1 0 Master mode #0 1 Slave mode #1 read-write REORDER Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\n In Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\n The byte reorder function is not supported when the variable serial clock function or Dual I/O mode is enabled. 19 1 0 Byte reorder function Disabled #0 1 Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE #1 read-write FIFO FIFO Mode Enable\nNote:\nBefore enabling FIFO mode, the other related settings should be set in advance.\nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after data is written into the FIFO buffer by software; the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0. 21 1 0 FIFO mode Disabled #0 1 FIFO mode Enabled #1 read-write TWOB 2-Bit Mode Enable\nNote: When 2-bit mode is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0. 22 1 0 2-bit mode Disabled #0 1 2-bit mode Enabled #1 read-write VARCLK_EN Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode). 23 1 0 Serial clock output frequency is fixed and decided only by the value of DIVIDER #0 1 Serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2 #1 read-write RX_EMPTY Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n 24 1 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 read-only RX_FULL Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n 25 1 0 Receive FIOF buffer is not full #0 1 Receive FIFO buffer is full #1 read-only TX_EMPTY Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].\n 26 1 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 read-only TX_FULL Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n 27 1 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 read-only SPI_DIVIDER SPI_DIVIDER Clock Divider Register 0x4 read-write 0x00000000 0xFFFFFFFF DIVIDER Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI engine clock source, which is defined in the CLKSEL1 register. 0 8 read-write DIVIDER2 Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning. 16 8 read-write SPI_SSR SPI_SSR Slave Select Register 0x8 read-write 0x00000000 0xFFFFFFFF SSR Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state; writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL. \nNote: SPISSx0 is defined as the slave select input in Slave mode. 0 2 read-write SS_LVL Slave Select Active Level\nThis bit defines the active status of slave select signal (SPISSx0/1).\n 2 1 0 The slave select signal SPISSx0/1 is active on low-level/falling-edge #0 1 The slave select signal SPISSx0/1 is active on high-level/rising-edge #1 read-write AUTOSS Automatic Slave Select Function Enable (Master Only)\n 3 1 0 If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0] #0 1 If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished #1 read-write SS_LTRIG Slave Select Level Trigger Enable (Slave Only)\n 4 1 0 Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge #0 1 Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high #1 read-write LTRIG_FLAG Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning. 5 1 0 Transferred bit length of one transaction does not meet the specified requirement #0 1 Transferred bit length meets the specified requirement which defined in TX_BIT_LEN #1 read-write SPI_RX0 SPI_RX0 Data Receive Register 0 0x10 read-only 0x00000000 0xFFFFFFFF RX Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register. 0 32 read-only SPI_RX1 SPI_RX1 Data Receive Register 1 0x14 SPI_TX0 SPI_TX0 Data Transmit Register 0 0x20 write-only 0x00000000 0xFFFFFFFF TX Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1 0 32 write-only SPI_TX1 SPI_TX1 Data Transmit Register 1 0x24 SPI_VARCLK SPI_VARCLK Variable Clock Pattern Register 0x34 read-write 0x007FFF87 0xFFFFFFFF VARCLK Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the "Variable Clock Function" paragraph for more detail description. 0 32 read-write SPI_DMA SPI_DMA SPI DMA Control Register 0x38 read-write 0x00000000 0xFFFFFFFF TX_DMA_GO Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit PDMA function is used to transfer data, the GO_BUSY bit should not be set to 1 by software. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn Slave mode and when FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI serial clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 serial clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit Transfer mode is enabled, additional 18 APB clock periods for the above conditions is required. 0 1 read-write RX_DMA_GO Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit should be set by software.\nEnabling FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn Slave mode and when FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave engine clock periods + 4 APB clock periods) for edge-trigger mode or (9.5 SPI slave engine clock periods + 4 APB clock periods) for level-trigger mode. 1 1 read-write PDMA_RST PDMA Reset\n 2 1 0 No effect #0 1 Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically #1 read-write SPI_CNTRL2 SPI_CNTRL2 Control and Status Register 2 0x3C read-write 0x00001000 0xFFFFFFFF NOSLVSEL Slave 3-Wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically. 8 1 0 4-wire bi-direction interface #0 1 3-wire bi-direction interface #1 read-write SLV_ABORT Slave 3-Wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software. 9 1 read-write SSTA_INTEN Slave 3-Wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n 10 1 0 Transaction start interrupt Disabled #0 1 Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared #1 read-write SLV_START_INTSTS Slave 3-Wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n 11 1 0 Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1 #0 1 A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit #1 read-write DUAL_IO_DIR Dual I/O Mode Direction Control\n 12 1 0 Dual Input mode #0 1 Dual Output mode #1 read-write DUAL_IO_EN Dual I/O Mode Enable\n 13 1 0 Dual I/O mode Disabled #0 1 Dual I/O mode Enabled #1 read-write SS_INT_OPT Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n 16 1 0 As the slave select signal goes to inactive level, the IF bit will NOT be set to 1 #0 1 As the slave select signal goes to inactive level, the IF bit will be set to 1 #1 read-write BCn SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details. 31 1 0 Backward compatible clock configuration #0 1 Clock configuration is not backward compatible #1 read-write SPI_FIFO_CTL SPI_FIFO_CTL SPI FIFO Control Register 0x40 read-write 0x44000000 0xFFFFFFFF RX_CLR Clear Receive FIFO Buffer\n 0 1 0 No effect #0 1 Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software #1 read-write TX_CLR Clear Transmit FIFO Buffer\n 1 1 0 No effect #0 1 Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software #1 read-write RX_INTEN Receive Threshold Interrupt Enable\n 2 1 0 RX threshold interrupt Disabled #0 1 RX threshold interrupt Enabled #1 read-write TX_INTEN Transmit Threshold Interrupt Enable\n 3 1 0 TX threshold interrupt Disabled #0 1 TX threshold interrupt Enabled #1 read-write RXOV_INTEN Receive FIFO Overrun Interrupt Enable\n 6 1 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 read-write TIMEOUT_INTEN Receive FIFO Time-out Interrupt Enable \n 21 1 0 Time-out interrupt Disabled #0 1 Time-out interrupt Enabled #1 read-write RX_THRESHOLD Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0. 24 3 read-write TX_THRESHOLD Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0. 28 3 read-write SPI_STATUS SPI_STATUS SPI Status Register 0x44 read-write 0x05000000 0xFFFFFFFF RX_INTSTS Receive FIFO Threshold Interrupt Status (Read Only)\n 0 1 0 The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD #1 read-only RX_OVERRUN Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself. 2 1 read-write TX_INTSTS Transmit FIFO Threshold Interrupt Status (Read Only)\n 4 1 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD #1 read-only SLV_START_INTSTS Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n 11 1 0 Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1 #0 1 A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit #1 read-write RX_FIFO_COUNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 12 4 read-only IF SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself. 16 1 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 read-write TIMEOUT Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. 20 1 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 read-write RX_EMPTY Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n 24 1 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 read-only RX_FULL Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n 25 1 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 read-only TX_EMPTY Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n 26 1 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 read-only TX_FULL Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n 27 1 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 read-only TX_FIFO_COUNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only SPI2 SPI Register Map SPI 0x40130000 0x0 0xC registers 0x10 0x8 registers 0x20 0x8 registers 0x34 0x14 registers SPI_CNTRL SPI_CNTRL Control and Status Register 0x0 read-write 0x05003004 0xFFFFFFFF GO_BUSY SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA finishes the data transfer. 0 1 0 Data transfer stopped #0 1 In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master #1 read-write RX_NEG Receive on Negative Edge\n 1 1 0 Received data input signal is latched on the rising edge of SPICLK #0 1 Received data input signal is latched on the falling edge of SPICLK #1 read-write TX_NEG Transmit on Negative Edge\n 2 1 0 Transmitted data output signal is changed on the rising edge of SPICLK #0 1 Transmitted data output signal is changed on the falling edge of SPICLK #1 read-write TX_BIT_LEN Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n 3 5 read-write LSB Send LSB First\n 10 1 0 The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first #0 1 The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1) #1 read-write CLKP Clock Polarity\n 11 1 0 SPICLK is idle low #0 1 SPICLK is idle high #1 read-write SP_CYCLE Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPICLK clock cycle. 12 4 read-write IF Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. 16 1 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 read-write IE Unit Transfer Interrupt Enable\n 17 1 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transfer interrupt Enabled #1 read-write SLAVE Slave Mode Enable\n 18 1 0 Master mode #0 1 Slave mode #1 read-write REORDER Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\n In Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\n The byte reorder function is not supported when the variable serial clock function or Dual I/O mode is enabled. 19 1 0 Byte reorder function Disabled #0 1 Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE #1 read-write FIFO FIFO Mode Enable\nNote:\nBefore enabling FIFO mode, the other related settings should be set in advance.\nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after data is written into the FIFO buffer by software; the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0. 21 1 0 FIFO mode Disabled #0 1 FIFO mode Enabled #1 read-write TWOB 2-Bit Mode Enable\nNote: When 2-bit mode is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0. 22 1 0 2-bit mode Disabled #0 1 2-bit mode Enabled #1 read-write VARCLK_EN Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode). 23 1 0 Serial clock output frequency is fixed and decided only by the value of DIVIDER #0 1 Serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2 #1 read-write RX_EMPTY Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n 24 1 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 read-only RX_FULL Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n 25 1 0 Receive FIOF buffer is not full #0 1 Receive FIFO buffer is full #1 read-only TX_EMPTY Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].\n 26 1 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 read-only TX_FULL Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n 27 1 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 read-only SPI_DIVIDER SPI_DIVIDER Clock Divider Register 0x4 read-write 0x00000000 0xFFFFFFFF DIVIDER Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI engine clock source, which is defined in the CLKSEL1 register. 0 8 read-write DIVIDER2 Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning. 16 8 read-write SPI_SSR SPI_SSR Slave Select Register 0x8 read-write 0x00000000 0xFFFFFFFF SSR Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state; writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL. \nNote: SPISSx0 is defined as the slave select input in Slave mode. 0 2 read-write SS_LVL Slave Select Active Level\nThis bit defines the active status of slave select signal (SPISSx0/1).\n 2 1 0 The slave select signal SPISSx0/1 is active on low-level/falling-edge #0 1 The slave select signal SPISSx0/1 is active on high-level/rising-edge #1 read-write AUTOSS Automatic Slave Select Function Enable (Master Only)\n 3 1 0 If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0] #0 1 If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished #1 read-write SS_LTRIG Slave Select Level Trigger Enable (Slave Only)\n 4 1 0 Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge #0 1 Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high #1 read-write LTRIG_FLAG Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning. 5 1 0 Transferred bit length of one transaction does not meet the specified requirement #0 1 Transferred bit length meets the specified requirement which defined in TX_BIT_LEN #1 read-write SPI_RX0 SPI_RX0 Data Receive Register 0 0x10 read-only 0x00000000 0xFFFFFFFF RX Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register. 0 32 read-only SPI_RX1 SPI_RX1 Data Receive Register 1 0x14 SPI_TX0 SPI_TX0 Data Transmit Register 0 0x20 write-only 0x00000000 0xFFFFFFFF TX Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1 0 32 write-only SPI_TX1 SPI_TX1 Data Transmit Register 1 0x24 SPI_VARCLK SPI_VARCLK Variable Clock Pattern Register 0x34 read-write 0x007FFF87 0xFFFFFFFF VARCLK Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the "Variable Clock Function" paragraph for more detail description. 0 32 read-write SPI_DMA SPI_DMA SPI DMA Control Register 0x38 read-write 0x00000000 0xFFFFFFFF TX_DMA_GO Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit PDMA function is used to transfer data, the GO_BUSY bit should not be set to 1 by software. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn Slave mode and when FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI serial clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 serial clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit Transfer mode is enabled, additional 18 APB clock periods for the above conditions is required. 0 1 read-write RX_DMA_GO Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit should be set by software.\nEnabling FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn Slave mode and when FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave engine clock periods + 4 APB clock periods) for edge-trigger mode or (9.5 SPI slave engine clock periods + 4 APB clock periods) for level-trigger mode. 1 1 read-write PDMA_RST PDMA Reset\n 2 1 0 No effect #0 1 Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically #1 read-write SPI_CNTRL2 SPI_CNTRL2 Control and Status Register 2 0x3C read-write 0x00001000 0xFFFFFFFF NOSLVSEL Slave 3-Wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically. 8 1 0 4-wire bi-direction interface #0 1 3-wire bi-direction interface #1 read-write SLV_ABORT Slave 3-Wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software. 9 1 read-write SSTA_INTEN Slave 3-Wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n 10 1 0 Transaction start interrupt Disabled #0 1 Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared #1 read-write SLV_START_INTSTS Slave 3-Wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n 11 1 0 Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1 #0 1 A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit #1 read-write DUAL_IO_DIR Dual I/O Mode Direction Control\n 12 1 0 Dual Input mode #0 1 Dual Output mode #1 read-write DUAL_IO_EN Dual I/O Mode Enable\n 13 1 0 Dual I/O mode Disabled #0 1 Dual I/O mode Enabled #1 read-write SS_INT_OPT Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n 16 1 0 As the slave select signal goes to inactive level, the IF bit will NOT be set to 1 #0 1 As the slave select signal goes to inactive level, the IF bit will be set to 1 #1 read-write BCn SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details. 31 1 0 Backward compatible clock configuration #0 1 Clock configuration is not backward compatible #1 read-write SPI_FIFO_CTL SPI_FIFO_CTL SPI FIFO Control Register 0x40 read-write 0x44000000 0xFFFFFFFF RX_CLR Clear Receive FIFO Buffer\n 0 1 0 No effect #0 1 Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software #1 read-write TX_CLR Clear Transmit FIFO Buffer\n 1 1 0 No effect #0 1 Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software #1 read-write RX_INTEN Receive Threshold Interrupt Enable\n 2 1 0 RX threshold interrupt Disabled #0 1 RX threshold interrupt Enabled #1 read-write TX_INTEN Transmit Threshold Interrupt Enable\n 3 1 0 TX threshold interrupt Disabled #0 1 TX threshold interrupt Enabled #1 read-write RXOV_INTEN Receive FIFO Overrun Interrupt Enable\n 6 1 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 read-write TIMEOUT_INTEN Receive FIFO Time-out Interrupt Enable \n 21 1 0 Time-out interrupt Disabled #0 1 Time-out interrupt Enabled #1 read-write RX_THRESHOLD Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0. 24 3 read-write TX_THRESHOLD Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0. 28 3 read-write SPI_STATUS SPI_STATUS SPI Status Register 0x44 read-write 0x05000000 0xFFFFFFFF RX_INTSTS Receive FIFO Threshold Interrupt Status (Read Only)\n 0 1 0 The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD #1 read-only RX_OVERRUN Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself. 2 1 read-write TX_INTSTS Transmit FIFO Threshold Interrupt Status (Read Only)\n 4 1 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD #1 read-only SLV_START_INTSTS Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n 11 1 0 Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1 #0 1 A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit #1 read-write RX_FIFO_COUNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 12 4 read-only IF SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself. 16 1 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 read-write TIMEOUT Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. 20 1 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 read-write RX_EMPTY Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n 24 1 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 read-only RX_FULL Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n 25 1 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 read-only TX_EMPTY Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n 26 1 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 read-only TX_FULL Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n 27 1 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 read-only TX_FIFO_COUNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only TMR01 TIMER Register Map TIMER 0x40010000 0x0 0x1C registers 0x20 0x1C registers TCSR0 TCSR0 Timer0 Control and Status Register 0x0 read-write 0x00000005 0xFFFFFFFF PRESCALE Pre-scale Counter\n 0 8 read-write TDR_EN Data Load Enable\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n 16 1 0 Timer Data Register update Disabled #0 1 Timer Data Register update Enabled #1 read-write WAKE_EN Wake-up Enable\nWhen WAKE_EN is set and the TIF is set, the timer controller will generator a wake-up trigger event to CPU.\n 23 1 0 Wake-up trigger event Disabled #0 1 Wake-up trigger event Enabled #1 read-write CTB Counter Mode Enable Bit \nThis bit is the counter mode enable bit. When Timer is used as an event counter, this bit should be set to 1 and Timer will work as an event counter. The counter detect phase can be selected as rising/falling edge of external pin by TX_PHASE field.\n 24 1 0 Counter mode Disabled #0 1 Counter mode Enabled #1 read-write CACT Timer Active Status Bit (Read only)\nThis bit indicates the up-timer status.\n 25 1 0 Timer is not active #0 1 Timer is active #1 read-only CRST Timer Reset Bit\nSet this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0.\n 26 1 0 No effect #0 1 Reset Timer's 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit #1 read-write MODE Timer Operating Mode\n 27 2 read-write IE Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal when the associated up-timer value is equal to TCMPR. 29 1 0 Timer Interrupt Disabled #0 1 Timer Interrupt Enabled #1 read-write CEN Timer Enable Bit\n 30 1 0 Stops/Suspends counting #0 1 Starts counting #1 read-write DBGACK_TMR ICE debug mode acknowledge Disable (Write-protection Bit)\nTIMER counter will keep going no matter ICE debug mode acknowledged or not. 31 1 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement disabled #1 read-write TCMPR0 TCMPR0 Timer0 Compare Register 0x4 read-write 0x00000000 0xFFFFFFFF TCMP Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state.\nNote2: When timer is operating in continuous counting mode, the 24-bit up-timer will count continuously if software writes a new value into TCMP. If timer is operating at other modes, the 24-bit up-timer will restart counting and using newest TCMP value to be the compared value if software writes a new value into TCMP. 0 24 read-write TISR0 TISR0 Timer0 Interrupt Status Register 0x8 read-write 0x00000000 0xFFFFFFFF TIF Timer Interrupt Flag\nThis bit indicates the interrupt status of timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit up-timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit. 0 1 read-write TWF Timer Wakeup Flag\nIf timer causes CPU wakes up from power-down mode, this bit will be set to high.\nIt must be cleared by software with a write 1 to this bit.\n 1 1 0 Timer does not cause CPU wakeup #0 1 CPU wakes up from sleep or power-down mode by timer time-out #1 read-write TDR0 TDR0 Timer0 Data Register 0xC read-only 0x00000000 0xFFFFFFFF TDR Timer Data Register\nUser can read TDR for getting current 24- bits up event counter value if TCSR[24] is 1 0 24 read-only TCAP0 TCAP0 Timer0 Capture Data Register 0x10 read-only 0x00000000 0xFFFFFFFF TCAP Timer Capture Data Register\nWhen TEXEN (TEXCON[3]) is set, RSTCAPn(TTXCON[4]) is 0, and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred, the internal 24-bit up-timer value will be loaded into TCAP. User can read this register for the counter value. 0 24 read-only TEXCON0 TEXCON0 Timer0 External Control Register 0x14 read-write 0x00000000 0xFFFFFFFF TX_PHASE Timer External Count Phase \nThis bit indicates the external count pin phase.\n 0 1 0 A falling edge of external count pin will be counted #0 1 A rising edge of external count pin will be counted #1 read-write TEX_EDGE Timer External Pin Edge Detect\n 1 2 0 1 to 0 transition on TEX will be detected #00 1 0 to 1 transition on TEX will be detected #01 2 Either 1 to 0 or 0 to 1 transition on TEX will be detected #10 3 Reserved #11 read-write TEXEN Timer External Pin Enable \nThis bit enables the reset/capture function on the TEX pin. \n 3 1 0 TEX pin will be ignored #0 1 Transition detected on the TEX pin will result in capture or reset of timer counter #1 read-write RSTCAPn Timer External Reset Counter/Capture Mode Selection\n 4 1 0 TEX transition is used as the timer capture function #0 1 TEX transition is used as the timer counter reset function #1 read-write TEXIEN Timer External Interrupt Enable Bit\n 5 1 0 Timer external interrupt Disabled #0 1 Timer external interrupt Enabled #1 read-write TEXDB Timer External Capture Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of T0EX~T3EX pin is detected with de-bounce circuit. 6 1 0 De-bounce Disabled #0 1 De-bounce Enabled #1 read-write TCDB Timer Counter Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of TM0~TM3 pin is detected with de-bounce circuit. 7 1 0 De-bounce Disabled #0 1 De-bounce Enabled #1 read-write TEXISR0 TEXISR0 Timer0 External Interrupt Status Register 0x18 read-write 0x00000000 0xFFFFFFFF TEXIF Timer External Interrupt Flag\nThis bit indicates the external interrupt status of Timer.\nThis bit is set by hardware when TEXEN (TEXCON[3]) is to 1, and the transition on the TEX pins associated with TEX_EDGE (TEXCON[2:1]) setting is occurred. It is cleared by writing 1 to this bit.\n 0 1 read-write TCSR1 TCSR1 Timer1 Control and Status Register 0x20 TCMPR1 TCMPR1 Timer1 Compare Register 0x24 TISR1 TISR1 Timer1 Interrupt Status Register 0x28 TDR1 TDR1 Timer1 Data Register 0x2C TCAP1 TCAP1 Timer1 Capture Data Register 0x30 TEXCON1 TEXCON1 Timer1 External Control Register 0x34 TEXISR1 TEXISR1 Timer1 External Interrupt Status Register 0x38 TMR23 TIMER Register Map TIMER 0x40110000 0x0 0x1C registers 0x20 0x1C registers TCSR2 TCSR2 Timer2 Control and Status Register 0x0 read-write 0x00000005 0xFFFFFFFF PRESCALE Pre-scale Counter\n 0 8 read-write TDR_EN Data Load Enable\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n 16 1 0 Timer Data Register update Disabled #0 1 Timer Data Register update Enabled #1 read-write WAKE_EN Wake-up Enable\nWhen WAKE_EN is set and the TIF is set, the timer controller will generator a wake-up trigger event to CPU.\n 23 1 0 Wake-up trigger event Disabled #0 1 Wake-up trigger event Enabled #1 read-write CTB Counter Mode Enable Bit \nThis bit is the counter mode enable bit. When Timer is used as an event counter, this bit should be set to 1 and Timer will work as an event counter. The counter detect phase can be selected as rising/falling edge of external pin by TX_PHASE field.\n 24 1 0 Counter mode Disabled #0 1 Counter mode Enabled #1 read-write CACT Timer Active Status Bit (Read only)\nThis bit indicates the up-timer status.\n 25 1 0 Timer is not active #0 1 Timer is active #1 read-only CRST Timer Reset Bit\nSet this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0.\n 26 1 0 No effect #0 1 Reset Timer's 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit #1 read-write MODE Timer Operating Mode\n 27 2 read-write IE Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal when the associated up-timer value is equal to TCMPR. 29 1 0 Timer Interrupt Disabled #0 1 Timer Interrupt Enabled #1 read-write CEN Timer Enable Bit\n 30 1 0 Stops/Suspends counting #0 1 Starts counting #1 read-write DBGACK_TMR ICE debug mode acknowledge Disable (Write-protection Bit)\nTIMER counter will keep going no matter ICE debug mode acknowledged or not. 31 1 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement disabled #1 read-write TCMPR2 TCMPR2 Timer2 Compare Register 0x4 read-write 0x00000000 0xFFFFFFFF TCMP Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state.\nNote2: When timer is operating in continuous counting mode, the 24-bit up-timer will count continuously if software writes a new value into TCMP. If timer is operating at other modes, the 24-bit up-timer will restart counting and using newest TCMP value to be the compared value if software writes a new value into TCMP. 0 24 read-write TISR2 TISR2 Timer2 Interrupt Status Register 0x8 read-write 0x00000000 0xFFFFFFFF TIF Timer Interrupt Flag\nThis bit indicates the interrupt status of timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit up-timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit. 0 1 read-write TWF Timer Wakeup Flag\nIf timer causes CPU wakes up from power-down mode, this bit will be set to high.\nIt must be cleared by software with a write 1 to this bit.\n 1 1 0 Timer does not cause CPU wakeup #0 1 CPU wakes up from sleep or power-down mode by timer time-out #1 read-write TDR2 TDR2 Timer2 Data Register 0xC read-only 0x00000000 0xFFFFFFFF TDR Timer Data Register\nUser can read TDR for getting current 24- bits up event counter value if TCSR[24] is 1 0 24 read-only TCAP2 TCAP2 Timer2 Capture Data Register 0x10 read-only 0x00000000 0xFFFFFFFF TCAP Timer Capture Data Register\nWhen TEXEN (TEXCON[3]) is set, RSTCAPn(TTXCON[4]) is 0, and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred, the internal 24-bit up-timer value will be loaded into TCAP. User can read this register for the counter value. 0 24 read-only TEXCON2 TEXCON2 Timer2 External Control Register 0x14 read-write 0x00000000 0xFFFFFFFF TX_PHASE Timer External Count Phase \nThis bit indicates the external count pin phase.\n 0 1 0 A falling edge of external count pin will be counted #0 1 A rising edge of external count pin will be counted #1 read-write TEX_EDGE Timer External Pin Edge Detect\n 1 2 0 1 to 0 transition on TEX will be detected #00 1 0 to 1 transition on TEX will be detected #01 2 Either 1 to 0 or 0 to 1 transition on TEX will be detected #10 3 Reserved #11 read-write TEXEN Timer External Pin Enable \nThis bit enables the reset/capture function on the TEX pin. \n 3 1 0 TEX pin will be ignored #0 1 Transition detected on the TEX pin will result in capture or reset of timer counter #1 read-write RSTCAPn Timer External Reset Counter/Capture Mode Selection\n 4 1 0 TEX transition is used as the timer capture function #0 1 TEX transition is used as the timer counter reset function #1 read-write TEXIEN Timer External Interrupt Enable Bit\n 5 1 0 Timer external interrupt Disabled #0 1 Timer external interrupt Enabled #1 read-write TEXDB Timer External Capture Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of T0EX~T3EX pin is detected with de-bounce circuit. 6 1 0 De-bounce Disabled #0 1 De-bounce Enabled #1 read-write TCDB Timer Counter Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of TM0~TM3 pin is detected with de-bounce circuit. 7 1 0 De-bounce Disabled #0 1 De-bounce Enabled #1 read-write TEXISR2 TEXISR2 Timer2 External Interrupt Status Register 0x18 read-write 0x00000000 0xFFFFFFFF TEXIF Timer External Interrupt Flag\nThis bit indicates the external interrupt status of Timer.\nThis bit is set by hardware when TEXEN (TEXCON[3]) is to 1, and the transition on the TEX pins associated with TEX_EDGE (TEXCON[2:1]) setting is occurred. It is cleared by writing 1 to this bit.\n 0 1 read-write TCSR3 TCSR3 Timer3 Control and Status Register 0x20 TCMPR3 TCMPR3 Timer3 Compare Register 0x24 TISR3 TISR3 Timer3 Interrupt Status Register 0x28 TDR3 TDR3 Timer3 Data Register 0x2C TCAP3 TCAP3 Timer3 Capture Data Register 0x30 TEXCON3 TEXCON3 Timer3 External Control Register 0x34 TEXISR3 TEXISR3 Timer3 External Interrupt Status Register 0x38 WDT WDT Register Map WDT 0x40004000 0x0 0x8 registers WTCR WTCR Watchdog Timer Control Register 0x0 read-write 0x00000700 0xFFFFFFFF WTR Clear Watchdog Timer (Write-protection Bit)\nSetting this bit will clear the Watchdog timer.\nNote: This bit will be automatically cleared by hardware. 0 1 0 No effect #0 1 Reset the contents of the Watchdog timer #1 read-write WTRE Watchdog Timer Reset Enable (Write-protection Bit)\nSetting this bit will enable the Watchdog timer reset function.\n 1 1 0 Watchdog timer reset function Disabled #0 1 Watchdog timer reset function Enabled #1 read-write WTRF Watchdog Timer Reset Flag\nWhen the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If WTRE is disabled, the Watchdog timer has no effect on this bit.\nNote: This bit is cleared by writing 1 to this bit. 2 1 0 Watchdog timer reset did not occur #0 1 Watchdog timer reset occurred #1 read-write WTIF Watchdog Timer Interrupt Flag\nIf the Watchdog timer interrupt is enabled, the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred.\nNote: This bit is cleared by writing 1 to this bit. 3 1 0 Watchdog timer interrupt did not occur #0 1 Watchdog timer interrupt occurred #1 read-write WTWKE Watchdog Timer Wake-up Function Enable bit (Write-protection Bit)\nNote: Chip can be woken up by WDT only if WDT clock source select RC10K. 4 1 0 Watchdog timer Wake-up chip function Disabled #0 1 Wake-up function Enabled so that Watchdog timer time-out can wake-up chip from Power-down mode #1 read-write WTWKF Watchdog Timer Wake-up Flag\nIf Watchdog timer causes chip to wake up from Power-down mode, this bit will be set to high. It must be cleared by software by writing 1 to this bit.\n 5 1 0 Watchdog timer does not cause chip wake up #0 1 Chip woken up from Idle or Power-down mode by Watchdog time-out #1 read-write WTIE Watchdog Timer Interrupt Enable (Write-protection Bit)\n 6 1 0 Watchdog timer interrupt Disabled #0 1 Watchdog timer interrupt Enabled #1 read-write WTE Watchdog Timer Enable (Write-protection Bit)\n 7 1 0 Watchdog timer Disabled (This action will reset the internal counter) #0 1 Watchdog timer Enabled #1 read-write WTIS Watchdog Timer Interval Selection (Write-protection Bit)\n 8 3 read-write DBGACK_WDT ICE Debug Mode Acknowledge Disable (Write-protection Bit)\nWatchdog Timer counter will keep going no matter ICE debug mode acknowledged or not. 31 1 0 ICE debug mode acknowledgement affects Watchdog Timer counting #0 1 ICE debug mode acknowledgement Disabled #1 read-write WTCRALT WTCRALT Watchdog Timer Alternative Control Register 0x4 read-write 0x00000000 0xFFFFFFFF WTRDSEL Watchdog Timer Reset Delay Select (Write-protection Bits)\nWhen watchdog time-out happened, software has a time named watchdog reset delay period to clear watchdog timer to prevent watchdog reset happened. Software can select a suitable value of watchdog reset delay period for different watchdog time-out period.\nThese bits are protected bit. It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.\nThis register will be reset if watchdog reset happened 0 2 0 Watchdog reset delay period is 1024 watchdog clock #00 1 Watchdog reset delay period is 128 watchdog clock #01 2 Watchdog reset delay period is 16 watchdog clock #10 3 Watchdog reset delay period is 1 watchdog clock #11 read-write WWDT WWDT Register Map WWDT 0x40004100 0x0 0x10 registers WWDTRLD WWDTRLD Window Watchdog Timer Reload Counter Register 0x0 write-only 0x00000000 0xFFFFFFFF WWDTRLD WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. \nNote: Software can only write WWDTRLD when WWDT counter value between 0 and WINCMP. If software writes WWDTRLD when WWDT counter value larger than WINCMP, WWDT will generate RESET signal. 0 32 write-only WWDTCR WWDTCR Window Watchdog Timer Control Register 0x4 read-write 0x003F0800 0xFFFFFFFF WWDTEN WWDT Enable\nSet this bit to enable the Window Watchdog timer.\n 0 1 0 Window Watchdog timer function Disabled #0 1 Window Watchdog timer function Enabled #1 read-write WWDTIE WWDT Interrupt Enable\nSet this bit to enable the Watchdog timer interrupt function.\n 1 1 0 Watchdog timer interrupt function Disabled #0 1 Watchdog timer interrupt function Enabled #1 read-write PERIODSEL WWDT Pre-scale Period Select\n 8 4 read-write WINCMP WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: Software can only write WWDTRLD when WWDT counter value between 0 and WINCMP. If software writes WWDTRLD when WWDT counter value is larger than WWCMP, WWDT will generate RESET signal. 16 6 read-write DBGACK_WWDT ICE debug mode acknowledge Disable\n 31 1 0 WWDT count stopped if system is in Debug mode #0 1 WWDT still count even system is in Debug mode #1 read-write WWDTSTS WWDTSTS Window Watchdog Timer Status Register 0x8 read-write 0x00000000 0xFFFFFFFF WWDTIF WWDT Compare Match Interrupt Flag\nWhen WWCMP matches the WWDT counter, this bit is set to 1. This bit will be cleared by software write 1 to this bit. 0 1 read-write WWDTRF WWDT Reset Flag\nWhen WWDT counter counts down to 0 or writes WWDTRLD during WWDT counter larger than WINCMP, chip will be reset and this bit is set to 1. Software can write 1 to clear this bit to 0. 1 1 read-write WWDTCVR WWDTCVR Window Watchdog Counter Value Register 0xC read-only 0x0000003F 0xFFFFFFFF WWDTCVAL WWDT Counter Value\nThis register reflects the counter value of window watchdog. This register is read only. 0 6 read-only UART0 UART Register Map UART 0x40050000 0x0 0x34 registers UA_RBR UA_RBR UART Receive Buffer Register 0x0 read-only 0x00000000 0x00000000 RBR Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first). 0 8 read-only UA_THR UA_RBR UA_THR UART Transmit Holding Register 0x0 write-only 0x00000000 0x00000000 THR Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first). 0 8 write-only UA_IER UA_IER UART Interrupt Enable Register 0x4 read-write 0x00000000 0xFFFFFFFF RDA_IEN Receive Data Available Interrupt Enable.\n 0 1 0 INT_RDA Masked off #0 1 INT_RDA Enabled #1 read-write THRE_IEN Transmit Holding Register Empty Interrupt Enable\n 1 1 0 INT_THRE Masked off #0 1 INT_THRE Enabled #1 read-write RLS_IEN Receive Line Status Interrupt Enable \n 2 1 0 INT_RLS Masked off #0 1 INT_RLS Enabled #1 read-write MODEM_IEN Modem Status Interrupt Enable\n 3 1 0 INT_MODEM Masked off #0 1 INT_MODEM Enabled #1 read-write RTO_IEN RX Time Out Interrupt Enable\n 4 1 0 INT_TOUT Masked off #0 1 INT_TOUT Enabled #1 read-write BUF_ERR_IEN Buffer Error Interrupt Enable\n 5 1 0 INT_BUF_ERR Masked off #0 1 INT_BUF_ERR Enabled #1 read-write WAKE_EN UART Wake-up Function Enable\n 6 1 0 UART wake-up function Disabled #0 1 UART wake-up function Enabled, when chip is in Power-down mode, an external CTS change will wake up chip from Power-down mode #1 read-write TIME_OUT_EN Time Out Counter Enable\n 11 1 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 read-write AUTO_RTS_EN RTS Auto Flow Control Enable\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO is equal to the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTS signal. 12 1 0 RTS auto flow control Disabled #0 1 RTS auto flow control Enabled #1 read-write AUTO_CTS_EN CTS Auto Flow Control Enable \nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). 13 1 0 CTS auto flow control Disabled #0 1 CTS auto flow control Enabled #1 read-write DMA_TX_EN TX DMA Enable\nThis bit can enable or disable TX DMA service.\n 14 1 0 TX DMA Disabled #0 1 TX DMA Enabled #1 read-write DMA_RX_EN RX DMA Enable\nThis bit can enable or disable RX DMA service.\n 15 1 0 RX DMA Disabled #0 1 RX DMA Enabled #1 read-write UA_FCR UA_FCR UART FIFO Control Register 0x8 read-write 0x00000101 0xFFFFFFFF RFR RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will be automatically cleared at least 3 UART engine clock cycles. 1 1 0 No effect #0 1 Reset the RX internal state machine and pointers #1 read-write TFR TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will be automatically cleared at least 3 UART engine clock cycles. 2 1 0 No effect #0 1 Reset the TX internal state machine and pointers #1 read-write RFITL RX FIFO Interrupt (INT_RDA) Trigger Level\n 4 4 read-write RX_DIS Receiver Disable Register\nThe receiver is enabled or disabled.\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed. 8 1 0 Receiver Enabled #0 1 Receiver Disabled #1 read-write RTS_TRI_LEV RTS Trigger Level for Auto-flow Control Use\n 16 4 read-write UA_LCR UA_LCR UART Line Control Register 0xC read-write 0x00000000 0xFFFFFFFF WLS Word Length Selection\n 0 2 read-write NSB Number of "STOP bit"\nTwo "STOP bit" are generated when 6-, 7- and 8-bit word length is selected. 2 1 0 One " STOP bit" is generated in the transmitted data #0 1 One and a half " STOP bit" is generated in the transmitted data when 5-bit word length is selected; #1 read-write PBE Parity Bit Enable\n 3 1 0 No parity bit #0 1 Parity bit is generated on each outgoing character and is checked on each incoming data #1 read-write EPE Even Parity Enable\nThis bit has effect only when bit 3 (parity bit enable) is set. 4 1 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 read-write SPE Stick Parity Enable\n 5 1 0 Stick parity Disabled #0 1 If bit 3 and 4 are logic 1, the parity bit is transmitted and cheched as logic 0. If bit 3 si 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1 #1 read-write BCB Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. 6 1 read-write UA_MCR UA_MCR UART Modem Control Register 0x10 read-write 0x00000200 0xFFFFFFFF RTS RTS (Request-To-Send) Signal\n 1 1 0 Drive RTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 0 (If the LEV_RTS set to high level triggered) #0 1 Drive RTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 1 (If the LEV_RTS set to high level triggered) #1 read-write LEV_RTS RTS Trigger Level\nThis bit can change the RTS trigger level.\n 9 1 0 Low level triggered #0 1 High level triggered #1 read-write RTS_ST RTS Pin State (Read Only)\nThis bit is the output pin status of RTS. 13 1 read-only UA_MSR UA_MSR UART Modem Status Register 0x14 read-write 0x00000110 0xFFFFFFFF DCTSF Detect CTS State Change Flag (Read Only)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nSoftware can write 1 to clear this bit to zero. 0 1 read-only CTS_ST CTS Pin Status (Read Only)\nThis bit is the pin status of CTS. 4 1 read-only LEV_CTS CTS Trigger Level\nThis bit can change the CTS trigger level.\n 8 1 0 Low level triggered #0 1 High level triggered #1 read-write UA_FSR UA_FSR UART FIFO Status Register 0x18 read-write 0x10404000 0xFFFFFFFF RX_OVER_IF RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only RS485_ADD_DETF RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it. 3 1 read-only PEF Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it. 4 1 read-only FEF Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it. 5 1 read-only BIF Break Interrupt Flag (Read Only)\nThis bit is set to a logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it. 6 1 read-only RX_POINTER RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one. 8 6 read-only RX_EMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only RX_FULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RX_POINTER is equal to 64/16(UART0/UART1); otherwise, it is cleared by hardware. 15 1 read-only TX_POINTER TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one. 16 6 read-only TX_EMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). 22 1 read-only TX_FULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TX_POINTER is equal to 64/16(UART0/UART1); otherwise, it is cleared by hardware. 23 1 read-only TX_OVER_IF TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. \nNote: This bit is read only, but can be cleared by writing '1' to it. 24 1 read-only TE_FLAG Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only UA_ISR UA_ISR UART Interrupt Status Register 0x1C read-write 0x00000002 0xFFFFFFFF RDA_IF Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX FIFO is equal to the RFITL, the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL). 0 1 read-only THRE_IF Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). 1 1 read-only RLS_IF Receive Line Interrupt Flag (Read Only). \nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. 2 1 read-only MODEM_IF MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF. 3 1 read-only TOUT_IF Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. 4 1 read-only BUF_ERR_IF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared. 5 1 read-only RDA_INT Receive Data Available Interrupt Indicator (Read Only).\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n 8 1 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 read-only THRE_INT Transmit Holding Register Empty Interrupt Indicator (Read Only).\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n 9 1 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 read-only RLS_INT Receive Line Status Interrupt Indicator (Read Only). \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n 10 1 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 read-only MODEM_INT MODEM Status Interrupt Indicator (Read Only).\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n 11 1 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 read-only TOUT_INT Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.\n 12 1 0 No Tout interrupt is generated #0 1 Tout interrupt is generated #1 read-only BUF_ERR_INT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n 13 1 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 read-only HW_RLS_IF In DMA Mode, Receive Line Status Flag (Read Only) \nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. 18 1 read-only HW_MODEM_IF In DMA Mode, MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF. 19 1 read-only HW_TOUT_IF In DMA Mode, Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. 20 1 read-only HW_BUF_ERR_IF In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared. 21 1 read-only HW_RLS_INT In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN and HW_RLS_IF are both set to 1.\n 26 1 0 No RLS interrupt is generated in DMA mode #0 1 RLS interrupt is generated in DMA mode #1 read-only HW_MODEM_INT In DMA Mode, MODEM Status Interrupt Indicator (Read Only) \nThis bit is set if MODEM_IEN and HW_MODEM_IF are both set to 1.\n 27 1 0 No Modem interrupt is generated in DMA mode #0 1 Modem interrupt is generated in DMA mode #1 read-only HW_TOUT_INT In DMA Mode, Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and HW_TOUT_IF are both set to 1.\n 28 1 0 No Tout interrupt is generated in DMA mode #0 1 Tout interrupt is generated in DMA mode #1 read-only HW_BUF_ERR_INT In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and HW_BUF_ERR_IF are both set to 1.\n 29 1 0 No buffer error interrupt is generated in DMA mode #0 1 Buffer error interrupt is generated in DMA mode #1 read-only UA_TOR UA_TOR UART Time Out Register 0x20 read-write 0x00000000 0xFFFFFFFF TOIC Time Out Interrupt Comparator\n 0 8 read-write DLY TX Delay time value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. 8 8 read-write UA_BAUD UA_BAUD UART Baud Rate Divisor Register 0x24 read-write 0x0F000000 0xFFFFFFFF BRD Baud Rate Divider\nThe field indicates the baud rate divider. 0 16 read-write DIVIDER_X Divider X\n 24 4 read-write DIV_X_ONE Divider X Equal to 1\nRefer to the Table 515 below for more information. 28 1 0 Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) #0 1 Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 8) #1 read-write DIV_X_EN Divider X Enable\nRefer to the table below for more information.\nNote: In IrDA mode, this bit must be disabled. 29 1 0 Divider X Disabled (the equation of M = 16) #0 1 Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) #1 read-write UA_IRCR UA_IRCR UART IrDA Control Register 0x28 read-write 0x00000040 0xFFFFFFFF TX_SELECT TX_SELECT\n 1 1 0 Enable IrDA receiver #0 1 Enable IrDA transmitter #1 read-write INV_TX INV_TX\n 5 1 0 No inversion #0 1 Inverse TX output signal #1 read-write INV_RX INV_RX\n 6 1 0 No inversion #0 1 Inverse RX input signal #1 read-write UA_ALT_CSR UA_ALT_CSR UART Alternate Control/Status Register 0x2C read-write 0x00000000 0xFFFFFFFF RS485_NMM RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It can't be active with RS-485_AAD operation mode. 8 1 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 read-write RS485_AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode. 9 1 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 read-write RS485_AUD RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 0 RS-485 Auto Direction Operation mode (AUD) Disabled #0 1 RS-485 Auto Direction Operation mode (AUD) Enabled #1 read-write RS485_ADD_EN RS-485 Address Detection Enable \nThis bit is used to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode. 15 1 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 read-write ADDR_MATCH Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 Auto Address Detection mode. 24 8 read-write UA_FUN_SEL UA_FUN_SEL UART Function Select Register 0x30 read-write 0x00000000 0xFFFFFFFF FUN_SEL Function Selection Enable\n 0 2 0 UART Function #00 1 Reserved #01 2 IrDA Function Enabled #10 3 RS-485 Function Enabled #11 read-write UART1 UART Register Map UART 0x40150000 0x0 0x34 registers UA_RBR UA_RBR UART Receive Buffer Register 0x0 read-only 0x00000000 0x00000000 RBR Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first). 0 8 read-only UA_THR UA_RBR UA_THR UART Transmit Holding Register 0x0 write-only 0x00000000 0x00000000 THR Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first). 0 8 write-only UA_IER UA_IER UART Interrupt Enable Register 0x4 read-write 0x00000000 0xFFFFFFFF RDA_IEN Receive Data Available Interrupt Enable.\n 0 1 0 INT_RDA Masked off #0 1 INT_RDA Enabled #1 read-write THRE_IEN Transmit Holding Register Empty Interrupt Enable\n 1 1 0 INT_THRE Masked off #0 1 INT_THRE Enabled #1 read-write RLS_IEN Receive Line Status Interrupt Enable \n 2 1 0 INT_RLS Masked off #0 1 INT_RLS Enabled #1 read-write MODEM_IEN Modem Status Interrupt Enable\n 3 1 0 INT_MODEM Masked off #0 1 INT_MODEM Enabled #1 read-write RTO_IEN RX Time Out Interrupt Enable\n 4 1 0 INT_TOUT Masked off #0 1 INT_TOUT Enabled #1 read-write BUF_ERR_IEN Buffer Error Interrupt Enable\n 5 1 0 INT_BUF_ERR Masked off #0 1 INT_BUF_ERR Enabled #1 read-write WAKE_EN UART Wake-up Function Enable\n 6 1 0 UART wake-up function Disabled #0 1 UART wake-up function Enabled, when chip is in Power-down mode, an external CTS change will wake up chip from Power-down mode #1 read-write TIME_OUT_EN Time Out Counter Enable\n 11 1 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 read-write AUTO_RTS_EN RTS Auto Flow Control Enable\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO is equal to the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTS signal. 12 1 0 RTS auto flow control Disabled #0 1 RTS auto flow control Enabled #1 read-write AUTO_CTS_EN CTS Auto Flow Control Enable \nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). 13 1 0 CTS auto flow control Disabled #0 1 CTS auto flow control Enabled #1 read-write DMA_TX_EN TX DMA Enable\nThis bit can enable or disable TX DMA service.\n 14 1 0 TX DMA Disabled #0 1 TX DMA Enabled #1 read-write DMA_RX_EN RX DMA Enable\nThis bit can enable or disable RX DMA service.\n 15 1 0 RX DMA Disabled #0 1 RX DMA Enabled #1 read-write UA_FCR UA_FCR UART FIFO Control Register 0x8 read-write 0x00000101 0xFFFFFFFF RFR RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will be automatically cleared at least 3 UART engine clock cycles. 1 1 0 No effect #0 1 Reset the RX internal state machine and pointers #1 read-write TFR TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will be automatically cleared at least 3 UART engine clock cycles. 2 1 0 No effect #0 1 Reset the TX internal state machine and pointers #1 read-write RFITL RX FIFO Interrupt (INT_RDA) Trigger Level\n 4 4 read-write RX_DIS Receiver Disable Register\nThe receiver is enabled or disabled.\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed. 8 1 0 Receiver Enabled #0 1 Receiver Disabled #1 read-write RTS_TRI_LEV RTS Trigger Level for Auto-flow Control Use\n 16 4 read-write UA_LCR UA_LCR UART Line Control Register 0xC read-write 0x00000000 0xFFFFFFFF WLS Word Length Selection\n 0 2 read-write NSB Number of "STOP bit"\nTwo "STOP bit" are generated when 6-, 7- and 8-bit word length is selected. 2 1 0 One " STOP bit" is generated in the transmitted data #0 1 One and a half " STOP bit" is generated in the transmitted data when 5-bit word length is selected; #1 read-write PBE Parity Bit Enable\n 3 1 0 No parity bit #0 1 Parity bit is generated on each outgoing character and is checked on each incoming data #1 read-write EPE Even Parity Enable\nThis bit has effect only when bit 3 (parity bit enable) is set. 4 1 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 read-write SPE Stick Parity Enable\n 5 1 0 Stick parity Disabled #0 1 If bit 3 and 4 are logic 1, the parity bit is transmitted and cheched as logic 0. If bit 3 si 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1 #1 read-write BCB Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic. 6 1 read-write UA_MCR UA_MCR UART Modem Control Register 0x10 read-write 0x00000200 0xFFFFFFFF RTS RTS (Request-To-Send) Signal\n 1 1 0 Drive RTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 0 (If the LEV_RTS set to high level triggered) #0 1 Drive RTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 1 (If the LEV_RTS set to high level triggered) #1 read-write LEV_RTS RTS Trigger Level\nThis bit can change the RTS trigger level.\n 9 1 0 Low level triggered #0 1 High level triggered #1 read-write RTS_ST RTS Pin State (Read Only)\nThis bit is the output pin status of RTS. 13 1 read-only UA_MSR UA_MSR UART Modem Status Register 0x14 read-write 0x00000110 0xFFFFFFFF DCTSF Detect CTS State Change Flag (Read Only)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nSoftware can write 1 to clear this bit to zero. 0 1 read-only CTS_ST CTS Pin Status (Read Only)\nThis bit is the pin status of CTS. 4 1 read-only LEV_CTS CTS Trigger Level\nThis bit can change the CTS trigger level.\n 8 1 0 Low level triggered #0 1 High level triggered #1 read-write UA_FSR UA_FSR UART FIFO Status Register 0x18 read-write 0x10404000 0xFFFFFFFF RX_OVER_IF RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only RS485_ADD_DETF RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it. 3 1 read-only PEF Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it. 4 1 read-only FEF Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it. 5 1 read-only BIF Break Interrupt Flag (Read Only)\nThis bit is set to a logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it. 6 1 read-only RX_POINTER RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one. 8 6 read-only RX_EMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only RX_FULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RX_POINTER is equal to 64/16(UART0/UART1); otherwise, it is cleared by hardware. 15 1 read-only TX_POINTER TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one. 16 6 read-only TX_EMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). 22 1 read-only TX_FULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TX_POINTER is equal to 64/16(UART0/UART1); otherwise, it is cleared by hardware. 23 1 read-only TX_OVER_IF TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. \nNote: This bit is read only, but can be cleared by writing '1' to it. 24 1 read-only TE_FLAG Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only UA_ISR UA_ISR UART Interrupt Status Register 0x1C read-write 0x00000002 0xFFFFFFFF RDA_IF Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX FIFO is equal to the RFITL, the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL). 0 1 read-only THRE_IF Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). 1 1 read-only RLS_IF Receive Line Interrupt Flag (Read Only). \nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. 2 1 read-only MODEM_IF MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF. 3 1 read-only TOUT_IF Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. 4 1 read-only BUF_ERR_IF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared. 5 1 read-only RDA_INT Receive Data Available Interrupt Indicator (Read Only).\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n 8 1 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 read-only THRE_INT Transmit Holding Register Empty Interrupt Indicator (Read Only).\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n 9 1 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 read-only RLS_INT Receive Line Status Interrupt Indicator (Read Only). \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n 10 1 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 read-only MODEM_INT MODEM Status Interrupt Indicator (Read Only).\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n 11 1 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 read-only TOUT_INT Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.\n 12 1 0 No Tout interrupt is generated #0 1 Tout interrupt is generated #1 read-only BUF_ERR_INT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n 13 1 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 read-only HW_RLS_IF In DMA Mode, Receive Line Status Flag (Read Only) \nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared. 18 1 read-only HW_MODEM_IF In DMA Mode, MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF. 19 1 read-only HW_TOUT_IF In DMA Mode, Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. 20 1 read-only HW_BUF_ERR_IF In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared. 21 1 read-only HW_RLS_INT In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN and HW_RLS_IF are both set to 1.\n 26 1 0 No RLS interrupt is generated in DMA mode #0 1 RLS interrupt is generated in DMA mode #1 read-only HW_MODEM_INT In DMA Mode, MODEM Status Interrupt Indicator (Read Only) \nThis bit is set if MODEM_IEN and HW_MODEM_IF are both set to 1.\n 27 1 0 No Modem interrupt is generated in DMA mode #0 1 Modem interrupt is generated in DMA mode #1 read-only HW_TOUT_INT In DMA Mode, Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and HW_TOUT_IF are both set to 1.\n 28 1 0 No Tout interrupt is generated in DMA mode #0 1 Tout interrupt is generated in DMA mode #1 read-only HW_BUF_ERR_INT In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and HW_BUF_ERR_IF are both set to 1.\n 29 1 0 No buffer error interrupt is generated in DMA mode #0 1 Buffer error interrupt is generated in DMA mode #1 read-only UA_TOR UA_TOR UART Time Out Register 0x20 read-write 0x00000000 0xFFFFFFFF TOIC Time Out Interrupt Comparator\n 0 8 read-write DLY TX Delay time value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. 8 8 read-write UA_BAUD UA_BAUD UART Baud Rate Divisor Register 0x24 read-write 0x0F000000 0xFFFFFFFF BRD Baud Rate Divider\nThe field indicates the baud rate divider. 0 16 read-write DIVIDER_X Divider X\n 24 4 read-write DIV_X_ONE Divider X Equal to 1\nRefer to the Table 515 below for more information. 28 1 0 Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) #0 1 Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 8) #1 read-write DIV_X_EN Divider X Enable\nRefer to the table below for more information.\nNote: In IrDA mode, this bit must be disabled. 29 1 0 Divider X Disabled (the equation of M = 16) #0 1 Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) #1 read-write UA_IRCR UA_IRCR UART IrDA Control Register 0x28 read-write 0x00000040 0xFFFFFFFF TX_SELECT TX_SELECT\n 1 1 0 Enable IrDA receiver #0 1 Enable IrDA transmitter #1 read-write INV_TX INV_TX\n 5 1 0 No inversion #0 1 Inverse TX output signal #1 read-write INV_RX INV_RX\n 6 1 0 No inversion #0 1 Inverse RX input signal #1 read-write UA_ALT_CSR UA_ALT_CSR UART Alternate Control/Status Register 0x2C read-write 0x00000000 0xFFFFFFFF RS485_NMM RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It can't be active with RS-485_AAD operation mode. 8 1 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 read-write RS485_AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode. 9 1 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 read-write RS485_AUD RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 0 RS-485 Auto Direction Operation mode (AUD) Disabled #0 1 RS-485 Auto Direction Operation mode (AUD) Enabled #1 read-write RS485_ADD_EN RS-485 Address Detection Enable \nThis bit is used to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode. 15 1 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 read-write ADDR_MATCH Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 Auto Address Detection mode. 24 8 read-write UA_FUN_SEL UA_FUN_SEL UART Function Select Register 0x30 read-write 0x00000000 0xFFFFFFFF FUN_SEL Function Selection Enable\n 0 2 0 UART Function #00 1 Reserved #01 2 IrDA Function Enabled #10 3 RS-485 Function Enabled #11 read-write PS2 PS2 Register Map PS2 0x40100000 0x0 0x20 registers PS2CON PS2CON PS/2 Control Register 0x0 read-write 0x00000000 0xFFFFFFFF PS2EN Enable PS/2 Device\nEnable PS/2 device controller.\n 0 1 0 Disabled #0 1 Enabled #1 read-write TXINTEN Enable Transmit Interrupt\n 1 1 0 Data transmit complete interrupt Disabled #0 1 Data transmit complete interrupt Enabled #1 read-write RXINTEN Enable Receive Interrupt\n 2 1 0 Data receive complete interrupt Disabled #0 1 Data receive complete interrupt Enabled #1 read-write TXFIFODIPTH Transmit Data FIFO Depth\nThere is 16-byte buffer for data transmit. Software can define the FIFO depth from 1 to 16 bytes depending on the application.\n 3 4 0 1 byte 0 1 2 bytes 1 14 15 bytes 14 15 16 bytes 15 read-write ACK Acknowledge Enable\n 7 1 0 Always sends acknowledge to host at 12th clock for host to device communication #0 1 If parity error or stop bit is not received correctly, acknowledge bit will not be sent to host at 12th clock #1 read-write CLRFIFO Clear TX FIFO\nWrite 1 to this bit to terminate device to host transmission. The TXEMPTY bit in PS2STATUS bit will be set to 1 and pointer BYTEIDEX is reset to 0 regardless there is residue data in buffer or not. The buffer content is not been cleared.\n 8 1 0 Not active #0 1 Clear FIFO #1 read-write OVERRIDE Software Override PS/2 CLK/DATA Pin State\n 9 1 0 PS2CLK and PS2DATA pins are controlled by internal state machine #0 1 PS2CLK and PS2DATA pins are controlled by software #1 read-write FPS2CLK Force PS2CLK Line\nIt forces PS2CLK line high or low regardless of the internal state of the device controller if OVERRIDE is set to high.\n 10 1 0 Force PS2CLK line low #0 1 Force PS2CLK line high #1 read-write FPS2DAT Force PS2DATA Line\nIt forces PS2DATA high or low regardless of the internal state of the device controller if OVERRIDE is set to high.\n 11 1 0 Force PS2DATA low #0 1 Force PS2DATA high #1 read-write PS2TXDATA0 PS2TXDATA0 PS/2 Transmit Data Register 0 0x4 read-write 0x00000000 0xFFFFFFFF PS2TXDATAx Transmit data\nWrite data to this register starts device to host communication if bus is in IDLE state. Software must enable PS2EN before writing data to TX buffer. 0 32 read-write PS2TXDATA1 PS2TXDATA1 PS/2 Transmit Data Register 1 0x8 PS2TXDATA2 PS2TXDATA2 PS/2 Transmit Data Register 2 0xC PS2TXDATA3 PS2TXDATA3 PS/2 Transmit Data Register 3 0x10 PS2RXDATA PS2RXDATA PS/2 Receive Data Register 0x14 read-only 0x00000000 0xFFFFFFFF PS2RXDATA Received Data\nFor host to device communication, after acknowledge bit is sent, the received data is copied from receive shift register to PS2RXDATA register. CPU must read this register before next byte reception complete; otherwise, the data will be overwritten and RXOVF bit in PS2STATUS[6] will be set to 1. 0 8 read-only PS2STATUS PS2STATUS PS/2 Status Register 0x18 read-write 0x00000083 0xFFFFFFFF PS2CLK CLK Pin State\nThis bit reflects the status of the PS2CLK line after synchronizing. 0 1 read-write PS2DATA DATA Pin State\nThis bit reflects the status of the PS2DATA line after synchronizing and sampling. 1 1 read-write FRAMERR Frame Error\nFor host to device communication, if STOP bit (logic 1) is not received it is a frame error. If frame error occurs, DATA line may keep at low state after 12th clock. At this moment, software overrides PS2CLK to send clock till PS2DATA release to high state. After that, device sends a "Resend" command to host.\nWrite 1 to clear this bit. 2 1 0 No frame error #0 1 Frame error occurred #1 read-write RXPARITY Received Parity\nThis bit reflects the parity bit for the last received data byte (odd parity).\nRead only bit. 3 1 read-write RXBUSY Receive Busy\nThis bit indicates that the PS/2 device is currently receiving data.\nRead only bit. 4 1 0 Idle #0 1 Currently receiving data #1 read-write TXBUSY Transmit Busy\nThis bit indicates that the PS/2 device is currently sending data.\nRead only bit. 5 1 0 Idle #0 1 Currently sending data #1 read-write RXOVF RX Buffer Overwrite\nWrite 1 to clear this bit. 6 1 0 No overwrite #0 1 Data in PS2RXDATA register is overwritten by new received data #1 read-write TXEMPTY TX FIFO Empty\nWhen software writes any data to PS2TXDATA0-3 the TXEMPTY bit is cleared to 0 immediately if PS2EN is enabled. When transmitted data byte number is equal to FIFODEPTH then TXEMPTY bit is set to 1.\nRead only bit. 7 1 0 There is data to be transmitted #0 1 FIFO is empty #1 read-write BYTEIDX Byte Index\n 8 4 read-write PS2INTID PS2INTID PS/2 Interrupt Identification Register 0x1C read-write 0x00000000 0xFFFFFFFF RXINT Receive Interrupt\nThis bit is set to 1 when acknowledge bit is sent for Host to device communication. Interrupt occurs if RXINTEN bit is set to 1.\nWrite 1 to clear this bit to 0. 0 1 0 No interrupt #0 1 Receive interrupt occurs #1 read-write TXINT Transmit Interrupt\nThis bit is set to 1 after STOP bit is transmitted. Interrupt occurs if TXINTEN bit is set to 1.\nWrite 1 to clear this bit to 0. 1 1 0 No interrupt #0 1 Transmit interrupt occurs #1 read-write I2S I2S Register Map I2S 0x401A0000 0x0 0x18 registers I2S_CON I2S_CON I2S Control Register 0x0 read-write 0x00000000 0xFFFFFFFF I2SEN I2S Controller Enable\n 0 1 0 Disabled #0 1 Enabled #1 read-write TXEN Transmit enable\n 1 1 0 Data transmission Disabled #0 1 Data transmission Enabled #1 read-write RXEN Receive enable\n 2 1 0 Data receiving Disabled #0 1 Data receiving Enabled #1 read-write MUTE Transmit Mute Enable\n 3 1 0 Transmit data is shifted from buffer #0 1 Transmit channel zero #1 read-write WORDWIDTH Word Width\n 4 2 0 Data is 8-bit #00 1 Data is 16-bit #01 2 Data is 24-bit #10 3 Data is 32-bit #11 read-write MONO Monaural Data\n 6 1 0 Data is stereo format #0 1 Data is monaural format #1 read-write FORMAT Data format Selection\n 7 1 0 I2S data format\nPCM mode A #0 1 MSB justified data format\nPCM mode B #1 read-write SLAVE Slave mode\nI2S can be operated as Master or Slave mode. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro( NUC123 series to Audio CODEC chip. In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.\n 8 1 0 Master mode #0 1 Slave mode #1 read-write TXTH Transmit FIFO threshold level\nIf remain data word (32 bits) in transmit FIFO is the same or less than threshold level, the TXTHF flag is set.\n 9 3 0 0 word data in transmit FIFO #000 1 1 word data in transmit FIFO #001 2 2 words data in transmit FIFO #010 3 3 words data in transmit FIFO #011 4 4 words data in transmit FIFO #100 5 5 words data in transmit FIFO #101 6 6 words data in transmit FIFO #110 7 7 words data in transmit FIFO #111 read-write RXTH Receive FIFO threshold level\nWhen received data word(s) in buffer is equal to or higher than threshold level, the RXTHF flag is set.\n 12 3 0 1 word data in receive FIFO #000 1 2 word data in receive FIFO #001 2 3 word data in receive FIFO #010 3 4 word data in receive FIFO #011 4 5 word data in receive FIFO #100 5 6 word data in receive FIFO #101 6 7 word data in receive FIFO #110 7 8 word data in receive FIFO #111 read-write MCLKEN Master clock enable\nFor NuMicro( NUC123 series, if the external crystal clock is frequency 2*N*256fs, software can program MCLK_DIV[2:0] in I2S_CLKDIV register to get 256fs clock to audio codec chip.\n 15 1 0 Master clock Disabled #0 1 Master clock Enabled #1 read-write RCHZCEN Right Channel Zero-cross Detect Enable\nIf this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCF flag in I2S_STATUS register is set to 1.\n 16 1 0 Right channel zero-cross detect Disabled #0 1 Right channel zero-cross detect Enabled #1 read-write LCHZCEN Left Channel Zero Cross Detect Enable\nIf this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCF flag in I2S_STATUS register is set to 1.\n 17 1 0 Left channel zero-cross detect Disabled #0 1 Left channel zero-cross detect Enabled #1 read-write CLR_TXFIFO Clear Transmit FIFO\nWrite 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXFIFO_LEVEL[3:0] returns to zero and transmit FIFO becomes empty but data in transmit FIFO is not changed. \nThis bit is cleared by hardware automatically, reading it returns zero. 18 1 read-write CLR_RXFIFO Clear Receive FIFO\nWrite 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXFIFO_LEVEL[3:0] returns to zero and receive FIFO becomes empty.\nThis bit is cleared by hardware automatically, reading it returns zero. 19 1 read-write TXDMA Enable Transmit DMA\nWhen TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.\n 20 1 0 TX DMA Disabled #0 1 TX DMA Enabled #1 read-write RXDMA Enable Receive DMA\nWhen RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.\n 21 1 0 RX DMA Disabled #0 1 RX DMA Enabled #1 read-write RXLCH Receive Left Channel Enable\n 23 1 0 Receives right channel data when monaural format is selected #0 1 Receives left channel data when monaural format is selected #1 read-write PCM PCM Interface Enable\n 24 1 0 I2S Interface #0 1 PCM interface #1 read-write I2S_CLKDIV I2S_CLKDIV I2S Clock Divider Register 0x4 read-write 0x00000000 0xFFFFFFFF MCLK_DIV Master Clock Divider\nIf chip external crystal frequency is (2xMCLK_DIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. If MCLK_DIV is set to 0, MCLK is the same as external clock input.\n 0 3 read-write BCLK_DIV Bit Clock Divider\nIf I2S operates in Master mode, bit clock is provided by NuMicro( NUC123 series. Software can program these bits to generate sampling rate clock frequency.\n 8 8 read-write I2S_IE I2S_IE I2S Interrupt Enable Register 0x8 read-write 0x00000000 0xFFFFFFFF RXUDFIE Receive FIFO Underflow Interrupt Enable\nIf software reads the received FIFO when it is empty, RXUDF flag in I2SSTATUS register is set to 1.\n 0 1 0 Interrupt Disabled #0 1 Interrupt Enabled #1 read-write RXOVFIE Receive FIFO Overflow Interrupt Enable\n 1 1 0 Interrupt Disabled #0 1 Interrupt Enabled #1 read-write RXTHIE Received FIFO Threshold Level Interrupt Enable\nWhen data word in receive FIFO is equal to or higher then RXTH[2:0] and the RXTHF bit is set to 1. If RXTHIE bit is enabled, interrupt occurs.\n 2 1 0 Interrupt Disabled #0 1 Interrupt Enabled #1 read-write TXUDFIE Transmitted FIFO Underflow Interrupt Enable\nInterrupt occurs if this bit is set to 1 and transmitted FIFO underflow flag is set to 1.\n 8 1 0 Interrupt Disabled #0 1 Interrupt Enabled #1 read-write TXOVFIE Transmitted FIFO Overflow Interrupt Enable\nInterrupt occurs if this bit is set to 1 and transmitted FIFO overflow flag is set to 1.\n 9 1 0 Interrupt Disabled #0 1 Interrupt Enabled #1 read-write TXTHIE Transmitted FIFO Threshold Level Interrupt Enable\nInterrupt occurs if this bit is set to 1 and data words in transmit FIFO are less than TXTH[2:0].\n 10 1 0 Interrupt Disabled #0 1 Interrupt Enabled #1 read-write RZCIE Right Channel Zero-cross Interrupt Enable\n 11 1 0 Interrupt Disabled #0 1 Interrupt Enabled #1 read-write LZCIE Left Channel Zero-cross Interrupt Enable\nInterrupt occurs if this bit is set to 1 and left channel zero-cross.\n 12 1 0 Interrupt Disabled #0 1 Interrupt Enabled #1 read-write I2S_STATUS I2S_STATUS I2S Status Register 0xC read-write 0x00141000 0xFFFFFFFF I2SINT I2S Interrupt Flag\nIt is wire-OR of I2STXINT and I2SRXINT bits.\nThis bit is read only. 0 1 0 No I2S interrupt #0 1 I2S interrupt #1 read-write I2SRXINT I2S Receive Interrupt\nThis bit is read only. 1 1 0 No receive interrupt #0 1 Receive interrupt #1 read-write I2STXINT I2S Transmit Interrupt\nThis bit is read only. 2 1 0 No transmit interrupt #0 1 Transmit interrupt #1 read-write RIGHT Right Channel\nThis bit indicates the current transmit data is belong to right channel.\nThis bit is read only. 3 1 0 Left channel #0 1 Right channel #1 read-write RXUDF Receive FIFO Underflow Flag\nRead receive FIFO when it is empty, this bit set to 1 indicate underflow occur.\nSoftware can write 1 to clear this bit to zero. 8 1 0 No underflow occurred #0 1 Underflow occurred #1 read-write RXOVF Receive FIFO Overflow Flag\nWhen receive FIFO is full and receive hardware attempt write to data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.\nSoftware can write 1 to clear this bit to zero. 9 1 0 No overflow occurred #0 1 Overflow occurred #1 read-write RXTHF Receive FIFO Threshold Flag\nWhen data word(s) in receive FIFO is equal or higher than threshold value set in RXTH[2:0] the RXTHF bit becomes to 1. It keeps at 1 till RXFIFO_LEVEL[3:0] less than RXTH[1:0] after software read RXFIFO register.\nThis bit is read only. 10 1 0 Data word(s) in FIFO is lower than threshold level #0 1 Data word(s) in FIFO is equal or higher than threshold level #1 read-write RXFULL Receive FIFO Full\nThis bit reflect data words number in receive FIFO is 8.\nThis bit is read only. 11 1 0 Not full #0 1 Full #1 read-write RXEMPTY Receive FIFO Empty\nThis bit reflects data words number in receive FIFO is zero.\nThis bit is read only. 12 1 0 Not empty #0 1 Empty #1 read-write TXUDF Transmit FIFO underflow flag\nWhen transmit FIFO is empty and shift logic hardware read data from data FIFO causes this set to 1.\nSoftware can write 1 to clear this bit to zero 16 1 0 No underflow #0 1 Underflow #1 read-write TXOVF Transmit FIFO Overflow Flag\nWrite data to transmit FIFO when it is full and this bit set to 1.\nSoftware can write 1 to clear this bit to zero. 17 1 0 No overflow #0 1 Overflow #1 read-write TXTHF Transmit FIFO Threshold Flag\nWhen data word(s) in transmit FIFO is equal to or lower than threshold value set in TXTH[2:0] the TXTHF bit becomes to 1. It keeps at 1 till TXFIFO_LEVEL[3:0] is higher than TXTH[1:0] after software write TXFIFO register.\nThis bit is read only. 18 1 0 Data word(s) in FIFO is higher than threshold level #0 1 Data word(s) in FIFO is equal or lower than threshold level #1 read-write TXFULL Transmit FIFO Full\nThis bit reflect data word number in transmit FIFO is 8.\nThis bit is read only 19 1 0 Not full #0 1 Full #1 read-write TXEMPTY Transmit FIFO Empty\nThis bit reflect data word number in transmit FIFO is zero.\nThis bit is read only. 20 1 0 Not empty #0 1 Empty #1 read-write TXBUSY Transmit Busy\nThis bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out, and set to 1 when the 1st data is load to shift buffer. \nThis bit is read only. 21 1 0 Transmit shift buffer is empty #0 1 Transmit shift buffer is busy #1 read-write RZCF Right Channel Zero-cross Flag\nIt indicates right channel next sample data sign bit is changed or all data bits are zero.\nSoftware can write 1 to clear this bit to zero. 22 1 0 No zero-cross #0 1 Right channel zero-cross is detected #1 read-write LZCF Left Channel Zero-cross Flag\nIt indicates left channel next the sample data sign bit is changed or all data bits are zero.\nSoftware can write 1 to clear this bit to zero 23 1 0 No zero-cross #0 1 Left channel zero-cross is detected #1 read-write RX_LEVEL Receive FIFO Level\nThese bits indicate word number in receive FIFO.\n 24 4 0 No data #0000 1 1 word in receive FIFO #0001 8 8 words in receive FIFO #1000 read-write TX_LEVEL Transmit FIFO Level\nThese bits indicate word number in transmit FIFO.\n 28 4 0 No data #0000 1 1 word in transmit FIFO #0001 8 8 words in transmit FIFO #1000 read-write I2S_TXFIFO I2S_TXFIFO I2S Transmit FIFO Register 0x10 read-write 0x00000000 0xFFFFFFFF TXFIFO Transmit FIFO register\nI2S contains 8 words (8x32 bit) data buffer for data transmission. Write data to this register to prepare data for transmit. The remaining word number is indicated by TX_LEVEL[3:0] in I2S_STATUS. 0 32 read-write I2S_RXFIFO I2S_RXFIFO I2S Receive FIFO Register 0x14 read-write 0x00000000 0xFFFFFFFF RXFIFO Receive FIFO register\nI2S contains 8 words (8x32 bit) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RX_LEVEL[3:0] in I2S_STATUS register. 0 32 read-write ADC ADC Register Map ADC 0x400E0000 0x0 0x34 registers 0x40 0x4 registers ADDR0 ADDR0 A/D Data Register 0 0x0 read-only 0x00000000 0xFFFFFFFF RSLT A/D Conversion Result\nThis field contains 10 bits conversion result of ADC. 0 16 read-only OVERRUN Over Run Flag\nIf converted data in RSLT[15:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read.\nThis is a read only bit. 16 1 0 Data in RSLT[15:0] is recent conversion result #0 1 Data in RSLT[15:0] is overwritten #1 read-only VALID Valid Flag\nThis bit is set to 1 when the corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit. 17 1 0 Data in RSLT[15:0] bits is not valid #0 1 Data in RSLT[15:0] bits is valid #1 read-only ADDR1 ADDR1 A/D Data Register 1 0x4 ADDR2 ADDR2 A/D Data Register 2 0x8 ADDR3 ADDR3 A/D Data Register 3 0xC ADDR4 ADDR4 A/D Data Register 4 0x10 ADDR5 ADDR5 A/D Data Register 5 0x14 ADDR6 ADDR6 A/D Data Register 6 0x18 ADDR7 ADDR7 A/D Data Register 7 0x1C ADCR ADCR A/D Control Register 0x20 read-write 0x00000000 0xFFFFFFFF ADEN A/D Converter Enable\nBefore starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit for saving power consumption. 0 1 0 Disabled #0 1 Enabled #1 read-write ADIE A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1. 1 1 0 A/D interrupt function Disabled #0 1 A/D interrupt function Enabled #1 read-write ADMD A/D Converter Operation Mode\nWhen changing the operation mode, software should disable ADST bit firstly. 2 2 0 Single conversion #00 1 Reserved #01 2 Single-cycle scan #10 3 Continuous scan #11 read-write TRGS Hardware Trigger Source\nSoftware should disable TRGEN and ADST before change TRGS.\nIn hardware trigger mode, the ADST bit is set by the external trigger from STADC. 4 2 0 A/D conversion is started by external STADC pin.\nA/D conversion is started by PWM center-aligned trigger #00 read-write TRGCOND External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.\n 6 2 0 Low level #00 1 High level #01 2 Falling edge #10 3 Rising edge #11 read-write TRGEN External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin.\nADC external trigger function is only supported in Single-cycle Scan mode. 8 1 0 Disabled #0 1 Enabled #1 read-write PTEN PDMA Transfer Enable\n 9 1 0 PDMA data transfer Disabled #0 1 PDMA data transfer in ADDR 0~7 Enabled #1 read-write ADST A/D Conversion Start\nADST bit can be set to 1 from three sources: software and external pin STADC, and pwm output. ADST will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan mode, A/D conversion is continuously performed until software write 0 to this bit or chip reset. 11 1 0 Conversion stopped and A/D converter entering Idle state #0 1 Conversion started #1 read-write ADCHER ADCHER A/D Channel Enable Register 0x24 read-write 0x00000000 0xFFFFFFFF CHEN0 Analog Input Channel 0 Enable\n 0 1 0 Disabled #0 1 Enabled #1 read-write CHEN1 Analog Input Channel 1 Enable\n 1 1 0 Disabled #0 1 Enabled #1 read-write CHEN2 Analog Input Channel 2 Enable\n 2 1 0 Disabled #0 1 Enabled #1 read-write CHEN3 Analog Input Channel 3 Enable\n 3 1 0 Disabled #0 1 Enabled #1 read-write CHEN4 Analog Input Channel 4 Enable\n 4 1 0 Disabled #0 1 Enabled #1 read-write CHEN5 Analog Input Channel 5 Enable\n 5 1 0 Disabled #0 1 Enabled #1 read-write CHEN6 Analog Input Channel 6 Enable\n 6 1 0 Disabled #0 1 Enabled #1 read-write CHEN7 Analog Input Channel 7 Enable\n 7 1 0 Disabled #0 1 Enabled #1 read-write PRESEL Analog Input Channel 7 Selection\nNote: When software selects the band-gap voltage as the analog input source of ADC channel 7, ADC clock rate needs to be limited to lower than 300 kHz. 8 1 0 External analog input #0 1 Internal band-gap voltage #1 read-write ADCMPR0 ADCMPR0 A/D Compare Register 0 0x28 read-write 0x00000000 0xFFFFFFFF CMPEN Compare Enable\nSet this bit to 1 to enable ADC controller to compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register. 0 1 0 Compare function Disabled #0 1 Compare function Enabled #1 read-write CMPIE Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated. 1 1 0 Compare function interrupt Disabled #0 1 Compare function interrupt Enabled #1 read-write CMPCOND Compare Conditions\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set. 2 1 0 Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one #0 1 Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one #1 read-write CMPCH Compare Channel Selection\n 3 3 0 Channel 0 conversion result is selected to be compared #000 1 Channel 1 conversion result is selected to be compared #001 2 Channel 2 conversion result is selected to be compared #010 3 Channel 3 conversion result is selected to be compared #011 4 Channel 4 conversion result is selected to be compared #100 5 Channel 5 conversion result is selected to be compared #101 6 Channel 6 conversion result is selected to be compared #110 7 Channel 7 conversion result is selected to be compared #111 read-write CMPMATCNT Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set. 8 4 read-write CMPD Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nWhen DMOF bit is set to 0, ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned format.\nWhen DMOF bit is set to 1, ADC comparator compares CMPD with conversion result with 2'complement format. CMPD should be filled in 2'complement format. 16 12 read-write ADCMPR1 ADCMPR1 A/D Compare Register 1 0x2C ADSR ADSR A/D Status Register 0x30 read-write 0x00000000 0xFFFFFFFF ADF A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these two conditions:\n1. When A/D conversion ends in Single mode.\n2. When A/D conversion ends on all specified channels in Scan mode.\nThis flag can be cleared by writing 1 to itself. 0 1 read-write CMPF0 Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to itself.\n 1 1 0 Conversion result in ADDR does not meet ADCMPR0 setting #0 1 Conversion result in ADDR meets ADCMPR0 setting #1 read-write CMPF1 Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. It is cleared by writing 1 to itself.\n 2 1 0 Conversion result in ADDR does not meet ADCMPR1 setting #0 1 Conversion result in ADDR meets ADCMPR1 setting #1 read-write BUSY BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR.\nIt is read only. 3 1 0 A/D converter is in Idle state #0 1 A/D converter is busy at conversion #1 read-write CHANNEL Current Conversion Channel\nIt is read only. 4 3 read-write VALID Data Valid flag\nIt is a mirror of VALID bit in ADDRx.\nIt is read only. 8 8 read-write OVERRUN Over Run Flag\nIt is a mirror to OVERRUN bit in ADDRx.\nIt is read only. 16 8 read-write ADPDMA ADPDMA ADC PDMA current transfer data 0x40 read-only 0x00000000 0xFFFFFFFF AD_PDMA ADC PDMA current transfer data register\nWhen PDMA transferring, read this register can monitor current PDMA transfer data.\nThis is a read only register. 0 10 read-only PDMA_ch0 PDMA Register Map PDMA 0x50008000 0x0 0x28 registers 0x80 0x4 registers PDMA_CSRx PDMA_CSRx PDMA Control Register 0x0 read-write 0x00000000 0xFFFFFFFF PDMACEN PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write SW_RST Software Engine Reset\n 1 1 0 No effect #0 1 Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles #1 read-write MODE_SEL PDMA Mode Selection\n 2 2 0 Memory to Memory mode (Memory-to-Memory) #00 1 Peripheral to Memory mode (Peripheral-to-Memory) #01 2 Memory to Peripheral mode (Memory-to-Peripheral) #10 read-write SAD_SEL Transfer Source Address Direction Selection\n 4 2 0 Transfer source address is increasing successively #00 1 Reserved #01 2 Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) #10 3 Reserved #11 read-write DAD_SEL Transfer Destination Address Direction Selection\n 6 2 0 Transfer destination address is increasing successively #00 1 Reserved #01 2 Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination) #10 3 Reserved #11 read-write APB_TWS Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). 19 2 0 One word (32-bit) is transferred for every PDMA operation #00 1 One byte (8-bit) is transferred for every PDMA operation #01 2 One half-word (16-bit) is transferred for every PDMA operation #10 3 Reserved #11 read-write TRIG_EN TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again. 23 1 0 No effect #0 1 PDMA data read or write transfer Enabled #1 read-write PDMA_SARx PDMA_SARx PDMA Source Address Register 0x4 read-write 0x00000000 0xFFFFFFFF PDMA_SAR PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. 0 32 read-write PDMA_DARx PDMA_DARx PDMA Destination Address Register 0x8 read-write 0x00000000 0xFFFFFFFF PDMA_DAR PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment. 0 32 read-write PDMA_BCRx PDMA_BCRx PDMA Transfer Byte Count Register 0xC read-write 0x00000000 0xFFFFFFFF PDMA_BCR PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment. 0 16 read-write PDMA_POINTx PDMA_POINTx PDMA Internal buffer pointer 0x10 read-only 0x00000000 0x0000FFFF PDMA_POINT PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer. 0 2 read-only PDMA_CSARx PDMA_CSARx PDMA Current Source Address Register 0x14 read-only 0x00000000 0xFFFFFFFF PDMA_CSAR PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs. 0 32 read-only PDMA_CDARx PDMA_CDARx PDMA Current Destination Address Register 0x18 read-only 0x00000000 0xFFFFFFFF PDMA_CDAR PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs. 0 32 read-only PDMA_CBCRx PDMA_CBCRx PDMA Current Transfer Byte Count Register 0x1C read-only 0x00000000 0xFFFFFFFF PDMA_CBCR PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value. 0 16 read-only PDMA_IERx PDMA_IERx PDMA Interrupt Enable Register 0x20 read-write 0x00000001 0xFFFFFFFF TABORT_IE PDMA Read/Write Target Abort Interrupt Enable\n 0 1 0 Target abort interrupt generation Disabled during PDMA transfer #0 1 Target abort interrupt generation Enabled during PDMA transfer #1 read-write BLKD_IE PDMA Transfer Done Interrupt Enable\n 1 1 0 Interrupt generator Disabled when PDMA transfer is done #0 1 Interrupt generator Enabled when PDMA transfer is done #1 read-write PDMA_ISRx PDMA_ISRx PDMA Interrupt Status Register 0x24 read-write 0x00000000 0xFFFFFFFF TABORT_IF PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. 0 1 0 No bus ERROR response received #0 1 Bus ERROR response received #1 read-write BLKD_IF Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. 1 1 0 Not finished #0 1 Done #1 read-write PDMA_SBUF_cx PDMA_SBUF_cx PDMA Shared Buffer FIFO 0x80 read-only 0x00000000 0xFFFFFFFF PDMA_SBUF PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. 0 32 read-only PDMA_ch1 PDMA Register Map PDMA 0x50008100 0x0 0x28 registers 0x80 0x4 registers PDMA_CSRx PDMA_CSRx PDMA Control Register 0x0 read-write 0x00000000 0xFFFFFFFF PDMACEN PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write SW_RST Software Engine Reset\n 1 1 0 No effect #0 1 Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles #1 read-write MODE_SEL PDMA Mode Selection\n 2 2 0 Memory to Memory mode (Memory-to-Memory) #00 1 Peripheral to Memory mode (Peripheral-to-Memory) #01 2 Memory to Peripheral mode (Memory-to-Peripheral) #10 read-write SAD_SEL Transfer Source Address Direction Selection\n 4 2 0 Transfer source address is increasing successively #00 1 Reserved #01 2 Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) #10 3 Reserved #11 read-write DAD_SEL Transfer Destination Address Direction Selection\n 6 2 0 Transfer destination address is increasing successively #00 1 Reserved #01 2 Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination) #10 3 Reserved #11 read-write APB_TWS Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). 19 2 0 One word (32-bit) is transferred for every PDMA operation #00 1 One byte (8-bit) is transferred for every PDMA operation #01 2 One half-word (16-bit) is transferred for every PDMA operation #10 3 Reserved #11 read-write TRIG_EN TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again. 23 1 0 No effect #0 1 PDMA data read or write transfer Enabled #1 read-write PDMA_SARx PDMA_SARx PDMA Source Address Register 0x4 read-write 0x00000000 0xFFFFFFFF PDMA_SAR PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. 0 32 read-write PDMA_DARx PDMA_DARx PDMA Destination Address Register 0x8 read-write 0x00000000 0xFFFFFFFF PDMA_DAR PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment. 0 32 read-write PDMA_BCRx PDMA_BCRx PDMA Transfer Byte Count Register 0xC read-write 0x00000000 0xFFFFFFFF PDMA_BCR PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment. 0 16 read-write PDMA_POINTx PDMA_POINTx PDMA Internal buffer pointer 0x10 read-only 0x00000000 0x0000FFFF PDMA_POINT PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer. 0 2 read-only PDMA_CSARx PDMA_CSARx PDMA Current Source Address Register 0x14 read-only 0x00000000 0xFFFFFFFF PDMA_CSAR PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs. 0 32 read-only PDMA_CDARx PDMA_CDARx PDMA Current Destination Address Register 0x18 read-only 0x00000000 0xFFFFFFFF PDMA_CDAR PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs. 0 32 read-only PDMA_CBCRx PDMA_CBCRx PDMA Current Transfer Byte Count Register 0x1C read-only 0x00000000 0xFFFFFFFF PDMA_CBCR PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value. 0 16 read-only PDMA_IERx PDMA_IERx PDMA Interrupt Enable Register 0x20 read-write 0x00000001 0xFFFFFFFF TABORT_IE PDMA Read/Write Target Abort Interrupt Enable\n 0 1 0 Target abort interrupt generation Disabled during PDMA transfer #0 1 Target abort interrupt generation Enabled during PDMA transfer #1 read-write BLKD_IE PDMA Transfer Done Interrupt Enable\n 1 1 0 Interrupt generator Disabled when PDMA transfer is done #0 1 Interrupt generator Enabled when PDMA transfer is done #1 read-write PDMA_ISRx PDMA_ISRx PDMA Interrupt Status Register 0x24 read-write 0x00000000 0xFFFFFFFF TABORT_IF PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. 0 1 0 No bus ERROR response received #0 1 Bus ERROR response received #1 read-write BLKD_IF Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. 1 1 0 Not finished #0 1 Done #1 read-write PDMA_SBUF_cx PDMA_SBUF_cx PDMA Shared Buffer FIFO 0x80 read-only 0x00000000 0xFFFFFFFF PDMA_SBUF PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. 0 32 read-only PDMA_ch2 PDMA Register Map PDMA 0x50008200 0x0 0x28 registers 0x80 0x4 registers PDMA_CSRx PDMA_CSRx PDMA Control Register 0x0 read-write 0x00000000 0xFFFFFFFF PDMACEN PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write SW_RST Software Engine Reset\n 1 1 0 No effect #0 1 Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles #1 read-write MODE_SEL PDMA Mode Selection\n 2 2 0 Memory to Memory mode (Memory-to-Memory) #00 1 Peripheral to Memory mode (Peripheral-to-Memory) #01 2 Memory to Peripheral mode (Memory-to-Peripheral) #10 read-write SAD_SEL Transfer Source Address Direction Selection\n 4 2 0 Transfer source address is increasing successively #00 1 Reserved #01 2 Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) #10 3 Reserved #11 read-write DAD_SEL Transfer Destination Address Direction Selection\n 6 2 0 Transfer destination address is increasing successively #00 1 Reserved #01 2 Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination) #10 3 Reserved #11 read-write APB_TWS Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). 19 2 0 One word (32-bit) is transferred for every PDMA operation #00 1 One byte (8-bit) is transferred for every PDMA operation #01 2 One half-word (16-bit) is transferred for every PDMA operation #10 3 Reserved #11 read-write TRIG_EN TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again. 23 1 0 No effect #0 1 PDMA data read or write transfer Enabled #1 read-write PDMA_SARx PDMA_SARx PDMA Source Address Register 0x4 read-write 0x00000000 0xFFFFFFFF PDMA_SAR PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. 0 32 read-write PDMA_DARx PDMA_DARx PDMA Destination Address Register 0x8 read-write 0x00000000 0xFFFFFFFF PDMA_DAR PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment. 0 32 read-write PDMA_BCRx PDMA_BCRx PDMA Transfer Byte Count Register 0xC read-write 0x00000000 0xFFFFFFFF PDMA_BCR PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment. 0 16 read-write PDMA_POINTx PDMA_POINTx PDMA Internal buffer pointer 0x10 read-only 0x00000000 0x0000FFFF PDMA_POINT PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer. 0 2 read-only PDMA_CSARx PDMA_CSARx PDMA Current Source Address Register 0x14 read-only 0x00000000 0xFFFFFFFF PDMA_CSAR PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs. 0 32 read-only PDMA_CDARx PDMA_CDARx PDMA Current Destination Address Register 0x18 read-only 0x00000000 0xFFFFFFFF PDMA_CDAR PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs. 0 32 read-only PDMA_CBCRx PDMA_CBCRx PDMA Current Transfer Byte Count Register 0x1C read-only 0x00000000 0xFFFFFFFF PDMA_CBCR PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value. 0 16 read-only PDMA_IERx PDMA_IERx PDMA Interrupt Enable Register 0x20 read-write 0x00000001 0xFFFFFFFF TABORT_IE PDMA Read/Write Target Abort Interrupt Enable\n 0 1 0 Target abort interrupt generation Disabled during PDMA transfer #0 1 Target abort interrupt generation Enabled during PDMA transfer #1 read-write BLKD_IE PDMA Transfer Done Interrupt Enable\n 1 1 0 Interrupt generator Disabled when PDMA transfer is done #0 1 Interrupt generator Enabled when PDMA transfer is done #1 read-write PDMA_ISRx PDMA_ISRx PDMA Interrupt Status Register 0x24 read-write 0x00000000 0xFFFFFFFF TABORT_IF PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. 0 1 0 No bus ERROR response received #0 1 Bus ERROR response received #1 read-write BLKD_IF Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. 1 1 0 Not finished #0 1 Done #1 read-write PDMA_SBUF_cx PDMA_SBUF_cx PDMA Shared Buffer FIFO 0x80 read-only 0x00000000 0xFFFFFFFF PDMA_SBUF PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. 0 32 read-only PDMA_ch3 PDMA Register Map PDMA 0x50008300 0x0 0x28 registers 0x80 0x4 registers PDMA_CSRx PDMA_CSRx PDMA Control Register 0x0 read-write 0x00000000 0xFFFFFFFF PDMACEN PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write SW_RST Software Engine Reset\n 1 1 0 No effect #0 1 Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles #1 read-write MODE_SEL PDMA Mode Selection\n 2 2 0 Memory to Memory mode (Memory-to-Memory) #00 1 Peripheral to Memory mode (Peripheral-to-Memory) #01 2 Memory to Peripheral mode (Memory-to-Peripheral) #10 read-write SAD_SEL Transfer Source Address Direction Selection\n 4 2 0 Transfer source address is increasing successively #00 1 Reserved #01 2 Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) #10 3 Reserved #11 read-write DAD_SEL Transfer Destination Address Direction Selection\n 6 2 0 Transfer destination address is increasing successively #00 1 Reserved #01 2 Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination) #10 3 Reserved #11 read-write APB_TWS Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). 19 2 0 One word (32-bit) is transferred for every PDMA operation #00 1 One byte (8-bit) is transferred for every PDMA operation #01 2 One half-word (16-bit) is transferred for every PDMA operation #10 3 Reserved #11 read-write TRIG_EN TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again. 23 1 0 No effect #0 1 PDMA data read or write transfer Enabled #1 read-write PDMA_SARx PDMA_SARx PDMA Source Address Register 0x4 read-write 0x00000000 0xFFFFFFFF PDMA_SAR PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. 0 32 read-write PDMA_DARx PDMA_DARx PDMA Destination Address Register 0x8 read-write 0x00000000 0xFFFFFFFF PDMA_DAR PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment. 0 32 read-write PDMA_BCRx PDMA_BCRx PDMA Transfer Byte Count Register 0xC read-write 0x00000000 0xFFFFFFFF PDMA_BCR PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment. 0 16 read-write PDMA_POINTx PDMA_POINTx PDMA Internal buffer pointer 0x10 read-only 0x00000000 0x0000FFFF PDMA_POINT PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer. 0 2 read-only PDMA_CSARx PDMA_CSARx PDMA Current Source Address Register 0x14 read-only 0x00000000 0xFFFFFFFF PDMA_CSAR PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs. 0 32 read-only PDMA_CDARx PDMA_CDARx PDMA Current Destination Address Register 0x18 read-only 0x00000000 0xFFFFFFFF PDMA_CDAR PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs. 0 32 read-only PDMA_CBCRx PDMA_CBCRx PDMA Current Transfer Byte Count Register 0x1C read-only 0x00000000 0xFFFFFFFF PDMA_CBCR PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value. 0 16 read-only PDMA_IERx PDMA_IERx PDMA Interrupt Enable Register 0x20 read-write 0x00000001 0xFFFFFFFF TABORT_IE PDMA Read/Write Target Abort Interrupt Enable\n 0 1 0 Target abort interrupt generation Disabled during PDMA transfer #0 1 Target abort interrupt generation Enabled during PDMA transfer #1 read-write BLKD_IE PDMA Transfer Done Interrupt Enable\n 1 1 0 Interrupt generator Disabled when PDMA transfer is done #0 1 Interrupt generator Enabled when PDMA transfer is done #1 read-write PDMA_ISRx PDMA_ISRx PDMA Interrupt Status Register 0x24 read-write 0x00000000 0xFFFFFFFF TABORT_IF PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. 0 1 0 No bus ERROR response received #0 1 Bus ERROR response received #1 read-write BLKD_IF Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. 1 1 0 Not finished #0 1 Done #1 read-write PDMA_SBUF_cx PDMA_SBUF_cx PDMA Shared Buffer FIFO 0x80 read-only 0x00000000 0xFFFFFFFF PDMA_SBUF PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. 0 32 read-only PDMA_ch4 PDMA Register Map PDMA 0x50008400 0x0 0x28 registers 0x80 0x4 registers PDMA_CSRx PDMA_CSRx PDMA Control Register 0x0 read-write 0x00000000 0xFFFFFFFF PDMACEN PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write SW_RST Software Engine Reset\n 1 1 0 No effect #0 1 Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles #1 read-write MODE_SEL PDMA Mode Selection\n 2 2 0 Memory to Memory mode (Memory-to-Memory) #00 1 Peripheral to Memory mode (Peripheral-to-Memory) #01 2 Memory to Peripheral mode (Memory-to-Peripheral) #10 read-write SAD_SEL Transfer Source Address Direction Selection\n 4 2 0 Transfer source address is increasing successively #00 1 Reserved #01 2 Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) #10 3 Reserved #11 read-write DAD_SEL Transfer Destination Address Direction Selection\n 6 2 0 Transfer destination address is increasing successively #00 1 Reserved #01 2 Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination) #10 3 Reserved #11 read-write APB_TWS Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). 19 2 0 One word (32-bit) is transferred for every PDMA operation #00 1 One byte (8-bit) is transferred for every PDMA operation #01 2 One half-word (16-bit) is transferred for every PDMA operation #10 3 Reserved #11 read-write TRIG_EN TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again. 23 1 0 No effect #0 1 PDMA data read or write transfer Enabled #1 read-write PDMA_SARx PDMA_SARx PDMA Source Address Register 0x4 read-write 0x00000000 0xFFFFFFFF PDMA_SAR PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. 0 32 read-write PDMA_DARx PDMA_DARx PDMA Destination Address Register 0x8 read-write 0x00000000 0xFFFFFFFF PDMA_DAR PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment. 0 32 read-write PDMA_BCRx PDMA_BCRx PDMA Transfer Byte Count Register 0xC read-write 0x00000000 0xFFFFFFFF PDMA_BCR PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment. 0 16 read-write PDMA_POINTx PDMA_POINTx PDMA Internal buffer pointer 0x10 read-only 0x00000000 0x0000FFFF PDMA_POINT PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer. 0 2 read-only PDMA_CSARx PDMA_CSARx PDMA Current Source Address Register 0x14 read-only 0x00000000 0xFFFFFFFF PDMA_CSAR PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs. 0 32 read-only PDMA_CDARx PDMA_CDARx PDMA Current Destination Address Register 0x18 read-only 0x00000000 0xFFFFFFFF PDMA_CDAR PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs. 0 32 read-only PDMA_CBCRx PDMA_CBCRx PDMA Current Transfer Byte Count Register 0x1C read-only 0x00000000 0xFFFFFFFF PDMA_CBCR PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value. 0 16 read-only PDMA_IERx PDMA_IERx PDMA Interrupt Enable Register 0x20 read-write 0x00000001 0xFFFFFFFF TABORT_IE PDMA Read/Write Target Abort Interrupt Enable\n 0 1 0 Target abort interrupt generation Disabled during PDMA transfer #0 1 Target abort interrupt generation Enabled during PDMA transfer #1 read-write BLKD_IE PDMA Transfer Done Interrupt Enable\n 1 1 0 Interrupt generator Disabled when PDMA transfer is done #0 1 Interrupt generator Enabled when PDMA transfer is done #1 read-write PDMA_ISRx PDMA_ISRx PDMA Interrupt Status Register 0x24 read-write 0x00000000 0xFFFFFFFF TABORT_IF PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. 0 1 0 No bus ERROR response received #0 1 Bus ERROR response received #1 read-write BLKD_IF Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. 1 1 0 Not finished #0 1 Done #1 read-write PDMA_SBUF_cx PDMA_SBUF_cx PDMA Shared Buffer FIFO 0x80 read-only 0x00000000 0xFFFFFFFF PDMA_SBUF PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. 0 32 read-only PDMA_ch5 PDMA Register Map PDMA 0x50008500 0x0 0x28 registers 0x80 0x4 registers PDMA_CSRx PDMA_CSRx PDMA Control Register 0x0 read-write 0x00000000 0xFFFFFFFF PDMACEN PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write SW_RST Software Engine Reset\n 1 1 0 No effect #0 1 Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles #1 read-write MODE_SEL PDMA Mode Selection\n 2 2 0 Memory to Memory mode (Memory-to-Memory) #00 1 Peripheral to Memory mode (Peripheral-to-Memory) #01 2 Memory to Peripheral mode (Memory-to-Peripheral) #10 read-write SAD_SEL Transfer Source Address Direction Selection\n 4 2 0 Transfer source address is increasing successively #00 1 Reserved #01 2 Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) #10 3 Reserved #11 read-write DAD_SEL Transfer Destination Address Direction Selection\n 6 2 0 Transfer destination address is increasing successively #00 1 Reserved #01 2 Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination) #10 3 Reserved #11 read-write APB_TWS Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). 19 2 0 One word (32-bit) is transferred for every PDMA operation #00 1 One byte (8-bit) is transferred for every PDMA operation #01 2 One half-word (16-bit) is transferred for every PDMA operation #10 3 Reserved #11 read-write TRIG_EN TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again. 23 1 0 No effect #0 1 PDMA data read or write transfer Enabled #1 read-write PDMA_SARx PDMA_SARx PDMA Source Address Register 0x4 read-write 0x00000000 0xFFFFFFFF PDMA_SAR PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. 0 32 read-write PDMA_DARx PDMA_DARx PDMA Destination Address Register 0x8 read-write 0x00000000 0xFFFFFFFF PDMA_DAR PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment. 0 32 read-write PDMA_BCRx PDMA_BCRx PDMA Transfer Byte Count Register 0xC read-write 0x00000000 0xFFFFFFFF PDMA_BCR PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment. 0 16 read-write PDMA_POINTx PDMA_POINTx PDMA Internal buffer pointer 0x10 read-only 0x00000000 0x0000FFFF PDMA_POINT PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer. 0 2 read-only PDMA_CSARx PDMA_CSARx PDMA Current Source Address Register 0x14 read-only 0x00000000 0xFFFFFFFF PDMA_CSAR PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs. 0 32 read-only PDMA_CDARx PDMA_CDARx PDMA Current Destination Address Register 0x18 read-only 0x00000000 0xFFFFFFFF PDMA_CDAR PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs. 0 32 read-only PDMA_CBCRx PDMA_CBCRx PDMA Current Transfer Byte Count Register 0x1C read-only 0x00000000 0xFFFFFFFF PDMA_CBCR PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value. 0 16 read-only PDMA_IERx PDMA_IERx PDMA Interrupt Enable Register 0x20 read-write 0x00000001 0xFFFFFFFF TABORT_IE PDMA Read/Write Target Abort Interrupt Enable\n 0 1 0 Target abort interrupt generation Disabled during PDMA transfer #0 1 Target abort interrupt generation Enabled during PDMA transfer #1 read-write BLKD_IE PDMA Transfer Done Interrupt Enable\n 1 1 0 Interrupt generator Disabled when PDMA transfer is done #0 1 Interrupt generator Enabled when PDMA transfer is done #1 read-write PDMA_ISRx PDMA_ISRx PDMA Interrupt Status Register 0x24 read-write 0x00000000 0xFFFFFFFF TABORT_IF PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. 0 1 0 No bus ERROR response received #0 1 Bus ERROR response received #1 read-write BLKD_IF Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. 1 1 0 Not finished #0 1 Done #1 read-write PDMA_SBUF_cx PDMA_SBUF_cx PDMA Shared Buffer FIFO 0x80 read-only 0x00000000 0xFFFFFFFF PDMA_SBUF PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. 0 32 read-only CRC PDMA Register Map PDMA 0x50008E00 0x0 0x8 registers 0xC 0x4 registers 0x14 0x4 registers 0x1C 0xC registers 0x80 0xC registers CRC_CTL CRC_CTL CRC Control Register 0x0 read-write 0x20000000 0xFFFFFFFF CRCCEN CRC Channel Enable\nSetting this bit to 1 enables CRC's operation.\n 0 1 read-write CRC_RST CRC Engine Reset\nNote: When operated in CPU PIO mode, setting this bit will reload the initial seed value. 1 1 0 No effect #0 1 Reset the internal CRC state machine and internal buffer. The contents of control register will not be cleared. This bit will automatically be cleared after few clock cycles #1 read-write TRIG_EN TRIG_EN\nNote1: If this bit assert indicates the CRC engine operation in CRC DMA mode, do not fill in any data in CRC_WDATA register.\nNote2: When CRC DMA transfer is completed, this bit will be cleared automatically.\nNote3: If the bus error occurs, all CRC DMA transfer will be stopped. Software must reset all DMA channel, and then trigger again. 23 1 0 No effect #0 1 CRC DMA data read or write transfer Enabled #1 read-write WDATA_RVS Write Data Order Reverse\nNote: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB 24 1 0 No bit order reversed for CRC write data in #0 1 Bit order reversed for CRC write data in (per byte) #1 read-write CHECKSUM_RVS Checksum Reverse\nNote: If the checksum data is 0XDD7B0F2E, the bit order reversed for CRC checksum is 0x74F0DEBB. 25 1 0 No bit order reverse for CRC checksum #0 1 Bit order reverse for CRC checksum #1 read-write WDATA_COM Write Data Complement\n 26 1 0 No 1's complement for CRC write data in #0 1 1's complement for CRC write data in #1 read-write CHECKSUM_COM Checksum Complement\n 27 1 0 No 1's complement for CRC checksum #0 1 1's complement for CRC checksum #1 read-write CPU_WDLEN CPU Write Data Length\nNote1: This field is used for CPU PIO mode.\nNote2: When the data length is 8-bit mode, the valid data is CRC_WDATA [7:0]; if the data length is 16-bit mode, the valid data is CRC_WDATA [15:0]. 28 2 0 Data length is 8-bit mode #00 1 Data length is 16-bit mode\nData length is 32-bit mode #01 read-write CRC_MODE CRC Polynomial Mode\n 30 2 0 CRC-CCITT Polynomial mode #00 1 CRC-8 Polynomial mode #01 2 CRC-16 Polynomial mode #10 3 CRC-32 Polynomial mode #11 read-write CRC_DMASAR CRC_DMASAR CRC DMA Source Address Register 0x4 read-write 0x00000000 0xFFFFFFFF CRC_DMASAR CRC DMA Transfer Source Address Register\nThis field indicates a 32-bit source address of CRC DMA.\nNote: The source address must be word alignment. 0 32 read-write CRC_DMABCR CRC_DMABCR CRC DMA Transfer Byte Count Register 0xC read-write 0x00000000 0xFFFFFFFF CRC_DMABCR CRC DMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of CRC DMA. 0 16 read-write CRC_DMACSAR CRC_DMACSAR CRC DMA Current Source Address Register 0x14 read-only 0x00000000 0xFFFFFFFF CRC_DMACSAR CRC DMA Current Source Address Register (Read Only)\nThis field indicates the source address where the CRC DMA transfer just occurs. 0 32 read-only CRC_DMACBCR CRC_DMACBCR CRC DMA Current Transfer Byte Count Register 0x1C read-only 0x00000000 0xFFFFFFFF CRC_DMACBCR CRC DMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of CRC_DMA.\nNote: CRC_RST will clear this register value. 0 16 read-only CRC_DMAIER CRC_DMAIER CRC DMA Interrupt Enable Register 0x20 read-write 0x00000001 0xFFFFFFFF TABORT_IE CRC DMA Read/Write Target Abort Interrupt Enable\n 0 1 0 Target abort interrupt generation Disabled during CRC DMA transfer #0 1 Target abort interrupt generation Enabled during CRC DMA transfer #1 read-write BLKD_IE CRC DMA Transfer Done Interrupt Enable\n 1 1 0 Interrupt generator Disabled when CRC DMA transfer is done #0 1 Interrupt generator Enabled when CRC DMA transfer is done #1 read-write CRC_DMAISR CRC_DMAISR CRC DMA Interrupt Status Register 0x24 read-write 0x00000000 0xFFFFFFFF TABORT_IF CRC DMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero. 0 1 0 No bus ERROR response received #0 1 Bus ERROR response received #1 read-write BLKD_IF Block Transfer Done Interrupt Flag\nThis bit indicates that CRC DMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero. 1 1 0 Not finished #0 1 Done #1 read-write CRC_WDATA CRC_WDATA CRC Write Data Register 0x80 read-write 0x00000000 0xFFFFFFFF CRC_WDATA CRC Write Data Register\n 0 32 read-write CRC_SEED CRC_SEED CRC Seed Register 0x84 read-write 0xFFFFFFFF 0xFFFFFFFF CRC_SEED CRC Seed Register\nThis field indicates the CRC seed value. 0 32 read-write CRC_CHECKSUM CRC_CHECKSUM CRC Checksum Register 0x88 read-only 0x00000000 0xFFFFFFFF CRC_CHECKSUM CRC Checksum Register\nThis field indicates the CRC checksum. 0 32 read-only DMA_GCR PDMA Register Map PDMA 0x50008F00 0x0 0x14 registers DMA_GCRCSR DMA_GCRCSR DMA Global Control Register 0x0 read-write 0x00000000 0xFFFFFFFF CLK0_EN PDMA Controller Channel 0 Clock Enable Control\n 8 1 0 Disabled #0 1 Enabled #1 read-write CLK1_EN PDMA Controller Channel 1 Clock Enable Control\n 9 1 0 Disabled #0 1 Enabled #1 read-write CLK2_EN PDMA Controller Channel 2 Clock Enable Control \n 10 1 0 Disabled #0 1 Enabled #1 read-write CLK3_EN PDMA Controller Channel 3 Clock Enable Control\n 11 1 0 Disabled #0 1 Enabled #1 read-write CLK4_EN PDMA Controller Channel 4 Clock Enable Control\n 12 1 0 Disabled #0 1 Enabled #1 read-write CLK5_EN PDMA Controller Channel 5 Clock Enable Control\n 13 1 0 Disabled #0 1 Enabled #1 read-write CRC_CLK_EN CRC Controller Clock Enable Control\n 24 1 0 Disabled #0 1 Enabled #1 read-write DMA_PDSSR0 DMA_PDSSR0 DMA Service Selection Control Register 0 0x4 read-write 0x00FFFFFF 0xFFFFFFFF SPI0_RXSEL PDMA SPI0 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI0 RX. Software can change the channel RX setting by SPI0_RXSEL.\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3 \n4'b0100: CH4 \n4'b0101: CH5\nOthers: Reserved\n 0 4 read-write SPI0_TXSEL PDMA SPI0 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI0 TX. Software can configure the TX channel setting by SPI0_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL. 4 4 read-write SPI1_RXSEL PDMA SPI1 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI1 RX. Software can configure the RX channel setting by SPI1_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL. 8 4 read-write SPI1_TXSEL PDMA SPI1 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI1 TX. Software can configure the TX channel setting by SPI1_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL. 12 4 read-write SPI2_RXSEL PDMA SPI2 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI2 RX. Software can configure the RX channel setting by SPI2_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL. 16 4 read-write SPI2_TXSEL PDMA SPI2 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI2 TX. Software can configure the TX channel setting by SPI2_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL. 20 4 read-write DMA_PDSSR1 DMA_PDSSR1 DMA Service Selection Control Register 1 0x8 read-write 0x0FFFFFFF 0xFFFFFFFF UART0_RXSEL This filed defines which PDMA channel is connected to the on-chip peripheral UART0 RX. Software can change the channel RX setting by UART0_RXSEL.\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3 \n4'b0100: CH4 \n4'b0101: CH5\nOthers : Reserved\n 0 4 read-write UART0_TXSEL PDMA UART0 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral UART0 TX. Software can configure the TX channel setting by UART0_TXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL. 4 4 read-write UART1_RXSEL PDMA UART1 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral UART1 RX. Software can configure the RX channel setting by UART1_RXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL. 8 4 read-write UART1_TXSEL PDMA UART1 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral UART1 TX. Software can configure the TX channel setting by UART1_TXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL. 12 4 read-write ADC_RXSEL PDMA ADC RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral ADC RX. Software can configure the RX channel setting by ADC_RXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL. 24 4 read-write DMA_GCRISR DMA_GCRISR DMA Global Interrupt Status Register 0xC read-only 0x00000000 0xFFFFFFFF INTR0 Interrupt Pin Status of Channel 0\nThis bit is the Interrupt status of PDMA channel 0.\nNote: This bit is read only. 0 1 read-only INTR1 Interrupt Pin Status of Channel 1\nThis bit is the Interrupt status of PDMA channel 1.\nNote: This bit is read only. 1 1 read-only INTR2 Interrupt Pin Status of Channel 2\nThis bit is the Interrupt status of PDMA channel 2.\nNote: This bit is read only. 2 1 read-only INTR3 Interrupt Pin Status of Channel 3\nThis bit is the Interrupt status of PDMA channel 3.\nNote: This bit is read only. 3 1 read-only INTR4 Interrupt Pin Status of Channel 4\nThis bit is the Interrupt status of PDMA channel 4.\nNote: This bit is read only. 4 1 read-only INTR5 Interrupt Pin Status of Channel 5 \nThis bit is the Interrupt status of PDMA channel 5.\nNote: This bit is read only. 5 1 read-only CRC_INTR Interrupt Pin Status of CRC Controller\nThis bit is the Interrupt status of CRC controller.\nNote: This bit is read only. 6 1 read-only INTR Interrupt Pin Status\nThis bit is the Interrupt status of PDMA controller.\nNote: This bit is read only 31 1 read-only DMA_PDSSR2 DMA_PDSSR2 DMA Service Selection Control Register 2 0x10 read-write 0x00FFFFFF 0xFFFFFFFF I2S_RXSEL PDMA I2S RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral I2S RX. Software can change the channel RX setting by I2S_RXSEL\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3\n4'b0100: CH4\n4'b0101: CH5\nOthers : Reserved\n 0 4 read-write I2S_TXSEL PDMA I2S TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral I2S TX. Software can configure the TX channel setting by I2S_TXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL. 4 4 read-write PWM0_RXSEL PDMA PWM0 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM0 RX. Software can configure the RX channel setting by PWM0_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL. 8 4 read-write PWM1_RXSEL PDMA PWM1 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM1 RX. Software can configure the RX channel setting by PWM1_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL. 12 4 read-write PWM2_RXSEL PDMA PWM2 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM2 RX. Software can configure the RX channel setting by PWM2_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL. 16 4 read-write PWM3_RXSEL PDMA PWM3 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM3 RX. Software can configure the RX channel setting by PWM3_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL. 20 4 read-write