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<?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
<name>NUC123AN_v1</name>
<version>1.0</version>
<description>NUC123AN_v1 SVD file</description>
<!-- Bus Interface Properties -->
<!-- Cortex-M0 is byte addressable -->
<addressUnitBits>8</addressUnitBits>
<!-- the maximum data bit width accessible within a single transfer is 32bits -->
<width>32</width>
<!-- Register Default Properties -->
<!-- the size of the registers is set to a bit width of 32. This can be overruled for individual peripherals and/or registers -->
<size>32</size>
<!-- the access to all registers is set to be readable and writeable. This can be overruled for individual peripherals and/or registers -->
<access>read-write</access>
<!-- for demonstration purposes the resetValue for all registers of the device is set to be 0. This can be overruled within the description -->
<resetValue>0</resetValue>
<!-- the resetMask = 0 specifies that by default no register of this device has a defined reset value -->
<resetMask>0</resetMask>
<peripherals>
<peripheral>
<name>SCS</name>
<description>SCS Register Map</description>
<groupName>SCS</groupName>
<baseAddress>0xE000E000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x10</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x100</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x180</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x200</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x280</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x400</offset>
<size>0x20</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0xD00</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0xD0C</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0xD1C</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SYST_CSR</name>
<!-- the display name is an unrestricted string. -->
<displayName>SYST_CSR</displayName>
<description>SysTick Control and Status Register</description>
<addressOffset>0x10</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ENABLE</name>
<description></description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Counter Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Counter will operate in a multi-shot manner</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TICKINT</name>
<description></description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick current value register by a register write in software will not cause SysTick to be pended</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CLKSRC</name>
<description></description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock source is (optional) external reference clock</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Core clock used for SysTick</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>COUNTFLAG</name>
<description>Returns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SYST_RVR</name>
<!-- the display name is an unrestricted string. -->
<displayName>SYST_RVR</displayName>
<description>SysTick Reload Value Register</description>
<addressOffset>0x14</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RELOAD</name>
<description>The value to load into the Current Value register when the counter reaches 0.</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SYST_CVR</name>
<!-- the display name is an unrestricted string. -->
<displayName>SYST_CVR</displayName>
<description>SysTick Current Value Register</description>
<addressOffset>0x18</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>CURRENT</name>
<description>Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ (see SysTick Reload Value register).</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>NVIC_ISER</name>
<!-- the display name is an unrestricted string. -->
<displayName>NVIC_ISER</displayName>
<description>IRQ0 ~ IRQ31 Set-Enable Control Register</description>
<addressOffset>0x100</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SETENA</name>
<description>Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nThe register reads back with the current enable state.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Associated interrupt Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>NVIC_ICER</name>
<!-- the display name is an unrestricted string. -->
<displayName>NVIC_ICER</displayName>
<description>IRQ0 ~ IRQ31 Clear-Enable Control Register</description>
<addressOffset>0x180</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLRENA</name>
<description>Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nThe register reads back with the current enable state.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Associated interrupt Disabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>NVIC_ISPR</name>
<!-- the display name is an unrestricted string. -->
<displayName>NVIC_ISPR</displayName>
<description>IRQ0 ~ IRQ31 Set-Pending Control Register</description>
<addressOffset>0x200</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SETPEND</name>
<description>The register reads back with the current pending state.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Set pending state of the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>NVIC_ICPR</name>
<!-- the display name is an unrestricted string. -->
<displayName>NVIC_ICPR</displayName>
<description>IRQ0 ~ IRQ31 Clear-Pending Control Register</description>
<addressOffset>0x280</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLRPEND</name>
<description>The register reads back with the current pending state.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Removes the pending state of associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>NVIC_IPR0</name>
<!-- the display name is an unrestricted string. -->
<displayName>NVIC_IPR0</displayName>
<description>IRQ0 ~ IRQ3 Priority Control Register</description>
<addressOffset>0x400</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PRI_0</name>
<description>Priority of IRQ0\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_1</name>
<description>Priority of IRQ1\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_2</name>
<description>Priority of IRQ2\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_3</name>
<description>Priority of IRQ3\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>NVIC_IPR1</name>
<!-- the display name is an unrestricted string. -->
<displayName>NVIC_IPR1</displayName>
<description>IRQ4 ~ IRQ7 Priority Control Register</description>
<addressOffset>0x404</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PRI_4</name>
<description>Priority of IRQ4\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_5</name>
<description>Priority of IRQ5\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_6</name>
<description>Priority of IRQ6\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_7</name>
<description>Priority of IRQ7\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>NVIC_IPR2</name>
<!-- the display name is an unrestricted string. -->
<displayName>NVIC_IPR2</displayName>
<description>IRQ8 ~ IRQ11 Priority Control Register</description>
<addressOffset>0x408</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PRI_8</name>
<description>Priority of IRQ8\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_9</name>
<description>Priority of IRQ9\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_10</name>
<description>Priority of IRQ10\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_11</name>
<description>Priority of IRQ11\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>NVIC_IPR3</name>
<!-- the display name is an unrestricted string. -->
<displayName>NVIC_IPR3</displayName>
<description>IRQ12 ~ IRQ15 Priority Control Register</description>
<addressOffset>0x40C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PRI_12</name>
<description>Priority of IRQ12\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_13</name>
<description>Priority of IRQ13\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_14</name>
<description>Priority of IRQ14\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_15</name>
<description>Priority of IRQ15\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>NVIC_IPR4</name>
<!-- the display name is an unrestricted string. -->
<displayName>NVIC_IPR4</displayName>
<description>IRQ16 ~ IRQ19 Priority Control Register</description>
<addressOffset>0x410</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PRI_16</name>
<description>Priority of IRQ16\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_17</name>
<description>Priority of IRQ17\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_18</name>
<description>Priority of IRQ18\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_19</name>
<description>Priority of IRQ19\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>NVIC_IPR5</name>
<!-- the display name is an unrestricted string. -->
<displayName>NVIC_IPR5</displayName>
<description>IRQ20 ~ IRQ23 Priority Control Register</description>
<addressOffset>0x414</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PRI_20</name>
<description>Priority of IRQ20\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_21</name>
<description>Priority of IRQ21\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_22</name>
<description>Priority of IRQ22\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_23</name>
<description>Priority of IRQ23\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>NVIC_IPR6</name>
<!-- the display name is an unrestricted string. -->
<displayName>NVIC_IPR6</displayName>
<description>IRQ24 ~ IRQ27 Priority Control Register</description>
<addressOffset>0x418</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PRI_24</name>
<description>Priority of IRQ24\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_25</name>
<description>Priority of IRQ25\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_26</name>
<description>Priority of IRQ26\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_27</name>
<description>Priority of IRQ27\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>NVIC_IPR7</name>
<!-- the display name is an unrestricted string. -->
<displayName>NVIC_IPR7</displayName>
<description>IRQ28 ~ IRQ31 Priority Control Register</description>
<addressOffset>0x41C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PRI_28</name>
<description>Priority of IRQ28\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_29</name>
<description>Priority of IRQ29\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_30</name>
<description>Priority of IRQ30\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_31</name>
<description>Priority of IRQ31\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CPUID</name>
<!-- the display name is an unrestricted string. -->
<displayName>CPUID</displayName>
<description>CPUID Register</description>
<addressOffset>0xD00</addressOffset>
<access>read-only</access>
<resetValue>0x410CC200</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>REVISION</name>
<description>Reads as 0x0</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PARTNO</name>
<description>Reads as 0xC20.</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PART</name>
<description>Reads as 0xC for ARMv6-M parts</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>IMPLEMENTER</name>
<description></description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ICSR</name>
<!-- the display name is an unrestricted string. -->
<displayName>ICSR</displayName>
<description>Interrupt Control and State Register</description>
<addressOffset>0xD04</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VECTACTIVE</name>
<description>Contains the active exception number.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Thread mode</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>VECTPENDING</name>
<description>Indicates the exception number of the highest priority pending enabled exception:\n</description>
<bitOffset>12</bitOffset>
<bitWidth>6</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No pending exceptions</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRPENDING</name>
<description>Interrupt Pending Flag, Rxcluding NMI and Faults\nThis is a read only bit.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt not pending</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt pending</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRPREEMPT</name>
<description>If set, a pending exception will be serviced on exit from the debug halt state.\nThis is a read only bit.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PENDSTCLR</name>
<description>SysTick Exception Clear-pending Bit\nWrite:\nThis is a write only bit. When you want to clear PENDST bit, you must "write 0 to PENDSTSET and write 1 to PENDSTCLR" at the same time.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Removes the pending state from the SysTick exception</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PENDSTSET</name>
<description>SysTick Exception Set-pending Bit\nWrite:\n</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect.\nSysTick exception is not pending</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Changes SysTick exception state to pending.\nSysTick exception is pending</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PENDSVCLR</name>
<description>PendSV Clear-pending Bit\nWrite:\nThis is a write only bit. When you want to clear PENDSV bit, you must "write 0 to PENDSVSET and write 1 to PENDSVCLR" at the same time.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Removes the pending state from the PendSV exception</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PENDSVSET</name>
<description>PendSV Set-pending Bit\nWrite:\nWriting 1 to this bit is the only way to set the PendSV exception state to pending.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect.\nPendSV exception is not pending</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Changes PendSV exception state to pending.\nPendSV exception is pending</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>NMIPENDSET</name>
<description>NMI Set-pending Bit\nWrite:\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect.\nNMI exception is not pending</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Changes NMI exception state to pending.\nNMI exception is pending</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>AIRCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>AIRCR</displayName>
<description>Application Interrupt and Reset Control Register</description>
<addressOffset>0xD0C</addressOffset>
<access>read-write</access>
<resetValue>0xFA050000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VECTCLRACTIVE</name>
<description>Set this bit to 1 will clears all active state information for fixed and configurable exceptions.\nThe bit is a write only bit and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SYSRESETREQ</name>
<description>Writing this bit 1 will cause a reset signal to be asserted to the chip and indicate a reset is requested.\nThe bit is a write only and self-cleared as part of the reset sequence.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VECTORKEY</name>
<description>When write this register, this field should be 0x05FA, otherwise the write action will be unpredictable.</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>SCR</displayName>
<description>System Control Register</description>
<addressOffset>0xD10</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SLEEPONEXIT</name>
<description>Indicates sleep-on-exit when returning from Handler mode to Thread mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Do not sleep when returning to Thread mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enters sleep, or deep sleep, on return from an ISR to Thread mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SLEEPDEEP</name>
<description>Controls whether the processor uses sleep or deep sleep as its low power mode:\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Sleep</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Deep sleep</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SEVONPEND</name>
<description>Send Event on Pending bit:\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Only enabled interrupts or events can wake up the processor, while disabled interrupts are excluded</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled events and all interrupts, including disabled interrupts, can wake up the processor</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SHPR2</name>
<!-- the display name is an unrestricted string. -->
<displayName>SHPR2</displayName>
<description>System Handler Priority Register 2</description>
<addressOffset>0xD1C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PRI_11</name>
<description>Priority of system handler 11 - SVCall\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SHPR3</name>
<!-- the display name is an unrestricted string. -->
<displayName>SHPR3</displayName>
<description>System Handler Priority Register 3</description>
<addressOffset>0xD20</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PRI_14</name>
<description>Priority of System Handler 14 - PendSV\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRI_15</name>
<description>Priority of System Handler 15 - SysTick\n"0" denotes the highest priority and "3" denotes the lowest priority.</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>INT</name>
<description>INT Register Map</description>
<groupName>INT</groupName>
<baseAddress>0x50000300</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x88</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>IRQ0_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ0_SRC</displayName>
<description>IRQ0 (BOD) interrupt source identity</description>
<addressOffset>0x0</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: BOD_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ1_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ1_SRC</displayName>
<description>IRQ1 (WDT) interrupt source identity</description>
<addressOffset>0x4</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: WDT_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ2_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ2_SRC</displayName>
<description>IRQ2 (EINT0) interrupt source identity</description>
<addressOffset>0x8</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: EINT0 - external interrupt 0 from PB.14</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ3_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ3_SRC</displayName>
<description>IRQ3 (EINT1) interrupt source identity</description>
<addressOffset>0xC</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: EINT1 - external interrupt 1 from PB.15 or PD.11</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ4_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ4_SRC</displayName>
<description>IRQ4 (GPA/B) interrupt source identity</description>
<addressOffset>0x10</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: GPB_INT\nBit0: GPA_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ5_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ5_SRC</displayName>
<description>IRQ5 (GPC/D/F) interrupt source identity</description>
<addressOffset>0x14</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit3: GPF_INT\nBit2: 0\nBit1: GPD_INT\nBit0: GPC_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ6_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ6_SRC</displayName>
<description>IRQ6 (PWMA) interrupt source identity</description>
<addressOffset>0x18</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit3: PWM3_INT\nBit2: PWM2_INT\nBit1: PWM1_INT\nBit0: PWM0_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ7_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ7_SRC</displayName>
<description>IRQ7 (Reserved) interrupt source identity</description>
<addressOffset>0x1C</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
</register>
<register>
<name>IRQ8_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ8_SRC</displayName>
<description>IRQ8 (TMR0) interrupt source identity</description>
<addressOffset>0x20</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: TMR0_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ9_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ9_SRC</displayName>
<description>IRQ9 (TMR1) interrupt source identity</description>
<addressOffset>0x24</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: TMR1_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ10_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ10_SRC</displayName>
<description>IRQ10 (TMR2) interrupt source identity</description>
<addressOffset>0x28</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: TMR2_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ11_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ11_SRC</displayName>
<description>IRQ11 (TMR3) interrupt source identity</description>
<addressOffset>0x2C</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: TMR3_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ12_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ12_SRC</displayName>
<description>IRQ12 (UART0) interrupt source identity</description>
<addressOffset>0x30</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: URT0_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ13_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ13_SRC</displayName>
<description>IRQ13 (UART1) interrupt source identity</description>
<addressOffset>0x34</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: UART1_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ14_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ14_SRC</displayName>
<description>IRQ14 (SPI0) interrupt source identity</description>
<addressOffset>0x38</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: SPI0_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ15_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ15_SRC</displayName>
<description>IRQ15 (SPI1) interrupt source identity</description>
<addressOffset>0x3C</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: SPI1_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ16_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ16_SRC</displayName>
<description>IRQ16 (SPI2) interrupt source identity</description>
<addressOffset>0x40</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: SPI2_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ17_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ17_SRC</displayName>
<description>IRQ17 (Reserved) interrupt source identity</description>
<addressOffset>0x44</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
</register>
<register>
<name>IRQ18_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ18_SRC</displayName>
<description>IRQ18 (I2C0) interrupt source identity</description>
<addressOffset>0x48</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: I2C0_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ19_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ19_SRC</displayName>
<description>IRQ19 (I2C1) interrupt source identity</description>
<addressOffset>0x4C</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: I2C1_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ20_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ20_SRC</displayName>
<description>IRQ20 (Reserved) interrupt source identity</description>
<addressOffset>0x50</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
</register>
<register>
<name>IRQ21_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ21_SRC</displayName>
<description>IRQ21 (Reserved) interrupt source identity</description>
<addressOffset>0x54</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
</register>
<register>
<name>IRQ22_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ22_SRC</displayName>
<description>IRQ22 (Reserved ) interrupt source identity</description>
<addressOffset>0x58</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
</register>
<register>
<name>IRQ23_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ23_SRC</displayName>
<description>IRQ23 (USBD) interrupt source identity</description>
<addressOffset>0x5C</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: USB_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ24_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ24_SRC</displayName>
<description>IRQ24 (PS/2) interrupt source identity</description>
<addressOffset>0x60</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: PS2_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ25_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ25_SRC</displayName>
<description>IRQ25 (Reserved) interrupt source identity</description>
<addressOffset>0x64</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
</register>
<register>
<name>IRQ26_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ26_SRC</displayName>
<description>IRQ26 (PDMA) interrupt source identity</description>
<addressOffset>0x68</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: PDMA_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ27_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ27_SRC</displayName>
<description>IRQ27 (I2S) interrupt source identity</description>
<addressOffset>0x6C</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: I2S_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ28_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ28_SRC</displayName>
<description>IRQ28 (PWRWU) interrupt source identity</description>
<addressOffset>0x70</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: PWRWU_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ29_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ29_SRC</displayName>
<description>IRQ29 (ADC) interrupt source identity</description>
<addressOffset>0x74</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>INT_SRC</name>
<description>Bit2: 0\nBit1: 0\nBit0: ADC_INT</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IRQ30_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ30_SRC</displayName>
<description>IRQ30 (Reserved) interrupt source identity</description>
<addressOffset>0x78</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
</register>
<register>
<name>IRQ31_SRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>IRQ31_SRC</displayName>
<description>IRQ31 (Reserved) interrupt source identity</description>
<addressOffset>0x7C</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
</register>
<register>
<name>NMI_SEL</name>
<!-- the display name is an unrestricted string. -->
<displayName>NMI_SEL</displayName>
<description>NMI source interrupt select control register</description>
<addressOffset>0x80</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>NMI_SEL</name>
<description>NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL.</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NMI_EN</name>
<description>NMI Interrupt Enable\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>NMI interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>NMI interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MCU_IRQ</name>
<!-- the display name is an unrestricted string. -->
<displayName>MCU_IRQ</displayName>
<description>MCU IRQ Number identity register</description>
<addressOffset>0x84</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MCU_IRQ</name>
<description>MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0. There are two modes to generate interrupt to Cortex-M0, Normal mode and Test mode.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them and then interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0: Set MCU_IRQ[n] 1 will generate an interrupt to Cortex_M0 NVIC[n].\nWhen the MCU_IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_bit[n] will clear the interrupt and setting MCU_IRQ[n] 0 has no effect.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GCR</name>
<description>GCR Register Map</description>
<groupName>GCR</groupName>
<baseAddress>0x50000000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x10</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x18</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x24</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x30</offset>
<size>0x10</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x44</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x50</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0xA0</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0xC0</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0xCC</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x100</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PDID</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDID</displayName>
<description>Part Device Identification Number Register</description>
<addressOffset>0x0</addressOffset>
<access>read-only</access>
<resetValue>0x00012300</resetValue>
<resetMask>0xFFFFFF00</resetMask>
<fields>
<field>
<name>PDID</name>
<description>Part Device Identification Number\nThis register reflects the device part number code. S/W can read this register to identify which device is used.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>RSTSRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>RSTSRC</displayName>
<description>System Reset Source Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFF00</resetMask>
<fields>
<field>
<name>RSTS_POR</name>
<description>The RSTS_POR flag is set by the "reset signal" from the Power-On Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No reset from POR or CHIP_RST</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Power-On Reset (POR) or CHIP_RST had issued the reset signal to reset the system</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RSTS_RESET</name>
<description>The RSTS_RESET flag is set by the "reset signal" from the /RESET pin to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No reset from /RESET pin</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pin /RESET had issued the reset signal to reset the system</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RSTS_WDT</name>
<description>The RSTS_WDT flag is set by the "reset signal" from the watchdog timer to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No reset from watchdog timer</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Watchdog timer had issued the reset signal to reset the system</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RSTS_LVR</name>
<description>The RSTS_LVR flag is set by the "reset signal" from the Low-Voltage-Reset controller to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No reset from LVR</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LVR controller had issued the reset signal to reset the system</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RSTS_BOD</name>
<description>The RSTS_BOD flag is set by the "reset signal" from the Brown-out-Detector to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No reset from BOD</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>BOD had issued the reset signal to reset the system</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RSTS_SYS</name>
<description>The RSTS_SYS flag is set by the "reset signal" from the Cortex_M0 kernel to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No reset from Cortex_M0</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Cortex_M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex_M0 kernel</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RSTS_CPU</name>
<description>The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC).\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No reset from CPU</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IPRSTC1</name>
<!-- the display name is an unrestricted string. -->
<displayName>IPRSTC1</displayName>
<description>IP Reset Control Register1</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CHIP_RST</name>
<description>CHIP One-shot Reset (Write-protection Bit)\nSetting this bit will reset the whole chip, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.\nFor the difference between CHIP_RST and SYSRESETREQ, please refer to section 5.2.2.\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CHIP normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CHIP one-shot reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CPU_RST</name>
<description>CPU kernel one-shot reset (Write-protection Bit)\nSetting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles\nThis bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CPU normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CPU one-shot reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PDMA_RST</name>
<description>PDMA Controller Reset (Write-protection)\nSetting this bit to 1 will generate a reset signal to the PDMA. User need to set this bit to 0 to release from reset state.\nThis bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PDMA controller normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PDMA controller reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IPRSTC2</name>
<!-- the display name is an unrestricted string. -->
<displayName>IPRSTC2</displayName>
<description>IP Reset Control Register2</description>
<addressOffset>0xC</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPIO_RST</name>
<description>GPIO controller Reset\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO controller normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO controller reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TMR0_RST</name>
<description>Timer0 controller Reset\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer0 controller normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer0 controller reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TMR1_RST</name>
<description>Timer1 controller Reset\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer1 controller normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer1 controller reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TMR2_RST</name>
<description>Timer2 controller Reset\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer2 controller normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer2 controller reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TMR3_RST</name>
<description>Timer3 controller Reset\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer3 controller normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer3 controller reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>I2C0_RST</name>
<description>I2C0 controller Reset\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>I2C0 controller normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>I2C0 controller reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>I2C1_RST</name>
<description>I2C1 controller Reset\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>I2C1 controller normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>I2C1 controller reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SPI0_RST</name>
<description>SPI0 controller Reset\n</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI0 controller normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI0 controller reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SPI1_RST</name>
<description>SPI1 controller Reset\n</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI1 controller normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI1 controller reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SPI2_RST</name>
<description>SPI2 controller Reset \n</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI2 controller normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI2 controller reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>UART0_RST</name>
<description>UART0 controller Reset\n</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART0 controller normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART0 controller reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>UART1_RST</name>
<description>UART1 controller Reset\n</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART1 controller normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART1 controller reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWM03_RST</name>
<description>PWM03 controller Reset\n</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PWM03 controller normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PWM03 controller reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PS2_RST</name>
<description>PS/2 Controller Reset\n</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PS/2 controller normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PS/2 controller reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>USBD_RST</name>
<description>USB Device Controller Reset\n</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>USB device controller normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>USB device controller reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ADC_RST</name>
<description>ADC Controller Reset\n</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ADC controller normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ADC controller reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>I2S_RST</name>
<description>I2S Controller Reset\n</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>I2S controller normal operation</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>I2S controller reset</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>BODCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>BODCR</displayName>
<description>Brown-out Detector Control Register</description>
<addressOffset>0x18</addressOffset>
<access>read-write</access>
<resetValue>0x00000080</resetValue>
<resetMask>0xFFFFFFF0</resetMask>
<fields>
<field>
<name>BOD_EN</name>
<description>Brown-out Detector Enable (Write-protection Bit)\nThe default value is set by flash controller user configuration register config0 bit[23].\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Brown-out Detector function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Brown-out Detector function Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BOD_VL</name>
<description>Brown-out Detector Threshold Voltage Selection (Write-protection Bits)\n</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BOD_RSTEN</name>
<description>Brown-out Reset Enable (Write-protection Bit)\nWhile the BOD function is enabled (BOD_EN high) and BOD interrupt function is enabled (BOD_RSTEN low), BOD will assert an interrupt if BOD_OUT is high. BOD interrupt will keep till to the BOD_EN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BOD_EN low).\nThe default value is set by flash controller user configuration register config0 bit[20].\nThis bit is the protected bit. It means programming this needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Brown-out "INTERRUPT" function Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Brown-out "RESET" function Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BOD_INTF</name>
<description>Brown-out Detector Interrupt Flag\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>When Brown-out Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BOD_LPM</name>
<description>Brown-out Detector Low power Mode (Write-protection Bit)\nThe BOD consumes about 100 uA in Normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.\nThis bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>BOD operated in Normal mode (Default)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>BOD low power mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BOD_OUT</name>
<description>Brown-out Detector Output Status\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Brown-out Detector output status is 0, which means the detected voltage is higher than BOD_VL setting or BOD_EN is 0</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Brown-out Detector output status is 1, which means the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0, BOD function disabled , this bit always responds to 0</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>LVR_EN</name>
<description>Low Voltage Reset Enable (Write-protection Bit)\nThe LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low Voltage Reset function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low Voltage Reset function Enabled- After enabling the bit, the LVR function will be active with 100uS delay for LVR output stable (Default)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PORCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>PORCR</displayName>
<description>Power-On-Reset Controller Register</description>
<addressOffset>0x24</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFF00</resetMask>
<fields>
<field>
<name>POR_DIS_CODE</name>
<description>The register is used for the Power-On-Reset enable control (Write-protection Bits)\nWhen powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.\nThe POR function will become active again when this field is set to another value or chip is reset by other reset source, including:\n/RESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPA_MFP</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPA_MFP</displayName>
<description>GPIOA Multiple Function and Input Type Control Register</description>
<addressOffset>0x30</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPA_MFP10</name>
<description>PA.10 Pin Function Selection\n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPA_MFP11</name>
<description>PA.11 Pin Function Selection\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPA_MFP12</name>
<description>PA.12 Pin Function Selection\n</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPA_MFP13</name>
<description>PA.13 Pin Function Selection\n</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPA_MFP14</name>
<description>PA.14 Pin Function Selection\n</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPA_MFP15</name>
<description>PA.15 Pin Function Selection\n</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPA_TYPEn</name>
<description>GPA[9:0] are reserved in this chip.</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIOA[15:0] I/O input Schmitt Trigger function Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIOA[15:0] I/O input Schmitt Trigger function Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPB_MFP</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPB_MFP</displayName>
<description>GPIOB Multiple Function and Input Type Control Register</description>
<addressOffset>0x34</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPB_MFP0</name>
<description>PB.0 Pin Function Selection\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIOB[0] is selected to the pin PB.0</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART0 RXD0 function is selected to the pin PB.0</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPB_MFP1</name>
<description>PB.1 Pin Function Selection\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIOB[1] is selected to the pin PB.1</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART0 TXD0 function is selected to the pin PB.1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPB_MFP2</name>
<description>PB.2 Pin Function Selection\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPB_MFP3</name>
<description>PB.3 Pin Function Selection\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPB_MFP4</name>
<description>PB.4 Pin Function Selection\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPB_MFP5</name>
<description>PB. </description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPB_MFP6</name>
<description>PB.6 Pin Function Selection\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPB_MFP7</name>
<description>PB.7 Pin Function Selection\n</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPB_MFP8</name>
<description>PB.8 Pin Function Selection\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPB_MFP9</name>
<description>PB.9 Pin Function Selection\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPB_MFP10</name>
<description>PB.10 Pin Function Selection\n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPB_MFP12</name>
<description>PB.12 Pin Function Selection\n</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPB_MFP13</name>
<description>PB.13 Pin Function Selection\n</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPB_MFP14</name>
<description>PB.14 Pin Function Selection\n</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPB_MFP15</name>
<description>PB.15 Pin Function Selection\n</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPB_TYPEn</name>
<description></description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIOB[15:0] I/O input Schmitt Trigger function Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIOB[15:0] I/O input Schmitt Trigger function Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPC_MFP</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPC_MFP</displayName>
<description>GPIOC Multiple Function and Input Type Control Register</description>
<addressOffset>0x38</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPC_MFP0</name>
<description>PC.0 Pin Function Selection\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPC_MFP1</name>
<description>PC.1 Pin Function Selection\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPC_MFP2</name>
<description>PC.2 Pin Function Selection\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPC_MFP3</name>
<description>PC.3 Pin Function Selection\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPC_MFP4</name>
<description>PC.4 Pin Function Selection\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPC_MFP5</name>
<description>PC.5 Pin Function Selection\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPC_MFP8</name>
<description>PC.8 Pin Function Selection\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPC_MFP9</name>
<description>PC.9 Pin Function Selection\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIOC[9] is selected to the pin PC.9</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPICLK1 (SPI1) function is selected to the pin PC.9</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPC_MFP10</name>
<description>PC.10 Pin Function Selection\n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The GPIOC[10] is selected to the pin PC.10</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MISO10 (SPI1 master input, slave output pin-0) function is selected to the pin PC.10</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPC_MFP11</name>
<description>PC.11 Pin Function Selection\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIOC[11] is selected to the pin PC.11</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MOSI10 (SPI1 master output, slave input pin-0) function is selected to the pin PC.11</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPC_MFP12</name>
<description>PC.12 Pin Function Selection\n</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPC_MFP13</name>
<description>PC.13 Pin Function Selection\n</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPC_TYPEn</name>
<description></description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIOC[15:0] I/O input Schmitt Trigger function Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIOC[15:0] I/O input Schmitt Trigger function Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPD_MFP</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPD_MFP</displayName>
<description>GPIOD Multiple Function and Input Type Control Register</description>
<addressOffset>0x3C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPD_MFP0</name>
<description>PD.0 Pin Function Selection \n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPD_MFP1</name>
<description>PD.1 Pin Function Selection\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPD_MFP2</name>
<description>PD.2 Pin Function Selection\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPD_MFP3</name>
<description>PD.3 Pin Function Selection\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPD_MFP4</name>
<description>PD.4 Pin Function Selection \n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPD_MFP5</name>
<description>PD.5 Pin Function Selection \n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPD_MFP8</name>
<description>PD.8 Pin Function Selection\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIOD[8] is selected to the pin PD8</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MOSI10 (SPI1 master output, slave input pin-0) function is selected to the pin PD8</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPD_MFP9</name>
<description>PD.9 Pin Function Selection\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPD_MFP10</name>
<description>PD.10 Pin Function Selection \n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIOD[10] is selected to the pin PD.10</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CLKO function is selected to the pin PD.10</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPD_MFP11</name>
<description>PD.11 Pin Function Selection\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIOD[11] is selected to the pin PD.11</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>/INT1 function is selected to the pin PD.11</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPD_TYPEn</name>
<description></description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIOD[15:0] I/O input Schmitt Trigger function Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIOD[15:0] I/O input Schmitt Trigger function Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPF_MFP</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPF_MFP</displayName>
<description>GPIOF Multiple Function and Input Type Control Register</description>
<addressOffset>0x44</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFF0</resetMask>
<fields>
<field>
<name>GPF_MFP0</name>
<description>PF.0 Pin Function Selection\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIOF[0] is selected to the pin PF.0</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>XT1_OUT function is selected to the pin PF.0</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPF_MFP1</name>
<description>PF.1 Pin Function Selection \n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIOF[1] is selected to the pin PF.1</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>XT1_IN function is selected to the pin PF.1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPF_MFP2</name>
<description>PF.2 Pin Function Selection\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPF_MFP3</name>
<description>PF.3 Pin Function Selection \n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GPF_TYPEn</name>
<description></description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIOF[3:0] I/O input Schmitt Trigger function Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIOF[3:0] I/O input Schmitt Trigger function Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ALT_MFP</name>
<!-- the display name is an unrestricted string. -->
<displayName>ALT_MFP</displayName>
<description>Alternative Multiple Function Pin Control Register</description>
<addressOffset>0x50</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PB10_MFP1</name>
<description>PB.10 Pin Alternate Function Selection\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PB9_MFP1</name>
<description>PB.9 Pin Alternate Function Selection\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PC0_MFP1</name>
<description>PC.0 Pin Function Selection\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PC1_MFP1</name>
<description>PC.1 Pin Alternate Function Selection\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PC2_MFP1</name>
<description>PC.2 Pin Alternate Function Selection\n</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PC3_MFP1</name>
<description>PC.3 Pin Alternate Function Selection\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PA15_MFP1</name>
<description>PA.15 Pin Alternate Function Selection\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PB12_MFP1</name>
<description>PB.12 Pin Alternate Function Selection\n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PA11_MFP1</name>
<description>PA.11 Pin Function Selection\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PA10_MFP1</name>
<description>PA.10 Pin Function Selection\n</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PB4_MFP1</name>
<description>PB.4 Pin Function Selection\n</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PB7_MFP1</name>
<description>PB.7 Pin Alternate Function Selection\n</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PB6_MFP1</name>
<description>PB.6 Pin Alternate Function Selection\n</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PB5_MFP1</name>
<description>PB. </description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PC12_MFP1</name>
<description>PC.12 Pin Function Selection\n</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PC13_MFP1</name>
<description>PC.13 Pin Function Selection\n</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PB15_MFP1</name>
<description>PB.15 Pin Alternate Function Selection\n</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PB2_MFP1</name>
<description>PB.2 Pin Alternate Function Selection\n</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PB3_MFP1</name>
<description>PB.3 Pin Alternate Function Selection\n</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PC4_MFP1</name>
<description>PC.4 Pin Function Selection\n</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PC5_MFP1</name>
<description>PC.5 Pin Function Selection\n</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ALT_MFP1</name>
<!-- the display name is an unrestricted string. -->
<displayName>ALT_MFP1</displayName>
<description>Alternative Multiple Function Pin Control Register 1</description>
<addressOffset>0x54</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PD0_MFP1</name>
<description>PD.0 Pin Function Selection \n</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD1_MFP1</name>
<description>PD.1 Pin Function Selection\n</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD2_MFP1</name>
<description>PD.2 Pin Function Selection\n</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD3_MFP1</name>
<description>PD.3 Pin Function Selection\n</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD4_MFP1</name>
<description>PD.4 Pin Function Selection \n</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD5_MFP1</name>
<description>PD.5 Pin Function Selection \n</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PF2_MFP1</name>
<description>PF.2 Pin Function Selection\n</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PF3_MFP1</name>
<description>PF.3 Pin Function Selection \n</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFP_CSR</name>
<!-- the display name is an unrestricted string. -->
<displayName>DFP_CSR</displayName>
<description>Pin Conflict Status</description>
<addressOffset>0xA0</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DFP0_CST</name>
<description>Conflict Status of PD.9\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PD.9 worked normally</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PD.9 is conflicted</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>DFP1_CST</name>
<description>Conflict Status of PD.10\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PD.10 worked normally</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PD.10 is conflicted</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>DFP2_CST</name>
<description>Conflict Status of PD.11\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PD.11 worked normally</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PD.11 is conflicted</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>DFP3_CST</name>
<description>Conflict Status of PB.4\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PB.4 worked normally</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PB.4 is conflicted</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>DFP4_CST</name>
<description>Conflict Status of PB.5\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PB.5 worked normally</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PB.5 is conflicted</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>DFP5_CST</name>
<description>Conflict Status of PB.6\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PB.6 worked normally</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PB.6 is conflicted</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>DFP6_CST</name>
<description>Conflict Status of PB.7\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PB.7 worked normally</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PB.7 is conflicted</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>GPA_IOCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPA_IOCR</displayName>
<description>GPIOA IO Control Register</description>
<addressOffset>0xC0</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPA10_DS</name>
<description>PA.10 Pin Driving Strength Selection\n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PA.10 strong driving strength mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PA.10 strong driving strength mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPA11_DS</name>
<description>PA.11 Pin Driving Strength Selection\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PA.11 strong driving strength mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PA.11 strong driving strength mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPB_IOCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPB_IOCR</displayName>
<description>GPIOB IO Control Register</description>
<addressOffset>0xC4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPB4_DS</name>
<description>PB.4 Pin Driving Strength Selection\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PB.4 strong driving strength mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PB.4 strong driving strength mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPB5_DS</name>
<description>PB.5 Pin Driving Strength Selection\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PB.5 strong driving strength mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PB.5 strong driving strength mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPB6_DS</name>
<description>PB.6 Pin Driving Strength Selection\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PB.6 strong driving strength mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PB.6 strong driving strength mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPB7_DS</name>
<description>PB.7 Pin Driving Strength Selection\n</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PB.7 strong driving strength mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PB.7 strong driving strength mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPB8_DS</name>
<description>PB.8 Pin Driving Strength Selection\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PB.8 strong driving strength mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PB.8 strong driving strength mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPB12_DS</name>
<description>PB.12 Pin Driving Strength Selection\n</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PB.12 strong driving strength mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PB.12 strong driving strength mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPB13_DS</name>
<description>PB.13 Pin Driving Strength Selection\n</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PB.13 strong driving strength mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PB.13 strong driving strength mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPB14_DS</name>
<description>PB.14 Pin Driving Strength Selection\n</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PB.14 strong driving strength mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PB.14 strong driving strength mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPD_IOCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPD_IOCR</displayName>
<description>GPIOD IO Control Register</description>
<addressOffset>0xCC</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GPD8_DS</name>
<description>PD.8 Pin Driving Strength Selection\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PD.8 strong driving strength mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PD.8 strong driving strength mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPD9_DS</name>
<description>PD.9 Pin Driving Strength Selection\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PD.9 strong driving strength mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PD.9 strong driving strength mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPD10_DS</name>
<description>PD.10 Pin Driving Strength Selection\n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PD.10 strong driving strength mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PD.10 strong driving strength mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>GPD11_DS</name>
<description>PD.11 Pin Driving Strength Selection\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PD.11 strong driving strength mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PD.11 strong driving strength mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>REGWRPROT</name>
<!-- the display name is an unrestricted string. -->
<displayName>REGWRPROT</displayName>
<description>Register Write Protect register</description>
<addressOffset>0x100</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>REGPROTDIS</name>
<description>Register Write-Protection Disable index (Read Only)\nThe Protected registers are:\nIPRSTC1: address 0x5000_0008\nBODCR: address 0x5000_0018\nPORCR: address 0x5000_0024\nPWRCON: address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear) \nAPBCLK bit[0]: address 0x5000_0208 (bit[0] is watchdog clock enabled)\nCLKSEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source select)\nCLKSEL1 bit[1:0]: address 0x5000_0214 (for watchdog clock source select)\nISPCON: address 0x5000_C000 (Flash ISP Control register)\nWTCR: address 0x4000_4000\nFATCON: address 0x5000_C018</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Write-protection Enabled for writing protected registers. Any write to the protected register is ignored</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Write-protection Disabled for writing protected registers</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>REGWRPROT</name>
<description>Register Write-Protection Code (Write Only)\nSome registers have write-protection function. Writing these registers has to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CLK</name>
<description>CLK Register Map</description>
<groupName>CLK</groupName>
<baseAddress>0x50000200</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x28</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x2C</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PWRCON</name>
<!-- the display name is an unrestricted string. -->
<displayName>PWRCON</displayName>
<description>System Power-down Control Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x00000010</resetValue>
<resetMask>0xFFFFFFF0</resetMask>
<fields>
<field>
<name>XTL12M_EN</name>
<description>External 4~24 MHz High Speed Crystal Enable (Write-protection Bit)\nThe bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external 4~24 MHz high speed crystal, this bit is set to 1 automatically\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External 4~24 MHz high speed crystal Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>External 4~24 MHz high speed crystal Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OSC22M_EN</name>
<description>Internal 22.1184 MHz High Speed Oscillator Enable (Write-protection Bit)\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal 22.1184 MHz high speed oscillator Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal 22.1184 MHz high speed oscillator Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OSC10K_EN</name>
<description>Internal 10 kHz Low Speed Oscillator Enable (Write-protection Bit)\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal 10 kHz low speed oscillator Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal 10 kHz low speed oscillator Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PD_WU_DLY</name>
<description>Enable the Wake-up Delay Counter (Write-protection Bit)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high speed oscillator.\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock cycles delay Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock cycles delay Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PD_WU_INT_EN</name>
<description>Power-down Mode Wake-up Interrupt Enable (Write-protection Bit)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PD_WU_STS</name>
<description>Power-down Mode Wake-up Interrupt Status\nSet by "Power-down wake-up event", which indicates that resume from Power-down mode" \nThe flag is set if the GPIO, USB, UART, WDT, CAN, ACMP or BOD wake-up occurred.\nWrite 1 to clear the bit to zero.\nNote: This bit works only when PD_WU_INT_EN (PWRCON[5]) set to 1.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWR_DOWN_EN</name>
<description>System Power-down Enable Bit (Write-protection Bit)\nWhen this bit is set to 1, the chip Power-down mode is enabled and chip Power-down behavior will depend on the PD_WAIT_CPU bit.\n(a) If the PD_WAIT_CPU is 0, the chip enters Power-down mode immediately after the PWR_DOWN_EN bit set.\n(b) If the PD_WAIT_CPU is 1, the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode\nWhen chip wakes up from Power-down mode, this bit is auto cleared. User needs to set this bit again for next Power-down.\nIn Power-down mode, external 4~24 MHz high speed crystal and the internal 22.1184 MHz high speed oscillator will be disabled in this mode, but the internal 10 kHz low speed oscillator is not controlled by Power-down mode.\nIn Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from the internal 10 kHz low speed oscillator.\n</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Chip operating normally or chip in Idle mode because of WFI command</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Chip entering the Power-down mode instantly or wait CPU sleep command WFI</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PD_WAIT_CPU</name>
<description>Power-down Entry Conditions Control (Write-protection Bit)\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Chip entering Power-down mode when the PWR_DOWN_EN bit is set to 1</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Chip entering Power-down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>AHBCLK</name>
<!-- the display name is an unrestricted string. -->
<displayName>AHBCLK</displayName>
<description>AHB Devices Clock Enable Control Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x0000000D</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_EN</name>
<description>PDMA Controller Clock Enable Control\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PDMA engine clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PDMA engine clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISP_EN</name>
<description>Flash ISP Controller Clock Enable Control\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Flash ISP engine clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Flash ISP engine clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APBCLK</name>
<!-- the display name is an unrestricted string. -->
<displayName>APBCLK</displayName>
<description>APB Devices Clock Enable Control Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFF0</resetMask>
<fields>
<field>
<name>WDT_EN</name>
<description>Watchdog Timer Clock Enable (Write-protection Bit)\nThis bit is the protected bit, which means programming it needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Watchdog Timer Clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Watchdog Timer Clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TMR0_EN</name>
<description>Timer0 Clock Enable\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer0 clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer0 clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TMR1_EN</name>
<description>Timer1 Clock Enable\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer1 clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer1 clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TMR2_EN</name>
<description>Timer2 Clock Enable\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer2 clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer2 clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TMR3_EN</name>
<description>Timer3 Clock Enable\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer3 clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer3 clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>FDIV_EN</name>
<description>Frequency Divider Output Clock Enable\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FDIV clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FDIV clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>I2C0_EN</name>
<description>I2C0 Clock Enable\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>I2C0 clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>I2C0 clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>I2C1_EN</name>
<description>I2C1 Clock Enable\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>I2C1 clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>I2C1 clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SPI0_EN</name>
<description>SPI0 Clock Enable\n</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI0 clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI0 clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SPI1_EN</name>
<description>SPI1 Clock Enable\n</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI1 clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI1 clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SPI2_EN</name>
<description>SPI2 Clock Enable\n</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI2 clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI2 clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>UART0_EN</name>
<description>UART0 Clock Enable\n</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART0 clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART0 clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>UART1_EN</name>
<description>UART1 Clock Enable\n</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART1 clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART1 clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWM01_EN</name>
<description>PWM_01 Clock Enable\n</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PWM01 clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PWM01 clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWM23_EN</name>
<description>PWM_23 Clock Enable\n</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PWM23 clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PWM23 clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>USBD_EN</name>
<description>USB 2.0 FS Device Controller Clock Enable\n</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>USB clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>USB clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ADC_EN</name>
<description>Analog-Digital-Converter (ADC) Clock Enable\n</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ADC clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ADC clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>I2S_EN</name>
<description>I2S Clock Enable\n</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>I2S Clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>I2S Clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PS2_EN</name>
<description>PS/2 Clock Enable\n</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PS/2 clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PS/2 clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLKSTATUS</name>
<!-- the display name is an unrestricted string. -->
<displayName>CLKSTATUS</displayName>
<description>Clock status monitor Register</description>
<addressOffset>0xC</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFF00</resetMask>
<fields>
<field>
<name>XTL12M_STB</name>
<description>External 4~24 MHz High Speed Crystal Clock Source Stable Flag\nThis is read only bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External 4~24 MHz high speed crystal clock is not stable or disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>External 4~24 MHz high speed crystal clock is stable</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PLL_STB</name>
<description>Internal PLL Clock Source Stable Flag\nThis is read only bit.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal PLL clock is not stable or disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal PLL clock is stable</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OSC10K_STB</name>
<description>Internal 10 kHz Low Speed Oscillator Clock Source Stable Flag\nThis is read only bit.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal 10 kHz low speed oscillator clock is not stable or disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal 10 kHz low speed oscillator clock is stable</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OSC22M_STB</name>
<description>Internal 22.1184 MHz High Speed Oscillator Clock Source Stable Flag\nThis is read only bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Internal 22.1184 MHz high speed oscillator clock is not stable or disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal 22.1184 MHz high speed oscillator clock is stable</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CLK_SW_FAIL</name>
<description>Clock Switching Fail Flag (Write-protection Bit)\nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nWrite 1 to clear the bit to zero.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock switching success</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock switching failed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLKSEL0</name>
<!-- the display name is an unrestricted string. -->
<displayName>CLKSEL0</displayName>
<description>Clock Source Select Control Register 0</description>
<addressOffset>0x10</addressOffset>
<access>read-write</access>
<resetValue>0x00000030</resetValue>
<resetMask>0xFFFFFFF0</resetMask>
<fields>
<field>
<name>HCLK_S</name>
<description>HCLK Clock Source Selection (Write-protection Bits)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turn on\nThe 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.\nThese bits are protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock source from external 4~24 MHz high speed crystal clock</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock source from PLL clock/2</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Clock source from PLL clock</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Clock source from internal 10 kHz low speed oscillator clock</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>Clock source from internal 22.1184 MHz high speed oscillator clock</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>STCLK_S</name>
<description>Cortex_M0 SysTick Clock Source Selection (Write-protection Bits)\n</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock source from external 4~24 MHz high speed crystal clock</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Clock source from external 4~24 MHz high speed crystal clock/2</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Clock source from HCLK/2</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>Clock source from internal 22.1184 MHz high speed oscillator clock/2</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLKSEL1</name>
<!-- the display name is an unrestricted string. -->
<displayName>CLKSEL1</displayName>
<description>Clock Source Select Control Register 1</description>
<addressOffset>0x14</addressOffset>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WDT_S</name>
<description>Watchdog Timer Clock Source Selection (Write-protection Bits)\nThese bits are protected bits and programming this needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>2</name>
<description>Clock source from HCLK/2048 clock</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Clock source from internal 10 kHz low speed oscillator clock</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ADC_S</name>
<description>ADC Clock Source Selection\n</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock source from external 4~24 MHz high speed crystal clock</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock source from PLL clock</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Clock source from HCLK</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Clock source from internal 22.1184 MHz high speed oscillator clock</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SPI0_S</name>
<description>SPI0 Clock Source Selection\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock source from PLL clock</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock source from HCLK</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SPI1_S</name>
<description>SPI1 Clock Source Selection\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock source from PLL clock</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock source from HCLK</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SPI2_S</name>
<description>SPI2 Clock Source Selection\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock source from PLL clock</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock source from HCLK</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TMR0_S</name>
<description>TIMER0 Clock Source Selection\n</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock source from external 4~24 MHz high speed crystal clock</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Clock source from HCLK</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Clock source from external clock source TM0</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>4</name>
<description>Clock source from internal 10 kHz low speed oscillator clock</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>Clock source from internal 22.1184 MHz high speed oscillator clock</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TMR1_S</name>
<description>TIMER1 Clock Source Selection\n</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock source from external 4~24 MHz high speed crystal clock</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Clock source from HCLK</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Clock source from external clock source TM1</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>4</name>
<description>Clock source from internal 10 kHz low speed oscillator clock</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>Clock source from internal 22.1184 MHz high speed oscillator clock</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TMR2_S</name>
<description>TIMER2 Clock Source Selection\n</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock source from external 4~24 MHz high speed crystal clock</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Clock source from HCLK</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Clock source from external clock source TM2</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>4</name>
<description>Clock source from internal 10 kHz low speed oscillator clock</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>Clock source from internal 22.1184 MHz high speed oscillator clock</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TMR3_S</name>
<description>TIMER3 Clock Source Selection\n</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock source from external 4~24 MHz high speed crystal clock</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Clock source from HCLK</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>4</name>
<description>Clock source from internal 10 kHz low speed oscillator clock</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>Clock source from internal 22.1184 MHz high speed oscillator clock</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>UART_S</name>
<description>UART Clock Source Selection\n</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock source from external 4~24 MHz high speed crystal clock</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock source from PLL clock</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Clock source from internal 22.1184 MHz high speed oscillator clock</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWM01_S</name>
<description>PWM0 and PWM1 Clock Source Select Bit [1:0]\nPWM0 and PWM1 use the same Engine clock source, and both of them use the same prescaler\nThe Engine clock source of PWM0 and PWM1 is defined by PWM01_S[2:0] and this field is combined by CLKSEL2[8] and CLKSEL1[29:28].\n</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWM23_S</name>
<description>PWM2 and PWM3 Clock Source Select Bit [1:0]\nPWM2 and PWM3 use the same Engine clock source, and both of them use the same prescaler.\nThe Engine clock source of PWM2 and PWM3 is defined by PWM23_S[2:0] and this field is combined by CLKSEL2[9] and CLKSEL1[31:30].\n</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLKDIV</name>
<!-- the display name is an unrestricted string. -->
<displayName>CLKDIV</displayName>
<description>Clock Divider Number Register</description>
<addressOffset>0x18</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>HCLK_N</name>
<description>HCLK Clock Divide Number from HCLK Clock Source\n</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USB_N</name>
<description>USB Clock Divide Number from PLL Clock\n</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UART_N</name>
<description>UART Clock Divide Number from UART Clock Source\n</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ADC_N</name>
<description>ADC Clock Divide Number from ADC Clock Source\n</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CLKSEL2</name>
<!-- the display name is an unrestricted string. -->
<displayName>CLKSEL2</displayName>
<description>Clock Source Select Control Register 2</description>
<addressOffset>0x1C</addressOffset>
<access>read-write</access>
<resetValue>0x000000FF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>I2S_S</name>
<description>I2S Clock Source Selection\n</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock source from external 4~24 MHz high speed crystal clock</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock source from PLL clock</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Clock source from HCLK</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Clock source from internal 22.1184 MHz high speed oscillator clock</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>FRQDIV_S</name>
<description>Clock Divider Clock Source Selection\n</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock source from external 4~24 MHz high speed crystal clock</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reserved</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Clock source from HCLK</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Clock source from internal 22.1184 MHz high speed oscillator clock</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWM01_S</name>
<description>PWM0 and PWM1 Clock Source Select Bit [2]\nPWM0 and PWM1 use the same Engine clock source, and both of them use the same prescaler.\nThe Engine clock source of PWM0 and PWM1 is defined by PWM01_S[2:0] and this field is combined by CLKSEL2[8] and CLKSEL1[29:28].\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWM23_S</name>
<description>PWM2 and PWM3 Clock Source Select Bit [2]\nPWM2 and PWM3 use the same Engine clock source, and both of them use the same prescaler.\nThe Engine clock source of PWM2 and PWM3 is defined by PWM23_S[2:0] and this field is combined by CLKSEL2[9] and CLKSEL1[31:30].\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WWDT_S</name>
<description>Windowed-Watchdog Timer Clock Source Selection (Write-protection Bits)\n</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>2</name>
<description>Clock source from HCLK/2048 clock</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Clock source from internal 10 kHz low speed oscillator clock</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PLLCON</name>
<!-- the display name is an unrestricted string. -->
<displayName>PLLCON</displayName>
<description>PLL Control Register</description>
<addressOffset>0x20</addressOffset>
<access>read-write</access>
<resetValue>0x0005C22E</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FB_DV</name>
<description>PLL Feedback Divider Control Pins\nRefer to the formulas below the table.</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IN_DV</name>
<description>PLL Input Divider Control Pins\nRefer to the formulas below the table.</description>
<bitOffset>9</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OUT_DV</name>
<description>PLL Output Divider Control Pins\nRefer to the formulas below the table.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PD</name>
<description>Power-down Mode\nIf the PWR_DOWN_EN bit set to 1 in PWRCON register, the PLL will also enter Power-down mode.\n</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PLL is in Normal mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PLL is in Power-down mode (default)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BP</name>
<description>PLL Bypass Control\n</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PLL is in Normal mode (default)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PLL clock output is the same as clock input (XTALin)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OE</name>
<description>PLL OE (FOUT Enable) Pin Control\n</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PLL FOUT Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PLL FOUT is fixed low</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PLL_SRC</name>
<description>PLL Source Clock Selection\n</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PLL source clock from external 4~24 MHz high speed crystal</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PLL source clock from internal 22.1184 MHz high speed oscillator</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FRQDIV</name>
<!-- the display name is an unrestricted string. -->
<displayName>FRQDIV</displayName>
<description>Frequency Divider Control Register</description>
<addressOffset>0x24</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FSEL</name>
<description>Divider Output Frequency Select Bits\nThe formula of output frequency is:\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0].</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DIVIDER_EN</name>
<description>Frequency Divider Enable Bit\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Frequency Divider Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Frequency Divider Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APBDIV</name>
<!-- the display name is an unrestricted string. -->
<displayName>APBDIV</displayName>
<description>APB Divider Control Register</description>
<addressOffset>0x2C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>APBDIV</name>
<description>APB Divider Enable Bit\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FMC</name>
<description>FMC Register Map</description>
<groupName>FMC</groupName>
<baseAddress>0x5000C000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x1C</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>ISPCON</name>
<!-- the display name is an unrestricted string. -->
<displayName>ISPCON</displayName>
<description>ISP Control Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISPEN</name>
<description>ISP Enable (Write-protection Bit)\nISP function enable bit. Set this bit to enable ISP function.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ISP function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ISP function Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BS</name>
<description>Boot Select (Write-protection Bit)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Boot from APROM</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Boot from LDROM</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>APUEN</name>
<description>APROM Update Enable (Write-protection Bit)\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>APROM cannot be updated when the chip runs in APROM</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>APROM can be updated when the chip runs in APROM</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CFGUEN</name>
<description>Enable Config-bits Update by ISP (Write-protection Bit)\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ISP Disabled to update config-bits</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ISP Enabled to update config-bits</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>LDUEN</name>
<description>LDROM Update Enable (Write-protection Bit)\nLDROM update enable bit.\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>LDROM cannot be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>LDROM can be updated</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISPFF</name>
<description>ISP Fail Flag (Write-protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Destination address is illegal, such as over an available range.\nWrite 1 to clear.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ISPADR</name>
<!-- the display name is an unrestricted string. -->
<displayName>ISPADR</displayName>
<description>ISP Address Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISPADR</name>
<description>ISP Address\nThe NuMicro( NUC123 Series is equipped with an embedded flash, and it supports word program only. ISPADR[1:0] must be kept 00b for ISP operation.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ISPDAT</name>
<!-- the display name is an unrestricted string. -->
<displayName>ISPDAT</displayName>
<description>ISP Data Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISPDAT</name>
<description>ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ISPCMD</name>
<!-- the display name is an unrestricted string. -->
<displayName>ISPCMD</displayName>
<description>ISP Command Register</description>
<addressOffset>0xC</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISPCMD</name>
<description>ISP Command\n</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ISPTRG</name>
<!-- the display name is an unrestricted string. -->
<displayName>ISPTRG</displayName>
<description>ISP Trigger Control Register</description>
<addressOffset>0x10</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISPGO</name>
<description>ISP Start Trigger\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ISP operation is finished</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ISP is progressed</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DFBADR</name>
<!-- the display name is an unrestricted string. -->
<displayName>DFBADR</displayName>
<description>Data Flash Start Address</description>
<addressOffset>0x14</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>DFBADR</name>
<description>Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nWhen DFVSEN is set to 0, the data flash is shared with APROM. The data flash size is defined by user configuration and the content of this register is loaded from Config1.\nWhen DFVSEN is set to 1, the data flash size is fixed as 4K and the start address can be read from this register is fixed at 0x0001_F000.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>FATCON</name>
<!-- the display name is an unrestricted string. -->
<displayName>FATCON</displayName>
<description>Flash Access Time Control Register</description>
<addressOffset>0x18</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>LFOM</name>
<description>Low Frequency Optimization Mode (Write-protection Bit)\nWhen chip operation frequency is lower than 25 MHz, chip can work more efficiently by setting this bit to 1\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low Frequency Optimization mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Low Frequency Optimization mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>MFOM</name>
<description>Middle Frequency Optimization Mode (Write-protection Bit)\nWhen chip operation frequency is lower than 50 MHz, chip can work more efficiently by setting this bit to 1\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Middle Frequency Optimization mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Middle Frequency Optimization mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>USB</name>
<description>USB Register Map</description>
<groupName>USB</groupName>
<baseAddress>0x40060000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x1C</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x90</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0xA4</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x500</offset>
<size>0x80</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>USB_INTEN</name>
<!-- the display name is an unrestricted string. -->
<displayName>USB_INTEN</displayName>
<description>USB Interrupt Enable Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BUS_IE</name>
<description>Bus Event Interrupt Enable\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>BUS event interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>BUS event interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>USB_IE</name>
<description>USB Event Interrupt Enable\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>USB event interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>USB event interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>FLDET_IE</name>
<description>Floating Detected Interrupt Enable\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Floating detect Interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Floating detect Interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>WAKEUP_IE</name>
<description>USB Wake-up Interrupt Enable\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Wake-up Interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Wake-up Interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>WAKEUP_EN</name>
<description>Wake-up Function Enable\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>USB wake-up function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>USB wake-up function Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>INNAK_EN</name>
<description>Active NAK Function and its Status in IN Token\n</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>NAK status wasn't updated into the endpoint status register when it was set to 0. It also disables the interrupt event when device responds NAK after receiving IN token</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>NAK status is updated into the endpoint status register, USB_EPSTS, when it is set to 1 and there is NAK response in IN token. It also enables the interrupt event when the device responds NAK after receiving IN token</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>USB_INTSTS</name>
<!-- the display name is an unrestricted string. -->
<displayName>USB_INTSTS</displayName>
<description>USB Interrupt Event Status Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BUS_STS</name>
<description>BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No BUS event occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus event occurred; check USB_ATTR[3:0] to know which kind of bus event was occurred, cleared by writing 1 to USB_INTSTS[0]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>USB_STS</name>
<description>USB event Interrupt Status\nThe USB event includes the Setup Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No USB event occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[1] or EPSTS0~5 and SETUP (USB_INTSTS[31])</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>FLDET_STS</name>
<description>Floating Detected Interrupt Status\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>There is not attached/detached event in the USB</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>There is attached/detached event in the USB bus and it is cleared by writing 1 to USB_INTSTS[2]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>WAKEUP_STS</name>
<description>Wake-up Interrupt Status\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No Wake-up event occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Wake-up event occurred, cleared by writing 1 to USB_INTSTS[3]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>EPEVT0</name>
<description>Endpoint 0's USB Event Status\n</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No event occurred on Endpoint 0</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[16] or USB_INTSTS[1]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>EPEVT1</name>
<description>Endpoint 1's USB Event Status\n</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No event occurred on Endpoint 1</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[17] or USB_INTSTS[1]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>EPEVT2</name>
<description>Endpoint 2's USB Event Status\n</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No event occurred on Endpoint 2</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[18] or USB_INTSTS[1]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>EPEVT3</name>
<description>Endpoint 3's USB Event Status\n</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No event occurred on Endpoint 3</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[19] or USB_INTSTS[1]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>EPEVT4</name>
<description>Endpoint 4's USB Event Status\n</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No event occurred on Endpoint 4</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[20] or USB_INTSTS[1]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>EPEVT5</name>
<description>Endpoint 5's USB Event Status\n</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No event occurred on Endpoint 5</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[21] or USB_INTSTS[1]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>EPEVT6</name>
<description>Endpoint 6's USB Event Status\n</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No event occurred on Endpoint 6</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>USB event occurred on Endpoint 6, check USB_EPSTS[28:26] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[22] or USB_INTSTS[1]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>EPEVT7</name>
<description>Endpoint 7's USB Event Status\n</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No event occurred in endpoint 7</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>USB event occurred on Endpoint 7, check USB_EPSTS[31:29] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[23] or USB_INTSTS[1]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SETUP</name>
<description>Setup Event Status\n</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No Setup event</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Setup event occurred, and cleared by writing 1 to USB_INTSTS[31]</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>USB_FADDR</name>
<!-- the display name is an unrestricted string. -->
<displayName>USB_FADDR</displayName>
<description>USB Device Function Address Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FADDR</name>
<description>USB device's Function Address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>USB_EPSTS</name>
<!-- the display name is an unrestricted string. -->
<displayName>USB_EPSTS</displayName>
<description>USB Endpoint Status Register</description>
<addressOffset>0xC</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OVERRUN</name>
<description>Overrun\nIt indicates that the received data is over the maximum payload number or not.\n</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No overrun</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Out data is more than the Max Payload in MXPLD register or the Setup data is more than 8 Bytes</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>EPSTS0</name>
<description>Endpoint 0 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>In ACK</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>In NAK</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Out Packet Data0 ACK</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Setup ACK</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>6</name>
<description>Out Packet Data1 ACK</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>Isochronous transfer end</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>EPSTS1</name>
<description>Endpoint 1 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n</description>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>In ACK</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>In NAK</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Out Packet Data0 ACK</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Setup ACK</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>6</name>
<description>Out Packet Data1 ACK</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>Isochronous transfer end</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>EPSTS2</name>
<description>Endpoint 2 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n</description>
<bitOffset>14</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>In ACK</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>In NAK</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Out Packet Data0 ACK</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Setup ACK</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>6</name>
<description>Out Packet Data1 ACK</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>Isochronous transfer end</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>EPSTS3</name>
<description>Endpoint 3 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>In ACK</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>In NAK</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Out Packet Data0 ACK</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Setup ACK</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>6</name>
<description>Out Packet Data1 ACK</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>Isochronous transfer end</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>EPSTS4</name>
<description>Endpoint 4 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>In ACK</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>In NAK</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Out Packet Data0 ACK</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Setup ACK</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>6</name>
<description>Out Packet Data1 ACK</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>Isochronous transfer end</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>EPSTS5</name>
<description>Endpoint 5 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n</description>
<bitOffset>23</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>In ACK</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>In NAK</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Out Packet Data0 ACK</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Setup ACK</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>6</name>
<description>Out Packet Data1 ACK</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>Isochronous transfer end</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>EPSTS6</name>
<description>Endpoint 6 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n</description>
<bitOffset>26</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>In ACK</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>In NAK</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Out Packet Data0 ACK</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Setup ACK</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>6</name>
<description>Out Packet Data1 ACK</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>Isochronous transfer end</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>EPSTS7</name>
<description>Endpoint 7 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n</description>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>In ACK</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>In NAK</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Out Packet Data0 ACK</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Setup ACK</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>6</name>
<description>Out Packet Data1 ACK</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>Isochronous transfer end</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>USB_ATTR</name>
<!-- the display name is an unrestricted string. -->
<displayName>USB_ATTR</displayName>
<description>USB Bus Status and Attribution Register</description>
<addressOffset>0x10</addressOffset>
<access>read-write</access>
<resetValue>0x00000040</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>USBRST</name>
<description>USB Reset Status\nIt is a read only bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus reset</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus reset when SE0 (single-ended 0) more than 2.5 us</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SUSPEND</name>
<description>Suspend Status\nIt is a read only bit.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus suspend</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus idle more than 3ms, either cable is plugged off or host is sleeping</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RESUME</name>
<description>Resume Status\nIt is a read only bit.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus resume</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Resume from suspend</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TIME_OUT</name>
<description>Time Out Status\nIt is a read only bit.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No time-out</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>No Bus response more than 18 bits time</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PHY_EN</name>
<description>PHY Transceiver Function Enable\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PHY transceiver function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PHY transceiver function Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RWAKEUP</name>
<description>Remote Wake-up\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Release the USB bus from K state</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Force USB bus to K (USB_DP low, USB_DM: high) state, used for remote wake-up</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>USB_EN</name>
<description>USB Controller Enable\n</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>USB Controller Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>USB Controller Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DPPU_EN</name>
<description>Pull-up resistor on USB_DP enable\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>the pull-up resistor in USB_DP bus Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Pull-up resistor in USB_DP bus Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWRDN</name>
<description>Power-down PHY Transceiver, Low Active\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Power-down related circuit of PHY transceiver</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Turn-on related circuit of PHY transceiver</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BYTEM</name>
<description>CPU access USB SRAM Size Mode Selection\n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Word Mode: The size of the transfer from CPU to USB SRAM can be Word only</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Byte Mode: The size of the transfer from CPU to USB SRAM can be Byte only</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>USB_FLDET</name>
<!-- the display name is an unrestricted string. -->
<displayName>USB_FLDET</displayName>
<description>USB Floating Detected Register</description>
<addressOffset>0x14</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FLDET</name>
<description>Device Floating Detected\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Controller isn't attached to the USB host</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Controller is attached to the BUS</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>USB_BUFSEG</name>
<!-- the display name is an unrestricted string. -->
<displayName>USB_BUFSEG</displayName>
<description>Setup Token Buffer Segmentation Register</description>
<addressOffset>0x18</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BUFSEG</name>
<description>It is used to indicate the offset address for the Setup token with the USB SRAM starting address. The effective starting address is:\nUSB_SRAM address + { BUFSEG[8:3], 3'b000} \nNote: It is used for Setup token only.</description>
<bitOffset>3</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>USB_DRVSE0</name>
<!-- the display name is an unrestricted string. -->
<displayName>USB_DRVSE0</displayName>
<description>USB Drive SE0 Control Register</description>
<addressOffset>0x90</addressOffset>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DRVSE0</name>
<description>Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_DP and USB_DM) are being pulled low.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>None</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Force USB PHY transceiver to drive SE0</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>USB_PDMA</name>
<!-- the display name is an unrestricted string. -->
<displayName>USB_PDMA</displayName>
<description>USB PDMA Control Register</description>
<addressOffset>0xA4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_RW</name>
<description>PDMA_RW\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The PDMA will read data from memory to USB buffer</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The PDMA will read data from USB buffer to memory</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PDMA_EN</name>
<description>PDMA Function Enable\nThis bit will be automatically cleared after PDMA transfer done.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The PDMA function is not active</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The PDMA function in USB is active</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>USB_BUFSEG0</name>
<!-- the display name is an unrestricted string. -->
<displayName>USB_BUFSEG0</displayName>
<description>Endpoint 0 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible.</description>
<addressOffset>0x500</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BUFSEGx</name>
<description>It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is:\nUSB_SRAM address + { BUFSEG[8:3], 3'b000}\nRefer to section 5.4.4.7 for the endpoint SRAM structure and its description.</description>
<bitOffset>3</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>USB_MXPLD0</name>
<!-- the display name is an unrestricted string. -->
<displayName>USB_MXPLD0</displayName>
<description>Endpoint 0 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible.</description>
<addressOffset>0x504</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MXPLD</name>
<description>Maximal Payload\nIt is used to define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It is also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.\n(1) When the register is written by CPU, \nFor IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.\nFor OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.\n(2) When the register is read by CPU,\nFor IN token, the value of MXPLD indicates the data length be transmitted to host\nFor OUT token, the value of MXPLD indicates the actual data length receiving from host.\nNote: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>USB_CFG0</name>
<!-- the display name is an unrestricted string. -->
<displayName>USB_CFG0</displayName>
<description>Endpoint 0 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible.</description>
<addressOffset>0x508</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>EP_NUM</name>
<description>Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint.</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ISOCH</name>
<description>Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint, no handshake.\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No Isochronous endpoint</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Isochronous endpoint</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>STATE</name>
<description>Endpoint STATE\n</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Endpoint Disabled</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Out endpoint</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>IN endpoint</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Undefined</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DSQ_SYNC</name>
<description>Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the following IN token transaction. H/W will toggle automatically in IN token base on the bit.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>DATA0 PID</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>DATA1 PID</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CSTALL</name>
<description>Clear STALL Response\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Device Disabled to clear the STALL handshake in the setup stage</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clear the device to respond STALL handshake in the setup stage</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>USB_CFGP0</name>
<!-- the display name is an unrestricted string. -->
<displayName>USB_CFGP0</displayName>
<description>Endpoint 0 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible.</description>
<addressOffset>0x50C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLRRDY</name>
<description>Clear Ready\nWhen the MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start, user can set this bit to 1 to turn it off and it is automatically cleared to 0.\nFor IN token, writing '1' is used to clear the IN token had ready to transmit the data to USB.\nFor OUT token, writing '1' is used to clear the OUT token had ready to receive the data from USB.\nThis bit is written 1 only and is always 0 when it was read back.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SSTALL</name>
<description>Set STALL\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Device Disabled to respond STALL</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Set the device to respond STALL automatically</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register derivedFrom="USB_BUFSEG0">
<name>USB_BUFSEG1</name>
<displayName>USB_BUFSEG1</displayName>
<description>Endpoint 1 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible.</description>
<addressOffset>0x510</addressOffset>
</register>
<register derivedFrom="USB_MXPLD0">
<name>USB_MXPLD1</name>
<displayName>USB_MXPLD1</displayName>
<description>Endpoint 1 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible.</description>
<addressOffset>0x514</addressOffset>
</register>
<register derivedFrom="USB_CFG0">
<name>USB_CFG1</name>
<displayName>USB_CFG1</displayName>
<description>Endpoint 1 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible.</description>
<addressOffset>0x518</addressOffset>
</register>
<register derivedFrom="USB_CFGP0">
<name>USB_CFGP1</name>
<displayName>USB_CFGP1</displayName>
<description>Endpoint 1 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible.</description>
<addressOffset>0x51C</addressOffset>
</register>
<register derivedFrom="USB_BUFSEG0">
<name>USB_BUFSEG2</name>
<displayName>USB_BUFSEG2</displayName>
<description>Endpoint 2 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible.</description>
<addressOffset>0x520</addressOffset>
</register>
<register derivedFrom="USB_MXPLD0">
<name>USB_MXPLD2</name>
<displayName>USB_MXPLD2</displayName>
<description>Endpoint 2 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible.</description>
<addressOffset>0x524</addressOffset>
</register>
<register derivedFrom="USB_CFG0">
<name>USB_CFG2</name>
<displayName>USB_CFG2</displayName>
<description>Endpoint 2 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible.</description>
<addressOffset>0x528</addressOffset>
</register>
<register derivedFrom="USB_CFGP0">
<name>USB_CFGP2</name>
<displayName>USB_CFGP2</displayName>
<description>Endpoint 2 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible.</description>
<addressOffset>0x52C</addressOffset>
</register>
<register derivedFrom="USB_BUFSEG0">
<name>USB_BUFSEG3</name>
<displayName>USB_BUFSEG3</displayName>
<description>Endpoint 3 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible.</description>
<addressOffset>0x530</addressOffset>
</register>
<register derivedFrom="USB_MXPLD0">
<name>USB_MXPLD3</name>
<displayName>USB_MXPLD3</displayName>
<description>Endpoint 3 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible.</description>
<addressOffset>0x534</addressOffset>
</register>
<register derivedFrom="USB_CFG0">
<name>USB_CFG3</name>
<displayName>USB_CFG3</displayName>
<description>Endpoint 3 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible.</description>
<addressOffset>0x538</addressOffset>
</register>
<register derivedFrom="USB_CFGP0">
<name>USB_CFGP3</name>
<displayName>USB_CFGP3</displayName>
<description>Endpoint 3 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible.</description>
<addressOffset>0x53C</addressOffset>
</register>
<register derivedFrom="USB_BUFSEG0">
<name>USB_BUFSEG4</name>
<displayName>USB_BUFSEG4</displayName>
<description>Endpoint 4 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible.</description>
<addressOffset>0x540</addressOffset>
</register>
<register derivedFrom="USB_MXPLD0">
<name>USB_MXPLD4</name>
<displayName>USB_MXPLD4</displayName>
<description>Endpoint 4 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible.</description>
<addressOffset>0x544</addressOffset>
</register>
<register derivedFrom="USB_CFG0">
<name>USB_CFG4</name>
<displayName>USB_CFG4</displayName>
<description>Endpoint 4 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible.</description>
<addressOffset>0x548</addressOffset>
</register>
<register derivedFrom="USB_CFGP0">
<name>USB_CFGP4</name>
<displayName>USB_CFGP4</displayName>
<description>Endpoint 4 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible.</description>
<addressOffset>0x54C</addressOffset>
</register>
<register derivedFrom="USB_BUFSEG0">
<name>USB_BUFSEG5</name>
<displayName>USB_BUFSEG5</displayName>
<description>Endpoint 5 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible.</description>
<addressOffset>0x550</addressOffset>
</register>
<register derivedFrom="USB_MXPLD0">
<name>USB_MXPLD5</name>
<displayName>USB_MXPLD5</displayName>
<description>Endpoint 5 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible.</description>
<addressOffset>0x554</addressOffset>
</register>
<register derivedFrom="USB_CFG0">
<name>USB_CFG5</name>
<displayName>USB_CFG5</displayName>
<description>Endpoint 5 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible.</description>
<addressOffset>0x558</addressOffset>
</register>
<register derivedFrom="USB_CFGP0">
<name>USB_CFGP5</name>
<displayName>USB_CFGP5</displayName>
<description>Endpoint 5 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible.</description>
<addressOffset>0x55C</addressOffset>
</register>
<register derivedFrom="USB_BUFSEG0">
<name>USB_BUFSEG6</name>
<displayName>USB_BUFSEG6</displayName>
<description>Endpoint 6 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible.</description>
<addressOffset>0x560</addressOffset>
</register>
<register derivedFrom="USB_MXPLD0">
<name>USB_MXPLD6</name>
<displayName>USB_MXPLD6</displayName>
<description>Endpoint 6 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible.</description>
<addressOffset>0x564</addressOffset>
</register>
<register derivedFrom="USB_CFG0">
<name>USB_CFG6</name>
<displayName>USB_CFG6</displayName>
<description>Endpoint 6 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible.</description>
<addressOffset>0x568</addressOffset>
</register>
<register derivedFrom="USB_CFGP0">
<name>USB_CFGP6</name>
<displayName>USB_CFGP6</displayName>
<description>Endpoint 6 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible.</description>
<addressOffset>0x56C</addressOffset>
</register>
<register derivedFrom="USB_BUFSEG0">
<name>USB_BUFSEG7</name>
<displayName>USB_BUFSEG7</displayName>
<description>Endpoint 7 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible.</description>
<addressOffset>0x570</addressOffset>
</register>
<register derivedFrom="USB_MXPLD0">
<name>USB_MXPLD7</name>
<displayName>USB_MXPLD7</displayName>
<description>Endpoint 7 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible.</description>
<addressOffset>0x574</addressOffset>
</register>
<register derivedFrom="USB_CFG0">
<name>USB_CFG7</name>
<displayName>USB_CFG7</displayName>
<description>Endpoint 7 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible.</description>
<addressOffset>0x578</addressOffset>
</register>
<register derivedFrom="USB_CFGP0">
<name>USB_CFGP7</name>
<displayName>USB_CFGP7</displayName>
<description>Endpoint 7 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible.</description>
<addressOffset>0x57C</addressOffset>
</register>
</registers>
</peripheral>
<peripheral>
<name>GP</name>
<description>GP Register Map</description>
<groupName>GP</groupName>
<baseAddress>0x50004000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x24</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x40</offset>
<size>0x24</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x80</offset>
<size>0x24</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0xC0</offset>
<size>0x24</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x140</offset>
<size>0x24</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x180</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x228</offset>
<size>0x90</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x2C0</offset>
<size>0x30</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x340</offset>
<size>0x10</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>GPIOA_PMD</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOA_PMD</displayName>
<description>GPIO Port A Pin I/O Mode Control</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PMD10</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD11</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD12</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD13</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD14</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD15</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOA_OFFD</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOA_OFFD</displayName>
<description>GPIO Port A Pin OFF Digital Enable</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OFFD10</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD11</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD12</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD13</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD14</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD15</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOA_DOUT</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOA_DOUT</displayName>
<description>GPIO Port A Data Output Value</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DOUT10</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT11</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT12</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT13</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT14</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT15</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOA_DMASK</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOA_DMASK</displayName>
<description>GPIO Port A Data Output Write Mask</description>
<addressOffset>0xC</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMASK10</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK11</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK12</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK13</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK14</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK15</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOA_PIN</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOA_PIN</displayName>
<description>GPIO Port A Pin Value</description>
<addressOffset>0x10</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFF0000</resetMask>
<fields>
<field>
<name>PIN10</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN11</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN12</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN13</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN14</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN15</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>GPIOA_DBEN</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOA_DBEN</displayName>
<description>GPIO Port A De-bounce Enable</description>
<addressOffset>0x14</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DBEN10</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN11</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN12</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN13</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN14</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN15</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOA_IMD</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOA_IMD</displayName>
<description>GPIO Port A Interrupt Mode Control</description>
<addressOffset>0x18</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IMD10</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD11</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD12</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD13</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD14</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD15</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOA_IEN</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOA_IEN</displayName>
<description>GPIO Port A Interrupt Enable</description>
<addressOffset>0x1C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IF_EN10</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN11</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN12</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN13</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN14</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN15</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN10</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN11</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN12</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN13</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN14</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN15</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOA_ISRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOA_ISRC</displayName>
<description>GPIO Port A Interrupt Source Flag</description>
<addressOffset>0x20</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISRC10</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC11</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC12</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC13</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC14</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC15</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOB_PMD</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOB_PMD</displayName>
<description>GPIO Port B Pin I/O Mode Control</description>
<addressOffset>0x40</addressOffset>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PMD0</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD1</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD2</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD3</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD4</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD5</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD6</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD7</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD8</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD9</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD10</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD12</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD13</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD14</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD15</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOB_OFFD</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOB_OFFD</displayName>
<description>GPIO Port B Pin OFF Digital Enable</description>
<addressOffset>0x44</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OFFD0</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD1</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD2</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD3</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD4</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD5</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD6</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD7</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD8</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD9</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD10</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD12</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD13</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD14</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD15</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOB_DOUT</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOB_DOUT</displayName>
<description>GPIO Port B Data Output Value</description>
<addressOffset>0x48</addressOffset>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DOUT0</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT1</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT2</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT3</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT4</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT5</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT6</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT7</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT8</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT9</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT10</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT12</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT13</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT14</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT15</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOB_DMASK</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOB_DMASK</displayName>
<description>GPIO Port B Data Output Write Mask</description>
<addressOffset>0x4C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMASK0</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK1</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK2</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK3</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK4</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK5</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK6</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK7</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK8</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK9</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK10</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK12</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK13</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK14</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK15</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOB_PIN</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOB_PIN</displayName>
<description>GPIO Port B Pin Value</description>
<addressOffset>0x50</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFF0000</resetMask>
<fields>
<field>
<name>PIN0</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN1</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN2</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN3</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN4</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN5</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN6</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN7</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN8</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN9</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN10</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN12</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN13</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN14</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN15</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>GPIOB_DBEN</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOB_DBEN</displayName>
<description>GPIO Port B De-bounce Enable</description>
<addressOffset>0x54</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DBEN0</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN1</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN2</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN3</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN4</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN5</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN6</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN7</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN8</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN9</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN10</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN12</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN13</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN14</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN15</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOB_IMD</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOB_IMD</displayName>
<description>GPIO Port B Interrupt Mode Control</description>
<addressOffset>0x58</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IMD0</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD1</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD2</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD3</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD4</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD5</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD6</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD7</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD8</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD9</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD10</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD12</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD13</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD14</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD15</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOB_IEN</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOB_IEN</displayName>
<description>GPIO Port B Interrupt Enable</description>
<addressOffset>0x5C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IF_EN0</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN1</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN2</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN3</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN4</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN5</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN6</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN7</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN8</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN9</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN10</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN12</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN13</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN14</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN15</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN0</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN1</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN2</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN3</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN4</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN5</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN6</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN7</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN8</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN9</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN10</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN12</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN13</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN14</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN15</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOB_ISRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOB_ISRC</displayName>
<description>GPIO Port B Interrupt Source Flag</description>
<addressOffset>0x60</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISRC0</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC1</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC2</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC3</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC4</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC5</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC6</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC7</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC8</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC9</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC10</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC12</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC13</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC14</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC15</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOC_PMD</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOC_PMD</displayName>
<description>GPIO Port C Pin I/O Mode Control</description>
<addressOffset>0x80</addressOffset>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PMD0</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD1</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD2</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD3</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD4</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD5</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD8</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD9</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD10</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD11</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD12</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD13</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOC_OFFD</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOC_OFFD</displayName>
<description>GPIO Port C Pin OFF Digital Enable</description>
<addressOffset>0x84</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OFFD0</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD1</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD2</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD3</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD4</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD5</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD8</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD9</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD10</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD11</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD12</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD13</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOC_DOUT</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOC_DOUT</displayName>
<description>GPIO Port C Data Output Value</description>
<addressOffset>0x88</addressOffset>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DOUT0</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT1</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT2</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT3</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT4</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT5</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT8</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT9</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT10</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT11</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT12</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT13</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOC_DMASK</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOC_DMASK</displayName>
<description>GPIO Port C Data Output Write Mask</description>
<addressOffset>0x8C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMASK0</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK1</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK2</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK3</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK4</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK5</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK8</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK9</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK10</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK11</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK12</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK13</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOC_PIN</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOC_PIN</displayName>
<description>GPIO Port C Pin Value</description>
<addressOffset>0x90</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFF0000</resetMask>
<fields>
<field>
<name>PIN0</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN1</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN2</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN3</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN4</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN5</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN8</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN9</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN10</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN11</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN12</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN13</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>GPIOC_DBEN</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOC_DBEN</displayName>
<description>GPIO Port C De-bounce Enable</description>
<addressOffset>0x94</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DBEN0</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN1</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN2</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN3</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN4</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN5</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN8</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN9</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN10</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN11</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN12</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN13</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOC_IMD</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOC_IMD</displayName>
<description>GPIO Port C Interrupt Mode Control</description>
<addressOffset>0x98</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IMD0</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD1</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD2</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD3</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD4</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD5</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD8</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD9</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD10</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD11</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD12</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD13</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOC_IEN</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOC_IEN</displayName>
<description>GPIO Port C Interrupt Enable</description>
<addressOffset>0x9C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IF_EN0</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN1</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN2</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN3</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN4</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN5</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN8</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN9</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN10</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN11</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN12</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN13</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN0</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN1</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN2</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN3</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN4</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN5</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN8</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN9</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN10</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN11</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN12</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN13</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOC_ISRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOC_ISRC</displayName>
<description>GPIO Port C Interrupt Source Flag</description>
<addressOffset>0xA0</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISRC0</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC1</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC2</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC3</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC4</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC5</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC8</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC9</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC10</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC11</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC12</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC13</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOD_PMD</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOD_PMD</displayName>
<description>GPIO Port D Pin I/O Mode Control</description>
<addressOffset>0xC0</addressOffset>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PMD0</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD1</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD2</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD3</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD4</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD5</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD8</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD9</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD10</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD11</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOD_OFFD</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOD_OFFD</displayName>
<description>GPIO Port D Pin OFF Digital Enable</description>
<addressOffset>0xC4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OFFD0</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD1</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD2</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD3</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD4</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD5</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD8</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD9</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD10</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD11</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOD_DOUT</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOD_DOUT</displayName>
<description>GPIO Port D Data Output Value</description>
<addressOffset>0xC8</addressOffset>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DOUT0</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT1</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT2</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT3</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT4</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT5</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT8</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT9</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT10</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT11</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOD_DMASK</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOD_DMASK</displayName>
<description>GPIO Port D Data Output Write Mask</description>
<addressOffset>0xCC</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMASK0</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK1</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK2</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK3</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK4</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK5</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK8</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK9</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK10</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK11</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOD_PIN</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOD_PIN</displayName>
<description>GPIO Port D Pin Value</description>
<addressOffset>0xD0</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFF0000</resetMask>
<fields>
<field>
<name>PIN0</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN1</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN2</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN3</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN4</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN5</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN8</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN9</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN10</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN11</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>GPIOD_DBEN</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOD_DBEN</displayName>
<description>GPIO Port D De-bounce Enable</description>
<addressOffset>0xD4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DBEN0</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN1</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN2</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN3</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN4</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN5</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN8</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN9</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN10</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN11</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOD_IMD</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOD_IMD</displayName>
<description>GPIO Port D Interrupt Mode Control</description>
<addressOffset>0xD8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IMD0</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD1</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD2</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD3</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD4</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD5</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD8</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD9</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD10</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD11</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOD_IEN</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOD_IEN</displayName>
<description>GPIO Port D Interrupt Enable</description>
<addressOffset>0xDC</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IF_EN0</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN1</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN2</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN3</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN4</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN5</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN8</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN9</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN10</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN11</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN0</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN1</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN2</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN3</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN4</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN5</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN8</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN9</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN10</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN11</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOD_ISRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOD_ISRC</displayName>
<description>GPIO Port D Interrupt Source Flag</description>
<addressOffset>0xE0</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISRC0</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC1</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC2</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC3</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC4</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC5</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC8</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC9</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC10</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC11</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOF_PMD</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOF_PMD</displayName>
<description>GPIO Port F Pin I/O Mode Control</description>
<addressOffset>0x140</addressOffset>
<access>read-write</access>
<resetValue>0x000000FF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PMD0</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD1</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD2</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PMD3</name>
<description>GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [n] pin is in INPUT mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [n] pin is in OUTPUT mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>GPIO port [n] pin is in Open-Drain mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>GPIO port [n] pin is in Quasi-bidirectional mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOF_OFFD</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOF_OFFD</displayName>
<description>GPIO Port F Pin OFF Digital Enable</description>
<addressOffset>0x144</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>OFFD0</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD1</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD2</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OFFD3</name>
<description>GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>IO digital input path Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>IO digital input path Disabled (digital input tied to low)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOF_DOUT</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOF_DOUT</displayName>
<description>GPIO Port F Data Output Value</description>
<addressOffset>0x148</addressOffset>
<access>read-write</access>
<resetValue>0x0000000F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DOUT0</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT1</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT2</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DOUT3</name>
<description>GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOF_DMASK</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOF_DMASK</displayName>
<description>GPIO Port F Data Output Write Mask</description>
<addressOffset>0x14C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DMASK0</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK1</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK2</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMASK3</name>
<description>Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The corresponding GPIOx_DOUT[n] bit can be updated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The corresponding GPIOx_DOUT[n] bit is protected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOF_PIN</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOF_PIN</displayName>
<description>GPIO Port F Pin Value</description>
<addressOffset>0x150</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFF0</resetMask>
<fields>
<field>
<name>PIN0</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN1</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN2</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PIN3</name>
<description>Port [A/B/C/D/ F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>GPIOF_DBEN</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOF_DBEN</displayName>
<description>GPIO Port F De-bounce Enable</description>
<addressOffset>0x154</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DBEN0</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN1</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN2</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBEN3</name>
<description>Port [A/B/C/D/ F] Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0]\nThe DBEN[n] is used for "edge-trigger" interrupt only, and ignored for "level trigger" interrupt\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The bit[n] de-bounce function is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The bit[n] de-bounce function is enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOF_IMD</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOF_IMD</displayName>
<description>GPIO Port F Interrupt Mode Control</description>
<addressOffset>0x158</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IMD0</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD1</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD2</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IMD3</name>
<description>Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge trigger interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Level trigger interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOF_IEN</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOF_IEN</displayName>
<description>GPIO Port F Interrupt Enable</description>
<addressOffset>0x15C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>IF_EN0</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN1</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN2</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IF_EN3</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function\nWhen set the IF_EN[n] bit to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "low" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "high-to-low" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] state low-level or high-to-low change interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] state low-level or high-to-low change interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN0</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN1</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN2</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IR_EN3</name>
<description>Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function \nWhen the IR_EN[n] bit is set to 1:\nIf the interrupt is level triggered, the input PIN[n] state at level "high" will generate the interrupt.\nIf the interrupt is edge triggered, the input PIN[n] state changes from "low-to-high" will generate the interrupt.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PIN[n] level-high or low-to-high interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PIN[n] level-high or low-to-high interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GPIOF_ISRC</name>
<!-- the display name is an unrestricted string. -->
<displayName>GPIOF_ISRC</displayName>
<description>GPIO Port F Interrupt Source Flag</description>
<addressOffset>0x160</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ISRC0</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC1</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC2</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ISRC3</name>
<description>Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt at GPIOx[n].\nNo action</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DBNCECON</name>
<!-- the display name is an unrestricted string. -->
<displayName>DBNCECON</displayName>
<description>De-bounce Cycle Control</description>
<addressOffset>0x180</addressOffset>
<access>read-write</access>
<resetValue>0x00000020</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DBCLKSEL</name>
<description>De-bounce sampling cycle selection\n</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DBCLKSRC</name>
<description>De-bounce counter clock source select\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>De-bounce counter clock source is the HCLK</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>De-bounce counter clock source is the internal 10 kHz low speed oscillator</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ICLK_ON</name>
<description>Interrupt clock On mode\nSetting this bit to 0 will disable the interrupt generate circuit clock if the pin[n] interrupt is disabled\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Clock Disabled if the GPIOA/B/C/D/F[n] interrupt is disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt generated circuit clock always Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PA10_PDIO</name>
<!-- the display name is an unrestricted string. -->
<displayName>PA10_PDIO</displayName>
<description>GPIO PA.n Pin Data Input/Output</description>
<addressOffset>0x228</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFF0</resetMask>
<fields>
<field>
<name>GPIOxx_DOUT</name>
<description>GPIOxx I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\nRead this register to get IO pin status.\nFor example: Writing GPIOA0_DOUT will reflect the written value to bit GPIOA_DOUT[0], read GPIOA0_DOUT will return the value of GPIOA_PIN[0]</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Set the corresponding GPIO pin to low</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Set the corresponding GPIO pin to high</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register derivedFrom="PA10_PDIO">
<name>PA11_PDIO</name>
<displayName>PA11_PDIO</displayName>
<description>GPIO PA.n Pin Data Input/Output</description>
<addressOffset>0x22C</addressOffset>
</register>
<register derivedFrom="PA10_PDIO">
<name>PA12_PDIO</name>
<displayName>PA12_PDIO</displayName>
<description>GPIO PA.n Pin Data Input/Output</description>
<addressOffset>0x230</addressOffset>
</register>
<register derivedFrom="PA10_PDIO">
<name>PA13_PDIO</name>
<displayName>PA13_PDIO</displayName>
<description>GPIO PA.n Pin Data Input/Output</description>
<addressOffset>0x234</addressOffset>
</register>
<register derivedFrom="PA10_PDIO">
<name>PA14_PDIO</name>
<displayName>PA14_PDIO</displayName>
<description>GPIO PA.n Pin Data Input/Output</description>
<addressOffset>0x238</addressOffset>
</register>
<register derivedFrom="PA10_PDIO">
<name>PA15_PDIO</name>
<displayName>PA15_PDIO</displayName>
<description>GPIO PA.n Pin Data Input/Output</description>
<addressOffset>0x23C</addressOffset>
</register>
<register derivedFrom="PA10_PDIO">
<name>PB0_PDIO</name>
<displayName>PB0_PDIO</displayName>
<description>GPIO PB.n Pin Data Input/Output</description>
<addressOffset>0x240</addressOffset>
</register>
<register derivedFrom="PB0_PDIO">
<name>PB1_PDIO</name>
<displayName>PB1_PDIO</displayName>
<description>GPIO PB.n Pin Data Input/Output</description>
<addressOffset>0x244</addressOffset>
</register>
<register derivedFrom="PB0_PDIO">
<name>PB2_PDIO</name>
<displayName>PB2_PDIO</displayName>
<description>GPIO PB.n Pin Data Input/Output</description>
<addressOffset>0x248</addressOffset>
</register>
<register derivedFrom="PB0_PDIO">
<name>PB3_PDIO</name>
<displayName>PB3_PDIO</displayName>
<description>GPIO PB.n Pin Data Input/Output</description>
<addressOffset>0x24C</addressOffset>
</register>
<register derivedFrom="PB0_PDIO">
<name>PB4_PDIO</name>
<displayName>PB4_PDIO</displayName>
<description>GPIO PB.n Pin Data Input/Output</description>
<addressOffset>0x250</addressOffset>
</register>
<register derivedFrom="PB0_PDIO">
<name>PB5_PDIO</name>
<displayName>PB5_PDIO</displayName>
<description>GPIO PB.n Pin Data Input/Output</description>
<addressOffset>0x254</addressOffset>
</register>
<register derivedFrom="PB0_PDIO">
<name>PB6_PDIO</name>
<displayName>PB6_PDIO</displayName>
<description>GPIO PB.n Pin Data Input/Output</description>
<addressOffset>0x258</addressOffset>
</register>
<register derivedFrom="PB0_PDIO">
<name>PB7_PDIO</name>
<displayName>PB7_PDIO</displayName>
<description>GPIO PB.n Pin Data Input/Output</description>
<addressOffset>0x25C</addressOffset>
</register>
<register derivedFrom="PB0_PDIO">
<name>PB8_PDIO</name>
<displayName>PB8_PDIO</displayName>
<description>GPIO PB.n Pin Data Input/Output</description>
<addressOffset>0x260</addressOffset>
</register>
<register derivedFrom="PB0_PDIO">
<name>PB9_PDIO</name>
<displayName>PB9_PDIO</displayName>
<description>GPIO PB.n Pin Data Input/Output</description>
<addressOffset>0x264</addressOffset>
</register>
<register derivedFrom="PB0_PDIO">
<name>PB10_PDIO</name>
<displayName>PB10_PDIO</displayName>
<description>GPIO PB.n Pin Data Input/Output</description>
<addressOffset>0x268</addressOffset>
</register>
<register derivedFrom="PB0_PDIO">
<name>PB11_PDIO</name>
<displayName>PB11_PDIO</displayName>
<description>GPIO PB.n Pin Data Input/Output</description>
<addressOffset>0x26C</addressOffset>
</register>
<register derivedFrom="PB0_PDIO">
<name>PB12_PDIO</name>
<displayName>PB12_PDIO</displayName>
<description>GPIO PB.n Pin Data Input/Output</description>
<addressOffset>0x270</addressOffset>
</register>
<register derivedFrom="PB0_PDIO">
<name>PB13_PDIO</name>
<displayName>PB13_PDIO</displayName>
<description>GPIO PB.n Pin Data Input/Output</description>
<addressOffset>0x274</addressOffset>
</register>
<register derivedFrom="PB0_PDIO">
<name>PB14_PDIO</name>
<displayName>PB14_PDIO</displayName>
<description>GPIO PB.n Pin Data Input/Output</description>
<addressOffset>0x278</addressOffset>
</register>
<register derivedFrom="PB0_PDIO">
<name>PB15_PDIO</name>
<displayName>PB15_PDIO</displayName>
<description>GPIO PB.n Pin Data Input/Output</description>
<addressOffset>0x27C</addressOffset>
</register>
<register derivedFrom="PA10_PDIO">
<name>PC0_PDIO</name>
<displayName>PC0_PDIO</displayName>
<description>GPIO PC.n Pin Data Input/Output</description>
<addressOffset>0x280</addressOffset>
</register>
<register derivedFrom="PC0_PDIO">
<name>PC1_PDIO</name>
<displayName>PC1_PDIO</displayName>
<description>GPIO PC.n Pin Data Input/Output</description>
<addressOffset>0x284</addressOffset>
</register>
<register derivedFrom="PC0_PDIO">
<name>PC2_PDIO</name>
<displayName>PC2_PDIO</displayName>
<description>GPIO PC.n Pin Data Input/Output</description>
<addressOffset>0x288</addressOffset>
</register>
<register derivedFrom="PC0_PDIO">
<name>PC3_PDIO</name>
<displayName>PC3_PDIO</displayName>
<description>GPIO PC.n Pin Data Input/Output</description>
<addressOffset>0x28C</addressOffset>
</register>
<register derivedFrom="PC0_PDIO">
<name>PC4_PDIO</name>
<displayName>PC4_PDIO</displayName>
<description>GPIO PC.n Pin Data Input/Output</description>
<addressOffset>0x290</addressOffset>
</register>
<register derivedFrom="PC0_PDIO">
<name>PC5_PDIO</name>
<displayName>PC5_PDIO</displayName>
<description>GPIO PC.n Pin Data Input/Output</description>
<addressOffset>0x294</addressOffset>
</register>
<register derivedFrom="PC0_PDIO">
<name>PC6_PDIO</name>
<displayName>PC6_PDIO</displayName>
<description>GPIO PC.n Pin Data Input/Output</description>
<addressOffset>0x298</addressOffset>
</register>
<register derivedFrom="PC0_PDIO">
<name>PC7_PDIO</name>
<displayName>PC7_PDIO</displayName>
<description>GPIO PC.n Pin Data Input/Output</description>
<addressOffset>0x29C</addressOffset>
</register>
<register derivedFrom="PC0_PDIO">
<name>PC8_PDIO</name>
<displayName>PC8_PDIO</displayName>
<description>GPIO PC.n Pin Data Input/Output</description>
<addressOffset>0x2A0</addressOffset>
</register>
<register derivedFrom="PC0_PDIO">
<name>PC9_PDIO</name>
<displayName>PC9_PDIO</displayName>
<description>GPIO PC.n Pin Data Input/Output</description>
<addressOffset>0x2A4</addressOffset>
</register>
<register derivedFrom="PC0_PDIO">
<name>PC10_PDIO</name>
<displayName>PC10_PDIO</displayName>
<description>GPIO PC.n Pin Data Input/Output</description>
<addressOffset>0x2A8</addressOffset>
</register>
<register derivedFrom="PC0_PDIO">
<name>PC11_PDIO</name>
<displayName>PC11_PDIO</displayName>
<description>GPIO PC.n Pin Data Input/Output</description>
<addressOffset>0x2AC</addressOffset>
</register>
<register derivedFrom="PC0_PDIO">
<name>PC12_PDIO</name>
<displayName>PC12_PDIO</displayName>
<description>GPIO PC.n Pin Data Input/Output</description>
<addressOffset>0x2B0</addressOffset>
</register>
<register derivedFrom="PC0_PDIO">
<name>PC13_PDIO</name>
<displayName>PC13_PDIO</displayName>
<description>GPIO PC.n Pin Data Input/Output</description>
<addressOffset>0x2B4</addressOffset>
</register>
<register derivedFrom="PA10_PDIO">
<name>PD0_PDIO</name>
<displayName>PD0_PDIO</displayName>
<description>GPIO PD.n Pin Data Input/Output</description>
<addressOffset>0x2C0</addressOffset>
</register>
<register derivedFrom="PD0_PDIO">
<name>PD1_PDIO</name>
<displayName>PD1_PDIO</displayName>
<description>GPIO PD.n Pin Data Input/Output</description>
<addressOffset>0x2C4</addressOffset>
</register>
<register derivedFrom="PD0_PDIO">
<name>PD2_PDIO</name>
<displayName>PD2_PDIO</displayName>
<description>GPIO PD.n Pin Data Input/Output</description>
<addressOffset>0x2C8</addressOffset>
</register>
<register derivedFrom="PD0_PDIO">
<name>PD3_PDIO</name>
<displayName>PD3_PDIO</displayName>
<description>GPIO PD.n Pin Data Input/Output</description>
<addressOffset>0x2CC</addressOffset>
</register>
<register derivedFrom="PD0_PDIO">
<name>PD4_PDIO</name>
<displayName>PD4_PDIO</displayName>
<description>GPIO PD.n Pin Data Input/Output</description>
<addressOffset>0x2D0</addressOffset>
</register>
<register derivedFrom="PD0_PDIO">
<name>PD5_PDIO</name>
<displayName>PD5_PDIO</displayName>
<description>GPIO PD.n Pin Data Input/Output</description>
<addressOffset>0x2D4</addressOffset>
</register>
<register derivedFrom="PD0_PDIO">
<name>PD6_PDIO</name>
<displayName>PD6_PDIO</displayName>
<description>GPIO PD.n Pin Data Input/Output</description>
<addressOffset>0x2D8</addressOffset>
</register>
<register derivedFrom="PD0_PDIO">
<name>PD7_PDIO</name>
<displayName>PD7_PDIO</displayName>
<description>GPIO PD.n Pin Data Input/Output</description>
<addressOffset>0x2DC</addressOffset>
</register>
<register derivedFrom="PD0_PDIO">
<name>PD8_PDIO</name>
<displayName>PD8_PDIO</displayName>
<description>GPIO PD.n Pin Data Input/Output</description>
<addressOffset>0x2E0</addressOffset>
</register>
<register derivedFrom="PD0_PDIO">
<name>PD9_PDIO</name>
<displayName>PD9_PDIO</displayName>
<description>GPIO PD.n Pin Data Input/Output</description>
<addressOffset>0x2E4</addressOffset>
</register>
<register derivedFrom="PD0_PDIO">
<name>PD10_PDIO</name>
<displayName>PD10_PDIO</displayName>
<description>GPIO PD.n Pin Data Input/Output</description>
<addressOffset>0x2E8</addressOffset>
</register>
<register derivedFrom="PD0_PDIO">
<name>PD11_PDIO</name>
<displayName>PD11_PDIO</displayName>
<description>GPIO PD.n Pin Data Input/Output</description>
<addressOffset>0x2EC</addressOffset>
</register>
<register derivedFrom="PA10_PDIO">
<name>PF0_PDIO</name>
<displayName>PF0_PDIO</displayName>
<description>GPIO PF.n Pin Data Input/Output</description>
<addressOffset>0x340</addressOffset>
</register>
<register derivedFrom="PF0_PDIO">
<name>PF1_PDIO</name>
<displayName>PF1_PDIO</displayName>
<description>GPIO PF.n Pin Data Input/Output</description>
<addressOffset>0x344</addressOffset>
</register>
<register derivedFrom="PF0_PDIO">
<name>PF2_PDIO</name>
<displayName>PF2_PDIO</displayName>
<description>GPIO PF.n Pin Data Input/Output</description>
<addressOffset>0x348</addressOffset>
</register>
<register derivedFrom="PF0_PDIO">
<name>PF3_PDIO</name>
<displayName>PF3_PDIO</displayName>
<description>GPIO PF.n Pin Data Input/Output</description>
<addressOffset>0x34C</addressOffset>
</register>
</registers>
</peripheral>
<peripheral>
<name>I2C0</name>
<description>I2C Register Map</description>
<groupName>I2C</groupName>
<baseAddress>0x40020000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x34</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x3C</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>I2CON</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2CON</displayName>
<description>I2C Control Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AA</name>
<description>Assert Acknowledge Control Bit\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SI</name>
<description>I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to this bit.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>STO</name>
<description>I2C STOP Control Bit\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a Slave mode, setting STO resets I2C hardware to the defined "not addressed" Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>STA</name>
<description>I2C START Control Bit\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ENS1</name>
<description>I2C Controller Enable Bit\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>EI</name>
<description>Enable Interrupt\n</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>I2C interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>I2C interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>I2CADDR0</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2CADDR0</displayName>
<description>I2C Slave Address Register0</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GC</name>
<description>General Call Function\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>General Call function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>General Call function Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>I2CADDR</name>
<description>I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the addresses is matched.</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>I2CDAT</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2CDAT</displayName>
<description>I2C Data Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>I2CDAT</name>
<description>I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>I2CSTATUS</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2CSTATUS</displayName>
<description>I2C Status Register</description>
<addressOffset>0xC</addressOffset>
<access>read-only</access>
<resetValue>0x000000F8</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>I2CSTATUS</name>
<description>I2C Status Register\nThe status register of I2C:\n</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>I2CLK</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2CLK</displayName>
<description>I2C Clock Divided Register</description>
<addressOffset>0x10</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>I2CLK</name>
<description>I2C clock divided Register\n</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>I2CTOC</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2CTOC</displayName>
<description>I2C Time-Out Counter Register</description>
<addressOffset>0x14</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIF</name>
<description>Time-Out Flag\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Software can clear the flag</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Time-out flag is set by H/W. It can interrupt CPU</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DIV4</name>
<description>Time-out Counter Input Clock Divided by 4\nWhen Enabled, the time-out period is extend 4 times.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ENTI</name>
<description>Time-out Counter Enable/Disable\nWhen Enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting the flag SI to high will reset counter and re-start counting up after SI is cleared.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register derivedFrom="I2CADDR0">
<name>I2CADDR1</name>
<displayName>I2CADDR1</displayName>
<description>I2C Slave Address Register1</description>
<addressOffset>0x18</addressOffset>
</register>
<register derivedFrom="I2CADDR0">
<name>I2CADDR2</name>
<displayName>I2CADDR2</displayName>
<description>I2C Slave Address Register2</description>
<addressOffset>0x1C</addressOffset>
</register>
<register derivedFrom="I2CADDR0">
<name>I2CADDR3</name>
<displayName>I2CADDR3</displayName>
<description>I2C Slave Address Register3</description>
<addressOffset>0x20</addressOffset>
</register>
<register>
<name>I2CADM0</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2CADM0</displayName>
<description>I2C Slave Address Mask Register0</description>
<addressOffset>0x24</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>I2CADM</name>
<description>I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, it means the received corresponding register bit should be exact the same as address register.</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Mask Disabled (the received corresponding register bit should be exactly the same as address register.)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Mask Enabled (the received corresponding address bit is don't care.)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register derivedFrom="I2CADM0">
<name>I2CADM1</name>
<displayName>I2CADM1</displayName>
<description>I2C Slave Address Mask Register1</description>
<addressOffset>0x28</addressOffset>
</register>
<register derivedFrom="I2CADM0">
<name>I2CADM2</name>
<displayName>I2CADM2</displayName>
<description>I2C Slave Address Mask Register2</description>
<addressOffset>0x2C</addressOffset>
</register>
<register derivedFrom="I2CADM0">
<name>I2CADM3</name>
<displayName>I2CADM3</displayName>
<description>I2C Slave Address Mask Register3</description>
<addressOffset>0x30</addressOffset>
</register>
<register>
<name>I2CWKUPCON</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2CWKUPCON</displayName>
<description>I2C Wake-up Control Register</description>
<addressOffset>0x3C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WKUPEN</name>
<description>I2C Wake-up Function Enable\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>I2C wake-up function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>I2C wake-up function Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>I2CWKUPSTS</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2CWKUPSTS</displayName>
<description>I2C Wake-up Status Register</description>
<addressOffset>0x40</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WKUPIF</name>
<description>Wake-up Interrupt Flag\nSoftware can write one to clear this flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Wake-up flag inactive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Wake-up flag active</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>I2C1</name>
<description>I2C Register Map</description>
<groupName>I2C</groupName>
<baseAddress>0x40120000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x34</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x3C</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>I2CON</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2CON</displayName>
<description>I2C Control Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AA</name>
<description>Assert Acknowledge Control Bit\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SI</name>
<description>I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to this bit.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>STO</name>
<description>I2C STOP Control Bit\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a Slave mode, setting STO resets I2C hardware to the defined "not addressed" Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>STA</name>
<description>I2C START Control Bit\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ENS1</name>
<description>I2C Controller Enable Bit\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>EI</name>
<description>Enable Interrupt\n</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>I2C interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>I2C interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>I2CADDR0</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2CADDR0</displayName>
<description>I2C Slave Address Register0</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GC</name>
<description>General Call Function\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>General Call function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>General Call function Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>I2CADDR</name>
<description>I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the addresses is matched.</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>I2CDAT</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2CDAT</displayName>
<description>I2C Data Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>I2CDAT</name>
<description>I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>I2CSTATUS</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2CSTATUS</displayName>
<description>I2C Status Register</description>
<addressOffset>0xC</addressOffset>
<access>read-only</access>
<resetValue>0x000000F8</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>I2CSTATUS</name>
<description>I2C Status Register\nThe status register of I2C:\n</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>I2CLK</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2CLK</displayName>
<description>I2C Clock Divided Register</description>
<addressOffset>0x10</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>I2CLK</name>
<description>I2C clock divided Register\n</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>I2CTOC</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2CTOC</displayName>
<description>I2C Time-Out Counter Register</description>
<addressOffset>0x14</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIF</name>
<description>Time-Out Flag\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Software can clear the flag</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Time-out flag is set by H/W. It can interrupt CPU</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DIV4</name>
<description>Time-out Counter Input Clock Divided by 4\nWhen Enabled, the time-out period is extend 4 times.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ENTI</name>
<description>Time-out Counter Enable/Disable\nWhen Enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting the flag SI to high will reset counter and re-start counting up after SI is cleared.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register derivedFrom="I2CADDR0">
<name>I2CADDR1</name>
<displayName>I2CADDR1</displayName>
<description>I2C Slave Address Register1</description>
<addressOffset>0x18</addressOffset>
</register>
<register derivedFrom="I2CADDR0">
<name>I2CADDR2</name>
<displayName>I2CADDR2</displayName>
<description>I2C Slave Address Register2</description>
<addressOffset>0x1C</addressOffset>
</register>
<register derivedFrom="I2CADDR0">
<name>I2CADDR3</name>
<displayName>I2CADDR3</displayName>
<description>I2C Slave Address Register3</description>
<addressOffset>0x20</addressOffset>
</register>
<register>
<name>I2CADM0</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2CADM0</displayName>
<description>I2C Slave Address Mask Register0</description>
<addressOffset>0x24</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>I2CADM</name>
<description>I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, it means the received corresponding register bit should be exact the same as address register.</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Mask Disabled (the received corresponding register bit should be exactly the same as address register.)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Mask Enabled (the received corresponding address bit is don't care.)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register derivedFrom="I2CADM0">
<name>I2CADM1</name>
<displayName>I2CADM1</displayName>
<description>I2C Slave Address Mask Register1</description>
<addressOffset>0x28</addressOffset>
</register>
<register derivedFrom="I2CADM0">
<name>I2CADM2</name>
<displayName>I2CADM2</displayName>
<description>I2C Slave Address Mask Register2</description>
<addressOffset>0x2C</addressOffset>
</register>
<register derivedFrom="I2CADM0">
<name>I2CADM3</name>
<displayName>I2CADM3</displayName>
<description>I2C Slave Address Mask Register3</description>
<addressOffset>0x30</addressOffset>
</register>
<register>
<name>I2CWKUPCON</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2CWKUPCON</displayName>
<description>I2C Wake-up Control Register</description>
<addressOffset>0x3C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WKUPEN</name>
<description>I2C Wake-up Function Enable\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>I2C wake-up function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>I2C wake-up function Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>I2CWKUPSTS</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2CWKUPSTS</displayName>
<description>I2C Wake-up Status Register</description>
<addressOffset>0x40</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WKUPIF</name>
<description>Wake-up Interrupt Flag\nSoftware can write one to clear this flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Wake-up flag inactive</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Wake-up flag active</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PWMA</name>
<description>PWM Register Map</description>
<groupName>PWM</groupName>
<baseAddress>0x40040000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x48</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x50</offset>
<size>0x48</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0xC0</offset>
<size>0x14</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PPR</name>
<!-- the display name is an unrestricted string. -->
<displayName>PPR</displayName>
<description>PWM Prescaler Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CP01</name>
<description>Clock Prescaler 0 (PWM-timer 0 / 1)\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CP23</name>
<description>Clock Prescaler 2 (PWM Timer2 / 3)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer.\n</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DZI01</name>
<description>Dead-zone Interval for Pair of Channel 0 and Channel 1 (PWM0 and PWM1 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits.</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DZI23</name>
<description>Dead-zone Interval for Pair of Channel2 and Channel3 (PWM2 and PWM3 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits.</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CSR</name>
<!-- the display name is an unrestricted string. -->
<displayName>CSR</displayName>
<description>PWM Clock Selector Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CSR0</name>
<description>PWM Timer 0 Clock Source Selection (PWM Timer 0)\nSelect clock input for PWM timer.\n(Table is the same as CSR3.)</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CSR1</name>
<description>PWM Timer 1 Clock Source Selection (PWM Timer 1)\nSelect clock input for PWM timer.\n(Table is the same as CSR3.)</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CSR2</name>
<description>PWM Timer 2 Clock Source Selection (PWM Timer 2)\nSelect clock input for PWM timer.\n(Table is the same as CSR3.)</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CSR3</name>
<description>PWM Timer 3 Clock Source Selection (PWM timer 3)\n</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>PCR</displayName>
<description>PWM Control Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CH0EN</name>
<description>PWM-Timer 0 Enable (PWM timer 0)\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding PWM-Timer Running Stopped</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding PWM-Timer Start Run Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CH0PINV</name>
<description>PWM-Timer 0 Output Polar Inverse Enable (PWM Timer 0)\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PWM0 output polar inverse Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PWM0 output polar inverse Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CH0INV</name>
<description>PWM-Timer 0 Output Inverter Enable (PWM Timer 0)\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverter Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverter Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CH0MOD</name>
<description>PWM-Timer 0 Auto-reload/One-Shot Mode (PWM Timer 0)\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be clear.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One-shot mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Auto-reload mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DZEN01</name>
<description>Dead-Zone 0 Generator Enable (PWM0 and PWM1 Pair)\nNote: When dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DZEN23</name>
<description>Dead-Zone 2 Generator Enable (PWM2 and PWM3 Pair)\nNote: When dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CH1EN</name>
<description>PWM-Timer 1 Enable (PWM Timer 1)\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding PWM-Timer Running Stopped</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding PWM-Timer Start Run Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CH1PINV</name>
<description>PWM-Timer 1 Output Polar Inverse Enable (PWM Timer 1)\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PWM1 output polar inverse Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PWM1 output polar inverse Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CH1INV</name>
<description>PWM-Timer 1 Output Inverter Enable (PWM Timer 1)\n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverter Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverter Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CH1MOD</name>
<description>PWM-Timer 1 Auto-reload/One-Shot Mode (PWM Timer 1)\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be clear.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One-shot mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Auto-load mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CH2EN</name>
<description>PWM-Timer 2 Enable (PWM Timer 2)\n</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding PWM-Timer Running Stopped</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding PWM-Timer Start Run Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CH2PINV</name>
<description>PWM-Timer 2 Output Polar Inverse Enable (PWM Timer 2)\n</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PWM2 output polar inverse Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PWM2 output polar inverse Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CH2INV</name>
<description>PWM-Timer 2 Output Inverter Enable (PWM Timer 2)\n</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverter Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverter Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CH2MOD</name>
<description>PWM-Timer 2 Auto-reload/One-Shot Mode (PWM Timer 2)\nNote: If there is a transition at this bit, it will cause CNR2 and CMR2 be clear.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One-shot mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Auto-reload mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CH3EN</name>
<description>PWM-Timer 3 Enable (PWM Timer 3)\n</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Corresponding PWM-Timer Running Stopped</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Corresponding PWM-Timer Start Run Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CH3PINV</name>
<description>PWM-Timer 3 Output Polar Inverse Enable (PWM Timer 3)\n</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PWM3 output polar inverse Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PWM3 output polar inverse Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CH3INV</name>
<description>PWM-Timer 3 Output Inverter Enable (PWM Timer 3)\n</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverter Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverter Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CH3MOD</name>
<description>PWM-Timer 3 Auto-reload/One-Shot Mode (PWM Timer 3)\nNote: If there is a transition at this bit, it will cause CNR3 and CMR3 be clear.</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One-shot mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Auto-reload mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWMTYPE01</name>
<description>PWM01 Aligned Type Selection Bit (PWM0 and PWM1 Pair)\n</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge-aligned type</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Center-aligned type</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWMTYPE23</name>
<description>PWM23 Aligned Type Selection Bit (PWM2 and PWM3 Pair)\n</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Edge-aligned type</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Center-aligned type</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CNR0</name>
<!-- the display name is an unrestricted string. -->
<displayName>CNR0</displayName>
<description>PWM Counter Register 0</description>
<addressOffset>0xC</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CNRx</name>
<description>PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in the next PWM cycle.\nNote: When PWM operating at center-aligned type, CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF, the PWM will work unpredictable.\nNote: When CNR value is set to 0, PWM output is always high.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CMR0</name>
<!-- the display name is an unrestricted string. -->
<displayName>CMR0</displayName>
<description>PWM Comparator Register 0</description>
<addressOffset>0x10</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CMRx</name>
<description>PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in the next PWM cycle.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDR0</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDR0</displayName>
<description>PWM Data Register 0</description>
<addressOffset>0x14</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDRx</name>
<description>PWM Data Register\nUser can monitor PDR to know the current value in 16-bit down counter.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register derivedFrom="CNR0">
<name>CNR1</name>
<displayName>CNR1</displayName>
<description>PWM Counter Register 1</description>
<addressOffset>0x18</addressOffset>
</register>
<register derivedFrom="CMR0">
<name>CMR1</name>
<displayName>CMR1</displayName>
<description>PWM Comparator Register 1</description>
<addressOffset>0x1C</addressOffset>
</register>
<register derivedFrom="PDR0">
<name>PDR1</name>
<displayName>PDR1</displayName>
<description>PWM Data Registe 1</description>
<addressOffset>0x20</addressOffset>
</register>
<register derivedFrom="CNR0">
<name>CNR2</name>
<displayName>CNR2</displayName>
<description>PWM Counter Register 2</description>
<addressOffset>0x24</addressOffset>
</register>
<register derivedFrom="CMR0">
<name>CMR2</name>
<displayName>CMR2</displayName>
<description>PWM Comparator Register 2</description>
<addressOffset>0x28</addressOffset>
</register>
<register derivedFrom="PDR0">
<name>PDR2</name>
<displayName>PDR2</displayName>
<description>PWM Data Register 2</description>
<addressOffset>0x2C</addressOffset>
</register>
<register derivedFrom="CNR0">
<name>CNR3</name>
<displayName>CNR3</displayName>
<description>PWM Counter Register 3</description>
<addressOffset>0x30</addressOffset>
</register>
<register derivedFrom="CMR0">
<name>CMR3</name>
<displayName>CMR3</displayName>
<description>PWM Comparator Register 3</description>
<addressOffset>0x34</addressOffset>
</register>
<register derivedFrom="PDR0">
<name>PDR3</name>
<displayName>PDR3</displayName>
<description>PWM Data Register 3</description>
<addressOffset>0x38</addressOffset>
</register>
<register>
<name>PBCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>PBCR</displayName>
<description>PWM backward compatible Register</description>
<addressOffset>0x3C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
</register>
<register>
<name>PIER</name>
<!-- the display name is an unrestricted string. -->
<displayName>PIER</displayName>
<description>PWM Interrupt Enable Register</description>
<addressOffset>0x40</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWMIE0</name>
<description>PWM Channel 0 Interrupt Enable\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWMIE1</name>
<description>PWM Channel 1 Interrupt Enable\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWMIE2</name>
<description>PWM Channel 2 Interrupt Enable\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWMIE3</name>
<description>PWM Channel 3 Interrupt Enable\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWMDIE0</name>
<description>PWM Channel 0 Duty Interrupt Enable\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWMDIE1</name>
<description>PWM Channel 1 Duty Interrupt Enable\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWMDIE2</name>
<description>PWM Channel 2 Duty Interrupt Enable\n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWMDIE3</name>
<description>PWM Channel 3 Duty Interrupt Enable\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>INTTYPE01</name>
<description>PWM01 Interrupt Type Selection Bit (PWM0 and PWM1 Pair)\nNote: This bit is effective when PWM in central align mode only.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PWMIFn will be set if PWM counter underflow</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PWMIFn will be set if PWM counter matches CNRn register</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>INTTYPE23</name>
<description>PWM12 Interrupt Type Selection Bit (PWM2 and PWM3 Pair)\nNote: This bit is effective when PWM in central align mode only.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PWMIFn will be set if PWM counter underflow</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PWMIFn will be set if PWM counter matches CNRn register</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PIIR</name>
<!-- the display name is an unrestricted string. -->
<displayName>PIIR</displayName>
<description>PWM Interrupt Indication Register</description>
<addressOffset>0x44</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWMIF0</name>
<description>PWM channel 0 Interrupt Status\nThis bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depending on INTTYPE01 bit of PIER register) if PWM0 interrupt enable bit (PWMIE0) is 1, software can write 1 to clear this bit to zero</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWMIF1</name>
<description>PWM channel 1 Interrupt Status\nThis bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depending on INTTYPE01 bit of PIER register) if PWM1 interrupt enable bit (PWMIE1) is 1, software can write 1 to clear this bit to zero</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWMIF2</name>
<description>PWM channel 2 Interrupt Status\nThis bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depending on INTTYPE23 bit of PIER register) if PWM2 interrupt enable bit (PWMIE2) is 1, software can write 1 to clear this bit to zero</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWMIF3</name>
<description>PWM channel 3 Interrupt Status\nThis bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depending on INTTYPE23 bit of PIER register) if PWM3 interrupt enable bit (PWMIE3) is 1, software can write 1 to clear this bit to zero</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWMDIF0</name>
<description>PWM channel 0 Duty Interrupt Flag\nFlag is set by hardware when channel 0 PWM counter down count and reaches CMR0, software can clear this bit by writing a one to it.\nNote: If CMR is equal to CNR, this flag is not working</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWMDIF1</name>
<description>PWM channel 1 Duty Interrupt Flag\nFlag is set by hardware when channel 1 PWM counter down count and reaches CMR1, software can clear this bit by writing a one to it.\nNote: If CMR is equal to CNR, this flag is not working</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWMDIF2</name>
<description>PWM channel 2 Duty Interrupt Flag\nFlag is set by hardware when channel 2 PWM counter down count and reaches CMR2, software can clear this bit by writing a one to it.\nNote: If CMR is equal to CNR, this flag is not working</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWMDIF3</name>
<description>PWM channel 3 Duty Interrupt Flag\nFlag is set by hardware when channel 3 PWM counter down count and reaches CMR3, software can clear this bit by writing a one to it.\nNote: If CMR is equal to CNR, this flag is not working</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CCR0</name>
<!-- the display name is an unrestricted string. -->
<displayName>CCR0</displayName>
<description>PWM Capture Control Register 0</description>
<addressOffset>0x50</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INV0</name>
<description>Channel 0 Inverter Enable\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverter Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CRL_IE0</name>
<description>Channel 0 Rising Latch Interrupt Enable\nWhen Enabled, if capture detects PWM group channel 0 has rising transition, capture issues an Interrupt.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Rising latch interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Rising latch interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CFL_IE0</name>
<description>Channel 0 Falling Latch Interrupt Enable\nWhen Enabled, if capture detects PWM group channel 0 has falling transition, capture issues an Interrupt.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Falling latch interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Falling latch interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CAPCH0EN</name>
<description>Channel 0 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Capture function on PWM group channel 0 Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Capture function on PWM group channel 0 Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CAPIF0</name>
<description>Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CRLRI0</name>
<description>CRLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CFLRI0</name>
<description>CFLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INV1</name>
<description>Channel 1 Inverter Enable\n</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverter Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CRL_IE1</name>
<description>Channel 1 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 1 has rising transition, capture issues an Interrupt.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Rising latch interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Rising latch interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CFL_IE1</name>
<description>Channel 1 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 1 has falling transition, capture issues an Interrupt.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Falling latch interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Falling latch interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CAPCH1EN</name>
<description>Channel 1 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Capture function on PWM group channel 1 Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Capture function on PWM group channel 1 Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CAPIF1</name>
<description>Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CRLRI1</name>
<description>CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition, CRLR1 is latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CFLRI1</name>
<description>CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition, CFLR1 is latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CCR2</name>
<!-- the display name is an unrestricted string. -->
<displayName>CCR2</displayName>
<description>PWM Capture Control Register 2</description>
<addressOffset>0x54</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INV2</name>
<description>Channel 2 Inverter Enable\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverter Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CRL_IE2</name>
<description>Channel 2 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 2 has rising transition, Capture issues an Interrupt.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Rising latch interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Rising latch interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CFL_IE2</name>
<description>Channel 2 Falling Latch Interrupt Enable\nWhen Enabled, if capture detects PWM group channel 2 has falling transition, capture issues an Interrupt.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Falling latch interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Falling latch interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CAPCH2EN</name>
<description>Channel 2 Capture Function Enable\nWhen Enabled, capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Capture function on PWM group channel 2 Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Capture function on PWM group channel 2 Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CAPIF2</name>
<description>Channel 2 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CRLRI2</name>
<description>CRLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CFLRI2</name>
<description>CFLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INV3</name>
<description>Channel 3 Inverter Enable\n</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Inverter Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CRL_IE3</name>
<description>Channel 3 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 3 has rising transition, capture issues an Interrupt.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Rising latch interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Rising latch interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CFL_IE3</name>
<description>Channel 3 Falling Latch Interrupt Enable\nWhen Enabled, if capture detects PWM group channel 3 has falling transition, capture issues an Interrupt.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Falling latch interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Falling latch interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CAPCH3EN</name>
<description>Channel 3 Capture Function Enable\nWhen Enabled, capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Capture function on PWM group channel 3 Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Capture function on PWM group channel 3 Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CAPIF3</name>
<description>Channel 3 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to zero</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CRLRI3</name>
<description>CRLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CFLRI3</name>
<description>CFLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to zero if BCn bit is 0, and can write 1 to clear this bit to zero if BCn bit is 1.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CRLR0</name>
<!-- the display name is an unrestricted string. -->
<displayName>CRLR0</displayName>
<description>PWM Capture Rising Latch Register (Channel 0)</description>
<addressOffset>0x58</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRLRx</name>
<description>Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CFLR0</name>
<!-- the display name is an unrestricted string. -->
<displayName>CFLR0</displayName>
<description>PWM Capture Falling Latch Register (Channel 0)</description>
<addressOffset>0x5C</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CFLRx</name>
<description>Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register derivedFrom="CRLR0">
<name>CRLR1</name>
<displayName>CRLR1</displayName>
<description>PWM Capture Rising Latch Register (Channel 1)</description>
<addressOffset>0x60</addressOffset>
</register>
<register derivedFrom="CFLR0">
<name>CFLR1</name>
<displayName>CFLR1</displayName>
<description>PWM Capture Falling Latch Register (Channel 1)</description>
<addressOffset>0x64</addressOffset>
</register>
<register derivedFrom="CRLR0">
<name>CRLR2</name>
<displayName>CRLR2</displayName>
<description>PWM Capture Rising Latch Register (Channel 2)</description>
<addressOffset>0x68</addressOffset>
</register>
<register derivedFrom="CFLR0">
<name>CFLR2</name>
<displayName>CFLR2</displayName>
<description>PWM Capture Falling Latch Register (Channel 2)</description>
<addressOffset>0x6C</addressOffset>
</register>
<register derivedFrom="CRLR0">
<name>CRLR3</name>
<displayName>CRLR3</displayName>
<description>PWM Capture Rising Latch Register (Channel 3)</description>
<addressOffset>0x70</addressOffset>
</register>
<register derivedFrom="CFLR0">
<name>CFLR3</name>
<displayName>CFLR3</displayName>
<description>PWM Capture Falling Latch Register (Channel 3)</description>
<addressOffset>0x74</addressOffset>
</register>
<register>
<name>CAPENR</name>
<!-- the display name is an unrestricted string. -->
<displayName>CAPENR</displayName>
<description>PWM Capture Input 0~3 Enable Register</description>
<addressOffset>0x78</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAPENR</name>
<description>Capture Input Enable Register\nThere are four capture inputs from pad. Bit0~Bit3 are used to control each input enable or disable. \n\nCAPENR\nBit 3210 for PWM group A\nBit xxx1 ( Capture channel 0 is from pin PA.12\nBit xx1x ( Capture channel 1 is from pin PA.13\nBit x1xx ( Capture channel 2 is from pin PA.14\nBit 1xxx ( Capture channel 3 is from pin PA.15\nBit 3210 for PWM group B\nBit xxx1 ( Capture channel 0 is from pin PB.11\nBit xx1x ( Capture channel 1 is from pin PE.5\nBit x1xx ( Capture channel 2 is from pin PE.0\nBit 1xxx ( Capture channel 3 is from pin PE.1</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled (PWMx multi-function pin input does not affect input capture function.)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled (PWMx multi-function pin input will affect its input capture function.)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>POE</name>
<!-- the display name is an unrestricted string. -->
<displayName>POE</displayName>
<description>PWM Output Enable for channel 0~3</description>
<addressOffset>0x7C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWM0</name>
<description>Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PWM channel 0 output to pin Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PWM channel 0 output to pin Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWM1</name>
<description>Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PWM channel 1 output to pin Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PWM channel 1 output to pin Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWM2</name>
<description>Channel 2 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PWM channel 2 output to pin Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PWM channel 2 output to pin Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWM3</name>
<description>Channel 3 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PWM channel 3 output to pin Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PWM channel 3 output to pin Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TCON</name>
<!-- the display name is an unrestricted string. -->
<displayName>TCON</displayName>
<description>PWM Trigger Control for channel 0~3</description>
<addressOffset>0x80</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWM0TEN</name>
<description>Channel 0 Center-Aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter counts up to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating in Center-aligned mode.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PWM channel 0 trigger ADC function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PWM channel 0 trigger ADC function Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWM1TEN</name>
<description>Channel 1 Center-Aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter counts up to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating in Center-aligned mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PWM channel 1 trigger ADC function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PWM channel 1 trigger ADC function Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWM2TEN</name>
<description>Channel 2 Center-Aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter counts up to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating in Center-aligned mode.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PWM channel 2 trigger ADC function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PWM channel 2 trigger ADC function Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PWM3TEN</name>
<description>Channel 3 Center-Aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter counts up to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating in Center-aligned mode.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PWM channel 3 trigger ADC function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PWM channel 3 trigger ADC function Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TSTATUS</name>
<!-- the display name is an unrestricted string. -->
<displayName>TSTATUS</displayName>
<description>PWM Trigger Status Register</description>
<addressOffset>0x84</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PWM0TF</name>
<description>Channel 0 Center-aligned Trigger Flag\nFor Center-aligned operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM0TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWM1TF</name>
<description>Channel 1 Center-aligned Trigger Flag\nFor Center-aligned operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM1TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWM2TF</name>
<description>Channel 2 Center-aligned Trigger Flag\nFor Center-aligned operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM2TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWM3TF</name>
<description>Channel 3 Center-aligned Trigger Flag\nFor Center-aligned operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM3TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SYNCBUSY0</name>
<!-- the display name is an unrestricted string. -->
<displayName>SYNCBUSY0</displayName>
<description>PWM0 Synchronous Busy Status Register</description>
<addressOffset>0x88</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>S_BUSY</name>
<description>PWM Synchronous Busy\nWhen software writes CNR0/CMR0/PPR or switch PWM0 operation mode (PCR[3]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes CNR0/CMR0/PPR or switch PWM0 operation mode (PCR[3]) to make sure previous setting has been update completely.\nThis bit will be set when software write CNR0/CMR0/PPR or switch PWM0 operation mode (PCR[3]) and will be cleared by hardware automatically when PWM update these value completely.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>SYNCBUSY1</name>
<!-- the display name is an unrestricted string. -->
<displayName>SYNCBUSY1</displayName>
<description>PWM1 Synchronous Busy Status Register</description>
<addressOffset>0x8C</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>S_BUSY</name>
<description>PWM Synchronous Busy\nWhen software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR1/CMR1/PPR or switching PWM1 operation mode (PCR[11]) to make sure the previous setting has been updated completely.\nThis bit will be set when software write CNR1/CMR1/PPR or switch PWM1 operation mode (PCR[11]) and will be cleared by hardware automatically when PWM updates these value completely.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>SYNCBUSY2</name>
<!-- the display name is an unrestricted string. -->
<displayName>SYNCBUSY2</displayName>
<description>PWM2 Synchronous Busy Status Register</description>
<addressOffset>0x90</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>S_BUSY</name>
<description>PWM Synchronous Busy\nWhen software writes CNR2/CMR2/PPR or switch PWM2 operation mode (PCR[19]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR2/CMR2/PPR or switching PWM2 operation mode (PCR[19]) to make sure the previous setting has been updated completely.\nThis bit will be set when software write CNR2/CMR2/PPR or switch PWM2 operation mode (PCR[19]) and will be cleared by hardware automatically when PWM updates these value completely.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>SYNCBUSY3</name>
<!-- the display name is an unrestricted string. -->
<displayName>SYNCBUSY3</displayName>
<description>PWM3 Synchronous Busy Status Register</description>
<addressOffset>0x94</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>S_BUSY</name>
<description>PWM Synchronous Busy\nWhen software writes CNR3/CMR3/PPR or switch PWM3 operation mode (PCR[27]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR3/CMR3/PPR or switching PWM3 operation mode (PCR[27]) to make sure the previous setting has been updated completely.\nThis bit will be set when software write CNR3/CMR3/PPR or switch PWM3 operation mode (PCR[27]) and will be cleared by hardware automatically when PWM updates these value completely.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CAPPDMACTL</name>
<!-- the display name is an unrestricted string. -->
<displayName>CAPPDMACTL</displayName>
<description>PWM PDMA Control Register</description>
<addressOffset>0xC0</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAP0PDMAEN</name>
<description>Channel 0 PDMA Enable\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel 0 PDMA function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel 0 PDMA function Enabled for the channel 0 captured data and transfer to memory</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CAP0PDMAMOD</name>
<description>Select CRLR0 or CFLR0 to Transfer PDMA\n</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reserved</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CRLR0</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>CFLR0</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Both CRLR0 and CFLR0</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CAP0RFORDER</name>
<description></description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CFLR0 is the first captured data to memory</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CRLR0 is the first captured data to memory</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CAP1PDMAEN</name>
<description>Channel 1 PDMA Enable\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel 1 PDMA function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel 1 PDMA function Enabled for the channel 1 captured data and transfer to memory</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CAP1PDMAMOD</name>
<description>Select CRLR1 or CFLR1 to Transfer PDMA\n</description>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reserved</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CRLR1</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>CFLR1</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>both CRLR1 and CFLR1</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CAP1RFORDER</name>
<description>Capture channel 1 Rising/Falling Order\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CFLR1 is the first captured data to memory</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CRLR1 is the first captured data to memory</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CAP2PDMAEN</name>
<description>Channel 2 PDMA Enable\n</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel 2 PDMA function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel 2 PDMA function Enabled for the channel 2 captured data and transfer to memory</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CAP2PDMAMOD</name>
<description>Select CRLR2 or CFLR2 to do PDMA Transfer\n</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reserved</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CRLR2</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>CFLR2</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Both CRLR2 and CFLR2</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CAP2RFORDER</name>
<description>Capture channel 2 Rising/Falling Order\n</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CFLR2 is the first captured data to memory</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CRLR2 is the first captured data to memory</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CAP3PDMAEN</name>
<description>Channel 3 PDMA enable\n</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel 3 PDMA function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel 3 PDMA function Enabled for the channel 3 captured data and transfer to memory</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CAP3PDMAMOD</name>
<description>Select CRLR3 or CFLR3 to do PDMA Transfer\n</description>
<bitOffset>25</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Reserved</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CRLR3</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>CFLR3</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Both CRLR3 and CFLR3</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CAP3RFORDER</name>
<description>Capture Channel 3 Rising/Falling Order\n</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CFLR3 is the first captured data to memory</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CRLR3 is the first captured data to memory</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CAP0PDMA</name>
<!-- the display name is an unrestricted string. -->
<displayName>CAP0PDMA</displayName>
<description>PWM PDMA Channel 0 Data Register</description>
<addressOffset>0xC4</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAP0RFPDMA</name>
<description>PDMA data register for channel 0\nit is the capturing value(CFLR0/CRLR0) for channel 0</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CAP1PDMA</name>
<!-- the display name is an unrestricted string. -->
<displayName>CAP1PDMA</displayName>
<description>PWM PDMA Channel 1 Data Register</description>
<addressOffset>0xC8</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAP1RFPDMA</name>
<description>PDMA data register for channel 1\nit is the capturing value(CFLR1/CRLR1) for channel 1</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CAP2PDMA</name>
<!-- the display name is an unrestricted string. -->
<displayName>CAP2PDMA</displayName>
<description>PWM PDMA Channel 2 Data Register</description>
<addressOffset>0xCC</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAP2RFPDMA</name>
<description>PDMA data register for channel 2\nit is the capturing value(CFLR2/CRLR2) for channel 2</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CAP3PDMA</name>
<!-- the display name is an unrestricted string. -->
<displayName>CAP3PDMA</displayName>
<description>PWM PDMA Channel 3 Data Register</description>
<addressOffset>0xD0</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CAP3RFPDMA</name>
<description>PDMA data register for channel 3\nit is the capturing value(CFLR3/CRLR3) for channel 3</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SPI0</name>
<description>SPI Register Map</description>
<groupName>SPI</groupName>
<baseAddress>0x40030000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x10</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x20</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x34</offset>
<size>0x14</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SPI_CNTRL</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_CNTRL</displayName>
<description>Control and Status Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x05003004</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GO_BUSY</name>
<description>SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA finishes the data transfer.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data transfer stopped</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RX_NEG</name>
<description>Receive on Negative Edge\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Received data input signal is latched on the rising edge of SPICLK</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Received data input signal is latched on the falling edge of SPICLK</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TX_NEG</name>
<description>Transmit on Negative Edge\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitted data output signal is changed on the rising edge of SPICLK</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitted data output signal is changed on the falling edge of SPICLK</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TX_BIT_LEN</name>
<description>Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n</description>
<bitOffset>3</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LSB</name>
<description>Send LSB First\n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CLKP</name>
<description>Clock Polarity\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPICLK is idle low</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPICLK is idle high</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SP_CYCLE</name>
<description>Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPICLK clock cycle.</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IF</name>
<description>Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No transaction has been finished since this bit was cleared to 0</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI controller has finished one unit transfer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IE</name>
<description>Unit Transfer Interrupt Enable\n</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI unit transfer interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI unit transfer interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SLAVE</name>
<description>Slave Mode Enable\n</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Master mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slave mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>REORDER</name>
<description>Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\n In Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\n The byte reorder function is not supported when the variable serial clock function or Dual I/O mode is enabled.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Byte reorder function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>FIFO</name>
<description>FIFO Mode Enable\nNote:\nBefore enabling FIFO mode, the other related settings should be set in advance.\nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after data is written into the FIFO buffer by software; the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FIFO mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FIFO mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TWOB</name>
<description>2-Bit Mode Enable\nNote: When 2-bit mode is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>2-bit mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>2-bit mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>VARCLK_EN</name>
<description>Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode).</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Serial clock output frequency is fixed and decided only by the value of DIVIDER</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RX_EMPTY</name>
<description>Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO buffer is not empty</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO buffer is empty</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>RX_FULL</name>
<description>Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIOF buffer is not full</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO buffer is full</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>TX_EMPTY</name>
<description>Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].\n</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO buffer is not empty</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO buffer is empty</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>TX_FULL</name>
<description>Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO buffer is not full</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO buffer is full</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>SPI_DIVIDER</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_DIVIDER</displayName>
<description>Clock Divider Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIVIDER</name>
<description>Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI engine clock source, which is defined in the CLKSEL1 register.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DIVIDER2</name>
<description>Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning.</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPI_SSR</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_SSR</displayName>
<description>Slave Select Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SSR</name>
<description>Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state; writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL. \nNote: SPISSx0 is defined as the slave select input in Slave mode.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SS_LVL</name>
<description>Slave Select Active Level\nThis bit defines the active status of slave select signal (SPISSx0/1).\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The slave select signal SPISSx0/1 is active on low-level/falling-edge</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The slave select signal SPISSx0/1 is active on high-level/rising-edge</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>AUTOSS</name>
<description>Automatic Slave Select Function Enable (Master Only)\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0]</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SS_LTRIG</name>
<description>Slave Select Level Trigger Enable (Slave Only)\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>LTRIG_FLAG</name>
<description>Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transferred bit length of one transaction does not meet the specified requirement</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transferred bit length meets the specified requirement which defined in TX_BIT_LEN</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPI_RX0</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_RX0</displayName>
<description>Data Receive Register 0</description>
<addressOffset>0x10</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RX</name>
<description>Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register derivedFrom="SPI_RX0">
<name>SPI_RX1</name>
<displayName>SPI_RX1</displayName>
<description>Data Receive Registe 1</description>
<addressOffset>0x14</addressOffset>
</register>
<register>
<name>SPI_TX0</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_TX0</displayName>
<description>Data Transmit Register 0</description>
<addressOffset>0x20</addressOffset>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TX</name>
<description>Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register derivedFrom="SPI_TX0">
<name>SPI_TX1</name>
<displayName>SPI_TX1</displayName>
<description>Data Transmit Register 1</description>
<addressOffset>0x24</addressOffset>
</register>
<register>
<name>SPI_VARCLK</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_VARCLK</displayName>
<description>Variable Clock Pattern Register</description>
<addressOffset>0x34</addressOffset>
<access>read-write</access>
<resetValue>0x007FFF87</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VARCLK</name>
<description>Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the "Variable Clock Function" paragraph for more detail description.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPI_DMA</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_DMA</displayName>
<description>SPI DMA Control Register</description>
<addressOffset>0x38</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TX_DMA_GO</name>
<description>Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit PDMA function is used to transfer data, the GO_BUSY bit should not be set to 1 by software. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn Slave mode and when FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI serial clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 serial clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit Transfer mode is enabled, additional 18 APB clock periods for the above conditions is required.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RX_DMA_GO</name>
<description>Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit should be set by software.\nEnabling FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn Slave mode and when FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave engine clock periods + 4 APB clock periods) for edge-trigger mode or (9.5 SPI slave engine clock periods + 4 APB clock periods) for level-trigger mode.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PDMA_RST</name>
<description>PDMA Reset\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPI_CNTRL2</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_CNTRL2</displayName>
<description>Control and Status Register 2</description>
<addressOffset>0x3C</addressOffset>
<access>read-write</access>
<resetValue>0x00001000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>NOSLVSEL</name>
<description>Slave 3-Wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>4-wire bi-direction interface</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>3-wire bi-direction interface</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SLV_ABORT</name>
<description>Slave 3-Wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SSTA_INTEN</name>
<description>Slave 3-Wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transaction start interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SLV_START_INTSTS</name>
<description>Slave 3-Wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DUAL_IO_DIR</name>
<description>Dual I/O Mode Direction Control\n</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Dual Input mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Dual Output mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DUAL_IO_EN</name>
<description>Dual I/O Mode Enable\n</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Dual I/O mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Dual I/O mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SS_INT_OPT</name>
<description>Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>As the slave select signal goes to inactive level, the IF bit will NOT be set to 1</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>As the slave select signal goes to inactive level, the IF bit will be set to 1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BCn</name>
<description>SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Backward compatible clock configuration</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock configuration is not backward compatible</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPI_FIFO_CTL</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_FIFO_CTL</displayName>
<description>SPI FIFO Control Register</description>
<addressOffset>0x40</addressOffset>
<access>read-write</access>
<resetValue>0x44000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RX_CLR</name>
<description>Clear Receive FIFO Buffer\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TX_CLR</name>
<description>Clear Transmit FIFO Buffer\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RX_INTEN</name>
<description>Receive Threshold Interrupt Enable\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RX threshold interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RX threshold interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TX_INTEN</name>
<description>Transmit Threshold Interrupt Enable\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TX threshold interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TX threshold interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RXOV_INTEN</name>
<description>Receive FIFO Overrun Interrupt Enable\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO overrun interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO overrun interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TIMEOUT_INTEN</name>
<description>Receive FIFO Time-out Interrupt Enable \n</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Time-out interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Time-out interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RX_THRESHOLD</name>
<description>Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TX_THRESHOLD</name>
<description>Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPI_STATUS</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_STATUS</displayName>
<description>SPI Status Register</description>
<addressOffset>0x44</addressOffset>
<access>read-write</access>
<resetValue>0x05000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RX_INTSTS</name>
<description>Receive FIFO Threshold Interrupt Status (Read Only)\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>RX_OVERRUN</name>
<description>Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TX_INTSTS</name>
<description>Transmit FIFO Threshold Interrupt Status (Read Only)\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>SLV_START_INTSTS</name>
<description>Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RX_FIFO_COUNT</name>
<description>Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>IF</name>
<description>SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No transaction has been finished since this bit was cleared to 0</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI controller has finished one unit transfer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TIMEOUT</name>
<description>Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive FIFO time-out event</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RX_EMPTY</name>
<description>Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO buffer is not empty</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO buffer is empty</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>RX_FULL</name>
<description>Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO buffer is not empty</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO buffer is empty</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>TX_EMPTY</name>
<description>Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO buffer is not empty</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO buffer is empty</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>TX_FULL</name>
<description>Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO buffer is not full</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO buffer is full</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>TX_FIFO_COUNT</name>
<description>Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SPI1</name>
<description>SPI Register Map</description>
<groupName>SPI</groupName>
<baseAddress>0x40034000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x10</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x20</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x34</offset>
<size>0x14</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SPI_CNTRL</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_CNTRL</displayName>
<description>Control and Status Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x05003004</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GO_BUSY</name>
<description>SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA finishes the data transfer.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data transfer stopped</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RX_NEG</name>
<description>Receive on Negative Edge\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Received data input signal is latched on the rising edge of SPICLK</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Received data input signal is latched on the falling edge of SPICLK</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TX_NEG</name>
<description>Transmit on Negative Edge\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitted data output signal is changed on the rising edge of SPICLK</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitted data output signal is changed on the falling edge of SPICLK</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TX_BIT_LEN</name>
<description>Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n</description>
<bitOffset>3</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LSB</name>
<description>Send LSB First\n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CLKP</name>
<description>Clock Polarity\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPICLK is idle low</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPICLK is idle high</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SP_CYCLE</name>
<description>Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPICLK clock cycle.</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IF</name>
<description>Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No transaction has been finished since this bit was cleared to 0</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI controller has finished one unit transfer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IE</name>
<description>Unit Transfer Interrupt Enable\n</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI unit transfer interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI unit transfer interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SLAVE</name>
<description>Slave Mode Enable\n</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Master mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slave mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>REORDER</name>
<description>Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\n In Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\n The byte reorder function is not supported when the variable serial clock function or Dual I/O mode is enabled.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Byte reorder function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>FIFO</name>
<description>FIFO Mode Enable\nNote:\nBefore enabling FIFO mode, the other related settings should be set in advance.\nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after data is written into the FIFO buffer by software; the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FIFO mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FIFO mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TWOB</name>
<description>2-Bit Mode Enable\nNote: When 2-bit mode is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>2-bit mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>2-bit mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>VARCLK_EN</name>
<description>Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode).</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Serial clock output frequency is fixed and decided only by the value of DIVIDER</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RX_EMPTY</name>
<description>Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO buffer is not empty</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO buffer is empty</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>RX_FULL</name>
<description>Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIOF buffer is not full</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO buffer is full</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>TX_EMPTY</name>
<description>Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].\n</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO buffer is not empty</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO buffer is empty</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>TX_FULL</name>
<description>Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO buffer is not full</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO buffer is full</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>SPI_DIVIDER</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_DIVIDER</displayName>
<description>Clock Divider Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIVIDER</name>
<description>Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI engine clock source, which is defined in the CLKSEL1 register.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DIVIDER2</name>
<description>Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning.</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPI_SSR</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_SSR</displayName>
<description>Slave Select Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SSR</name>
<description>Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state; writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL. \nNote: SPISSx0 is defined as the slave select input in Slave mode.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SS_LVL</name>
<description>Slave Select Active Level\nThis bit defines the active status of slave select signal (SPISSx0/1).\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The slave select signal SPISSx0/1 is active on low-level/falling-edge</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The slave select signal SPISSx0/1 is active on high-level/rising-edge</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>AUTOSS</name>
<description>Automatic Slave Select Function Enable (Master Only)\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0]</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SS_LTRIG</name>
<description>Slave Select Level Trigger Enable (Slave Only)\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>LTRIG_FLAG</name>
<description>Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transferred bit length of one transaction does not meet the specified requirement</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transferred bit length meets the specified requirement which defined in TX_BIT_LEN</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPI_RX0</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_RX0</displayName>
<description>Data Receive Register 0</description>
<addressOffset>0x10</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RX</name>
<description>Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register derivedFrom="SPI_RX0">
<name>SPI_RX1</name>
<displayName>SPI_RX1</displayName>
<description>Data Receive Register 1</description>
<addressOffset>0x14</addressOffset>
</register>
<register>
<name>SPI_TX0</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_TX0</displayName>
<description>Data Transmit Register 0</description>
<addressOffset>0x20</addressOffset>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TX</name>
<description>Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register derivedFrom="SPI_TX0">
<name>SPI_TX1</name>
<displayName>SPI_TX1</displayName>
<description>Data Transmit Register 1</description>
<addressOffset>0x24</addressOffset>
</register>
<register>
<name>SPI_VARCLK</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_VARCLK</displayName>
<description>Variable Clock Pattern Register</description>
<addressOffset>0x34</addressOffset>
<access>read-write</access>
<resetValue>0x007FFF87</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VARCLK</name>
<description>Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the "Variable Clock Function" paragraph for more detail description.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPI_DMA</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_DMA</displayName>
<description>SPI DMA Control Register</description>
<addressOffset>0x38</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TX_DMA_GO</name>
<description>Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit PDMA function is used to transfer data, the GO_BUSY bit should not be set to 1 by software. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn Slave mode and when FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI serial clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 serial clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit Transfer mode is enabled, additional 18 APB clock periods for the above conditions is required.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RX_DMA_GO</name>
<description>Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit should be set by software.\nEnabling FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn Slave mode and when FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave engine clock periods + 4 APB clock periods) for edge-trigger mode or (9.5 SPI slave engine clock periods + 4 APB clock periods) for level-trigger mode.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PDMA_RST</name>
<description>PDMA Reset\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPI_CNTRL2</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_CNTRL2</displayName>
<description>Control and Status Register 2</description>
<addressOffset>0x3C</addressOffset>
<access>read-write</access>
<resetValue>0x00001000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>NOSLVSEL</name>
<description>Slave 3-Wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>4-wire bi-direction interface</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>3-wire bi-direction interface</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SLV_ABORT</name>
<description>Slave 3-Wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SSTA_INTEN</name>
<description>Slave 3-Wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transaction start interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SLV_START_INTSTS</name>
<description>Slave 3-Wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DUAL_IO_DIR</name>
<description>Dual I/O Mode Direction Control\n</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Dual Input mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Dual Output mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DUAL_IO_EN</name>
<description>Dual I/O Mode Enable\n</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Dual I/O mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Dual I/O mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SS_INT_OPT</name>
<description>Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>As the slave select signal goes to inactive level, the IF bit will NOT be set to 1</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>As the slave select signal goes to inactive level, the IF bit will be set to 1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BCn</name>
<description>SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Backward compatible clock configuration</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock configuration is not backward compatible</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPI_FIFO_CTL</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_FIFO_CTL</displayName>
<description>SPI FIFO Control Register</description>
<addressOffset>0x40</addressOffset>
<access>read-write</access>
<resetValue>0x44000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RX_CLR</name>
<description>Clear Receive FIFO Buffer\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TX_CLR</name>
<description>Clear Transmit FIFO Buffer\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RX_INTEN</name>
<description>Receive Threshold Interrupt Enable\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RX threshold interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RX threshold interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TX_INTEN</name>
<description>Transmit Threshold Interrupt Enable\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TX threshold interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TX threshold interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RXOV_INTEN</name>
<description>Receive FIFO Overrun Interrupt Enable\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO overrun interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO overrun interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TIMEOUT_INTEN</name>
<description>Receive FIFO Time-out Interrupt Enable \n</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Time-out interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Time-out interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RX_THRESHOLD</name>
<description>Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TX_THRESHOLD</name>
<description>Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPI_STATUS</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_STATUS</displayName>
<description>SPI Status Register</description>
<addressOffset>0x44</addressOffset>
<access>read-write</access>
<resetValue>0x05000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RX_INTSTS</name>
<description>Receive FIFO Threshold Interrupt Status (Read Only)\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>RX_OVERRUN</name>
<description>Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TX_INTSTS</name>
<description>Transmit FIFO Threshold Interrupt Status (Read Only)\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>SLV_START_INTSTS</name>
<description>Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RX_FIFO_COUNT</name>
<description>Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>IF</name>
<description>SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No transaction has been finished since this bit was cleared to 0</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI controller has finished one unit transfer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TIMEOUT</name>
<description>Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive FIFO time-out event</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RX_EMPTY</name>
<description>Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO buffer is not empty</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO buffer is empty</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>RX_FULL</name>
<description>Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO buffer is not empty</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO buffer is empty</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>TX_EMPTY</name>
<description>Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO buffer is not empty</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO buffer is empty</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>TX_FULL</name>
<description>Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO buffer is not full</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO buffer is full</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>TX_FIFO_COUNT</name>
<description>Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SPI2</name>
<description>SPI Register Map</description>
<groupName>SPI</groupName>
<baseAddress>0x40130000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x10</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x20</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x34</offset>
<size>0x14</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SPI_CNTRL</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_CNTRL</displayName>
<description>Control and Status Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x05003004</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>GO_BUSY</name>
<description>SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA finishes the data transfer.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data transfer stopped</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>In Master mode, writing 1 to this bit to start the SPI data transfer; in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RX_NEG</name>
<description>Receive on Negative Edge\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Received data input signal is latched on the rising edge of SPICLK</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Received data input signal is latched on the falling edge of SPICLK</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TX_NEG</name>
<description>Transmit on Negative Edge\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmitted data output signal is changed on the rising edge of SPICLK</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmitted data output signal is changed on the falling edge of SPICLK</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TX_BIT_LEN</name>
<description>Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n</description>
<bitOffset>3</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LSB</name>
<description>Send LSB First\n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CLKP</name>
<description>Clock Polarity\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPICLK is idle low</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPICLK is idle high</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SP_CYCLE</name>
<description>Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPICLK clock cycle.</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IF</name>
<description>Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No transaction has been finished since this bit was cleared to 0</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI controller has finished one unit transfer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>IE</name>
<description>Unit Transfer Interrupt Enable\n</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>SPI unit transfer interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI unit transfer interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SLAVE</name>
<description>Slave Mode Enable\n</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Master mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slave mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>REORDER</name>
<description>Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\n In Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\n The byte reorder function is not supported when the variable serial clock function or Dual I/O mode is enabled.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Byte reorder function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>FIFO</name>
<description>FIFO Mode Enable\nNote:\nBefore enabling FIFO mode, the other related settings should be set in advance.\nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after data is written into the FIFO buffer by software; the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>FIFO mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FIFO mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TWOB</name>
<description>2-Bit Mode Enable\nNote: When 2-bit mode is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>2-bit mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>2-bit mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>VARCLK_EN</name>
<description>Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode).</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Serial clock output frequency is fixed and decided only by the value of DIVIDER</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RX_EMPTY</name>
<description>Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO buffer is not empty</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO buffer is empty</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>RX_FULL</name>
<description>Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIOF buffer is not full</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO buffer is full</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>TX_EMPTY</name>
<description>Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].\n</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO buffer is not empty</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO buffer is empty</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>TX_FULL</name>
<description>Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO buffer is not full</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO buffer is full</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>SPI_DIVIDER</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_DIVIDER</displayName>
<description>Clock Divider Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DIVIDER</name>
<description>Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI engine clock source, which is defined in the CLKSEL1 register.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DIVIDER2</name>
<description>Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning.</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPI_SSR</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_SSR</displayName>
<description>Slave Select Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SSR</name>
<description>Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.\nIf the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state; writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL. \nNote: SPISSx0 is defined as the slave select input in Slave mode.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SS_LVL</name>
<description>Slave Select Active Level\nThis bit defines the active status of slave select signal (SPISSx0/1).\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The slave select signal SPISSx0/1 is active on low-level/falling-edge</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The slave select signal SPISSx0/1 is active on high-level/rising-edge</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>AUTOSS</name>
<description>Automatic Slave Select Function Enable (Master Only)\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0]</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SS_LTRIG</name>
<description>Slave Select Level Trigger Enable (Slave Only)\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>LTRIG_FLAG</name>
<description>Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transferred bit length of one transaction does not meet the specified requirement</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transferred bit length meets the specified requirement which defined in TX_BIT_LEN</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPI_RX0</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_RX0</displayName>
<description>Data Receive Register 0</description>
<addressOffset>0x10</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RX</name>
<description>Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register derivedFrom="SPI_RX0">
<name>SPI_RX1</name>
<displayName>SPI_RX1</displayName>
<description>Data Receive Register 1</description>
<addressOffset>0x14</addressOffset>
</register>
<register>
<name>SPI_TX0</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_TX0</displayName>
<description>Data Transmit Register 0</description>
<addressOffset>0x20</addressOffset>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TX</name>
<description>Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register derivedFrom="SPI_TX0">
<name>SPI_TX1</name>
<displayName>SPI_TX1</displayName>
<description>Data Transmit Register 1</description>
<addressOffset>0x24</addressOffset>
</register>
<register>
<name>SPI_VARCLK</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_VARCLK</displayName>
<description>Variable Clock Pattern Register</description>
<addressOffset>0x34</addressOffset>
<access>read-write</access>
<resetValue>0x007FFF87</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>VARCLK</name>
<description>Variable Clock Pattern\nThis register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the "Variable Clock Function" paragraph for more detail description.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPI_DMA</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_DMA</displayName>
<description>SPI DMA Control Register</description>
<addressOffset>0x38</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TX_DMA_GO</name>
<description>Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit PDMA function is used to transfer data, the GO_BUSY bit should not be set to 1 by software. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn Slave mode and when FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI serial clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 serial clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit Transfer mode is enabled, additional 18 APB clock periods for the above conditions is required.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RX_DMA_GO</name>
<description>Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit should be set by software.\nEnabling FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn Slave mode and when FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave engine clock periods + 4 APB clock periods) for edge-trigger mode or (9.5 SPI slave engine clock periods + 4 APB clock periods) for level-trigger mode.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PDMA_RST</name>
<description>PDMA Reset\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPI_CNTRL2</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_CNTRL2</displayName>
<description>Control and Status Register 2</description>
<addressOffset>0x3C</addressOffset>
<access>read-write</access>
<resetValue>0x00001000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>NOSLVSEL</name>
<description>Slave 3-Wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>4-wire bi-direction interface</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>3-wire bi-direction interface</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SLV_ABORT</name>
<description>Slave 3-Wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SSTA_INTEN</name>
<description>Slave 3-Wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transaction start interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SLV_START_INTSTS</name>
<description>Slave 3-Wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DUAL_IO_DIR</name>
<description>Dual I/O Mode Direction Control\n</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Dual Input mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Dual Output mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DUAL_IO_EN</name>
<description>Dual I/O Mode Enable\n</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Dual I/O mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Dual I/O mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SS_INT_OPT</name>
<description>Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>As the slave select signal goes to inactive level, the IF bit will NOT be set to 1</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>As the slave select signal goes to inactive level, the IF bit will be set to 1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BCn</name>
<description>SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Backward compatible clock configuration</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clock configuration is not backward compatible</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPI_FIFO_CTL</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_FIFO_CTL</displayName>
<description>SPI FIFO Control Register</description>
<addressOffset>0x40</addressOffset>
<access>read-write</access>
<resetValue>0x44000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RX_CLR</name>
<description>Clear Receive FIFO Buffer\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TX_CLR</name>
<description>Clear Transmit FIFO Buffer\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RX_INTEN</name>
<description>Receive Threshold Interrupt Enable\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RX threshold interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RX threshold interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TX_INTEN</name>
<description>Transmit Threshold Interrupt Enable\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TX threshold interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TX threshold interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RXOV_INTEN</name>
<description>Receive FIFO Overrun Interrupt Enable\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO overrun interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO overrun interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TIMEOUT_INTEN</name>
<description>Receive FIFO Time-out Interrupt Enable \n</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Time-out interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Time-out interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RX_THRESHOLD</name>
<description>Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TX_THRESHOLD</name>
<description>Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SPI_STATUS</name>
<!-- the display name is an unrestricted string. -->
<displayName>SPI_STATUS</displayName>
<description>SPI Status Register</description>
<addressOffset>0x44</addressOffset>
<access>read-write</access>
<resetValue>0x05000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RX_INTSTS</name>
<description>Receive FIFO Threshold Interrupt Status (Read Only)\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>RX_OVERRUN</name>
<description>Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TX_INTSTS</name>
<description>Transmit FIFO Threshold Interrupt Status (Read Only)\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>SLV_START_INTSTS</name>
<description>Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RX_FIFO_COUNT</name>
<description>Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>IF</name>
<description>SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No transaction has been finished since this bit was cleared to 0</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>SPI controller has finished one unit transfer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TIMEOUT</name>
<description>Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive FIFO time-out event</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RX_EMPTY</name>
<description>Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO buffer is not empty</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO buffer is empty</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>RX_FULL</name>
<description>Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receive FIFO buffer is not empty</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive FIFO buffer is empty</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>TX_EMPTY</name>
<description>Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO buffer is not empty</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO buffer is empty</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>TX_FULL</name>
<description>Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit FIFO buffer is not full</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit FIFO buffer is full</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>TX_FIFO_COUNT</name>
<description>Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TMR01</name>
<description>TIMER Register Map</description>
<groupName>TIMER</groupName>
<baseAddress>0x40010000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x1C</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x20</offset>
<size>0x1C</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>TCSR0</name>
<!-- the display name is an unrestricted string. -->
<displayName>TCSR0</displayName>
<description>Timer0 Control and Status Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x00000005</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PRESCALE</name>
<description>Pre-scale Counter\n</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TDR_EN</name>
<description>Data Load Enable\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer Data Register update Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer Data Register update Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>WAKE_EN</name>
<description>Wake-up Enable\nWhen WAKE_EN is set and the TIF is set, the timer controller will generator a wake-up trigger event to CPU.\n</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Wake-up trigger event Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Wake-up trigger event Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CTB</name>
<description>Counter Mode Enable Bit \nThis bit is the counter mode enable bit. When Timer is used as an event counter, this bit should be set to 1 and Timer will work as an event counter. The counter detect phase can be selected as rising/falling edge of external pin by TX_PHASE field.\n</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Counter mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Counter mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CACT</name>
<description>Timer Active Status Bit (Read only)\nThis bit indicates the up-timer status.\n</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer is not active</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer is active</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>CRST</name>
<description>Timer Reset Bit\nSet this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0.\n</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset Timer's 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>MODE</name>
<description>Timer Operating Mode\n</description>
<bitOffset>27</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IE</name>
<description>Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal when the associated up-timer value is equal to TCMPR.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer Interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer Interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CEN</name>
<description>Timer Enable Bit\n</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stops/Suspends counting</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Starts counting</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBGACK_TMR</name>
<description>ICE debug mode acknowledge Disable (Write-protection Bit)\nTIMER counter will keep going no matter ICE debug mode acknowledged or not.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ICE debug mode acknowledgement effects TIMER counting</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ICE debug mode acknowledgement disabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TCMPR0</name>
<!-- the display name is an unrestricted string. -->
<displayName>TCMPR0</displayName>
<description>Timer0 Compare Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TCMP</name>
<description>Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state.\nNote2: When timer is operating in continuous counting mode, the 24-bit up-timer will count continuously if software writes a new value into TCMP. If timer is operating at other modes, the 24-bit up-timer will restart counting and using newest TCMP value to be the compared value if software writes a new value into TCMP.</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TISR0</name>
<!-- the display name is an unrestricted string. -->
<displayName>TISR0</displayName>
<description>Timer0 Interrupt Status Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIF</name>
<description>Timer Interrupt Flag\nThis bit indicates the interrupt status of timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit up-timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TWF</name>
<description>Timer Wakeup Flag\nIf timer causes CPU wakes up from power-down mode, this bit will be set to high.\nIt must be cleared by software with a write 1 to this bit.\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer does not cause CPU wakeup</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CPU wakes up from sleep or power-down mode by timer time-out</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TDR0</name>
<!-- the display name is an unrestricted string. -->
<displayName>TDR0</displayName>
<description>Timer0 Data Register</description>
<addressOffset>0xC</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TDR</name>
<description>Timer Data Register\nUser can read TDR for getting current 24- bits up event counter value if TCSR[24] is 1</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TCAP0</name>
<!-- the display name is an unrestricted string. -->
<displayName>TCAP0</displayName>
<description>Timer0 Capture Data Register</description>
<addressOffset>0x10</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TCAP</name>
<description>Timer Capture Data Register\nWhen TEXEN (TEXCON[3]) is set, RSTCAPn(TTXCON[4]) is 0, and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred, the internal 24-bit up-timer value will be loaded into TCAP. User can read this register for the counter value.</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TEXCON0</name>
<!-- the display name is an unrestricted string. -->
<displayName>TEXCON0</displayName>
<description>Timer0 External Control Register</description>
<addressOffset>0x14</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TX_PHASE</name>
<description>Timer External Count Phase \nThis bit indicates the external count pin phase.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A falling edge of external count pin will be counted</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A rising edge of external count pin will be counted</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TEX_EDGE</name>
<description>Timer External Pin Edge Detect\n</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>1 to 0 transition on TEX will be detected</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>0 to 1 transition on TEX will be detected</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Either 1 to 0 or 0 to 1 transition on TEX will be detected</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TEXEN</name>
<description>Timer External Pin Enable \nThis bit enables the reset/capture function on the TEX pin. \n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TEX pin will be ignored</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transition detected on the TEX pin will result in capture or reset of timer counter</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RSTCAPn</name>
<description>Timer External Reset Counter/Capture Mode Selection\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TEX transition is used as the timer capture function</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TEX transition is used as the timer counter reset function</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TEXIEN</name>
<description>Timer External Interrupt Enable Bit\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer external interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer external interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TEXDB</name>
<description>Timer External Capture Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of T0EX~T3EX pin is detected with de-bounce circuit.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>De-bounce Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>De-bounce Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TCDB</name>
<description>Timer Counter Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of TM0~TM3 pin is detected with de-bounce circuit.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>De-bounce Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>De-bounce Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TEXISR0</name>
<!-- the display name is an unrestricted string. -->
<displayName>TEXISR0</displayName>
<description>Timer0 External Interrupt Status Register</description>
<addressOffset>0x18</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TEXIF</name>
<description>Timer External Interrupt Flag\nThis bit indicates the external interrupt status of Timer.\nThis bit is set by hardware when TEXEN (TEXCON[3]) is to 1, and the transition on the TEX pins associated with TEX_EDGE (TEXCON[2:1]) setting is occurred. It is cleared by writing 1 to this bit.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register derivedFrom="TCSR0">
<name>TCSR1</name>
<displayName>TCSR1</displayName>
<description>Timer1 Control and Status Register</description>
<addressOffset>0x20</addressOffset>
</register>
<register derivedFrom="TCMPR0">
<name>TCMPR1</name>
<displayName>TCMPR1</displayName>
<description>Timer1 Compare Register</description>
<addressOffset>0x24</addressOffset>
</register>
<register derivedFrom="TISR0">
<name>TISR1</name>
<displayName>TISR1</displayName>
<description>Timer1 Interrupt Status Register</description>
<addressOffset>0x28</addressOffset>
</register>
<register derivedFrom="TDR0">
<name>TDR1</name>
<displayName>TDR1</displayName>
<description>Timer1 Data Register</description>
<addressOffset>0x2C</addressOffset>
</register>
<register derivedFrom="TCAP0">
<name>TCAP1</name>
<displayName>TCAP1</displayName>
<description>Timer1 Capture Data Register</description>
<addressOffset>0x30</addressOffset>
</register>
<register derivedFrom="TEXCON0">
<name>TEXCON1</name>
<displayName>TEXCON1</displayName>
<description>Timer1 External Control Register</description>
<addressOffset>0x34</addressOffset>
</register>
<register derivedFrom="TEXISR0">
<name>TEXISR1</name>
<displayName>TEXISR1</displayName>
<description>Timer1 External Interrupt Status Register</description>
<addressOffset>0x38</addressOffset>
</register>
</registers>
</peripheral>
<peripheral>
<name>TMR23</name>
<description>TIMER Register Map</description>
<groupName>TIMER</groupName>
<baseAddress>0x40110000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x1C</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x20</offset>
<size>0x1C</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>TCSR2</name>
<!-- the display name is an unrestricted string. -->
<displayName>TCSR2</displayName>
<description>Timer2 Control and Status Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x00000005</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PRESCALE</name>
<description>Pre-scale Counter\n</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TDR_EN</name>
<description>Data Load Enable\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer Data Register update Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer Data Register update Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>WAKE_EN</name>
<description>Wake-up Enable\nWhen WAKE_EN is set and the TIF is set, the timer controller will generator a wake-up trigger event to CPU.\n</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Wake-up trigger event Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Wake-up trigger event Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CTB</name>
<description>Counter Mode Enable Bit \nThis bit is the counter mode enable bit. When Timer is used as an event counter, this bit should be set to 1 and Timer will work as an event counter. The counter detect phase can be selected as rising/falling edge of external pin by TX_PHASE field.\n</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Counter mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Counter mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CACT</name>
<description>Timer Active Status Bit (Read only)\nThis bit indicates the up-timer status.\n</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer is not active</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer is active</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>CRST</name>
<description>Timer Reset Bit\nSet this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0.\n</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset Timer's 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>MODE</name>
<description>Timer Operating Mode\n</description>
<bitOffset>27</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IE</name>
<description>Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal when the associated up-timer value is equal to TCMPR.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer Interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer Interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CEN</name>
<description>Timer Enable Bit\n</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stops/Suspends counting</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Starts counting</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DBGACK_TMR</name>
<description>ICE debug mode acknowledge Disable (Write-protection Bit)\nTIMER counter will keep going no matter ICE debug mode acknowledged or not.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ICE debug mode acknowledgement effects TIMER counting</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ICE debug mode acknowledgement disabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TCMPR2</name>
<!-- the display name is an unrestricted string. -->
<displayName>TCMPR2</displayName>
<description>Timer2 Compare Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TCMP</name>
<description>Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state.\nNote2: When timer is operating in continuous counting mode, the 24-bit up-timer will count continuously if software writes a new value into TCMP. If timer is operating at other modes, the 24-bit up-timer will restart counting and using newest TCMP value to be the compared value if software writes a new value into TCMP.</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TISR2</name>
<!-- the display name is an unrestricted string. -->
<displayName>TISR2</displayName>
<description>Timer2 Interrupt Status Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TIF</name>
<description>Timer Interrupt Flag\nThis bit indicates the interrupt status of timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit up-timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TWF</name>
<description>Timer Wakeup Flag\nIf timer causes CPU wakes up from power-down mode, this bit will be set to high.\nIt must be cleared by software with a write 1 to this bit.\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer does not cause CPU wakeup</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CPU wakes up from sleep or power-down mode by timer time-out</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TDR2</name>
<!-- the display name is an unrestricted string. -->
<displayName>TDR2</displayName>
<description>Timer2 Data Register</description>
<addressOffset>0xC</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TDR</name>
<description>Timer Data Register\nUser can read TDR for getting current 24- bits up event counter value if TCSR[24] is 1</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TCAP2</name>
<!-- the display name is an unrestricted string. -->
<displayName>TCAP2</displayName>
<description>Timer2 Capture Data Register</description>
<addressOffset>0x10</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TCAP</name>
<description>Timer Capture Data Register\nWhen TEXEN (TEXCON[3]) is set, RSTCAPn(TTXCON[4]) is 0, and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred, the internal 24-bit up-timer value will be loaded into TCAP. User can read this register for the counter value.</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TEXCON2</name>
<!-- the display name is an unrestricted string. -->
<displayName>TEXCON2</displayName>
<description>Timer2 External Control Register</description>
<addressOffset>0x14</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TX_PHASE</name>
<description>Timer External Count Phase \nThis bit indicates the external count pin phase.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A falling edge of external count pin will be counted</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A rising edge of external count pin will be counted</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TEX_EDGE</name>
<description>Timer External Pin Edge Detect\n</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>1 to 0 transition on TEX will be detected</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>0 to 1 transition on TEX will be detected</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Either 1 to 0 or 0 to 1 transition on TEX will be detected</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TEXEN</name>
<description>Timer External Pin Enable \nThis bit enables the reset/capture function on the TEX pin. \n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TEX pin will be ignored</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transition detected on the TEX pin will result in capture or reset of timer counter</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RSTCAPn</name>
<description>Timer External Reset Counter/Capture Mode Selection\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TEX transition is used as the timer capture function</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TEX transition is used as the timer counter reset function</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TEXIEN</name>
<description>Timer External Interrupt Enable Bit\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Timer external interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Timer external interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TEXDB</name>
<description>Timer External Capture Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of T0EX~T3EX pin is detected with de-bounce circuit.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>De-bounce Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>De-bounce Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TCDB</name>
<description>Timer Counter Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of TM0~TM3 pin is detected with de-bounce circuit.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>De-bounce Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>De-bounce Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TEXISR2</name>
<!-- the display name is an unrestricted string. -->
<displayName>TEXISR2</displayName>
<description>Timer2 External Interrupt Status Register</description>
<addressOffset>0x18</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TEXIF</name>
<description>Timer External Interrupt Flag\nThis bit indicates the external interrupt status of Timer.\nThis bit is set by hardware when TEXEN (TEXCON[3]) is to 1, and the transition on the TEX pins associated with TEX_EDGE (TEXCON[2:1]) setting is occurred. It is cleared by writing 1 to this bit.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register derivedFrom="TCSR2">
<name>TCSR3</name>
<displayName>TCSR3</displayName>
<description>Timer3 Control and Status Register</description>
<addressOffset>0x20</addressOffset>
</register>
<register derivedFrom="TCMPR2">
<name>TCMPR3</name>
<displayName>TCMPR3</displayName>
<description>Timer3 Compare Register</description>
<addressOffset>0x24</addressOffset>
</register>
<register derivedFrom="TISR2">
<name>TISR3</name>
<displayName>TISR3</displayName>
<description>Timer3 Interrupt Status Register</description>
<addressOffset>0x28</addressOffset>
</register>
<register derivedFrom="TDR2">
<name>TDR3</name>
<displayName>TDR3</displayName>
<description>Timer3 Data Register</description>
<addressOffset>0x2C</addressOffset>
</register>
<register derivedFrom="TCAP2">
<name>TCAP3</name>
<displayName>TCAP3</displayName>
<description>Timer3 Capture Data Register</description>
<addressOffset>0x30</addressOffset>
</register>
<register derivedFrom="TEXCON2">
<name>TEXCON3</name>
<displayName>TEXCON3</displayName>
<description>Timer3 External Control Register</description>
<addressOffset>0x34</addressOffset>
</register>
<register derivedFrom="TEXISR2">
<name>TEXISR3</name>
<displayName>TEXISR3</displayName>
<description>Timer3 External Interrupt Status Register</description>
<addressOffset>0x38</addressOffset>
</register>
</registers>
</peripheral>
<peripheral>
<name>WDT</name>
<description>WDT Register Map</description>
<groupName>WDT</groupName>
<baseAddress>0x40004000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>WTCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>WTCR</displayName>
<description>Watchdog Timer Control Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x00000700</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WTR</name>
<description>Clear Watchdog Timer (Write-protection Bit)\nSetting this bit will clear the Watchdog timer.\nNote: This bit will be automatically cleared by hardware.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset the contents of the Watchdog timer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>WTRE</name>
<description>Watchdog Timer Reset Enable (Write-protection Bit)\nSetting this bit will enable the Watchdog timer reset function.\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Watchdog timer reset function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Watchdog timer reset function Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>WTRF</name>
<description>Watchdog Timer Reset Flag\nWhen the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If WTRE is disabled, the Watchdog timer has no effect on this bit.\nNote: This bit is cleared by writing 1 to this bit.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Watchdog timer reset did not occur</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Watchdog timer reset occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>WTIF</name>
<description>Watchdog Timer Interrupt Flag\nIf the Watchdog timer interrupt is enabled, the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred.\nNote: This bit is cleared by writing 1 to this bit.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Watchdog timer interrupt did not occur</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Watchdog timer interrupt occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>WTWKE</name>
<description>Watchdog Timer Wake-up Function Enable bit (Write-protection Bit)\nNote: Chip can be woken up by WDT only if WDT clock source select RC10K.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Watchdog timer Wake-up chip function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Wake-up function Enabled so that Watchdog timer time-out can wake-up chip from Power-down mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>WTWKF</name>
<description>Watchdog Timer Wake-up Flag\nIf Watchdog timer causes chip to wake up from Power-down mode, this bit will be set to high. It must be cleared by software by writing 1 to this bit.\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Watchdog timer does not cause chip wake up</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Chip woken up from Idle or Power-down mode by Watchdog time-out</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>WTIE</name>
<description>Watchdog Timer Interrupt Enable (Write-protection Bit)\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Watchdog timer interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Watchdog timer interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>WTE</name>
<description>Watchdog Timer Enable (Write-protection Bit)\n</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Watchdog timer Disabled (This action will reset the internal counter)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Watchdog timer Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>WTIS</name>
<description>Watchdog Timer Interval Selection (Write-protection Bit)\n</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DBGACK_WDT</name>
<description>ICE Debug Mode Acknowledge Disable (Write-protection Bit)\nWatchdog Timer counter will keep going no matter ICE debug mode acknowledged or not.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>ICE debug mode acknowledgement affects Watchdog Timer counting</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>ICE debug mode acknowledgement Disabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WTCRALT</name>
<!-- the display name is an unrestricted string. -->
<displayName>WTCRALT</displayName>
<description>Watchdog Timer Alternative Control Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WTRDSEL</name>
<description>Watchdog Timer Reset Delay Select (Write-protection Bits)\nWhen watchdog time-out happened, software has a time named watchdog reset delay period to clear watchdog timer to prevent watchdog reset happened. Software can select a suitable value of watchdog reset delay period for different watchdog time-out period.\nThese bits are protected bit. It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.\nThis register will be reset if watchdog reset happened</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Watchdog reset delay period is 1024 watchdog clock</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Watchdog reset delay period is 128 watchdog clock</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Watchdog reset delay period is 16 watchdog clock</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Watchdog reset delay period is 1 watchdog clock</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>WWDT</name>
<description>WWDT Register Map</description>
<groupName>WWDT</groupName>
<baseAddress>0x40004100</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x10</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>WWDTRLD</name>
<!-- the display name is an unrestricted string. -->
<displayName>WWDTRLD</displayName>
<description>Window Watchdog Timer Reload Counter Register</description>
<addressOffset>0x0</addressOffset>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WWDTRLD</name>
<description>WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. \nNote: Software can only write WWDTRLD when WWDT counter value between 0 and WINCMP. If software writes WWDTRLD when WWDT counter value larger than WINCMP, WWDT will generate RESET signal.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>WWDTCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>WWDTCR</displayName>
<description>Window Watchdog Timer Control Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x003F0800</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WWDTEN</name>
<description>WWDT Enable\nSet this bit to enable the Window Watchdog timer.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Window Watchdog timer function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Window Watchdog timer function Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>WWDTIE</name>
<description>WWDT Interrupt Enable\nSet this bit to enable the Watchdog timer interrupt function.\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Watchdog timer interrupt function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Watchdog timer interrupt function Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PERIODSEL</name>
<description>WWDT Pre-scale Period Select\n</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WINCMP</name>
<description>WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: Software can only write WWDTRLD when WWDT counter value between 0 and WINCMP. If software writes WWDTRLD when WWDT counter value is larger than WWCMP, WWDT will generate RESET signal.</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DBGACK_WWDT</name>
<description>ICE debug mode acknowledge Disable\n</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>WWDT count stopped if system is in Debug mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>WWDT still count even system is in Debug mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WWDTSTS</name>
<!-- the display name is an unrestricted string. -->
<displayName>WWDTSTS</displayName>
<description>Window Watchdog Timer Status Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WWDTIF</name>
<description>WWDT Compare Match Interrupt Flag\nWhen WWCMP matches the WWDT counter, this bit is set to 1. This bit will be cleared by software write 1 to this bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WWDTRF</name>
<description>WWDT Reset Flag\nWhen WWDT counter counts down to 0 or writes WWDTRLD during WWDT counter larger than WINCMP, chip will be reset and this bit is set to 1. Software can write 1 to clear this bit to 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WWDTCVR</name>
<!-- the display name is an unrestricted string. -->
<displayName>WWDTCVR</displayName>
<description>Window Watchdog Counter Value Register</description>
<addressOffset>0xC</addressOffset>
<access>read-only</access>
<resetValue>0x0000003F</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WWDTCVAL</name>
<description>WWDT Counter Value\nThis register reflects the counter value of window watchdog. This register is read only.</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UART0</name>
<description>UART Register Map</description>
<groupName>UART</groupName>
<baseAddress>0x40050000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x34</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>UA_RBR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_RBR</displayName>
<description>UART Receive Buffer Register</description>
<addressOffset>0x0</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RBR</name>
<description>Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UA_THR</name>
<alternateRegister>UA_RBR</alternateRegister>
<!-- the display name is an unrestricted string. -->
<displayName>UA_THR</displayName>
<description>UART Transmit Holding Register</description>
<addressOffset>0x0</addressOffset>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>THR</name>
<description>Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>UA_IER</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_IER</displayName>
<description>UART Interrupt Enable Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDA_IEN</name>
<description>Receive Data Available Interrupt Enable.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>INT_RDA Masked off</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>INT_RDA Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>THRE_IEN</name>
<description>Transmit Holding Register Empty Interrupt Enable\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>INT_THRE Masked off</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>INT_THRE Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RLS_IEN</name>
<description>Receive Line Status Interrupt Enable \n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>INT_RLS Masked off</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>INT_RLS Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>MODEM_IEN</name>
<description>Modem Status Interrupt Enable\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>INT_MODEM Masked off</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>INT_MODEM Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RTO_IEN</name>
<description>RX Time Out Interrupt Enable\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>INT_TOUT Masked off</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>INT_TOUT Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BUF_ERR_IEN</name>
<description>Buffer Error Interrupt Enable\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>INT_BUF_ERR Masked off</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>INT_BUF_ERR Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>WAKE_EN</name>
<description>UART Wake-up Function Enable\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART wake-up function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART wake-up function Enabled, when chip is in Power-down mode, an external CTS change will wake up chip from Power-down mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TIME_OUT_EN</name>
<description>Time Out Counter Enable\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Time-out counter Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Time-out counter Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>AUTO_RTS_EN</name>
<description>RTS Auto Flow Control Enable\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO is equal to the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTS signal.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RTS auto flow control Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RTS auto flow control Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>AUTO_CTS_EN</name>
<description>CTS Auto Flow Control Enable \nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CTS auto flow control Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CTS auto flow control Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMA_TX_EN</name>
<description>TX DMA Enable\nThis bit can enable or disable TX DMA service.\n</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TX DMA Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TX DMA Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMA_RX_EN</name>
<description>RX DMA Enable\nThis bit can enable or disable RX DMA service.\n</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RX DMA Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RX DMA Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UA_FCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_FCR</displayName>
<description>UART FIFO Control Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000101</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RFR</name>
<description>RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will be automatically cleared at least 3 UART engine clock cycles.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset the RX internal state machine and pointers</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TFR</name>
<description>TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will be automatically cleared at least 3 UART engine clock cycles.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset the TX internal state machine and pointers</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RFITL</name>
<description>RX FIFO Interrupt (INT_RDA) Trigger Level\n</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RX_DIS</name>
<description>Receiver Disable Register\nThe receiver is enabled or disabled.\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver Disabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RTS_TRI_LEV</name>
<description>RTS Trigger Level for Auto-flow Control Use\n</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UA_LCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_LCR</displayName>
<description>UART Line Control Register</description>
<addressOffset>0xC</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WLS</name>
<description>Word Length Selection\n</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NSB</name>
<description>Number of "STOP bit"\nTwo "STOP bit" are generated when 6-, 7- and 8-bit word length is selected.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One " STOP bit" is generated in the transmitted data</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>One and a half " STOP bit" is generated in the transmitted data when 5-bit word length is selected;</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PBE</name>
<description>Parity Bit Enable\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No parity bit</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Parity bit is generated on each outgoing character and is checked on each incoming data</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>EPE</name>
<description>Even Parity Enable\nThis bit has effect only when bit 3 (parity bit enable) is set.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Odd number of logic 1's is transmitted and checked in each word</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Even number of logic 1's is transmitted and checked in each word</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SPE</name>
<description>Stick Parity Enable\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stick parity Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If bit 3 and 4 are logic 1, the parity bit is transmitted and cheched as logic 0. If bit 3 si 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BCB</name>
<description>Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UA_MCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_MCR</displayName>
<description>UART Modem Control Register</description>
<addressOffset>0x10</addressOffset>
<access>read-write</access>
<resetValue>0x00000200</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RTS</name>
<description>RTS (Request-To-Send) Signal\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Drive RTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 0 (If the LEV_RTS set to high level triggered)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Drive RTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 1 (If the LEV_RTS set to high level triggered)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>LEV_RTS</name>
<description>RTS Trigger Level\nThis bit can change the RTS trigger level.\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low level triggered</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High level triggered</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RTS_ST</name>
<description>RTS Pin State (Read Only)\nThis bit is the output pin status of RTS.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UA_MSR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_MSR</displayName>
<description>UART Modem Status Register</description>
<addressOffset>0x14</addressOffset>
<access>read-write</access>
<resetValue>0x00000110</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DCTSF</name>
<description>Detect CTS State Change Flag (Read Only)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CTS_ST</name>
<description>CTS Pin Status (Read Only)\nThis bit is the pin status of CTS.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LEV_CTS</name>
<description>CTS Trigger Level\nThis bit can change the CTS trigger level.\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low level triggered</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High level triggered</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UA_FSR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_FSR</displayName>
<description>UART FIFO Status Register</description>
<addressOffset>0x18</addressOffset>
<access>read-write</access>
<resetValue>0x10404000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RX_OVER_IF</name>
<description>RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RS485_ADD_DETF</name>
<description>RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PEF</name>
<description>Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FEF</name>
<description>Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BIF</name>
<description>Break Interrupt Flag (Read Only)\nThis bit is set to a logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RX_POINTER</name>
<description>RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one.</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RX_EMPTY</name>
<description>Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RX_FULL</name>
<description>Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RX_POINTER is equal to 64/16(UART0/UART1); otherwise, it is cleared by hardware.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TX_POINTER</name>
<description>TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one.</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TX_EMPTY</name>
<description>Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TX_FULL</name>
<description>Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TX_POINTER is equal to 64/16(UART0/UART1); otherwise, it is cleared by hardware.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TX_OVER_IF</name>
<description>TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. \nNote: This bit is read only, but can be cleared by writing '1' to it.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TE_FLAG</name>
<description>Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UA_ISR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_ISR</displayName>
<description>UART Interrupt Status Register</description>
<addressOffset>0x1C</addressOffset>
<access>read-write</access>
<resetValue>0x00000002</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDA_IF</name>
<description>Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX FIFO is equal to the RFITL, the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>THRE_IF</name>
<description>Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RLS_IF</name>
<description>Receive Line Interrupt Flag (Read Only). \nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MODEM_IF</name>
<description>MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TOUT_IF</name>
<description>Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BUF_ERR_IF</name>
<description>Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RDA_INT</name>
<description>Receive Data Available Interrupt Indicator (Read Only).\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No RDA interrupt is generated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RDA interrupt is generated</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>THRE_INT</name>
<description>Transmit Holding Register Empty Interrupt Indicator (Read Only).\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No THRE interrupt is generated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>THRE interrupt is generated</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>RLS_INT</name>
<description>Receive Line Status Interrupt Indicator (Read Only). \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No RLS interrupt is generated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RLS interrupt is generated</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>MODEM_INT</name>
<description>MODEM Status Interrupt Indicator (Read Only).\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No Modem interrupt is generated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Modem interrupt is generated</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>TOUT_INT</name>
<description>Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.\n</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No Tout interrupt is generated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Tout interrupt is generated</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>BUF_ERR_INT</name>
<description>Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No buffer error interrupt is generated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Buffer error interrupt is generated</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>HW_RLS_IF</name>
<description>In DMA Mode, Receive Line Status Flag (Read Only) \nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HW_MODEM_IF</name>
<description>In DMA Mode, MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HW_TOUT_IF</name>
<description>In DMA Mode, Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HW_BUF_ERR_IF</name>
<description>In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HW_RLS_INT</name>
<description>In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN and HW_RLS_IF are both set to 1.\n</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No RLS interrupt is generated in DMA mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RLS interrupt is generated in DMA mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>HW_MODEM_INT</name>
<description>In DMA Mode, MODEM Status Interrupt Indicator (Read Only) \nThis bit is set if MODEM_IEN and HW_MODEM_IF are both set to 1.\n</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No Modem interrupt is generated in DMA mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Modem interrupt is generated in DMA mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>HW_TOUT_INT</name>
<description>In DMA Mode, Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and HW_TOUT_IF are both set to 1.\n</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No Tout interrupt is generated in DMA mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Tout interrupt is generated in DMA mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>HW_BUF_ERR_INT</name>
<description>In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and HW_BUF_ERR_IF are both set to 1.\n</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No buffer error interrupt is generated in DMA mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Buffer error interrupt is generated in DMA mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UA_TOR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_TOR</displayName>
<description>UART Time Out Register</description>
<addressOffset>0x20</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TOIC</name>
<description>Time Out Interrupt Comparator\n</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DLY</name>
<description>TX Delay time value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UA_BAUD</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_BAUD</displayName>
<description>UART Baud Rate Divisor Register</description>
<addressOffset>0x24</addressOffset>
<access>read-write</access>
<resetValue>0x0F000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BRD</name>
<description>Baud Rate Divider\nThe field indicates the baud rate divider.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DIVIDER_X</name>
<description>Divider X\n</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DIV_X_ONE</name>
<description>Divider X Equal to 1\nRefer to the Table 515 below for more information.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 8)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DIV_X_EN</name>
<description>Divider X Enable\nRefer to the table below for more information.\nNote: In IrDA mode, this bit must be disabled.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Divider X Disabled (the equation of M = 16)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UA_IRCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_IRCR</displayName>
<description>UART IrDA Control Register</description>
<addressOffset>0x28</addressOffset>
<access>read-write</access>
<resetValue>0x00000040</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TX_SELECT</name>
<description>TX_SELECT\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Enable IrDA receiver</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable IrDA transmitter</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>INV_TX</name>
<description>INV_TX\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No inversion</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverse TX output signal</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>INV_RX</name>
<description>INV_RX\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No inversion</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverse RX input signal</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UA_ALT_CSR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_ALT_CSR</displayName>
<description>UART Alternate Control/Status Register</description>
<addressOffset>0x2C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RS485_NMM</name>
<description>RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It can't be active with RS-485_AAD operation mode.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RS-485 Normal Multi-drop Operation mode (NMM) Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RS-485 Normal Multi-drop Operation mode (NMM) Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RS485_AAD</name>
<description>RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RS-485 Auto Address Detection Operation mode (AAD) Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RS-485 Auto Address Detection Operation mode (AAD) Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RS485_AUD</name>
<description>RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RS-485 Auto Direction Operation mode (AUD) Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RS-485 Auto Direction Operation mode (AUD) Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RS485_ADD_EN</name>
<description>RS-485 Address Detection Enable \nThis bit is used to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Address detection mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Address detection mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ADDR_MATCH</name>
<description>Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 Auto Address Detection mode.</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UA_FUN_SEL</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_FUN_SEL</displayName>
<description>UART Function Select Register</description>
<addressOffset>0x30</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUN_SEL</name>
<description>Function Selection Enable\n</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART Function</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reserved</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>IrDA Function Enabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>RS-485 Function Enabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UART1</name>
<description>UART Register Map</description>
<groupName>UART</groupName>
<baseAddress>0x40150000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x34</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>UA_RBR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_RBR</displayName>
<description>UART Receive Buffer Register</description>
<addressOffset>0x0</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>RBR</name>
<description>Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UA_THR</name>
<alternateRegister>UA_RBR</alternateRegister>
<!-- the display name is an unrestricted string. -->
<displayName>UA_THR</displayName>
<description>UART Transmit Holding Register</description>
<addressOffset>0x0</addressOffset>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x00000000</resetMask>
<fields>
<field>
<name>THR</name>
<description>Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first).</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>UA_IER</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_IER</displayName>
<description>UART Interrupt Enable Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDA_IEN</name>
<description>Receive Data Available Interrupt Enable.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>INT_RDA Masked off</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>INT_RDA Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>THRE_IEN</name>
<description>Transmit Holding Register Empty Interrupt Enable\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>INT_THRE Masked off</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>INT_THRE Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RLS_IEN</name>
<description>Receive Line Status Interrupt Enable \n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>INT_RLS Masked off</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>INT_RLS Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>MODEM_IEN</name>
<description>Modem Status Interrupt Enable\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>INT_MODEM Masked off</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>INT_MODEM Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RTO_IEN</name>
<description>RX Time Out Interrupt Enable\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>INT_TOUT Masked off</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>INT_TOUT Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BUF_ERR_IEN</name>
<description>Buffer Error Interrupt Enable\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>INT_BUF_ERR Masked off</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>INT_BUF_ERR Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>WAKE_EN</name>
<description>UART Wake-up Function Enable\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART wake-up function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>UART wake-up function Enabled, when chip is in Power-down mode, an external CTS change will wake up chip from Power-down mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TIME_OUT_EN</name>
<description>Time Out Counter Enable\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Time-out counter Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Time-out counter Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>AUTO_RTS_EN</name>
<description>RTS Auto Flow Control Enable\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO is equal to the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTS signal.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RTS auto flow control Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RTS auto flow control Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>AUTO_CTS_EN</name>
<description>CTS Auto Flow Control Enable \nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CTS auto flow control Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CTS auto flow control Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMA_TX_EN</name>
<description>TX DMA Enable\nThis bit can enable or disable TX DMA service.\n</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TX DMA Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TX DMA Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DMA_RX_EN</name>
<description>RX DMA Enable\nThis bit can enable or disable RX DMA service.\n</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RX DMA Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RX DMA Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UA_FCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_FCR</displayName>
<description>UART FIFO Control Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000101</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RFR</name>
<description>RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will be automatically cleared at least 3 UART engine clock cycles.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset the RX internal state machine and pointers</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TFR</name>
<description>TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will be automatically cleared at least 3 UART engine clock cycles.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset the TX internal state machine and pointers</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RFITL</name>
<description>RX FIFO Interrupt (INT_RDA) Trigger Level\n</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RX_DIS</name>
<description>Receiver Disable Register\nThe receiver is enabled or disabled.\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receiver Enabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receiver Disabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RTS_TRI_LEV</name>
<description>RTS Trigger Level for Auto-flow Control Use\n</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UA_LCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_LCR</displayName>
<description>UART Line Control Register</description>
<addressOffset>0xC</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>WLS</name>
<description>Word Length Selection\n</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NSB</name>
<description>Number of "STOP bit"\nTwo "STOP bit" are generated when 6-, 7- and 8-bit word length is selected.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One " STOP bit" is generated in the transmitted data</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>One and a half " STOP bit" is generated in the transmitted data when 5-bit word length is selected;</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PBE</name>
<description>Parity Bit Enable\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No parity bit</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Parity bit is generated on each outgoing character and is checked on each incoming data</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>EPE</name>
<description>Even Parity Enable\nThis bit has effect only when bit 3 (parity bit enable) is set.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Odd number of logic 1's is transmitted and checked in each word</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Even number of logic 1's is transmitted and checked in each word</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SPE</name>
<description>Stick Parity Enable\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Stick parity Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If bit 3 and 4 are logic 1, the parity bit is transmitted and cheched as logic 0. If bit 3 si 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BCB</name>
<description>Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UA_MCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_MCR</displayName>
<description>UART Modem Control Register</description>
<addressOffset>0x10</addressOffset>
<access>read-write</access>
<resetValue>0x00000200</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RTS</name>
<description>RTS (Request-To-Send) Signal\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Drive RTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 0 (If the LEV_RTS set to high level triggered)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Drive RTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive RTS pin to logic 1 (If the LEV_RTS set to high level triggered)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>LEV_RTS</name>
<description>RTS Trigger Level\nThis bit can change the RTS trigger level.\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low level triggered</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High level triggered</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RTS_ST</name>
<description>RTS Pin State (Read Only)\nThis bit is the output pin status of RTS.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UA_MSR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_MSR</displayName>
<description>UART Modem Status Register</description>
<addressOffset>0x14</addressOffset>
<access>read-write</access>
<resetValue>0x00000110</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>DCTSF</name>
<description>Detect CTS State Change Flag (Read Only)\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CTS_ST</name>
<description>CTS Pin Status (Read Only)\nThis bit is the pin status of CTS.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LEV_CTS</name>
<description>CTS Trigger Level\nThis bit can change the CTS trigger level.\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low level triggered</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High level triggered</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UA_FSR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_FSR</displayName>
<description>UART FIFO Status Register</description>
<addressOffset>0x18</addressOffset>
<access>read-write</access>
<resetValue>0x10404000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RX_OVER_IF</name>
<description>RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RS485_ADD_DETF</name>
<description>RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PEF</name>
<description>Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FEF</name>
<description>Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BIF</name>
<description>Break Interrupt Flag (Read Only)\nThis bit is set to a logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RX_POINTER</name>
<description>RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one.</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RX_EMPTY</name>
<description>Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RX_FULL</name>
<description>Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RX_POINTER is equal to 64/16(UART0/UART1); otherwise, it is cleared by hardware.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TX_POINTER</name>
<description>TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one.</description>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TX_EMPTY</name>
<description>Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TX_FULL</name>
<description>Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TX_POINTER is equal to 64/16(UART0/UART1); otherwise, it is cleared by hardware.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TX_OVER_IF</name>
<description>TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. \nNote: This bit is read only, but can be cleared by writing '1' to it.</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TE_FLAG</name>
<description>Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UA_ISR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_ISR</displayName>
<description>UART Interrupt Status Register</description>
<addressOffset>0x1C</addressOffset>
<access>read-write</access>
<resetValue>0x00000002</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RDA_IF</name>
<description>Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX FIFO is equal to the RFITL, the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>THRE_IF</name>
<description>Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RLS_IF</name>
<description>Receive Line Interrupt Flag (Read Only). \nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MODEM_IF</name>
<description>MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TOUT_IF</name>
<description>Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BUF_ERR_IF</name>
<description>Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RDA_INT</name>
<description>Receive Data Available Interrupt Indicator (Read Only).\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No RDA interrupt is generated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RDA interrupt is generated</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>THRE_INT</name>
<description>Transmit Holding Register Empty Interrupt Indicator (Read Only).\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No THRE interrupt is generated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>THRE interrupt is generated</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>RLS_INT</name>
<description>Receive Line Status Interrupt Indicator (Read Only). \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No RLS interrupt is generated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RLS interrupt is generated</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>MODEM_INT</name>
<description>MODEM Status Interrupt Indicator (Read Only).\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No Modem interrupt is generated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Modem interrupt is generated</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>TOUT_INT</name>
<description>Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.\n</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No Tout interrupt is generated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Tout interrupt is generated</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>BUF_ERR_INT</name>
<description>Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No buffer error interrupt is generated</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Buffer error interrupt is generated</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>HW_RLS_IF</name>
<description>In DMA Mode, Receive Line Status Flag (Read Only) \nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HW_MODEM_IF</name>
<description>In DMA Mode, MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HW_TOUT_IF</name>
<description>In DMA Mode, Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HW_BUF_ERR_IF</name>
<description>In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HW_RLS_INT</name>
<description>In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN and HW_RLS_IF are both set to 1.\n</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No RLS interrupt is generated in DMA mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RLS interrupt is generated in DMA mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>HW_MODEM_INT</name>
<description>In DMA Mode, MODEM Status Interrupt Indicator (Read Only) \nThis bit is set if MODEM_IEN and HW_MODEM_IF are both set to 1.\n</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No Modem interrupt is generated in DMA mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Modem interrupt is generated in DMA mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>HW_TOUT_INT</name>
<description>In DMA Mode, Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and HW_TOUT_IF are both set to 1.\n</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No Tout interrupt is generated in DMA mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Tout interrupt is generated in DMA mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>HW_BUF_ERR_INT</name>
<description>In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and HW_BUF_ERR_IF are both set to 1.\n</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No buffer error interrupt is generated in DMA mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Buffer error interrupt is generated in DMA mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>UA_TOR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_TOR</displayName>
<description>UART Time Out Register</description>
<addressOffset>0x20</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TOIC</name>
<description>Time Out Interrupt Comparator\n</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DLY</name>
<description>TX Delay time value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UA_BAUD</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_BAUD</displayName>
<description>UART Baud Rate Divisor Register</description>
<addressOffset>0x24</addressOffset>
<access>read-write</access>
<resetValue>0x0F000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>BRD</name>
<description>Baud Rate Divider\nThe field indicates the baud rate divider.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DIVIDER_X</name>
<description>Divider X\n</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DIV_X_ONE</name>
<description>Divider X Equal to 1\nRefer to the Table 515 below for more information.</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 8)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DIV_X_EN</name>
<description>Divider X Enable\nRefer to the table below for more information.\nNote: In IrDA mode, this bit must be disabled.</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Divider X Disabled (the equation of M = 16)</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UA_IRCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_IRCR</displayName>
<description>UART IrDA Control Register</description>
<addressOffset>0x28</addressOffset>
<access>read-write</access>
<resetValue>0x00000040</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TX_SELECT</name>
<description>TX_SELECT\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Enable IrDA receiver</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enable IrDA transmitter</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>INV_TX</name>
<description>INV_TX\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No inversion</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverse TX output signal</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>INV_RX</name>
<description>INV_RX\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No inversion</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Inverse RX input signal</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UA_ALT_CSR</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_ALT_CSR</displayName>
<description>UART Alternate Control/Status Register</description>
<addressOffset>0x2C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RS485_NMM</name>
<description>RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It can't be active with RS-485_AAD operation mode.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RS-485 Normal Multi-drop Operation mode (NMM) Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RS-485 Normal Multi-drop Operation mode (NMM) Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RS485_AAD</name>
<description>RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RS-485 Auto Address Detection Operation mode (AAD) Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RS-485 Auto Address Detection Operation mode (AAD) Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RS485_AUD</name>
<description>RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RS-485 Auto Direction Operation mode (AUD) Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RS-485 Auto Direction Operation mode (AUD) Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RS485_ADD_EN</name>
<description>RS-485 Address Detection Enable \nThis bit is used to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Address detection mode Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Address detection mode Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ADDR_MATCH</name>
<description>Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 Auto Address Detection mode.</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>UA_FUN_SEL</name>
<!-- the display name is an unrestricted string. -->
<displayName>UA_FUN_SEL</displayName>
<description>UART Function Select Register</description>
<addressOffset>0x30</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUN_SEL</name>
<description>Function Selection Enable\n</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>UART Function</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reserved</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>IrDA Function Enabled</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>RS-485 Function Enabled</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PS2</name>
<description>PS2 Register Map</description>
<groupName>PS2</groupName>
<baseAddress>0x40100000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x20</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PS2CON</name>
<!-- the display name is an unrestricted string. -->
<displayName>PS2CON</displayName>
<description>PS/2 Control Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS2EN</name>
<description>Enable PS/2 Device\nEnable PS/2 device controller.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TXINTEN</name>
<description>Enable Transmit Interrupt\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data transmit complete interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data transmit complete interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RXINTEN</name>
<description>Enable Receive Interrupt\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data receive complete interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data receive complete interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TXFIFODIPTH</name>
<description>Transmit Data FIFO Depth\nThere is 16-byte buffer for data transmit. Software can define the FIFO depth from 1 to 16 bytes depending on the application.\n</description>
<bitOffset>3</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>1 byte</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>2 bytes</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>14</name>
<description>15 bytes</description>
<value>14</value>
</enumeratedValue>
<enumeratedValue>
<name>15</name>
<description>16 bytes</description>
<value>15</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ACK</name>
<description>Acknowledge Enable\n</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Always sends acknowledge to host at 12th clock for host to device communication</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>If parity error or stop bit is not received correctly, acknowledge bit will not be sent to host at 12th clock</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CLRFIFO</name>
<description>Clear TX FIFO\nWrite 1 to this bit to terminate device to host transmission. The TXEMPTY bit in PS2STATUS bit will be set to 1 and pointer BYTEIDEX is reset to 0 regardless there is residue data in buffer or not. The buffer content is not been cleared.\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not active</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Clear FIFO</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>OVERRIDE</name>
<description>Software Override PS/2 CLK/DATA Pin State\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PS2CLK and PS2DATA pins are controlled by internal state machine</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PS2CLK and PS2DATA pins are controlled by software</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>FPS2CLK</name>
<description>Force PS2CLK Line\nIt forces PS2CLK line high or low regardless of the internal state of the device controller if OVERRIDE is set to high.\n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Force PS2CLK line low</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Force PS2CLK line high</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>FPS2DAT</name>
<description>Force PS2DATA Line\nIt forces PS2DATA high or low regardless of the internal state of the device controller if OVERRIDE is set to high.\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Force PS2DATA low</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Force PS2DATA high</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PS2TXDATA0</name>
<!-- the display name is an unrestricted string. -->
<displayName>PS2TXDATA0</displayName>
<description>PS/2 Transmit Data Register 0</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS2TXDATAx</name>
<description>Transmit data\nWrite data to this register starts device to host communication if bus is in IDLE state. Software must enable PS2EN before writing data to TX buffer.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register derivedFrom="PS2TXDATA0">
<name>PS2TXDATA1</name>
<displayName>PS2TXDATA1</displayName>
<description>PS/2 Transmit Data Register 1</description>
<addressOffset>0x8</addressOffset>
</register>
<register derivedFrom="PS2TXDATA0">
<name>PS2TXDATA2</name>
<displayName>PS2TXDATA2</displayName>
<description>PS/2 Transmit Data Register 2</description>
<addressOffset>0xC</addressOffset>
</register>
<register derivedFrom="PS2TXDATA0">
<name>PS2TXDATA3</name>
<displayName>PS2TXDATA3</displayName>
<description>PS/2 Transmit Data Register 3</description>
<addressOffset>0x10</addressOffset>
</register>
<register>
<name>PS2RXDATA</name>
<!-- the display name is an unrestricted string. -->
<displayName>PS2RXDATA</displayName>
<description>PS/2 Receive Data Register</description>
<addressOffset>0x14</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS2RXDATA</name>
<description>Received Data\nFor host to device communication, after acknowledge bit is sent, the received data is copied from receive shift register to PS2RXDATA register. CPU must read this register before next byte reception complete; otherwise, the data will be overwritten and RXOVF bit in PS2STATUS[6] will be set to 1.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PS2STATUS</name>
<!-- the display name is an unrestricted string. -->
<displayName>PS2STATUS</displayName>
<description>PS/2 Status Register</description>
<addressOffset>0x18</addressOffset>
<access>read-write</access>
<resetValue>0x00000083</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PS2CLK</name>
<description>CLK Pin State\nThis bit reflects the status of the PS2CLK line after synchronizing.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PS2DATA</name>
<description>DATA Pin State\nThis bit reflects the status of the PS2DATA line after synchronizing and sampling.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FRAMERR</name>
<description>Frame Error\nFor host to device communication, if STOP bit (logic 1) is not received it is a frame error. If frame error occurs, DATA line may keep at low state after 12th clock. At this moment, software overrides PS2CLK to send clock till PS2DATA release to high state. After that, device sends a "Resend" command to host.\nWrite 1 to clear this bit.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No frame error</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Frame error occurred </description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RXPARITY</name>
<description>Received Parity\nThis bit reflects the parity bit for the last received data byte (odd parity).\nRead only bit.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXBUSY</name>
<description>Receive Busy\nThis bit indicates that the PS/2 device is currently receiving data.\nRead only bit.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Currently receiving data</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TXBUSY</name>
<description>Transmit Busy\nThis bit indicates that the PS/2 device is currently sending data.\nRead only bit.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Idle</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Currently sending data</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RXOVF</name>
<description>RX Buffer Overwrite\nWrite 1 to clear this bit.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No overwrite</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data in PS2RXDATA register is overwritten by new received data</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TXEMPTY</name>
<description>TX FIFO Empty\nWhen software writes any data to PS2TXDATA0-3 the TXEMPTY bit is cleared to 0 immediately if PS2EN is enabled. When transmitted data byte number is equal to FIFODEPTH then TXEMPTY bit is set to 1.\nRead only bit.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>There is data to be transmitted</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>FIFO is empty</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BYTEIDX</name>
<description>Byte Index\n</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PS2INTID</name>
<!-- the display name is an unrestricted string. -->
<displayName>PS2INTID</displayName>
<description>PS/2 Interrupt Identification Register</description>
<addressOffset>0x1C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXINT</name>
<description>Receive Interrupt\nThis bit is set to 1 when acknowledge bit is sent for Host to device communication. Interrupt occurs if RXINTEN bit is set to 1.\nWrite 1 to clear this bit to 0.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive interrupt occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TXINT</name>
<description>Transmit Interrupt\nThis bit is set to 1 after STOP bit is transmitted. Interrupt occurs if TXINTEN bit is set to 1.\nWrite 1 to clear this bit to 0.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit interrupt occurs</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>I2S</name>
<description>I2S Register Map</description>
<groupName>I2S</groupName>
<baseAddress>0x401A0000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x18</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>I2S_CON</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2S_CON</displayName>
<description>I2S Control Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>I2SEN</name>
<description>I2S Controller Enable\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TXEN</name>
<description>Transmit enable\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data transmission Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data transmission Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RXEN</name>
<description>Receive enable\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data receiving Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data receiving Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>MUTE</name>
<description>Transmit Mute Enable\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit data is shifted from buffer</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit channel zero</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>WORDWIDTH</name>
<description>Word Width\n</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data is 8-bit</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data is 16-bit</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Data is 24-bit</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Data is 32-bit</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>MONO</name>
<description>Monaural Data\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data is stereo format</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data is monaural format</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>FORMAT</name>
<description>Data format Selection\n</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>I2S data format\nPCM mode A</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>MSB justified data format\nPCM mode B</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SLAVE</name>
<description>Slave mode\nI2S can be operated as Master or Slave mode. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro( NUC123 series to Audio CODEC chip. In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Master mode</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Slave mode</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TXTH</name>
<description>Transmit FIFO threshold level\nIf remain data word (32 bits) in transmit FIFO is the same or less than threshold level, the TXTHF flag is set.\n</description>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>0 word data in transmit FIFO</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>1 word data in transmit FIFO</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>2 words data in transmit FIFO</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>3 words data in transmit FIFO</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>4</name>
<description>4 words data in transmit FIFO</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>5</name>
<description>5 words data in transmit FIFO</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>6</name>
<description>6 words data in transmit FIFO</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>7 words data in transmit FIFO</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RXTH</name>
<description>Receive FIFO threshold level\nWhen received data word(s) in buffer is equal to or higher than threshold level, the RXTHF flag is set.\n</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>1 word data in receive FIFO</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>2 word data in receive FIFO</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>3 word data in receive FIFO</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>4 word data in receive FIFO</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>4</name>
<description>5 word data in receive FIFO</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>5</name>
<description>6 word data in receive FIFO</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>6</name>
<description>7 word data in receive FIFO</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>8 word data in receive FIFO</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>MCLKEN</name>
<description>Master clock enable\nFor NuMicro( NUC123 series, if the external crystal clock is frequency 2*N*256fs, software can program MCLK_DIV[2:0] in I2S_CLKDIV register to get 256fs clock to audio codec chip.\n</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Master clock Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Master clock Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RCHZCEN</name>
<description>Right Channel Zero-cross Detect Enable\nIf this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCF flag in I2S_STATUS register is set to 1.\n</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Right channel zero-cross detect Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Right channel zero-cross detect Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>LCHZCEN</name>
<description>Left Channel Zero Cross Detect Enable\nIf this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCF flag in I2S_STATUS register is set to 1.\n</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Left channel zero-cross detect Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Left channel zero-cross detect Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CLR_TXFIFO</name>
<description>Clear Transmit FIFO\nWrite 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXFIFO_LEVEL[3:0] returns to zero and transmit FIFO becomes empty but data in transmit FIFO is not changed. \nThis bit is cleared by hardware automatically, reading it returns zero.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLR_RXFIFO</name>
<description>Clear Receive FIFO\nWrite 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXFIFO_LEVEL[3:0] returns to zero and receive FIFO becomes empty.\nThis bit is cleared by hardware automatically, reading it returns zero.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXDMA</name>
<description>Enable Transmit DMA\nWhen TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.\n</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>TX DMA Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>TX DMA Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RXDMA</name>
<description>Enable Receive DMA\nWhen RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.\n</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>RX DMA Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>RX DMA Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RXLCH</name>
<description>Receive Left Channel Enable\n</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Receives right channel data when monaural format is selected</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receives left channel data when monaural format is selected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PCM</name>
<description>PCM Interface Enable\n</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>I2S Interface</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PCM interface</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>I2S_CLKDIV</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2S_CLKDIV</displayName>
<description>I2S Clock Divider Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>MCLK_DIV</name>
<description>Master Clock Divider\nIf chip external crystal frequency is (2xMCLK_DIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. If MCLK_DIV is set to 0, MCLK is the same as external clock input.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BCLK_DIV</name>
<description>Bit Clock Divider\nIf I2S operates in Master mode, bit clock is provided by NuMicro( NUC123 series. Software can program these bits to generate sampling rate clock frequency.\n</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>I2S_IE</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2S_IE</displayName>
<description>I2S Interrupt Enable Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXUDFIE</name>
<description>Receive FIFO Underflow Interrupt Enable\nIf software reads the received FIFO when it is empty, RXUDF flag in I2SSTATUS register is set to 1.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RXOVFIE</name>
<description>Receive FIFO Overflow Interrupt Enable\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RXTHIE</name>
<description>Received FIFO Threshold Level Interrupt Enable\nWhen data word in receive FIFO is equal to or higher then RXTH[2:0] and the RXTHF bit is set to 1. If RXTHIE bit is enabled, interrupt occurs.\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TXUDFIE</name>
<description>Transmitted FIFO Underflow Interrupt Enable\nInterrupt occurs if this bit is set to 1 and transmitted FIFO underflow flag is set to 1.\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TXOVFIE</name>
<description>Transmitted FIFO Overflow Interrupt Enable\nInterrupt occurs if this bit is set to 1 and transmitted FIFO overflow flag is set to 1.\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TXTHIE</name>
<description>Transmitted FIFO Threshold Level Interrupt Enable\nInterrupt occurs if this bit is set to 1 and data words in transmit FIFO are less than TXTH[2:0].\n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RZCIE</name>
<description>Right Channel Zero-cross Interrupt Enable\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>LZCIE</name>
<description>Left Channel Zero-cross Interrupt Enable\nInterrupt occurs if this bit is set to 1 and left channel zero-cross.\n</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>I2S_STATUS</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2S_STATUS</displayName>
<description>I2S Status Register</description>
<addressOffset>0xC</addressOffset>
<access>read-write</access>
<resetValue>0x00141000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>I2SINT</name>
<description>I2S Interrupt Flag\nIt is wire-OR of I2STXINT and I2SRXINT bits.\nThis bit is read only.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No I2S interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>I2S interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>I2SRXINT</name>
<description>I2S Receive Interrupt\nThis bit is read only.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No receive interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Receive interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>I2STXINT</name>
<description>I2S Transmit Interrupt\nThis bit is read only.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No transmit interrupt</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit interrupt</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RIGHT</name>
<description>Right Channel\nThis bit indicates the current transmit data is belong to right channel.\nThis bit is read only.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Left channel</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Right channel</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RXUDF</name>
<description>Receive FIFO Underflow Flag\nRead receive FIFO when it is empty, this bit set to 1 indicate underflow occur.\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No underflow occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Underflow occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RXOVF</name>
<description>Receive FIFO Overflow Flag\nWhen receive FIFO is full and receive hardware attempt write to data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No overflow occurred</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Overflow occurred</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RXTHF</name>
<description>Receive FIFO Threshold Flag\nWhen data word(s) in receive FIFO is equal or higher than threshold value set in RXTH[2:0] the RXTHF bit becomes to 1. It keeps at 1 till RXFIFO_LEVEL[3:0] less than RXTH[1:0] after software read RXFIFO register.\nThis bit is read only.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data word(s) in FIFO is lower than threshold level</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data word(s) in FIFO is equal or higher than threshold level</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RXFULL</name>
<description>Receive FIFO Full\nThis bit reflect data words number in receive FIFO is 8.\nThis bit is read only.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not full</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Full</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RXEMPTY</name>
<description>Receive FIFO Empty\nThis bit reflects data words number in receive FIFO is zero.\nThis bit is read only.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not empty</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Empty</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TXUDF</name>
<description>Transmit FIFO underflow flag\nWhen transmit FIFO is empty and shift logic hardware read data from data FIFO causes this set to 1.\nSoftware can write 1 to clear this bit to zero</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No underflow</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Underflow</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TXOVF</name>
<description>Transmit FIFO Overflow Flag\nWrite data to transmit FIFO when it is full and this bit set to 1.\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No overflow</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Overflow</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TXTHF</name>
<description>Transmit FIFO Threshold Flag\nWhen data word(s) in transmit FIFO is equal to or lower than threshold value set in TXTH[2:0] the TXTHF bit becomes to 1. It keeps at 1 till TXFIFO_LEVEL[3:0] is higher than TXTH[1:0] after software write TXFIFO register.\nThis bit is read only.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data word(s) in FIFO is higher than threshold level</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data word(s) in FIFO is equal or lower than threshold level</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TXFULL</name>
<description>Transmit FIFO Full\nThis bit reflect data word number in transmit FIFO is 8.\nThis bit is read only</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not full</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Full</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TXEMPTY</name>
<description>Transmit FIFO Empty\nThis bit reflect data word number in transmit FIFO is zero.\nThis bit is read only.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not empty</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Empty</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TXBUSY</name>
<description>Transmit Busy\nThis bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out, and set to 1 when the 1st data is load to shift buffer. \nThis bit is read only.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transmit shift buffer is empty</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Transmit shift buffer is busy</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RZCF</name>
<description>Right Channel Zero-cross Flag\nIt indicates right channel next sample data sign bit is changed or all data bits are zero.\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No zero-cross</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Right channel zero-cross is detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>LZCF</name>
<description>Left Channel Zero-cross Flag\nIt indicates left channel next the sample data sign bit is changed or all data bits are zero.\nSoftware can write 1 to clear this bit to zero</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No zero-cross</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Left channel zero-cross is detected</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>RX_LEVEL</name>
<description>Receive FIFO Level\nThese bits indicate word number in receive FIFO.\n</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No data</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>1 word in receive FIFO</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>8</name>
<description>8 words in receive FIFO</description>
<value>#1000</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TX_LEVEL</name>
<description>Transmit FIFO Level\nThese bits indicate word number in transmit FIFO.\n</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No data</description>
<value>#0000</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>1 word in transmit FIFO</description>
<value>#0001</value>
</enumeratedValue>
<enumeratedValue>
<name>8</name>
<description>8 words in transmit FIFO</description>
<value>#1000</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>I2S_TXFIFO</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2S_TXFIFO</displayName>
<description>I2S Transmit FIFO Register</description>
<addressOffset>0x10</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TXFIFO</name>
<description>Transmit FIFO register\nI2S contains 8 words (8x32 bit) data buffer for data transmission. Write data to this register to prepare data for transmit. The remaining word number is indicated by TX_LEVEL[3:0] in I2S_STATUS.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>I2S_RXFIFO</name>
<!-- the display name is an unrestricted string. -->
<displayName>I2S_RXFIFO</displayName>
<description>I2S Receive FIFO Register</description>
<addressOffset>0x14</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RXFIFO</name>
<description>Receive FIFO register\nI2S contains 8 words (8x32 bit) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RX_LEVEL[3:0] in I2S_STATUS register.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ADC</name>
<description>ADC Register Map</description>
<groupName>ADC</groupName>
<baseAddress>0x400E0000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x34</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x40</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>ADDR0</name>
<!-- the display name is an unrestricted string. -->
<displayName>ADDR0</displayName>
<description>A/D Data Register 0</description>
<addressOffset>0x0</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>RSLT</name>
<description>A/D Conversion Result\nThis field contains 10 bits conversion result of ADC.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OVERRUN</name>
<description>Over Run Flag\nIf converted data in RSLT[15:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read.\nThis is a read only bit.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data in RSLT[15:0] is recent conversion result</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data in RSLT[15:0] is overwritten</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
<field>
<name>VALID</name>
<description>Valid Flag\nThis bit is set to 1 when the corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data in RSLT[15:0] bits is not valid</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data in RSLT[15:0] bits is valid</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-only</access>
</field>
</fields>
</register>
<register derivedFrom="ADDR0">
<name>ADDR1</name>
<displayName>ADDR1</displayName>
<description>A/D Data Register 1</description>
<addressOffset>0x4</addressOffset>
</register>
<register derivedFrom="ADDR0">
<name>ADDR2</name>
<displayName>ADDR2</displayName>
<description>A/D Data Register 2</description>
<addressOffset>0x8</addressOffset>
</register>
<register derivedFrom="ADDR0">
<name>ADDR3</name>
<displayName>ADDR3</displayName>
<description>A/D Data Register 3</description>
<addressOffset>0xC</addressOffset>
</register>
<register derivedFrom="ADDR0">
<name>ADDR4</name>
<displayName>ADDR4</displayName>
<description>A/D Data Register 4</description>
<addressOffset>0x10</addressOffset>
</register>
<register derivedFrom="ADDR0">
<name>ADDR5</name>
<displayName>ADDR5</displayName>
<description>A/D Data Register 5</description>
<addressOffset>0x14</addressOffset>
</register>
<register derivedFrom="ADDR0">
<name>ADDR6</name>
<displayName>ADDR6</displayName>
<description>A/D Data Register 6</description>
<addressOffset>0x18</addressOffset>
</register>
<register derivedFrom="ADDR0">
<name>ADDR7</name>
<displayName>ADDR7</displayName>
<description>A/D Data Register 7</description>
<addressOffset>0x1C</addressOffset>
</register>
<register>
<name>ADCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>ADCR</displayName>
<description>A/D Control Register</description>
<addressOffset>0x20</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADEN</name>
<description>A/D Converter Enable\nBefore starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit for saving power consumption.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ADIE</name>
<description>A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A/D interrupt function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A/D interrupt function Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ADMD</name>
<description>A/D Converter Operation Mode\nWhen changing the operation mode, software should disable ADST bit firstly.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Single conversion</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reserved</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Single-cycle scan</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Continuous scan</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TRGS</name>
<description>Hardware Trigger Source\nSoftware should disable TRGEN and ADST before change TRGS.\nIn hardware trigger mode, the ADST bit is set by the external trigger from STADC.</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A/D conversion is started by external STADC pin.\nA/D conversion is started by PWM center-aligned trigger</description>
<value>#00</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TRGCOND</name>
<description>External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.\n</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Low level</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>High level</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Falling edge</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Rising edge</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TRGEN</name>
<description>External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin.\nADC external trigger function is only supported in Single-cycle Scan mode.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PTEN</name>
<description>PDMA Transfer Enable\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>PDMA data transfer Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PDMA data transfer in ADDR 0~7 Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>ADST</name>
<description>A/D Conversion Start\nADST bit can be set to 1 from three sources: software and external pin STADC, and pwm output. ADST will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan mode, A/D conversion is continuously performed until software write 0 to this bit or chip reset.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Conversion stopped and A/D converter entering Idle state</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Conversion started</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADCHER</name>
<!-- the display name is an unrestricted string. -->
<displayName>ADCHER</displayName>
<description>A/D Channel Enable Register</description>
<addressOffset>0x24</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CHEN0</name>
<description>Analog Input Channel 0 Enable\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CHEN1</name>
<description>Analog Input Channel 1 Enable\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CHEN2</name>
<description>Analog Input Channel 2 Enable\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CHEN3</name>
<description>Analog Input Channel 3 Enable\n</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CHEN4</name>
<description>Analog Input Channel 4 Enable\n</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CHEN5</name>
<description>Analog Input Channel 5 Enable\n</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CHEN6</name>
<description>Analog Input Channel 6 Enable\n</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CHEN7</name>
<description>Analog Input Channel 7 Enable\n</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>PRESEL</name>
<description>Analog Input Channel 7 Selection\nNote: When software selects the band-gap voltage as the analog input source of ADC channel 7, ADC clock rate needs to be limited to lower than 300 kHz.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>External analog input</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Internal band-gap voltage</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADCMPR0</name>
<!-- the display name is an unrestricted string. -->
<displayName>ADCMPR0</displayName>
<description>A/D Compare Register 0</description>
<addressOffset>0x28</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CMPEN</name>
<description>Compare Enable\nSet this bit to 1 to enable ADC controller to compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Compare function Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Compare function Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CMPIE</name>
<description>Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Compare function interrupt Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Compare function interrupt Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CMPCOND</name>
<description>Compare Conditions\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CMPCH</name>
<description>Compare Channel Selection\n</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Channel 0 conversion result is selected to be compared</description>
<value>#000</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Channel 1 conversion result is selected to be compared</description>
<value>#001</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Channel 2 conversion result is selected to be compared</description>
<value>#010</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Channel 3 conversion result is selected to be compared</description>
<value>#011</value>
</enumeratedValue>
<enumeratedValue>
<name>4</name>
<description>Channel 4 conversion result is selected to be compared</description>
<value>#100</value>
</enumeratedValue>
<enumeratedValue>
<name>5</name>
<description>Channel 5 conversion result is selected to be compared</description>
<value>#101</value>
</enumeratedValue>
<enumeratedValue>
<name>6</name>
<description>Channel 6 conversion result is selected to be compared</description>
<value>#110</value>
</enumeratedValue>
<enumeratedValue>
<name>7</name>
<description>Channel 7 conversion result is selected to be compared</description>
<value>#111</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CMPMATCNT</name>
<description>Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CMPD</name>
<description>Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nWhen DMOF bit is set to 0, ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned format.\nWhen DMOF bit is set to 1, ADC comparator compares CMPD with conversion result with 2'complement format. CMPD should be filled in 2'complement format.</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register derivedFrom="ADCMPR0">
<name>ADCMPR1</name>
<displayName>ADCMPR1</displayName>
<description>A/D Compare Register 1</description>
<addressOffset>0x2C</addressOffset>
</register>
<register>
<name>ADSR</name>
<!-- the display name is an unrestricted string. -->
<displayName>ADSR</displayName>
<description>A/D Status Register</description>
<addressOffset>0x30</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>ADF</name>
<description>A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these two conditions:\n1. When A/D conversion ends in Single mode.\n2. When A/D conversion ends on all specified channels in Scan mode.\nThis flag can be cleared by writing 1 to itself.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CMPF0</name>
<description>Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to itself.\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Conversion result in ADDR does not meet ADCMPR0 setting</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Conversion result in ADDR meets ADCMPR0 setting</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CMPF1</name>
<description>Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. It is cleared by writing 1 to itself.\n</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Conversion result in ADDR does not meet ADCMPR1 setting</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Conversion result in ADDR meets ADCMPR1 setting</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BUSY</name>
<description>BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR.\nIt is read only.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>A/D converter is in Idle state</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>A/D converter is busy at conversion</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CHANNEL</name>
<description>Current Conversion Channel\nIt is read only.</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VALID</name>
<description>Data Valid flag\nIt is a mirror of VALID bit in ADDRx.\nIt is read only.</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OVERRUN</name>
<description>Over Run Flag\nIt is a mirror to OVERRUN bit in ADDRx.\nIt is read only.</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ADPDMA</name>
<!-- the display name is an unrestricted string. -->
<displayName>ADPDMA</displayName>
<description>ADC PDMA current transfer data</description>
<addressOffset>0x40</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>AD_PDMA</name>
<description>ADC PDMA current transfer data register\nWhen PDMA transferring, read this register can monitor current PDMA transfer data.\nThis is a read only register.</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PDMA_ch0</name>
<description>PDMA Register Map</description>
<groupName>PDMA</groupName>
<baseAddress>0x50008000</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x28</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x80</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PDMA_CSRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CSRx</displayName>
<description>PDMA Control Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMACEN</name>
<description>PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SW_RST</name>
<description>Software Engine Reset\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>MODE_SEL</name>
<description>PDMA Mode Selection\n</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Memory to Memory mode (Memory-to-Memory)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Peripheral to Memory mode (Peripheral-to-Memory)</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Memory to Peripheral mode (Memory-to-Peripheral)</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SAD_SEL</name>
<description>Transfer Source Address Direction Selection\n</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer source address is increasing successively</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reserved</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DAD_SEL</name>
<description>Transfer Destination Address Direction Selection\n</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer destination address is increasing successively</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reserved</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>APB_TWS</name>
<description>Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).</description>
<bitOffset>19</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One word (32-bit) is transferred for every PDMA operation</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>One byte (8-bit) is transferred for every PDMA operation</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>One half-word (16-bit) is transferred for every PDMA operation</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TRIG_EN</name>
<description>TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PDMA data read or write transfer Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_SARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_SARx</displayName>
<description>PDMA Source Address Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_SAR</name>
<description>PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_DARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_DARx</displayName>
<description>PDMA Destination Address Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_DAR</name>
<description>PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_BCRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_BCRx</displayName>
<description>PDMA Transfer Byte Count Register</description>
<addressOffset>0xC</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_BCR</name>
<description>PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_POINTx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_POINTx</displayName>
<description>PDMA Internal buffer pointer</description>
<addressOffset>0x10</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x0000FFFF</resetMask>
<fields>
<field>
<name>PDMA_POINT</name>
<description>PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_CSARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CSARx</displayName>
<description>PDMA Current Source Address Register</description>
<addressOffset>0x14</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_CSAR</name>
<description>PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_CDARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CDARx</displayName>
<description>PDMA Current Destination Address Register</description>
<addressOffset>0x18</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_CDAR</name>
<description>PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_CBCRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CBCRx</displayName>
<description>PDMA Current Transfer Byte Count Register</description>
<addressOffset>0x1C</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_CBCR</name>
<description>PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_IERx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_IERx</displayName>
<description>PDMA Interrupt Enable Register</description>
<addressOffset>0x20</addressOffset>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TABORT_IE</name>
<description>PDMA Read/Write Target Abort Interrupt Enable\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Target abort interrupt generation Disabled during PDMA transfer</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Target abort interrupt generation Enabled during PDMA transfer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BLKD_IE</name>
<description>PDMA Transfer Done Interrupt Enable\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt generator Disabled when PDMA transfer is done</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt generator Enabled when PDMA transfer is done</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_ISRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_ISRx</displayName>
<description>PDMA Interrupt Status Register</description>
<addressOffset>0x24</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TABORT_IF</name>
<description>PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus ERROR response received</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus ERROR response received</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BLKD_IF</name>
<description>Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not finished</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Done</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_SBUF_cx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_SBUF_cx</displayName>
<description>PDMA Shared Buffer FIFO</description>
<addressOffset>0x80</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_SBUF</name>
<description>PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PDMA_ch1</name>
<description>PDMA Register Map</description>
<groupName>PDMA</groupName>
<baseAddress>0x50008100</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x28</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x80</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PDMA_CSRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CSRx</displayName>
<description>PDMA Control Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMACEN</name>
<description>PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SW_RST</name>
<description>Software Engine Reset\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>MODE_SEL</name>
<description>PDMA Mode Selection\n</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Memory to Memory mode (Memory-to-Memory)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Peripheral to Memory mode (Peripheral-to-Memory)</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Memory to Peripheral mode (Memory-to-Peripheral)</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SAD_SEL</name>
<description>Transfer Source Address Direction Selection\n</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer source address is increasing successively</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reserved</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DAD_SEL</name>
<description>Transfer Destination Address Direction Selection\n</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer destination address is increasing successively</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reserved</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>APB_TWS</name>
<description>Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).</description>
<bitOffset>19</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One word (32-bit) is transferred for every PDMA operation</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>One byte (8-bit) is transferred for every PDMA operation</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>One half-word (16-bit) is transferred for every PDMA operation</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TRIG_EN</name>
<description>TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PDMA data read or write transfer Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_SARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_SARx</displayName>
<description>PDMA Source Address Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_SAR</name>
<description>PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_DARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_DARx</displayName>
<description>PDMA Destination Address Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_DAR</name>
<description>PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_BCRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_BCRx</displayName>
<description>PDMA Transfer Byte Count Register</description>
<addressOffset>0xC</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_BCR</name>
<description>PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_POINTx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_POINTx</displayName>
<description>PDMA Internal buffer pointer</description>
<addressOffset>0x10</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x0000FFFF</resetMask>
<fields>
<field>
<name>PDMA_POINT</name>
<description>PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_CSARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CSARx</displayName>
<description>PDMA Current Source Address Register</description>
<addressOffset>0x14</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_CSAR</name>
<description>PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_CDARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CDARx</displayName>
<description>PDMA Current Destination Address Register</description>
<addressOffset>0x18</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_CDAR</name>
<description>PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_CBCRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CBCRx</displayName>
<description>PDMA Current Transfer Byte Count Register</description>
<addressOffset>0x1C</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_CBCR</name>
<description>PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_IERx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_IERx</displayName>
<description>PDMA Interrupt Enable Register</description>
<addressOffset>0x20</addressOffset>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TABORT_IE</name>
<description>PDMA Read/Write Target Abort Interrupt Enable\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Target abort interrupt generation Disabled during PDMA transfer</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Target abort interrupt generation Enabled during PDMA transfer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BLKD_IE</name>
<description>PDMA Transfer Done Interrupt Enable\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt generator Disabled when PDMA transfer is done</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt generator Enabled when PDMA transfer is done</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_ISRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_ISRx</displayName>
<description>PDMA Interrupt Status Register</description>
<addressOffset>0x24</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TABORT_IF</name>
<description>PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus ERROR response received</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus ERROR response received</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BLKD_IF</name>
<description>Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not finished</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Done</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_SBUF_cx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_SBUF_cx</displayName>
<description>PDMA Shared Buffer FIFO</description>
<addressOffset>0x80</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_SBUF</name>
<description>PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PDMA_ch2</name>
<description>PDMA Register Map</description>
<groupName>PDMA</groupName>
<baseAddress>0x50008200</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x28</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x80</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PDMA_CSRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CSRx</displayName>
<description>PDMA Control Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMACEN</name>
<description>PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SW_RST</name>
<description>Software Engine Reset\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>MODE_SEL</name>
<description>PDMA Mode Selection\n</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Memory to Memory mode (Memory-to-Memory)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Peripheral to Memory mode (Peripheral-to-Memory)</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Memory to Peripheral mode (Memory-to-Peripheral)</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SAD_SEL</name>
<description>Transfer Source Address Direction Selection\n</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer source address is increasing successively</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reserved</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DAD_SEL</name>
<description>Transfer Destination Address Direction Selection\n</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer destination address is increasing successively</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reserved</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>APB_TWS</name>
<description>Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).</description>
<bitOffset>19</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One word (32-bit) is transferred for every PDMA operation</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>One byte (8-bit) is transferred for every PDMA operation</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>One half-word (16-bit) is transferred for every PDMA operation</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TRIG_EN</name>
<description>TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PDMA data read or write transfer Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_SARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_SARx</displayName>
<description>PDMA Source Address Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_SAR</name>
<description>PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_DARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_DARx</displayName>
<description>PDMA Destination Address Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_DAR</name>
<description>PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_BCRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_BCRx</displayName>
<description>PDMA Transfer Byte Count Register</description>
<addressOffset>0xC</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_BCR</name>
<description>PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_POINTx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_POINTx</displayName>
<description>PDMA Internal buffer pointer</description>
<addressOffset>0x10</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x0000FFFF</resetMask>
<fields>
<field>
<name>PDMA_POINT</name>
<description>PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_CSARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CSARx</displayName>
<description>PDMA Current Source Address Register</description>
<addressOffset>0x14</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_CSAR</name>
<description>PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_CDARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CDARx</displayName>
<description>PDMA Current Destination Address Register</description>
<addressOffset>0x18</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_CDAR</name>
<description>PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_CBCRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CBCRx</displayName>
<description>PDMA Current Transfer Byte Count Register</description>
<addressOffset>0x1C</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_CBCR</name>
<description>PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_IERx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_IERx</displayName>
<description>PDMA Interrupt Enable Register</description>
<addressOffset>0x20</addressOffset>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TABORT_IE</name>
<description>PDMA Read/Write Target Abort Interrupt Enable\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Target abort interrupt generation Disabled during PDMA transfer</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Target abort interrupt generation Enabled during PDMA transfer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BLKD_IE</name>
<description>PDMA Transfer Done Interrupt Enable\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt generator Disabled when PDMA transfer is done</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt generator Enabled when PDMA transfer is done</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_ISRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_ISRx</displayName>
<description>PDMA Interrupt Status Register</description>
<addressOffset>0x24</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TABORT_IF</name>
<description>PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus ERROR response received</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus ERROR response received</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BLKD_IF</name>
<description>Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not finished</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Done</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_SBUF_cx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_SBUF_cx</displayName>
<description>PDMA Shared Buffer FIFO</description>
<addressOffset>0x80</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_SBUF</name>
<description>PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PDMA_ch3</name>
<description>PDMA Register Map</description>
<groupName>PDMA</groupName>
<baseAddress>0x50008300</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x28</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x80</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PDMA_CSRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CSRx</displayName>
<description>PDMA Control Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMACEN</name>
<description>PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SW_RST</name>
<description>Software Engine Reset\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>MODE_SEL</name>
<description>PDMA Mode Selection\n</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Memory to Memory mode (Memory-to-Memory)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Peripheral to Memory mode (Peripheral-to-Memory)</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Memory to Peripheral mode (Memory-to-Peripheral)</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SAD_SEL</name>
<description>Transfer Source Address Direction Selection\n</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer source address is increasing successively</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reserved</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DAD_SEL</name>
<description>Transfer Destination Address Direction Selection\n</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer destination address is increasing successively</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reserved</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>APB_TWS</name>
<description>Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).</description>
<bitOffset>19</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One word (32-bit) is transferred for every PDMA operation</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>One byte (8-bit) is transferred for every PDMA operation</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>One half-word (16-bit) is transferred for every PDMA operation</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TRIG_EN</name>
<description>TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PDMA data read or write transfer Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_SARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_SARx</displayName>
<description>PDMA Source Address Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_SAR</name>
<description>PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_DARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_DARx</displayName>
<description>PDMA Destination Address Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_DAR</name>
<description>PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_BCRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_BCRx</displayName>
<description>PDMA Transfer Byte Count Register</description>
<addressOffset>0xC</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_BCR</name>
<description>PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_POINTx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_POINTx</displayName>
<description>PDMA Internal buffer pointer</description>
<addressOffset>0x10</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x0000FFFF</resetMask>
<fields>
<field>
<name>PDMA_POINT</name>
<description>PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_CSARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CSARx</displayName>
<description>PDMA Current Source Address Register</description>
<addressOffset>0x14</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_CSAR</name>
<description>PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_CDARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CDARx</displayName>
<description>PDMA Current Destination Address Register</description>
<addressOffset>0x18</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_CDAR</name>
<description>PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_CBCRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CBCRx</displayName>
<description>PDMA Current Transfer Byte Count Register</description>
<addressOffset>0x1C</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_CBCR</name>
<description>PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_IERx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_IERx</displayName>
<description>PDMA Interrupt Enable Register</description>
<addressOffset>0x20</addressOffset>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TABORT_IE</name>
<description>PDMA Read/Write Target Abort Interrupt Enable\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Target abort interrupt generation Disabled during PDMA transfer</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Target abort interrupt generation Enabled during PDMA transfer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BLKD_IE</name>
<description>PDMA Transfer Done Interrupt Enable\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt generator Disabled when PDMA transfer is done</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt generator Enabled when PDMA transfer is done</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_ISRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_ISRx</displayName>
<description>PDMA Interrupt Status Register</description>
<addressOffset>0x24</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TABORT_IF</name>
<description>PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus ERROR response received</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus ERROR response received</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BLKD_IF</name>
<description>Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not finished</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Done</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_SBUF_cx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_SBUF_cx</displayName>
<description>PDMA Shared Buffer FIFO</description>
<addressOffset>0x80</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_SBUF</name>
<description>PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PDMA_ch4</name>
<description>PDMA Register Map</description>
<groupName>PDMA</groupName>
<baseAddress>0x50008400</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x28</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x80</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PDMA_CSRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CSRx</displayName>
<description>PDMA Control Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMACEN</name>
<description>PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SW_RST</name>
<description>Software Engine Reset\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>MODE_SEL</name>
<description>PDMA Mode Selection\n</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Memory to Memory mode (Memory-to-Memory)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Peripheral to Memory mode (Peripheral-to-Memory)</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Memory to Peripheral mode (Memory-to-Peripheral)</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SAD_SEL</name>
<description>Transfer Source Address Direction Selection\n</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer source address is increasing successively</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reserved</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DAD_SEL</name>
<description>Transfer Destination Address Direction Selection\n</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer destination address is increasing successively</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reserved</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>APB_TWS</name>
<description>Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).</description>
<bitOffset>19</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One word (32-bit) is transferred for every PDMA operation</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>One byte (8-bit) is transferred for every PDMA operation</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>One half-word (16-bit) is transferred for every PDMA operation</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TRIG_EN</name>
<description>TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PDMA data read or write transfer Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_SARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_SARx</displayName>
<description>PDMA Source Address Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_SAR</name>
<description>PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_DARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_DARx</displayName>
<description>PDMA Destination Address Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_DAR</name>
<description>PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_BCRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_BCRx</displayName>
<description>PDMA Transfer Byte Count Register</description>
<addressOffset>0xC</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_BCR</name>
<description>PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_POINTx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_POINTx</displayName>
<description>PDMA Internal buffer pointer</description>
<addressOffset>0x10</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x0000FFFF</resetMask>
<fields>
<field>
<name>PDMA_POINT</name>
<description>PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_CSARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CSARx</displayName>
<description>PDMA Current Source Address Register</description>
<addressOffset>0x14</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_CSAR</name>
<description>PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_CDARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CDARx</displayName>
<description>PDMA Current Destination Address Register</description>
<addressOffset>0x18</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_CDAR</name>
<description>PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_CBCRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CBCRx</displayName>
<description>PDMA Current Transfer Byte Count Register</description>
<addressOffset>0x1C</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_CBCR</name>
<description>PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_IERx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_IERx</displayName>
<description>PDMA Interrupt Enable Register</description>
<addressOffset>0x20</addressOffset>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TABORT_IE</name>
<description>PDMA Read/Write Target Abort Interrupt Enable\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Target abort interrupt generation Disabled during PDMA transfer</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Target abort interrupt generation Enabled during PDMA transfer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BLKD_IE</name>
<description>PDMA Transfer Done Interrupt Enable\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt generator Disabled when PDMA transfer is done</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt generator Enabled when PDMA transfer is done</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_ISRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_ISRx</displayName>
<description>PDMA Interrupt Status Register</description>
<addressOffset>0x24</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TABORT_IF</name>
<description>PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus ERROR response received</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus ERROR response received</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BLKD_IF</name>
<description>Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not finished</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Done</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_SBUF_cx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_SBUF_cx</displayName>
<description>PDMA Shared Buffer FIFO</description>
<addressOffset>0x80</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_SBUF</name>
<description>PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PDMA_ch5</name>
<description>PDMA Register Map</description>
<groupName>PDMA</groupName>
<baseAddress>0x50008500</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x28</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x80</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PDMA_CSRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CSRx</displayName>
<description>PDMA Control Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMACEN</name>
<description>PDMA Channel Enable\nSetting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SW_RST</name>
<description>Software Engine Reset\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>MODE_SEL</name>
<description>PDMA Mode Selection\n</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Memory to Memory mode (Memory-to-Memory)</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Peripheral to Memory mode (Peripheral-to-Memory)</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Memory to Peripheral mode (Memory-to-Peripheral)</description>
<value>#10</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>SAD_SEL</name>
<description>Transfer Source Address Direction Selection\n</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer source address is increasing successively</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reserved</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>DAD_SEL</name>
<description>Transfer Destination Address Direction Selection\n</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Transfer destination address is increasing successively</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reserved</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>Transfer destination address is fixed (This feature can be used when data transferred from multiple sources to a single destination)</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>APB_TWS</name>
<description>Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).</description>
<bitOffset>19</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>One word (32-bit) is transferred for every PDMA operation</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>One byte (8-bit) is transferred for every PDMA operation</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>One half-word (16-bit) is transferred for every PDMA operation</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>Reserved</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TRIG_EN</name>
<description>TRIG_EN\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>PDMA data read or write transfer Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_SARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_SARx</displayName>
<description>PDMA Source Address Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_SAR</name>
<description>PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_DARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_DARx</displayName>
<description>PDMA Destination Address Register</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_DAR</name>
<description>PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_BCRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_BCRx</displayName>
<description>PDMA Transfer Byte Count Register</description>
<addressOffset>0xC</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_BCR</name>
<description>PDMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_POINTx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_POINTx</displayName>
<description>PDMA Internal buffer pointer</description>
<addressOffset>0x10</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0x0000FFFF</resetMask>
<fields>
<field>
<name>PDMA_POINT</name>
<description>PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_CSARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CSARx</displayName>
<description>PDMA Current Source Address Register</description>
<addressOffset>0x14</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_CSAR</name>
<description>PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurs.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_CDARx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CDARx</displayName>
<description>PDMA Current Destination Address Register</description>
<addressOffset>0x18</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_CDAR</name>
<description>PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurs.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_CBCRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_CBCRx</displayName>
<description>PDMA Current Transfer Byte Count Register</description>
<addressOffset>0x1C</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_CBCR</name>
<description>PDMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: SW_RST will clear this register value.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PDMA_IERx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_IERx</displayName>
<description>PDMA Interrupt Enable Register</description>
<addressOffset>0x20</addressOffset>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TABORT_IE</name>
<description>PDMA Read/Write Target Abort Interrupt Enable\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Target abort interrupt generation Disabled during PDMA transfer</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Target abort interrupt generation Enabled during PDMA transfer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BLKD_IE</name>
<description>PDMA Transfer Done Interrupt Enable\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt generator Disabled when PDMA transfer is done</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt generator Enabled when PDMA transfer is done</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_ISRx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_ISRx</displayName>
<description>PDMA Interrupt Status Register</description>
<addressOffset>0x24</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TABORT_IF</name>
<description>PDMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus ERROR response received</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus ERROR response received</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BLKD_IF</name>
<description>Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not finished</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Done</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PDMA_SBUF_cx</name>
<!-- the display name is an unrestricted string. -->
<displayName>PDMA_SBUF_cx</displayName>
<description>PDMA Shared Buffer FIFO</description>
<addressOffset>0x80</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>PDMA_SBUF</name>
<description>PDMA Shared Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CRC</name>
<description>PDMA Register Map</description>
<groupName>PDMA</groupName>
<baseAddress>0x50008E00</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0xC</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x14</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x1C</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x80</offset>
<size>0xC</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CRC_CTL</name>
<!-- the display name is an unrestricted string. -->
<displayName>CRC_CTL</displayName>
<description>CRC Control Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x20000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRCCEN</name>
<description>CRC Channel Enable\nSetting this bit to 1 enables CRC's operation.\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CRC_RST</name>
<description>CRC Engine Reset\nNote: When operated in CPU PIO mode, setting this bit will reload the initial seed value.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Reset the internal CRC state machine and internal buffer. The contents of control register will not be cleared. This bit will automatically be cleared after few clock cycles</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>TRIG_EN</name>
<description>TRIG_EN\nNote1: If this bit assert indicates the CRC engine operation in CRC DMA mode, do not fill in any data in CRC_WDATA register.\nNote2: When CRC DMA transfer is completed, this bit will be cleared automatically.\nNote3: If the bus error occurs, all CRC DMA transfer will be stopped. Software must reset all DMA channel, and then trigger again.</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No effect</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CRC DMA data read or write transfer Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>WDATA_RVS</name>
<description>Write Data Order Reverse\nNote: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bit order reversed for CRC write data in</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bit order reversed for CRC write data in (per byte)</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CHECKSUM_RVS</name>
<description>Checksum Reverse\nNote: If the checksum data is 0XDD7B0F2E, the bit order reversed for CRC checksum is 0x74F0DEBB.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bit order reverse for CRC checksum</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bit order reverse for CRC checksum</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>WDATA_COM</name>
<description>Write Data Complement\n</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No 1's complement for CRC write data in</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>1's complement for CRC write data in</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CHECKSUM_COM</name>
<description>Checksum Complement\n</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No 1's complement for CRC checksum</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>1's complement for CRC checksum</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CPU_WDLEN</name>
<description>CPU Write Data Length\nNote1: This field is used for CPU PIO mode.\nNote2: When the data length is 8-bit mode, the valid data is CRC_WDATA [7:0]; if the data length is 16-bit mode, the valid data is CRC_WDATA [15:0].</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Data length is 8-bit mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Data length is 16-bit mode\nData length is 32-bit mode</description>
<value>#01</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CRC_MODE</name>
<description>CRC Polynomial Mode\n</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>CRC-CCITT Polynomial mode</description>
<value>#00</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>CRC-8 Polynomial mode</description>
<value>#01</value>
</enumeratedValue>
<enumeratedValue>
<name>2</name>
<description>CRC-16 Polynomial mode</description>
<value>#10</value>
</enumeratedValue>
<enumeratedValue>
<name>3</name>
<description>CRC-32 Polynomial mode</description>
<value>#11</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CRC_DMASAR</name>
<!-- the display name is an unrestricted string. -->
<displayName>CRC_DMASAR</displayName>
<description>CRC DMA Source Address Register</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRC_DMASAR</name>
<description>CRC DMA Transfer Source Address Register\nThis field indicates a 32-bit source address of CRC DMA.\nNote: The source address must be word alignment.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CRC_DMABCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>CRC_DMABCR</displayName>
<description>CRC DMA Transfer Byte Count Register</description>
<addressOffset>0xC</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRC_DMABCR</name>
<description>CRC DMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of CRC DMA.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CRC_DMACSAR</name>
<!-- the display name is an unrestricted string. -->
<displayName>CRC_DMACSAR</displayName>
<description>CRC DMA Current Source Address Register</description>
<addressOffset>0x14</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRC_DMACSAR</name>
<description>CRC DMA Current Source Address Register (Read Only)\nThis field indicates the source address where the CRC DMA transfer just occurs.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CRC_DMACBCR</name>
<!-- the display name is an unrestricted string. -->
<displayName>CRC_DMACBCR</displayName>
<description>CRC DMA Current Transfer Byte Count Register</description>
<addressOffset>0x1C</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRC_DMACBCR</name>
<description>CRC DMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of CRC_DMA.\nNote: CRC_RST will clear this register value.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CRC_DMAIER</name>
<!-- the display name is an unrestricted string. -->
<displayName>CRC_DMAIER</displayName>
<description>CRC DMA Interrupt Enable Register</description>
<addressOffset>0x20</addressOffset>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TABORT_IE</name>
<description>CRC DMA Read/Write Target Abort Interrupt Enable\n</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Target abort interrupt generation Disabled during CRC DMA transfer</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Target abort interrupt generation Enabled during CRC DMA transfer</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BLKD_IE</name>
<description>CRC DMA Transfer Done Interrupt Enable\n</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Interrupt generator Disabled when CRC DMA transfer is done</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Interrupt generator Enabled when CRC DMA transfer is done</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CRC_DMAISR</name>
<!-- the display name is an unrestricted string. -->
<displayName>CRC_DMAISR</displayName>
<description>CRC DMA Interrupt Status Register</description>
<addressOffset>0x24</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>TABORT_IF</name>
<description>CRC DMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>No bus ERROR response received</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Bus ERROR response received</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>BLKD_IF</name>
<description>Block Transfer Done Interrupt Flag\nThis bit indicates that CRC DMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Not finished</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Done</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CRC_WDATA</name>
<!-- the display name is an unrestricted string. -->
<displayName>CRC_WDATA</displayName>
<description>CRC Write Data Register</description>
<addressOffset>0x80</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRC_WDATA</name>
<description>CRC Write Data Register\n</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CRC_SEED</name>
<!-- the display name is an unrestricted string. -->
<displayName>CRC_SEED</displayName>
<description>CRC Seed Register</description>
<addressOffset>0x84</addressOffset>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRC_SEED</name>
<description>CRC Seed Register\nThis field indicates the CRC seed value.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CRC_CHECKSUM</name>
<!-- the display name is an unrestricted string. -->
<displayName>CRC_CHECKSUM</displayName>
<description>CRC Checksum Register</description>
<addressOffset>0x88</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CRC_CHECKSUM</name>
<description>CRC Checksum Register\nThis field indicates the CRC checksum.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMA_GCR</name>
<description>PDMA Register Map</description>
<groupName>PDMA</groupName>
<baseAddress>0x50008F00</baseAddress>
<!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
<addressBlock>
<offset>0x0</offset>
<size>0x14</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DMA_GCRCSR</name>
<!-- the display name is an unrestricted string. -->
<displayName>DMA_GCRCSR</displayName>
<description>DMA Global Control Register</description>
<addressOffset>0x0</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>CLK0_EN</name>
<description>PDMA Controller Channel 0 Clock Enable Control\n</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CLK1_EN</name>
<description>PDMA Controller Channel 1 Clock Enable Control\n</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CLK2_EN</name>
<description>PDMA Controller Channel 2 Clock Enable Control \n</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CLK3_EN</name>
<description>PDMA Controller Channel 3 Clock Enable Control\n</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CLK4_EN</name>
<description>PDMA Controller Channel 4 Clock Enable Control\n</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CLK5_EN</name>
<description>PDMA Controller Channel 5 Clock Enable Control\n</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
<field>
<name>CRC_CLK_EN</name>
<description>CRC Controller Clock Enable Control\n</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>0</name>
<description>Disabled</description>
<value>#0</value>
</enumeratedValue>
<enumeratedValue>
<name>1</name>
<description>Enabled</description>
<value>#1</value>
</enumeratedValue>
</enumeratedValues>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DMA_PDSSR0</name>
<!-- the display name is an unrestricted string. -->
<displayName>DMA_PDSSR0</displayName>
<description>DMA Service Selection Control Register 0</description>
<addressOffset>0x4</addressOffset>
<access>read-write</access>
<resetValue>0x00FFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>SPI0_RXSEL</name>
<description>PDMA SPI0 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI0 RX. Software can change the channel RX setting by SPI0_RXSEL.\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3 \n4'b0100: CH4 \n4'b0101: CH5\nOthers: Reserved\n</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI0_TXSEL</name>
<description>PDMA SPI0 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI0 TX. Software can configure the TX channel setting by SPI0_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI1_RXSEL</name>
<description>PDMA SPI1 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI1 RX. Software can configure the RX channel setting by SPI1_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI1_TXSEL</name>
<description>PDMA SPI1 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI1 TX. Software can configure the TX channel setting by SPI1_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI2_RXSEL</name>
<description>PDMA SPI2 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI2 RX. Software can configure the RX channel setting by SPI2_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI2_TXSEL</name>
<description>PDMA SPI2 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI2 TX. Software can configure the TX channel setting by SPI2_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DMA_PDSSR1</name>
<!-- the display name is an unrestricted string. -->
<displayName>DMA_PDSSR1</displayName>
<description>DMA Service Selection Control Register 1</description>
<addressOffset>0x8</addressOffset>
<access>read-write</access>
<resetValue>0x0FFFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>UART0_RXSEL</name>
<description>This filed defines which PDMA channel is connected to the on-chip peripheral UART0 RX. Software can change the channel RX setting by UART0_RXSEL.\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3 \n4'b0100: CH4 \n4'b0101: CH5\nOthers : Reserved\n</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UART0_TXSEL</name>
<description>PDMA UART0 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral UART0 TX. Software can configure the TX channel setting by UART0_TXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UART1_RXSEL</name>
<description>PDMA UART1 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral UART1 RX. Software can configure the RX channel setting by UART1_RXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL.</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UART1_TXSEL</name>
<description>PDMA UART1 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral UART1 TX. Software can configure the TX channel setting by UART1_TXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL.</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ADC_RXSEL</name>
<description>PDMA ADC RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral ADC RX. Software can configure the RX channel setting by ADC_RXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL.</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DMA_GCRISR</name>
<!-- the display name is an unrestricted string. -->
<displayName>DMA_GCRISR</displayName>
<description>DMA Global Interrupt Status Register</description>
<addressOffset>0xC</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>INTR0</name>
<description>Interrupt Pin Status of Channel 0\nThis bit is the Interrupt status of PDMA channel 0.\nNote: This bit is read only.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>INTR1</name>
<description>Interrupt Pin Status of Channel 1\nThis bit is the Interrupt status of PDMA channel 1.\nNote: This bit is read only.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>INTR2</name>
<description>Interrupt Pin Status of Channel 2\nThis bit is the Interrupt status of PDMA channel 2.\nNote: This bit is read only.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>INTR3</name>
<description>Interrupt Pin Status of Channel 3\nThis bit is the Interrupt status of PDMA channel 3.\nNote: This bit is read only.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>INTR4</name>
<description>Interrupt Pin Status of Channel 4\nThis bit is the Interrupt status of PDMA channel 4.\nNote: This bit is read only.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>INTR5</name>
<description>Interrupt Pin Status of Channel 5 \nThis bit is the Interrupt status of PDMA channel 5.\nNote: This bit is read only.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CRC_INTR</name>
<description>Interrupt Pin Status of CRC Controller\nThis bit is the Interrupt status of CRC controller.\nNote: This bit is read only.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>INTR</name>
<description>Interrupt Pin Status\nThis bit is the Interrupt status of PDMA controller.\nNote: This bit is read only</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DMA_PDSSR2</name>
<!-- the display name is an unrestricted string. -->
<displayName>DMA_PDSSR2</displayName>
<description>DMA Service Selection Control Register 2</description>
<addressOffset>0x10</addressOffset>
<access>read-write</access>
<resetValue>0x00FFFFFF</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>I2S_RXSEL</name>
<description>PDMA I2S RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral I2S RX. Software can change the channel RX setting by I2S_RXSEL\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3\n4'b0100: CH4\n4'b0101: CH5\nOthers : Reserved\n</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>I2S_TXSEL</name>
<description>PDMA I2S TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral I2S TX. Software can configure the TX channel setting by I2S_TXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL.</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWM0_RXSEL</name>
<description>PDMA PWM0 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM0 RX. Software can configure the RX channel setting by PWM0_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL.</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWM1_RXSEL</name>
<description>PDMA PWM1 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM1 RX. Software can configure the RX channel setting by PWM1_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL.</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWM2_RXSEL</name>
<description>PDMA PWM2 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM2 RX. Software can configure the RX channel setting by PWM2_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL.</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWM3_RXSEL</name>
<description>PDMA PWM3 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM3 RX. Software can configure the RX channel setting by PWM3_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL.</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>
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