158 lines
5.6 KiB
C
158 lines
5.6 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* FSMC driver system settings.
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*/
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#define STM32_FSMC_USE_FSMC1 FALSE
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#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10
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/*
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* FSMC NAND driver system settings.
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*/
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#define STM32_NAND_USE_NAND1 FALSE
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#define STM32_NAND_USE_NAND2 FALSE
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#define STM32_NAND_USE_EXT_INT FALSE
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#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_NAND_DMA_PRIORITY 0
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#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")
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/*
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* FSMC SRAM driver system settings.
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*/
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#define STM32_USE_FSMC_SRAM FALSE
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#define STM32_SRAM_USE_FSMC_SRAM1 FALSE
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#define STM32_SRAM_USE_FSMC_SRAM2 FALSE
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#define STM32_SRAM_USE_FSMC_SRAM3 FALSE
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#define STM32_SRAM_USE_FSMC_SRAM4 FALSE
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/*
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* FSMC SDRAM driver system settings.
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*/
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#define STM32_USE_FSMC_SDRAM FALSE
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#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE
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#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE
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/*
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* TIMCAP driver system settings.
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*/
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#define STM32_TIMCAP_USE_TIM1 TRUE
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#define STM32_TIMCAP_USE_TIM2 FALSE
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#define STM32_TIMCAP_USE_TIM3 TRUE
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#define STM32_TIMCAP_USE_TIM4 TRUE
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#define STM32_TIMCAP_USE_TIM5 TRUE
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#define STM32_TIMCAP_USE_TIM8 TRUE
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#define STM32_TIMCAP_USE_TIM9 TRUE
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#define STM32_TIMCAP_TIM1_IRQ_PRIORITY 3
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#define STM32_TIMCAP_TIM2_IRQ_PRIORITY 3
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#define STM32_TIMCAP_TIM3_IRQ_PRIORITY 3
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#define STM32_TIMCAP_TIM4_IRQ_PRIORITY 3
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#define STM32_TIMCAP_TIM5_IRQ_PRIORITY 3
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#define STM32_TIMCAP_TIM8_IRQ_PRIORITY 3
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#define STM32_TIMCAP_TIM9_IRQ_PRIORITY 3
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/*
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* COMP driver system settings.
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*/
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#define STM32_COMP_USE_COMP1 TRUE
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#define STM32_COMP_USE_COMP2 TRUE
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#define STM32_COMP_USE_COMP3 TRUE
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#define STM32_COMP_USE_COMP4 TRUE
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#define STM32_COMP_USE_COMP5 TRUE
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#define STM32_COMP_USE_COMP6 TRUE
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#define STM32_COMP_USE_COMP7 TRUE
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#define STM32_COMP_USE_INTERRUPTS TRUE
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#define STM32_COMP_1_2_3_IRQ_PRIORITY 5
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#define STM32_COMP_4_5_6_IRQ_PRIORITY 5
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#define STM32_COMP_7_IRQ_PRIORITY 5
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#if STM32_COMP_USE_INTERRUPTS
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#define STM32_DISABLE_EXTI21_22_29_HANDLER
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#define STM32_DISABLE_EXTI30_32_HANDLER
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#define STM32_DISABLE_EXTI33_HANDLER
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#endif
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/*
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* USBH driver system settings.
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*/
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#define STM32_OTG_FS_CHANNELS_NUMBER 8
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#define STM32_OTG_HS_CHANNELS_NUMBER 12
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#define STM32_USBH_USE_OTG1 1
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#define STM32_OTG_FS_RXFIFO_SIZE 1024
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#define STM32_OTG_FS_PTXFIFO_SIZE 128
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#define STM32_OTG_FS_NPTXFIFO_SIZE 128
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#define STM32_USBH_USE_OTG2 0
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#define STM32_OTG_HS_RXFIFO_SIZE 2048
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#define STM32_OTG_HS_PTXFIFO_SIZE 1024
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#define STM32_OTG_HS_NPTXFIFO_SIZE 1024
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#define STM32_USBH_MIN_QSPACE 4
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#define STM32_USBH_CHANNELS_NP 4
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/*
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* CRC driver system settings.
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*/
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#define STM32_CRC_USE_CRC1 TRUE
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#define STM32_CRC_CRC1_DMA_IRQ_PRIORITY 1
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#define STM32_CRC_CRC1_DMA_PRIORITY 2
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#define STM32_CRC_CRC1_DMA_STREAM STM32_DMA1_STREAM2
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#define CRCSW_USE_CRC1 FALSE
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#define CRCSW_CRC32_TABLE TRUE
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#define CRCSW_CRC16_TABLE TRUE
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#define CRCSW_PROGRAMMABLE TRUE
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/*
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* EICU driver system settings.
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*/
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#define STM32_EICU_USE_TIM1 TRUE
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#define STM32_EICU_USE_TIM2 FALSE
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#define STM32_EICU_USE_TIM3 TRUE
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#define STM32_EICU_USE_TIM4 TRUE
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#define STM32_EICU_USE_TIM5 TRUE
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#define STM32_EICU_USE_TIM8 TRUE
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#define STM32_EICU_USE_TIM9 TRUE
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#define STM32_EICU_USE_TIM10 TRUE
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#define STM32_EICU_USE_TIM11 TRUE
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#define STM32_EICU_USE_TIM12 TRUE
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#define STM32_EICU_USE_TIM13 TRUE
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#define STM32_EICU_USE_TIM14 TRUE
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#define STM32_EICU_TIM1_IRQ_PRIORITY 7
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#define STM32_EICU_TIM2_IRQ_PRIORITY 7
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#define STM32_EICU_TIM3_IRQ_PRIORITY 7
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#define STM32_EICU_TIM4_IRQ_PRIORITY 7
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#define STM32_EICU_TIM5_IRQ_PRIORITY 7
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#define STM32_EICU_TIM8_IRQ_PRIORITY 7
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#define STM32_EICU_TIM9_IRQ_PRIORITY 7
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#define STM32_EICU_TIM10_IRQ_PRIORITY 7
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#define STM32_EICU_TIM11_IRQ_PRIORITY 7
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#define STM32_EICU_TIM12_IRQ_PRIORITY 7
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#define STM32_EICU_TIM13_IRQ_PRIORITY 7
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#define STM32_EICU_TIM14_IRQ_PRIORITY 7
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/*
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* QEI driver system settings.
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*/
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#define STM32_QEI_USE_TIM1 TRUE
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#define STM32_QEI_USE_TIM2 FALSE
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#define STM32_QEI_USE_TIM3 TRUE
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#define STM32_QEI_TIM1_IRQ_PRIORITY 3
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#define STM32_QEI_TIM2_IRQ_PRIORITY 3
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#define STM32_QEI_TIM3_IRQ_PRIORITY 3
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