826 lines
21 KiB
C
826 lines
21 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2021 Stefan Kerkmann
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file CAN/hal_can_lld.c
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* @brief GD32 CAN subsystem low level driver source.
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*
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* @addtogroup CAN
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_CAN || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*
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* Addressing differences in the headers, they seem unable to agree on names.
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*/
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#if GD32_CAN_USE_CAN0
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#if !defined(CAN0)
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#define CAN0 CAN
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#endif
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#endif
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief CAN0 driver identifier.*/
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#if GD32_CAN_USE_CAN0 || defined(__DOXYGEN__)
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CANDriver CAND1;
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#endif
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/** @brief CAN1 driver identifier.*/
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#if GD32_CAN_USE_CAN1 || defined(__DOXYGEN__)
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CANDriver CAND2;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Programs the filters of CAN 1 and CAN 2.
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*
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* @param[in] canp pointer to the @p CANDriver object
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* @param[in] can2sb number of the first filter assigned to CAN1
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* @param[in] num number of entries in the filters array, if zero then
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* a default filter is programmed
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* @param[in] cfp pointer to the filters array, can be @p NULL if
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* (num == 0)
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*
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* @notapi
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*/
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static void can_lld_set_filters(CANDriver* canp,
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uint32_t can2sb,
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uint32_t num,
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const CANFilter *cfp) {
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#if GD32_CAN_USE_CAN1
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if (canp == &CAND2) {
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/* Set handle to CAN0, because CAN0 manages the filters of CAN1.*/
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canp = &CAND1;
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}
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#endif
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/* Temporarily enabling CAN clock.*/
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#if GD32_CAN_USE_CAN0
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if (canp == &CAND1) {
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rcuEnableCAN0(true);
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/* Filters initialization.*/
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canp->can->FCTL = (canp->can->FCTL & 0xFFFF0000) | CAN_FCTL_FLD;
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canp->can->FCTL = (canp->can->FCTL & 0xFFFF0000) | (can2sb << 8) | CAN_FCTL_FLD;
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}
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#endif
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if (num > 0) {
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uint32_t i, fmask;
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/* All filters cleared.*/
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canp->can->FW = 0;
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canp->can->FMCFG = 0;
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canp->can->FSCFG = 0;
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canp->can->FAFIFO = 0;
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#if GD32_CAN_USE_CAN0
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if (canp == &CAND1) {
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for (i = 0; i < GD32_CAN_MAX_FILTERS; i++) {
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canp->can->sFilterRegister[i].FR1 = 0;
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canp->can->sFilterRegister[i].FR2 = 0;
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}
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}
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#endif
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/* Scanning the filters array.*/
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for (i = 0; i < num; i++) {
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fmask = 1 << cfp->filter;
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if (cfp->mode)
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canp->can->FMCFG |= fmask;
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if (cfp->scale)
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canp->can->FSCFG |= fmask;
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if (cfp->assignment)
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canp->can->FAFIFO |= fmask;
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canp->can->sFilterRegister[cfp->filter].FR1 = cfp->register1;
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canp->can->sFilterRegister[cfp->filter].FR2 = cfp->register2;
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canp->can->FW |= fmask;
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cfp++;
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}
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}
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else {
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/* Setting up a single default filter that enables everything for both
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CANs.*/
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canp->can->sFilterRegister[0].FR1 = 0;
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canp->can->sFilterRegister[0].FR2 = 0;
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#if GD32_CAN_USE_CAN1
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if (canp == &CAND1) {
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canp->can->sFilterRegister[can2sb].FR1 = 0;
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canp->can->sFilterRegister[can2sb].FR2 = 0;
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}
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#endif
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canp->can->FMCFG = 0;
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canp->can->FAFIFO = 0;
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canp->can->FSCFG = 1;
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canp->can->FW = 1;
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#if GD32_CAN_USE_CAN1
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if (canp == &CAND1) {
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canp->can->FSCFG |= 1 << can2sb;
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canp->can->FW |= 1 << can2sb;
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}
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#endif
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}
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canp->can->FCTL &= ~CAN_FCTL_FLD;
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/* Clock disabled, it will be enabled again in can_lld_start().*/
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/* Temporarily enabling CAN clock.*/
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#if GD32_CAN_USE_CAN0
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if (canp == &CAND1) {
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rcuDisableCAN0();
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}
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#endif
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}
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/**
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* @brief Common TX ISR handler.
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*
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* @param[in] canp pointer to the @p CANDriver object
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*
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* @notapi
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*/
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static void can_lld_tx_handler(CANDriver *canp) {
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uint32_t tstat;
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eventflags_t flags;
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/* Clearing IRQ sources.*/
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tstat = canp->can->TSTAT;
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canp->can->TSTAT = tstat;
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/* Flags to be signaled through the TX event source.*/
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flags = 0U;
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/* Checking mailbox 0.*/
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if ((tstat & CAN_TSTAT_MTF0) != 0U) {
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if ((tstat & (CAN_TSTAT_MAL0 | CAN_TSTAT_MTE0)) != 0U) {
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flags |= CAN_MAILBOX_TO_MASK(1U) << 16U;
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}
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else {
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flags |= CAN_MAILBOX_TO_MASK(1U);
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}
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}
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/* Checking mailbox 1.*/
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if ((tstat & CAN_TSTAT_MTF1) != 0U) {
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if ((tstat & (CAN_TSTAT_MAL1 | CAN_TSTAT_MTE1)) != 0U) {
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flags |= CAN_MAILBOX_TO_MASK(2U) << 16U;
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}
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else {
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flags |= CAN_MAILBOX_TO_MASK(2U);
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}
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}
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/* Checking mailbox 2.*/
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if ((tstat & CAN_TSTAT_MTF2) != 0U) {
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if ((tstat & (CAN_TSTAT_MAL2 | CAN_TSTAT_MTE2)) != 0U) {
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flags |= CAN_MAILBOX_TO_MASK(3U) << 16U;
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}
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else {
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flags |= CAN_MAILBOX_TO_MASK(3U);
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}
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}
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/* Signaling flags and waking up threads waiting for a transmission slot.*/
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_can_tx_empty_isr(canp, flags);
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}
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/**
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* @brief Common RX0 ISR handler.
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*
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* @param[in] canp pointer to the @p CANDriver object
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*
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* @notapi
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*/
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static void can_lld_rx0_handler(CANDriver *canp) {
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uint32_t rfifo0;
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rfifo0 = canp->can->RFIFO0;
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if ((rfifo0 & CAN_RFIFO0_RFL0) > 0) {
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/* No more receive events until the queue 0 has been emptied.*/
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canp->can->INTEN &= ~CAN_INTEN_RFNEIE0;
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_can_rx_full_isr(canp, CAN_MAILBOX_TO_MASK(1U));
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}
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if ((rfifo0 & CAN_RFIFO0_RFO0) > 0) {
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/* Overflow events handling.*/
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canp->can->RFIFO0 = CAN_RFIFO0_RFO0;
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_can_error_isr(canp, CAN_OVERFLOW_ERROR);
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}
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}
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/**
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* @brief Common RX1 ISR handler.
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*
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* @param[in] canp pointer to the @p CANDriver object
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*
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* @notapi
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*/
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static void can_lld_rx1_handler(CANDriver *canp) {
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uint32_t rfifo1;
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rfifo1 = canp->can->RFIFO1;
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if ((rfifo1 & CAN_RFIFO1_RFL1) > 0) {
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/* No more receive events until the queue 0 has been emptied.*/
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canp->can->INTEN &= ~CAN_INTEN_RFNEIE1;
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_can_rx_full_isr(canp, CAN_MAILBOX_TO_MASK(2U));
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}
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if ((rfifo1 & CAN_RFIFO1_RFO1) > 0) {
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/* Overflow events handling.*/
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canp->can->RFIFO1 = CAN_RFIFO1_RFO1;
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_can_error_isr(canp, CAN_OVERFLOW_ERROR);
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}
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}
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/**
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* @brief Common SCE ISR handler.
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*
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* @param[in] canp pointer to the @p CANDriver object
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*
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* @notapi
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*/
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static void can_lld_sce_handler(CANDriver *canp) {
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uint32_t stat;
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/* Clearing IRQ sources.*/
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stat = canp->can->STAT;
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canp->can->STAT = stat;
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/* Wakeup event.*/
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#if CAN_USE_SLEEP_MODE
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if (stat & CAN_STAT_WUIF) {
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canp->state = CAN_READY;
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canp->can->CTL &= ~CAN_CTL_SLPWMOD;
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_can_wakeup_isr(canp);
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}
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#endif /* CAN_USE_SLEEP_MODE */
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/* Error event.*/
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if (stat & CAN_STAT_ERRIF) {
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eventflags_t flags;
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uint32_t err = canp->can->ERR;
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#if GD32_CAN_REPORT_ALL_ERRORS
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flags = (eventflags_t)(err & 7);
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if ((err & CAN_ERR_ERRN) > 0)
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flags |= CAN_FRAMING_ERROR;
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#else
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flags = 0;
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#endif
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/* The content of the ESR register is copied unchanged in the upper
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half word of the listener flags mask.*/
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_can_error_isr(canp, flags | (eventflags_t)(err << 16U));
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}
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if GD32_CAN_USE_CAN0 || defined(__DOXYGEN__)
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#if !defined(GD32_CAN0_TX_HANDLER)
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#error "GD32_CAN0_TX_HANDLER not defined"
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#endif
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#if !defined(GD32_CAN0_RX0_HANDLER)
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#error "GD32_CAN0_RX0_HANDLER not defined"
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#endif
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#if !defined(GD32_CAN0_RX1_HANDLER)
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#error "GD32_CAN0_RX1_HANDLER not defined"
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#endif
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#if !defined(GD32_CAN0_EWMC_HANDLER)
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#error "GD32_CAN0_EWMC_HANDLER not defined"
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#endif
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/**
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* @brief CAN0 TX interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_CAN0_TX_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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can_lld_tx_handler(&CAND1);
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief CAN0 RX0 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_CAN0_RX0_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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can_lld_rx0_handler(&CAND1);
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief CAN0 RX1 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_CAN0_RX1_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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can_lld_rx1_handler(&CAND1);
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief CAN0 SCE interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_CAN0_EWMC_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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can_lld_sce_handler(&CAND1);
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* GD32_CAN_USE_CAN0 */
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#if GD32_CAN_USE_CAN1 || defined(__DOXYGEN__)
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#if !defined(GD32_CAN0_TX_HANDLER)
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#error "GD32_CAN0_TX_HANDLER not defined"
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#endif
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#if !defined(GD32_CAN0_RX0_HANDLER)
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#error "GD32_CAN0_RX0_HANDLER not defined"
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#endif
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#if !defined(GD32_CAN0_RX1_HANDLER)
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#error "GD32_CAN0_RX1_HANDLER not defined"
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#endif
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#if !defined(GD32_CAN0_EWMC_HANDLER)
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#error "GD32_CAN0_EWMC_HANDLER not defined"
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#endif
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/**
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* @brief CAN1 TX interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_CAN0_TX_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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can_lld_tx_handler(&CAND2);
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief CAN1 RX0 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_CAN0_RX0_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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can_lld_rx0_handler(&CAND2);
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief CAN1 RX1 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_CAN0_RX1_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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can_lld_rx1_handler(&CAND2);
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief CAN1 SCE interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_CAN0_EWMC_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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can_lld_sce_handler(&CAND2);
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* GD32_CAN_USE_CAN1 */
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level CAN driver initialization.
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*
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* @notapi
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*/
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void can_lld_init(void) {
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#if GD32_CAN_USE_CAN0
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/* Driver initialization.*/
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canObjectInit(&CAND1);
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CAND1.can = CAN0;
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eclicEnableVector(GD32_CAN0_TX_NUMBER, GD32_CAN_CAN0_IRQ_PRIORITY, GD32_CAN_CAN0_IRQ_TRIGGER);
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eclicEnableVector(GD32_CAN0_RX0_NUMBER, GD32_CAN_CAN0_IRQ_PRIORITY, GD32_CAN_CAN0_IRQ_TRIGGER);
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eclicEnableVector(GD32_CAN0_RX1_NUMBER, GD32_CAN_CAN0_IRQ_PRIORITY, GD32_CAN_CAN0_IRQ_TRIGGER);
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eclicEnableVector(GD32_CAN0_EWMC_NUMBER, GD32_CAN_CAN0_IRQ_PRIORITY, GD32_CAN_CAN0_IRQ_TRIGGER);
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#endif
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#if GD32_CAN_USE_CAN1
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/* Driver initialization.*/
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canObjectInit(&CAND2);
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CAND2.can = CAN1;
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eclicEnableVector(GD32_CAN0_TX_NUMBER, GD32_CAN_CAN1_IRQ_PRIORITY, GD32_CAN_CAN1_IRQ_TRIGGER);
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eclicEnableVector(GD32_CAN0_RX0_NUMBER, GD32_CAN_CAN1_IRQ_PRIORITY, GD32_CAN_CAN1_IRQ_TRIGGER);
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eclicEnableVector(GD32_CAN0_RX1_NUMBER, GD32_CAN_CAN1_IRQ_PRIORITY, GD32_CAN_CAN1_IRQ_TRIGGER);
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eclicEnableVector(GD32_CAN0_EWMC_NUMBER, GD32_CAN_CAN1_IRQ_PRIORITY, GD32_CAN_CAN1_IRQ_TRIGGER);
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#endif
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/* Filters initialization.*/
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#if GD32_CAN_USE_CAN0
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#if GD32_HAS_CAN1
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can_lld_set_filters(&CAND1, GD32_CAN_MAX_FILTERS / 2, 0, NULL);
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#else
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can_lld_set_filters(&CAND1, GD32_CAN_MAX_FILTERS, 0, NULL);
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#endif
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#endif
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}
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/**
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* @brief Configures and activates the CAN peripheral.
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*
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* @param[in] canp pointer to the @p CANDriver object
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*
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* @notapi
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*/
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void can_lld_start(CANDriver *canp) {
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/* Clock activation.*/
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#if GD32_CAN_USE_CAN0
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if (&CAND1 == canp) {
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rcuEnableCAN0(true);
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}
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#endif
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#if GD32_CAN_USE_CAN1
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if (&CAND2 == canp) {
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rcuEnableCAN0(true); /* CAN 2 requires CAN0, so enabling it first.*/
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rcuEnableCAN1(true);
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}
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#endif
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/* Configuring CAN. */
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canp->can->CTL = CAN_CTL_IWMOD;
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while ((canp->can->STAT & CAN_STAT_IWS) == 0)
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osalThreadSleepS(1);
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canp->can->BT = canp->config->bt;
|
|
canp->can->CTL = canp->config->ctl;
|
|
|
|
/* Interrupt sources initialization.*/
|
|
#if GD32_CAN_REPORT_ALL_ERRORS
|
|
canp->can->INTEN = CAN_INTEN_TMEIE | CAN_INTEN_RFNEIE0 | CAN_INTEN_RFNEIE1 |
|
|
CAN_INTEN_WIE | CAN_INTEN_ERRIE | CAN_INTEN_ERRNIE |
|
|
CAN_INTEN_BOIE | CAN_INTEN_PERRIE | CAN_INTEN_WERRIE |
|
|
CAN_INTEN_RFOIE0 | CAN_INTEN_RFOIE1;
|
|
#else
|
|
canp->can->INTEN = CAN_INTEN_TMEIE | CAN_INTEN_RFNEIE0 | CAN_INTEN_RFNEIE1 |
|
|
CAN_INTEN_WIE | CAN_INTEN_ERRIE |
|
|
CAN_INTEN_BOIE | CAN_INTEN_PERRIE | CAN_INTEN_WERRIE |
|
|
CAN_INTEN_RFOIE0 | CAN_INTEN_RFOIE1;
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
* @brief Deactivates the CAN peripheral.
|
|
*
|
|
* @param[in] canp pointer to the @p CANDriver object
|
|
*
|
|
* @notapi
|
|
*/
|
|
void can_lld_stop(CANDriver *canp) {
|
|
|
|
/* If in ready state then disables the CAN peripheral.*/
|
|
if (canp->state == CAN_READY) {
|
|
#if GD32_CAN_USE_CAN0
|
|
if (&CAND1 == canp) {
|
|
CAN0->CTL = 0x00010002; /* Register reset value. */
|
|
CAN0->INTEN = 0x00000000; /* All sources disabled. */
|
|
#if GD32_CAN_USE_CAN1
|
|
/* If CAND2 is stopped then CAN0 clock is stopped here.*/
|
|
if (CAND2.state == CAN_STOP)
|
|
#endif
|
|
{
|
|
rcuDisableCAN0();
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#if GD32_CAN_USE_CAN1
|
|
if (&CAND2 == canp) {
|
|
CAN1->CTL = 0x00010002; /* Register reset value. */
|
|
CAN1->INTEN = 0x00000000; /* All sources disabled. */
|
|
#if GD32_CAN_USE_CAN0
|
|
/* If CAND1 is stopped then CAN0 clock is stopped here.*/
|
|
if (CAND1.state == CAN_STOP)
|
|
#endif
|
|
{
|
|
rcuDisableCAN0();
|
|
}
|
|
rcuDisableCAN1();
|
|
}
|
|
#endif
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Determines whether a frame can be transmitted.
|
|
*
|
|
* @param[in] canp pointer to the @p CANDriver object
|
|
* @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
|
|
*
|
|
* @return The queue space availability.
|
|
* @retval false no space in the transmit queue.
|
|
* @retval true transmit slot available.
|
|
*
|
|
* @notapi
|
|
*/
|
|
bool can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) {
|
|
|
|
switch (mailbox) {
|
|
case CAN_ANY_MAILBOX:
|
|
return (canp->can->TSTAT & CAN_TSTAT_TME) != 0;
|
|
case 1:
|
|
return (canp->can->TSTAT & CAN_TSTAT_TME0) != 0;
|
|
case 2:
|
|
return (canp->can->TSTAT & CAN_TSTAT_TME1) != 0;
|
|
case 3:
|
|
return (canp->can->TSTAT & CAN_TSTAT_TME2) != 0;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Inserts a frame into the transmit queue.
|
|
*
|
|
* @param[in] canp pointer to the @p CANDriver object
|
|
* @param[in] ctfp pointer to the CAN frame to be transmitted
|
|
* @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
|
|
*
|
|
* @notapi
|
|
*/
|
|
void can_lld_transmit(CANDriver *canp,
|
|
canmbx_t mailbox,
|
|
const CANTxFrame *ctfp) {
|
|
uint32_t tmi;
|
|
CAN_TxMailBox_TypeDef *tmbp;
|
|
|
|
/* Pointer to a free transmission mailbox.*/
|
|
switch (mailbox) {
|
|
case CAN_ANY_MAILBOX:
|
|
tmbp = &canp->can->sTxMailBox[(canp->can->TSTAT & CAN_TSTAT_NUM) >> 24];
|
|
break;
|
|
case 1:
|
|
tmbp = &canp->can->sTxMailBox[0];
|
|
break;
|
|
case 2:
|
|
tmbp = &canp->can->sTxMailBox[1];
|
|
break;
|
|
case 3:
|
|
tmbp = &canp->can->sTxMailBox[2];
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
|
|
/* Preparing the message.*/
|
|
if (ctfp->IDE)
|
|
tmi = ((uint32_t)ctfp->EID << 3) | ((uint32_t)ctfp->RTR << 1) |
|
|
CAN_TMI0_FF;
|
|
else
|
|
tmi = ((uint32_t)ctfp->SID << 21) | ((uint32_t)ctfp->RTR << 1);
|
|
tmbp->TMP = ctfp->DLC;
|
|
tmbp->TMDATA0 = ctfp->data32[0];
|
|
tmbp->TMDATA1 = ctfp->data32[1];
|
|
tmbp->TMI = tmi | CAN_TMI0_TEN;
|
|
}
|
|
|
|
/**
|
|
* @brief Determines whether a frame has been received.
|
|
*
|
|
* @param[in] canp pointer to the @p CANDriver object
|
|
* @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
|
|
*
|
|
* @return The queue space availability.
|
|
* @retval false no space in the transmit queue.
|
|
* @retval true transmit slot available.
|
|
*
|
|
* @notapi
|
|
*/
|
|
bool can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) {
|
|
|
|
switch (mailbox) {
|
|
case CAN_ANY_MAILBOX:
|
|
return ((canp->can->RFIFO0 & CAN_RFIFO0_RFL0) != 0 ||
|
|
(canp->can->RFIFO1 & CAN_RFIFO1_RFL1) != 0);
|
|
case 1:
|
|
return (canp->can->RFIFO0 & CAN_RFIFO0_RFL0) != 0;
|
|
case 2:
|
|
return (canp->can->RFIFO1 & CAN_RFIFO1_RFL1) != 0;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Receives a frame from the input queue.
|
|
*
|
|
* @param[in] canp pointer to the @p CANDriver object
|
|
* @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
|
|
* @param[out] crfp pointer to the buffer where the CAN frame is copied
|
|
*
|
|
* @notapi
|
|
*/
|
|
void can_lld_receive(CANDriver *canp,
|
|
canmbx_t mailbox,
|
|
CANRxFrame *crfp) {
|
|
uint32_t rfifomi, rfifomp;
|
|
|
|
if (mailbox == CAN_ANY_MAILBOX) {
|
|
if ((canp->can->RFIFO0 & CAN_RFIFO0_RFL0) != 0)
|
|
mailbox = 1;
|
|
else if ((canp->can->RFIFO1 & CAN_RFIFO1_RFL1) != 0)
|
|
mailbox = 2;
|
|
else {
|
|
/* Should not happen, do nothing.*/
|
|
return;
|
|
}
|
|
}
|
|
switch (mailbox) {
|
|
case 1:
|
|
/* Fetches the message.*/
|
|
rfifomi = canp->can->sFIFOMailBox[0].RFIFOMI;
|
|
rfifomp = canp->can->sFIFOMailBox[0].RFIFOMP;
|
|
crfp->data32[0] = canp->can->sFIFOMailBox[0].RFIFOMDATA0;
|
|
crfp->data32[1] = canp->can->sFIFOMailBox[0].RFIFOMDATA1;
|
|
|
|
/* Releases the mailbox.*/
|
|
canp->can->RFIFO0 = CAN_RFIFO0_RFD0;
|
|
|
|
/* If the queue is empty re-enables the interrupt in order to generate
|
|
events again.*/
|
|
if ((canp->can->RFIFO0 & CAN_RFIFO0_RFL0) == 0)
|
|
canp->can->INTEN |= CAN_INTEN_RFNEIE0;
|
|
break;
|
|
case 2:
|
|
/* Fetches the message.*/
|
|
rfifomi = canp->can->sFIFOMailBox[1].RFIFOMI;
|
|
rfifomp = canp->can->sFIFOMailBox[1].RFIFOMP;
|
|
crfp->data32[0] = canp->can->sFIFOMailBox[1].RFIFOMDATA0;
|
|
crfp->data32[1] = canp->can->sFIFOMailBox[1].RFIFOMDATA1;
|
|
|
|
/* Releases the mailbox.*/
|
|
canp->can->RFIFO1 = CAN_RFIFO1_RFD1;
|
|
|
|
/* If the queue is empty re-enables the interrupt in order to generate
|
|
events again.*/
|
|
if ((canp->can->RFIFO1 & CAN_RFIFO1_RFL1) == 0)
|
|
canp->can->INTEN |= CAN_INTEN_RFNEIE1;
|
|
break;
|
|
default:
|
|
/* Should not happen, do nothing.*/
|
|
return;
|
|
}
|
|
|
|
/* Decodes the various fields in the RX frame.*/
|
|
crfp->RTR = (rfifomi & CAN_RFIFOMI0_FT) >> 1;
|
|
crfp->IDE = (rfifomi & CAN_RFIFOMI0_FF) >> 2;
|
|
if (crfp->IDE)
|
|
crfp->EID = rfifomi >> 3;
|
|
else
|
|
crfp->SID = rfifomi >> 21;
|
|
crfp->DLC = rfifomp & CAN_RFIFOMP0_DLENC;
|
|
crfp->FMI = (uint8_t)(rfifomp >> 8);
|
|
crfp->TIME = (uint16_t)(rfifomp >> 16);
|
|
}
|
|
|
|
/**
|
|
* @brief Tries to abort an ongoing transmission.
|
|
*
|
|
* @param[in] canp pointer to the @p CANDriver object
|
|
* @param[in] mailbox mailbox number
|
|
*
|
|
* @notapi
|
|
*/
|
|
void can_lld_abort(CANDriver *canp,
|
|
canmbx_t mailbox) {
|
|
|
|
canp->can->TSTAT = 128U << ((mailbox - 1U) * 8U);
|
|
}
|
|
|
|
#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__)
|
|
/**
|
|
* @brief Enters the sleep mode.
|
|
*
|
|
* @param[in] canp pointer to the @p CANDriver object
|
|
*
|
|
* @notapi
|
|
*/
|
|
void can_lld_sleep(CANDriver *canp) {
|
|
|
|
canp->can->CTL |= CAN_CTL_SLPWMOD;
|
|
}
|
|
|
|
/**
|
|
* @brief Enforces leaving the sleep mode.
|
|
*
|
|
* @param[in] canp pointer to the @p CANDriver object
|
|
*
|
|
* @notapi
|
|
*/
|
|
void can_lld_wakeup(CANDriver *canp) {
|
|
|
|
canp->can->CTL &= ~CAN_CTL_SLPWMOD;
|
|
}
|
|
#endif /* CAN_USE_SLEEP_MODE */
|
|
|
|
/**
|
|
* @brief Programs the filters.
|
|
* @note This is an GD32-specific API.
|
|
*
|
|
* @param[in] canp pointer to the @p CANDriver object
|
|
* @param[in] can2sb number of the first filter assigned to CAN1
|
|
* @param[in] num number of entries in the filters array, if zero then
|
|
* a default filter is programmed
|
|
* @param[in] cfp pointer to the filters array, can be @p NULL if
|
|
* (num == 0)
|
|
*
|
|
* @api
|
|
*/
|
|
void canGD32SetFilters(CANDriver *canp, uint32_t can2sb,
|
|
uint32_t num, const CANFilter *cfp) {
|
|
|
|
#if GD32_CAN_USE_CAN1
|
|
osalDbgCheck((can2sb <= GD32_CAN_MAX_FILTERS) &&
|
|
(num <= GD32_CAN_MAX_FILTERS));
|
|
#endif
|
|
|
|
#if GD32_CAN_USE_CAN0
|
|
osalDbgAssert(CAND1.state == CAN_STOP, "invalid state");
|
|
#endif
|
|
#if GD32_CAN_USE_CAN1
|
|
osalDbgAssert(CAND2.state == CAN_STOP, "invalid state");
|
|
#endif
|
|
|
|
#if GD32_CAN_USE_CAN0
|
|
if (canp == &CAND1) {
|
|
can_lld_set_filters(canp, can2sb, num, cfp);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
#endif /* HAL_USE_CAN */
|
|
|
|
/** @} */
|