463 lines
14 KiB
C
463 lines
14 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2021 Stefan Kerkmann
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file DAC/hal_dac_lld.c
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* @brief GD32 DAC subsystem low level driver source.
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*
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* @addtogroup DAC
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_DAC || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#define DAC_CH1_DMA_CHANNEL \
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GD32_DMA_GETCHANNEL(GD32_DAC_CH1_DMA_STREAM, \
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GD32_DAC_CH1_DMA_CHN)
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#define DAC_CH2_DMA_CHANNEL \
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GD32_DMA_GETCHANNEL(GD32_DAC_CH2_DMA_STREAM, \
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GD32_DAC_CH2_DMA_CHN)
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#define CHANNEL_DATA_OFFSET 3U
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief DAC CH1 driver identifier.*/
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#if GD32_DAC_USE_DAC_CH1 || defined(__DOXYGEN__)
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DACDriver DACD1;
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#endif
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/** @brief DAC CH2 driver identifier.*/
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#if (GD32_DAC_USE_DAC_CH2 && !GD32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
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DACDriver DACD2;
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#endif
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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#if GD32_DAC_USE_DAC_CH1 == TRUE
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static const dacparams_t dac1_ch1_params = {
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.dac = DAC,
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.dataoffset = 0U,
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.regshift = 0U,
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.regmask = 0xFFFF0000U,
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.dmastream = GD32_DAC_CH1_DMA_STREAM,
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.dmamode = GD32_DMA_CTL_CHSEL(DAC_CH1_DMA_CHANNEL) |
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GD32_DMA_CTL_PRIO(GD32_DAC_CH1_DMA_PRIORITY) |
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GD32_DMA_CTL_MNAGA | GD32_DMA_CTL_CMEN | GD32_DMA_CTL_DIR_M2P |
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GD32_DMA_CTL_ERRIE | GD32_DMA_CTL_HTFIE |
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GD32_DMA_CTL_FTFIE,
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.dmairqprio = GD32_DAC_CH1_IRQ_PRIORITY
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};
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#endif
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#if GD32_DAC_USE_DAC_CH2 == TRUE
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static const dacparams_t dac1_ch2_params = {
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.dac = DAC,
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.dataoffset = CHANNEL_DATA_OFFSET,
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.regshift = 16U,
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.regmask = 0x0000FFFFU,
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.dmastream = GD32_DAC_CH2_DMA_STREAM,
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.dmamode = GD32_DMA_CTL_CHSEL(DAC_CH2_DMA_CHANNEL) |
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GD32_DMA_CTL_PRIO(GD32_DAC_CH2_DMA_PRIORITY) |
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GD32_DMA_CTL_MNAGA | GD32_DMA_CTL_CMEN | GD32_DMA_CTL_DIR_M2P |
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GD32_DMA_CTL_ERRIE | GD32_DMA_CTL_HTFIE |
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GD32_DMA_CTL_FTFIE,
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.dmairqprio = GD32_DAC_CH2_IRQ_PRIORITY
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};
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#endif
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Shared end/half-of-tx service routine.
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*
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* @param[in] dacp pointer to the @p DACDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void dac_lld_serve_tx_interrupt(DACDriver *dacp, uint32_t flags) {
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if ((flags & (GD32_DMA_INTF_ERRIF)) != 0) {
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/* DMA errors handling.*/
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dac_lld_stop_conversion(dacp);
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_dac_isr_error_code(dacp, DAC_ERR_DMAFAILURE);
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}
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else {
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if ((flags & GD32_DMA_INTF_HTFIF) != 0) {
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/* Half transfer processing.*/
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_dac_isr_half_code(dacp);
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}
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if ((flags & GD32_DMA_INTF_FTFIF) != 0) {
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/* Transfer complete processing.*/
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_dac_isr_full_code(dacp);
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}
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}
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level DAC driver initialization.
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*
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* @notapi
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*/
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void dac_lld_init(void) {
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#if GD32_DAC_USE_DAC_CH1
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dacObjectInit(&DACD1);
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DACD1.params = &dac1_ch1_params;
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DACD1.dma = NULL;
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#endif
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#if GD32_DAC_USE_DAC_CH2
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dacObjectInit(&DACD2);
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DACD2.params = &dac1_ch2_params;
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DACD2.dma = NULL;
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#endif
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}
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/**
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* @brief Configures and activates the DAC peripheral.
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*
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* @param[in] dacp pointer to the @p DACDriver object
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*
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* @notapi
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*/
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void dac_lld_start(DACDriver *dacp) {
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/* If the driver is in DAC_STOP state then a full initialization is
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required.*/
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if (dacp->state == DAC_STOP) {
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dacchannel_t channel = 0;
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/* Enabling the clock source.*/
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#if GD32_DAC_USE_DAC_CH1
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if (&DACD1 == dacp) {
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rcuEnableDAC(true);
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}
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#endif
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#if GD32_DAC_USE_DAC_CH2
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if (&DACD2 == dacp) {
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rcuEnableDAC(true);
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channel = 1;
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}
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#endif
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/* Enabling DAC in SW triggering mode initially, initializing data to
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zero.*/
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#if GD32_DAC_DUAL_MODE == FALSE
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{
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uint32_t ctl;
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ctl = dacp->params->dac->CTL;
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ctl &= dacp->params->regmask;
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ctl |= (DAC_CTL_DEN0 | dacp->config->ctl) << dacp->params->regshift;
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dacp->params->dac->CTL = ctl;
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dac_lld_put_channel(dacp, channel, dacp->config->init);
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}
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#else
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if ((dacp->config->datamode == DAC_DHRM_12BIT_RIGHT_DUAL) ||
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(dacp->config->datamode == DAC_DHRM_12BIT_LEFT_DUAL) ||
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(dacp->config->datamode == DAC_DHRM_8BIT_RIGHT_DUAL)) {
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dacp->params->dac->CTL = DAC_CTL_DEN1 | (dacp->config->ctl << 16) | DAC_CTL_DEN0 | dacp->config->ctl;
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dac_lld_put_channel(dacp, 1U, dacp->config->init);
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}
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else {
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dacp->params->dac->CTL = DAC_CTL_DEN0 | dacp->config->ctl;
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}
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dac_lld_put_channel(dacp, channel, dacp->config->init);
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#endif
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}
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}
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/**
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* @brief Deactivates the DAC peripheral.
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*
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* @param[in] dacp pointer to the @p DACDriver object
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*
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* @notapi
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*/
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void dac_lld_stop(DACDriver *dacp) {
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/* If in ready state then disables the DAC clock.*/
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if (dacp->state == DAC_READY) {
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/* Disabling DAC.*/
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dacp->params->dac->CTL &= dacp->params->regmask;
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#if GD32_DAC_USE_DAC_CH1
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if (&DACD1 == dacp) {
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if ((dacp->params->dac->CTL & DAC_CTL_DEN1) == 0U) {
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rcuDisableDAC();
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}
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}
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#endif
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#if GD32_DAC_USE_DAC_CH2
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if (&DACD2 == dacp) {
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if ((dacp->params->dac->CTL & DAC_CTL_DEN0) == 0U) {
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rcuDisableDAC();
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}
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}
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#endif
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}
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}
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/**
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* @brief Outputs a value directly on a DAC channel.
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*
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* @param[in] dacp pointer to the @p DACDriver object
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* @param[in] channel DAC channel number
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* @param[in] sample value to be output
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*
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* @api
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*/
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void dac_lld_put_channel(DACDriver *dacp,
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dacchannel_t channel,
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dacsample_t sample) {
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switch (dacp->config->datamode) {
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case DAC_DHRM_12BIT_RIGHT:
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#if GD32_DAC_DUAL_MODE
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case DAC_DHRM_12BIT_RIGHT_DUAL:
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#endif
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if (channel == 0U) {
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#if GD32_DAC_DUAL_MODE
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dacp->params->dac->R12DH0 = (uint32_t)sample;
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#else
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*(&dacp->params->dac->R12DH0 + dacp->params->dataoffset) = (uint32_t)sample;
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#endif
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}
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#if (GD32_HAS_DAC_CH2)
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else {
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dacp->params->dac->R12DH1 = (uint32_t)sample;
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}
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#endif
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break;
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case DAC_DHRM_12BIT_LEFT:
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#if GD32_DAC_DUAL_MODE
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case DAC_DHRM_12BIT_LEFT_DUAL:
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#endif
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if (channel == 0U) {
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#if GD32_DAC_DUAL_MODE
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dacp->params->dac->L12DH0 = (uint32_t)sample;
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#else
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*(&dacp->params->dac->L12DH0 + dacp->params->dataoffset) = (uint32_t)sample;
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#endif
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}
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#if (GD32_HAS_DAC_CH2)
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else {
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dacp->params->dac->L12DH1 = (uint32_t)sample;
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}
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#endif
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break;
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case DAC_DHRM_8BIT_RIGHT:
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#if GD32_DAC_DUAL_MODE
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case DAC_DHRM_8BIT_RIGHT_DUAL:
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#endif
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if (channel == 0U) {
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#if GD32_DAC_DUAL_MODE
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dacp->params->dac->R8DH0 = (uint32_t)sample;
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#else
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*(&dacp->params->dac->R8DH0 + dacp->params->dataoffset) = (uint32_t)sample;
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#endif
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}
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#if (GD32_HAS_DAC_CH2)
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else {
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dacp->params->dac->R8DH1 = (uint32_t)sample;
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}
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#endif
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break;
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default:
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osalDbgAssert(false, "unexpected DAC mode");
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break;
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}
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}
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/**
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* @brief Starts a DAC conversion.
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* @details Starts an asynchronous conversion operation.
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* @note In @p DAC_DHRM_8BIT_RIGHT mode the parameters passed to the
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* callback are wrong because two samples are packed in a single
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* dacsample_t element. This will not be corrected, do not rely
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* on those parameters.
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* @note In @p DAC_DHRM_8BIT_RIGHT_DUAL mode two samples are treated
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* as a single 16 bits sample and packed into a single dacsample_t
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* element. The num_channels must be set to one in the group
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* conversion configuration structure.
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*
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* @param[in] dacp pointer to the @p DACDriver object
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*
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* @notapi
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*/
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void dac_lld_start_conversion(DACDriver *dacp) {
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uint32_t n, ctl, dmamode;
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/* Number of DMA operations per buffer.*/
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n = dacp->depth * dacp->grpp->num_channels;
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/* Allocating the DMA channel.*/
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dacp->dma = dmaStreamAllocI(dacp->params->dmastream,
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dacp->params->dmairqprio,
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(gd32_dmaisr_t)dac_lld_serve_tx_interrupt,
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(void *)dacp);
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osalDbgAssert(dacp->dma != NULL, "unable to allocate stream");
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/* DMA settings depend on the chosen DAC mode.*/
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switch (dacp->config->datamode) {
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/* Sets the DAC data register */
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case DAC_DHRM_12BIT_RIGHT:
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osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
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dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->R12DH0 +
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dacp->params->dataoffset);
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dmamode = dacp->params->dmamode |
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GD32_DMA_CTL_PWIDTH_HWORD | GD32_DMA_CTL_MWIDTH_HWORD;
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break;
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case DAC_DHRM_12BIT_LEFT:
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osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
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dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->L12DH0 +
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dacp->params->dataoffset);
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dmamode = dacp->params->dmamode |
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GD32_DMA_CTL_PWIDTH_HWORD | GD32_DMA_CTL_MWIDTH_HWORD;
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break;
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case DAC_DHRM_8BIT_RIGHT:
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osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
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dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->R8DH0 +
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dacp->params->dataoffset);
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dmamode = dacp->params->dmamode |
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GD32_DMA_CTL_PWIDTH_BYTE | GD32_DMA_CTL_MWIDTH_BYTE;
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/* In this mode the size of the buffer is halved because two samples
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packed in a single dacsample_t element.*/
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n = (n + 1) / 2;
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break;
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#if GD32_DAC_DUAL_MODE == TRUE
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case DAC_DHRM_12BIT_RIGHT_DUAL:
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osalDbgAssert(dacp->grpp->num_channels == 2, "invalid number of channels");
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dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->R12DH);
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dmamode = dacp->params->dmamode |
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GD32_DMA_CTL_PWIDTH_WORD | GD32_DMA_CTL_MWIDTH_WORD;
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n /= 2;
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break;
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case DAC_DHRM_12BIT_LEFT_DUAL:
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osalDbgAssert(dacp->grpp->num_channels == 2, "invalid number of channels");
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dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->L12DH);
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dmamode = dacp->params->dmamode |
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GD32_DMA_CTL_PWIDTH_WORD | GD32_DMA_CTL_MWIDTH_WORD;
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n /= 2;
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break;
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case DAC_DHRM_8BIT_RIGHT_DUAL:
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osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
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dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->R8DH);
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dmamode = dacp->params->dmamode |
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GD32_DMA_CTL_PWIDTH_HWORD | GD32_DMA_CTL_MWIDTH_HWORD;
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n /= 2;
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break;
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#endif
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default:
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osalDbgAssert(false, "unexpected DAC mode");
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return;
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}
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dmaStreamSetMemory0(dacp->dma, dacp->samples);
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dmaStreamSetTransactionSize(dacp->dma, n);
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dmaStreamSetMode(dacp->dma, dmamode |
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GD32_DMA_CTL_ERRIE |
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GD32_DMA_CTL_HTFIE | GD32_DMA_CTL_FTFIE);
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dmaStreamEnable(dacp->dma);
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/* DAC configuration.*/
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ctl = dacp->params->dac->CTL;
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#if GD32_DAC_DUAL_MODE == FALSE
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ctl &= dacp->params->regmask;
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ctl |= (DAC_CTL_DDMAEN0 | (dacp->grpp->trigger << DAC_CTL_DTSEL0_Pos) | DAC_CTL_DTEN0 | DAC_CTL_DEN0 | dacp->config->ctl) << dacp->params->regshift;
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#else
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ctl = DAC_CTL_DDMAEN0 | (dacp->grpp->trigger << DAC_CTL_DTSEL0_Pos) | DAC_CTL_DTEN0 | DAC_CTL_DEN0 | dacp->config->ctl
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| (dacp->grpp->trigger << DAC_CTL_DTSEL1_Pos) | DAC_CTL_DTEN1 | DAC_CTL_DEN1 | (dacp->config->ctl << 16);
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#endif
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dacp->params->dac->CTL = ctl;
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}
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/**
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* @brief Stops an ongoing conversion.
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* @details This function stops the currently ongoing conversion and returns
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* the driver in the @p DAC_READY state. If there was no conversion
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* being processed then the function does nothing.
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*
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* @param[in] dacp pointer to the @p DACDriver object
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*
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* @iclass
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*/
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void dac_lld_stop_conversion(DACDriver *dacp) {
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uint32_t ctl;
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/* DMA channel disabled and released.*/
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dmaStreamDisable(dacp->dma);
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dmaStreamFreeI(dacp->dma);
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dacp->dma = NULL;
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ctl = dacp->params->dac->CTL;
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#if GD32_DAC_DUAL_MODE == FALSE
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ctl &= dacp->params->regmask;
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ctl |= (DAC_CTL_DEN0 | dacp->config->ctl) << dacp->params->regshift;
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#else
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if ((dacp->config->datamode == DAC_DHRM_12BIT_RIGHT_DUAL) ||
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(dacp->config->datamode == DAC_DHRM_12BIT_LEFT_DUAL) ||
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(dacp->config->datamode == DAC_DHRM_8BIT_RIGHT_DUAL)) {
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ctl = DAC_CTL_DEN1 | (dacp->config->ctl << 16) |
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DAC_CTL_DEN0 | dacp->config->ctl;
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}
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else {
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ctl = DAC_CTL_DEN0 | dacp->config->ctl;
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}
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#endif
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dacp->params->dac->CTL = ctl;
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}
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#endif /* HAL_USE_DAC */
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/** @} */
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