591 lines
16 KiB
C
591 lines
16 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2021 Stefan Kerkmann
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file DMA/gd32_dma.c
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* @brief DMA helper driver code.
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*
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* @addtogroup GD32_DMA
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* @details DMA sharing helper driver. In the GD32 the DMA streams are a
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* shared resource, this driver allows to allocate and free DMA
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* streams at runtime in order to allow all the other device
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* drivers to coordinate the access to the resource.
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* @note The DMA ISR handlers are all declared into this module because
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* sharing, the various device drivers can associate a callback to
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* ISRs when allocating streams.
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* @{
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*/
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#include "hal.h"
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/* The following macro is only defined if some driver requiring DMA services
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has been enabled.*/
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#if defined(GD32_DMA_REQUIRED) || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/**
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* @brief Mask of the DMA0 streams in @p dma_streams_mask.
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*/
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#define GD32_DMA0_STREAMS_MASK ((1U << GD32_DMA0_NUM_CHANNELS) - 1U)
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/**
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* @brief Mask of the DMA1 streams in @p dma_streams_mask.
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*/
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#define GD32_DMA1_STREAMS_MASK (((1U << GD32_DMA1_NUM_CHANNELS) - \
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1U) << GD32_DMA0_NUM_CHANNELS)
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#define DMA0_CH0_VARIANT 0
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#define DMA0_CH1_VARIANT 0
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#define DMA0_CH2_VARIANT 0
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#define DMA0_CH3_VARIANT 0
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#define DMA0_CH4_VARIANT 0
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#define DMA0_CH5_VARIANT 0
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#define DMA0_CH6_VARIANT 0
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#define DMA1_CH0_VARIANT 0
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#define DMA1_CH1_VARIANT 0
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#define DMA1_CH2_VARIANT 0
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#define DMA1_CH3_VARIANT 0
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#define DMA1_CH4_VARIANT 0
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/*
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* Default ISR collision masks.
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*/
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#if !defined(GD32_DMA0_CH0_CMASK)
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#define GD32_DMA0_CH0_CMASK (1U << 0U)
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#endif
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#if !defined(GD32_DMA0_CH1_CMASK)
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#define GD32_DMA0_CH1_CMASK (1U << 1U)
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#endif
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#if !defined(GD32_DMA0_CH2_CMASK)
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#define GD32_DMA0_CH2_CMASK (1U << 2U)
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#endif
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#if !defined(GD32_DMA0_CH3_CMASK)
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#define GD32_DMA0_CH3_CMASK (1U << 3U)
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#endif
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#if !defined(GD32_DMA0_CH4_CMASK)
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#define GD32_DMA0_CH4_CMASK (1U << 4U)
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#endif
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#if !defined(GD32_DMA0_CH5_CMASK)
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#define GD32_DMA0_CH5_CMASK (1U << 5U)
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#endif
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#if !defined(GD32_DMA0_CH6_CMASK)
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#define GD32_DMA0_CH6_CMASK (1U << 6U)
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#endif
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#if !defined(GD32_DMA1_CH0_CMASK)
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#define GD32_DMA1_CH0_CMASK (1U << (GD32_DMA0_NUM_CHANNELS + 0U))
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#endif
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#if !defined(GD32_DMA1_CH1_CMASK)
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#define GD32_DMA1_CH1_CMASK (1U << (GD32_DMA0_NUM_CHANNELS + 1U))
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#endif
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#if !defined(GD32_DMA1_CH2_CMASK)
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#define GD32_DMA1_CH2_CMASK (1U << (GD32_DMA0_NUM_CHANNELS + 2U))
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#endif
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#if !defined(GD32_DMA1_CH3_CMASK)
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#define GD32_DMA1_CH3_CMASK (1U << (GD32_DMA0_NUM_CHANNELS + 3U))
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#endif
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#if !defined(GD32_DMA1_CH4_CMASK)
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#define GD32_DMA1_CH4_CMASK (1U << (GD32_DMA0_NUM_CHANNELS + 4U))
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#endif
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/**
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* @brief DMA streams descriptors.
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* @details This table keeps the association between an unique stream
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* identifier and the involved physical registers.
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* @note Don't use this array directly, use the appropriate wrapper macros
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* instead: @p GD32_DMA0_STREAM0, @p GD32_DMA0_STREAM1 etc.
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*/
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const gd32_dma_stream_t _gd32_dma_streams[GD32_DMA_STREAMS] = {
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{DMA0, DMA0_Channel0, GD32_DMA0_CH0_CMASK, DMA0_CH0_VARIANT, 0, 0, GD32_DMA0_CH0_NUMBER},
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{DMA0, DMA0_Channel1, GD32_DMA0_CH1_CMASK, DMA0_CH1_VARIANT, 4, 1, GD32_DMA0_CH1_NUMBER},
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{DMA0, DMA0_Channel2, GD32_DMA0_CH2_CMASK, DMA0_CH2_VARIANT, 8, 2, GD32_DMA0_CH2_NUMBER},
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{DMA0, DMA0_Channel3, GD32_DMA0_CH3_CMASK, DMA0_CH3_VARIANT, 12, 3, GD32_DMA0_CH3_NUMBER},
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{DMA0, DMA0_Channel4, GD32_DMA0_CH4_CMASK, DMA0_CH4_VARIANT, 16, 4, GD32_DMA0_CH4_NUMBER},
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{DMA0, DMA0_Channel5, GD32_DMA0_CH5_CMASK, DMA0_CH5_VARIANT, 20, 5, GD32_DMA0_CH5_NUMBER},
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{DMA0, DMA0_Channel6, GD32_DMA0_CH6_CMASK, DMA0_CH6_VARIANT, 24, 6, GD32_DMA0_CH6_NUMBER},
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{DMA1, DMA1_Channel0, GD32_DMA1_CH0_CMASK, DMA1_CH0_VARIANT, 0, 0 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH0_NUMBER},
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{DMA1, DMA1_Channel1, GD32_DMA1_CH1_CMASK, DMA1_CH1_VARIANT, 4, 1 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH1_NUMBER},
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{DMA1, DMA1_Channel2, GD32_DMA1_CH2_CMASK, DMA1_CH2_VARIANT, 8, 2 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH2_NUMBER},
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{DMA1, DMA1_Channel3, GD32_DMA1_CH3_CMASK, DMA1_CH3_VARIANT, 12, 3 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH3_NUMBER},
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{DMA1, DMA1_Channel4, GD32_DMA1_CH4_CMASK, DMA1_CH4_VARIANT, 16, 4 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH4_NUMBER},
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};
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/**
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* @brief Global DMA-related data structures.
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*/
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static struct {
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/**
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* @brief Mask of the allocated streams.
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*/
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uint32_t allocated_mask;
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/**
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* @brief Mask of the enabled streams ISRs.
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*/
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uint32_t isr_mask;
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/**
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* @brief DMA IRQ redirectors.
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*/
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struct {
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/**
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* @brief DMA callback function.
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*/
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gd32_dmaisr_t func;
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/**
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* @brief DMA callback parameter.
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*/
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void *param;
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} streams[GD32_DMA_STREAMS];
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} dma;
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if defined(GD32_DMA0_CH0_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA0 stream 0 shared ISR.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_DMA0_CH0_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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dmaServeInterrupt(GD32_DMA0_STREAM0);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(GD32_DMA0_CH1_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA0 stream 1 shared ISR.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_DMA0_CH1_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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dmaServeInterrupt(GD32_DMA0_STREAM1);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(GD32_DMA0_CH2_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA0 stream 2 shared ISR.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_DMA0_CH2_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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dmaServeInterrupt(GD32_DMA0_STREAM2);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(GD32_DMA0_CH3_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA0 stream 3 shared ISR.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_DMA0_CH3_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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dmaServeInterrupt(GD32_DMA0_STREAM3);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(GD32_DMA0_CH4_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA0 stream 4 shared ISR.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_DMA0_CH4_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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dmaServeInterrupt(GD32_DMA0_STREAM4);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(GD32_DMA0_CH5_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA0 stream 5 shared ISR.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_DMA0_CH5_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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dmaServeInterrupt(GD32_DMA0_STREAM5);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(GD32_DMA0_CH6_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA0 stream 6 shared ISR.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_DMA0_CH6_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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dmaServeInterrupt(GD32_DMA0_STREAM6);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(GD32_DMA1_CH0_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA1 stream 0 shared ISR.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_DMA1_CH0_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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dmaServeInterrupt(GD32_DMA1_STREAM0);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(GD32_DMA1_CH1_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA1 stream 1 shared ISR.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_DMA1_CH1_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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dmaServeInterrupt(GD32_DMA1_STREAM1);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(GD32_DMA1_CH2_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA1 stream 2 shared ISR.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_DMA1_CH2_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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dmaServeInterrupt(GD32_DMA1_STREAM2);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(GD32_DMA1_CH3_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA1 stream 3 shared ISR.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_DMA1_CH3_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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dmaServeInterrupt(GD32_DMA1_STREAM3);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if defined(GD32_DMA1_CH4_HANDLER) || defined(__DOXYGEN__)
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/**
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* @brief DMA1 stream 4 shared ISR.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_DMA1_CH4_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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dmaServeInterrupt(GD32_DMA1_STREAM4);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief GD32 DMA helper initialization.
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*
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* @init
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*/
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void dmaInit(void) {
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int i;
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dma.allocated_mask = 0U;
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dma.isr_mask = 0U;
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for (i = 0; i < GD32_DMA_STREAMS; i++) {
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_gd32_dma_streams[i].channel->CTL = GD32_DMA_CTL_RESET_VALUE;
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dma.streams[i].func = NULL;
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}
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DMA0->INTC = 0xFFFFFFFFU;
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DMA1->INTC = 0xFFFFFFFFU;
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}
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/**
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* @brief Allocates a DMA stream.
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* @details The stream is allocated and, if required, the DMA clock enabled.
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* The function also enables the IRQ vector associated to the stream
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* and initializes its priority.
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*
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* @param[in] id numeric identifiers of a specific stream or:
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* - @p GD32_DMA_STREAM_ID_ANY for any stream.
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* - @p GD32_DMA_STREAM_ID_ANY_DMA0 for any stream
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* on DMA0.
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* - @p GD32_DMA_STREAM_ID_ANY_DMA1 for any stream
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* on DMA1.
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* .
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* @param[in] priority IRQ priority for the DMA stream
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* @param[in] func handling function pointer, can be @p NULL
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* @param[in] param a parameter to be passed to the handling function
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* @return Pointer to the allocated @p gd32_dma_stream_t
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* structure.
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* @retval NULL if a/the stream is not available.
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*
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* @iclass
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*/
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const gd32_dma_stream_t *dmaStreamAllocI(uint32_t id,
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uint32_t priority,
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gd32_dmaisr_t func,
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void *param) {
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uint32_t i, startid, endid;
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osalDbgCheckClassI();
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if (id < GD32_DMA_STREAMS) {
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startid = id;
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endid = id;
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} else {
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osalDbgCheck(false);
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return NULL;
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}
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for (i = startid; i <= endid; i++) {
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uint32_t mask = (1U << i);
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if ((dma.allocated_mask & mask) == 0U) {
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const gd32_dma_stream_t *dmastp = GD32_DMA_STREAM(i);
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/* Installs the DMA handler.*/
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dma.streams[i].func = func;
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dma.streams[i].param = param;
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dma.allocated_mask |= mask;
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/* Enabling DMA clocks required by the current streams set.*/
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if ((GD32_DMA0_STREAMS_MASK & mask) != 0U) {
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rcuEnableDMA0(true);
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}
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if ((GD32_DMA1_STREAMS_MASK & mask) != 0U) {
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rcuEnableDMA1(true);
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}
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/* Enables the associated IRQ vector if not already enabled and if a
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callback is defined.*/
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if (func != NULL) {
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if ((dma.isr_mask & dmastp->cmask) == 0U) {
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eclicEnableVector(dmastp->vector, priority, ECLIC_DMA_TRIGGER);
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}
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dma.isr_mask |= mask;
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}
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/* Putting the stream in a known state.*/
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dmaStreamDisable(dmastp);
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dmastp->channel->CTL = GD32_DMA_CTL_RESET_VALUE;
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return dmastp;
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}
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}
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return NULL;
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}
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/**
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* @brief Allocates a DMA stream.
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* @details The stream is allocated and, if required, the DMA clock enabled.
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* The function also enables the IRQ vector associated to the stream
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* and initializes its priority.
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*
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* @param[in] id numeric identifiers of a specific stream or:
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* - @p GD32_DMA_STREAM_ID_ANY for any stream.
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* - @p GD32_DMA_STREAM_ID_ANY_DMA0 for any stream
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* on DMA0.
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* - @p GD32_DMA_STREAM_ID_ANY_DMA1 for any stream
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* on DMA1.
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* .
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* @param[in] priority IRQ priority for the DMA stream
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* @param[in] func handling function pointer, can be @p NULL
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* @param[in] param a parameter to be passed to the handling function
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* @return Pointer to the allocated @p gd32_dma_stream_t
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* structure.
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* @retval NULL if a/the stream is not available.
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*
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* @api
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*/
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const gd32_dma_stream_t *dmaStreamAlloc(uint32_t id,
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uint32_t priority,
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gd32_dmaisr_t func,
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void *param) {
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const gd32_dma_stream_t *dmastp;
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osalSysLock();
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dmastp = dmaStreamAllocI(id, priority, func, param);
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osalSysUnlock();
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|
|
|
return dmastp;
|
|
}
|
|
|
|
/**
|
|
* @brief Releases a DMA stream.
|
|
* @details The stream is freed and, if required, the DMA clock disabled.
|
|
* Trying to release a unallocated stream is an illegal operation
|
|
* and is trapped if assertions are enabled.
|
|
*
|
|
* @param[in] dmastp pointer to a gd32_dma_stream_t structure
|
|
*
|
|
* @iclass
|
|
*/
|
|
void dmaStreamFreeI(const gd32_dma_stream_t *dmastp) {
|
|
uint32_t selfindex = (uint32_t)dmastp->selfindex;
|
|
|
|
osalDbgCheck(dmastp != NULL);
|
|
|
|
/* Check if the streams is not taken.*/
|
|
osalDbgAssert((dma.allocated_mask & (1 << selfindex)) != 0U,
|
|
"not allocated");
|
|
|
|
/* Marks the stream as not allocated.*/
|
|
dma.allocated_mask &= ~(1U << selfindex);
|
|
dma.isr_mask &= ~(1U << selfindex);
|
|
|
|
/* Disables the associated IRQ vector if it is no more in use.*/
|
|
if ((dma.isr_mask & dmastp->cmask) == 0U) {
|
|
eclicDisableVector(dmastp->vector);
|
|
}
|
|
|
|
/* Removes the DMA handler.*/
|
|
dma.streams[selfindex].func = NULL;
|
|
dma.streams[selfindex].param = NULL;
|
|
|
|
/* Shutting down clocks that are no more required, if any.*/
|
|
if ((dma.allocated_mask & GD32_DMA0_STREAMS_MASK) == 0U) {
|
|
rcuDisableDMA0();
|
|
}
|
|
if ((dma.allocated_mask & GD32_DMA1_STREAMS_MASK) == 0U) {
|
|
rcuDisableDMA1();
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Releases a DMA stream.
|
|
* @details The stream is freed and, if required, the DMA clock disabled.
|
|
* Trying to release a unallocated stream is an illegal operation
|
|
* and is trapped if assertions are enabled.
|
|
*
|
|
* @param[in] dmastp pointer to a gd32_dma_stream_t structure
|
|
*
|
|
* @api
|
|
*/
|
|
void dmaStreamFree(const gd32_dma_stream_t *dmastp) {
|
|
|
|
osalSysLock();
|
|
dmaStreamFreeI(dmastp);
|
|
osalSysUnlock();
|
|
}
|
|
|
|
/**
|
|
* @brief Serves a DMA IRQ.
|
|
*
|
|
* @param[in] dmastp pointer to a gd32_dma_stream_t structure
|
|
*
|
|
* @special
|
|
*/
|
|
void dmaServeInterrupt(const gd32_dma_stream_t *dmastp) {
|
|
uint32_t flags;
|
|
uint32_t selfindex = (uint32_t)dmastp->selfindex;
|
|
|
|
flags = (dmastp->dma->INTF >> dmastp->shift) & GD32_DMA_INTF_MASK;
|
|
if (flags & dmastp->channel->CTL) {
|
|
dmastp->dma->INTC = flags << dmastp->shift;
|
|
if (dma.streams[selfindex].func) {
|
|
dma.streams[selfindex].func(dma.streams[selfindex].param, flags);
|
|
}
|
|
}
|
|
}
|
|
|
|
#endif /* GD32_DMA_REQUIRED */
|
|
|
|
/** @} */
|