865 lines
43 KiB
C
865 lines
43 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2021 Stefan Kerkmann
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file OTG/gd32_otg.h
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* @brief GD32 OTG registers layout header.
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*
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* @addtogroup USB
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* @{
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*/
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#ifndef GD32_USBFS_H
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#define GD32_USBFS_H
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/**
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* @brief USBFS FIFO memory size in words.
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*/
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#define GD32_USBFS_FIFO_MEM_SIZE 320
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/**
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* @brief Host channel registers group.
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*/
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typedef struct {
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volatile uint32_t HCHCTL; /**< @brief Host channel characteristics
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register. */
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volatile uint32_t resvd8;
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volatile uint32_t HCHINTF; /**< @brief Host channel interrupt register.*/
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volatile uint32_t HCHINTEN; /**< @brief Host channel interrupt mask
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register. */
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volatile uint32_t HCHLEN; /**< @brief Host channel transfer size
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register. */
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volatile uint32_t resvd14;
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volatile uint32_t resvd18;
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volatile uint32_t resvd1c;
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} gd32_usbfs_host_chn_t;
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/**
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* @brief Device input endpoint registers group.
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*/
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typedef struct {
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volatile uint32_t DIEPCTL; /**< @brief Device control IN endpoint
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control register. */
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volatile uint32_t resvd4;
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volatile uint32_t DIEPINTF; /**< @brief Device IN endpoint interrupt
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register. */
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volatile uint32_t resvdC;
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volatile uint32_t DIEPLEN; /**< @brief Device IN endpoint transfer size
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register. */
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volatile uint32_t resvd14;
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volatile uint32_t DIEPTFSTAT; /**< @brief Device IN endpoint transmit FIFO
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status register. */
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volatile uint32_t resvd1C;
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} gd32_usbfs_in_ep_t;
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/**
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* @brief Device output endpoint registers group.
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*/
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typedef struct {
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volatile uint32_t DOEPCTL; /**< @brief Device control OUT endpoint
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control register. */
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volatile uint32_t resvd4;
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volatile uint32_t DOEPINTF; /**< @brief Device OUT endpoint interrupt
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register. */
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volatile uint32_t resvdC;
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volatile uint32_t DOEPLEN; /**< @brief Device OUT endpoint transfer
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size register. */
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volatile uint32_t resvd14;
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volatile uint32_t resvd18;
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volatile uint32_t resvd1C;
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} gd32_usbfs_out_ep_t;
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/**
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* @brief USB registers memory map.
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*/
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typedef struct {
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volatile uint32_t GOTGCS; /**< @brief OTG control and status register.*/
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volatile uint32_t GOTGINTF; /**< @brief OTG interrupt register. */
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volatile uint32_t GAHBCS; /**< @brief AHB configuration register. */
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volatile uint32_t GUSBCS; /**< @brief USB configuration register. */
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volatile uint32_t GRSTCTL; /**< @brief Reset register size. */
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volatile uint32_t GINTF; /**< @brief Interrupt register. */
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volatile uint32_t GINTEN; /**< @brief Interrupt mask register. */
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volatile uint32_t GRSTATR; /**< @brief Receive status debug read
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register. */
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volatile uint32_t GRSTATP; /**< @brief Receive status read/pop
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register. */
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volatile uint32_t GRFLEN; /**< @brief Receive FIFO size register. */
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volatile uint32_t DIEPTFLEN0; /**< @brief Endpoint 0 transmit FIFO size
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register. */
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volatile uint32_t HNPTFQSTAT; /**< @brief Non-periodic transmit FIFO/queue
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status register. */
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volatile uint32_t resvd30;
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volatile uint32_t resvd34;
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volatile uint32_t GCCFG; /**< @brief General core configuration. */
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volatile uint32_t CID; /**< @brief Core ID register. */
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volatile uint32_t resvd58[48];
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volatile uint32_t HPTFLEN; /**< @brief Host periodic transmit FIFO size
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register. */
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volatile uint32_t DIEPTFLEN[15];/**< @brief Device IN endpoint transmit FIFO
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size registers. */
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volatile uint32_t resvd140[176];
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volatile uint32_t HCTL; /**< @brief Host configuration register. */
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volatile uint32_t HFT; /**< @brief Host frame interval register. */
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volatile uint32_t HFINFR; /**< @brief Host frame number/frame time
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Remaining register. */
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volatile uint32_t resvd40C;
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volatile uint32_t HPTFQSTAT; /**< @brief Host periodic transmit FIFO/queue
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status register. */
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volatile uint32_t HACHINT; /**< @brief Host all channels interrupt
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register. */
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volatile uint32_t HACHINTEN; /**< @brief Host all channels interrupt mask
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register. */
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volatile uint32_t resvd41C[9];
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volatile uint32_t HPCS; /**< @brief Host port control and status
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register. */
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volatile uint32_t resvd444[47];
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gd32_usbfs_host_chn_t hc[16]; /**< @brief Host channels array. */
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volatile uint32_t resvd700[64];
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volatile uint32_t DCFG; /**< @brief Device configuration register. */
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volatile uint32_t DCTL; /**< @brief Device control register. */
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volatile uint32_t DSTAT; /**< @brief Device status register. */
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volatile uint32_t resvd80C;
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volatile uint32_t DIEPINTF; /**< @brief Device IN endpoint common
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interrupt mask register. */
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volatile uint32_t DOEPINTF; /**< @brief Device OUT endpoint common
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interrupt mask register. */
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volatile uint32_t DAEPINT; /**< @brief Device all endpoints interrupt
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register. */
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volatile uint32_t DAEPINTEN; /**< @brief Device all endpoints interrupt
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mask register. */
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volatile uint32_t resvd820;
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volatile uint32_t resvd824;
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volatile uint32_t DVBUSDT; /**< @brief Device VBUS discharge time
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register. */
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volatile uint32_t DVBUSPT; /**< @brief Device VBUS pulsing time
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register. */
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volatile uint32_t resvd830;
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volatile uint32_t DIEPFEINTEN; /**< @brief Device IN endpoint FIFO empty
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interrupt mask register. */
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volatile uint32_t resvd838;
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volatile uint32_t resvd83C;
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volatile uint32_t resvd840[16];
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volatile uint32_t resvd880[16];
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volatile uint32_t resvd8C0[16];
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gd32_usbfs_in_ep_t ie[16]; /**< @brief Input endpoints. */
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gd32_usbfs_out_ep_t oe[16]; /**< @brief Output endpoints. */
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volatile uint32_t resvdD00[64];
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volatile uint32_t PWRCLKCTL; /**< @brief Power and clock gating control
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register. */
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volatile uint32_t resvdE04[127];
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volatile uint32_t FIFO[16][1024];
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} gd32_usbfs_t;
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/**
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* @name GOTGCS register bit definitions
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* @{
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*/
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#define GOTGCS_BSV (1U<<19) /**< B-Session Valid. */
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#define GOTGCS_ASV (1U<<18) /**< A-Session Valid. */
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#define GOTGCS_DI (1U<<17) /**< Long/Short debounce time. */
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#define GOTGCS_IDPS (1U<<16) /**< Connector ID status. */
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#define GOTGCS_DHNPEN (1U<<11) /**< Device HNP enabled. */
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#define GOTGCS_HHNPEN (1U<<10) /**< Host Set HNP enable. */
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#define GOTGCS_HNPREQ (1U<<9) /**< HNP request. */
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#define GOTGCS_HNPS (1U<<8) /**< Host negotiation success. */
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#define GOTGCS_SRPREQ (1U<<1) /**< Session request. */
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#define GOTGCS_SRPREQSCS (1U<<0) /**< Session request success. */
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/** @} */
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/**
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* @name GOTGINTF register bit definitions
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* @{
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*/
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#define GOTGINTF_DF (1U<<19) /**< Debounce done. */
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#define GOTGINTF_ADTO (1U<<18) /**< A-Device timeout change. */
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#define GOTGINTF_HNPDET (1U<<17) /**< Host negotiation detected. */
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#define GOTGINTF_HNPEND (1U<<9) /**< Host negotiation success
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status change. */
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#define GOTGINTF_SRPEND (1U<<8) /**< Session request success
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status change. */
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#define GOTGINTF_SESEND (1U<<2) /**< Session end detected. */
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/** @} */
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/**
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* @name GAHBCS register bit definitions
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* @{
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*/
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#define GAHBCS_PTXFTH (1U<<8) /**< Periodic TxFIFO empty
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level. */
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#define GAHBCS_TXFTH (1U<<7) /**< Non-periodic TxFIFO empty
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level. */
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#define GAHBCS_GINTEN (1U<<0) /**< Global interrupt mask. */
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/** @} */
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/**
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* @name GUSBCS register bit definitions
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* @{
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*/
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#define GUSBCS_FDM (1U<<30) /**< Force Device Mode. */
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#define GUSBCS_FHM (1U<<29) /**< Force Host Mode. */
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#define GUSBCS_UTT_MASK (15U<<10) /**< USB Turnaround time field
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mask. */
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#define GUSBCS_UTT(n) ((n)<<10) /**< USB Turnaround time field
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value. */
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#define GUSBCS_HNPCEN (1U<<9) /**< HNP-Capable. */
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#define GUSBCS_SRPCEN (1U<<8) /**< SRP-Capable. */
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#define GUSBCS_TOC_MASK (7U<<0) /**< HS/FS timeout calibration
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field mask. */
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#define GUSBCS_TOC(n) ((n)<<0) /**< HS/FS timeout calibration
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field value. */
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/** @} */
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/**
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* @name GRSTCTL register bit definitions
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* @{
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*/
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#define GRSTCTL_TXFNUM_MASK (31U<<6) /**< TxFIFO number field mask. */
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#define GRSTCTL_TXFNUM(n) ((n)<<6) /**< TxFIFO number field value. */
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#define GRSTCTL_TXFF (1U<<5) /**< TxFIFO flush. */
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#define GRSTCTL_RXFF (1U<<4) /**< RxFIFO flush. */
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#define GRSTCTL_HFCRST (1U<<2) /**< Host frame counter reset. */
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#define GRSTCTL_HCSRST (1U<<1) /**< HClk soft reset. */
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#define GRSTCTL_CSRST (1U<<0) /**< Core soft reset. */
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/** @} */
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/**
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* @name GINTF register bit definitions
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* @{
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*/
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#define GINTF_WKUPIF (1U<<31) /**< Resume/Remote wakeup
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detected interrupt. */
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#define GINTF_SESIF (1U<<30) /**< Session request/New session
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detected interrupt. */
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#define GINTF_DISCIF (1U<<29) /**< Disconnect detected
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interrupt. */
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#define GINTF_IDPSC (1U<<28) /**< Connector ID status change.*/
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#define GINTF_PTXFEIF (1U<<26) /**< Periodic TxFIFO empty. */
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#define GINTF_HCIF (1U<<25) /**< Host channels interrupt. */
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#define GINTF_HPIF (1U<<24) /**< Host port interrupt. */
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#define GINTF_PXNCIF (1U<<21) /**< Incomplete periodic
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transfer. */
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#define GINTF_ISOONCIF (1U<<21) /**< Incomplete isochronous OUT
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transfer. */
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#define GINTF_ISOINCIF (1U<<20) /**< Incomplete isochronous IN
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transfer. */
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#define GINTF_OEPIF (1U<<19) /**< OUT endpoints interrupt. */
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#define GINTF_IEPIF (1U<<18) /**< IN endpoints interrupt. */
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#define GINTF_EOPFIF (1U<<15) /**< End of periodic frame
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interrupt. */
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#define GINTF_ISOOPDIF (1U<<14) /**< Isochronous OUT packet
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dropped interrupt. */
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#define GINTF_ENUMF (1U<<13) /**< Enumeration done. */
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#define GINTF_RST (1U<<12) /**< USB reset. */
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#define GINTF_SP (1U<<11) /**< USB suspend. */
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#define GINTF_ESP (1U<<10) /**< Early suspend. */
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#define GINTF_GONAK (1U<<7) /**< Global OUT NAK effective. */
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#define GINTF_GNPINAK (1U<<6) /**< Global IN non-periodic NAK
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effective. */
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#define GINTF_NPTXFEIF (1U<<5) /**< Non-periodic TxFIFO empty. */
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#define GINTF_RXFNEIF (1U<<4) /**< RxFIFO non-empty. */
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#define GINTF_SOF (1U<<3) /**< Start of frame. */
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#define GINTF_OTGIF (1U<<2) /**< OTG interrupt. */
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#define GINTF_MFIF (1U<<1) /**< Mode Mismatch interrupt. */
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#define GINTF_COPM (1U<<0) /**< Current mode of operation. */
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/** @} */
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/**
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* @name GINTEN register bit definitions
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* @{
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*/
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#define GINTEN_WKUPIE (1U<<31) /**< Resume/remote wakeup
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detected interrupt mask. */
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#define GINTEN_SESIE (1U<<30) /**< Session request/New session
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detected interrupt mask. */
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#define GINTEN_DISCIE (1U<<29) /**< Disconnect detected
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interrupt mask. */
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#define GINTEN_IDPSCIE (1U<<28) /**< Connector ID status change
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mask. */
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#define GINTEN_PTXFEIFE (1U<<26) /**< Periodic TxFIFO empty mask.*/
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#define GINTEN_HCIE (1U<<25) /**< Host channels interrupt
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mask. */
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#define GINTEN_HPIE (1U<<24) /**< Host port interrupt mask. */
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#define GINTEN_PXNCIE (1U<<21) /**< Incomplete periodic
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transfer mask. */
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#define GINTEN_ISOONCIE (1U<<21) /**< Incomplete isochronous OUT
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transfer mask. */
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#define GINTEN_ISOINCIE (1U<<20) /**< Incomplete isochronous IN
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transfer mask. */
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#define GINTEN_OEPIE (1U<<19) /**< OUT endpoints interrupt
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mask. */
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#define GINTEN_IEPIE (1U<<18) /**< IN endpoints interrupt
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mask. */
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#define GINTEN_EOPFIE (1U<<15) /**< End of periodic frame
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interrupt mask. */
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#define GINTEN_ISOOPDIE (1U<<14) /**< Isochronous OUT packet
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dropped interrupt mask. */
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#define GINTEN_ENUMFIE (1U<<13) /**< Enumeration done mask. */
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#define GINTEN_RSTIE (1U<<12) /**< USB reset mask. */
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#define GINTEN_SPIE (1U<<11) /**< USB suspend mask. */
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#define GINTEN_ESPIE (1U<<10) /**< Early suspend mask. */
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#define GINTEN_GONAKIE (1U<<7) /**< Global OUT NAK effective
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mask. */
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#define GINTEN_GNPINAKIE (1U<<6) /**< Global non-periodic IN NAK
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effective mask. */
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#define GINTEN_NPTXFEIE (1U<<5) /**< Non-periodic TxFIFO empty
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mask. */
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#define GINTEN_RXFNEIE (1U<<4) /**< Receive FIFO non-empty
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mask. */
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#define GINTEN_SOFIE (1U<<3) /**< Start of (micro)frame mask.*/
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#define GINTEN_OTGIE (1U<<2) /**< OTG interrupt mask. */
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#define GINTEN_MFIE (1U<<1) /**< Mode Mismatch interrupt
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mask. */
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/** @} */
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/**
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* @name GRSTATR register bit definitions
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* @{
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*/
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#define GRSTATR_RPCKST_MASK (15U<<17) /**< Packet status mask. */
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#define GRSTATR_RPCKST(n) ((n)<<17) /**< Packet status value. */
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#define GRSTATR_OUT_GLOBAL_NAK GRSTATR_RPCKST(1)
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#define GRSTATR_OUT_DATA GRSTATR_RPCKST(2)
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#define GRSTATR_OUT_COMP GRSTATR_RPCKST(3)
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#define GRSTATR_SETUP_COMP GRSTATR_RPCKST(4)
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#define GRSTATR_SETUP_DATA GRSTATR_RPCKST(6)
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#define GRSTATR_DPID_MASK (3U<<15) /**< Data PID mask. */
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#define GRSTATR_DPID(n) ((n)<<15) /**< Data PID value. */
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#define GRSTATR_BCOUNT_MASK (0x7FF<<4) /**< Byte count mask. */
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#define GRSTATR_BCOUNT(n) ((n)<<4) /**< Byte count value. */
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#define GRSTATR_CNUM_MASK (15U<<0) /**< Channel number mask. */
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#define GRSTATR_CNUM(n) ((n)<<0) /**< Channel number value. */
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#define GRSTATR_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */
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#define GRSTATR_EPNUM(n) ((n)<<0) /**< Endpoint number value. */
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/** @} */
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/**
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* @name GRSTATP register bit definitions
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* @{
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*/
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#define GRSTATP_RPCKST_MASK (15<<17) /**< Packet status mask. */
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#define GRSTATP_RPCKST(n) ((n)<<17) /**< Packet status value. */
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#define GRSTATP_OUT_GLOBAL_NAK GRSTATP_RPCKST(1)
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#define GRSTATP_OUT_DATA GRSTATP_RPCKST(2)
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#define GRSTATP_OUT_COMP GRSTATP_RPCKST(3)
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#define GRSTATP_SETUP_COMP GRSTATP_RPCKST(4)
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#define GRSTATP_SETUP_DATA GRSTATP_RPCKST(6)
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#define GRSTATP_DPID_MASK (3U<<15) /**< Data PID mask. */
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#define GRSTATP_DPID(n) ((n)<<15) /**< Data PID value. */
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#define GRSTATP_BCOUNT_MASK (0x7FF<<4) /**< Byte count mask. */
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#define GRSTATP_BCOUNT_OFF 4 /**< Byte count offset. */
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#define GRSTATP_BCOUNT(n) ((n)<<4) /**< Byte count value. */
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#define GRSTATP_CNUM_MASK (15U<<0) /**< Channel number mask. */
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#define GRSTATP_CNUM(n) ((n)<<0) /**< Channel number value. */
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#define GRSTATP_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */
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#define GRSTATP_EPNUM_OFF 0 /**< Endpoint number offset. */
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#define GRSTATP_EPNUM(n) ((n)<<0) /**< Endpoint number value. */
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/** @} */
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/**
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* @name GRFLEN register bit definitions
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* @{
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*/
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#define GRFLEN_RXFD_MASK (0xFFFF<<0) /**< RxFIFO depth mask. */
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#define GRFLEN_RXFD(n) ((n)<<0) /**< RxFIFO depth value. */
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/** @} */
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/**
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* @name DIEPTFLENx register bit definitions
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* @{
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*/
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#define DIEPTFLEN_IEPTXFD_MASK (0xFFFFU<<16)/**< IN endpoint TxFIFO depth
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mask. */
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#define DIEPTFLEN_IEPTXFD(n) ((n)<<16) /**< IN endpoint TxFIFO depth
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value. */
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#define DIEPTFLEN_IEPTXRSAR_MASK (0xFFFF<<0) /**< IN endpoint FIFOx transmit
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RAM start address mask. */
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#define DIEPTFLEN_IEPTXRSAR(n) ((n)<<0) /**< IN endpoint FIFOx transmit
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RAM start address value. */
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/** @} */
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/**
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* @name GCCFG register bit definitions
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* @{
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*/
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/* Definitions for stepping 1.*/
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#define GCCFG_VBUSIG (1U<<21) /**< VBUS sensing disable. */
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#define GCCFG_SOFOEN (1U<<20) /**< SOF output enable. */
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#define GCCFG_VBUSBCEN (1U<<19) /**< Enable the VBUS sensing "B"
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device. */
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#define GCCFG_VBUSACEN (1U<<18) /**< Enable the VBUS sensing "A"
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device. */
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#define GCCFG_PWRON (1U<<16) /**< Power down. */
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/** @} */
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/**
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* @name HPTFLEN register bit definitions
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* @{
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*/
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#define HPTFLEN_HPTXFD_MASK (0xFFFFU<<16)/**< Host periodic TxFIFO
|
|
depth mask. */
|
|
#define HPTFLEN_HPTXFD(n) ((n)<<16) /**< Host periodic TxFIFO
|
|
depth value. */
|
|
#define HPTFLEN_HPTXRSAR_MASK (0xFFFFU<<0)/**< Host periodic TxFIFO
|
|
Start address mask. */
|
|
#define HPTFLEN_HPTXRSAR(n) ((n)<<0) /**< Host periodic TxFIFO
|
|
start address value. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name HCTL register bit definitions
|
|
* @{
|
|
*/
|
|
#define HCTL_CLKSEL (1U<<2) /**< FS- and LS-only support. */
|
|
#define HCTL_CLKSELPCS_MASK (3U<<0) /**< FS/LS PHY clock select
|
|
mask. */
|
|
#define HCTL_CLKSELPCS_48 (1U<<0) /**< PHY clock is running at
|
|
48 MHz. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name HFT register bit definitions
|
|
* @{
|
|
*/
|
|
#define HFT_FRI_MASK (0xFFFFU<<0)/**< Frame interval mask. */
|
|
#define HFT_FRI(n) ((n)<<0) /**< Frame interval value. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name HFINFR register bit definitions
|
|
* @{
|
|
*/
|
|
#define HFINFR_FTR_MASK (0xFFFFU<<16)/**< Frame time Remaining mask.*/
|
|
#define HFINFR_FTR(n) ((n)<<16) /**< Frame time Remaining value.*/
|
|
#define HFINFR_FRNUM_MASK (0xFFFFU<<0)/**< Frame number mask. */
|
|
#define HFINFR_FRNUM(n) ((n)<<0) /**< Frame number value. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name HPTFQSTAT register bit definitions
|
|
* @{
|
|
*/
|
|
#define HPTFQSTAT_PTXREQT_MASK (0xFFU<<24) /**< Top of the periodic
|
|
transmit request queue
|
|
mask. */
|
|
#define HPTFQSTAT_PTXREQT(n) ((n)<<24) /**< Top of the periodic
|
|
transmit request queue
|
|
value. */
|
|
#define HPTFQSTAT_PTXREQS_MASK (0xFF<<16) /**< Periodic transmit request
|
|
queue Space Available
|
|
mask. */
|
|
#define HPTFQSTAT_PTXREQS(n) ((n)<<16) /**< Periodic transmit request
|
|
queue Space Available
|
|
value. */
|
|
#define HPTFQSTAT_PTXFS_MASK (0xFFFF<<0) /**< Periodic transmit Data
|
|
FIFO Space Available
|
|
mask. */
|
|
#define HPTFQSTAT_PTXFS(n) ((n)<<0) /**< Periodic transmit Data
|
|
FIFO Space Available
|
|
value. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name HACHINT register bit definitions
|
|
* @{
|
|
*/
|
|
#define HACHINT_HACHINT_MASK (0xFFFFU<<0)/**< Channel interrupts mask. */
|
|
#define HACHINT_HACHINT(n) ((n)<<0) /**< Channel interrupts value. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name HACHINTEN register bit definitions
|
|
* @{
|
|
*/
|
|
#define HACHINTEN_CINTEN_MASK (0xFFFFU<<0)/**< Channel interrupt mask
|
|
mask. */
|
|
#define HACHINTEN_CINTEN(n) ((n)<<0) /**< Channel interrupt mask
|
|
value. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name HPCS register bit definitions
|
|
* @{
|
|
*/
|
|
#define HPCS_PS_MASK (3U<<17) /**< Port speed mask. */
|
|
#define HPCS_PS_FS (1U<<17) /**< Full speed value. */
|
|
#define HPCS_PS_LS (2U<<17) /**< Low speed value. */
|
|
#define HPCS_PP (1U<<12) /**< Port power. */
|
|
#define HPCS_PLST_MASK (3U<<11) /**< Port Line status mask. */
|
|
#define HPCS_PLST_DM (1U<<11) /**< Logic level of D-. */
|
|
#define HPCS_PLST_DP (1U<<10) /**< Logic level of D+. */
|
|
#define HPCS_PRST (1U<<8) /**< Port reset. */
|
|
#define HPCS_PSP (1U<<7) /**< Port suspend. */
|
|
#define HPCS_PREM (1U<<6) /**< Port Resume. */
|
|
#define HPCS_PEDC (1U<<3) /**< Port enable/disable change.*/
|
|
#define HPCS_PE (1U<<2) /**< Port enable. */
|
|
#define HPCS_PCD (1U<<1) /**< Port Connect detected. */
|
|
#define HPCS_PCST (1U<<0) /**< Port connect status. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name HCHCTL register bit definitions
|
|
* @{
|
|
*/
|
|
#define HCHCTL_CEN (1U<<31) /**< Channel enable. */
|
|
#define HCHCTL_CDIS (1U<<30) /**< Channel Disable. */
|
|
#define HCHCTL_ODDFRM (1U<<29) /**< Odd frame. */
|
|
#define HCHCTL_DAR_MASK (0x7FU<<22) /**< Device Address mask. */
|
|
#define HCHCTL_DAR(n) ((n)<<22) /**< Device Address value. */
|
|
#define HCHCTL_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */
|
|
#define HCHCTL_EPTYP(n) ((n)<<18) /**< Endpoint type value. */
|
|
#define HCHCTL_EPTYP_CTL (0U<<18) /**< Control endpoint value. */
|
|
#define HCHCTL_EPTYP_ISO (1U<<18) /**< Isochronous endpoint value.*/
|
|
#define HCHCTL_EPTYP_BULK (2U<<18) /**< Bulk endpoint value. */
|
|
#define HCHCTL_EPTYP_INTR (3U<<18) /**< Interrupt endpoint value. */
|
|
#define HCHCTL_LSD (1U<<17) /**< Low-Speed device. */
|
|
#define HCHCTL_EPDIR (1U<<15) /**< Endpoint direction. */
|
|
#define HCHCTL_EPNUM_MASK (15U<<11) /**< Endpoint number mask. */
|
|
#define HCHCTL_EPNUM(n) ((n)<<11) /**< Endpoint number value. */
|
|
#define HCHCTL_MPL_MASK (0x7FFU<<0) /**< Maximum packet size mask. */
|
|
#define HCHCTL_MPL(n) ((n)<<0) /**< Maximum packet size value. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name HCHINTF register bit definitions
|
|
* @{
|
|
*/
|
|
#define HCHINTF_DTER (1U<<10) /**< Data toggle error. */
|
|
#define HCHINTF_REQOVR (1U<<9) /**< Frame overrun. */
|
|
#define HCHINTF_BBER (1U<<8) /**< Babble error. */
|
|
#define HCHINTF_USBER (1U<<7) /**< Transaction Error. */
|
|
#define HCHINTF_ACK (1U<<5) /**< ACK response
|
|
received/transmitted
|
|
interrupt. */
|
|
#define HCHINTF_NAK (1U<<4) /**< NAK response received
|
|
interrupt. */
|
|
#define HCHINTF_STALL (1U<<3) /**< STALL response received
|
|
interrupt. */
|
|
#define HCHINTF_CH (1U<<1) /**< Channel halted. */
|
|
#define HCHINTF_TF (1U<<0) /**< Transfer completed. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name HCHINTEN register bit definitions
|
|
* @{
|
|
*/
|
|
#define HCHINTEN_DTERIE (1U<<10) /**< Data toggle error mask. */
|
|
#define HCHINTEN_REQOVRIE (1U<<9) /**< Frame overrun mask. */
|
|
#define HCHINTEN_BBERIE (1U<<8) /**< Babble error mask. */
|
|
#define HCHINTEN_USBERIE (1U<<7) /**< Transaction error mask. */
|
|
#define HCHINTEN_ACKIE (1U<<5) /**< ACK Response
|
|
received/transmitted
|
|
interrupt mask. */
|
|
#define HCHINTEN_NAKIE (1U<<4) /**< NAK response received
|
|
interrupt mask. */
|
|
#define HCHINTEN_STALLIE (1U<<3) /**< STALL response received
|
|
interrupt mask. */
|
|
#define HCHINTEN_CHIE (1U<<1) /**< Channel halted mask. */
|
|
#define HCHINTEN_TFIE (1U<<0) /**< Transfer completed mask. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name HCHLEN register bit definitions
|
|
* @{
|
|
*/
|
|
#define HCHLEN_DPID_MASK (3U<<29) /**< PID mask. */
|
|
#define HCHLEN_DPID_DATA0 (0U<<29) /**< DATA0. */
|
|
#define HCHLEN_DPID_DATA2 (1U<<29) /**< DATA2. */
|
|
#define HCHLEN_DPID_DATA1 (2U<<29) /**< DATA1. */
|
|
#define HCHLEN_DPID_MDATA (3U<<29) /**< MDATA. */
|
|
#define HCHLEN_DPID_SETUP (3U<<29) /**< SETUP. */
|
|
#define HCHLEN_PCNT_MASK (0x3FFU<<19)/**< Packet count mask. */
|
|
#define HCHLEN_PCNT(n) ((n)<<19) /**< Packet count value. */
|
|
#define HCHLEN_TLEN_MASK (0x7FFFF<<0)/**< Transfer size mask. */
|
|
#define HCHLEN_TLEN(n) ((n)<<0) /**< Transfer size value. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name DCFG register bit definitions
|
|
* @{
|
|
*/
|
|
#define DCFG_EOPFT_MASK (3U<<11) /**< Periodic frame interval
|
|
mask. */
|
|
#define DCFG_EOPFT(n) ((n)<<11) /**< Periodic frame interval
|
|
value. */
|
|
#define DCFG_DAR_MASK (0x7FU<<4) /**< Device address mask. */
|
|
#define DCFG_DAR(n) ((n)<<4) /**< Device address value. */
|
|
#define DCFG_NZLSOH (1U<<2) /**< Non-Zero-Length status
|
|
OUT handshake. */
|
|
#define DCFG_DS_MASK (3U<<0) /**< Device speed mask. */
|
|
#define DCFG_DS_FS11 (3U<<0) /**< Full speed (USB 1.1
|
|
transceiver clock is 48
|
|
MHz). */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name DCTL register bit definitions
|
|
* @{
|
|
*/
|
|
#define DCTL_POIF (1U<<11) /**< Power-on programming done. */
|
|
#define DCTL_CGONAK (1U<<10) /**< Clear global OUT NAK. */
|
|
#define DCTL_SGONAK (1U<<9) /**< Set global OUT NAK. */
|
|
#define DCTL_CGINAK (1U<<8) /**< Clear global non-periodic
|
|
IN NAK. */
|
|
#define DCTL_SGINAK (1U<<7) /**< Set global non-periodic
|
|
IN NAK. */
|
|
#define DCTL_GONS (1U<<3) /**< Global OUT NAK status. */
|
|
#define DCTL_GINS (1U<<2) /**< Global non-periodic IN
|
|
NAK status. */
|
|
#define DCTL_SD (1U<<1) /**< Soft disconnect. */
|
|
#define DCTL_RWKUP (1U<<0) /**< Remote wakeup signaling. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name DSTAT register bit definitions
|
|
* @{
|
|
*/
|
|
#define DSTAT_FNRSOF_MASK (0x3FFU<<8) /**< Frame number of the received
|
|
SOF mask. */
|
|
#define DSTAT_FNRSOF(n) ((n)<<8) /**< Frame number of the received
|
|
SOF value. */
|
|
#define DSTAT_FNRSOF_ODD (1U<<8) /**< Frame parity of the received
|
|
SOF value. */
|
|
#define DSTAT_ES_MASK (3U<<1) /**< Enumerated speed mask. */
|
|
#define DSTAT_ES_FS_48 (3U<<1) /**< Full speed (PHY clock is
|
|
running at 48 MHz). */
|
|
#define DSTAT_SPST (1U<<0) /**< Suspend status. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name DIEPINTF register bit definitions
|
|
* @{
|
|
*/
|
|
#define DIEPINTF_IEPNEEN (1U<<6) /**< Transmit FIFO empty mask. */
|
|
#define DIEPINTF_EPTXFUDEN (1U<<4) /**< IN token received when
|
|
TxFIFO empty mask. */
|
|
#define DIEPINTF_CITOEN (1U<<3) /**< Timeout condition mask. */
|
|
#define DIEPINTF_EPDISEN (1U<<1) /**< Endpoint disabled
|
|
interrupt mask. */
|
|
#define DIEPINTF_TFEN (1U<<0) /**< Transfer completed
|
|
interrupt mask. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name DOEPINTF register bit definitions
|
|
* @{
|
|
*/
|
|
#define DOEPINTF_BTBSTPEN (1U<<6) /**< Back-to-back Setup packets
|
|
interrupt enable bit */
|
|
#define DOEPINTF_EPRXFOVREN (1U<<4) /**< OUT token received when
|
|
endpoint disabled mask. */
|
|
#define DOEPINTF_STPFEN (1U<<3) /**< SETUP phase done mask. */
|
|
#define DOEPINTF_EPDISEN (1U<<1) /**< Endpoint disabled
|
|
interrupt mask. */
|
|
#define DOEPINTF_TFEN (1U<<0) /**< Transfer completed
|
|
interrupt mask. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name DAEPINT register bit definitions
|
|
* @{
|
|
*/
|
|
#define DAEPINT_OEPITB_MASK (0xFFFFU<<16)/**< OUT endpoint interrupt
|
|
bits mask. */
|
|
#define DAEPINT_OEPITB(n) ((n)<<16) /**< OUT endpoint interrupt
|
|
bits value. */
|
|
#define DAEPINT_IEPITB_MASK (0xFFFFU<<0)/**< IN endpoint interrupt
|
|
bits mask. */
|
|
#define DAEPINT_IEPITB(n) ((n)<<0) /**< IN endpoint interrupt
|
|
bits value. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name DAEPINTEN register bit definitions
|
|
* @{
|
|
*/
|
|
#define DAEPINTEN_OEPIE_MASK (0xFFFFU<<16)/**< OUT EP interrupt mask
|
|
bits mask. */
|
|
#define DAEPINTEN_OEPIE(n) (1U<<(16+(n)))/**< OUT EP interrupt mask
|
|
bits value. */
|
|
#define DAEPINTEN_IEPIE_MASK (0xFFFFU<<0)/**< IN EP interrupt mask
|
|
bits mask. */
|
|
#define DAEPINTEN_IEPIE(n) (1U<<(n)) /**< IN EP interrupt mask
|
|
bits value. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name DVBUSDT register bit definitions
|
|
* @{
|
|
*/
|
|
#define DVBUSDT_DVBUSDT_MASK (0xFFFFU<<0)/**< Device VBUS discharge
|
|
time mask. */
|
|
#define DVBUSDT_DVBUSDT(n) ((n)<<0) /**< Device VBUS discharge
|
|
time value. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name DVBUSPT register bit definitions
|
|
* @{
|
|
*/
|
|
#define DVBUSPT_DVBUSPT_MASK (0xFFFU<<0) /**< Device VBUSpulsing time
|
|
mask. */
|
|
#define DVBUSPT_DVBUSPT(n) ((n)<<0) /**< Device VBUS pulsing time
|
|
value. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name DIEPFEINTEN register bit definitions
|
|
* @{
|
|
*/
|
|
#define DIEPFEINTEN_IEPTXFEIE(n) (1U<<(n)) /**< IN EP Tx FIFO empty
|
|
interrupt mask bit. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name DIEPCTL register bit definitions
|
|
* @{
|
|
*/
|
|
#define DIEPCTL_EPEN (1U<<31) /**< Endpoint enable. */
|
|
#define DIEPCTL_EPD (1U<<30) /**< Endpoint disable. */
|
|
#define DIEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */
|
|
#define DIEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */
|
|
#define DIEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */
|
|
#define DIEPCTL_SEVENFRM (1U<<28) /**< Set even frame. */
|
|
#define DIEPCTL_SNAK (1U<<27) /**< Set NAK. */
|
|
#define DIEPCTL_CNAK (1U<<26) /**< Clear NAK. */
|
|
#define DIEPCTL_TXFNUM_MASK (15U<<22) /**< TxFIFO number mask. */
|
|
#define DIEPCTL_TXFNUM(n) ((n)<<22) /**< TxFIFO number value. */
|
|
#define DIEPCTL_STALL (1U<<21) /**< STALL handshake. */
|
|
#define DIEPCTL_SNPM (1U<<20) /**< Snoop mode. */
|
|
#define DIEPCTL_EPTYPE_MASK (3<<18) /**< Endpoint type mask. */
|
|
#define DIEPCTL_EPTYPE_CTRL (0U<<18) /**< Control. */
|
|
#define DIEPCTL_EPTYPE_ISO (1U<<18) /**< Isochronous. */
|
|
#define DIEPCTL_EPTYPE_BULK (2U<<18) /**< Bulk. */
|
|
#define DIEPCTL_EPTYPE_INTR (3U<<18) /**< Interrupt. */
|
|
#define DIEPCTL_NAKS (1U<<17) /**< NAK status. */
|
|
#define DIEPCTL_EONUM (1U<<16) /**< Even/odd frame. */
|
|
#define DIEPCTL_DPID (1U<<16) /**< Endpoint data PID. */
|
|
#define DIEPCTL_EPACT (1U<<15) /**< USB active endpoint. */
|
|
#define DIEPCTL_MPL_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */
|
|
#define DIEPCTL_MPL(n) ((n)<<0) /**< Maximum Packet size value. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name DIEPINTF register bit definitions
|
|
* @{
|
|
*/
|
|
#define DIEPINTFF_TXFE (1U<<7) /**< Transmit FIFO empty. */
|
|
#define DIEPINTFF_IEPNE (1U<<6) /**< IN endpoint NAK effective. */
|
|
#define DIEPINTFF_EPTXFUD (1U<<4) /**< IN Token received when
|
|
TxFIFO is empty. */
|
|
#define DIEPINTFF_CITO (1U<<3) /**< Timeout condition. */
|
|
#define DIEPINTFF_EPDIS (1U<<1) /**< Endpoint disabled
|
|
interrupt. */
|
|
#define DIEPINTFF_TF (1U<<0) /**< Transfer completed. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name DIEPLEN register bit definitions
|
|
* @{
|
|
*/
|
|
#define DIEPLEN_MCPF_MASK (3U<<29) /**< Multi count mask. */
|
|
#define DIEPLEN_MCPF(n) ((n)<<29) /**< Multi count value. */
|
|
#define DIEPLEN_PCNT_MASK (0x3FF<<19) /**< Packet count mask. */
|
|
#define DIEPLEN_PCNT(n) ((n)<<19) /**< Packet count value. */
|
|
#define DIEPLEN_TLEN_MASK (0x7FFFFU<<0)/**< Transfer size mask. */
|
|
#define DIEPLEN_TLEN(n) ((n)<<0) /**< Transfer size value. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name DIEPTFSTAT register bit definitions.
|
|
* @{
|
|
*/
|
|
#define DIEPTFSTAT_IEPTFS_MASK (0xFFFF<<0) /**< IN endpoint TxFIFO space
|
|
available. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name DOEPCTL register bit definitions.
|
|
* @{
|
|
*/
|
|
#define DOEPCTL_EPEN (1U<<31) /**< Endpoint enable. */
|
|
#define DOEPCTL_EPD (1U<<30) /**< Endpoint disable. */
|
|
#define DOEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */
|
|
#define DOEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */
|
|
#define DOEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */
|
|
#define DOEPCTL_SEVENFRM (1U<<28) /**< Set even frame. */
|
|
#define DOEPCTL_SNAK (1U<<27) /**< Set NAK. */
|
|
#define DOEPCTL_CNAK (1U<<26) /**< Clear NAK. */
|
|
#define DOEPCTL_STALL (1U<<21) /**< STALL handshake. */
|
|
#define DOEPCTL_SNOOP (1U<<20) /**< Snoop mode. */
|
|
#define DOEPCTL_EPTYPE_MASK (3U<<18) /**< Endpoint type mask. */
|
|
#define DOEPCTL_EPTYPE_CTRL (0U<<18) /**< Control. */
|
|
#define DOEPCTL_EPTYPE_ISO (1U<<18) /**< Isochronous. */
|
|
#define DOEPCTL_EPTYPE_BULK (2U<<18) /**< Bulk. */
|
|
#define DOEPCTL_EPTYPE_INTR (3U<<18) /**< Interrupt. */
|
|
#define DOEPCTL_NAKS (1U<<17) /**< NAK status. */
|
|
#define DOEPCTL_EOFRM (1U<<16) /**< Even/odd frame. */
|
|
#define DOEPCTL_DPID (1U<<16) /**< Endpoint data PID. */
|
|
#define DOEPCTL_EPACT (1U<<15) /**< USB active endpoint. */
|
|
#define DOEPCTL_MPL_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */
|
|
#define DOEPCTL_MPL(n) ((n)<<0) /**< Maximum Packet size value. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name DOEPINTF register bit definitions
|
|
* @{
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|
*/
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|
#define DOEPINTF_BTBSTP (1U<<6) /**< Back-to-back SETUP packets
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|
received. */
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|
#define DOEPINTF_EPRXFOVR (1U<<4) /**< OUT token received when
|
|
endpoint disabled. */
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|
#define DOEPINTF_STPF (1U<<3) /**< SETUP phase done. */
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|
#define DOEPINTF_EPDIS (1U<<1) /**< Endpoint disabled
|
|
interrupt. */
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|
#define DOEPINTF_TF (1U<<0) /**< Transfer completed
|
|
interrupt. */
|
|
/** @} */
|
|
|
|
/**
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|
* @name DOEPLEN register bit definitions
|
|
* @{
|
|
*/
|
|
#define DOEPLEN_RXDPID_MASK (3U<<29) /**< Received data PID mask. */
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|
#define DOEPLEN_RXDPID(n) ((n)<<29) /**< Received data PID value. */
|
|
#define DOEPLEN_STPCNT_MASK (3U<<29) /**< SETUP packet count mask. */
|
|
#define DOEPLEN_STPCNT(n) ((n)<<29) /**< SETUP packet count value. */
|
|
#define DOEPLEN_PCNT_MASK (0x3FFU<<19)/**< Packet count mask. */
|
|
#define DOEPLEN_PCNT(n) ((n)<<19) /**< Packet count value. */
|
|
#define DOEPLEN_TLEN_MASK (0x7FFFFU<<0)/**< Transfer size mask. */
|
|
#define DOEPLEN_TLEN(n) ((n)<<0) /**< Transfer size value. */
|
|
/** @} */
|
|
|
|
/**
|
|
* @name PWRCLKCTL register bit definitions
|
|
* @{
|
|
*/
|
|
#define PWRCLKCTL_SHCLK (1U<<1) /**< Gate HCLK. */
|
|
#define PWRCLKCTL_SUCLK (1U<<0) /**< Stop PCLK. */
|
|
/** @} */
|
|
|
|
#define USBFS_ADDR 0x50000000
|
|
|
|
/**
|
|
* @brief Accesses to the USBFS registers block.
|
|
*/
|
|
#define USBFS ((gd32_usbfs_t *)USBFS_ADDR)
|
|
|
|
#endif /* GD32_USBFS_H */
|
|
|
|
/** @} */
|