530 lines
18 KiB
C
530 lines
18 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2021 Stefan Kerkmann
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file SPI/hal_spi_lld.c
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* @brief GD32 SPI subsystem low level driver source.
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*
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* @addtogroup SPI
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_SPI || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#define SPI0_RX_DMA_CHANNEL \
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GD32_DMA_GETCHANNEL(GD32_SPI_SPI0_RX_DMA_STREAM, \
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GD32_SPI0_RX_DMA_CHN)
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#define SPI0_TX_DMA_CHANNEL \
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GD32_DMA_GETCHANNEL(GD32_SPI_SPI0_TX_DMA_STREAM, \
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GD32_SPI0_TX_DMA_CHN)
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#define SPI1_RX_DMA_CHANNEL \
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GD32_DMA_GETCHANNEL(GD32_SPI_SPI1_RX_DMA_STREAM, \
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GD32_SPI1_RX_DMA_CHN)
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#define SPI1_TX_DMA_CHANNEL \
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GD32_DMA_GETCHANNEL(GD32_SPI_SPI1_TX_DMA_STREAM, \
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GD32_SPI1_TX_DMA_CHN)
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#define SPI2_RX_DMA_CHANNEL \
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GD32_DMA_GETCHANNEL(GD32_SPI_SPI2_RX_DMA_STREAM, \
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GD32_SPI2_RX_DMA_CHN)
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#define SPI2_TX_DMA_CHANNEL \
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GD32_DMA_GETCHANNEL(GD32_SPI_SPI2_TX_DMA_STREAM, \
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GD32_SPI2_TX_DMA_CHN)
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief SPI0 driver identifier.*/
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#if GD32_SPI_USE_SPI0 || defined(__DOXYGEN__)
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SPIDriver SPID1;
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#endif
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/** @brief SPI1 driver identifier.*/
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#if GD32_SPI_USE_SPI1 || defined(__DOXYGEN__)
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SPIDriver SPID2;
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#endif
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/** @brief SPI2 driver identifier.*/
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#if GD32_SPI_USE_SPI2 || defined(__DOXYGEN__)
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SPIDriver SPID3;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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static const uint16_t dummytx = 0xFFFFU;
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static uint16_t dummyrx;
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Shared end-of-rx service routine.
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*
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* @param[in] spip pointer to the @p SPIDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) {
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/* DMA errors handling.*/
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#if defined(GD32_SPI_DMA_ERROR_HOOK)
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if ((flags & (GD32_DMA_INTF_ERRIF)) != 0) {
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GD32_SPI_DMA_ERROR_HOOK(spip);
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}
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#else
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(void)flags;
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#endif
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if (spip->config->circular) {
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if ((flags & GD32_DMA_INTF_HTFIF) != 0U) {
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/* Half buffer interrupt.*/
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_spi_isr_half_code(spip);
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}
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if ((flags & GD32_DMA_INTF_FTFIF) != 0U) {
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/* End buffer interrupt.*/
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_spi_isr_full_code(spip);
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}
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}
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else {
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/* Stopping DMAs.*/
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dmaStreamDisable(spip->dmatx);
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dmaStreamDisable(spip->dmarx);
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/* Portable SPI ISR code defined in the high level driver, note, it is
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a macro.*/
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_spi_isr_code(spip);
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}
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}
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/**
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* @brief Shared end-of-tx service routine.
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*
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* @param[in] spip pointer to the @p SPIDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) {
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/* DMA errors handling.*/
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#if defined(GD32_SPI_DMA_ERROR_HOOK)
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(void)spip;
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if ((flags & (GD32_DMA_INTF_ERRIF)) != 0) {
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GD32_SPI_DMA_ERROR_HOOK(spip);
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}
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#else
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(void)spip;
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(void)flags;
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#endif
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level SPI driver initialization.
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*
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* @notapi
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*/
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void spi_lld_init(void) {
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#if GD32_SPI_USE_SPI0
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spiObjectInit(&SPID1);
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SPID1.spi = SPI0;
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SPID1.dmarx = NULL;
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SPID1.dmatx = NULL;
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SPID1.rxdmamode = GD32_DMA_CTL_CHSEL(SPI0_RX_DMA_CHANNEL) |
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GD32_DMA_CTL_PRIO(GD32_SPI_SPI0_DMA_PRIORITY) |
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GD32_DMA_CTL_DIR_P2M |
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GD32_DMA_CTL_FTFIE |
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GD32_DMA_CTL_ERRIE;
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SPID1.txdmamode = GD32_DMA_CTL_CHSEL(SPI0_TX_DMA_CHANNEL) |
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GD32_DMA_CTL_PRIO(GD32_SPI_SPI0_DMA_PRIORITY) |
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GD32_DMA_CTL_DIR_M2P |
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GD32_DMA_CTL_ERRIE;
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#endif
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#if GD32_SPI_USE_SPI1
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spiObjectInit(&SPID2);
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SPID2.spi = SPI1;
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SPID2.dmarx = NULL;
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SPID2.dmatx = NULL;
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SPID2.rxdmamode = GD32_DMA_CTL_CHSEL(SPI1_RX_DMA_CHANNEL) |
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GD32_DMA_CTL_PRIO(GD32_SPI_SPI1_DMA_PRIORITY) |
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GD32_DMA_CTL_DIR_P2M |
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GD32_DMA_CTL_FTFIE |
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GD32_DMA_CTL_ERRIE;
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SPID2.txdmamode = GD32_DMA_CTL_CHSEL(SPI1_TX_DMA_CHANNEL) |
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GD32_DMA_CTL_PRIO(GD32_SPI_SPI1_DMA_PRIORITY) |
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GD32_DMA_CTL_DIR_M2P |
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GD32_DMA_CTL_ERRIE;
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#endif
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#if GD32_SPI_USE_SPI2
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spiObjectInit(&SPID3);
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SPID3.spi = SPI2;
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SPID3.dmarx = NULL;
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SPID3.dmatx = NULL;
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SPID3.rxdmamode = GD32_DMA_CTL_CHSEL(SPI2_RX_DMA_CHANNEL) |
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GD32_DMA_CTL_PRIO(GD32_SPI_SPI2_DMA_PRIORITY) |
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GD32_DMA_CTL_DIR_P2M |
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GD32_DMA_CTL_FTFIE |
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GD32_DMA_CTL_ERRIE;
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SPID3.txdmamode = GD32_DMA_CTL_CHSEL(SPI2_TX_DMA_CHANNEL) |
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GD32_DMA_CTL_PRIO(GD32_SPI_SPI2_DMA_PRIORITY) |
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GD32_DMA_CTL_DIR_M2P |
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GD32_DMA_CTL_ERRIE;
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#endif
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}
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/**
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* @brief Configures and activates the SPI peripheral.
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*
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* @param[in] spip pointer to the @p SPIDriver object
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*
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* @notapi
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*/
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void spi_lld_start(SPIDriver *spip) {
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/* If in stopped state then enables the SPI and DMA clocks.*/
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if (spip->state == SPI_STOP) {
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#if GD32_SPI_USE_SPI0
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if (&SPID1 == spip) {
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spip->dmarx = dmaStreamAllocI(GD32_SPI_SPI0_RX_DMA_STREAM,
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GD32_SPI_SPI0_IRQ_PRIORITY,
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(gd32_dmaisr_t)spi_lld_serve_rx_interrupt,
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(void *)spip);
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osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
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spip->dmatx = dmaStreamAllocI(GD32_SPI_SPI0_TX_DMA_STREAM,
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GD32_SPI_SPI0_IRQ_PRIORITY,
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(gd32_dmaisr_t)spi_lld_serve_tx_interrupt,
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(void *)spip);
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osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
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rcuEnableSPI0(true);
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}
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#endif
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#if GD32_SPI_USE_SPI1
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if (&SPID2 == spip) {
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spip->dmarx = dmaStreamAllocI(GD32_SPI_SPI1_RX_DMA_STREAM,
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GD32_SPI_SPI1_IRQ_PRIORITY,
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(gd32_dmaisr_t)spi_lld_serve_rx_interrupt,
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(void *)spip);
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osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
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spip->dmatx = dmaStreamAllocI(GD32_SPI_SPI1_TX_DMA_STREAM,
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GD32_SPI_SPI1_IRQ_PRIORITY,
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(gd32_dmaisr_t)spi_lld_serve_tx_interrupt,
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(void *)spip);
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osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
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rcuEnableSPI1(true);
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}
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#endif
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#if GD32_SPI_USE_SPI2
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if (&SPID3 == spip) {
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spip->dmarx = dmaStreamAllocI(GD32_SPI_SPI2_RX_DMA_STREAM,
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GD32_SPI_SPI2_IRQ_PRIORITY,
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(gd32_dmaisr_t)spi_lld_serve_rx_interrupt,
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(void *)spip);
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osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
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spip->dmatx = dmaStreamAllocI(GD32_SPI_SPI2_TX_DMA_STREAM,
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GD32_SPI_SPI2_IRQ_PRIORITY,
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(gd32_dmaisr_t)spi_lld_serve_tx_interrupt,
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(void *)spip);
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osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
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rcuEnableSPI2(true);
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}
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#endif
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/* DMA setup.*/
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dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DATA);
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dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DATA);
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}
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/* Configuration-specific DMA setup.*/
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if ((spip->config->ctl0 & SPI_CTL0_FF16) == 0) {
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/* Frame width is 8 bits or smaller.*/
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spip->rxdmamode = (spip->rxdmamode & ~GD32_DMA_CTL_SIZE_MASK) |
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GD32_DMA_CTL_PWIDTH_BYTE | GD32_DMA_CTL_MWIDTH_BYTE;
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spip->txdmamode = (spip->txdmamode & ~GD32_DMA_CTL_SIZE_MASK) |
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GD32_DMA_CTL_PWIDTH_BYTE | GD32_DMA_CTL_MWIDTH_BYTE;
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}
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else {
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/* Frame width is larger than 8 bits.*/
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spip->rxdmamode = (spip->rxdmamode & ~GD32_DMA_CTL_SIZE_MASK) |
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GD32_DMA_CTL_PWIDTH_HWORD | GD32_DMA_CTL_MWIDTH_HWORD;
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spip->txdmamode = (spip->txdmamode & ~GD32_DMA_CTL_SIZE_MASK) |
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GD32_DMA_CTL_PWIDTH_HWORD | GD32_DMA_CTL_MWIDTH_HWORD;
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}
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if (spip->config->circular) {
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spip->rxdmamode |= (GD32_DMA_CTL_CMEN | GD32_DMA_CTL_HTFIE);
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spip->txdmamode |= (GD32_DMA_CTL_CMEN | GD32_DMA_CTL_HTFIE);
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}
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else {
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spip->rxdmamode &= ~(GD32_DMA_CTL_CMEN | GD32_DMA_CTL_HTFIE);
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spip->txdmamode &= ~(GD32_DMA_CTL_CMEN | GD32_DMA_CTL_HTFIE);
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}
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/* SPI setup and enable.*/
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spip->spi->CTL0 &= ~SPI_CTL0_SPIEN;
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spip->spi->CTL0 = spip->config->ctl0 | SPI_CTL0_MSTMOD | SPI_CTL0_SWNSSEN |
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SPI_CTL0_SWNSS;
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spip->spi->CTL1 = spip->config->ctl1 | SPI_CTL1_NSSDRV | SPI_CTL1_DMAREN |
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SPI_CTL1_DMATEN;
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spip->spi->CTL0 |= SPI_CTL0_SPIEN;
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}
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/**
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* @brief Deactivates the SPI peripheral.
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*
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* @param[in] spip pointer to the @p SPIDriver object
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*
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* @notapi
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*/
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void spi_lld_stop(SPIDriver *spip) {
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/* If in ready state then disables the SPI clock.*/
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if (spip->state == SPI_READY) {
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/* SPI disable.*/
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spip->spi->CTL0 &= ~SPI_CTL0_SPIEN;
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spip->spi->CTL0 = 0;
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spip->spi->CTL1 = 0;
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dmaStreamFreeI(spip->dmarx);
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dmaStreamFreeI(spip->dmatx);
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spip->dmarx = NULL;
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spip->dmatx = NULL;
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#if GD32_SPI_USE_SPI0
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if (&SPID1 == spip)
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rcuDisableSPI0();
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#endif
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#if GD32_SPI_USE_SPI1
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if (&SPID2 == spip)
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rcuDisableSPI1();
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#endif
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#if GD32_SPI_USE_SPI2
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if (&SPID3 == spip)
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rcuDisableSPI2();
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#endif
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}
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}
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#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LLD) || defined(__DOXYGEN__)
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/**
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* @brief Asserts the slave select signal and prepares for transfers.
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*
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* @param[in] spip pointer to the @p SPIDriver object
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*
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* @notapi
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*/
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void spi_lld_select(SPIDriver *spip) {
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/* No implementation on GD32.*/
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}
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/**
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* @brief Deasserts the slave select signal.
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* @details The previously selected peripheral is unselected.
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*
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* @param[in] spip pointer to the @p SPIDriver object
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*
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* @notapi
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*/
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void spi_lld_unselect(SPIDriver *spip) {
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/* No implementation on GD32.*/
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}
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#endif
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/**
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* @brief Ignores data on the SPI bus.
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* @details This asynchronous function starts the transmission of a series of
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* idle words on the SPI bus and ignores the received data.
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* @post At the end of the operation the configured callback is invoked.
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*
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* @param[in] spip pointer to the @p SPIDriver object
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* @param[in] n number of words to be ignored
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*
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* @notapi
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*/
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void spi_lld_ignore(SPIDriver *spip, size_t n) {
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osalDbgAssert(n < 65536, "unsupported DMA transfer size");
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dmaStreamSetMemory0(spip->dmarx, &dummyrx);
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dmaStreamSetTransactionSize(spip->dmarx, n);
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dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
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dmaStreamSetMemory0(spip->dmatx, &dummytx);
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dmaStreamSetTransactionSize(spip->dmatx, n);
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dmaStreamSetMode(spip->dmatx, spip->txdmamode);
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dmaStreamEnable(spip->dmarx);
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dmaStreamEnable(spip->dmatx);
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}
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/**
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* @brief Exchanges data on the SPI bus.
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* @details This asynchronous function starts a simultaneous transmit/receive
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* operation.
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* @post At the end of the operation the configured callback is invoked.
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* @note The buffers are organized as uint8_t arrays for data sizes below or
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* equal to 8 bits else it is organized as uint16_t arrays.
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*
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* @param[in] spip pointer to the @p SPIDriver object
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* @param[in] n number of words to be exchanged
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* @param[in] txbuf the pointer to the transmit buffer
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* @param[out] rxbuf the pointer to the receive buffer
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*
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* @notapi
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*/
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void spi_lld_exchange(SPIDriver *spip, size_t n,
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const void *txbuf, void *rxbuf) {
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osalDbgAssert(n < 65536, "unsupported DMA transfer size");
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dmaStreamSetMemory0(spip->dmarx, rxbuf);
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dmaStreamSetTransactionSize(spip->dmarx, n);
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dmaStreamSetMode(spip->dmarx, spip->rxdmamode| GD32_DMA_CTL_MNAGA);
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dmaStreamSetMemory0(spip->dmatx, txbuf);
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dmaStreamSetTransactionSize(spip->dmatx, n);
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dmaStreamSetMode(spip->dmatx, spip->txdmamode | GD32_DMA_CTL_MNAGA);
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dmaStreamEnable(spip->dmarx);
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dmaStreamEnable(spip->dmatx);
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}
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/**
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* @brief Sends data over the SPI bus.
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* @details This asynchronous function starts a transmit operation.
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* @post At the end of the operation the configured callback is invoked.
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* @note The buffers are organized as uint8_t arrays for data sizes below or
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* equal to 8 bits else it is organized as uint16_t arrays.
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*
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* @param[in] spip pointer to the @p SPIDriver object
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* @param[in] n number of words to send
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* @param[in] txbuf the pointer to the transmit buffer
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*
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* @notapi
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*/
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void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
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osalDbgAssert(n < 65536, "unsupported DMA transfer size");
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dmaStreamSetMemory0(spip->dmarx, &dummyrx);
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dmaStreamSetTransactionSize(spip->dmarx, n);
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dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
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dmaStreamSetMemory0(spip->dmatx, txbuf);
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dmaStreamSetTransactionSize(spip->dmatx, n);
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dmaStreamSetMode(spip->dmatx, spip->txdmamode | GD32_DMA_CTL_MNAGA);
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dmaStreamEnable(spip->dmarx);
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dmaStreamEnable(spip->dmatx);
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}
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/**
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* @brief Receives data from the SPI bus.
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* @details This asynchronous function starts a receive operation.
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* @post At the end of the operation the configured callback is invoked.
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* @note The buffers are organized as uint8_t arrays for data sizes below or
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* equal to 8 bits else it is organized as uint16_t arrays.
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*
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* @param[in] spip pointer to the @p SPIDriver object
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|
* @param[in] n number of words to receive
|
|
* @param[out] rxbuf the pointer to the receive buffer
|
|
*
|
|
* @notapi
|
|
*/
|
|
void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
|
|
|
|
osalDbgAssert(n < 65536, "unsupported DMA transfer size");
|
|
|
|
dmaStreamSetMemory0(spip->dmarx, rxbuf);
|
|
dmaStreamSetTransactionSize(spip->dmarx, n);
|
|
dmaStreamSetMode(spip->dmarx, spip->rxdmamode | GD32_DMA_CTL_MNAGA);
|
|
|
|
dmaStreamSetMemory0(spip->dmatx, &dummytx);
|
|
dmaStreamSetTransactionSize(spip->dmatx, n);
|
|
dmaStreamSetMode(spip->dmatx, spip->txdmamode);
|
|
|
|
dmaStreamEnable(spip->dmarx);
|
|
dmaStreamEnable(spip->dmatx);
|
|
}
|
|
|
|
#if (SPI_SUPPORTS_CIRCULAR == TRUE) || defined(__DOXYGEN__)
|
|
/**
|
|
* @brief Aborts the ongoing SPI operation, if any.
|
|
*
|
|
* @param[in] spip pointer to the @p SPIDriver object
|
|
*
|
|
* @notapi
|
|
*/
|
|
void spi_lld_abort(SPIDriver *spip) {
|
|
|
|
/* Stopping DMAs.*/
|
|
dmaStreamDisable(spip->dmatx);
|
|
dmaStreamDisable(spip->dmarx);
|
|
}
|
|
#endif /* SPI_SUPPORTS_CIRCULAR == TRUE */
|
|
|
|
/**
|
|
* @brief Exchanges one frame using a polled wait.
|
|
* @details This synchronous function exchanges one frame using a polled
|
|
* synchronization method. This function is useful when exchanging
|
|
* small amount of data on high speed channels, usually in this
|
|
* situation is much more efficient just wait for completion using
|
|
* polling than suspending the thread waiting for an interrupt.
|
|
*
|
|
* @param[in] spip pointer to the @p SPIDriver object
|
|
* @param[in] frame the data frame to send over the SPI bus
|
|
* @return The received data frame from the SPI bus.
|
|
*/
|
|
uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
|
|
|
|
spip->spi->DATA = frame;
|
|
while ((spip->spi->STAT & SPI_STAT_RBNE) == 0)
|
|
;
|
|
return spip->spi->DATA;
|
|
}
|
|
|
|
#endif /* HAL_USE_SPI */
|
|
|
|
/** @} */
|