268 lines
9.0 KiB
C
268 lines
9.0 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2021 Stefan Kerkmann
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file SPI/hal_spi_lld.h
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* @brief GD32 SPI subsystem low level driver header.
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*
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* @addtogroup SPI
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* @{
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*/
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#ifndef HAL_SPI_LLD_H
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#define HAL_SPI_LLD_H
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#if HAL_USE_SPI || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Circular mode support flag.
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*/
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#define SPI_SUPPORTS_CIRCULAR TRUE
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief SPI0 driver enable switch.
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* @details If set to @p TRUE the support for SPI0 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(GD32_SPI_USE_SPI0) || defined(__DOXYGEN__)
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#define GD32_SPI_USE_SPI0 FALSE
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#endif
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/**
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* @brief SPI1 driver enable switch.
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* @details If set to @p TRUE the support for SPI1 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(GD32_SPI_USE_SPI1) || defined(__DOXYGEN__)
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#define GD32_SPI_USE_SPI1 FALSE
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#endif
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/**
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* @brief SPI2 driver enable switch.
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* @details If set to @p TRUE the support for SPI2 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(GD32_SPI_USE_SPI2) || defined(__DOXYGEN__)
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#define GD32_SPI_USE_SPI2 FALSE
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#endif
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/**
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* @brief SPI0 interrupt priority level setting.
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*/
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#if !defined(GD32_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_SPI_SPI0_IRQ_PRIORITY 10
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#endif
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/**
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* @brief SPI1 interrupt priority level setting.
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*/
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#if !defined(GD32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_SPI_SPI1_IRQ_PRIORITY 10
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#endif
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/**
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* @brief SPI2 interrupt priority level setting.
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*/
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#if !defined(GD32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_SPI_SPI2_IRQ_PRIORITY 10
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#endif
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/**
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* @brief SPI0 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA streams but
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* because of the streams ordering the RX stream has always priority
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* over the TX stream.
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*/
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#if !defined(GD32_SPI_SPI0_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_SPI_SPI0_DMA_PRIORITY 1
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#endif
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/**
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* @brief SPI1 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA streams but
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* because of the streams ordering the RX stream has always priority
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* over the TX stream.
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*/
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#if !defined(GD32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_SPI_SPI1_DMA_PRIORITY 1
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#endif
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/**
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* @brief SPI2 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA streams but
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* because of the streams ordering the RX stream has always priority
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* over the TX stream.
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*/
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#if !defined(GD32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_SPI_SPI2_DMA_PRIORITY 1
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#endif
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/**
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* @brief SPI DMA error hook.
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*/
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#if !defined(GD32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
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#define GD32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if GD32_SPI_USE_SPI0 && !GD32_HAS_SPI0
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#error "SPI0 not present in the selected device"
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#endif
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#if GD32_SPI_USE_SPI1 && !GD32_HAS_SPI1
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#error "SPI1 not present in the selected device"
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#endif
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#if GD32_SPI_USE_SPI2 && !GD32_HAS_SPI2
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#error "SPI2 not present in the selected device"
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#endif
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#if !GD32_SPI_USE_SPI0 && !GD32_SPI_USE_SPI1 && !GD32_SPI_USE_SPI2
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#error "SPI driver activated but no SPI peripheral assigned"
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#endif
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#if GD32_SPI_USE_SPI0 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SPI_SPI0_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to SPI0"
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#endif
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#if GD32_SPI_USE_SPI1 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SPI_SPI1_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to SPI1"
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#endif
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#if GD32_SPI_USE_SPI2 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SPI_SPI2_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to SPI2"
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#endif
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#if GD32_SPI_USE_SPI0 && \
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!GD32_DMA_IS_VALID_PRIORITY(GD32_SPI_SPI0_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to SPI0"
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#endif
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#if GD32_SPI_USE_SPI1 && \
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!GD32_DMA_IS_VALID_PRIORITY(GD32_SPI_SPI1_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to SPI1"
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#endif
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#if GD32_SPI_USE_SPI2 && \
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!GD32_DMA_IS_VALID_PRIORITY(GD32_SPI_SPI2_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to SPI2"
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#endif
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#if !defined(GD32_DMA_REQUIRED)
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#define GD32_DMA_REQUIRED
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#endif
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#if SPI_SELECT_MODE == SPI_SELECT_MODE_LLD
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#error "SPI_SELECT_MODE_LLD not supported by this driver"
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @brief Low level fields of the SPI driver structure.
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*/
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#define spi_lld_driver_fields \
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/* Pointer to the SPIx registers block.*/ \
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SPI_TypeDef *spi; \
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/* Receive DMA stream.*/ \
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const gd32_dma_stream_t *dmarx; \
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/* Transmit DMA stream.*/ \
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const gd32_dma_stream_t *dmatx; \
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/* RX DMA mode bit mask.*/ \
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uint32_t rxdmamode; \
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/* TX DMA mode bit mask.*/ \
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uint32_t txdmamode
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/**
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* @brief Low level fields of the SPI configuration structure.
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*/
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#define spi_lld_config_fields \
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/* SPI CR1 register initialization data.*/ \
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uint16_t ctl0; \
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/* SPI CR2 register initialization data.*/ \
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uint16_t ctl1
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if GD32_SPI_USE_SPI0 && !defined(__DOXYGEN__)
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extern SPIDriver SPID1;
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#endif
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#if GD32_SPI_USE_SPI1 && !defined(__DOXYGEN__)
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extern SPIDriver SPID2;
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#endif
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#if GD32_SPI_USE_SPI2 && !defined(__DOXYGEN__)
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extern SPIDriver SPID3;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void spi_lld_init(void);
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void spi_lld_start(SPIDriver *spip);
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void spi_lld_stop(SPIDriver *spip);
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#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LLD) || defined(__DOXYGEN__)
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void spi_lld_select(SPIDriver *spip);
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void spi_lld_unselect(SPIDriver *spip);
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#endif
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void spi_lld_ignore(SPIDriver *spip, size_t n);
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void spi_lld_exchange(SPIDriver *spip, size_t n,
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const void *txbuf, void *rxbuf);
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void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
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void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
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#if (SPI_SUPPORTS_CIRCULAR == TRUE) || defined(__DOXYGEN__)
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void spi_lld_abort(SPIDriver *spip);
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#endif
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uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
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#ifdef __cplusplus
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}
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#endif
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#endif /* HAL_USE_SPI */
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#endif /* HAL_SPI_LLD_H */
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/** @} */
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