699 lines
20 KiB
C
699 lines
20 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2021 Stefan Kerkmann
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file TIM/hal_pwm_lld.c
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* @brief GD32 PWM subsystem low level driver header.
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*
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* @addtogroup PWM
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_PWM || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/**
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* @brief PWMD1 driver identifier.
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* @note The driver PWMD1 allocates the complex timer TIM0 when enabled.
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*/
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#if GD32_PWM_USE_TIM0 || defined(__DOXYGEN__)
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PWMDriver PWMD1;
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#endif
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/**
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* @brief PWMD2 driver identifier.
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* @note The driver PWMD2 allocates the timer TIM1 when enabled.
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*/
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#if GD32_PWM_USE_TIM1 || defined(__DOXYGEN__)
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PWMDriver PWMD2;
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#endif
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/**
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* @brief PWMD3 driver identifier.
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* @note The driver PWMD3 allocates the timer TIM2 when enabled.
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*/
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#if GD32_PWM_USE_TIM2 || defined(__DOXYGEN__)
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PWMDriver PWMD3;
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#endif
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/**
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* @brief PWMD4 driver identifier.
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* @note The driver PWMD4 allocates the timer TIM3 when enabled.
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*/
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#if GD32_PWM_USE_TIM3 || defined(__DOXYGEN__)
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PWMDriver PWMD4;
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#endif
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/**
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* @brief PWMD5 driver identifier.
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* @note The driver PWMD5 allocates the timer TIM4 when enabled.
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*/
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#if GD32_PWM_USE_TIM4 || defined(__DOXYGEN__)
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PWMDriver PWMD5;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if GD32_PWM_USE_TIM0 || defined(__DOXYGEN__)
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#if !defined(GD32_TIM0_SUPPRESS_ISR)
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#if !defined(GD32_TIM0_UP_HANDLER)
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#error "GD32_TIM0_UP_HANDLER not defined"
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#endif
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/**
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* @brief TIM0 update interrupt handler.
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* @note It is assumed that this interrupt is only activated if the callback
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* pointer is not equal to @p NULL in order to not perform an extra
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* check in a potentially critical interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_TIM0_UP_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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pwm_lld_serve_interrupt(&PWMD1);
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OSAL_IRQ_EPILOGUE();
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}
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#if !defined(GD32_TIM0_CC_HANDLER)
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#error "GD32_TIM0_CC_HANDLER not defined"
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#endif
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/**
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* @brief TIM0 compare interrupt handler.
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* @note It is assumed that the various sources are only activated if the
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* associated callback pointer is not equal to @p NULL in order to not
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* perform an extra check in a potentially critical interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_TIM0_CC_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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pwm_lld_serve_interrupt(&PWMD1);
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* !defined(GD32_TIM0_SUPPRESS_ISR) */
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#endif /* GD32_PWM_USE_TIM0 */
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#if GD32_PWM_USE_TIM1 || defined(__DOXYGEN__)
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#if !defined(GD32_TIM1_SUPPRESS_ISR)
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#if !defined(GD32_TIM1_HANDLER)
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#error "GD32_TIM1_HANDLER not defined"
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#endif
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/**
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* @brief TIM1 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_TIM1_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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pwm_lld_serve_interrupt(&PWMD2);
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* !defined(GD32_TIM1_SUPPRESS_ISR) */
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#endif /* GD32_PWM_USE_TIM1 */
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#if GD32_PWM_USE_TIM2 || defined(__DOXYGEN__)
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#if !defined(GD32_TIM2_SUPPRESS_ISR)
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#if !defined(GD32_TIM2_HANDLER)
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#error "GD32_TIM2_HANDLER not defined"
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#endif
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/**
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* @brief TIM2 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_TIM2_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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pwm_lld_serve_interrupt(&PWMD3);
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* !defined(GD32_TIM2_SUPPRESS_ISR) */
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#endif /* GD32_PWM_USE_TIM2 */
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#if GD32_PWM_USE_TIM3 || defined(__DOXYGEN__)
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#if !defined(GD32_TIM3_SUPPRESS_ISR)
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#if !defined(GD32_TIM3_HANDLER)
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#error "GD32_TIM3_HANDLER not defined"
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#endif
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/**
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* @brief TIM3 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_TIM3_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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pwm_lld_serve_interrupt(&PWMD4);
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* !defined(GD32_TIM3_SUPPRESS_ISR) */
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#endif /* GD32_PWM_USE_TIM3 */
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#if GD32_PWM_USE_TIM4 || defined(__DOXYGEN__)
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#if !defined(GD32_TIM4_SUPPRESS_ISR)
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#if !defined(GD32_TIM4_HANDLER)
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#error "GD32_TIM4_HANDLER not defined"
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#endif
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/**
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* @brief TIM4 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(GD32_TIM4_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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pwm_lld_serve_interrupt(&PWMD5);
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* !defined(GD32_TIM4_SUPPRESS_ISR) */
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#endif /* GD32_PWM_USE_TIM4 */
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level PWM driver initialization.
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*
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* @notapi
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*/
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void pwm_lld_init(void) {
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#if GD32_PWM_USE_TIM0
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/* Driver initialization.*/
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pwmObjectInit(&PWMD1);
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PWMD1.channels = GD32_TIM0_CHANNELS;
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PWMD1.tim = GD32_TIM0;
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#endif
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#if GD32_PWM_USE_TIM1
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/* Driver initialization.*/
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pwmObjectInit(&PWMD2);
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PWMD2.channels = GD32_TIM1_CHANNELS;
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PWMD2.tim = GD32_TIM1;
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#endif
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#if GD32_PWM_USE_TIM2
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/* Driver initialization.*/
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pwmObjectInit(&PWMD3);
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PWMD3.channels = GD32_TIM2_CHANNELS;
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PWMD3.tim = GD32_TIM2;
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#endif
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#if GD32_PWM_USE_TIM3
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/* Driver initialization.*/
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pwmObjectInit(&PWMD4);
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PWMD4.channels = GD32_TIM3_CHANNELS;
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PWMD4.tim = GD32_TIM3;
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#endif
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#if GD32_PWM_USE_TIM4
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/* Driver initialization.*/
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pwmObjectInit(&PWMD5);
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PWMD5.channels = GD32_TIM4_CHANNELS;
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PWMD5.tim = GD32_TIM4;
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#endif
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}
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/**
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* @brief Configures and activates the PWM peripheral.
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* @note Starting a driver that is already in the @p PWM_READY state
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* disables all the active channels.
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*
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* @param[in] pwmp pointer to a @p PWMDriver object
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*
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* @notapi
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*/
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void pwm_lld_start(PWMDriver *pwmp) {
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uint32_t psc;
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uint32_t ccer;
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if (pwmp->state == PWM_STOP) {
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/* Clock activation and timer reset.*/
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#if GD32_PWM_USE_TIM0
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if (&PWMD1 == pwmp) {
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rcuEnableTIM0(true);
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rcuResetTIM0();
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#if !defined(GD32_TIM0_SUPPRESS_ISR)
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eclicEnableVector(GD32_TIM0_UP_NUMBER, GD32_PWM_TIM0_IRQ_PRIORITY, GD32_PWM_TIM0_IRQ_TRIGGER);
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eclicEnableVector(GD32_TIM0_CC_NUMBER, GD32_PWM_TIM0_IRQ_PRIORITY, GD32_PWM_TIM0_IRQ_TRIGGER);
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#endif
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#if defined(GD32_TIM0CLK)
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pwmp->clock = GD32_TIM0CLK;
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#else
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pwmp->clock = GD32_TIMCLK2;
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#endif
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}
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#endif
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#if GD32_PWM_USE_TIM1
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if (&PWMD2 == pwmp) {
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rcuEnableTIM1(true);
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rcuResetTIM1();
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#if !defined(GD32_TIM1_SUPPRESS_ISR)
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eclicEnableVector(GD32_TIM1_NUMBER, GD32_PWM_TIM1_IRQ_PRIORITY, GD32_PWM_TIM1_IRQ_TRIGGER);
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#endif
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#if defined(GD32_TIM1CLK)
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pwmp->clock = GD32_TIM1CLK;
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#else
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pwmp->clock = GD32_TIMCLK1;
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#endif
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}
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#endif
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#if GD32_PWM_USE_TIM2
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if (&PWMD3 == pwmp) {
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rcuEnableTIM2(true);
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rcuResetTIM2();
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#if !defined(GD32_TIM2_SUPPRESS_ISR)
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eclicEnableVector(GD32_TIM2_NUMBER, GD32_PWM_TIM2_IRQ_PRIORITY, GD32_PWM_TIM2_IRQ_TRIGGER);
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#endif
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#if defined(GD32_TIM2CLK)
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pwmp->clock = GD32_TIM2CLK;
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#else
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pwmp->clock = GD32_TIMCLK1;
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#endif
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}
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#endif
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#if GD32_PWM_USE_TIM3
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if (&PWMD4 == pwmp) {
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rcuEnableTIM3(true);
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rcuResetTIM3();
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#if !defined(GD32_TIM3_SUPPRESS_ISR)
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eclicEnableVector(GD32_TIM3_NUMBER, GD32_PWM_TIM3_IRQ_PRIORITY, GD32_PWM_TIM3_IRQ_TRIGGER);
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#endif
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#if defined(GD32_TIM3CLK)
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pwmp->clock = GD32_TIM3CLK;
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#else
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pwmp->clock = GD32_TIMCLK1;
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#endif
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}
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#endif
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#if GD32_PWM_USE_TIM4
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if (&PWMD5 == pwmp) {
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rcuEnableTIM4(true);
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rcuResetTIM4();
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#if !defined(GD32_TIM4_SUPPRESS_ISR)
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eclicEnableVector(GD32_TIM4_NUMBER, GD32_PWM_TIM4_IRQ_PRIORITY, GD32_PWM_TIM4_IRQ_TRIGGER);
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#endif
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#if defined(GD32_TIM4CLK)
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pwmp->clock = GD32_TIM4CLK;
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#else
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pwmp->clock = GD32_TIMCLK1;
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#endif
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}
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#endif
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/* All channels configured in PWM1 mode with preload enabled and will
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stay that way until the driver is stopped.*/
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pwmp->tim->CHCTL0 = GD32_TIM_CCMR1_OC1M(6) | GD32_TIM_CCMR1_OC1PE |
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GD32_TIM_CCMR1_OC2M(6) | GD32_TIM_CCMR1_OC2PE;
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pwmp->tim->CHCTL1 = GD32_TIM_CCMR2_OC3M(6) | GD32_TIM_CCMR2_OC3PE |
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GD32_TIM_CCMR2_OC4M(6) | GD32_TIM_CCMR2_OC4PE;
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}
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else {
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/* Driver re-configuration scenario, it must be stopped first.*/
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pwmp->tim->CTL0 = 0; /* Timer disabled. */
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pwmp->tim->CHCV[0] = 0; /* Comparator 1 disabled. */
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pwmp->tim->CHCV[1] = 0; /* Comparator 2 disabled. */
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pwmp->tim->CHCV[2] = 0; /* Comparator 3 disabled. */
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pwmp->tim->CHCV[3] = 0; /* Comparator 4 disabled. */
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pwmp->tim->CNT = 0; /* Counter reset to zero. */
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}
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/* Timer configuration.*/
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psc = (pwmp->clock / pwmp->config->frequency) - 1;
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osalDbgAssert((psc <= 0xFFFF) &&
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((psc + 1) * pwmp->config->frequency) == pwmp->clock,
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"invalid frequency");
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pwmp->tim->PSC = psc;
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pwmp->tim->CAR = pwmp->period - 1;
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pwmp->tim->CTL1 = pwmp->config->ctl1;
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/* Output enables and polarities setup.*/
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ccer = 0;
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switch (pwmp->config->channels[0].mode & PWM_OUTPUT_MASK) {
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case PWM_OUTPUT_ACTIVE_LOW:
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ccer |= GD32_TIM_CCER_CC1P;
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/* Falls through.*/
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case PWM_OUTPUT_ACTIVE_HIGH:
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ccer |= GD32_TIM_CCER_CC1E;
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/* Falls through.*/
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default:
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;
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}
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switch (pwmp->config->channels[1].mode & PWM_OUTPUT_MASK) {
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case PWM_OUTPUT_ACTIVE_LOW:
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ccer |= GD32_TIM_CCER_CC2P;
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/* Falls through.*/
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case PWM_OUTPUT_ACTIVE_HIGH:
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ccer |= GD32_TIM_CCER_CC2E;
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/* Falls through.*/
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default:
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;
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}
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switch (pwmp->config->channels[2].mode & PWM_OUTPUT_MASK) {
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case PWM_OUTPUT_ACTIVE_LOW:
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ccer |= GD32_TIM_CCER_CC3P;
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/* Falls through.*/
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case PWM_OUTPUT_ACTIVE_HIGH:
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ccer |= GD32_TIM_CCER_CC3E;
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/* Falls through.*/
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default:
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;
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}
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switch (pwmp->config->channels[3].mode & PWM_OUTPUT_MASK) {
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case PWM_OUTPUT_ACTIVE_LOW:
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ccer |= GD32_TIM_CCER_CC4P;
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/* Falls through.*/
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case PWM_OUTPUT_ACTIVE_HIGH:
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ccer |= GD32_TIM_CCER_CC4E;
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/* Falls through.*/
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default:
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;
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}
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#if GD32_PWM_USE_ADVANCED
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if (&PWMD1 == pwmp) {
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switch (pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
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case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:
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ccer |= GD32_TIM_CCER_CC1NP;
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/* Falls through.*/
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case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:
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ccer |= GD32_TIM_CCER_CC1NE;
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/* Falls through.*/
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default:
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;
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}
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switch (pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
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case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:
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ccer |= GD32_TIM_CCER_CC2NP;
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/* Falls through.*/
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case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:
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ccer |= GD32_TIM_CCER_CC2NE;
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/* Falls through.*/
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default:
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;
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}
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switch (pwmp->config->channels[2].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
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case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:
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ccer |= GD32_TIM_CCER_CC3NP;
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/* Falls through.*/
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case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:
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ccer |= GD32_TIM_CCER_CC3NE;
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/* Falls through.*/
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default:
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;
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}
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switch (pwmp->config->channels[3].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
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case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:
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ccer |= GD32_TIM_CCER_CC4NP;
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/* Falls through.*/
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case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:
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ccer |= GD32_TIM_CCER_CC4NE;
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/* Falls through.*/
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default:
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;
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}
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}
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#endif /* GD32_PWM_USE_ADVANCED*/
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pwmp->tim->CHCTL2 = ccer;
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pwmp->tim->SWEVG = GD32_TIM_EGR_UG; /* Update event. */
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pwmp->tim->INTF = 0; /* Clear pending IRQs. */
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pwmp->tim->DMAINTEN = pwmp->config->dmainten & /* DMA-related DIER settings. */
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~GD32_TIM_DIER_IRQ_MASK;
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#if GD32_PWM_USE_TIM0
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#if GD32_PWM_USE_ADVANCED
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pwmp->tim->CCHP = pwmp->config->cchp | GD32_TIM_BDTR_MOE;
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#else
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pwmp->tim->CCHP = GD32_TIM_BDTR_MOE;
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#endif
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#endif
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/* Timer configured and started.*/
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pwmp->tim->CTL0 = GD32_TIM_CR1_ARPE | GD32_TIM_CR1_URS |
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GD32_TIM_CR1_CEN;
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}
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/**
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* @brief Deactivates the PWM peripheral.
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*
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* @param[in] pwmp pointer to a @p PWMDriver object
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*
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* @notapi
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*/
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void pwm_lld_stop(PWMDriver *pwmp) {
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/* If in ready state then disables the PWM clock.*/
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if (pwmp->state == PWM_READY) {
|
|
pwmp->tim->CTL0 = 0; /* Timer disabled. */
|
|
pwmp->tim->DMAINTEN = 0; /* All IRQs disabled. */
|
|
pwmp->tim->INTF = 0; /* Clear eventual pending IRQs. */
|
|
#if GD32_PWM_USE_TIM0
|
|
pwmp->tim->CCHP = 0;
|
|
#endif
|
|
|
|
#if GD32_PWM_USE_TIM0
|
|
if (&PWMD1 == pwmp) {
|
|
#if !defined(GD32_TIM0_SUPPRESS_ISR)
|
|
eclicDisableVector(GD32_TIM0_UP_NUMBER);
|
|
eclicDisableVector(GD32_TIM0_CC_NUMBER);
|
|
#endif
|
|
rcuDisableTIM0();
|
|
}
|
|
#endif
|
|
|
|
#if GD32_PWM_USE_TIM1
|
|
if (&PWMD2 == pwmp) {
|
|
#if !defined(GD32_TIM1_SUPPRESS_ISR)
|
|
eclicDisableVector(GD32_TIM1_NUMBER);
|
|
#endif
|
|
rcuDisableTIM1();
|
|
}
|
|
#endif
|
|
|
|
#if GD32_PWM_USE_TIM2
|
|
if (&PWMD3 == pwmp) {
|
|
#if !defined(GD32_TIM2_SUPPRESS_ISR)
|
|
eclicDisableVector(GD32_TIM2_NUMBER);
|
|
#endif
|
|
rcuDisableTIM2();
|
|
}
|
|
#endif
|
|
|
|
#if GD32_PWM_USE_TIM3
|
|
if (&PWMD4 == pwmp) {
|
|
#if !defined(GD32_TIM3_SUPPRESS_ISR)
|
|
eclicDisableVector(GD32_TIM3_NUMBER);
|
|
#endif
|
|
rcuDisableTIM3();
|
|
}
|
|
#endif
|
|
|
|
#if GD32_PWM_USE_TIM4
|
|
if (&PWMD5 == pwmp) {
|
|
#if !defined(GD32_TIM4_SUPPRESS_ISR)
|
|
eclicDisableVector(GD32_TIM4_NUMBER);
|
|
#endif
|
|
rcuDisableTIM4();
|
|
}
|
|
#endif
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enables a PWM channel.
|
|
* @pre The PWM unit must have been activated using @p pwmStart().
|
|
* @post The channel is active using the specified configuration.
|
|
* @note The function has effect at the next cycle start.
|
|
* @note Channel notification is not enabled.
|
|
*
|
|
* @param[in] pwmp pointer to a @p PWMDriver object
|
|
* @param[in] channel PWM channel identifier (0...channels-1)
|
|
* @param[in] width PWM pulse width as clock pulses number
|
|
*
|
|
* @notapi
|
|
*/
|
|
void pwm_lld_enable_channel(PWMDriver *pwmp,
|
|
pwmchannel_t channel,
|
|
pwmcnt_t width) {
|
|
|
|
/* Changing channel duty cycle on the fly.*/
|
|
pwmp->tim->CHCV[channel] = width;
|
|
}
|
|
|
|
/**
|
|
* @brief Disables a PWM channel and its notification.
|
|
* @pre The PWM unit must have been activated using @p pwmStart().
|
|
* @post The channel is disabled and its output line returned to the
|
|
* idle state.
|
|
* @note The function has effect at the next cycle start.
|
|
*
|
|
* @param[in] pwmp pointer to a @p PWMDriver object
|
|
* @param[in] channel PWM channel identifier (0...channels-1)
|
|
*
|
|
* @notapi
|
|
*/
|
|
void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
|
|
pwmp->tim->CHCV[channel] = 0;
|
|
pwmp->tim->DMAINTEN &= ~(2 << channel);
|
|
}
|
|
|
|
/**
|
|
* @brief Enables the periodic activation edge notification.
|
|
* @pre The PWM unit must have been activated using @p pwmStart().
|
|
* @note If the notification is already enabled then the call has no effect.
|
|
*
|
|
* @param[in] pwmp pointer to a @p PWMDriver object
|
|
*
|
|
* @notapi
|
|
*/
|
|
void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
|
|
uint32_t dier = pwmp->tim->DMAINTEN;
|
|
|
|
/* If the IRQ is not already enabled care must be taken to clear it,
|
|
it is probably already pending because the timer is running.*/
|
|
if ((dier & GD32_TIM_DIER_UIE) == 0) {
|
|
pwmp->tim->INTF = ~GD32_TIM_SR_UIF;
|
|
pwmp->tim->DMAINTEN = dier | GD32_TIM_DIER_UIE;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Disables the periodic activation edge notification.
|
|
* @pre The PWM unit must have been activated using @p pwmStart().
|
|
* @note If the notification is already disabled then the call has no effect.
|
|
*
|
|
* @param[in] pwmp pointer to a @p PWMDriver object
|
|
*
|
|
* @notapi
|
|
*/
|
|
void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
|
|
|
|
pwmp->tim->DMAINTEN &= ~GD32_TIM_DIER_UIE;
|
|
}
|
|
|
|
/**
|
|
* @brief Enables a channel de-activation edge notification.
|
|
* @pre The PWM unit must have been activated using @p pwmStart().
|
|
* @pre The channel must have been activated using @p pwmEnableChannel().
|
|
* @note If the notification is already enabled then the call has no effect.
|
|
*
|
|
* @param[in] pwmp pointer to a @p PWMDriver object
|
|
* @param[in] channel PWM channel identifier (0...channels-1)
|
|
*
|
|
* @notapi
|
|
*/
|
|
void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
|
|
pwmchannel_t channel) {
|
|
uint32_t dier = pwmp->tim->DMAINTEN;
|
|
|
|
/* If the IRQ is not already enabled care must be taken to clear it,
|
|
it is probably already pending because the timer is running.*/
|
|
if ((dier & (2 << channel)) == 0) {
|
|
pwmp->tim->INTF = ~(2 << channel);
|
|
pwmp->tim->DMAINTEN = dier | (2 << channel);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Disables a channel de-activation edge notification.
|
|
* @pre The PWM unit must have been activated using @p pwmStart().
|
|
* @pre The channel must have been activated using @p pwmEnableChannel().
|
|
* @note If the notification is already disabled then the call has no effect.
|
|
*
|
|
* @param[in] pwmp pointer to a @p PWMDriver object
|
|
* @param[in] channel PWM channel identifier (0...channels-1)
|
|
*
|
|
* @notapi
|
|
*/
|
|
void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
|
|
pwmchannel_t channel) {
|
|
|
|
pwmp->tim->DMAINTEN &= ~(2 << channel);
|
|
}
|
|
|
|
/**
|
|
* @brief Common TIM1...TIM4 IRQ handler.
|
|
* @note It is assumed that the various sources are only activated if the
|
|
* associated callback pointer is not equal to @p NULL in order to not
|
|
* perform an extra check in a potentially critical interrupt handler.
|
|
*
|
|
* @param[in] pwmp pointer to a @p PWMDriver object
|
|
*
|
|
* @notapi
|
|
*/
|
|
void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
|
|
uint32_t sr;
|
|
|
|
sr = pwmp->tim->INTF;
|
|
sr &= pwmp->tim->DMAINTEN & GD32_TIM_DIER_IRQ_MASK;
|
|
pwmp->tim->INTF = ~sr;
|
|
if (((sr & GD32_TIM_SR_CC1IF) != 0) &&
|
|
(pwmp->config->channels[0].callback != NULL))
|
|
pwmp->config->channels[0].callback(pwmp);
|
|
if (((sr & GD32_TIM_SR_CC2IF) != 0) &&
|
|
(pwmp->config->channels[1].callback != NULL))
|
|
pwmp->config->channels[1].callback(pwmp);
|
|
if (((sr & GD32_TIM_SR_CC3IF) != 0) &&
|
|
(pwmp->config->channels[2].callback != NULL))
|
|
pwmp->config->channels[2].callback(pwmp);
|
|
if (((sr & GD32_TIM_SR_CC4IF) != 0) &&
|
|
(pwmp->config->channels[3].callback != NULL))
|
|
pwmp->config->channels[3].callback(pwmp);
|
|
if (((sr & GD32_TIM_SR_UIF) != 0) && (pwmp->config->callback != NULL))
|
|
pwmp->config->callback(pwmp);
|
|
}
|
|
|
|
#endif /* HAL_USE_PWM */
|
|
|
|
/** @} */
|