278 lines
6.7 KiB
C
278 lines
6.7 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2021 Stefan Kerkmann
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file GD32VF103/gd32_isr.c
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* @brief GD32VF103 ISR handler code.
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*
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* @addtogroup GD32VF103_ISR
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* @{
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*/
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#include "hal.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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#define exti_serve_irq(pd, channel) \
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{ \
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\
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if ((pd) & (1U << (channel))) { \
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_pal_isr_code(channel); \
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} \
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__)
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#if !defined(GD32_DISABLE_EXTI0_HANDLER)
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/**
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* @brief EXTI[0] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(vector25) {
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uint32_t pd;
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OSAL_IRQ_PROLOGUE();
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pd = EXTI->PD;
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pd &= EXTI->INTEN & (1U << 0);
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EXTI->PD = pd;
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exti_serve_irq(pd, 0);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(GD32_DISABLE_EXTI1_HANDLER)
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/**
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* @brief EXTI[1] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(vector26) {
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uint32_t pd;
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OSAL_IRQ_PROLOGUE();
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pd = EXTI->PD;
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pd &= EXTI->INTEN & (1U << 1);
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EXTI->PD = pd;
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exti_serve_irq(pd, 1);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(GD32_DISABLE_EXTI2_HANDLER)
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/**
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* @brief EXTI[2] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(vector27) {
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uint32_t pd;
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OSAL_IRQ_PROLOGUE();
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pd = EXTI->PD;
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pd &= EXTI->INTEN & (1U << 2);
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EXTI->PD = pd;
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exti_serve_irq(pd, 2);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(GD32_DISABLE_EXTI3_HANDLER)
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/**
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* @brief EXTI[3] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(vector28) {
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uint32_t pd;
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OSAL_IRQ_PROLOGUE();
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pd = EXTI->PD;
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pd &= EXTI->INTEN & (1U << 3);
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EXTI->PD = pd;
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exti_serve_irq(pd, 3);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(GD32_DISABLE_EXTI4_HANDLER)
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/**
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* @brief EXTI[4] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(vector29) {
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uint32_t pd;
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OSAL_IRQ_PROLOGUE();
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pd = EXTI->PD;
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pd &= EXTI->INTEN & (1U << 4);
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EXTI->PD = pd;
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exti_serve_irq(pd, 4);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(GD32_DISABLE_EXTI5_9_HANDLER)
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/**
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* @brief EXTI[5]...EXTI[9] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector9C) {
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uint32_t pd;
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OSAL_IRQ_PROLOGUE();
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pd = EXTI->PD;
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pd &= EXTI->INTEN & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9));
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EXTI->PD = pd;
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exti_serve_irq(pd, 5);
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exti_serve_irq(pd, 6);
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exti_serve_irq(pd, 7);
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exti_serve_irq(pd, 8);
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exti_serve_irq(pd, 9);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if !defined(GD32_DISABLE_EXTI10_15_HANDLER)
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/**
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* @brief EXTI[10]...EXTI[15] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(vector59) {
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uint32_t pd;
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OSAL_IRQ_PROLOGUE();
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pd = EXTI->PD;
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pd &= EXTI->INTEN & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
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(1U << 14) | (1U << 15));
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EXTI->PD = pd;
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exti_serve_irq(pd, 10);
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exti_serve_irq(pd, 11);
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exti_serve_irq(pd, 12);
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exti_serve_irq(pd, 13);
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exti_serve_irq(pd, 14);
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exti_serve_irq(pd, 15);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#endif /* HAL_USE_PAL */
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Enables IRQ sources.
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*
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* @notapi
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*/
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void irqInit(void) {
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/* Disable interrupts during init */
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__disable_irq();
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/* Reset eclic configuration registers */
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ECLIC->CFG = 0;
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ECLIC->MTH = 0;
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/* Reset eclic interrupt registers */
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for (int32_t i = 0; i < SOC_INT_MAX; i++){
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ECLIC->CTRL[0].INTIP = 0;
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ECLIC->CTRL[0].INTIE = 0;
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ECLIC->CTRL[0].INTATTR = 0;
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ECLIC->CTRL[0].INTCTRL = 0;
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}
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/* Set 4 bits for interrupt level and 0 bits for priority */
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__ECLIC_SetCfgNlbits(4);
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/* Enable interrupts globaly */
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__enable_irq();
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#if HAL_USE_PAL
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eclicEnableVector(EXTI0_IRQn, GD32_IRQ_EXTI0_PRIORITY, GD32_IRQ_EXTI0_TRIGGER);
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eclicEnableVector(EXTI1_IRQn, GD32_IRQ_EXTI1_PRIORITY, GD32_IRQ_EXTI1_TRIGGER);
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eclicEnableVector(EXTI2_IRQn, GD32_IRQ_EXTI2_PRIORITY, GD32_IRQ_EXTI2_TRIGGER);
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eclicEnableVector(EXTI3_IRQn, GD32_IRQ_EXTI3_PRIORITY, GD32_IRQ_EXTI3_TRIGGER);
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eclicEnableVector(EXTI4_IRQn, GD32_IRQ_EXTI4_PRIORITY, GD32_IRQ_EXTI4_TRIGGER);
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eclicEnableVector(EXTI5_9_IRQn, GD32_IRQ_EXTI5_9_PRIORITY, GD32_IRQ_EXTI5_9_TRIGGER);
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eclicEnableVector(EXTI10_15_IRQn, GD32_IRQ_EXTI10_15_PRIORITY, GD32_IRQ_EXTI10_15_TRIGGER);
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#endif
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}
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/**
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* @brief Disables IRQ sources.
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*
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* @notapi
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*/
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void irqDeinit(void) {
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#if HAL_USE_PAL
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eclicDisableVector(EXTI0_IRQn);
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eclicDisableVector(EXTI1_IRQn);
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eclicDisableVector(EXTI2_IRQn);
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eclicDisableVector(EXTI3_IRQn);
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eclicDisableVector(EXTI4_IRQn);
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eclicDisableVector(EXTI5_9_IRQn);
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eclicDisableVector(EXTI10_15_IRQn);
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#endif
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}
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/** @} */
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