286 lines
12 KiB
C
286 lines
12 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2021 Stefan Kerkmann
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file GD32VF103/hal_adc_lld.h
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* @brief GD32VF103 ADC subsystem low level driver header.
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*
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* @addtogroup ADC
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* @{
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*/
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#ifndef HAL_ADC_LLD_H
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#define HAL_ADC_LLD_H
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#if HAL_USE_ADC || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name Triggers selection
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* @{
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*/
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#define ADC_CTL1_ETSRC_SRC(n) ((n) << 17) /**< @brief Trigger source. */
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#define ADC_CTL1_ETSRC_SWSTART (7 << 17) /**< @brief Software trigger. */
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/** @} */
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/**
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* @name Available analog channels
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* @{
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*/
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#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */
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#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */
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#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */
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#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */
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#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */
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#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */
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#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */
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#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */
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#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */
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#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */
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#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */
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#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */
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#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */
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#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */
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#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */
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#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */
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#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/
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#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */
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/** @} */
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/**
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* @name Sampling rates
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* @{
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*/
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#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */
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#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */
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#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */
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#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */
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#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */
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#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */
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#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */
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#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief ADC0 driver enable switch.
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* @details If set to @p TRUE the support for ADC0 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(GD32_ADC_USE_ADC0) || defined(__DOXYGEN__)
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#define GD32_ADC_USE_ADC0 FALSE
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#endif
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/**
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* @brief ADC0 DMA priority (0..3|lowest..highest).
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*/
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#if !defined(GD32_ADC_ADC0_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_ADC_ADC0_DMA_PRIORITY 2
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#endif
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/**
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* @brief ADC0 interrupt priority level setting.
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*/
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#if !defined(GD32_ADC_ADC0_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_ADC_ADC0_IRQ_PRIORITY 5
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if GD32_ADC_USE_ADC0 && !GD32_HAS_ADC0
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#error "ADC0 not present in the selected device"
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#endif
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#if !GD32_ADC_USE_ADC0
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#error "ADC driver activated but no ADC peripheral assigned"
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#endif
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#if !defined(GD32_DMA_REQUIRED)
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#define GD32_DMA_REQUIRED
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief ADC sample data type.
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*/
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typedef uint16_t adcsample_t;
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/**
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* @brief Channels number in a conversion group.
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*/
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typedef uint16_t adc_channels_num_t;
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/**
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* @brief Possible ADC failure causes.
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* @note Error codes are architecture dependent and should not relied
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* upon.
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*/
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typedef enum {
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ADC_ERR_DMAFAILURE = 0 /**< DMA operations failure. */
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} adcerror_t;
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @brief Low level fields of the ADC driver structure.
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*/
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#define adc_lld_driver_fields \
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/* Pointer to the ADCx registers block.*/ \
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ADC_TypeDef *adc; \
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/* Pointer to associated DMA channel.*/ \
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const gd32_dma_stream_t *dmastp; \
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/* DMA mode bit mask.*/ \
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uint32_t dmamode
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/**
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* @brief Low level fields of the ADC configuration structure.
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*/
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#define adc_lld_config_fields \
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/* Dummy configuration, it is not needed.*/ \
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uint32_t dummy
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/**
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* @brief Low level fields of the ADC configuration structure.
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*/
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#define adc_lld_configuration_group_fields \
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/* ADC CTL0 register initialization data. \
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NOTE: All the required bits must be defined into this field except \
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@p ADC_CTL0_SM that is enforced inside the driver.*/ \
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uint32_t ctl0; \
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/* ADC CTL1 register initialization data. \
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NOTE: All the required bits must be defined into this field except \
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@p ADC_CTL1_DMA, @p ADC_CTL1_CTN and @p ADC_CTL1_ADCON that are \
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enforced inside the driver.*/ \
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uint32_t ctl1; \
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/* ADC SAMPT0 register initialization data. \
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NOTE: In this field must be specified the sample times for channels \
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10...17.*/ \
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uint32_t sampt0; \
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/* ADC SAMPT1 register initialization data. \
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NOTE: In this field must be specified the sample times for channels \
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0...9.*/ \
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uint32_t sampt1; \
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/* ADC RSQ0 register initialization data. \
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NOTE: Conversion group sequence 13...16 + sequence length.*/ \
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uint32_t rsq0; \
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/* ADC RSQ1 register initialization data. \
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NOTE: Conversion group sequence 7...12.*/ \
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uint32_t rsq1; \
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/* ADC RSQ2 register initialization data. \
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NOTE: Conversion group sequence 1...6.*/ \
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uint32_t rsq2
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/**
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* @name Sequences building helper macros
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* @{
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*/
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/**
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* @brief Number of channels in a conversion sequence.
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*/
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#define ADC_RSQ0_NUM_CH(n) (((n) - 1) << 20)
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#define ADC_RSQ2_RSQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */
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#define ADC_RSQ2_RSQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */
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#define ADC_RSQ2_RSQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */
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#define ADC_RSQ2_RSQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */
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#define ADC_RSQ2_RSQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */
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#define ADC_RSQ2_RSQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */
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#define ADC_RSQ1_RSQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */
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#define ADC_RSQ1_RSQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */
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#define ADC_RSQ1_RSQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */
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#define ADC_RSQ1_RSQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/
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#define ADC_RSQ1_RSQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/
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#define ADC_RSQ1_RSQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/
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#define ADC_RSQ0_RSQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/
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#define ADC_RSQ0_RSQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/
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#define ADC_RSQ0_RSQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/
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#define ADC_RSQ0_RSQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/
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/** @} */
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/**
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* @name Sampling rate settings helper macros
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* @{
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*/
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#define ADC_SAMPT1_SMP_SPT0(n) ((n) << 0) /**< @brief AN0 sampling time. */
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#define ADC_SAMPT1_SMP_SPT1(n) ((n) << 3) /**< @brief AN1 sampling time. */
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#define ADC_SAMPT1_SMP_SPT2(n) ((n) << 6) /**< @brief AN2 sampling time. */
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#define ADC_SAMPT1_SMP_SPT3(n) ((n) << 9) /**< @brief AN3 sampling time. */
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#define ADC_SAMPT1_SMP_SPT4(n) ((n) << 12) /**< @brief AN4 sampling time. */
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#define ADC_SAMPT1_SMP_SPT5(n) ((n) << 15) /**< @brief AN5 sampling time. */
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#define ADC_SAMPT1_SMP_SPT6(n) ((n) << 18) /**< @brief AN6 sampling time. */
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#define ADC_SAMPT1_SMP_SPT7(n) ((n) << 21) /**< @brief AN7 sampling time. */
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#define ADC_SAMPT1_SMP_SPT8(n) ((n) << 24) /**< @brief AN8 sampling time. */
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#define ADC_SAMPT1_SMP_SPT9(n) ((n) << 27) /**< @brief AN9 sampling time. */
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#define ADC_SAMPT0_SMP_SPT10(n) ((n) << 0) /**< @brief AN10 sampling time. */
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#define ADC_SAMPT0_SMP_SPT11(n) ((n) << 3) /**< @brief AN11 sampling time. */
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#define ADC_SAMPT0_SMP_SPT12(n) ((n) << 6) /**< @brief AN12 sampling time. */
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#define ADC_SAMPT0_SMP_SPT13(n) ((n) << 9) /**< @brief AN13 sampling time. */
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#define ADC_SAMPT0_SMP_SPT14(n) ((n) << 12) /**< @brief AN14 sampling time. */
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#define ADC_SAMPT0_SMP_SPT15(n) ((n) << 15) /**< @brief AN15 sampling time. */
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#define ADC_SAMPT0_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
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sampling time. */
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#define ADC_SAMPT0_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference
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sampling time. */
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/** @} */
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if GD32_ADC_USE_ADC0 && !defined(__DOXYGEN__)
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extern ADCDriver ADCD1;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void adc_lld_init(void);
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void adc_lld_start(ADCDriver *adcp);
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void adc_lld_stop(ADCDriver *adcp);
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void adc_lld_start_conversion(ADCDriver *adcp);
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void adc_lld_stop_conversion(ADCDriver *adcp);
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#ifdef __cplusplus
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}
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#endif
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#endif /* HAL_USE_ADC */
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#endif /* HAL_ADC_LLD_H */
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/** @} */
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