242 lines
7.8 KiB
C
242 lines
7.8 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2021 Stefan Kerkmann
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file GD32VF103/hal_lld.c
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* @brief GD32VF103 HAL subsystem low level driver source.
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*
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* @addtogroup HAL
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* @{
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*/
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#include "hal.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/**
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* @brief NMSIS system core clock variable.
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* @note It is declared in system_gd32vf103.h.
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*/
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uint32_t SystemCoreClock = GD32_HCLK;
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Initializes the backup domain.
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* @note WARNING! Changing clock source impossible without resetting
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* of the whole BKP domain.
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*/
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static void hal_lld_backup_domain_init(void) {
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/* Backup domain access enabled and left open.*/
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PMU->CTL |= PMU_CTL_BKPWEN;
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#if HAL_USE_RTC
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/* Reset BKP domain if different clock source selected.*/
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if ((RCU->BDCTL & GD32_RTCSRC_MASK) != GD32_RTCSRC) {
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/* Backup domain reset.*/
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RCU->BDCTL = RCU_BDCTL_BKPRST;
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RCU->BDCTL = 0;
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}
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/* If enabled then the LXTAL is started.*/
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#if GD32_LXTAL_ENABLED
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#if defined(GD32_LXTAL_BYPASS)
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/* LXTAL Bypass.*/
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RCU->BDCTL |= RCU_BDCTL_LXTALEN | RCU_BDCTL_LXTALBPS;
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#else
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/* No LXTAL Bypass.*/
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RCU->BDCTL |= RCU_BDCTL_LXTALEN;
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#endif
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while ((RCU->BDCTL & RCU_BDCTL_LXTALSTB) == 0)
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; /* Waits until LXTAL is stable. */
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#endif /* GD32_LXTAL_ENABLED */
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#if GD32_RTCSRC != GD32_RTCSRC_NOCLOCK
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/* If the backup domain hasn't been initialized yet then proceed with
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initialization.*/
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if ((RCU->BDCTL & RCU_BDCTL_RTCEN) == 0) {
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/* Selects clock source.*/
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RCU->BDCTL |= GD32_RTCSRC;
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/* Prescaler value loaded in registers.*/
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rtc_lld_set_prescaler();
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/* RTC clock enabled.*/
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RCU->BDCTL |= RCU_BDCTL_RTCEN;
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}
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#endif /* GD32_RTCSRC != GD32_RTCSRC_NOCLOCK */
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#endif /* HAL_USE_RTC */
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level HAL driver initialization.
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*
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* @notapi
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*/
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void hal_lld_init(void) {
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/* Reset of all peripherals.*/
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rcuResetAPB1(0xFFFFFFFF);
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rcuResetAPB2(0xFFFFFFFF);
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/* PMU and BD clocks enabled.*/
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rcuEnablePMUInterface(true);
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rcuEnableBKPInterface(true);
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/* Initializes the backup domain.*/
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hal_lld_backup_domain_init();
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/* DMA subsystems initialization.*/
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#if defined(GD32_DMA_REQUIRED)
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dmaInit();
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#endif
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/* IRQ subsystem initialization.*/
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irqInit();
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/* Programmable voltage detector enable.*/
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#if GD32_PVD_ENABLE
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PMU->CTL |= PMU_CTL_LVDEN | (GD32_LVDT & GD32_LVDT_MASK);
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#endif /* GD32_PVD_ENABLE */
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}
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/**
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* @brief GD32 clocks and PLL initialization.
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* @note All the involved constants come from the file @p board.h.
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* @note This function should be invoked just after the system reset.
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*
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* @special
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*/
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/*
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* Clocks initialization for the CL sub-family.
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*/
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void gd32_clock_init(void) {
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#if !GD32_NO_INIT
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/* IRC8M setup, it enforces the reset situation in order to handle possible
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problems with JTAG probes and re-initializations.*/
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RCU->CTL |= RCU_CTL_IRC8MEN; /* Make sure IRC8M is ON. */
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while (!(RCU->CTL & RCU_CTL_IRC8MSTB))
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; /* Wait until IRC8M is stable. */
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/* IRC8M is selected as new source without touching the other fields in
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CFGR. Clearing the register has to be postponed after IRC8M is the
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new source.*/
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RCU->CFG0 &= ~RCU_CFG0_SCS; /* Reset SW, selecting IRC8M. */
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while ((RCU->CFG0 & RCU_CFG0_SCSS) != RCU_CFG0_SCSS_IRC8M)
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; /* Wait until IRC8M is selected. */
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/* Registers finally cleared to reset values.*/
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RCU->CTL &= RCU_CTL_IRC8MADJ | RCU_CTL_IRC8MEN; /* CR Reset value. */
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RCU->CFG0 = 0; /* CFGR reset value. */
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#if GD32_HXTAL_ENABLED
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#if defined(GD32_HXTAL_BYPASS)
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/* HXTAL Bypass.*/
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RCU->CTL |= RCU_CTL_HXTALBPS;
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#endif
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/* HXTAL activation.*/
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RCU->CTL |= RCU_CTL_HXTALEN;
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while (!(RCU->CTL & RCU_CTL_HXTALSTB))
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; /* Waits until HXTAL is stable. */
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#endif
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#if GD32_IRC40K_ENABLED
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/* IRC40K activation.*/
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RCU->RSTSCK |= RCU_RSTSCK_IRC40KEN;
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while ((RCU->RSTSCK & RCU_RSTSCK_IRC40KSTB) == 0)
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; /* Waits until IRC40K is stable. */
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#endif
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/* Settings of various dividers and multipliers in CFGR2.*/
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RCU->CFG1 = GD32_PLL2MF | GD32_PLL1MF | GD32_PREDV1 |
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GD32_PREDV0 | GD32_PREDV0SEL;
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/* PLL1 setup, if activated.*/
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#if GD32_ACTIVATE_PLL1
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RCU->CTL |= RCU_CTL_PLL1EN;
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while (!(RCU->CTL & RCU_CTL_PLL1STB))
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; /* Waits until PLL1 is stable. */
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#endif
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/* PLL2 setup, if activated.*/
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#if GD32_ACTIVATE_PLL2
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RCU->CTL |= RCU_CTL_PLL2EN;
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while (!(RCU->CTL & RCU_CTL_PLL2STB))
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; /* Waits until PLL2 is stable. */
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#endif
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/* PLL setup, if activated.*/
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#if GD32_ACTIVATE_PLL
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RCU->CFG0 |= GD32_PLLMF | GD32_PLLSEL;
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RCU->CTL |= RCU_CTL_PLLEN;
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while (!(RCU->CTL & RCU_CTL_PLLSTB))
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; /* Waits until PLL is stable. */
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#endif
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/* Clock settings.*/
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#if GD32_HAS_USBFS
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RCU->CFG0 = GD32_CKOUT0SEL | GD32_USBFSPSC | GD32_PLLMF | GD32_PLLSEL |
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GD32_ADCPSC | GD32_APB2PSC | GD32_APB1PSC | GD32_AHBPSC;
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#else
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RCU->CFG0 = GD32_MCO | GD32_PLLMF | GD32_PLLSEL |
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GD32_ADCPSC | GD32_APB2PSC | GD32_APB1PSC | GD32_AHBPSC;
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#endif
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/* Flash setup and final clock selection. */
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FLASH->WS = GD32_FLASHBITS; /* Flash wait states depending on clock. */
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while ((FLASH->WS & FLASH_WS_WSCNT_Msk) !=
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(GD32_FLASHBITS & FLASH_WS_WSCNT_Msk)) {
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}
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/* Switching to the configured clock source if it is different from IRC8M.*/
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#if (GD32_SCS != GD32_SCS_IRC8M)
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RCU->CFG0 |= GD32_SCS; /* Switches on the selected clock source. */
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while ((RCU->CFG0 & RCU_CFG0_SCSS) != (GD32_SCS << 2))
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;
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#endif
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#if !GD32_IRC8M_ENABLED
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RCU->CTL &= ~RCU_CTL_IRC8MEN;
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#endif
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#endif /* !GD32_NO_INIT */
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}
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/** @} */
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