277 lines
8.9 KiB
C
277 lines
8.9 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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Concepts and parts of this file have been contributed by Uladzimir Pylinsky
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aka barthess.
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*/
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/*
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TODO:
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write memtest function using ideas from http://www.memtest86.com/technical.htm
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*/
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#include "ch.h"
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#include "hal.h"
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#include "string.h"
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#include "fsmc_sdram.h"
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/*
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******************************************************************************
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* DEFINES
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******************************************************************************
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*/
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#define USE_INFINITE_MEMTEST FALSE
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/*
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* FMC SDRAM Mode definition register defines
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*/
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#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001)
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#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002)
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#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004)
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#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
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#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020)
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#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030)
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#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
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#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
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/*
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* FMC_ReadPipe_Delay
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*/
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#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000)
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#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000)
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#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000)
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#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000)
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/*
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* FMC_Read_Burst
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*/
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#define FMC_Read_Burst_Disable ((uint32_t)0x00000000)
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#define FMC_Read_Burst_Enable ((uint32_t)0x00001000)
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#define FMC_Read_Burst_Mask ((uint32_t)0x00001000)
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/*
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* FMC_SDClock_Period
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*/
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#define FMC_SDClock_Disable ((uint32_t)0x00000000)
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#define FMC_SDClock_Period_2 ((uint32_t)0x00000800)
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#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00)
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#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00)
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/*
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* FMC_ColumnBits_Number
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*/
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#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000)
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#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001)
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#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002)
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#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003)
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/*
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* FMC_RowBits_Number
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*/
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#define FMC_RowBits_Number_11b ((uint32_t)0x00000000)
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#define FMC_RowBits_Number_12b ((uint32_t)0x00000004)
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#define FMC_RowBits_Number_13b ((uint32_t)0x00000008)
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/*
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* FMC_SDMemory_Data_Width
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*/
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#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000)
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#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010)
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#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020)
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/*
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* FMC_InternalBank_Number
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*/
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#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000)
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#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040)
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/*
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* FMC_CAS_Latency
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*/
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#define FMC_CAS_Latency_1 ((uint32_t)0x00000080)
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#define FMC_CAS_Latency_2 ((uint32_t)0x00000100)
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#define FMC_CAS_Latency_3 ((uint32_t)0x00000180)
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/*
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* FMC_Write_Protection
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*/
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#define FMC_Write_Protection_Disable ((uint32_t)0x00000000)
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#define FMC_Write_Protection_Enable ((uint32_t)0x00000200)
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/*
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******************************************************************************
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* EXTERNS
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******************************************************************************
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*/
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/*
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******************************************************************************
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* PROTOTYPES
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******************************************************************************
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*/
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/*
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******************************************************************************
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* GLOBAL VARIABLES
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******************************************************************************
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*/
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static uint32_t extram_check_buf[16 * 1024];
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static uint32_t *extram_start = (uint32_t *)STM32_SDRAM1_MAP_BASE;
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static const size_t extram_size = 1024*1024;
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/*
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* SDRAM driver configuration structure.
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*/
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static const SDRAMConfig sdram_cfg = {
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.sdcr = (uint32_t) FMC_ColumnBits_Number_9b |
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FMC_RowBits_Number_13b |
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FMC_SDMemory_Width_16b |
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FMC_InternalBank_Number_4 |
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FMC_CAS_Latency_3 |
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FMC_Write_Protection_Disable |
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FMC_SDClock_Period_3 |
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FMC_Read_Burst_Enable |
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FMC_ReadPipe_Delay_1,
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.sdtr = (uint32_t) (2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles)
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(7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns))
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(4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns))
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(7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns))
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(2 << 16) | // FMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns))
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(2 << 20) | // FMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns)
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(2 << 24), // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns)
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/* NRFS = 4-1*/
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.sdcmr = (3 << 5) | (FMC_SDCMR_MRD_BURST_LENGTH_2 |
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FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |
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FMC_SDCMR_MRD_CAS_LATENCY_3 |
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FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |
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FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9,
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/* if (STM32_SYSCLK == 180000000) ->
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64ms/4096=15.625us
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15.625us*90MHz=1406-20=1386 */
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.sdrtr = 1386 << 1
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};
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/* benchmarking results in MiB/S */
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double memset_speed_ext;
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double memset_speed_int;
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double memcpy_speed_ext2int;
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double memcpy_speed_int2ext;
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/*
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******************************************************************************
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******************************************************************************
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* LOCAL FUNCTIONS
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******************************************************************************
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******************************************************************************
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*/
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/**
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*
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*/
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static void extram_benchmark(void){
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size_t i=0;
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time_measurement_t mem_tmu;
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/* memset speed ext */
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chTMObjectInit(&mem_tmu);
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chTMStartMeasurementX(&mem_tmu);
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memset(extram_start, 0x55, extram_size);
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//memset(extram_start, 0x00, extram_size);
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chTMStopMeasurementX(&mem_tmu);
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memset_speed_ext = 1 / (mem_tmu.cumulative / (double)STM32_SYSCLK);
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/* memset speed int */
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chTMObjectInit(&mem_tmu);
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chTMStartMeasurementX(&mem_tmu);
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for (i=0; i<16; i++)
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memset(extram_check_buf, i, sizeof(extram_check_buf));
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chTMStopMeasurementX(&mem_tmu);
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memset_speed_int = 1 / (mem_tmu.cumulative / (double)STM32_SYSCLK);
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/* memcpy ext2int */
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chTMObjectInit(&mem_tmu);
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chTMStartMeasurementX(&mem_tmu);
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for (i=0; i<16; i++)
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memcpy(extram_check_buf, extram_start+ i * sizeof(extram_check_buf), sizeof(extram_check_buf));
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chTMStopMeasurementX(&mem_tmu);
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memcpy_speed_ext2int = 1 / (mem_tmu.cumulative / (double)STM32_SYSCLK);
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/* memcpy int2ext */
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chTMObjectInit(&mem_tmu);
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memset(extram_check_buf, 0xAA, sizeof(extram_check_buf));
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chTMStartMeasurementX(&mem_tmu);
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for (i=0; i<16; i++)
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memcpy(extram_start + i * sizeof(extram_check_buf), extram_check_buf, sizeof(extram_check_buf));
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chTMStopMeasurementX(&mem_tmu);
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memcpy_speed_int2ext = 1 / (mem_tmu.cumulative / (double)STM32_SYSCLK);
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}
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/**
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*
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*/
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#if USE_INFINITE_MEMTEST
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static void memstest(void){
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while (true) {
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;
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}
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}
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#endif /* USE_INFINITE_MEMTEST */
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/*
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******************************************************************************
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* EXPORTED FUNCTIONS
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******************************************************************************
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*/
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/*
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* Application entry point.
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*/
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int main(void) {
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/*
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* System initializations.
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* - HAL initialization, this also initializes the configured device drivers
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* and performs the board-specific initializations.
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* - Kernel initialization, the main() function becomes a thread and the
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* RTOS is active.
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*/
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halInit();
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chSysInit();
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fsmcSdramInit();
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fsmcSdramStart(&SDRAMD, &sdram_cfg);
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extram_benchmark();
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#if USE_INFINITE_MEMTEST
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memtest();
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#endif
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/*
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* Normal main() thread activity, in this demo it does nothing.
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*/
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while (TRUE) {
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chThdSleepMilliseconds(500);
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}
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}
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