202 lines
6.7 KiB
C
202 lines
6.7 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2021 Stefan Kerkmann
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32F1xx/hal_lld.h
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* @brief STM32F1xx HAL subsystem low level driver header.
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* @pre This module requires the following macros to be defined in the
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* @p board.h file:
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* - GD32_LSECLK.
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* - GD32_LSE_BYPASS (optionally).
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* - GD32_HSECLK.
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* - GD32_HSE_BYPASS (optionally).
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* .
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* One of the following macros must also be defined:
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* - STM32F100xB for Value Line Medium Density devices.
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* - STM32F100xE for Value Line High Density devices.
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* - STM32F101x6, STM32F102x6, STM32F103x6 for Performance
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* Low Density devices.
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* - STM32F101xB, STM32F102xB, STM32F103xB for Performance
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* Medium Density devices.
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* - STM32F101xE, STM32F103xE for Performance High Density devices.
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* - STM32F101xG, STM32F103xG for Performance eXtra Density devices.
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* - STM32F105xC, STM32F107xC for Connectivity Line devices.
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* .
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef HAL_LLD_H
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#define HAL_LLD_H
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name Platform identification
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* @{
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*/
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#if defined(__DOXYGEN__) || \
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defined(GD32VF103TB) || defined(GD32VF103T8) || defined(GD32VF103T6) || defined(GD32VF103T4) || \
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defined(GD32VF103CB) || defined(GD32VF103C8) || defined(GD32VF103C6) || defined(GD32VF103C4) || \
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defined(GD32VF103RB) || defined(GD32VF103R8) || defined(GD32VF103R6) || defined(GD32VF103R4) || \
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defined(GD32VF103VB) || defined(GD32VF103V8)
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#define PLATFORM_NAME "GigaDevice GD32VF103 RISC-V"
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#define GD32VF103
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#else
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#error "unsupported or unrecognized GD32VF103 member"
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#endif
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/**
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* @brief Sub-family identifier.
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*/
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#if !defined(STM32F1XX) || !defined(GD32VF103) || defined(__DOXYGEN__)
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#define STM32F1XX
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#define GD32VF103
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#endif
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/** @} */
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/**
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* @name Internal clock sources
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* @{
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*/
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#define GD32_HSICLK 8000000 /**< High speed internal clock. */
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#define GD32_LSICLK 40000 /**< Low speed internal clock. */
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/** @} */
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/**
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* @name PWR_CR register bits definitions
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* @{
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*/
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#define GD32_PLS_MASK (7 << 5) /**< PLS bits mask. */
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#define GD32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
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#define GD32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
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#define GD32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
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#define GD32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
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#define GD32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
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#define GD32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
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#define GD32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
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#define GD32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
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/** @} */
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief Disables the PWR/RCC initialization in the HAL.
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*/
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#if !defined(GD32_NO_INIT) || defined(__DOXYGEN__)
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#define GD32_NO_INIT FALSE
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#endif
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/**
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* @brief Enables or disables the programmable voltage detector.
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*/
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#if !defined(GD32_PVD_ENABLE) || defined(__DOXYGEN__)
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#define GD32_PVD_ENABLE FALSE
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#endif
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/**
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* @brief Sets voltage level for programmable voltage detector.
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*/
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#if !defined(GD32_PLS) || defined(__DOXYGEN__)
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#define GD32_PLS GD32_PLS_LEV0
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#endif
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/**
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* @brief Enables or disables the HSI clock source.
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*/
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#if !defined(GD32_HSI_ENABLED) || defined(__DOXYGEN__)
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#define GD32_HSI_ENABLED TRUE
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#endif
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/**
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* @brief Enables or disables the LSI clock source.
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*/
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#if !defined(GD32_LSI_ENABLED) || defined(__DOXYGEN__)
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#define GD32_LSI_ENABLED FALSE
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#endif
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/**
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* @brief Enables or disables the HSE clock source.
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*/
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#if !defined(GD32_HSE_ENABLED) || defined(__DOXYGEN__)
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#define GD32_HSE_ENABLED TRUE
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#endif
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/**
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* @brief Enables or disables the LSE clock source.
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*/
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#if !defined(GD32_LSE_ENABLED) || defined(__DOXYGEN__)
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#define GD32_LSE_ENABLED FALSE
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#include "gd32_registry.h"
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#include "stm32f105xc.h"
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#include "hal_lld_f103.h"
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//#include "hal_lld_f105_f107.h"
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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/* Various helpers.*/
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#include "eclic.h"
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#include "gd32_isr.h"
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#include "gd32_dma.h"
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#include "gd32_rcc.h"
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#include "gd32_tim.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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void hal_lld_init(void);
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void gd32_clock_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* HAL_LLD_H */
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/** @} */
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