824 lines
23 KiB
C
824 lines
23 KiB
C
/*
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Copyright (C) 2014..2016 Marco Veeneman
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file TIVA/mac_lld.c
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* @brief MAC Driver subsystem low level driver source.
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*
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* @addtogroup MAC
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* @{
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*/
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#include <string.h>
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#include "hal.h"
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#if HAL_USE_MAC || defined(__DOXYGEN__)
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#include "hal_mii.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#define BUFFER_SIZE ((((TIVA_MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4)
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/* MII divider optimal value.*/
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#if (TIVA_SYSCLK >= 100000000)
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#define MACMIIADDR_CR (0x01 << 2)
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#elif (TIVA_SYSCLK >= 60000000)
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#define MACMIIADDR_CR (0x00 << 2)
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#elif (TIVA_SYSCLK >= 35000000)
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#define MACMIIADDR_CR (0x03 << 2)
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#elif (TIVA_SYSCLK >= 20000000)
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#define MACMIIADDR_CR (0x02 << 2)
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#else
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#error "TIVA_SYSCLK below minimum frequency for ETH operations (20MHz)"
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#endif
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#define EMAC_MIIADDR_MIIW 0x00000002 /* MII Write */
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#define EMAC_MIIADDR_MIIB 0x00000001 /* MII Busy */
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/**
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* @brief Ethernet driver 1.
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*/
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MACDriver ETHD1;
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13,
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0x37, 0x01, 0x10};
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static tiva_eth_rx_descriptor_t rd[TIVA_MAC_RECEIVE_BUFFERS];
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static tiva_eth_tx_descriptor_t td[TIVA_MAC_TRANSMIT_BUFFERS];
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static uint32_t rb[TIVA_MAC_RECEIVE_BUFFERS][BUFFER_SIZE];
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static uint32_t tb[TIVA_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE];
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Writes a PHY register.
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*
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* @param[in] macp pointer to the @p MACDriver object
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* @param[in] reg register number
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* @param[in] value new register value
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*
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* @notapi
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*/
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static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value)
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{
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ETH->MIIDATA = value;
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ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB;
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while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0)
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;
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}
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/**
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* @brief Writes an extended PHY register.
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*
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* @param[in] macp pointer to the @p MACDriver object
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* @param[in] reg register number
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* @param[in] value new register value
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*
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* @notapi
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*/
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static void mii_write_extended(MACDriver *macp, uint32_t reg, uint32_t value)
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{
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mii_write(macp, TIVA_REGCTL, 0x001F);
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mii_write(macp, TIVA_ADDAR, reg);
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mii_write(macp, TIVA_REGCTL, 0x401F);
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mii_write(macp, TIVA_ADDAR, value);
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}
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/**
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* @brief Reads a PHY register.
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*
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* @param[in] macp pointer to the @p MACDriver object
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* @param[in] reg register number
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*
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* @return The PHY register content.
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*
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* @notapi
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*/
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static uint32_t mii_read(MACDriver *macp, uint32_t reg)
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{
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ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB;
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while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0)
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;
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return ETH->MIIDATA;
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}
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/**
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* @brief Reads an extended PHY register.
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*
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* @param[in] macp pointer to the @p MACDriver object
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* @param[in] reg register number
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*
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* @return The extended PHY register content.
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*
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* @notapi
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*/
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static uint32_t mii_read_extended(MACDriver *macp, uint32_t reg)
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{
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mii_write(macp, TIVA_REGCTL, 0x001F);
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mii_write(macp, TIVA_ADDAR, reg);
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mii_write(macp, TIVA_REGCTL, 0x401F);
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return mii_read(macp, TIVA_ADDAR);
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}
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#if !defined(BOARD_PHY_ADDRESS)
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/**
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* @brief PHY address detection.
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*
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* @param[in] macp pointer to the @p MACDriver object
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*/
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static void mii_find_phy(MACDriver *macp)
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{
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uint32_t i;
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#if TIVA_MAC_PHY_TIMEOUT > 0
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rtcnt_t start = chSysGetRealtimeCounterX();
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rtcnt_t timeout = start + MS2RTC(STM32_HCLK,STM32_MAC_PHY_TIMEOUT);
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rtcnt_t time = start;
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while (chSysIsCounterWithinX(time, start, timeout)) {
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#endif
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for (i = 0; i < 31; i++) {
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macp->phyaddr = i << 11;
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ETH->MIIDATA = (i << 6) | MACMIIADDR_CR;
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if ((mii_read(macp, TIVA_ID1) == (BOARD_PHY_ID >> 16)) &&
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((mii_read(macp, TIVA_ID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) {
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return;
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}
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}
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#if TIVA_MAC_PHY_TIMEOUT > 0
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time = chSysGetRealtimeCounterX();
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}
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#endif
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/* Wrong or defective board.*/
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osalSysHalt("MAC failure");
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}
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#endif
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/**
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* @brief MAC address setup.
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*
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* @param[in] p pointer to a six bytes buffer containing the MAC
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* address
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*/
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static void mac_lld_set_address(const uint8_t *p)
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{
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/* MAC address configuration, only a single address comparator is used,
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hash table not used.*/
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ETH->ADDR0H = ((uint32_t)p[5] << 8) |
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((uint32_t)p[4] << 0);
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ETH->ADDR0L = ((uint32_t)p[3] << 24) |
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((uint32_t)p[2] << 16) |
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((uint32_t)p[1] << 8) |
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((uint32_t)p[0] << 0);
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ETH->ADDR1H = 0x0000FFFF;
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ETH->ADDR1L = 0xFFFFFFFF;
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ETH->ADDR2H = 0x0000FFFF;
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ETH->ADDR2L = 0xFFFFFFFF;
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ETH->ADDR3H = 0x0000FFFF;
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ETH->ADDR3L = 0xFFFFFFFF;
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ETH->HASHTBLH = 0;
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ETH->HASHTBLL = 0;
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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CH_IRQ_HANDLER(TIVA_MAC_HANDLER)
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{
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uint32_t dmaris;
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CH_IRQ_PROLOGUE();
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dmaris = ETH->DMARIS;
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ETH->DMARIS = dmaris & 0x0001FFFF; /* Clear status bits.*/
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if (dmaris & (1 << 6)) {
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/* Data Received.*/
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osalSysLockFromISR();
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osalThreadDequeueAllI(ÐD1.rdqueue, MSG_RESET);
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#if MAC_USE_EVENTS
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osalEventBroadcastFlagsI(ÐD1.rdevent, 0);
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#endif
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osalSysUnlockFromISR();
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}
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if (dmaris & (1 << 0)) {
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/* Data Transmitted.*/
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osalSysLockFromISR();
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osalThreadDequeueAllI(ÐD1.tdqueue, MSG_RESET);
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osalSysUnlockFromISR();
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}
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CH_IRQ_EPILOGUE();
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}
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level MAC initialization.
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*
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* @notapi
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*/
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void mac_lld_init(void)
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{
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uint8_t i;
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macObjectInit(ÐD1);
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ETHD1.link_up = false;
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/* Descriptor tables are initialized in chained mode, note that the first
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word is not initialized here but in mac_lld_start().*/
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for (i = 0; i < TIVA_MAC_RECEIVE_BUFFERS; i++) {
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rd[i].rdes1 = TIVA_RDES1_RCH | TIVA_RDES1_RBS1(TIVA_MAC_BUFFERS_SIZE);
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rd[i].rdes2 = (uint32_t)rb[i];
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rd[i].rdes3 = (uint32_t)&rd[(i + 1) % TIVA_MAC_RECEIVE_BUFFERS];
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}
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for (i = 0; i < TIVA_MAC_TRANSMIT_BUFFERS; i++) {
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td[i].tdes1 = 0;
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td[i].tdes2 = (uint32_t)tb[i];
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td[i].tdes3 = (uint32_t)&td[(i + 1) % TIVA_MAC_TRANSMIT_BUFFERS];
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}
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/* Enable MAC clock */
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SYSCTL->RCGCEMAC = 1;
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while (SYSCTL->PREMAC != 0x01)
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;
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/* Set PHYHOLD bit */
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ETH->PC |= 1;
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/* Enable PHY clock */
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SYSCTL->RCGCEPHY = 1;
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while (SYSCTL->PREPHY != 0x01)
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;
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/* Enable power to PHY */
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SYSCTL->PCEPHY |= 1;
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while (SYSCTL->PREPHY != 0x01)
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;
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#if BOARD_PHY_RMII
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ETH->PC = EMAC_PHY_CONFIG | (0x04 << 28);
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#else
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ETH->PC = EMAC_PHY_CONFIG;
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#endif
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/*
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* Write OHY led configuration.
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* 0: link ok
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* 1: tx activity
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* 2: link ok
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* blink rate: 20Hz
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*/
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mii_write_extended(ÐD1, TIVA_LEDCFG, (0 << 8) | (2 << 4) | (0 << 0));
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mii_write(ÐD1, TIVA_LEDCR, (0 << 9));
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/* Set done bit after writing EMACPC register */
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mii_write(ÐD1, TIVA_CFG1, (1 << 15) | mii_read(ÐD1, TIVA_CFG1));
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while(ETH->DMABUSMOD & 1)
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;
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/* Reset MAC */
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ETH->DMABUSMOD |= 1;
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while (ETH->DMABUSMOD & 1)
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;
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/* PHY address setup.*/
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#if defined(BOARD_PHY_ADDRESS)
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ETHD1.phyaddr = BOARD_PHY_ADDRESS << 11;
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#else
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mii_find_phy(ÐD1);
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#endif
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#if defined(BOARD_PHY_RESET)
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/* PHY board-specific reset procedure.*/
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BOARD_PHY_RESET();
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#else
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/* PHY soft reset procedure.*/
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mii_write(ÐD1, MII_BMCR, BMCR_RESET);
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#if defined(BOARD_PHY_RESET_DELAY)
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chSysPolledDelayX(BOARD_PHY_RESET_DELAY);
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#endif
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while (mii_read(ÐD1, MII_BMCR) & BMCR_RESET)
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;
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#endif
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#if TIVA_MAC_CHANGE_PHY_STATE
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/* PHY in power down mode until the driver will be started.*/
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mii_write(ÐD1, MII_BMCR, mii_read(ÐD1, MII_BMCR) | BMCR_PDOWN);
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#endif
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/* Disable MAC clock */
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SYSCTL->RCGCEMAC = 0;
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/* Disable PHY clock */
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SYSCTL->RCGCEPHY = 0;
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}
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/**
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* @brief Configures and activates the MAC peripheral.
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*
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* @param[in] macp pointer to the @p MACDriver object
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*
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* @notapi
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*/
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void mac_lld_start(MACDriver *macp)
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{
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uint8_t i;
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/* Resets the state of all descriptors.*/
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for (i = 0; i < TIVA_MAC_RECEIVE_BUFFERS; i++) {
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rd[i].rdes0 = TIVA_RDES0_OWN;
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}
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macp->rxptr = (tiva_eth_rx_descriptor_t *)rd;
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for (i = 0; i < TIVA_MAC_TRANSMIT_BUFFERS; i++) {
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td[i].tdes0 = TIVA_TDES0_TCH;
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td[i].locked = 0;
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}
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macp->txptr = (tiva_eth_tx_descriptor_t *)td;
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/* Enable MAC clock */
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SYSCTL->RCGCEMAC = 1;
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while (SYSCTL->PREMAC != 0x01)
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;
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/* Enable PHY clock */
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SYSCTL->RCGCEPHY = 1;
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while (!SYSCTL->PREPHY)
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;
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/* ISR vector enabled.*/
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nvicEnableVector(TIVA_MAC_NUMBER, TIVA_MAC_IRQ_PRIORITY);
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#if TIVA_MAC_CHANGE_PHY_STATE
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/* PHY in power up mode.*/
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mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN);
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#endif
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/* MAC configuration.*/
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ETH->FRAMEFLTR = 0;
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ETH->FLOWCTL = 0;
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ETH->VLANTG = 0;
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/* MAC address setup.*/
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if (macp->config->mac_address == NULL)
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mac_lld_set_address(default_mac_address);
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else
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mac_lld_set_address(macp->config->mac_address);
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/* Transmitter and receiver enabled.
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Note that the complete setup of the MAC is performed when the link
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status is detected.*/
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#if TIVA_MAC_IP_CHECKSUM_OFFLOAD
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ETH->CFG = (1 << 10) | (1 << 3) | (1 << 2);
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#else
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ETH->CFG = (1 << 3) | (1 << 2);
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#endif
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/* DMA configuration:
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Descriptor chains pointers.*/
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ETH->RXDLADDR = (uint32_t)rd;
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ETH->TXDLADDR = (uint32_t)td;
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/* Enabling required interrupt sources.*/
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ETH->DMARIS &= 0xFFFF;
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ETH->DMAIM = (1 << 16) | (1 << 6) | (1 << 0);
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/* DMA general settings.*/
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ETH->DMABUSMOD = (1 << 25) | (1 << 17) | (1 << 8);
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/* Transmit FIFO flush.*/
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ETH->DMAOPMODE = (1 << 20);
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while (ETH->DMAOPMODE & (1 << 20))
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;
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/* DMA final configuration and start.*/
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ETH->DMAOPMODE = (1 << 26) | (1 << 25) | (1 << 21) |
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(1 << 13) | (1 << 1);
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}
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/**
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* @brief Deactivates the MAC peripheral.
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*
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* @param[in] macp pointer to the @p MACDriver object
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*
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* @notapi
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*/
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void mac_lld_stop(MACDriver *macp)
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{
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if (macp->state != MAC_STOP) {
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#if TIVA_MAC_CHANGE_PHY_STATE
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/* PHY in power down mode until the driver will be restarted.*/
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mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN);
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#endif
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/* MAC and DMA stopped.*/
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ETH->CFG = 0;
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ETH->DMAOPMODE = 0;
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ETH->DMAIM = 0;
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ETH->DMARIS &= 0xFFFF;
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/* MAC clocks stopped.*/
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SYSCTL->RCGCEMAC = 0;
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/* PHY clock stopped.*/
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SYSCTL->RCGCEPHY = 0;
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/* ISR vector disabled.*/
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nvicDisableVector(TIVA_MAC_NUMBER);
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}
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}
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/**
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* @brief Returns a transmission descriptor.
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* @details One of the available transmission descriptors is locked and
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* returned.
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*
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* @param[in] macp pointer to the @p MACDriver object
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* @param[out] tdp pointer to a @p MACTransmitDescriptor structure
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* @return The operation status.
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* @retval RDY_OK the descriptor has been obtained.
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* @retval RDY_TIMEOUT descriptor not available.
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*
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* @notapi
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*/
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msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
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MACTransmitDescriptor *tdp)
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{
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tiva_eth_tx_descriptor_t *tdes;
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if (!macp->link_up)
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return MSG_TIMEOUT;
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osalSysLock();
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/* Get Current TX descriptor.*/
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tdes = macp->txptr;
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/* Ensure that descriptor isn't owned by the Ethernet DMA or locked by
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another thread.*/
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if (tdes->tdes0 & (TIVA_TDES0_OWN) || (tdes->locked)) {
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osalSysUnlock();
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return MSG_TIMEOUT;
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}
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/* Marks the current descriptor as locked.*/
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tdes->locked = 1;
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/* Next TX descriptor to use.*/
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macp->txptr = (tiva_eth_tx_descriptor_t *)tdes->tdes3;
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osalSysUnlock();
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/* Set the buffer size and configuration.*/
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tdp->offset = 0;
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tdp->size = TIVA_MAC_BUFFERS_SIZE;
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tdp->physdesc = tdes;
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return MSG_OK;
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}
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/**
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* @brief Releases a transmit descriptor and starts the transmission of the
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* enqueued data as a single frame.
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*
|
|
* @param[in] tdp the pointer to the @p MACTransmitDescriptor structure
|
|
*
|
|
* @notapi
|
|
*/
|
|
void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp)
|
|
{
|
|
osalDbgAssert(!(tdp->physdesc->tdes0 & TIVA_TDES0_OWN),
|
|
"attempt to release descriptor already owned by DMA");
|
|
|
|
osalSysLock();
|
|
|
|
/* Unlocks the descriptor and returns it to the DMA engine.*/
|
|
tdp->physdesc->tdes1 = tdp->offset;
|
|
tdp->physdesc->tdes0 = TIVA_TDES0_CIC(TIVA_MAC_IP_CHECKSUM_OFFLOAD) |
|
|
TIVA_TDES0_IC | TIVA_TDES0_LS | TIVA_TDES0_FS |
|
|
TIVA_TDES0_TCH | TIVA_TDES0_OWN;
|
|
tdp->physdesc->locked = 0;
|
|
|
|
/* If the DMA engine is stalled then a restart request is issued.*/
|
|
if ((ETH->DMARIS & (0x7 << 20)) == (6 << 20)) {
|
|
ETH->DMARIS = (1 << 2);
|
|
ETH->TXPOLLD = 1; /* Any value is OK.*/
|
|
}
|
|
|
|
osalSysUnlock();
|
|
}
|
|
|
|
/**
|
|
* @brief Returns a receive descriptor.
|
|
*
|
|
* @param[in] macp pointer to the @p MACDriver object
|
|
* @param[out] rdp pointer to a @p MACReceiveDescriptor structure
|
|
* @return The operation status.
|
|
* @retval RDY_OK the descriptor has been obtained.
|
|
* @retval RDY_TIMEOUT descriptor not available.
|
|
*
|
|
* @notapi
|
|
*/
|
|
msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
|
|
MACReceiveDescriptor *rdp)
|
|
{
|
|
tiva_eth_rx_descriptor_t *rdes;
|
|
|
|
osalSysLock();
|
|
|
|
/* Get Current RX descriptor.*/
|
|
rdes = macp->rxptr;
|
|
|
|
/* Iterates through received frames until a valid one is found, invalid
|
|
frames are discarded.*/
|
|
while (!(rdes->rdes0 & TIVA_RDES0_OWN)) {
|
|
if (!(rdes->rdes0 & (TIVA_RDES0_AFM | TIVA_RDES0_ES))
|
|
#if TIVA_MAC_IP_CHECKSUM_OFFLOAD
|
|
&& (rdes->rdes0 & TIVA_RDES0_FT)
|
|
&& !(rdes->rdes0 & (TIVA_RDES0_IPHCE | TIVA_RDES0_PCE))
|
|
#endif
|
|
&& (rdes->rdes0 & TIVA_RDES0_FS) && (rdes->rdes0 & TIVA_RDES0_LS)) {
|
|
/* Found a valid one.*/
|
|
rdp->offset = 0;
|
|
rdp->size = ((rdes->rdes0 & TIVA_RDES0_FL_MASK) >> 16) - 4;
|
|
rdp->physdesc = rdes;
|
|
macp->rxptr = (tiva_eth_rx_descriptor_t *)rdes->rdes3;
|
|
|
|
osalSysUnlock();
|
|
return MSG_OK;
|
|
}
|
|
/* Invalid frame found, purging.*/
|
|
rdes->rdes0 = TIVA_RDES0_OWN;
|
|
rdes = (tiva_eth_rx_descriptor_t *)rdes->rdes3;
|
|
}
|
|
|
|
/* Next descriptor to check.*/
|
|
macp->rxptr = rdes;
|
|
|
|
osalSysUnlock();
|
|
return MSG_TIMEOUT;
|
|
}
|
|
|
|
/**
|
|
* @brief Releases a receive descriptor.
|
|
* @details The descriptor and its buffer are made available for more incoming
|
|
* frames.
|
|
*
|
|
* @param[in] rdp the pointer to the @p MACReceiveDescriptor structure
|
|
*
|
|
* @notapi
|
|
*/
|
|
void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp)
|
|
{
|
|
osalDbgAssert(!(rdp->physdesc->rdes0 & TIVA_RDES0_OWN),
|
|
"attempt to release descriptor already owned by DMA");
|
|
|
|
osalSysLock();
|
|
|
|
/* Give buffer back to the Ethernet DMA.*/
|
|
rdp->physdesc->rdes0 = TIVA_RDES0_OWN;
|
|
|
|
/* If the DMA engine is stalled then a restart request is issued.*/
|
|
if ((ETH->STATUS & (0xf << 17)) == (4 << 17)) {
|
|
ETH->DMARIS = (1 << 7);
|
|
ETH->TXPOLLD = 1; /* Any value is OK.*/
|
|
}
|
|
|
|
osalSysUnlock();
|
|
}
|
|
|
|
/**
|
|
* @brief Updates and returns the link status.
|
|
*
|
|
* @param[in] macp pointer to the @p MACDriver object
|
|
* @return The link status.
|
|
* @retval TRUE if the link is active.
|
|
* @retval FALSE if the link is down.
|
|
*
|
|
* @notapi
|
|
*/
|
|
bool mac_lld_poll_link_status(MACDriver *macp)
|
|
{
|
|
uint32_t maccfg, bmsr, bmcr;
|
|
|
|
maccfg = ETH->CFG;
|
|
|
|
/* PHY CR and SR registers read.*/
|
|
(void)mii_read(macp, MII_BMSR);
|
|
bmsr = mii_read(macp, MII_BMSR);
|
|
bmcr = mii_read(macp, MII_BMCR);
|
|
|
|
/* Check on auto-negotiation mode.*/
|
|
if (bmcr & BMCR_ANENABLE) {
|
|
uint32_t lpa;
|
|
|
|
/* Auto-negotiation must be finished without faults and link established.*/
|
|
if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) !=
|
|
(BMSR_LSTATUS | BMSR_ANEGCOMPLETE))
|
|
return macp->link_up = false;
|
|
|
|
/* Auto-negotiation enabled, checks the LPA register.*/
|
|
lpa = mii_read(macp, MII_LPA);
|
|
|
|
/* Check on link speed.*/
|
|
if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4))
|
|
maccfg |= (1 << 14);
|
|
else
|
|
maccfg &= ~(1 << 14);
|
|
|
|
/* Check on link mode.*/
|
|
if (lpa & (LPA_10FULL | LPA_100FULL))
|
|
maccfg |= (1 << 11);
|
|
else
|
|
maccfg &= ~(1 << 11);
|
|
}
|
|
else {
|
|
/* Link must be established.*/
|
|
if (!(bmsr & BMSR_LSTATUS))
|
|
return macp->link_up = false;
|
|
|
|
/* Check on link speed.*/
|
|
if (bmcr & BMCR_SPEED100)
|
|
maccfg |= (1 << 14);
|
|
else
|
|
maccfg &= ~(1 << 14);
|
|
|
|
/* Check on link mode.*/
|
|
if (bmcr & BMCR_FULLDPLX)
|
|
maccfg |= (1 << 11);
|
|
else
|
|
maccfg &= ~(1 << 11);
|
|
}
|
|
|
|
/* Changes the mode in the MAC.*/
|
|
ETH->CFG = maccfg;
|
|
|
|
/* Returns the link status.*/
|
|
return macp->link_up = true;
|
|
}
|
|
|
|
/**
|
|
* @brief Writes to a transmit descriptor's stream.
|
|
*
|
|
* @param[in] tdp pointer to a @p MACTransmitDescriptor structure
|
|
* @param[in] buf pointer to the buffer containing the data to be
|
|
* written
|
|
* @param[in] size number of bytes to be written
|
|
* @return The number of bytes written into the descriptor's
|
|
* stream, this value can be less than the amount
|
|
* specified in the parameter @p size if the maximum
|
|
* frame size is reached.
|
|
*
|
|
* @notapi
|
|
*/
|
|
size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
|
|
uint8_t *buf,
|
|
size_t size)
|
|
{
|
|
osalDbgAssert(!(tdp->physdesc->tdes0 & TIVA_TDES0_OWN),
|
|
"attempt to write descriptor already owned by DMA");
|
|
|
|
if (size > tdp->size - tdp->offset)
|
|
size = tdp->size - tdp->offset;
|
|
|
|
if (size > 0) {
|
|
memcpy((uint8_t *)(tdp->physdesc->tdes2) + tdp->offset, buf, size);
|
|
tdp->offset += size;
|
|
}
|
|
return size;
|
|
}
|
|
|
|
/**
|
|
* @brief Reads from a receive descriptor's stream.
|
|
*
|
|
* @param[in] rdp pointer to a @p MACReceiveDescriptor structure
|
|
* @param[in] buf pointer to the buffer that will receive the read data
|
|
* @param[in] size number of bytes to be read
|
|
* @return The number of bytes read from the descriptor's
|
|
* stream, this value can be less than the amount
|
|
* specified in the parameter @p size if there are
|
|
* no more bytes to read.
|
|
*
|
|
* @notapi
|
|
*/
|
|
size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
|
|
uint8_t *buf,
|
|
size_t size)
|
|
{
|
|
osalDbgAssert(!(rdp->physdesc->rdes0 & TIVA_RDES0_OWN),
|
|
"attempt to read descriptor already owned by DMA");
|
|
|
|
if (size > rdp->size - rdp->offset)
|
|
size = rdp->size - rdp->offset;
|
|
|
|
if (size > 0) {
|
|
memcpy(buf, (uint8_t *)(rdp->physdesc->rdes2) + rdp->offset, size);
|
|
rdp->offset += size;
|
|
}
|
|
return size;
|
|
}
|
|
|
|
#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__)
|
|
/**
|
|
* @brief Returns a pointer to the next transmit buffer in the descriptor
|
|
* chain.
|
|
* @note The API guarantees that enough buffers can be requested to fill
|
|
* a whole frame.
|
|
*
|
|
* @param[in] tdp pointer to a @p MACTransmitDescriptor structure
|
|
* @param[in] size size of the requested buffer. Specify the frame size
|
|
* on the first call then scale the value down subtracting
|
|
* the amount of data already copied into the previous
|
|
* buffers.
|
|
* @param[out] sizep pointer to variable receiving the buffer size, it is
|
|
* zero when the last buffer has already been returned.
|
|
* Note that a returned size lower than the amount
|
|
* requested means that more buffers must be requested
|
|
* in order to fill the frame data entirely.
|
|
* @return Pointer to the returned buffer.
|
|
* @retval NULL if the buffer chain has been entirely scanned.
|
|
*
|
|
* @notapi
|
|
*/
|
|
uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp,
|
|
size_t size,
|
|
size_t *sizep)
|
|
{
|
|
if (tdp->offset == 0) {
|
|
*sizep = tdp->size;
|
|
tdp->offset = size;
|
|
return (uint8_t *)tdp->physdesc->tdes2;
|
|
}
|
|
*sizep = 0;
|
|
return NULL;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns a pointer to the next receive buffer in the descriptor
|
|
* chain.
|
|
* @note The API guarantees that the descriptor chain contains a whole
|
|
* frame.
|
|
*
|
|
* @param[in] rdp pointer to a @p MACReceiveDescriptor structure
|
|
* @param[out] sizep pointer to variable receiving the buffer size, it is
|
|
* zero when the last buffer has already been returned.
|
|
* @return Pointer to the returned buffer.
|
|
* @retval NULL if the buffer chain has been entirely scanned.
|
|
*
|
|
* @notapi
|
|
*/
|
|
const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp,
|
|
size_t *sizep)
|
|
{
|
|
if (rdp->size > 0) {
|
|
*sizep = rdp->size;
|
|
rdp->offset = rdp->size;
|
|
rdp->size = 0;
|
|
return (uint8_t *)rdp->physdesc->rdes2;
|
|
}
|
|
*sizep = 0;
|
|
return NULL;
|
|
}
|
|
#endif /* MAC_USE_ZERO_COPY */
|
|
|
|
#endif /* HAL_USE_MAC */
|
|
|
|
/** @} */
|