321 lines
12 KiB
C
321 lines
12 KiB
C
/*
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ChibiOS - Copyright (C) 2021 Stefan Kerkmann
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file GD32VF103/gd32_isr.h
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* @brief GD32VF103 ISR handler header.
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*
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* @addtogroup GD32VF103_ISR
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* @{
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*/
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#ifndef GD32_ISR_H
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#define GD32_ISR_H
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name ISR names and numbers remapping
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* @{
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*/
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/*
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* CAN units.
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*/
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#define GD32_CAN0_TX_HANDLER vector38
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#define GD32_CAN0_RX0_HANDLER vector39
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#define GD32_CAN0_RX1_HANDLER vector40
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#define GD32_CAN0_EWMC_HANDLER vector41
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#define GD32_CAN1_TX_HANDLER vector82
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#define GD32_CAN1_RX0_HANDLER vector83
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#define GD32_CAN1_RX1_HANDLER vector84
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#define GD32_CAN1_EWMC_HANDLER vector85
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#define GD32_CAN0_TX_NUMBER 38
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#define GD32_CAN0_RX0_NUMBER 39
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#define GD32_CAN0_RX1_NUMBER 40
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#define GD32_CAN0_EWMC_NUMBER 41
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#define GD32_CAN1_TX_NUMBER 82
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#define GD32_CAN1_RX0_NUMBER 83
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#define GD32_CAN1_RX1_NUMBER 84
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#define GD32_CAN1_EWMC_NUMBER 85
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/*
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* I2C units.
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*/
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#define GD32_I2C1_EVENT_HANDLER vector50
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#define GD32_I2C1_ERROR_HANDLER vector51
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#define GD32_I2C1_EVENT_NUMBER 50
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#define GD32_I2C1_ERROR_NUMBER 51
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#define GD32_I2C2_EVENT_HANDLER vector52
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#define GD32_I2C2_ERROR_HANDLER vector53
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#define GD32_I2C2_EVENT_NUMBER 52
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#define GD32_I2C2_ERROR_NUMBER 53
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/*
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* TIM units.
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*/
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#define GD32_TIM1_UP_HANDLER vector44
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#define GD32_TIM1_CC_HANDLER vector46
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#define GD32_TIM2_HANDLER vector47
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#define GD32_TIM3_HANDLER vector48
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#define GD32_TIM4_HANDLER vector49
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#define GD32_TIM5_HANDLER vector69
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#define GD32_TIM6_HANDLER vector73
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#define GD32_TIM7_HANDLER vector74
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#define GD32_TIM1_UP_NUMBER 44
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#define GD32_TIM1_CC_NUMBER 46
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#define GD32_TIM2_NUMBER 47
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#define GD32_TIM3_NUMBER 48
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#define GD32_TIM4_NUMBER 49
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#define GD32_TIM5_NUMBER 69
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#define GD32_TIM6_NUMBER 73
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#define GD32_TIM7_NUMBER 74
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/*
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* USART units.
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*/
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#define GD32_USART1_HANDLER vector56
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#define GD32_USART2_HANDLER vector57
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#define GD32_USART3_HANDLER vector58
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#define GD32_UART4_HANDLER vector71
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#define GD32_UART5_HANDLER vector72
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#define GD32_USART1_NUMBER 56
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#define GD32_USART2_NUMBER 57
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#define GD32_USART3_NUMBER 58
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#define GD32_UART4_NUMBER 71
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#define GD32_UART5_NUMBER 72
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/*
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* OTG units.
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*/
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#define GD32_OTG1_HANDLER vector86
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#define GD32_OTG1_NUMBER 86
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/*
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* RTC unit
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*/
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#define GD32_RTC1_HANDLER vector22
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#define GD32_RTC1_NUMBER 22
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief EXTI0 interrupt priority level setting.
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*/
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#if !defined(GD32_IRQ_EXTI0_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_IRQ_EXTI0_PRIORITY 6
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#endif
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/**
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* @brief EXTI1 interrupt priority level setting.
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*/
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#if !defined(GD32_IRQ_EXTI1_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_IRQ_EXTI1_PRIORITY 6
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#endif
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/**
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* @brief EXTI2 interrupt priority level setting.
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*/
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#if !defined(GD32_IRQ_EXTI2_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_IRQ_EXTI2_PRIORITY 6
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#endif
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/**
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* @brief EXTI3 interrupt priority level setting.
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*/
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#if !defined(GD32_IRQ_EXTI3_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_IRQ_EXTI3_PRIORITY 6
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#endif
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/**
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* @brief EXTI4 interrupt priority level setting.
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*/
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#if !defined(GD32_IRQ_EXTI4_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_IRQ_EXTI4_PRIORITY 6
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#endif
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/**
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* @brief EXTI9..5 interrupt priority level setting.
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*/
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#if !defined(GD32_IRQ_EXTI5_9_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_IRQ_EXTI5_9_PRIORITY 6
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#endif
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/**
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* @brief EXTI15..10 interrupt priority level setting.
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*/
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#if !defined(GD32_IRQ_EXTI10_15_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_IRQ_EXTI10_15_PRIORITY 6
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#endif
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/**
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* @brief EXTI16 interrupt priority level setting.
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*/
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#if !defined(GD32_IRQ_EXTI16_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_IRQ_EXTI16_PRIORITY 6
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#endif
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/**
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* @brief EXTI17 interrupt priority level setting.
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*/
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#if !defined(GD32_IRQ_EXTI17_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_IRQ_EXTI17_PRIORITY 6
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#endif
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/**
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* @brief EXTI18 interrupt priority level setting.
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*/
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#if !defined(GD32_IRQ_EXTI18_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_IRQ_EXTI18_PRIORITY 6
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#endif
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/**
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* @brief EXTI19 interrupt priority level setting.
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*/
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#if !defined(GD32_IRQ_EXTI19_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_IRQ_EXTI19_PRIORITY 6
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#endif
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/** @} */
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#define __ECLIC_PRESENT 1
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#include "nmsis_core.h"
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#define ECLIC_TRIGGER_DEFAULT ECLIC_POSTIVE_EDGE_TRIGGER
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#define ECLIC_DMA_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_CAN_CAN1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_CAN_CAN2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_CAN_CAN3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM10_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM11_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM12_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM13_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM14_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM21_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM22_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM5_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM6_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM7_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_GPT_TIM9_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_I2C_I2C1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_I2C_I2C2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_I2C_I2C3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_ICU_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_ICU_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_ICU_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_ICU_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_ICU_TIM5_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_ICU_TIM8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_EXTI0_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_EXTI10_15_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_EXTI1_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_EXTI2_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_EXTI3_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_EXTI4_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_EXTI5_9_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_TIM14_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_TIM15_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_TIM16_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_TIM17_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_TIM1_CC_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_TIM1_UP_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_TIM20_CC_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_TIM20_UP_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_TIM21_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_TIM22_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_TIM2_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_TIM3_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_TIM4_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_TIM5_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_TIM6_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_TIM7_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_TIM8_CC_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_IRQ_TIM8_UP_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_PWM_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_PWM_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_PWM_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_PWM_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_PWM_TIM5_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_PWM_TIM8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_RTC_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_SDC_SDIO_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_SERIAL_UART4_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_SERIAL_UART5_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_SERIAL_UART7_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_SERIAL_UART8_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_SERIAL_USART1_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_SERIAL_USART2_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_SERIAL_USART3_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_SERIAL_USART6_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_UART_UART4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_UART_UART5_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_UART_UART7_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_UART_UART8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_UART_USART1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_UART_USART2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_UART_USART3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_UART_USART6_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_USB_OTG1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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#define GD32_USB_OTG2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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void irqInit(void);
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void irqDeinit(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* GD32_ISR_H */
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/** @} */
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