Stefan Kerkmann b875108cd0 Add R/W memory and instruction barrier after mstatus access ... Fast subsequent reads and writes to the mstatus csr lead to illegal instruction exceptions on the nucleisys bumblee core of the gd32vf103. This behavior only occurred in high load situations e.g. interrupt frequency of 5khz but reliably let to these errors. Adding the instruction and memory barriers solved the problem. There is some negligible performance impact.		2021-04-16 16:10:08 +02:00
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ext	Add Nucleisys NMSIS sources	2021-04-06 13:38:21 +02:00
ports	Add R/W memory and instruction barrier after mstatus access	2021-04-16 16:10:08 +02:00
startup	Add myself to copyright notes :-)	2021-04-06 13:38:23 +02:00