441 lines
17 KiB
C
441 lines
17 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file DMA/gd32_dma.h
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* @brief DMA helper driver header.
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* @note This driver uses the new naming convention used for the STM32F2xx
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* so the "DMA channels" are referred as "DMA streams".
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*
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* @addtogroup GD32_DMA
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* @{
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*/
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#ifndef GD32_DMA_H
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#define GD32_DMA_H
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Total number of DMA streams.
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* @details This is the total number of streams among all the DMA units.
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*/
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#define GD32_DMA_STREAMS (GD32_DMA0_NUM_CHANNELS + \
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GD32_DMA1_NUM_CHANNELS)
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/**
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* @brief Mask of the ISR bits passed to the DMA callback functions.
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*/
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#define GD32_DMA_INTF_MASK 0x0E
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/**
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* @brief Returns the request line associated to the specified stream.
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* @note In some STM32 manuals the request line is named confusingly
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* channel.
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*
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* @param[in] id the unique numeric stream identifier
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* @param[in] c a stream/request association word, one request per
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* nibble
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* @return Returns the request associated to the stream.
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*/
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#define GD32_DMA_GETCHANNEL(id, c) \
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(((uint32_t)(c) >> (((uint32_t)(id) % (uint32_t)GD32_DMA0_NUM_CHANNELS) * 4U)) & 15U)
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/**
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* @brief Checks if a DMA priority is within the valid range.
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* @param[in] prio DMA priority
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*
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* @retval The check result.
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* @retval false invalid DMA priority.
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* @retval true correct DMA priority.
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*/
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#define GD32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U))
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/**
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* @brief Checks if a DMA stream id is within the valid range.
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*
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* @param[in] id DMA stream id
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* @retval The check result.
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* @retval false invalid DMA channel.
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* @retval true correct DMA channel.
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*/
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#define GD32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \
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((id) < GD32_DMA_STREAMS))
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/**
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* @brief Returns an unique numeric identifier for a DMA stream.
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*
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* @param[in] dma the DMA unit number
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* @param[in] stream the stream number
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* @return An unique numeric stream identifier.
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*/
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#define GD32_DMA_STREAM_ID(dma, stream) \
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((((dma)) * GD32_DMA0_NUM_CHANNELS) + ((stream)))
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/**
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* @brief Returns a DMA stream identifier mask.
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*
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*
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* @param[in] dma the DMA unit number
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* @param[in] stream the stream number
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* @return A DMA stream identifier mask.
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*/
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#define GD32_DMA_STREAM_ID_MSK(dma, stream) \
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(1U << GD32_DMA_STREAM_ID(dma, stream))
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/**
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* @brief Checks if a DMA stream unique identifier belongs to a mask.
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*
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* @param[in] id the stream numeric identifier
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* @param[in] mask the stream numeric identifiers mask
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*
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* @retval The check result.
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* @retval false id does not belong to the mask.
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* @retval true id belongs to the mask.
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*/
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#define GD32_DMA_IS_VALID_ID(id, mask) (((1U << (id)) & (mask)))
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/**
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* @name DMA streams identifiers
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* @{
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*/
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/**
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* @brief Returns a pointer to a gd32_dma_stream_t structure.
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*
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* @param[in] id the stream numeric identifier
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* @return A pointer to the gd32_dma_stream_t constant structure
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* associated to the DMA stream.
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*/
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#define GD32_DMA_STREAM(id) (&_gd32_dma_streams[id])
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#define GD32_DMA0_STREAM0 GD32_DMA_STREAM(0)
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#define GD32_DMA0_STREAM1 GD32_DMA_STREAM(1)
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#define GD32_DMA0_STREAM2 GD32_DMA_STREAM(2)
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#define GD32_DMA0_STREAM3 GD32_DMA_STREAM(3)
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#define GD32_DMA0_STREAM4 GD32_DMA_STREAM(4)
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#define GD32_DMA0_STREAM5 GD32_DMA_STREAM(5)
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#define GD32_DMA0_STREAM6 GD32_DMA_STREAM(6)
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#define GD32_DMA1_STREAM0 GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 0)
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#define GD32_DMA1_STREAM1 GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 1)
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#define GD32_DMA1_STREAM2 GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 2)
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#define GD32_DMA1_STREAM3 GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 3)
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#define GD32_DMA1_STREAM4 GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 4)
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/** @} */
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/**
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* @name CR register constants common to all DMA types
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* @{
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*/
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#define GD32_DMA_CTL_RESET_VALUE 0x00000000U
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#define GD32_DMA_CTL_EN DMA_CTL_CHEN
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#define GD32_DMA_CTL_ERRIE DMA_CTL_ERRIE
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#define GD32_DMA_CTL_HTFIE DMA_CTL_HTFIE
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#define GD32_DMA_CTL_FTFIE DMA_CTL_FTFIE
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#define GD32_DMA_CTL_DIR_MASK (DMA_CTL_DIR | DMA_CTL_M2M)
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#define GD32_DMA_CTL_DIR_P2M 0U
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#define GD32_DMA_CTL_DIR_M2P DMA_CTL_DIR
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#define GD32_DMA_CTL_DIR_M2M DMA_CTL_M2M
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#define GD32_DMA_CTL_CMEN DMA_CTL_CMEN
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#define GD32_DMA_CTL_PNAGA DMA_CTL_PNAGA
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#define GD32_DMA_CTL_MNAGA DMA_CTL_MNAGA
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#define GD32_DMA_CTL_PWIDTH_MASK DMA_CTL_PWIDTH
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#define GD32_DMA_CTL_PWIDTH_BYTE 0U
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#define GD32_DMA_CTL_PWIDTH_HWORD DMA_CTL_PWIDTH_0
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#define GD32_DMA_CTL_PWIDTH_WORD DMA_CTL_PWIDTH_1
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#define GD32_DMA_CTL_MWIDTH_MASK DMA_CTL_MWIDTH
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#define GD32_DMA_CTL_MWIDTH_BYTE 0U
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#define GD32_DMA_CTL_MWIDTH_HWORD DMA_CTL_MWIDTH_0
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#define GD32_DMA_CTL_MWIDTH_WORD DMA_CTL_MWIDTH_1
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#define GD32_DMA_CTL_SIZE_MASK (GD32_DMA_CTL_PWIDTH_MASK | \
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GD32_DMA_CTL_MWIDTH_MASK)
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#define GD32_DMA_CTL_PRIO_MASK DMA_CTL_PRIO
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#define GD32_DMA_CTL_PRIO(n) ((n) << 12U)
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/** @} */
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/**
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* @name Request line selector macro
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* @{
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*/
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#define GD32_DMA_CTL_CHSEL_MASK 0U
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#define GD32_DMA_CTL_CHSEL(n) 0U
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/** @} */
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/**
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* @name Status flags passed to the ISR callbacks
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* @{
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*/
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#define GD32_DMA_INTF_FEIF 0U
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#define GD32_DMA_INTF_ERRIF DMA_INTF_ERRIF0
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#define GD32_DMA_INTF_HTFIF DMA_INTF_HTFIF0
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#define GD32_DMA_INTF_FTFIF DMA_INTF_FTFIF0
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if !defined(GD32_DMA0_NUM_CHANNELS)
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#error "GD32_DMA0_NUM_CHANNELS not defined in registry"
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#endif
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#if !defined(GD32_DMA1_NUM_CHANNELS)
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#error "GD32_DMA1_NUM_CHANNELS not defined in registry"
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#endif
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#if (GD32_DMA0_NUM_CHANNELS < 0) || (GD32_DMA0_NUM_CHANNELS > 7)
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#error "unsupported channels configuration"
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#endif
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#if (GD32_DMA1_NUM_CHANNELS < 0) || (GD32_DMA1_NUM_CHANNELS > 5)
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#error "unsupported channels configuration"
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief Type of a DMA callback.
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*
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* @param[in] p parameter for the registered function
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* @param[in] flags pre-shifted content of the ISR register, the bits
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* are aligned to bit zero
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*/
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typedef void (*gd32_dmaisr_t)(void *p, uint32_t flags);
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/**
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* @brief STM32 DMA stream descriptor structure.
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*/
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typedef struct {
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DMA_TypeDef *dma; /**< @brief Associated DMA. */
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DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */
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uint32_t cmask; /**< @brief Mask of streams sharing
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the same ISR. */
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uint8_t dummy; /**< @brief Filler. */
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uint8_t shift; /**< @brief Bit offset in ISR, IFCR
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and CSELR registers. */
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uint8_t selfindex; /**< @brief Index to self in array. */
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uint8_t vector; /**< @brief Associated IRQ vector. */
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} gd32_dma_stream_t;
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @name Macro Functions
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* @{
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*/
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/**
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* @brief Associates a peripheral data register to a DMA stream.
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* @note This function can be invoked in both ISR or thread context.
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* @pre The stream must have been allocated using @p dmaStreamAlloc().
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* @post After use the stream can be released using @p dmaStreamRelease().
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*
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* @param[in] dmastp pointer to a gd32_dma_stream_t structure
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* @param[in] addr value to be written in the PADDR register
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*
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* @special
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*/
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#define dmaStreamSetPeripheral(dmastp, addr) { \
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(dmastp)->channel->PADDR = (uint32_t)(addr); \
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}
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/**
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* @brief Associates a memory destination to a DMA stream.
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* @note This function can be invoked in both ISR or thread context.
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* @pre The stream must have been allocated using @p dmaStreamAlloc().
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* @post After use the stream can be released using @p dmaStreamRelease().
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*
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* @param[in] dmastp pointer to a gd32_dma_stream_t structure
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* @param[in] addr value to be written in the MADDR register
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*
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* @special
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*/
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#define dmaStreamSetMemory0(dmastp, addr) { \
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(dmastp)->channel->MADDR = (uint32_t)(addr); \
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}
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/**
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* @brief Sets the number of transfers to be performed.
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* @note This function can be invoked in both ISR or thread context.
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* @pre The stream must have been allocated using @p dmaStreamAlloc().
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* @post After use the stream can be released using @p dmaStreamRelease().
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*
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* @param[in] dmastp pointer to a gd32_dma_stream_t structure
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* @param[in] size value to be written in the CNT register
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*
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* @special
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*/
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#define dmaStreamSetTransactionSize(dmastp, size) { \
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(dmastp)->channel->CNT = (uint32_t)(size); \
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}
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/**
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* @brief Returns the number of transfers to be performed.
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* @note This function can be invoked in both ISR or thread context.
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* @pre The stream must have been allocated using @p dmaStreamAlloc().
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* @post After use the stream can be released using @p dmaStreamRelease().
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*
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* @param[in] dmastp pointer to a gd32_dma_stream_t structure
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* @return The number of transfers to be performed.
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*
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* @special
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*/
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#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNT))
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/**
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* @brief Programs the stream mode settings.
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* @note This function can be invoked in both ISR or thread context.
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* @pre The stream must have been allocated using @p dmaStreamAlloc().
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* @post After use the stream can be released using @p dmaStreamRelease().
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*
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* @param[in] dmastp pointer to a gd32_dma_stream_t structure
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* @param[in] mode value to be written in the CCR register
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*
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* @special
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*/
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#define dmaStreamSetMode(dmastp, mode) { \
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(dmastp)->channel->CTL = (uint32_t)(mode); \
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}
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/**
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* @brief DMA stream enable.
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* @note This function can be invoked in both ISR or thread context.
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* @pre The stream must have been allocated using @p dmaStreamAlloc().
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* @post After use the stream can be released using @p dmaStreamRelease().
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*
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* @param[in] dmastp pointer to a gd32_dma_stream_t structure
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*
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* @special
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*/
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#define dmaStreamEnable(dmastp) { \
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(dmastp)->channel->CTL |= GD32_DMA_CTL_EN; \
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}
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/**
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* @brief DMA stream disable.
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* @details The function disables the specified stream and then clears any
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* pending interrupt.
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* @note This function can be invoked in both ISR or thread context.
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* @note Interrupts enabling flags are set to zero after this call, see
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* bug 3607518.
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* @pre The stream must have been allocated using @p dmaStreamAlloc().
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* @post After use the stream can be released using @p dmaStreamRelease().
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*
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* @param[in] dmastp pointer to a gd32_dma_stream_t structure
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*
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* @special
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*/
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#define dmaStreamDisable(dmastp) { \
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(dmastp)->channel->CTL &= ~(GD32_DMA_CTL_FTFIE | GD32_DMA_CTL_HTFIE | \
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GD32_DMA_CTL_ERRIE | GD32_DMA_CTL_EN); \
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dmaStreamClearInterrupt(dmastp); \
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}
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/**
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* @brief DMA stream interrupt sources clear.
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* @note This function can be invoked in both ISR or thread context.
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* @pre The stream must have been allocated using @p dmaStreamAlloc().
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* @post After use the stream can be released using @p dmaStreamRelease().
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*
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* @param[in] dmastp pointer to a gd32_dma_stream_t structure
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*
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* @special
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*/
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#define dmaStreamClearInterrupt(dmastp) { \
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(dmastp)->dma->INTC = GD32_DMA_INTF_MASK << (dmastp)->shift; \
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}
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/**
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* @brief Starts a memory to memory operation using the specified stream.
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* @note The default transfer data mode is "byte to byte" but it can be
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* changed by specifying extra options in the @p mode parameter.
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* @pre The stream must have been allocated using @p dmaStreamAlloc().
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* @post After use the stream can be released using @p dmaStreamRelease().
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*
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* @param[in] dmastp pointer to a gd32_dma_stream_t structure
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* @param[in] mode value to be written in the CCR register, this value
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* is implicitly ORed with:
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* - @p GD32_DMA_CTL_MNAGA
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* - @p GD32_DMA_CTL_PNAGA
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* - @p GD32_DMA_CTL_DIR_M2M
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* - @p GD32_DMA_CTL_EN
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* .
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* @param[in] src source address
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* @param[in] dst destination address
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* @param[in] n number of data units to copy
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*/
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#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \
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dmaStreamSetPeripheral(dmastp, src); \
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dmaStreamSetMemory0(dmastp, dst); \
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dmaStreamSetTransactionSize(dmastp, n); \
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dmaStreamSetMode(dmastp, (mode) | \
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GD32_DMA_CTL_MNAGA | GD32_DMA_CTL_PNAGA | \
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GD32_DMA_CTL_DIR_M2M | GD32_DMA_CTL_EN); \
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}
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/**
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* @brief Polled wait for DMA transfer end.
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* @pre The stream must have been allocated using @p dmaStreamAlloc().
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* @post After use the stream can be released using @p dmaStreamRelease().
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*
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* @param[in] dmastp pointer to a gd32_dma_stream_t structure
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*/
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#define dmaWaitCompletion(dmastp) { \
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while ((dmastp)->channel->CNT > 0U) \
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; \
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dmaStreamDisable(dmastp); \
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}
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/** @} */
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if !defined(__DOXYGEN__)
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extern const gd32_dma_stream_t _gd32_dma_streams[GD32_DMA_STREAMS];
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void dmaInit(void);
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const gd32_dma_stream_t *dmaStreamAllocI(uint32_t id,
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uint32_t priority,
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gd32_dmaisr_t func,
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void *param);
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const gd32_dma_stream_t *dmaStreamAlloc(uint32_t id,
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uint32_t priority,
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gd32_dmaisr_t func,
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void *param);
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void dmaStreamFreeI(const gd32_dma_stream_t *dmastp);
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void dmaStreamFree(const gd32_dma_stream_t *dmastp);
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void dmaServeInterrupt(const gd32_dma_stream_t *dmastp);
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#ifdef __cplusplus
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}
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#endif
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#endif /* GD32_DMA_H */
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/** @} */
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