331 lines
12 KiB
C
331 lines
12 KiB
C
/*
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ChibiOS - Copyright (C) 2021 Stefan Kerkmann
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file GD32VF103/gd32_registry.h
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* @brief GD32VF103xx capabilities registry.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef GD32_REGISTRY_H
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#define GD32_REGISTRY_H
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#if defined(GD32VF103TB) || defined(GD32VF103T8)
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#define GD32_HAS_TIM_1234 TRUE
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#define GD32_HAS_USART_01 TRUE
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#define GD32_HAS_I2C_0 TRUE
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#define GD32_HAS_SPI_0 TRUE
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#define GD32_HAS_GPIO_AB TRUE
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#elif defined(GD32VF103T6) || defined(GD32VF103T4)
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#define GD32_HAS_TIM_12 TRUE
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#define GD32_HAS_USART_01 TRUE
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#define GD32_HAS_I2C_0 TRUE
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#define GD32_HAS_SPI_0 TRUE
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#define GD32_HAS_GPIO_AB TRUE
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#elif defined(GD32VF103CB) || defined(GD32VF103C8)
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#define GD32_HAS_TIM_1234 TRUE
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#define GD32_HAS_USART_012 TRUE
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#define GD32_HAS_I2C_01 TRUE
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#define GD32_HAS_SPI_012 TRUE
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#define GD32_HAS_GPIO_AB TRUE
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#elif defined(GD32VF103C6) || defined(GD32VF103C4)
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#define GD32_HAS_TIM_12 TRUE
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#define GD32_HAS_USART_01 TRUE
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#define GD32_HAS_I2C_0 TRUE
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#define GD32_HAS_SPI_0 TRUE
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#define GD32_HAS_GPIO_AB TRUE
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#elif defined(GD32VF103RB) || defined(GD32VF103R8)
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#define GD32_HAS_TIM_1234 TRUE
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#define GD32_HAS_USART_01234 TRUE
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#define GD32_HAS_I2C_01 TRUE
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#define GD32_HAS_SPI_012 TRUE
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#define GD32_HAS_GPIO_ABCD TRUE
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#elif defined(GD32VF103R6) || defined(GD32VF103R4)
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#define GD32_HAS_TIM_12 TRUE
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#define GD32_HAS_USART_01 TRUE
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#define GD32_HAS_I2C_0 TRUE
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#define GD32_HAS_SPI_0 TRUE
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#define GD32_HAS_GPIO_ABCD TRUE
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#elif defined(GD32VF103VB) || defined(GD32VF103V8)
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#define GD32_HAS_TIM_1234 TRUE
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#define GD32_HAS_USART_01234 TRUE
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#define GD32_HAS_I2C_01 TRUE
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#define GD32_HAS_SPI_012 TRUE
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#define GD32_HAS_GPIO_ABCDE TRUE
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#define GD32_HAS_EXMC TRUE
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#else
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#error "unsupported or unrecognized GD32VF103 member"
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#endif
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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#if defined(GD32VF103) || defined(__DOXYGEN__)
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/**
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* @name GD32VF103 family capabilities
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* @{
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*/
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/* ADC attributes.*/
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#define GD32_HAS_ADC0 TRUE
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#define GD32_HAS_ADC1 TRUE
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/* CAN attributes.*/
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#define GD32_HAS_CAN0 TRUE
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#define GD32_HAS_CAN1 TRUE
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#define GD32_CAN_MAX_FILTERS 28
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/* DAC attributes.*/
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#define GD32_HAS_DAC_CH1 TRUE
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#define GD32_DAC_CH1_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
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#define GD32_HAS_DAC_CH2 TRUE
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#define GD32_DAC_CH2_DMA_STREAM GD32_DMA_STREAM_ID(2, 3)
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/* DMA attributes.*/
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#define GD32_DMA0_NUM_CHANNELS 7
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#define GD32_DMA0_CH0_HANDLER vector30
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#define GD32_DMA0_CH1_HANDLER vector31
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#define GD32_DMA0_CH2_HANDLER vector32
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#define GD32_DMA0_CH3_HANDLER vector33
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#define GD32_DMA0_CH4_HANDLER vector34
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#define GD32_DMA0_CH5_HANDLER vector35
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#define GD32_DMA0_CH6_HANDLER vector36
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#define GD32_DMA0_CH0_NUMBER 30
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#define GD32_DMA0_CH1_NUMBER 31
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#define GD32_DMA0_CH2_NUMBER 32
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#define GD32_DMA0_CH3_NUMBER 33
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#define GD32_DMA0_CH4_NUMBER 34
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#define GD32_DMA0_CH5_NUMBER 35
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#define GD32_DMA0_CH6_NUMBER 36
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#define GD32_DMA1_NUM_CHANNELS 5
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#define GD32_DMA1_CH0_HANDLER vector75
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#define GD32_DMA1_CH1_HANDLER vector76
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#define GD32_DMA1_CH2_HANDLER vector77
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#define GD32_DMA1_CH3_HANDLER vector78
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#define GD32_DMA1_CH4_HANDLER vector79
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#define GD32_DMA1_CH0_NUMBER 75
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#define GD32_DMA1_CH1_NUMBER 76
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#define GD32_DMA1_CH2_NUMBER 77
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#define GD32_DMA1_CH3_NUMBER 78
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#define GD32_DMA1_CH4_NUMBER 79
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/* EXTI attributes.*/
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#define GD32_EXTI_NUM_LINES 15
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#define GD32_EXTI_IMR_MASK 0x00000000U
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/* Flash attributes.*/
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#define GD32_FLASH_NUMBER_OF_BANKS 1
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#define GD32_FLASH_SECTOR_SIZE 1024U
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#if !defined(GD32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__)
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#define GD32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/
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#endif
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/* GPIO attributes.*/
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#if GD32_HAS_GPIO_AB || GD32_HAS_GPIO_ABCD || GD32_HAS_GPIO_ABCDE
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#define GD32_HAS_GPIOA TRUE
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#define GD32_HAS_GPIOB TRUE
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#else
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#define GD32_HAS_GPIOA FALSE
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#define GD32_HAS_GPIOB FALSE
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#endif
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#if GD32_HAS_GPIO_ABCD || GD32_HAS_GPIO_ABCDE
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#define GD32_HAS_GPIOC TRUE
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#define GD32_HAS_GPIOD TRUE
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#else
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#define GD32_HAS_GPIOC FALSE
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#define GD32_HAS_GPIOD FALSE
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#endif
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#if GD32_HAS_GPIO_ABCDE
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#define GD32_HAS_GPIOE TRUE
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#else
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#define GD32_HAS_GPIOE FALSE
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#endif
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/* I2C attributes.*/
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#if GD32_HAS_I2C_0 || GD32_HAS_I2C_01
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#define GD32_HAS_I2C0 TRUE
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#define GD32_I2C_I2C0_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 6)
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#define GD32_I2C_I2C0_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 5)
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#else
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#define GD32_HAS_I2C0 FALSE
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#endif
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#if GD32_HAS_I2C_01
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#define GD32_HAS_I2C1 TRUE
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#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 4)
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#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 3)
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#else
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#define GD32_HAS_I2C1 FALSE
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#endif
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/* RTC attributes.*/
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#define GD32_HAS_RTC TRUE
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#define GD32_RTC_HAS_SUBSECONDS TRUE
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#define GD32_RTC_IS_CALENDAR FALSE
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/* SPI attributes.*/
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#if GD32_HAS_SPI_0 || GD32_HAS_SPI_012
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#define GD32_HAS_SPI0 TRUE
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#define GD32_SPI0_SUPPORTS_I2S FALSE
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#define GD32_SPI_SPI0_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 1)
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#define GD32_SPI_SPI0_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 2)
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#else
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#define GD32_HAS_SPI0 FALSE
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#endif
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#if GD32_HAS_SPI_012
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#define GD32_HAS_SPI1 TRUE
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#define GD32_SPI1_SUPPORTS_I2S TRUE
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#define GD32_SPI1_I2S_FULLDUPLEX FALSE
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#define GD32_SPI_SPI1_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 3)
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#define GD32_SPI_SPI1_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 4)
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#define GD32_I2S_SPI1_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 3)
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#define GD32_I2S_SPI1_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 4)
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#define GD32_HAS_SPI2 TRUE
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#define GD32_SPI2_SUPPORTS_I2S TRUE
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#define GD32_SPI2_I2S_FULLDUPLEX FALSE
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#define GD32_SPI_SPI2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 0)
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#define GD32_SPI_SPI2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 1)
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#define GD32_I2S_SPI2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 0)
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#define GD32_I2S_SPI2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 1)
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#else
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#define GD32_HAS_SPI1 FALSE
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#define GD32_HAS_SPI2 FALSE
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#endif
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/* TIM attributes.*/
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#define GD32_TIM_MAX_CHANNELS 4
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#define GD32_HAS_TIM0 TRUE
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#define GD32_TIM0_IS_32BITS FALSE
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#define GD32_TIM0_CHANNELS 4
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#if GD32_HAS_TIM_12 || GD32_HAS_TIM_1234
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#define GD32_HAS_TIM1 TRUE
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#define GD32_TIM1_IS_32BITS FALSE
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#define GD32_TIM1_CHANNELS 4
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#define GD32_HAS_TIM2 TRUE
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#define GD32_TIM2_IS_32BITS FALSE
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#define GD32_TIM2_CHANNELS 4
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#else
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#define GD32_HAS_TIM1 FALSE
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#define GD32_HAS_TIM2 FALSE
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#endif
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#if GD32_HAS_TIM_1234
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#define GD32_HAS_TIM3 TRUE
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#define GD32_TIM3_IS_32BITS FALSE
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#define GD32_TIM3_CHANNELS 4
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#define GD32_HAS_TIM4 TRUE
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#define GD32_TIM4_IS_32BITS FALSE
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#define GD32_TIM4_CHANNELS 4
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#else
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#define GD32_HAS_TIM3 FALSE
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#define GD32_HAS_TIM4 FALSE
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#endif
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#define GD32_HAS_TIM5 TRUE
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#define GD32_TIM5_IS_32BITS FALSE
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#define GD32_TIM5_CHANNELS 0
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#define GD32_HAS_TIM6 TRUE
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#define GD32_TIM6_IS_32BITS FALSE
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#define GD32_TIM6_CHANNELS 0
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/* USART attributes.*/
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#if GD32_HAS_USART_01 || GD32_HAS_USART_012 || GD32_HAS_USART_01234
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#define GD32_HAS_USART0 TRUE
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#define GD32_UART_USART0_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 4)
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#define GD32_UART_USART0_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 3)
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#define GD32_HAS_USART1 TRUE
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#define GD32_UART_USART1_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 5)
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#define GD32_UART_USART1_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 6)
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#else
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#define GD32_HAS_USART0 FALSE
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#define GD32_HAS_USART1 FALSE
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#endif
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#if GD32_HAS_USART_012 || GD32_HAS_USART_01234
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#define GD32_HAS_USART2 TRUE
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#define GD32_UART_USART2_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 2)
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#define GD32_UART_USART2_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 1)
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#else
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#define GD32_HAS_USART2 FALSE
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#endif
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#if GD32_HAS_USART_01234
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#define GD32_HAS_UART3 TRUE
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#define GD32_UART_UART3_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
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#define GD32_UART_UART3_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
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#define GD32_HAS_UART4 TRUE
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#else
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#define GD32_HAS_UART3 FALSE
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#define GD32_HAS_UART4 FALSE
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#endif
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/* USB attributes.*/
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#define GD32_HAS_USBFS TRUE
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#define GD32_USBFS_ENDPOINTS 3
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#define GD32_HAS_USB TRUE
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/* FWDGT attributes.*/
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#define GD32_HAS_FWDGT TRUE
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/* EXMC attributes.*/
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#if GD32_HAS_EXMC
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#define GD32_HAS_EXMC TRUE
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#else
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#define GD32_HAS_EXMC FALSE
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#endif
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/* CRC attributes.*/
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#define GD32_HAS_CRC TRUE
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#define GD32_CRC_PROGRAMMABLE FALSE
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#endif
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/** @} */
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#endif /* GD32_REGISTRY_H */
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/** @} */
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