555 lines
16 KiB
C
555 lines
16 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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Rewritten by Emil Fresk (1/5 - 2014) for extended input capture
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functionality. And fix for spurious callbacks in the interrupt handler.
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*/
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/*
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Improved by Uladzimir Pylinsky aka barthess (1/3 - 2015) for support of
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32-bit timers and timers with single capture/compare channels.
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*/
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#ifndef __EICU_LLD_H
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#define __EICU_LLD_H
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#include "stm32_tim.h"
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#if (HAL_USE_EICU = TRUE) || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief EICUD1 driver enable switch.
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* @details If set to @p TRUE the support for EICUD1 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_EICU_USE_TIM1) || defined(__DOXYGEN__)
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#define STM32_EICU_USE_TIM1 FALSE
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#endif
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/**
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* @brief EICUD2 driver enable switch.
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* @details If set to @p TRUE the support for EICUD2 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_EICU_USE_TIM2) || defined(__DOXYGEN__)
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#define STM32_EICU_USE_TIM2 FALSE
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#endif
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/**
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* @brief EICUD3 driver enable switch.
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* @details If set to @p TRUE the support for EICUD3 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_EICU_USE_TIM3) || defined(__DOXYGEN__)
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#define STM32_EICU_USE_TIM3 FALSE
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#endif
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/**
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* @brief EICUD4 driver enable switch.
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* @details If set to @p TRUE the support for EICUD4 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_EICU_USE_TIM4) || defined(__DOXYGEN__)
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#define STM32_EICU_USE_TIM4 FALSE
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#endif
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/**
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* @brief EICUD5 driver enable switch.
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* @details If set to @p TRUE the support for EICUD5 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_EICU_USE_TIM5) || defined(__DOXYGEN__)
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#define STM32_EICU_USE_TIM5 FALSE
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#endif
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/**
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* @brief EICUD8 driver enable switch.
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* @details If set to @p TRUE the support for EICUD8 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_EICU_USE_TIM8) || defined(__DOXYGEN__)
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#define STM32_EICU_USE_TIM8 FALSE
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#endif
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/**
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* @brief EICUD9 driver enable switch.
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* @details If set to @p TRUE the support for EICUD9 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_EICU_USE_TIM9) || defined(__DOXYGEN__)
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#define STM32_EICU_USE_TIM9 FALSE
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#endif
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/**
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* @brief EICUD12 driver enable switch.
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* @details If set to @p TRUE the support for EICUD12 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_EICU_USE_TIM12) || defined(__DOXYGEN__)
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#define STM32_EICU_USE_TIM12 FALSE
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#endif
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/**
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* @brief EICUD1 interrupt priority level setting.
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*/
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#if !defined(STM32_EICU_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EICU_TIM1_IRQ_PRIORITY 7
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#endif
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/**
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* @brief EICUD2 interrupt priority level setting.
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*/
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#if !defined(STM32_EICU_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EICU_TIM2_IRQ_PRIORITY 7
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#endif
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/**
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* @brief EICUD3 interrupt priority level setting.
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*/
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#if !defined(STM32_EICU_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EICU_TIM3_IRQ_PRIORITY 7
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#endif
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/**
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* @brief EICUD4 interrupt priority level setting.
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*/
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#if !defined(STM32_EICU_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EICU_TIM4_IRQ_PRIORITY 7
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#endif
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/**
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* @brief EICUD5 interrupt priority level setting.
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*/
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#if !defined(STM32_EICU_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EICU_TIM5_IRQ_PRIORITY 7
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#endif
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/**
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* @brief EICUD8 interrupt priority level setting.
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*/
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#if !defined(STM32_EICU_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EICU_TIM8_IRQ_PRIORITY 7
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#endif
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/**
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* @brief EICUD9 interrupt priority level setting.
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*/
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#if !defined(STM32_EICU_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EICU_TIM9_IRQ_PRIORITY 7
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#endif
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/**
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* @brief EICUD12 interrupt priority level setting.
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*/
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#if !defined(STM32_EICU_TIM12_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EICU_TIM12_IRQ_PRIORITY 7
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#endif
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/**
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* @brief EICUD10 interrupt priority level setting.
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*/
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#if !defined(STM32_EICU_TIM10_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EICU_TIM10_IRQ_PRIORITY 7
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#endif
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/**
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* @brief EICUD11 interrupt priority level setting.
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*/
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#if !defined(STM32_EICU_TIM11_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EICU_TIM11_IRQ_PRIORITY 7
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#endif
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/**
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* @brief EICUD13 interrupt priority level setting.
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*/
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#if !defined(STM32_EICU_TIM13_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EICU_TIM13_IRQ_PRIORITY 7
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#endif
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/**
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* @brief EICUD14 interrupt priority level setting.
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*/
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#if !defined(STM32_EICU_TIM14_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EICU_TIM14_IRQ_PRIORITY 7
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if STM32_EICU_USE_TIM1 && !STM32_HAS_TIM1
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#error "TIM1 not present in the selected device"
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#endif
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#if STM32_EICU_USE_TIM2 && !STM32_HAS_TIM2
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#error "TIM2 not present in the selected device"
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#endif
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#if STM32_EICU_USE_TIM3 && !STM32_HAS_TIM3
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#error "TIM3 not present in the selected device"
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#endif
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#if STM32_EICU_USE_TIM4 && !STM32_HAS_TIM4
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#error "TIM4 not present in the selected device"
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#endif
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#if STM32_EICU_USE_TIM5 && !STM32_HAS_TIM5
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#error "TIM5 not present in the selected device"
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#endif
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#if STM32_EICU_USE_TIM8 && !STM32_HAS_TIM8
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#error "TIM8 not present in the selected device"
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#endif
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#if STM32_EICU_USE_TIM9 && !STM32_HAS_TIM9
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#error "TIM9 not present in the selected device"
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#endif
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#if STM32_EICU_USE_TIM12 && !STM32_HAS_TIM12
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#error "TIM12 not present in the selected device"
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#endif
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#if STM32_EICU_USE_TIM10 && !STM32_HAS_TIM10
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#error "TIM10 not present in the selected device"
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#endif
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#if STM32_EICU_USE_TIM11 && !STM32_HAS_TIM11
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#error "TIM11 not present in the selected device"
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#endif
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#if STM32_EICU_USE_TIM13 && !STM32_HAS_TIM13
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#error "TIM13 not present in the selected device"
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#endif
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#if STM32_EICU_USE_TIM14 && !STM32_HAS_TIM14
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#error "TIM14 not present in the selected device"
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#endif
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#if !STM32_EICU_USE_TIM1 && !STM32_EICU_USE_TIM2 && \
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!STM32_EICU_USE_TIM3 && !STM32_EICU_USE_TIM4 && \
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!STM32_EICU_USE_TIM5 && !STM32_EICU_USE_TIM8 && \
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!STM32_EICU_USE_TIM9 && !STM32_EICU_USE_TIM12 && \
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!STM32_EICU_USE_TIM10 && !STM32_EICU_USE_TIM11 && \
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!STM32_EICU_USE_TIM13 && !STM32_EICU_USE_TIM14
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#error "EICU driver activated but no TIM peripheral assigned"
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#endif
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#if STM32_EICU_USE_TIM1 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM1_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM1"
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#endif
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#if STM32_EICU_USE_TIM2 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM2_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM2"
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#endif
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#if STM32_EICU_USE_TIM3 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM3_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM3"
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#endif
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#if STM32_EICU_USE_TIM4 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM4_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM4"
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#endif
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#if STM32_EICU_USE_TIM5 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM5_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM5"
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#endif
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#if STM32_EICU_USE_TIM8 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM8_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM8"
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#endif
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#if STM32_EICU_USE_TIM9 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM9_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM9"
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#endif
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#if STM32_EICU_USE_TIM12 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM12_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM12"
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#endif
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#if STM32_EICU_USE_TIM10 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM10_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM10"
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#endif
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#if STM32_EICU_USE_TIM11 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM11_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM11"
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#endif
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#if STM32_EICU_USE_TIM13 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM13_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM13"
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#endif
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#if STM32_EICU_USE_TIM14 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_EICU_TIM14_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM14"
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief Active level selector.
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*/
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typedef enum {
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EICU_INPUT_ACTIVE_HIGH, /**< Trigger on rising edge. */
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EICU_INPUT_ACTIVE_LOW, /**< Trigger on falling edge. */
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} eicuactivelevel_t;
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/**
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* @brief Input type selector.
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*/
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typedef enum {
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/**
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* @brief Measures time between consequent edges.
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* @details Callback fires on every _active_ edge.
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*/
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EICU_INPUT_EDGE,
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/**
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* @brief Measures pulse width.
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* @details Callback fires on _idle_ edge of pulse.
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*/
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EICU_INPUT_PULSE,
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/**
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* @brief Measures both period and width..
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* @details Callback fires on _active_ edge of pulse.
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*/
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EICU_INPUT_BOTH
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} eicucapturemode_t;
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/**
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* @brief Timer registers width in bits.
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*/
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typedef enum {
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EICU_WIDTH_16,
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EICU_WIDTH_32
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} eicutimerwidth_t;
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/**
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* @brief EICU frequency type.
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*/
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typedef uint32_t eicufreq_t;
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/**
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* @brief EICU counter type.
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*/
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typedef uint32_t eicucnt_t;
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/**
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* @brief EICU captured width and (or) period.
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*/
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typedef struct {
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/**
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* @brief Pulse width.
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*/
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eicucnt_t width;
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/**
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* @brief Pulse period.
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*/
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eicucnt_t period;
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} eicuresult_t;
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/**
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* @brief EICU Capture Channel Config structure definition.
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*/
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typedef struct {
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/**
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* @brief Specifies the active level of the input signal.
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*/
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eicuactivelevel_t alvl;
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/**
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* @brief Specifies the channel capture mode.
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*/
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eicucapturemode_t mode;
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/**
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* @brief Capture event callback. Used for PWM width, pulse width and
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* pulse period capture event.
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*/
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eicucallback_t capture_cb;
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} EICUChannelConfig;
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/**
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* @brief EICU Capture Channel structure definition.
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*/
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typedef struct {
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/**
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* @brief Channel state for the internal state machine.
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*/
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eicuchannelstate_t state;
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/**
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* @brief Cached value for pulse width calculation.
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*/
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eicucnt_t last_active;
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/**
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* @brief Cached value for period calculation.
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*/
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eicucnt_t last_idle;
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/**
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* @brief Pointer to Input Capture channel configuration.
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*/
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const EICUChannelConfig *config;
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/**
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* @brief CCR register pointer for faster access.
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*/
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volatile uint32_t *ccrp;
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} EICUChannel;
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/**
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* @brief EICU Config structure definition.
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*/
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typedef struct {
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/**
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* @brief Specifies the Timer clock in Hz.
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*/
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eicufreq_t frequency;
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/**
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* @brief Pointer to each Input Capture channel configuration.
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* @note A NULL parameter indicates the channel as unused.
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* @note In PWM mode, only Channel 1 OR Channel 2 may be used.
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*/
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const EICUChannelConfig *iccfgp[EICU_CHANNEL_ENUM_END];
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/**
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* @brief TIM DIER register initialization data.
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*/
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uint32_t dier;
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} EICUConfig;
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/**
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* @brief EICU Driver structure definition
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*/
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struct EICUDriver {
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/**
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* @brief STM32 timer peripheral for Input Capture.
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*/
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stm32_tim_t *tim;
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/**
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* @brief Driver state for the internal state machine.
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*/
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eicustate_t state;
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/**
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* @brief Channels' data structures.
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*/
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EICUChannel channel[EICU_CHANNEL_ENUM_END];
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/**
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* @brief Timer base clock.
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*/
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uint32_t clock;
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/**
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* @brief Number of available capture compare channels in timer.
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*/
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size_t channels;
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/**
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* @brief Timer registers width in bits.
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*/
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eicutimerwidth_t width;
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/**
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* @brief Pointer to configuration for the driver.
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*/
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const EICUConfig *config;
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};
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if STM32_EICU_USE_TIM1 && !defined(__DOXYGEN__)
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extern EICUDriver EICUD1;
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#endif
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#if STM32_EICU_USE_TIM2 && !defined(__DOXYGEN__)
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extern EICUDriver EICUD2;
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#endif
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#if STM32_EICU_USE_TIM3 && !defined(__DOXYGEN__)
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extern EICUDriver EICUD3;
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#endif
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#if STM32_EICU_USE_TIM4 && !defined(__DOXYGEN__)
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extern EICUDriver EICUD4;
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#endif
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#if STM32_EICU_USE_TIM5 && !defined(__DOXYGEN__)
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extern EICUDriver EICUD5;
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#endif
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#if STM32_EICU_USE_TIM8 && !defined(__DOXYGEN__)
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extern EICUDriver EICUD8;
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#endif
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#if STM32_EICU_USE_TIM9 && !defined(__DOXYGEN__)
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extern EICUDriver EICUD9;
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#endif
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#if STM32_EICU_USE_TIM12 && !defined(__DOXYGEN__)
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extern EICUDriver EICUD12;
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#endif
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#if STM32_EICU_USE_TIM10 && !defined(__DOXYGEN__)
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extern EICUDriver EICUD10;
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#endif
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#if STM32_EICU_USE_TIM11 && !defined(__DOXYGEN__)
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extern EICUDriver EICUD11;
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#endif
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#if STM32_EICU_USE_TIM13 && !defined(__DOXYGEN__)
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extern EICUDriver EICUD13;
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#endif
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#if STM32_EICU_USE_TIM14 && !defined(__DOXYGEN__)
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extern EICUDriver EICUD14;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void eicu_lld_init(void);
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void eicu_lld_start(EICUDriver *eicup);
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void eicu_lld_stop(EICUDriver *eicup);
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void eicu_lld_enable(EICUDriver *eicup);
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void eicu_lld_disable(EICUDriver *eicup);
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#ifdef __cplusplus
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}
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#endif
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#endif /* HAL_USE_EICU */
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#endif /* __EICU_LLD_H */
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