ChibiOS-Contrib/os
Stefan Kerkmann b875108cd0 Add R/W memory and instruction barrier after mstatus access
Fast subsequent reads and writes to the mstatus csr lead to
illegal instruction exceptions on the nucleisys bumblee core
of the gd32vf103. This behavior only occurred in high load
situations e.g. interrupt frequency of 5khz but reliably let
to these errors.  Adding the instruction and memory barriers solved
the problem. There is some negligible performance impact.
2021-04-16 16:10:08 +02:00
..
common Add R/W memory and instruction barrier after mstatus access 2021-04-16 16:10:08 +02:00
hal Merge branch 'chibios-20.3.x' into nuc123-efl-fix 2021-04-08 20:17:24 +09:00
various fix Segger Sysview bindings 2021-02-14 13:12:05 +01:00
.keep Added 'demos' and 'os' subdirectories 2014-10-05 14:27:49 +03:00