245 lines
9.8 KiB
C
245 lines
9.8 KiB
C
/*
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Copyright (C) 2019 /u/KeepItUnder
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file NUC123/nuc123_registry.h
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* @brief NUC123 capabilities registry.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef NUC123_REGISTRY_H
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#define NUC123_REGISTRY_H
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/**
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* @name NUC123 capabilities
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* @{
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*/
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/* RCC attributes. */
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#define NUC123_HAS_HSI48 FALSE
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#define NUC123_HAS_HSI_PREDIV FALSE
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#define NUC123_HAS_MCO_PREDIV TRUE
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/* ADC attributes.*/
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#define NUC123_HAS_ADC1 TRUE
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#define NUC123_ADC_SUPPORTS_PRESCALER FALSE
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#define NUC123_ADC_SUPPORTS_OVERSAMPLING FALSE
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#define NUC123_ADC1_IRQ_SHARED_WITH_EXTI FALSE
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#define NUC123_ADC1_HANDLER Vector70
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#define NUC123_ADC1_NUMBER Vector70_IRQn
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#define NUC123_ADC1_DMA_MSK (NUC123_DMA_STREAM_ID_MSK(1, 1) |\
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NUC123_DMA_STREAM_ID_MSK(1, 2))
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#define NUC123_ADC1_DMA_CHN 0x00000011
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#define NUC123_HAS_ADC2 FALSE
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#define NUC123_HAS_ADC3 FALSE
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#define NUC123_HAS_ADC4 FALSE
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/* CAN attributes.*/
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#define NUC123_HAS_CAN1 FALSE
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#define NUC123_HAS_CAN2 FALSE
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#define NUC123_HAS_CAN3 FALSE
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/* DAC attributes.*/
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#define NUC123_HAS_DAC1_CH1 FALSE
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#define NUC123_HAS_DAC1_CH2 FALSE
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#define NUC123_HAS_DAC2_CH1 FALSE
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#define NUC123_HAS_DAC2_CH2 FALSE
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/* DMA attributes.*/
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#define NUC123_ADVANCED_DMA FALSE
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#define NUC123_DMA_SUPPORTS_CSELR FALSE
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#define NUC123_DMA1_NUM_CHANNELS 6
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#define NUC123_DMA2_NUM_CHANNELS 0
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#define NUC123_DMA1_CH1_HANDLER Vector64
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#define NUC123_DMA1_CH23_HANDLER Vector68
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#define NUC123_DMA1_CH4567_HANDLER Vector6C
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#define NUC123_DMA1_CH1_NUMBER Vector64_IRQn
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#define NUC123_DMA1_CH23_NUMBER Vector68_IRQn
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#define NUC123_DMA1_CH4567_NUMBER Vector6C_IRQn
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#define NUC123_DMA1_CH2_NUMBER NUC123_DMA1_CH23_NUMBER
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#define NUC123_DMA1_CH3_NUMBER NUC123_DMA1_CH23_NUMBER
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#define DMA1_CH2_CMASK 0x00000006U
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#define DMA1_CH3_CMASK 0x00000006U
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#define NUC123_DMA1_CH4_NUMBER NUC123_DMA1_CH4567_NUMBER
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#define NUC123_DMA1_CH5_NUMBER NUC123_DMA1_CH4567_NUMBER
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#define NUC123_DMA1_CH6_NUMBER NUC123_DMA1_CH4567_NUMBER
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#define NUC123_DMA1_CH7_NUMBER NUC123_DMA1_CH4567_NUMBER
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#define DMA1_CH4_CMASK 0x00000078U
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#define DMA1_CH5_CMASK 0x00000078U
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#define DMA1_CH6_CMASK 0x00000078U
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#define DMA1_CH7_CMASK 0x00000078U
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/* ETH attributes.*/
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#define NUC123_HAS_ETH FALSE
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/* EXTI attributes.*/
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/* #define NUC123_EXTI_NUM_LINES 20 */
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/* #define NUC123_EXTI_IMR_MASK 0xFFF50000U */
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/* GPIO attributes.*/
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#define NUC123_HAS_GPIOA TRUE
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#define NUC123_HAS_GPIOB TRUE
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#define NUC123_HAS_GPIOC TRUE
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#define NUC123_HAS_GPIOD TRUE
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#define NUC123_HAS_GPIOE FALSE
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#define NUC123_HAS_GPIOF TRUE
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#define NUC123_HAS_GPIOG FALSE
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#define NUC123_HAS_GPIOH FALSE
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#define NUC123_HAS_GPIOI FALSE
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#define NUC123_HAS_GPIOJ FALSE
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#define NUC123_HAS_GPIOK FALSE
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/* I2C attributes.*/
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#define NUC123_HAS_I2C0 TRUE
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#define NUC123_HAS_I2C1 TRUE
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/* QUADSPI attributes.*/
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#define NUC123_HAS_QUADSPI1 FALSE
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/* RTC attributes.*/
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#define NUC123_HAS_RTC FALSE
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#define NUC123_RTC_HAS_SUBSECONDS FALSE
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#define NUC123_RTC_HAS_PERIODIC_WAKEUPS FALSE
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#define NUC123_RTC_NUM_ALARMS 0
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#define NUC123_RTC_HAS_INTERRUPTS FALSE
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/* SDIO attributes.*/
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#define NUC123_HAS_SDIO FALSE
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/* SPI attributes.*/
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#define NUC123_HAS_SPI1 TRUE
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#define NUC123_SPI1_SUPPORTS_I2S FALSE
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#define NUC123_SPI1_RX_DMA_MSK NUC123_DMA_STREAM_ID_MSK(1, 2)
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#define NUC123_SPI1_RX_DMA_CHN 0x00000030
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#define NUC123_SPI1_TX_DMA_MSK NUC123_DMA_STREAM_ID_MSK(1, 3)
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#define NUC123_SPI1_TX_DMA_CHN 0x00000300
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#define NUC123_HAS_SPI2 TRUE
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#define NUC123_SPI2_SUPPORTS_I2S FALSE
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#define NUC123_SPI2_RX_DMA_MSK NUC123_DMA_STREAM_ID_MSK(1, 4)
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#define NUC123_SPI2_RX_DMA_CHN 0x00003000
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#define NUC123_SPI2_TX_DMA_MSK NUC123_DMA_STREAM_ID_MSK(1, 5)
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#define NUC123_SPI2_TX_DMA_CHN 0x00030000
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#define NUC123_HAS_SPI3 FALSE
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#define NUC123_HAS_SPI4 FALSE
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#define NUC123_HAS_SPI5 FALSE
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#define NUC123_HAS_SPI6 FALSE
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/* TIM attributes.*/
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#define NUC123_TIM_MAX_CHANNELS 4
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#define NUC123_HAS_TIM1 TRUE
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#define NUC123_TIM1_IS_32BITS TRUE
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#define NUC123_TIM1_CHANNELS 1
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#define NUC123_HAS_TIM2 TRUE
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#define NUC123_TIM2_IS_32BITS TRUE
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#define NUC123_TIM2_CHANNELS 1
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#define NUC123_HAS_TIM3 TRUE
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#define NUC123_TIM3_IS_32BITS TRUE
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#define NUC123_TIM3_CHANNELS 1
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#define NUC123_HAS_TIM4 TRUE
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#define NUC123_TIM14_IS_32BITS TRUE
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#define NUC123_TIM14_CHANNELS 1
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#define NUC123_HAS_TIM5 FALSE
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#define NUC123_HAS_TIM6 FALSE
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#define NUC123_HAS_TIM7 FALSE
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#define NUC123_HAS_TIM8 FALSE
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#define NUC123_HAS_TIM9 FALSE
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#define NUC123_HAS_TIM10 FALSE
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#define NUC123_HAS_TIM11 FALSE
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#define NUC123_HAS_TIM12 FALSE
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#define NUC123_HAS_TIM13 FALSE
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#define NUC123_HAS_TIM14 FALSE
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#define NUC123_HAS_TIM15 FALSE
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#define NUC123_HAS_TIM16 FALSE
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#define NUC123_HAS_TIM17 FALSE
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#define NUC123_HAS_TIM18 FALSE
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#define NUC123_HAS_TIM19 FALSE
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#define NUC123_HAS_TIM20 FALSE
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#define NUC123_HAS_TIM21 FALSE
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#define NUC123_HAS_TIM22 FALSE
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/* USART attributes.*/
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/* #define NUC123_HAS_USART1 TRUE
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#define NUC123_USART1_RX_DMA_MSK (NUC123_DMA_STREAM_ID_MSK(1, 1) |\
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NUC123_DMA_STREAM_ID_MSK(1, 3) |\
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NUC123_DMA_STREAM_ID_MSK(1, 5))
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#define NUC123_USART1_RX_DMA_CHN 0x00080808
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#define NUC123_USART1_TX_DMA_MSK (NUC123_DMA_STREAM_ID_MSK(1, 2) |\
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NUC123_DMA_STREAM_ID_MSK(1, 4))
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#define NUC123_USART1_TX_DMA_CHN 0x00008080
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#define NUC123_HAS_USART2 TRUE
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#define NUC123_USART2_RX_DMA_MSK (NUC123_DMA_STREAM_ID_MSK(1, 1) |\
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NUC123_DMA_STREAM_ID_MSK(1, 3) |\
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NUC123_DMA_STREAM_ID_MSK(1, 5))
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#define NUC123_USART2_RX_DMA_CHN 0x00090909
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#define NUC123_USART2_TX_DMA_MSK (NUC123_DMA_STREAM_ID_MSK(1, 2) |\
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NUC123_DMA_STREAM_ID_MSK(1, 4))
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#define NUC123_USART2_TX_DMA_CHN 0x00009090 */
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#define NUC123_HAS_USART1 FALSE
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#define NUC123_HAS_USART2 FALSE
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#define NUC123_HAS_USART3 FALSE
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#define NUC123_HAS_UART4 FALSE
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#define NUC123_HAS_UART5 FALSE
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#define NUC123_HAS_USART6 FALSE
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#define NUC123_HAS_UART7 FALSE
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#define NUC123_HAS_UART8 FALSE
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#define NUC123_HAS_LPUART1 FALSE
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/* USB attributes.*/
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#define NUC123_HAS_USB TRUE
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#define NUC123_HAS_OTG1 FALSE
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#define NUC123_HAS_OTG2 FALSE
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/* IWDG attributes.*/
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#define NUC123_HAS_IWDG TRUE
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#define NUC123_IWDG_IS_WINDOWED TRUE
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/* LTDC attributes.*/
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#define NUC123_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define NUC123_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define NUC123_HAS_FSMC FALSE
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/* CRC attributes.*/
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#define NUC123_HAS_CRC TRUE
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#define NUC123_CRC_PROGRAMMABLE FALSE
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/** @} */
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#endif /* NUC123_REGISTRY_H */
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/** @} */
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