299 lines
7.6 KiB
C
299 lines
7.6 KiB
C
/******************************************************************************
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* @file system_SN32F290.c
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* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File
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* for the SONIX SN32F790 Devices
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* @version V0.0.5
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* @date 2018/06/14
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*
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* @note
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* Copyright (C) 2016-2017 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#include <stdint.h>
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#include <system_SN32F2xx.h>
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#include <mcuconf.h>
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/*
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//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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*/
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/*--------------------- Clock Configuration ----------------------------------
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//
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// <o0.0..2> SYSCLKSEL (SYS0_CLKCFG)
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// <0=> IHRC
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// <1=> ILRC
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// <2=> EHS X'TAL
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// <3=> ELS X'TAL
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// <4=> PLL
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//
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// <o1> EHS Source Frequency (MHz)
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// <10-25>
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//
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//<e2> PLL ENABLE
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// <h> PLL Control Register (SYS0_PLLCTRL)
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// <i> F_CLKOUT = F_VCO / P = (F_CLKIN * M) / P
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// <i> 10 MHz <= F_CLKIN <= 25 MHz
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// <i> 96 MHz <= (F_CLKIN * M) <= 144 MHz
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// <o3> MSEL
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// <0=> M = 4
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// <1=> M = 6
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// <2=> M = 8
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// <3=> M = 10
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// <4=> M = 12
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// <o4> PSEL
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// <0=> P = 2
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// <1=> P = 4
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// <o5> PLL CLKIN Source selection
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// <0=> IHRC
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// <1=> EHS X'TAL
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// </h>
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//</e>
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// <o6> AHB Clock Prescaler Register (SYS0_AHBCP)
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// <0=> SYSCLK/1
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// <1=> SYSCLK/2
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// <2=> SYSCLK/4
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// <3=> SYSCLK/8
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// <4=> SYSCLK/16
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// <5=> SYSCLK/32
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// <6=> SYSCLK/64
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// <7=> SYSCLK/128
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// <o7> SYSCLK prescaler Register (SYS0_AHBCP)
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// <0=> SYSCLK/1
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// <1=> SYSCLK/1.5
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// <o8> CLKOUT selection
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// <0=> Disable
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// <1=> ILRC
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// <2=> ELS X'TAL
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// <4=> HCLK
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// <5=> IHRC
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// <6=> EHS X'TAL
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// <7=> PLL
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// <o9> CLKOUT Prescaler Register (SYS1_APBCP1)
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// <0=> CLKOUT selection/1
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// <1=> CLKOUT selection/2
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// <2=> CLKOUT selection/4
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// <3=> CLKOUT selection/8
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// <4=> CLKOUT selection/16
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// <5=> CLKOUT selection/32
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// <6=> CLKOUT selection/64
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// <7=> CLKOUT selection/128
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*/
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#ifndef SYS0_CLKCFG_VAL
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#define SYS0_CLKCFG_VAL 0
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#endif
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#ifndef EHS_FREQ
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#define EHS_FREQ 16
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#endif
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#ifndef PLL_ENABLE
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#define PLL_ENABLE 0
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#endif
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#ifndef PLL_MSEL
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#define PLL_MSEL 1
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#endif
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#ifndef PLL_PSEL
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#define PLL_PSEL 0
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#endif
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#ifndef PLL_CLKIN
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#define PLL_CLKIN 0
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#endif
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#ifndef AHB_PRESCALAR
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#define AHB_PRESCALAR 0x0
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#endif
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#ifndef AHB_1P5PRESCALAR
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#define AHB_1P5PRESCALAR 0x0
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#endif
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#ifndef CLKOUT_SEL_VAL
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#define CLKOUT_SEL_VAL 0x0
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#endif
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#ifndef CLKOUT_PRESCALAR
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#define CLKOUT_PRESCALAR 0x0
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#endif
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/*
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//-------- <<< end of configuration section >>> ------------------------------
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*/
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/*----------------------------------------------------------------------------
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DEFINES
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*----------------------------------------------------------------------------*/
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#ifndef IHRC
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#define IHRC 0
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#endif
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#ifndef ILRC
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#define ILRC 1
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#endif
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#ifndef EHSXTAL
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#define EHSXTAL 2
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#endif
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#ifndef ELSXTAL
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#define ELSXTAL 3
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#endif
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#ifndef PLL
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#define PLL 4
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#endif
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/*----------------------------------------------------------------------------
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Define clocks
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*----------------------------------------------------------------------------*/
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#define __IHRC_FREQ (12000000UL)
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#define __ILRC_FREQ (32000UL)
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#define __ELS_XTAL_FREQ (32768UL)
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#define SYS0_PLLCTRL_VAL (PLL_ENABLE<<15) | (PLL_CLKIN<<12) | (PLL_PSEL<<5) | PLL_MSEL
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/*----------------------------------------------------------------------------
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Clock Variable definitions
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*----------------------------------------------------------------------------*/
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uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
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/*----------------------------------------------------------------------------
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Clock functions
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*----------------------------------------------------------------------------*/
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void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
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{
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uint32_t AHB_prescaler;
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switch (SN_SYS0->CLKCFG_b.SYSCLKST)
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{
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case 0: //IHRC
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SystemCoreClock = __IHRC_FREQ;
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break;
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case 1: //ILRC
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SystemCoreClock = __ILRC_FREQ;
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break;
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case 2: //EHS X'TAL
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SystemCoreClock = EHS_FREQ * 1000000;
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break;
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case 3: //ELS X'TAL
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SystemCoreClock = __ELS_XTAL_FREQ;
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break;
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case 4: //PLL
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if (PLL_CLKIN == 0x0) //IHRC as F_CLKIN
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SystemCoreClock = __IHRC_FREQ * (PLL_MSEL+2) / (PLL_PSEL+1);
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else
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SystemCoreClock = EHS_FREQ * 1000000 * (PLL_MSEL+2) / (PLL_PSEL+1);
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break;
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default:
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break;
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}
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switch (SN_SYS0->AHBCP)
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{
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case 0: AHB_prescaler = 1; break;
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case 1: AHB_prescaler = 2; break;
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case 2: AHB_prescaler = 4; break;
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case 3: AHB_prescaler = 8; break;
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case 4: AHB_prescaler = 16; break;
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case 5: AHB_prescaler = 32; break;
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case 6: AHB_prescaler = 64; break;
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case 7: AHB_prescaler = 128;break;
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default: break;
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}
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SystemCoreClock /= AHB_prescaler;
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if (SN_SYS0->AHBCP_b.DIV1P5 == 1)
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SystemCoreClock = SystemCoreClock*2/3;
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//;;;;;;;;; Need for SN32F780 Begin ;;;;;;;;;
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if (SystemCoreClock > 48000000)
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SN_FLASH->LPCTRL = 0x5AFA0031;
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else if (SystemCoreClock > 24000000)
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SN_FLASH->LPCTRL = 0x5AFA0011;
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else
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SN_FLASH->LPCTRL = 0x5AFA0000;
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//;;;;;;;;; Need for SN32F780 End ;;;;;;;;;
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return;
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}
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Setup the microcontroller system.
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* Initialize the System.
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*/
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void SystemInit (void)
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{
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#if SYS0_CLKCFG_VAL == IHRC //IHRC
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SN_SYS0->CLKCFG = 0x0;
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while ((SN_SYS0->CLKCFG & 0x70) != 0x0);
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#endif
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#if SYS0_CLKCFG_VAL == ILRC //ILRC
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SN_SYS0->CLKCFG = 0x1;
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while ((SN_SYS0->CLKCFG & 0x70) != 0x10);
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#endif
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#if (SYS0_CLKCFG_VAL == EHSXTAL) //EHS XTAL
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#if (EHS_FREQ > 12)
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SN_SYS0->ANBCTRL_b.EHSFREQ = 1;
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SN_FLASH->LPCTRL = 0x5AFA0011;
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#else
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SN_SYS0->ANBCTRL_b.EHSFREQ = 0;
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#endif
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SN_SYS0->ANBCTRL_b.EHSEN = 1;
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while ((SN_SYS0->CSST & 0x10) != 0x10);
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SN_SYS0->CLKCFG = 0x2;
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while ((SN_SYS0->CLKCFG & 0x70) != 0x20);
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#endif
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#if (SYS0_CLKCFG_VAL == ELSXTAL) //ELS XTAL
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SN_SYS0->ANBCTRL_b.ELSEN = 1;
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while((SN_SYS0->CSST & 0x4) != 0x4);
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SN_SYS0->CLKCFG = 0x3;
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while ((SN_SYS0->CLKCFG & 0x70) != 0x30);
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#endif
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#if (PLL_ENABLE == 1)
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SN_SYS0->PLLCTRL = SYS0_PLLCTRL_VAL;
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if (PLL_CLKIN == 0x1) //EHS XTAL as F_CLKIN
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{
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//Enable EHS
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#if (EHS_FREQ > 12)
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SN_SYS0->ANBCTRL_b.EHSFREQ = 1;
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#else
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SN_SYS0->ANBCTRL_b.EHSFREQ = 0;
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#endif
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SN_SYS0->ANBCTRL_b.EHSEN = 1;
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while ((SN_SYS0->CSST & 0x10) != 0x10);
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}
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while ((SN_SYS0->CSST & 0x40) != 0x40);
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#if (SYS0_CLKCFG_VAL == PLL) //PLL
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SN_FLASH->LPCTRL = 0x5AFA0031;
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SN_SYS0->CLKCFG = 0x4;
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while ((SN_SYS0->CLKCFG & 0x70) != 0x40);
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#endif
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#endif
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SN_SYS0->AHBCP = AHB_PRESCALAR;
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SN_SYS0->AHBCP_b.DIV1P5 = AHB_1P5PRESCALAR;
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#if (CLKOUT_SEL_VAL > 0) //CLKOUT
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SN_SYS1->AHBCLKEN_b.CLKOUTSEL = CLKOUT_SEL_VAL;
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SN_SYS1->APBCP1_b.CLKOUTPRE = CLKOUT_PRESCALAR;
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#endif
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}
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