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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5345 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2013-03-03 08:45:54 +00:00
parent b2a6a639f8
commit 033585af1a
8 changed files with 173 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
boards/ST_STM32373C_EVAL/board.h
View File

@ -59,7 +59,7 @@
#define GPIOA_PIN4 4
#define GPIOA_PIN5 5
#define GPIOA_PIN6 6
#define GPIOA_COMP2 OUT 7
#define GPIOA_COMP2_OUT 7
#define GPIOA_I2C2_SMB 8
#define GPIOA_I2C2_SCL 9
#define GPIOA_I2C2_SDA 10
@ -186,7 +186,7 @@
* PA4 - PIN4 (input pullup).
* PA5 - PIN5 (input floating).
* PA6 - PIN6 (input pullup).
* PA7 - COMP2 OUT (output pushpull maximum).
* PA7 - COMP2_OUT (output pushpull maximum).
* PA8 - I2C2_SMB (input floating).
* PA9 - I2C2_SCL (alternate 4).
* PA10 - I2C2_SDA (alternate 4).
@ -203,7 +203,7 @@
PIN_MODE_INPUT(GPIOA_PIN4) | \
PIN_MODE_INPUT(GPIOA_PIN5) | \
PIN_MODE_INPUT(GPIOA_PIN6) | \
PIN_MODE_OUTPUT(GPIOA_COMP2 OUT) | \
PIN_MODE_OUTPUT(GPIOA_COMP2_OUT) | \
PIN_MODE_INPUT(GPIOA_I2C2_SMB) | \
PIN_MODE_ALTERNATE(GPIOA_I2C2_SCL) | \
PIN_MODE_ALTERNATE(GPIOA_I2C2_SDA) | \
@ -219,7 +219,7 @@
PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
PIN_OTYPE_PUSHPULL(GPIOA_COMP2 OUT) | \
PIN_OTYPE_PUSHPULL(GPIOA_COMP2_OUT) | \
PIN_OTYPE_PUSHPULL(GPIOA_I2C2_SMB) | \
PIN_OTYPE_OPENDRAIN(GPIOA_I2C2_SCL) | \
PIN_OTYPE_PUSHPULL(GPIOA_I2C2_SDA) | \
@ -235,7 +235,7 @@
PIN_OSPEED_2M(GPIOA_PIN4) | \
PIN_OSPEED_100M(GPIOA_PIN5) | \
PIN_OSPEED_2M(GPIOA_PIN6) | \
PIN_OSPEED_100M(GPIOA_COMP2 OUT) | \
PIN_OSPEED_100M(GPIOA_COMP2_OUT) | \
PIN_OSPEED_2M(GPIOA_I2C2_SMB) | \
PIN_OSPEED_100M(GPIOA_I2C2_SCL) | \
PIN_OSPEED_100M(GPIOA_I2C2_SDA) | \
@ -251,7 +251,7 @@
PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
PIN_PUPDR_FLOATING(GPIOA_PIN5) | \
PIN_PUPDR_PULLUP(GPIOA_PIN6) | \
PIN_PUPDR_FLOATING(GPIOA_COMP2 OUT) | \
PIN_PUPDR_FLOATING(GPIOA_COMP2_OUT) | \
PIN_PUPDR_FLOATING(GPIOA_I2C2_SMB) | \
PIN_PUPDR_FLOATING(GPIOA_I2C2_SCL) | \
PIN_PUPDR_FLOATING(GPIOA_I2C2_SDA) | \
@ -267,7 +267,7 @@
PIN_ODR_HIGH(GPIOA_PIN4) | \
PIN_ODR_HIGH(GPIOA_PIN5) | \
PIN_ODR_HIGH(GPIOA_PIN6) | \
PIN_ODR_LOW(GPIOA_COMP2 OUT) | \
PIN_ODR_LOW(GPIOA_COMP2_OUT) | \
PIN_ODR_HIGH(GPIOA_I2C2_SMB) | \
PIN_ODR_HIGH(GPIOA_I2C2_SCL) | \
PIN_ODR_HIGH(GPIOA_I2C2_SDA) | \
@ -283,7 +283,7 @@
PIN_AFIO_AF(GPIOA_PIN4, 0) | \
PIN_AFIO_AF(GPIOA_PIN5, 5) | \
PIN_AFIO_AF(GPIOA_PIN6, 0) | \
PIN_AFIO_AF(GPIOA_COMP2 OUT, 0))
PIN_AFIO_AF(GPIOA_COMP2_OUT, 0))
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_I2C2_SMB, 0) | \
PIN_AFIO_AF(GPIOA_I2C2_SCL, 4) | \
PIN_AFIO_AF(GPIOA_I2C2_SDA, 4) | \

4
boards/ST_STM32373C_EVAL/board.mk
View File

@ -1,5 +1,5 @@
# List of all the board related files.
BOARDSRC = ${CHIBIOS}/boards/ST STM32373C-EVAL/board.c
BOARDSRC = ${CHIBIOS}/boards/ST_STM32373C_EVAL/board.c
# Required include directories
BOARDINC = ${CHIBIOS}/boards/ST STM32373C-EVAL
BOARDINC = ${CHIBIOS}/boards/ST_STM32373C_EVAL

2
boards/ST_STM32373C_EVAL/cfg/board.chcfg
View File

@ -72,7 +72,7 @@
Mode="Input"
Alternate="0" />
<pin7
ID="COMP2 OUT"
ID="COMP2_OUT"
Type="PushPull"
Speed="Maximum"
Resistor="Floating"

6
demos/ARMCM4-STM32F373-STM32373C_EVAL/Makefile
View File

@ -65,15 +65,15 @@ PROJECT = ch
# Imported source files and paths
CHIBIOS = ../..
include $(CHIBIOS)/boards/ST_STM32F3_DISCOVERY/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32F30x/platform.mk
include $(CHIBIOS)/boards/ST_STM32373C_EVAL/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32F37x/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F3xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F303xC.ld
LDSCRIPT= $(PORTLD)/STM32F373xC.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.

9
demos/ARMCM4-STM32F373-STM32373C_EVAL/mcuconf.h
View File

@ -32,7 +32,7 @@
* 0...3 Lowest...Highest.
*/
#define STM32F30x_MCUCONF
#define STM32F37x_MCUCONF
/*
* HAL driver system settings.
@ -52,17 +52,12 @@
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_ADC12PRES STM32_ADC12PRES_DIV1
#define STM32_ADC34PRES STM32_ADC34PRES_DIV1
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_USART1SW STM32_USART1SW_PCLK
#define STM32_USART2SW STM32_USART2SW_PCLK
#define STM32_USART3SW STM32_USART3SW_PCLK
#define STM32_UART4SW STM32_UART4SW_PCLK
#define STM32_UART5SW STM32_UART5SW_PCLK
#define STM32_I2C1SW STM32_I2C1SW_SYSCLK
#define STM32_I2C2SW STM32_I2C2SW_SYSCLK
#define STM32_TIM1SW STM32_TIM1SW_PCLK2
#define STM32_TIM8SW STM32_TIM8SW_PCLK2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_USB_CLOCK_REQUIRED TRUE
#define STM32_USBPRE STM32_USBPRE_DIV1P5

14
os/hal/platforms/STM32F37x/hal_lld.c
View File

@ -136,9 +136,6 @@ void hal_lld_init(void) {
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
/* USB IRQ relocated to not conflict with CAN.*/
SYSCFG->CFGR1 |= SYSCFG_CFGR1_USB_IT_RMP;
}
/**
@ -182,13 +179,12 @@ void stm32_clock_init(void) {
#endif
/* Clock settings.*/
RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL |
STM32_PLLSRC | STM32_PPRE1 | STM32_PPRE2 |
RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL |
STM32_PLLSRC | STM32_PPRE1 | STM32_PPRE2 |
STM32_HPRE;
RCC->CFGR2 = STM32_ADC34PRES | STM32_ADC12PRES | STM32_PREDIV;
RCC->CFGR3 = STM32_UART5SW | STM32_UART4SW | STM32_USART3SW |
STM32_USART2SW | STM32_TIM8SW | STM32_TIM1SW |
STM32_I2C2SW | STM32_I2C1SW | STM32_USART1SW;
RCC->CFGR2 = STM32_PREDIV;
RCC->CFGR3 = STM32_USART3SW | STM32_USART2SW | STM32_I2C2SW |
STM32_I2C1SW | STM32_USART1SW;
#if STM32_ACTIVATE_PLL
/* PLL activation.*/

4
os/hal/platforms/STM32F37x/hal_lld.h
View File

@ -564,7 +564,7 @@
* @brief ADC prescaler value.
*/
#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
#define STM32_ADCPRE STM32_ADCPRE_DIV2
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#endif
/**
@ -947,7 +947,7 @@
#endif
/* ADC minimum frequency check.*/
#if STM32ADCLK < STM32_ADCCLK_MIN
#if STM32_ADCLK < STM32_ADCCLK_MIN
#error "STM32_ADCLK exceeding maximum frequency (STM32_ADCCLK_MIN)"
#endif

150
os/ports/GCC/ARMCMx/STM32F3xx/ld/STM32F373xC.ld Normal file
View File

@ -0,0 +1,150 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* ST32F373xC memory setup.
*/
__main_stack_size__ = 0x0400;
__process_stack_size__ = 0x0400;
MEMORY
{
flash : org = 0x08000000, len = 256k
ram : org = 0x20000000, len = 32k
}
__ram_start__ = ORIGIN(ram);
__ram_size__ = LENGTH(ram);
__ram_end__ = __ram_start__ + __ram_size__;
SECTIONS
{
. = 0;
_text = .;
startup : ALIGN(16) SUBALIGN(16)
{
KEEP(*(vectors))
} > flash
constructors : ALIGN(4) SUBALIGN(4)
{
PROVIDE(__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE(__init_array_end = .);
} > flash
destructors : ALIGN(4) SUBALIGN(4)
{
PROVIDE(__fini_array_start = .);
KEEP(*(.fini_array))
KEEP(*(SORT(.fini_array.*)))
PROVIDE(__fini_array_end = .);
} > flash
.text : ALIGN(16) SUBALIGN(16)
{
*(.text.startup.*)
*(.text)
*(.text.*)
*(.rodata)
*(.rodata.*)
*(.glue_7t)
*(.glue_7)
*(.gcc*)
} > flash
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > flash
.ARM.exidx : {
PROVIDE(__exidx_start = .);
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
PROVIDE(__exidx_end = .);
} > flash
.eh_frame_hdr :
{
*(.eh_frame_hdr)
} > flash
.eh_frame : ONLY_IF_RO
{
*(.eh_frame)
} > flash
.textalign : ONLY_IF_RO
{
. = ALIGN(8);
} > flash
_etext = .;
_textdata = _etext;
.stacks :
{
. = ALIGN(8);
__main_stack_base__ = .;
. += __main_stack_size__;
. = ALIGN(8);
__main_stack_end__ = .;
__process_stack_base__ = .;
__main_thread_stack_base__ = .;
. += __process_stack_size__;
. = ALIGN(8);
__process_stack_end__ = .;
__main_thread_stack_end__ = .;
} > ram
.data :
{
. = ALIGN(4);
PROVIDE(_data = .);
*(.data)
. = ALIGN(4);
*(.data.*)
. = ALIGN(4);
*(.ramtext)
. = ALIGN(4);
PROVIDE(_edata = .);
} > ram AT > flash
.bss :
{
. = ALIGN(4);
PROVIDE(_bss_start = .);
*(.bss)
. = ALIGN(4);
*(.bss.*)
. = ALIGN(4);
*(COMMON)
. = ALIGN(4);
PROVIDE(_bss_end = .);
} > ram
}
PROVIDE(end = .);
_end = .;
__heap_base__ = _end;
__heap_end__ = __ram_end__;