mirror of https://github.com/rusefi/ChibiOS.git
Added support for HSI48 on STM32L4 devices that have it.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11134 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio
parent
f3ac9042e1
commit
052945de4d
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@ -41,6 +41,7 @@
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_HSI16_ENABLED FALSE
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#define STM32_HSI48_ENABLED FALSE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_HSE_ENABLED FALSE
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#define STM32_LSE_ENABLED TRUE
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@ -191,7 +191,16 @@ void stm32_clock_init(void) {
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/* HSI activation.*/
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RCC->CR |= RCC_CR_HSION;
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while ((RCC->CR & RCC_CR_HSIRDY) == 0)
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; /* Wait until HSI is stable. */
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; /* Wait until HSI16 is stable. */
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#endif
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#if STM32_CLOCK_HAS_HSI48
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#if STM32_HSI48_ENABLED
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/* HSI activation.*/
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RCC->CRRCR |= RCC_CRRCR_HSI48ON;
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while ((RCC->CRRCR & RCC_CRRCR_HSI48RDY) == 0)
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; /* Wait until HSI48 is stable. */
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#endif
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#endif
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#if STM32_HSE_ENABLED
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@ -71,7 +71,8 @@
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* @name Internal clock sources
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* @{
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*/
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#define STM32_HSI16CLK 16000000 /**< High speed internal clock. */
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#define STM32_HSI16CLK 16000000 /**< 16MHz internal clock. */
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#define STM32_HSI48CLK 48000000 /**< 48MHz internal clock. */
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#define STM32_LSICLK 32000 /**< Low speed internal clock. */
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/** @} */
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@ -157,7 +158,7 @@
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#define STM32_STOPWUCK_MSI (0 << 15) /**< Wakeup clock is MSI. */
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#define STM32_STOPWUCK_HSI16 (1 << 15) /**< Wakeup clock is HSI16. */
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#define STM32_MCOSEL_MASK (7 << 24) /**< MCOSEL field mask. */
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#define STM32_MCOSEL_MASK (15 << 24) /**< MCOSEL field mask. */
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#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
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#define STM32_MCOSEL_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */
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#define STM32_MCOSEL_MSI (2 << 24) /**< MSI clock on MCO pin. */
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@ -269,7 +270,11 @@
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#define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/
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#define STM32_CLK48SEL_MASK (3 << 26) /**< CLK48SEL mask. */
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#if !STM32_CLOCK_HAS_HSI48
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#define STM32_CLK48SEL_NOCLK (0 << 26) /**< CLK48 disabled. */
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#else
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#define STM32_CLK48SEL_HSI48 (0 << 26) /**< CLK48 source is HSI48. */
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#endif
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#define STM32_CLK48SEL_PLLSAI1 (1 << 26) /**< CLK48 source is PLLSAI1-Q. */
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#define STM32_CLK48SEL_PLL (2 << 26) /**< CLK48 source is PLL-Q. */
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#define STM32_CLK48SEL_MSI (3 << 26) /**< CLK48 source is MSI. */
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@ -362,6 +367,13 @@
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#define STM32_HSI16_ENABLED FALSE
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#endif
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/**
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* @brief Enables or disables the HSI48 clock source.
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*/
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#if !defined(STM32_HSI48_ENABLED) || defined(__DOXYGEN__)
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#define STM32_HSI48_ENABLED FALSE
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#endif
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/**
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* @brief Enables or disables the LSI clock source.
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*/
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@ -1001,9 +1013,22 @@
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(STM32_PLLSRC == STM32_PLLSRC_HSI16)
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#error "HSI16 not enabled, required by STM32_SAI2SEL"
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#endif
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#endif /* !STM32_HSI16_ENABLED */
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#if STM32_CLOCK_HAS_HSI48
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#if STM32_HSI48_ENABLED
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#else /* !STM32_HSI48_ENABLED */
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#if STM32_MCOSEL == STM32_MCOSEL_HSI48
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#error "HSI48 not enabled, required by STM32_MCOSEL"
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#endif
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#if STM32_CLK48SEL == STM32_CLK48SEL_HSI48
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#error "HSI48 not enabled, required by STM32_CLK48SEL"
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#endif
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#endif /* !STM32_HSI48_ENABLED */
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#endif /* STM32_CLOCK_HAS_HSI48 */
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/*
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* HSE related checks.
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*/
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@ -1793,6 +1818,9 @@
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#elif STM32_MCOSEL == STM32_MCOSEL_LSE
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#define STM32_MCODIVCLK STM32_LSECLK
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#elif STM32_MCOSEL == STM32_MCOSEL_HSI48
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#define STM32_MCODIVCLK STM32_HSI48CLK
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#else
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#error "invalid STM32_MCOSEL value specified"
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#endif
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@ -2000,6 +2028,8 @@
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/**
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* @brief 48MHz clock frequency.
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*/
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#if !STM32_CLOCK_HAS_HSI48 || defined(__DOXYGEN__)
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#if (STM32_CLK48SEL == STM32_CLK48SEL_NOCLK) || defined(__DOXYGEN__)
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#define STM32_48CLK 0
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#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1
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@ -2011,6 +2041,26 @@
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#else
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#error "invalid source selected for 48CLK clock"
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#endif
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#else /* STM32_CLOCK_HAS_HSI48 */
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#if (STM32_CLK48SEL == STM32_CLK48SEL_HSI48) || defined(__DOXYGEN__)
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#define STM32_48CLK STM32_HSI48CLK
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#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1
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#define STM32_48CLK (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE)
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#elif STM32_CLK48SEL == STM32_CLK48SEL_PLL
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#define STM32_48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
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#elif STM32_CLK48SEL == STM32_CLK48SEL_MSI
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#define STM32_48CLK STM32_MSICLK
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#else
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#error "invalid source selected for 48CLK clock"
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#endif
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#endif /* STM32_CLOCK_HAS_HSI48 */
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/**
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* @brief USB clock point.
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*/
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#define STM32_USBCLK STM32_48CLK
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/**
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@ -52,6 +52,9 @@
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#if defined(STM32L432xx) || defined(__DOXYGEN__)
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/* Clock attributes.*/
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#define STM32_CLOCK_HAS_HSI48 TRUE
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_HANDLER Vector88
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@ -371,6 +374,9 @@
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#if defined(STM32L476xx)
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/* Clock attributes.*/
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#define STM32_CLOCK_HAS_HSI48 FALSE
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_HANDLER Vector88
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@ -774,6 +780,9 @@
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#if defined(STM32L496xx)
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/* Clock attributes.*/
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#define STM32_CLOCK_HAS_HSI48 FALSE
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_HANDLER Vector88
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