mirror of https://github.com/rusefi/ChibiOS.git
Serial port working.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11189 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio
parent
8db4d4f312
commit
0714e7283d
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@ -5,7 +5,7 @@
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# Compiler options here.
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ifeq ($(USE_OPT),)
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USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
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USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
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endif
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# C specific options here (added to USE_OPT).
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@ -111,9 +111,9 @@ include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
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# Auto-build files in ./source recursively.
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include $(CHIBIOS)/tools/mk/autobuild.mk
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# Other files (optional).
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#include $(CHIBIOS)/test/lib/test.mk
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#include $(CHIBIOS)/test/rt/rt_test.mk
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#include $(CHIBIOS)/test/oslib/oslib_test.mk
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include $(CHIBIOS)/test/lib/test.mk
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include $(CHIBIOS)/test/rt/rt_test.mk
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include $(CHIBIOS)/test/oslib/oslib_test.mk
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# Define linker script file here
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LDSCRIPT= $(STARTUPLD)/STM32H743xI.ld
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File diff suppressed because one or more lines are too long
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@ -146,7 +146,7 @@
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* @brief Enables the SERIAL subsystem.
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*/
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#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
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#define HAL_USE_SERIAL FALSE
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#define HAL_USE_SERIAL TRUE
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#endif
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/**
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@ -16,8 +16,8 @@
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#include "ch.h"
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#include "hal.h"
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//#include "rt_test_root.h"
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//#include "oslib_test_root.h"
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#include "rt_test_root.h"
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#include "oslib_test_root.h"
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/*
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* This is a periodic thread that does absolutely nothing except flashing
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@ -54,7 +54,7 @@ int main(void) {
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/*
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* Activates the serial driver 1 using the driver default configuration.
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*/
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// sdStart(&SD1, NULL);
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sdStart(&SD3, NULL);
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/*
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* Creates the example thread.
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@ -66,12 +66,10 @@ int main(void) {
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* sleeping in a loop and check the button state.
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*/
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while (1) {
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#if 0
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if (palReadLine(LINE_BUTTON_USER)) {
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test_execute((BaseSequentialStream *)&SD1, &rt_test_suite);
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test_execute((BaseSequentialStream *)&SD1, &oslib_test_suite);
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if (palReadLine(LINE_BUTTON)) {
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test_execute((BaseSequentialStream *)&SD3, &rt_test_suite);
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test_execute((BaseSequentialStream *)&SD3, &oslib_test_suite);
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}
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#endif
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chThdSleepMilliseconds(500);
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}
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}
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@ -332,9 +332,9 @@
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/*
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* SERIAL driver system settings.
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*/
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#define STM32_SERIAL_USE_USART1 TRUE
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#define STM32_SERIAL_USE_USART1 FALSE
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#define STM32_SERIAL_USE_USART2 FALSE
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#define STM32_SERIAL_USE_USART3 FALSE
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#define STM32_SERIAL_USE_USART3 TRUE
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#define STM32_SERIAL_USE_UART4 FALSE
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#define STM32_SERIAL_USE_UART5 FALSE
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#define STM32_SERIAL_USE_USART6 FALSE
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@ -2280,6 +2280,104 @@
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#endif
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#endif
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#if (STM32_USART16SEL == STM32_USART16SEL_PCLK2) || defined(__DOXYGEN__)
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/**
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* @brief USART1 clock.
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*/
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#define STM32_USART1CLK STM32_PCLK2
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/**
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* @brief USART6 clock.
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*/
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#define STM32_USART6CLK STM32_PCLK2
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#elif STM32_USART1SEL == STM32_USART16SEL_PLL2_Q_CK
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#define STM32_USART1CLK STM32_PLL2_Q_CK
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#define STM32_USART6CLK STM32_PLL2_Q_CK
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#elif STM32_USART16SEL == STM32_USART16SEL_PLL3_Q_CK
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#define STM32_USART1CLK STM32_PLL3_Q_CK
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#define STM32_USART6CLK STM32_PLL3_Q_CK
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#elif STM32_USART16SEL == STM32_USART16SEL_HSI_KER_CK
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#define STM32_USART1CLK STM32_HSICLK
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#define STM32_USART6CLK STM32_HSICLK
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#elif STM32_USART16SEL == STM32_USART16SEL_CSI_KER_CK
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#define STM32_USART1CLK STM32_CSICLK
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#define STM32_USART6CLK STM32_CSICLK
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#elif STM32_USART16SEL == STM32_USART16SEL_LSE_CK
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#define STM32_USART1CLK STM32_LSECLK
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#define STM32_USART6CLK STM32_LSECLK
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#else
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#error "invalid source selected for STM32_USART16SEL clock"
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#endif
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#if (STM32_USART234578SEL == STM32_USART234578SEL_PCLK1) || defined(__DOXYGEN__)
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/**
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* @brief USART2 clock.
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*/
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#define STM32_USART2CLK STM32_PCLK1
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/**
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* @brief USART3 clock.
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*/
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#define STM32_USART3CLK STM32_PCLK1
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/**
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* @brief USART4 clock.
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*/
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#define STM32_USART4CLK STM32_PCLK1
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/**
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* @brief USART5 clock.
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*/
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#define STM32_USART5CLK STM32_PCLK1
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/**
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* @brief USART7 clock.
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*/
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#define STM32_USART7CLK STM32_PCLK1
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/**
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* @brief USART8 clock.
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*/
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#define STM32_USART8CLK STM32_PCLK2
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#elif STM32_USART234578SEL == STM32_USART234578SEL_PLL2_Q_CK
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#define STM32_USART2CLK STM32_PLL2_Q_CK
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#define STM32_USART3CLK STM32_PLL2_Q_CK
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#define STM32_USART4CLK STM32_PLL2_Q_CK
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#define STM32_USART5CLK STM32_PLL2_Q_CK
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#define STM32_USART7CLK STM32_PLL2_Q_CK
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#define STM32_USART8CLK STM32_PLL2_Q_CK
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#elif STM32_USART234578SEL == STM32_USART234578SEL_PLL3_Q_CK
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#define STM32_USART2CLK STM32_PLL3_Q_CK
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#define STM32_USART3CLK STM32_PLL3_Q_CK
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#define STM32_USART4CLK STM32_PLL3_Q_CK
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#define STM32_USART5CLK STM32_PLL3_Q_CK
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#define STM32_USART7CLK STM32_PLL3_Q_CK
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#define STM32_USART8CLK STM32_PLL3_Q_CK
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#elif STM32_USART234578SEL == STM32_USART234578SEL_HSI_KER_CK
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#define STM32_USART2CLK STM32_HSICLK
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#define STM32_USART3CLK STM32_HSICLK
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#define STM32_USART4CLK STM32_HSICLK
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#define STM32_USART5CLK STM32_HSICLK
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#define STM32_USART7CLK STM32_HSICLK
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#define STM32_USART8CLK STM32_HSICLK
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#elif STM32_USART234578SEL == STM32_USART234578SEL_CSI_KER_CK
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#define STM32_USART2CLK STM32_CSICLK
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#define STM32_USART3CLK STM32_CSICLK
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#define STM32_USART4CLK STM32_CSICLK
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#define STM32_USART5CLK STM32_CSICLK
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#define STM32_USART7CLK STM32_CSICLK
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#define STM32_USART8CLK STM32_CSICLK
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#elif STM32_USART234578SEL == STM32_USART234578SEL_LSE_CK
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#define STM32_USART2CLK STM32_LSECLK
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#define STM32_USART3CLK STM32_LSECLK
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#define STM32_USART4CLK STM32_LSECLK
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#define STM32_USART6CLK STM32_LSECLK
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#define STM32_USART7CLK STM32_LSECLK
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#define STM32_USART8CLK STM32_LSECLK
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#else
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#error "invalid source selected for STM32_USART234578SEL clock"
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#endif
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@ -2303,126 +2401,6 @@
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#if 0
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/**
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* @brief USART1 frequency.
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*/
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#if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN__)
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#define STM32_USART1CLK STM32_PCLK2
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#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK
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#define STM32_USART1CLK STM32_SYSCLK
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#elif STM32_USART1SEL == STM32_USART1SEL_HSI
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#define STM32_USART1CLK STM32_HSICLK
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#elif STM32_USART1SEL == STM32_USART1SEL_LSE
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#define STM32_USART1CLK STM32_LSECLK
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#else
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#error "invalid source selected for USART1 clock"
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#endif
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/**
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* @brief USART2 frequency.
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*/
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#if (STM32_USART2SEL == STM32_USART2SEL_PCLK1) || defined(__DOXYGEN__)
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#define STM32_USART2CLK STM32_PCLK1
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#elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK
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#define STM32_USART2CLK STM32_SYSCLK
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#elif STM32_USART2SEL == STM32_USART2SEL_HSI
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#define STM32_USART2CLK STM32_HSICLK
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#elif STM32_USART2SEL == STM32_USART2SEL_LSE
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#define STM32_USART2CLK STM32_LSECLK
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#else
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#error "invalid source selected for USART2 clock"
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#endif
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/**
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* @brief USART3 frequency.
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*/
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#if (STM32_USART3SEL == STM32_USART3SEL_PCLK1) || defined(__DOXYGEN__)
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#define STM32_USART3CLK STM32_PCLK1
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#elif STM32_USART3SEL == STM32_USART3SEL_SYSCLK
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#define STM32_USART3CLK STM32_SYSCLK
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#elif STM32_USART3SEL == STM32_USART3SEL_HSI
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#define STM32_USART3CLK STM32_HSICLK
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#elif STM32_USART3SEL == STM32_USART3SEL_LSE
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#define STM32_USART3CLK STM32_LSECLK
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#else
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#error "invalid source selected for USART3 clock"
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#endif
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/**
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* @brief UART4 frequency.
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*/
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#if (STM32_UART4SEL == STM32_UART4SEL_PCLK1) || defined(__DOXYGEN__)
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#define STM32_UART4CLK STM32_PCLK1
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#elif STM32_UART4SEL == STM32_UART4SEL_SYSCLK
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#define STM32_UART4CLK STM32_SYSCLK
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#elif STM32_UART4SEL == STM32_UART4SEL_HSI
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#define STM32_UART4CLK STM32_HSICLK
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#elif STM32_UART4SEL == STM32_UART4SEL_LSE
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#define STM32_UART4CLK STM32_LSECLK
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#else
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#error "invalid source selected for UART4 clock"
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#endif
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/**
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* @brief UART5 frequency.
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*/
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#if (STM32_UART5SEL == STM32_UART5SEL_PCLK1) || defined(__DOXYGEN__)
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#define STM32_UART5CLK STM32_PCLK1
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#elif STM32_UART5SEL == STM32_UART5SEL_SYSCLK
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#define STM32_UART5CLK STM32_SYSCLK
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#elif STM32_UART5SEL == STM32_UART5SEL_HSI
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#define STM32_UART5CLK STM32_HSICLK
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#elif STM32_UART5SEL == STM32_UART5SEL_LSE
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#define STM32_UART5CLK STM32_LSECLK
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#else
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#error "invalid source selected for UART5 clock"
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#endif
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/**
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* @brief USART6 frequency.
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*/
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#if (STM32_USART6SEL == STM32_USART6SEL_PCLK2) || defined(__DOXYGEN__)
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#define STM32_USART6CLK STM32_PCLK2
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#elif STM32_USART6SEL == STM32_USART6SEL_SYSCLK
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#define STM32_USART6CLK STM32_SYSCLK
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#elif STM32_USART6SEL == STM32_USART6SEL_HSI
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#define STM32_USART6CLK STM32_HSICLK
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#elif STM32_USART6SEL == STM32_USART6SEL_LSE
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#define STM32_USART6CLK STM32_LSECLK
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#else
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#error "invalid source selected for USART6 clock"
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#endif
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/**
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* @brief UART7 frequency.
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*/
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#if (STM32_UART7SEL == STM32_UART7SEL_PCLK1) || defined(__DOXYGEN__)
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#define STM32_UART7CLK STM32_PCLK1
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#elif STM32_UART7SEL == STM32_UART7SEL_SYSCLK
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#define STM32_UART7CLK STM32_SYSCLK
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#elif STM32_UART7SEL == STM32_UART7SEL_HSI
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#define STM32_UART7CLK STM32_HSICLK
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#elif STM32_UART7SEL == STM32_UART7SEL_LSE
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#define STM32_UART7CLK STM32_LSECLK
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#else
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#error "invalid source selected for UART7 clock"
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#endif
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/**
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* @brief UART8 frequency.
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*/
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#if (STM32_UART8SEL == STM32_UART8SEL_PCLK1) || defined(__DOXYGEN__)
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#define STM32_UART8CLK STM32_PCLK1
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#elif STM32_UART8SEL == STM32_UART8SEL_SYSCLK
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#define STM32_UART8CLK STM32_SYSCLK
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#elif STM32_UART8SEL == STM32_UART8SEL_HSI
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#define STM32_UART8CLK STM32_HSICLK
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#elif STM32_UART8SEL == STM32_UART8SEL_LSE
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#define STM32_UART8CLK STM32_LSECLK
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#else
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#error "invalid source selected for UART8 clock"
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#endif
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/**
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* @brief I2C1 frequency.
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*/
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