diff --git a/os/hal/ports/STM32/STM32L4xx+/hal_lld.h b/os/hal/ports/STM32/STM32L4xx+/hal_lld.h
index 91103f013..23028e14e 100644
--- a/os/hal/ports/STM32/STM32L4xx+/hal_lld.h
+++ b/os/hal/ports/STM32/STM32L4xx+/hal_lld.h
@@ -1371,7 +1371,7 @@
 #endif
 
 /**
- * @brief   PLLs input clock frequency.
+ * @brief   PLL input clock frequency.
  */
 #if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
 #define STM32_PLLCLKIN              (STM32_HSECLK / STM32_PLLM_VALUE)
@@ -1471,6 +1471,44 @@
 #include "stm32_apb1.inc"
 #include "stm32_apb2.inc"
 
+/**
+ * @brief   PLLSAI1 input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1CLKIN          (STM32_HSECLK / STM32_PLLSAI1M_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_MSI
+#define STM32_PLLSAI1CLKIN          (STM32_MSICLK / STM32_PLLSAI1M_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI16
+#define STM32_PLLSAI1CLKIN          (STM32_HSI16CLK / STM32_PLLSAI1M_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
+#define STM32_PLLSAI1CLKIN          0
+
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/**
+ * @brief   PLLSAI2 input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2CLKIN          (STM32_HSECLK / STM32_PLLSAI2M_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_MSI
+#define STM32_PLLSAI2CLKIN          (STM32_MSICLK / STM32_PLLSAI2M_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI16
+#define STM32_PLLSAI2CLKIN          (STM32_HSI16CLK / STM32_PLLSAI2M_VALUE)
+
+#elif STM32_PLLSRC == STM32_PLLSRC_NOCLOCK
+#define STM32_PLLSAI2CLKIN          0
+
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
 /*
  * PLLSAI1 enable check.
  */
@@ -1561,10 +1599,7 @@
  */
 #define STM32_PLLSAI2REN            (1 << 24)
 
-/* Inclusion of PLLSAI-related checks and calculations, all PLLs share the
-   same clock source so enforcing this condition.*/
-#define STM32_PLLSAI1CLKIN STM32_PLLCLKIN
-#define STM32_PLLSAI2CLKIN STM32_PLLCLKIN
+/* Inclusion of PLLSAI-related checks and calculations.*/
 #include <stm32_pllsai1.inc>
 #include <stm32_pllsai2.inc>
 
diff --git a/readme.txt b/readme.txt
index 801b10751..a52d913d9 100644
--- a/readme.txt
+++ b/readme.txt
@@ -84,6 +84,8 @@
 - NEW: EFL driver and demo for STM32F3xx.
 - NEW: New unit test subsystem under /os/test. Now it is officially
        ChibiOS/TEST.
+- FIX: Fixed PLLSA1x input frequency calculated incorrectly (bug #1197)
+       (TBP to 21.6.1).
 - FIX: Fixed ARMCMx port, MPU not enabled when PORT_ENABLE_GUARD_PAGES is set
        (bug #1195)(backported to 20.3.4)(TBP to 21.6.1).
 - FIX: Fixed removed incorrect ADCv4 checks for MONEN (bug #1194)