mirror of https://github.com/rusefi/ChibiOS.git
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@605 35acf78f-673a-0410-8e92-d51de3d6d3f4
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gdisirio
parent
49adf9423c
commit
078651da50
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/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* ARM7 port system code.
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*/
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#include <chconf.h>
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.set MODE_USR, 0x10
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.set MODE_FIQ, 0x11
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.set MODE_IRQ, 0x12
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.set MODE_SVC, 0x13
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.set MODE_ABT, 0x17
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.set MODE_UND, 0x1B
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.set MODE_SYS, 0x1F
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.equ I_BIT, 0x80
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.equ F_BIT, 0x40
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.text
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/*
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* Interrupt enable/disable functions, only present if there is THUMB code in
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* the system because those are inlined in ARM code.
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*/
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#ifdef THUMB_PRESENT
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.balign 16
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.code 16
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.thumb_func
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.global _lock
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_lock:
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mov r0, pc
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bx r0
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.code 32
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mrs r0, CPSR
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msr CPSR_c, #MODE_SYS | I_BIT
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bx lr
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.balign 16
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.code 16
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.thumb_func
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.global _unlock
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_unlock:
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mov r1, pc
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bx r1
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.code 32
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msr CPSR_c, r0
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bx lr
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.balign 16
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.code 16
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.thumb_func
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.global _enable
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_enable:
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mov r0, pc
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bx r0
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.code 32
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msr CPSR_c, #MODE_SYS
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bx lr
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#endif
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.balign 16
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#ifdef THUMB_PRESENT
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.code 16
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.thumb_func
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.global chSysSwitchI_thumb
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chSysSwitchI_thumb:
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mov r2, pc
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bx r2
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// Jumps into chSysSwitchI in ARM mode
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#endif
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.code 32
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.global chSysSwitchI_arm
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chSysSwitchI_arm:
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#ifdef CH_CURRP_REGISTER_CACHE
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stmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr}
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str sp, [r0, #16]
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ldr sp, [r1, #16]
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#ifdef THUMB_PRESENT
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ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr}
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bx lr
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#else /* !THUMB_PRESENT */
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ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, pc}
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#endif /* !THUMB_PRESENT */
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#else /* !CH_CURRP_REGISTER_CACHE */
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stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr}
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str sp, [r0, #16]
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ldr sp, [r1, #16]
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#ifdef THUMB_PRESENT
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ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr}
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bx lr
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#else /* !THUMB_PRESENT */
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ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc}
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#endif /* !THUMB_PRESENT */
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#endif /* !CH_CURRP_REGISTER_CACHE */
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/*
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* Common exit point for all IRQ routines, it performs the rescheduling if
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* required.
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* System stack frame structure after a context switch in the
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* interrupt handler:
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*
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* High +------------+
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* | LR_USR | -+
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* | R12 | |
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* | R3 | |
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* | R2 | | External context: IRQ handler frame
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* | R1 | |
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* | R0 | |
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* | PC | | (user code return address)
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* | PSR_USR | -+ (user code status)
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* | .... | <- mk_DoRescheduleI() stack frame, optimize it for space
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* | LR | -+ (system code return address)
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* | R11 | |
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* | R10 | |
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* | R9 | |
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* | R8 | | Internal context: mk_SwitchI() frame
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* | (R7) | | (optional, see CH_CURRP_REGISTER_CACHE)
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* | R6 | |
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* | R5 | |
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* SP-> | R4 | -+
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* Low +------------+
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*/
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.balign 16
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#ifdef THUMB_NO_INTERWORKING
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.code 16
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.thumb_func
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.globl IrqCommon
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IrqCommon:
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bl chSchRescRequiredI
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mov lr, pc
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bx lr
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.code 32
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#else /* !THUMB_NO_INTERWORKING */
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.code 32
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.globl IrqCommon
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IrqCommon:
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bl chSchRescRequiredI
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#endif /* !THUMB_NO_INTERWORKING */
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cmp r0, #0 // Simply returns if a
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ldmeqfd sp!, {r0-r3, r12, lr} // reschedule is not
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subeqs pc, lr, #4 // required.
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// Saves the IRQ mode registers in the system stack.
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ldmfd sp!, {r0-r3, r12, lr} // IRQ stack now empty.
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msr CPSR_c, #MODE_SYS | I_BIT
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stmfd sp!, {r0-r3, r12, lr} // Registers on System Stack.
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msr CPSR_c, #MODE_IRQ | I_BIT
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mrs r0, SPSR
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mov r1, lr
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msr CPSR_c, #MODE_SYS | I_BIT
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stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ.
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// Context switch.
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#ifdef THUMB_NO_INTERWORKING
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add r0, pc, #1
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bx r0
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.code 16
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bl chSchDoRescheduleI
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mov lr, pc
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bx lr
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.code 32
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#else /* !THUMB_NO_INTERWORKING */
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bl chSchDoRescheduleI
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#endif /* !THUMB_NO_INTERWORKING */
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// Re-establish the IRQ conditions again.
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ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ.
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msr CPSR_c, #MODE_IRQ | I_BIT
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msr SPSR_fsxc, r0
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mov lr, r1
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msr CPSR_c, #MODE_SYS | I_BIT
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ldmfd sp!, {r0-r3, r12, lr}
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msr CPSR_c, #MODE_IRQ | I_BIT
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subs pc, lr, #4
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/*
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* Threads trampoline code.
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* NOTE: The threads always start in ARM mode then switch to the thread-function mode.
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*/
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.balign 16
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.code 32
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.globl threadstart
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threadstart:
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msr CPSR_c, #MODE_SYS
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#ifndef THUMB_NO_INTERWORKING
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mov r0, r5
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mov lr, pc
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bx r4
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bl chThdExit
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#else /* !THUMB_NO_INTERWORKING */
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add r0, pc, #1
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bx r0
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.code 16
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mov r0, r5
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bl jmpr4
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bl chThdExit
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jmpr4:
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bx r4
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#endif /* !THUMB_NO_INTERWORKING */
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/*
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* System stop code.
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*/
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.code 16
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.p2align 2,,
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.thumb_func
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.weak _halt16
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.globl _halt16
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_halt16:
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mov r0, pc
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bx r0
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.code 32
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.weak _halt32
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.globl _halt32
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_halt32:
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mrs r0, CPSR
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orr r0, #I_BIT | F_BIT
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msr CPSR_c, r0
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.loop: b .loop
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