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Update STM32WB implementation 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14003 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
cinsights 2020-12-29 09:13:07 +00:00
parent 9bb2f4eadf
commit 0cc119c1dd
20 changed files with 1690 additions and 1057 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
os/common/startup/ARMCMx/compilers/GCC/ld/STM32WB55xG.ld
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@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2019 Ilya Kharin
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.

2
os/common/startup/ARMCMx/devices/STM32WBxx/cmparams.h
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@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2019 Ilya Kharin
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.

35
os/hal/boards/ST_NUCLEO68_WB55RG/board.c
View File

@ -45,7 +45,6 @@ typedef struct {
uint32_t odr;
uint32_t afrl;
uint32_t afrh;
uint32_t ascr;
uint32_t lockr;
} gpio_setup_t;
@ -94,58 +93,47 @@ typedef struct {
static const gpio_config_t gpio_default_config = {
#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR,
VAL_GPIOA_LOCKR},
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_LOCKR},
#endif
#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR,
VAL_GPIOB_LOCKR},
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_LOCKR},
#endif
#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR,
VAL_GPIOC_LOCKR},
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_LOCKR},
#endif
#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR,
VAL_GPIOD_LOCKR},
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_LOCKR},
#endif
#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR,
VAL_GPIOE_LOCKR},
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_LOCKR},
#endif
#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR,
VAL_GPIOF_LOCKR},
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_LOCKR},
#endif
#if STM32_HAS_GPIOG
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR,
VAL_GPIOG_LOCKR},
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_LOCKR},
#endif
#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR,
VAL_GPIOH_LOCKR},
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_LOCKR},
#endif
#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR,
VAL_GPIOI_LOCKR},
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_LOCKR},
#endif
#if STM32_HAS_GPIOJ
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR,
VAL_GPIOJ_LOCKR},
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_LOCKR},
#endif
#if STM32_HAS_GPIOK
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR,
VAL_GPIOK_LOCKR}
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_LOCKR}
#endif
};
@ -156,7 +144,6 @@ static const gpio_config_t gpio_default_config = {
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
gpiop->OTYPER = config->otyper;
gpiop->ASCR = config->ascr;
gpiop->OSPEEDR = config->ospeedr;
gpiop->PUPDR = config->pupdr;
gpiop->ODR = config->odr;

976
os/hal/boards/ST_NUCLEO68_WB55RG/board.h
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File diff suppressed because it is too large Load Diff

1605
os/hal/boards/ST_NUCLEO68_WB55RG/cfg/board.chcfg
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File diff suppressed because it is too large Load Diff

2
os/hal/ports/STM32/LLD/EXTIv1/stm32_exti16-31-33.inc
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@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2020 Ilya Kharin
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.

2
os/hal/ports/STM32/LLD/TIMv1/stm32_tim1_16_17.inc
View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2020 Ilya Kharin
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.

2
os/hal/ports/STM32/STM32WBxx/hal_lld.c
View File

@ -189,14 +189,12 @@ void stm32_clock_init(void) {
; /* Wait until HSI16 is stable. */
#endif
#if STM32_CLOCK_HAS_HSI48
#if STM32_HSI48_ENABLED
/* HSI activation.*/
RCC->CRRCR |= RCC_CRRCR_HSI48ON;
while ((RCC->CRRCR & RCC_CRRCR_HSI48RDY) == 0)
; /* Wait until HSI48 is stable. */
#endif
#endif
#if STM32_HSE_ENABLED
#if defined(STM32_HSE_BYPASS)

24
os/hal/ports/STM32/STM32WBxx/hal_lld.h
View File

@ -302,11 +302,7 @@
#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/
#define STM32_CLK48SEL_MASK (3 << 26) /**< CLK48SEL mask. */
#if !STM32_CLOCK_HAS_HSI48
#define STM32_CLK48SEL_NOCLK (0 << 26) /**< CLK48 disabled. */
#else
#define STM32_CLK48SEL_HSI48 (0 << 26) /**< CLK48 source is HSI48. */
#endif
#define STM32_CLK48SEL_PLLSAI1 (1 << 26) /**< CLK48 source is PLLSAI1-Q. */
#define STM32_CLK48SEL_PLL (2 << 26) /**< CLK48 source is PLL-Q. */
#define STM32_CLK48SEL_MSI (3 << 26) /**< CLK48 source is MSI. */
@ -950,7 +946,6 @@
#endif /* !STM32_HSI16_ENABLED */
#if STM32_CLOCK_HAS_HSI48
#if STM32_HSI48_ENABLED
#else /* !STM32_HSI48_ENABLED */
@ -962,7 +957,6 @@
#error "HSI48 not enabled, required by STM32_CLK48SEL"
#endif
#endif /* !STM32_HSI48_ENABLED */
#endif /* STM32_CLOCK_HAS_HSI48 */
/*
* HSE related checks.
@ -1691,22 +1685,6 @@
/**
* @brief 48MHz clock frequency.
*/
#if !STM32_CLOCK_HAS_HSI48 || defined(__DOXYGEN__)
#if (STM32_CLK48SEL == STM32_CLK48SEL_NOCLK) || defined(__DOXYGEN__)
#define STM32_48CLK 0
#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1
#define STM32_48CLK (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE)
#elif STM32_CLK48SEL == STM32_CLK48SEL_PLL
#define STM32_48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
#elif STM32_CLK48SEL == STM32_CLK48SEL_MSI
#define STM32_48CLK STM32_MSICLK
#else
#error "invalid source selected for 48CLK clock"
#endif
#else /* STM32_CLOCK_HAS_HSI48 */
#if (STM32_CLK48SEL == STM32_CLK48SEL_HSI48) || defined(__DOXYGEN__)
#define STM32_48CLK STM32_HSI48CLK
#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1
@ -1719,8 +1697,6 @@
#error "invalid source selected for 48CLK clock"
#endif
#endif /* STM32_CLOCK_HAS_HSI48 */
/**
* @brief SAI1 clock frequency.
*/

3
os/hal/ports/STM32/STM32WBxx/stm32_registry.h
View File

@ -74,9 +74,6 @@
#if defined(STM32WB55xx) || defined(__DOXYGEN__)
/* Clock attributes.*/
#define STM32_CLOCK_HAS_HSI48 TRUE
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 FALSE

4
testhal/STM32/multi/ADC/Makefile
View File

@ -29,7 +29,7 @@ all:
@echo ====================================================================
@echo
@echo === Building for STM32WB55RG_Nucleo64 =============================
+@make --no-print-directory -f ./make/stm32wb55rg_nucleo64.make all
+@make --no-print-directory -f ./make/stm32wb55rg_nucleo68.make all
@echo ====================================================================
@echo
@ -47,7 +47,7 @@ clean:
@echo
+@make --no-print-directory -f ./make/stm32l4r5zi_nucleo144.make clean
@echo
+@make --no-print-directory -f ./make/stm32wb55rg_nucleo64.make clean
+@make --no-print-directory -f ./make/stm32wb55rg_nucleo68.make clean
@echo
#

4
testhal/STM32/multi/ADC/make/stm32wb55rg_nucleo64.make → testhal/STM32/multi/ADC/make/stm32wb55rg_nucleo68.make
View File

@ -91,8 +91,8 @@ MCU = cortex-m4
# Imported source files and paths.
CHIBIOS := ../../../..
CONFDIR := ./cfg/stm32wb55rg_nucleo68
BUILDDIR := ./build/st32wb55rg_nucleo68
DEPDIR := ./.dep/st32wb55rg_nucleo68
BUILDDIR := ./build/stm32wb55rg_nucleo68
DEPDIR := ./.dep/stm32wb55rg_nucleo68
# Licensing files.
include $(CHIBIOS)/os/license/license.mk

4
testhal/STM32/multi/RTC/Makefile
View File

@ -37,7 +37,7 @@ all:
@echo ====================================================================
@echo
@echo === Building for STM32WB55-Nucleo64 ===============================
+@make --no-print-directory -f ./make/stm32wb55rg_nucleo64.make all
+@make --no-print-directory -f ./make/stm32wb55rg_nucleo68.make all
@echo ====================================================================
@echo
@ -59,7 +59,7 @@ clean:
@echo
+@make --no-print-directory -f ./make/stm32g071_nucleo64.make clean
@echo
+@make --no-print-directory -f ./make/stm32wb55rg_nucleo64.make clean
+@make --no-print-directory -f ./make/stm32wb55rg_nucleo68.make clean
@echo
#

0
testhal/STM32/multi/USB_CDC/make/stm32wb55rg_nucleo64.make → testhal/STM32/multi/RTC/make/stm32wb55rg_nucleo68.make
View File

4
testhal/STM32/multi/TRNG/Makefile
View File

@ -13,7 +13,7 @@ all:
@echo ====================================================================
@echo
@echo === Building for STM32WB55RG-Nucleo64 ==============================
+@make --no-print-directory -f ./make/stm32wb55rg_nucleo64.make all
+@make --no-print-directory -f ./make/stm32wb55rg_nucleo68.make all
@echo ====================================================================
@echo
@ -23,7 +23,7 @@ clean:
@echo
+@make --no-print-directory -f ./make/stm32l4r5zi_nucleo144.make clean
@echo
+@make --no-print-directory -f ./make/stm32wb55rg_nucleo64.make clean
+@make --no-print-directory -f ./make/stm32wb55rg_nucleo68.make clean
@echo
#

6
testhal/STM32/multi/TRNG/make/stm32wb55rg_nucleo64.make → testhal/STM32/multi/TRNG/make/stm32wb55rg_nucleo68.make
View File

@ -91,8 +91,8 @@ MCU = cortex-m4
# Imported source files and paths.
CHIBIOS := ../../../..
CONFDIR := ./cfg/stm32wb55rg_nucleo68
BUILDDIR := ./build/st32wb55rg_nucleo68
DEPDIR := ./.dep/st32wb55rg_nucleo68
BUILDDIR := ./build/stm32wb55rg_nucleo68
DEPDIR := ./.dep/stm32wb55rg_nucleo68
# Licensing files.
include $(CHIBIOS)/os/license/license.mk
@ -101,7 +101,7 @@ include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32wbxx.m
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/hal/ports/STM32/STM32WBxx/platform.mk
include $(CHIBIOS)/os/hal/boards/ST_NUCLEO_WB55RG/board.mk
include $(CHIBIOS)/os/hal/boards/ST_NUCLEO68_WB55RG/board.mk
include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
# RTOS files (optional).
include $(CHIBIOS)/os/rt/rt.mk

4
testhal/STM32/multi/UART/Makefile
View File

@ -21,7 +21,7 @@ all:
@echo ====================================================================
@echo
@echo === Building for STM32WB55RG_Nucleo64 =============================
+@make --no-print-directory -f ./make/stm32wb55rg_nucleo64.make all
+@make --no-print-directory -f ./make/stm32wb55rg_nucleo68.make all
@echo ====================================================================
@echo
@ -35,7 +35,7 @@ clean:
@echo
+@make --no-print-directory -f ./make/stm32f746_discovery.make clean
@echo
+@make --no-print-directory -f ./make/stm32wb55rg_nucleo64.make clean
+@make --no-print-directory -f ./make/stm32wb55rg_nucleo68.make clean
@echo
#

4
testhal/STM32/multi/RTC/make/stm32wb55rg_nucleo64.make → testhal/STM32/multi/USB_CDC/make/stm32wb55rg_nucleo68.make
View File

@ -91,8 +91,8 @@ MCU = cortex-m4
# Imported source files and paths.
CHIBIOS := ../../../..
CONFDIR := ./cfg/stm32wb55rg_nucleo68
BUILDDIR := ./build/st32wb55rg_nucleo68
DEPDIR := ./.dep/st32wb55rg_nucleo68
BUILDDIR := ./build/stm32wb55rg_nucleo68
DEPDIR := ./.dep/stm32wb55rg_nucleo68
# Licensing files.
include $(CHIBIOS)/os/license/license.mk

35
tools/ftl/processors/boards/stm32wbxx/templates/board.c.ftl
View File

@ -62,7 +62,6 @@ typedef struct {
uint32_t odr;
uint32_t afrl;
uint32_t afrh;
uint32_t ascr;
uint32_t lockr;
} gpio_setup_t;
@ -122,58 +121,47 @@ const PALConfig pal_default_config = {
[/#if]
#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR,
VAL_GPIOA_LOCKR},
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_LOCKR},
#endif
#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR,
VAL_GPIOB_LOCKR},
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_LOCKR},
#endif
#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR,
VAL_GPIOC_LOCKR},
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_LOCKR},
#endif
#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR,
VAL_GPIOD_LOCKR},
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_LOCKR},
#endif
#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR,
VAL_GPIOE_LOCKR},
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_LOCKR},
#endif
#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR,
VAL_GPIOF_LOCKR},
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_LOCKR},
#endif
#if STM32_HAS_GPIOG
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR,
VAL_GPIOG_LOCKR},
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_LOCKR},
#endif
#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR,
VAL_GPIOH_LOCKR},
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_LOCKR},
#endif
#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR,
VAL_GPIOI_LOCKR},
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_LOCKR},
#endif
#if STM32_HAS_GPIOJ
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR,
VAL_GPIOJ_LOCKR},
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_LOCKR},
#endif
#if STM32_HAS_GPIOK
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR,
VAL_GPIOK_LOCKR}
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_LOCKR}
#endif
};
[#if doc1.board.configuration_settings.hal_version[0]?trim == "4.0.x"]
@ -188,7 +176,6 @@ const PALConfig pal_default_config = {
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
gpiop->OTYPER = config->otyper;
gpiop->ASCR = config->ascr;
gpiop->OSPEEDR = config->ospeedr;
gpiop->PUPDR = config->pupdr;
gpiop->ODR = config->odr;

29
tools/ftl/processors/boards/stm32wbxx/templates/board.h.ftl
View File

@ -172,8 +172,6 @@
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
#define PIN_ASCR_DISABLED(n) (0U << (n))
#define PIN_ASCR_ENABLED(n) (1U << (n))
#define PIN_LOCKR_DISABLED(n) (0U << (n))
#define PIN_LOCKR_ENABLED(n) (1U << (n))
@ -376,33 +374,6 @@ ${line + ")"}
${(line + " |")?right_pad(76, " ") + "\\"}
[/#if]
[/#list]
[#--
-- Generating ASCR register value.
--]
[#list port.* as pin]
[#assign names = pin.@ID[0]?string?word_list /]
[#if names?size == 0]
[#assign name = pin?node_name?upper_case /]
[#else]
[#assign name = names[0] /]
[/#if]
[#assign switch = pin.@AnalogSwitch[0] /]
[#if switch == "Disabled"]
[#assign out = "PIN_ASCR_DISABLED(" + port_name + "_" + name + ")" /]
[#else]
[#assign out = "PIN_ASCR_ENABLED(" + port_name + "_" + name + ")" /]
[/#if]
[#if pin_index == 0]
[#assign line = "#define VAL_" + port_name + "_ASCR (" + out /]
[#else]
[#assign line = " " + out /]
[/#if]
[#if pin_index < 15]
${(line + " |")?right_pad(76, " ") + "\\"}
[#else]
${line + ")"}
[/#if]
[/#list]
[#--
-- Generating LOCKR register value.
--]