mirror of https://github.com/rusefi/ChibiOS.git
Update STM32WB implementation
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14003 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
parent
9bb2f4eadf
commit
0cc119c1dd
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@ -1,5 +1,5 @@
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/*
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ChibiOS - Copyright (C) 2006..2019 Ilya Kharin
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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@ -1,5 +1,5 @@
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/*
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ChibiOS - Copyright (C) 2006..2019 Ilya Kharin
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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@ -45,7 +45,6 @@ typedef struct {
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uint32_t odr;
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uint32_t afrl;
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uint32_t afrh;
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uint32_t ascr;
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uint32_t lockr;
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} gpio_setup_t;
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@ -94,58 +93,47 @@ typedef struct {
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static const gpio_config_t gpio_default_config = {
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#if STM32_HAS_GPIOA
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{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
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VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR,
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VAL_GPIOA_LOCKR},
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VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_LOCKR},
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#endif
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#if STM32_HAS_GPIOB
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{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
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VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR,
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VAL_GPIOB_LOCKR},
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VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_LOCKR},
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#endif
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#if STM32_HAS_GPIOC
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{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
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VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR,
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VAL_GPIOC_LOCKR},
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VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_LOCKR},
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#endif
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#if STM32_HAS_GPIOD
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{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
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VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR,
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VAL_GPIOD_LOCKR},
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VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_LOCKR},
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#endif
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#if STM32_HAS_GPIOE
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{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
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VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR,
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VAL_GPIOE_LOCKR},
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VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_LOCKR},
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#endif
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#if STM32_HAS_GPIOF
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{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
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VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR,
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VAL_GPIOF_LOCKR},
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VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_LOCKR},
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#endif
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#if STM32_HAS_GPIOG
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{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
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VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR,
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VAL_GPIOG_LOCKR},
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VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_LOCKR},
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#endif
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#if STM32_HAS_GPIOH
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{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
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VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR,
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VAL_GPIOH_LOCKR},
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VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_LOCKR},
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#endif
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#if STM32_HAS_GPIOI
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{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
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VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR,
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VAL_GPIOI_LOCKR},
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VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_LOCKR},
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#endif
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#if STM32_HAS_GPIOJ
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{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
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VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR,
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VAL_GPIOJ_LOCKR},
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VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_LOCKR},
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#endif
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#if STM32_HAS_GPIOK
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{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
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VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR,
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VAL_GPIOK_LOCKR}
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VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_LOCKR}
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#endif
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};
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@ -156,7 +144,6 @@ static const gpio_config_t gpio_default_config = {
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static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
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gpiop->OTYPER = config->otyper;
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gpiop->ASCR = config->ascr;
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gpiop->OSPEEDR = config->ospeedr;
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gpiop->PUPDR = config->pupdr;
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gpiop->ODR = config->odr;
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -1,5 +1,5 @@
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/*
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ChibiOS - Copyright (C) 2006..2020 Ilya Kharin
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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@ -1,5 +1,5 @@
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/*
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ChibiOS - Copyright (C) 2006..2020 Ilya Kharin
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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@ -189,14 +189,12 @@ void stm32_clock_init(void) {
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; /* Wait until HSI16 is stable. */
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#endif
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#if STM32_CLOCK_HAS_HSI48
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#if STM32_HSI48_ENABLED
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/* HSI activation.*/
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RCC->CRRCR |= RCC_CRRCR_HSI48ON;
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while ((RCC->CRRCR & RCC_CRRCR_HSI48RDY) == 0)
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; /* Wait until HSI48 is stable. */
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#endif
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#endif
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#if STM32_HSE_ENABLED
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#if defined(STM32_HSE_BYPASS)
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@ -302,11 +302,7 @@
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#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/
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#define STM32_CLK48SEL_MASK (3 << 26) /**< CLK48SEL mask. */
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#if !STM32_CLOCK_HAS_HSI48
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#define STM32_CLK48SEL_NOCLK (0 << 26) /**< CLK48 disabled. */
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#else
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#define STM32_CLK48SEL_HSI48 (0 << 26) /**< CLK48 source is HSI48. */
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#endif
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#define STM32_CLK48SEL_PLLSAI1 (1 << 26) /**< CLK48 source is PLLSAI1-Q. */
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#define STM32_CLK48SEL_PLL (2 << 26) /**< CLK48 source is PLL-Q. */
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#define STM32_CLK48SEL_MSI (3 << 26) /**< CLK48 source is MSI. */
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#endif /* !STM32_HSI16_ENABLED */
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#if STM32_CLOCK_HAS_HSI48
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#if STM32_HSI48_ENABLED
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#else /* !STM32_HSI48_ENABLED */
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#error "HSI48 not enabled, required by STM32_CLK48SEL"
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#endif
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#endif /* !STM32_HSI48_ENABLED */
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#endif /* STM32_CLOCK_HAS_HSI48 */
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/*
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* HSE related checks.
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@ -1691,22 +1685,6 @@
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/**
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* @brief 48MHz clock frequency.
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*/
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#if !STM32_CLOCK_HAS_HSI48 || defined(__DOXYGEN__)
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#if (STM32_CLK48SEL == STM32_CLK48SEL_NOCLK) || defined(__DOXYGEN__)
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#define STM32_48CLK 0
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#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1
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#define STM32_48CLK (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE)
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#elif STM32_CLK48SEL == STM32_CLK48SEL_PLL
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#define STM32_48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
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#elif STM32_CLK48SEL == STM32_CLK48SEL_MSI
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#define STM32_48CLK STM32_MSICLK
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#else
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#error "invalid source selected for 48CLK clock"
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#endif
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#else /* STM32_CLOCK_HAS_HSI48 */
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#if (STM32_CLK48SEL == STM32_CLK48SEL_HSI48) || defined(__DOXYGEN__)
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#define STM32_48CLK STM32_HSI48CLK
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#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1
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#error "invalid source selected for 48CLK clock"
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#endif
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#endif /* STM32_CLOCK_HAS_HSI48 */
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/**
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* @brief SAI1 clock frequency.
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*/
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@ -74,9 +74,6 @@
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#if defined(STM32WB55xx) || defined(__DOXYGEN__)
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/* Clock attributes.*/
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#define STM32_CLOCK_HAS_HSI48 TRUE
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 FALSE
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@ -29,7 +29,7 @@ all:
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@echo ====================================================================
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@echo
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@echo === Building for STM32WB55RG_Nucleo64 =============================
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+@make --no-print-directory -f ./make/stm32wb55rg_nucleo64.make all
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+@make --no-print-directory -f ./make/stm32wb55rg_nucleo68.make all
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@echo ====================================================================
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@echo
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@echo
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+@make --no-print-directory -f ./make/stm32l4r5zi_nucleo144.make clean
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@echo
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+@make --no-print-directory -f ./make/stm32wb55rg_nucleo64.make clean
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+@make --no-print-directory -f ./make/stm32wb55rg_nucleo68.make clean
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@echo
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#
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@ -91,8 +91,8 @@ MCU = cortex-m4
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# Imported source files and paths.
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CHIBIOS := ../../../..
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CONFDIR := ./cfg/stm32wb55rg_nucleo68
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BUILDDIR := ./build/st32wb55rg_nucleo68
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DEPDIR := ./.dep/st32wb55rg_nucleo68
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BUILDDIR := ./build/stm32wb55rg_nucleo68
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DEPDIR := ./.dep/stm32wb55rg_nucleo68
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# Licensing files.
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include $(CHIBIOS)/os/license/license.mk
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@ -37,7 +37,7 @@ all:
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@echo ====================================================================
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@echo
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@echo === Building for STM32WB55-Nucleo64 ===============================
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+@make --no-print-directory -f ./make/stm32wb55rg_nucleo64.make all
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+@make --no-print-directory -f ./make/stm32wb55rg_nucleo68.make all
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@echo ====================================================================
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@echo
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@echo
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+@make --no-print-directory -f ./make/stm32g071_nucleo64.make clean
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@echo
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+@make --no-print-directory -f ./make/stm32wb55rg_nucleo64.make clean
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+@make --no-print-directory -f ./make/stm32wb55rg_nucleo68.make clean
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@echo
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#
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@ -13,7 +13,7 @@ all:
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@echo ====================================================================
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@echo
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@echo === Building for STM32WB55RG-Nucleo64 ==============================
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+@make --no-print-directory -f ./make/stm32wb55rg_nucleo64.make all
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+@make --no-print-directory -f ./make/stm32wb55rg_nucleo68.make all
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@echo ====================================================================
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@echo
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@ -23,7 +23,7 @@ clean:
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@echo
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+@make --no-print-directory -f ./make/stm32l4r5zi_nucleo144.make clean
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@echo
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+@make --no-print-directory -f ./make/stm32wb55rg_nucleo64.make clean
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+@make --no-print-directory -f ./make/stm32wb55rg_nucleo68.make clean
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@echo
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#
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@ -91,8 +91,8 @@ MCU = cortex-m4
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# Imported source files and paths.
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CHIBIOS := ../../../..
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CONFDIR := ./cfg/stm32wb55rg_nucleo68
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BUILDDIR := ./build/st32wb55rg_nucleo68
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DEPDIR := ./.dep/st32wb55rg_nucleo68
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BUILDDIR := ./build/stm32wb55rg_nucleo68
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DEPDIR := ./.dep/stm32wb55rg_nucleo68
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# Licensing files.
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include $(CHIBIOS)/os/license/license.mk
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@ -101,7 +101,7 @@ include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32wbxx.m
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# HAL-OSAL files (optional).
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include $(CHIBIOS)/os/hal/hal.mk
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include $(CHIBIOS)/os/hal/ports/STM32/STM32WBxx/platform.mk
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include $(CHIBIOS)/os/hal/boards/ST_NUCLEO_WB55RG/board.mk
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include $(CHIBIOS)/os/hal/boards/ST_NUCLEO68_WB55RG/board.mk
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include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
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# RTOS files (optional).
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include $(CHIBIOS)/os/rt/rt.mk
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@ -21,7 +21,7 @@ all:
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@echo ====================================================================
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@echo
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@echo === Building for STM32WB55RG_Nucleo64 =============================
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+@make --no-print-directory -f ./make/stm32wb55rg_nucleo64.make all
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+@make --no-print-directory -f ./make/stm32wb55rg_nucleo68.make all
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@echo ====================================================================
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@echo
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@ -35,7 +35,7 @@ clean:
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@echo
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+@make --no-print-directory -f ./make/stm32f746_discovery.make clean
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@echo
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+@make --no-print-directory -f ./make/stm32wb55rg_nucleo64.make clean
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+@make --no-print-directory -f ./make/stm32wb55rg_nucleo68.make clean
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@echo
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#
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@ -91,8 +91,8 @@ MCU = cortex-m4
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# Imported source files and paths.
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CHIBIOS := ../../../..
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CONFDIR := ./cfg/stm32wb55rg_nucleo68
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BUILDDIR := ./build/st32wb55rg_nucleo68
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DEPDIR := ./.dep/st32wb55rg_nucleo68
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BUILDDIR := ./build/stm32wb55rg_nucleo68
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DEPDIR := ./.dep/stm32wb55rg_nucleo68
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# Licensing files.
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include $(CHIBIOS)/os/license/license.mk
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@ -62,7 +62,6 @@ typedef struct {
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uint32_t odr;
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uint32_t afrl;
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uint32_t afrh;
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uint32_t ascr;
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uint32_t lockr;
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} gpio_setup_t;
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@ -122,58 +121,47 @@ const PALConfig pal_default_config = {
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[/#if]
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#if STM32_HAS_GPIOA
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{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
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VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR,
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VAL_GPIOA_LOCKR},
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VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_LOCKR},
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#endif
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#if STM32_HAS_GPIOB
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{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
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VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR,
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VAL_GPIOB_LOCKR},
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VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_LOCKR},
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#endif
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#if STM32_HAS_GPIOC
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{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
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VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR,
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VAL_GPIOC_LOCKR},
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VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_LOCKR},
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#endif
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#if STM32_HAS_GPIOD
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{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
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VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR,
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VAL_GPIOD_LOCKR},
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VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_LOCKR},
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#endif
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#if STM32_HAS_GPIOE
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{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
|
||||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR,
|
||||
VAL_GPIOE_LOCKR},
|
||||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
|
||||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR,
|
||||
VAL_GPIOF_LOCKR},
|
||||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
|
||||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR,
|
||||
VAL_GPIOG_LOCKR},
|
||||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
|
||||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR,
|
||||
VAL_GPIOH_LOCKR},
|
||||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
|
||||
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR,
|
||||
VAL_GPIOI_LOCKR},
|
||||
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
|
||||
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR,
|
||||
VAL_GPIOJ_LOCKR},
|
||||
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
|
||||
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR,
|
||||
VAL_GPIOK_LOCKR}
|
||||
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_LOCKR}
|
||||
#endif
|
||||
};
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "4.0.x"]
|
||||
|
@ -188,7 +176,6 @@ const PALConfig pal_default_config = {
|
|||
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
|
||||
|
||||
gpiop->OTYPER = config->otyper;
|
||||
gpiop->ASCR = config->ascr;
|
||||
gpiop->OSPEEDR = config->ospeedr;
|
||||
gpiop->PUPDR = config->pupdr;
|
||||
gpiop->ODR = config->odr;
|
||||
|
|
|
@ -172,8 +172,6 @@
|
|||
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
|
||||
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
|
||||
#define PIN_ASCR_DISABLED(n) (0U << (n))
|
||||
#define PIN_ASCR_ENABLED(n) (1U << (n))
|
||||
#define PIN_LOCKR_DISABLED(n) (0U << (n))
|
||||
#define PIN_LOCKR_ENABLED(n) (1U << (n))
|
||||
|
||||
|
@ -376,33 +374,6 @@ ${line + ")"}
|
|||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating ASCR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign switch = pin.@AnalogSwitch[0] /]
|
||||
[#if switch == "Disabled"]
|
||||
[#assign out = "PIN_ASCR_DISABLED(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_ASCR_ENABLED(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_ASCR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating LOCKR register value.
|
||||
--]
|
||||
|
|
Loading…
Reference in New Issue