diff --git a/demos/STM32/RT-STM32L432KC-NUCLEO32/mcuconf.h b/demos/STM32/RT-STM32L432KC-NUCLEO32/mcuconf.h
index dc9259869..6803c8b24 100644
--- a/demos/STM32/RT-STM32L432KC-NUCLEO32/mcuconf.h
+++ b/demos/STM32/RT-STM32L432KC-NUCLEO32/mcuconf.h
@@ -89,7 +89,7 @@
 #define STM32_CLK48SEL                      STM32_CLK48SEL_PLLSAI1
 #define STM32_ADCSEL                        STM32_ADCSEL_SYSCLK
 #define STM32_SWPMI1SEL                     STM32_SWPMI1SEL_PCLK1
-#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK1
+#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK2
 #define STM32_RTCSEL                        STM32_RTCSEL_LSI
 
 /*
diff --git a/demos/STM32/RT-STM32L476-DISCOVERY/cfg/mcuconf.h b/demos/STM32/RT-STM32L476-DISCOVERY/cfg/mcuconf.h
index 81c061785..afc2ccee7 100644
--- a/demos/STM32/RT-STM32L476-DISCOVERY/cfg/mcuconf.h
+++ b/demos/STM32/RT-STM32L476-DISCOVERY/cfg/mcuconf.h
@@ -88,7 +88,7 @@
 #define STM32_CLK48SEL                      STM32_CLK48SEL_PLLSAI1
 #define STM32_ADCSEL                        STM32_ADCSEL_SYSCLK
 #define STM32_SWPMI1SEL                     STM32_SWPMI1SEL_PCLK1
-#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK1
+#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK2
 #define STM32_RTCSEL                        STM32_RTCSEL_LSI
 
 /*
diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO64/mcuconf.h b/demos/STM32/RT-STM32L476RG-NUCLEO64/mcuconf.h
index 85f8cf75d..b41126580 100644
--- a/demos/STM32/RT-STM32L476RG-NUCLEO64/mcuconf.h
+++ b/demos/STM32/RT-STM32L476RG-NUCLEO64/mcuconf.h
@@ -88,7 +88,7 @@
 #define STM32_CLK48SEL                      STM32_CLK48SEL_PLLSAI1
 #define STM32_ADCSEL                        STM32_ADCSEL_SYSCLK
 #define STM32_SWPMI1SEL                     STM32_SWPMI1SEL_PCLK1
-#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK1
+#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK2
 #define STM32_RTCSEL                        STM32_RTCSEL_LSI
 
 /*
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/os/hal/ports/STM32/STM32L4xx/hal_lld.c
index a144142bb..fa02600af 100644
--- a/os/hal/ports/STM32/STM32L4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.c
@@ -92,6 +92,9 @@ static void hal_lld_backup_domain_init(void) {
     RCC->BDCR |= RCC_BDCR_RTCEN;
   }
 #endif /* HAL_USE_RTC */
+
+  /* Low speed output mode.*/
+  RCC->BDCR |= STM32_LSCOSEL;
 }
 
 /*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.h b/os/hal/ports/STM32/STM32L4xx/hal_lld.h
index 3722fd0ee..c792a9313 100644
--- a/os/hal/ports/STM32/STM32L4xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.h
@@ -291,7 +291,7 @@
 #define STM32_SWPMI1SEL_HSI16   (1 << 30)   /**< SWPMI1 source is HSI16.    */
 
 #define STM32_DFSDMSEL_MASK     (1 << 31)   /**< DFSDMSEL mask.             */
-#define STM32_DFSDMSEL_PCLK1    (0 << 31)   /**< DFSDM source is PCLK1.     */
+#define STM32_DFSDMSEL_PCLK2    (0 << 31)   /**< DFSDM source is PCLK2.     */
 #define STM32_DFSDMSEL_SYSCLK   (1 << 31)   /**< DFSDM source is SYSCLK.    */
 /** @} */
 
@@ -2130,8 +2130,8 @@
 /**
  * @brief   DFSDM clock frequency.
  */
-#if (STM32_DFSDMSEL == STM32_DFSDMSEL_PCLK1) || defined(__DOXYGEN__)
-#define STM32_DFSDMCLK              STM32_PCLK1
+#if (STM32_DFSDMSEL == STM32_DFSDMSEL_PCLK2) || defined(__DOXYGEN__)
+#define STM32_DFSDMCLK              STM32_PCLK2
 #elif STM32_DFSDMSEL == STM32_DFSDMSEL_SYSCLK
 #define STM32_DFSDMCLK              STM32_SYSCLK
 #else
diff --git a/readme.txt b/readme.txt
index 19328ead0..ae0a3b812 100644
--- a/readme.txt
+++ b/readme.txt
@@ -141,6 +141,10 @@
 - EX:  Updated LIS302DL to 1.1.0 (backported to 18.2.1).
 - EX:  Updated LPS25H to 1.1.0 (backported to 18.2.1).
 - EX:  Updated LSM303DLHC to 1.1.0 (backported to 18.2.1).
+- HAL: Fixed option STM32_LSCOSEL not written in STM32L4 HAL (bug #970)
+       (backported to 18.2.2 and 17.6.5).
+- HAL: Fixed invalid DFSDM1SEL option in STM32L4 HAL (bug #969)(backported
+       to 18.2.2 and 17.6.5).
 - HAL: Fixed incorrect checks on STM32_SAI2SEL option in STM32L4 HAL
        (bug #968)(backported to 18.2.2 and 17.6.5).
 - HAL: Fixed incorrect handling of PDIV dividers in STM32L4 HAL (bug #967)
diff --git a/testex/STM32/STM32L4xx/QSPI-N25Q128/mcuconf.h b/testex/STM32/STM32L4xx/QSPI-N25Q128/mcuconf.h
index f5948bff5..e44f48ccb 100644
--- a/testex/STM32/STM32L4xx/QSPI-N25Q128/mcuconf.h
+++ b/testex/STM32/STM32L4xx/QSPI-N25Q128/mcuconf.h
@@ -88,7 +88,7 @@
 #define STM32_CLK48SEL                      STM32_CLK48SEL_PLLSAI1
 #define STM32_ADCSEL                        STM32_ADCSEL_SYSCLK
 #define STM32_SWPMI1SEL                     STM32_SWPMI1SEL_PCLK1
-#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK1
+#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK2
 #define STM32_RTCSEL                        STM32_RTCSEL_LSI
 
 /*
diff --git a/testhal/STM32/STM32L4xx/ADC/mcuconf.h b/testhal/STM32/STM32L4xx/ADC/mcuconf.h
index 5c5e0a61b..4cda1fe8f 100644
--- a/testhal/STM32/STM32L4xx/ADC/mcuconf.h
+++ b/testhal/STM32/STM32L4xx/ADC/mcuconf.h
@@ -88,7 +88,7 @@
 #define STM32_CLK48SEL                      STM32_CLK48SEL_PLLSAI1
 #define STM32_ADCSEL                        STM32_ADCSEL_SYSCLK
 #define STM32_SWPMI1SEL                     STM32_SWPMI1SEL_PCLK1
-#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK1
+#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK2
 #define STM32_RTCSEL                        STM32_RTCSEL_LSI
 
 /*
diff --git a/testhal/STM32/STM32L4xx/CAN/mcuconf.h b/testhal/STM32/STM32L4xx/CAN/mcuconf.h
index db54aadfd..0921502d2 100644
--- a/testhal/STM32/STM32L4xx/CAN/mcuconf.h
+++ b/testhal/STM32/STM32L4xx/CAN/mcuconf.h
@@ -88,7 +88,7 @@
 #define STM32_CLK48SEL                      STM32_CLK48SEL_PLLSAI1
 #define STM32_ADCSEL                        STM32_ADCSEL_SYSCLK
 #define STM32_SWPMI1SEL                     STM32_SWPMI1SEL_PCLK1
-#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK1
+#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK2
 #define STM32_RTCSEL                        STM32_RTCSEL_LSI
 
 /*
diff --git a/testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h b/testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h
index b00f1446e..4f850d82d 100644
--- a/testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h
+++ b/testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h
@@ -88,7 +88,7 @@
 #define STM32_CLK48SEL                      STM32_CLK48SEL_PLLSAI1
 #define STM32_ADCSEL                        STM32_ADCSEL_SYSCLK
 #define STM32_SWPMI1SEL                     STM32_SWPMI1SEL_PCLK1
-#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK1
+#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK2
 #define STM32_RTCSEL                        STM32_RTCSEL_LSI
 
 /*
diff --git a/testhal/STM32/STM32L4xx/IRQ_STORM/mcuconf.h b/testhal/STM32/STM32L4xx/IRQ_STORM/mcuconf.h
index 1119ce8ca..185b900f9 100644
--- a/testhal/STM32/STM32L4xx/IRQ_STORM/mcuconf.h
+++ b/testhal/STM32/STM32L4xx/IRQ_STORM/mcuconf.h
@@ -88,7 +88,7 @@
 #define STM32_CLK48SEL                      STM32_CLK48SEL_PLLSAI1
 #define STM32_ADCSEL                        STM32_ADCSEL_SYSCLK
 #define STM32_SWPMI1SEL                     STM32_SWPMI1SEL_PCLK1
-#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK1
+#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK2
 #define STM32_RTCSEL                        STM32_RTCSEL_LSI
 
 /*
diff --git a/testhal/STM32/multi/PAL/cfg/stm32l476_discovery/mcuconf.h b/testhal/STM32/multi/PAL/cfg/stm32l476_discovery/mcuconf.h
index c632cd5f2..8ad311d58 100644
--- a/testhal/STM32/multi/PAL/cfg/stm32l476_discovery/mcuconf.h
+++ b/testhal/STM32/multi/PAL/cfg/stm32l476_discovery/mcuconf.h
@@ -88,7 +88,7 @@
 #define STM32_CLK48SEL                      STM32_CLK48SEL_MSI
 #define STM32_ADCSEL                        STM32_ADCSEL_SYSCLK
 #define STM32_SWPMI1SEL                     STM32_SWPMI1SEL_PCLK1
-#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK1
+#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK2
 #define STM32_RTCSEL                        STM32_RTCSEL_LSI
 
 /*
diff --git a/testhal/STM32/multi/QSPI-MFS/cfg/stm32l476_discovery/mcuconf.h b/testhal/STM32/multi/QSPI-MFS/cfg/stm32l476_discovery/mcuconf.h
index 8734a7042..af8d116af 100644
--- a/testhal/STM32/multi/QSPI-MFS/cfg/stm32l476_discovery/mcuconf.h
+++ b/testhal/STM32/multi/QSPI-MFS/cfg/stm32l476_discovery/mcuconf.h
@@ -88,7 +88,7 @@
 #define STM32_CLK48SEL                      STM32_CLK48SEL_MSI
 #define STM32_ADCSEL                        STM32_ADCSEL_SYSCLK
 #define STM32_SWPMI1SEL                     STM32_SWPMI1SEL_PCLK1
-#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK1
+#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK2
 #define STM32_RTCSEL                        STM32_RTCSEL_LSI
 
 /*
diff --git a/testhal/STM32/multi/USB_CDC/cfg/stm32l476_discovery/mcuconf.h b/testhal/STM32/multi/USB_CDC/cfg/stm32l476_discovery/mcuconf.h
index 192d9f6ed..793e44186 100644
--- a/testhal/STM32/multi/USB_CDC/cfg/stm32l476_discovery/mcuconf.h
+++ b/testhal/STM32/multi/USB_CDC/cfg/stm32l476_discovery/mcuconf.h
@@ -88,7 +88,7 @@
 #define STM32_CLK48SEL                      STM32_CLK48SEL_MSI
 #define STM32_ADCSEL                        STM32_ADCSEL_SYSCLK
 #define STM32_SWPMI1SEL                     STM32_SWPMI1SEL_PCLK1
-#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK1
+#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK2
 #define STM32_RTCSEL                        STM32_RTCSEL_LSI
 
 /*