mirror of https://github.com/rusefi/ChibiOS.git
G4 configurations update.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13323 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
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@ -40,7 +40,9 @@
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*/
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_NO_INIT FALSE
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#define STM32_VOS STM32_VOS_RANGE1
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#define STM32_VOS STM32_VOS_RANGE1
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#define STM32_PWR_CR2 (STM32_PLS_LEV0 | STM32_PVDE_DISABLED)
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#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
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#define STM32_PWR_CR3 (PWR_CR3_EIWF)
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#define STM32_PWR_CR4 (0U)
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#define STM32_HSI16_ENABLED TRUE
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#define STM32_HSI16_ENABLED TRUE
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#define STM32_HSI48_ENABLED TRUE
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#define STM32_HSI48_ENABLED TRUE
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#define STM32_HSE_ENABLED TRUE
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#define STM32_HSE_ENABLED TRUE
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/*
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/*
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* ADC driver system settings.
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* ADC driver system settings.
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*/
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*/
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#define STM32_ADC_DUAL_MODE FALSE
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#define STM32_ADC_COMPACT_SAMPLES FALSE
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_USE_ADC2 FALSE
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#define STM32_ADC_USE_ADC3 FALSE
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#define STM32_ADC_USE_ADC4 FALSE
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_ADC2_DMA_PRIORITY 2
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#define STM32_ADC_ADC3_DMA_PRIORITY 2
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#define STM32_ADC_ADC4_DMA_PRIORITY 2
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#define STM32_ADC_ADC12_IRQ_PRIORITY 5
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#define STM32_ADC_ADC345_IRQ_PRIORITY 5
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
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#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
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#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
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#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
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#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
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#define STM32_ADC_ADC345_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
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/*
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/*
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* CAN driver system settings.
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* CAN driver system settings.
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@ -42,7 +42,9 @@
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*/
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_NO_INIT FALSE
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#define STM32_VOS STM32_VOS_RANGE1
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#define STM32_VOS STM32_VOS_RANGE1
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#define STM32_PWR_CR2 (STM32_PLS_LEV0 | STM32_PVDE_DISABLED)
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#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0)
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#define STM32_PWR_CR3 (PWR_CR3_EIWF)
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#define STM32_PWR_CR4 (0U)
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#define STM32_HSI16_ENABLED TRUE
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#define STM32_HSI16_ENABLED TRUE
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#define STM32_HSI48_ENABLED TRUE
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#define STM32_HSI48_ENABLED TRUE
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#define STM32_HSE_ENABLED TRUE
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#define STM32_HSE_ENABLED TRUE
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*/
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*/
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#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
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#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
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#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"}
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#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"}
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#define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(STM32_PLS_LEV0 | STM32_PVDE_DISABLED)"}
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#define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(PWR_CR2_PLS_LEV0)"}
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#define STM32_PWR_CR3 ${doc.STM32_PWR_CR3!"(PWR_CR3_EIWF)"}
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#define STM32_PWR_CR4 ${doc.STM32_PWR_CR4!"(0U)"}
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#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"TRUE"}
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#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"TRUE"}
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#define STM32_HSI48_ENABLED ${doc.STM32_HSI48_ENABLED!"TRUE"}
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#define STM32_HSI48_ENABLED ${doc.STM32_HSI48_ENABLED!"TRUE"}
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#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"TRUE"}
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#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"TRUE"}
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